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535.146.02

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This commit is contained in:
Bernhard Stoeckner
2023-12-07 15:09:52 +01:00
parent e573018659
commit 7165299dee
77 changed files with 965 additions and 362 deletions
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8
src/common/displayport/src/dp_connectorimpl.cpp
View File

@@ -1360,7 +1360,7 @@ bool ConnectorImpl::compoundQueryAttach(Group * target,
if (dev->pconCaps.maxHdmiLinkBandwidthGbps != 0)
{
NvU64 requiredBW = (NvU64)(modesetParams.modesetInfo.pixelClockHz * modesetParams.modesetInfo.depth);
NvU64 availableBw = (NvU64)(dev->pconCaps.maxHdmiLinkBandwidthGbps * 1000000000);
NvU64 availableBw = (NvU64)(dev->pconCaps.maxHdmiLinkBandwidthGbps * (NvU64)1000000000);
if (requiredBW > availableBw)
{
compoundQueryResult = false;
@@ -1375,10 +1375,10 @@ bool ConnectorImpl::compoundQueryAttach(Group * target,
else if (dev->pconCaps.maxTmdsClkRate != 0)
{
NvU64 maxTmdsClkRateU64 = (NvU64)(dev->pconCaps.maxTmdsClkRate);
NvU64 requireBw = (NvU64)(modesetParams.modesetInfo.pixelClockHz * modesetParams.modesetInfo.depth);
NvU64 requiredBw = (NvU64)(modesetParams.modesetInfo.pixelClockHz * modesetParams.modesetInfo.depth);
if (modesetParams.colorFormat == dpColorFormat_YCbCr420)
{
if (maxTmdsClkRateU64 < ((requireBw/24)/2))
if (maxTmdsClkRateU64 < ((requiredBw/24)/2))
{
compoundQueryResult = false;
return false;
@@ -1386,7 +1386,7 @@ bool ConnectorImpl::compoundQueryAttach(Group * target,
}
else
{
if (maxTmdsClkRateU64 < (requireBw/24))
if (maxTmdsClkRateU64 < (requiredBw/24))
{
compoundQueryResult = false;
return false;

20
src/common/inc/nvBldVer.h
View File

@@ -36,25 +36,25 @@
// and then checked back in. You cannot make changes to these sections without
// corresponding changes to the buildmeister script
#ifndef NV_BUILD_BRANCH
#define NV_BUILD_BRANCH r537_68
#define NV_BUILD_BRANCH r537_94
#endif
#ifndef NV_PUBLIC_BRANCH
#define NV_PUBLIC_BRANCH r537_68
#define NV_PUBLIC_BRANCH r537_94
#endif
#if defined(NV_LINUX) || defined(NV_BSD) || defined(NV_SUNOS)
#define NV_BUILD_BRANCH_VERSION "rel/gpu_drv/r535/r537_68-335"
#define NV_BUILD_CHANGELIST_NUM (33430121)
#define NV_BUILD_BRANCH_VERSION "rel/gpu_drv/r535/r537_94-386"
#define NV_BUILD_CHANGELIST_NUM (33606179)
#define NV_BUILD_TYPE "Official"
#define NV_BUILD_NAME "rel/gpu_drv/r535/r537_68-335"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (33430121)
#define NV_BUILD_NAME "rel/gpu_drv/r535/r537_94-386"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (33606179)
#else /* Windows builds */
#define NV_BUILD_BRANCH_VERSION "r537_68-2"
#define NV_BUILD_CHANGELIST_NUM (33425293)
#define NV_BUILD_BRANCH_VERSION "r537_94-2"
#define NV_BUILD_CHANGELIST_NUM (33602158)
#define NV_BUILD_TYPE "Official"
#define NV_BUILD_NAME "537.70"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (33425293)
#define NV_BUILD_NAME "537.99"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (33602158)
#define NV_BUILD_BRANCH_BASE_VERSION R535
#endif
// End buildmeister python edited section

2
src/common/inc/nvUnixVersion.h
View File

@@ -4,7 +4,7 @@
#if defined(NV_LINUX) || defined(NV_BSD) || defined(NV_SUNOS) || defined(NV_VMWARE) || defined(NV_QNX) || defined(NV_INTEGRITY) || \
(defined(RMCFG_FEATURE_PLATFORM_GSP) && RMCFG_FEATURE_PLATFORM_GSP == 1)
#define NV_VERSION_STRING "535.129.03"
#define NV_VERSION_STRING "535.146.02"
#else

178
src/common/inc/nveGPUConfig.h
View File

@@ -39,48 +39,63 @@ extern "C" {
#endif //NV_UNIX
#endif //!__cplusplus
// Surprise removal capable TB3 and TB2 BUS Device ID
#define BUS_DEVICE_ID_TB3_ALPINE_RIDGE_01 0x1578
#define BUS_DEVICE_ID_TB3_02 0x1576
#define BUS_DEVICE_ID_TB3_03 0x15C0
#define BUS_DEVICE_ID_TB3_04 0x15D3
#define BUS_DEVICE_ID_TB3_05 0x15DA
#define BUS_DEVICE_ID_TB3_06 0x15EA
#define BUS_DEVICE_ID_TB3_07 0x15E7
#define BUS_DEVICE_ID_TB3_08 0x15EF
#define BUS_DEVICE_ID_TB3_09 0x1133
#define BUS_DEVICE_ID_TB3_10 0x1136
#define PARENT_EGPU_BUS_DEVICE_43 0x57A4
#define PARENT_EGPU_BUS_DEVICE_42 0x5786
#define PARENT_EGPU_BUS_DEVICE_41 0x1578
#define PARENT_EGPU_BUS_DEVICE_40 0x1576
#define PARENT_EGPU_BUS_DEVICE_39 0x15C0
#define PARENT_EGPU_BUS_DEVICE_38 0x15D3
#define PARENT_EGPU_BUS_DEVICE_37 0x15DA
#define PARENT_EGPU_BUS_DEVICE_36 0x15EA
#define PARENT_EGPU_BUS_DEVICE_35 0x15E7
#define PARENT_EGPU_BUS_DEVICE_34 0x15EF
#define PARENT_EGPU_BUS_DEVICE_33 0x1133
#define PARENT_EGPU_BUS_DEVICE_32 0x1136
// IceLake-U TB3 device ids. Below TB3 would be integrated to CPU.
#define BUS_DEVICE_ID_ICELAKE_TB3_01 0x8A1D
#define BUS_DEVICE_ID_ICELAKE_TB3_02 0x8A1F
#define BUS_DEVICE_ID_ICELAKE_TB3_03 0x8A21
#define BUS_DEVICE_ID_ICELAKE_TB3_04 0x8A23
#define BUS_DEVICE_ID_ICELAKE_TB3_05 0x8A0D
#define BUS_DEVICE_ID_ICELAKE_TB3_06 0x8A17
#define PARENT_EGPU_BUS_DEVICE_31 0x8A1D
#define PARENT_EGPU_BUS_DEVICE_30 0x8A1F
#define PARENT_EGPU_BUS_DEVICE_29 0x8A21
#define PARENT_EGPU_BUS_DEVICE_28 0x8A23
#define PARENT_EGPU_BUS_DEVICE_27 0x8A0D
#define PARENT_EGPU_BUS_DEVICE_26 0x8A17
// TigerLake Thunderbolt device ids.
#define BUS_DEVICE_ID_TIGERLAKE_TB3_01 0x9A1B
#define BUS_DEVICE_ID_TIGERLAKE_TB3_02 0x9A1D
#define BUS_DEVICE_ID_TIGERLAKE_TB3_03 0x9A1F
#define BUS_DEVICE_ID_TIGERLAKE_TB3_04 0x9A21
#define BUS_DEVICE_ID_TIGERLAKE_TB3_05 0x9A23
#define BUS_DEVICE_ID_TIGERLAKE_TB3_06 0x9A25
#define BUS_DEVICE_ID_TIGERLAKE_TB3_07 0x9A27
#define BUS_DEVICE_ID_TIGERLAKE_TB3_08 0x9A29
#define BUS_DEVICE_ID_TIGERLAKE_TB3_09 0x9A2B
#define BUS_DEVICE_ID_TIGERLAKE_TB3_10 0x9A2D
//#define BUS_DEVICE_ID_TB2_FALCON_RIDGE_DSL5520_01 0X156C // obsolete
#define BUS_DEVICE_ID_TB2_FALCON_RIDGE_DSL5520_02 0X156D
#define BUS_DEVICE_ID_TB2_03 0x157E
#define BUS_DEVICE_ID_TB2_04 0x156B
#define BUS_DEVICE_ID_TB2_05 0x1567
#define BUS_DEVICE_ID_TB2_06 0x1569
//#define BUS_DEVICE_ID_TB2_07 0x1548 // obsolete
#define BUS_DEVICE_ID_TB2_08 0x151B
#define BUS_DEVICE_ID_TB2_09 0x1549
#define BUS_DEVICE_ID_TB2_10 0x1513
#define PARENT_EGPU_BUS_DEVICE_25 0x9A1B
#define PARENT_EGPU_BUS_DEVICE_24 0x9A1D
#define PARENT_EGPU_BUS_DEVICE_23 0x9A1F
#define PARENT_EGPU_BUS_DEVICE_22 0x9A21
#define PARENT_EGPU_BUS_DEVICE_21 0x9A23
#define PARENT_EGPU_BUS_DEVICE_20 0x9A25
#define PARENT_EGPU_BUS_DEVICE_19 0x9A27
#define PARENT_EGPU_BUS_DEVICE_18 0x9A29
#define PARENT_EGPU_BUS_DEVICE_17 0x9A2B
#define PARENT_EGPU_BUS_DEVICE_16 0x9A2D
#define PARENT_EGPU_BUS_DEVICE_15 0x7EB2
#define PARENT_EGPU_BUS_DEVICE_14 0x7EC2
#define PARENT_EGPU_BUS_DEVICE_13 0x7EC3
#define PARENT_EGPU_BUS_DEVICE_12 0x7EB4
#define PARENT_EGPU_BUS_DEVICE_11 0x7EC4
#define PARENT_EGPU_BUS_DEVICE_10 0x7EB5
#define PARENT_EGPU_BUS_DEVICE_09 0x7EC5
#define PARENT_EGPU_BUS_DEVICE_08 0x7EC6
#define PARENT_EGPU_BUS_DEVICE_07 0x7EC7
#define PARENT_EGPU_BUS_DEVICE_06 0xA73E
#define PARENT_EGPU_BUS_DEVICE_05 0xA76D
#define PARENT_EGPU_BUS_DEVICE_04 0x466E
#define PARENT_EGPU_BUS_DEVICE_03 0x463F
#define PARENT_EGPU_BUS_DEVICE_02 0x462F
#define PARENT_EGPU_BUS_DEVICE_01 0x461F
#define PARENT_EGPU_BUS_DEVICE_02_08 0X156D
#define PARENT_EGPU_BUS_DEVICE_02_07 0x157E
#define PARENT_EGPU_BUS_DEVICE_02_06 0x156B
#define PARENT_EGPU_BUS_DEVICE_02_05 0x1567
#define PARENT_EGPU_BUS_DEVICE_02_04 0x1569
#define PARENT_EGPU_BUS_DEVICE_02_03 0x151B
#define PARENT_EGPU_BUS_DEVICE_02_02 0x1549
#define PARENT_EGPU_BUS_DEVICE_02_01 0x1513
//*****************************************************************************
// Function: isTB3DeviceID
@@ -103,33 +118,51 @@ extern "C" {
EGPU_INLINE NvBool isTB3DeviceID(NvU16 deviceID)
{
NvU32 index;
NvU16 tb3DeviceIDList[]={ BUS_DEVICE_ID_TB3_ALPINE_RIDGE_01,
BUS_DEVICE_ID_TB3_02,
BUS_DEVICE_ID_TB3_03,
BUS_DEVICE_ID_TB3_04,
BUS_DEVICE_ID_TB3_05,
BUS_DEVICE_ID_TB3_06,
BUS_DEVICE_ID_TB3_07,
BUS_DEVICE_ID_TB3_08,
BUS_DEVICE_ID_TB3_09,
BUS_DEVICE_ID_TB3_10,
BUS_DEVICE_ID_ICELAKE_TB3_01,
BUS_DEVICE_ID_ICELAKE_TB3_02,
BUS_DEVICE_ID_ICELAKE_TB3_03,
BUS_DEVICE_ID_ICELAKE_TB3_04,
BUS_DEVICE_ID_ICELAKE_TB3_05,
BUS_DEVICE_ID_ICELAKE_TB3_06,
BUS_DEVICE_ID_TIGERLAKE_TB3_01,
BUS_DEVICE_ID_TIGERLAKE_TB3_02,
BUS_DEVICE_ID_TIGERLAKE_TB3_03,
BUS_DEVICE_ID_TIGERLAKE_TB3_04,
BUS_DEVICE_ID_TIGERLAKE_TB3_05,
BUS_DEVICE_ID_TIGERLAKE_TB3_06,
BUS_DEVICE_ID_TIGERLAKE_TB3_07,
BUS_DEVICE_ID_TIGERLAKE_TB3_08,
BUS_DEVICE_ID_TIGERLAKE_TB3_09,
BUS_DEVICE_ID_TIGERLAKE_TB3_10
};
NvU16 tb3DeviceIDList[]={ PARENT_EGPU_BUS_DEVICE_01,
PARENT_EGPU_BUS_DEVICE_02,
PARENT_EGPU_BUS_DEVICE_03,
PARENT_EGPU_BUS_DEVICE_04,
PARENT_EGPU_BUS_DEVICE_05,
PARENT_EGPU_BUS_DEVICE_06,
PARENT_EGPU_BUS_DEVICE_07,
PARENT_EGPU_BUS_DEVICE_08,
PARENT_EGPU_BUS_DEVICE_09,
PARENT_EGPU_BUS_DEVICE_10,
PARENT_EGPU_BUS_DEVICE_11,
PARENT_EGPU_BUS_DEVICE_12,
PARENT_EGPU_BUS_DEVICE_13,
PARENT_EGPU_BUS_DEVICE_14,
PARENT_EGPU_BUS_DEVICE_15,
PARENT_EGPU_BUS_DEVICE_16,
PARENT_EGPU_BUS_DEVICE_17,
PARENT_EGPU_BUS_DEVICE_18,
PARENT_EGPU_BUS_DEVICE_19,
PARENT_EGPU_BUS_DEVICE_20,
PARENT_EGPU_BUS_DEVICE_21,
PARENT_EGPU_BUS_DEVICE_22,
PARENT_EGPU_BUS_DEVICE_23,
PARENT_EGPU_BUS_DEVICE_24,
PARENT_EGPU_BUS_DEVICE_25,
PARENT_EGPU_BUS_DEVICE_26,
PARENT_EGPU_BUS_DEVICE_27,
PARENT_EGPU_BUS_DEVICE_28,
PARENT_EGPU_BUS_DEVICE_29,
PARENT_EGPU_BUS_DEVICE_30,
PARENT_EGPU_BUS_DEVICE_31,
PARENT_EGPU_BUS_DEVICE_32,
PARENT_EGPU_BUS_DEVICE_33,
PARENT_EGPU_BUS_DEVICE_34,
PARENT_EGPU_BUS_DEVICE_35,
PARENT_EGPU_BUS_DEVICE_36,
PARENT_EGPU_BUS_DEVICE_37,
PARENT_EGPU_BUS_DEVICE_38,
PARENT_EGPU_BUS_DEVICE_39,
PARENT_EGPU_BUS_DEVICE_40,
PARENT_EGPU_BUS_DEVICE_41,
PARENT_EGPU_BUS_DEVICE_42,
PARENT_EGPU_BUS_DEVICE_43
};
for (index = 0; index < (sizeof(tb3DeviceIDList)/sizeof(NvU16)); index++)
{
if (deviceID == tb3DeviceIDList[index])
@@ -161,11 +194,14 @@ EGPU_INLINE NvBool isTB3DeviceID(NvU16 deviceID)
EGPU_INLINE NvBool isTB2DeviceID(NvU16 deviceID)
{
NvU32 index;
NvU16 tb2DeviceIDList[]={ BUS_DEVICE_ID_TB2_FALCON_RIDGE_DSL5520_02,
BUS_DEVICE_ID_TB2_03, BUS_DEVICE_ID_TB2_04,
BUS_DEVICE_ID_TB2_05, BUS_DEVICE_ID_TB2_06,
BUS_DEVICE_ID_TB2_08, BUS_DEVICE_ID_TB2_09,
BUS_DEVICE_ID_TB2_10
NvU16 tb2DeviceIDList[]={ PARENT_EGPU_BUS_DEVICE_02_01,
PARENT_EGPU_BUS_DEVICE_02_02,
PARENT_EGPU_BUS_DEVICE_02_03,
PARENT_EGPU_BUS_DEVICE_02_04,
PARENT_EGPU_BUS_DEVICE_02_05,
PARENT_EGPU_BUS_DEVICE_02_06,
PARENT_EGPU_BUS_DEVICE_02_07,
PARENT_EGPU_BUS_DEVICE_02_08
};
for (index = 0; index < (sizeof(tb2DeviceIDList)/sizeof(NvU16)); index++)
{

1
src/common/inc/swref/published/turing/tu102/dev_gc6_island.h
View File

@@ -24,6 +24,7 @@
#ifndef __tu102_dev_gc6_island_h__
#define __tu102_dev_gc6_island_h__
#define NV_PGC6 0x118fff:0x118000 /* RW--D */
#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_PRIV_LEVEL_MASK 0x00118128 /* RW-4R */
#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */

4
src/common/inc/swref/published/turing/tu102/dev_nv_xve.h
View File

@@ -28,6 +28,10 @@
#define NV_XVE_MSIX_CAP_HDR_ENABLE 31:31 /* RWIVF */
#define NV_XVE_MSIX_CAP_HDR_ENABLE_ENABLED 0x00000001 /* RW--V */
#define NV_XVE_MSIX_CAP_HDR_ENABLE_DISABLED 0x00000000 /* RWI-V */
#define NV_XVE_PRIV_MISC_1 0x0000041C /* RW-4R */
#define NV_XVE_PRIV_MISC_1_CYA_HIDE_MSIX_CAP 29:29 /* RWCVF */
#define NV_XVE_PRIV_MISC_1_CYA_HIDE_MSIX_CAP_TRUE 0x00000001 /* RW--V */
#define NV_XVE_PRIV_MISC_1_CYA_HIDE_MSIX_CAP_FALSE 0x00000000 /* RWC-V */
#define NV_XVE_SRIOV_CAP_HDR3 0x00000BD8 /* R--4R */
#define NV_XVE_SRIOV_CAP_HDR3_TOTAL_VFS 31:16 /* R-EVF */
#define NV_XVE_SRIOV_CAP_HDR5 0x00000BE0 /* R--4R */

29
src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080fb.h
View File

@@ -227,7 +227,36 @@ typedef struct NV0080_CTRL_FB_GET_CAPS_V2_PARAMS {
NvU8 capsTbl[NV0080_CTRL_FB_CAPS_TBL_SIZE];
} NV0080_CTRL_FB_GET_CAPS_V2_PARAMS;
/**
* NV0080_CTRL_CMD_FB_SET_DEFAULT_VIDMEM_PHYSICALITY
*
* When clients allocate video memory specifying _DEFAULT (0) for
* NVOS32_ATTR_PHYSICALITY, RM will usually allocate contiguous memory.
* Clients can change that behavior with this command so that _DEFAULT maps to
* another value.
*
* The expectation is that clients currently implicitly rely on the default,
* but can be incrementally updated to explicitly specify _CONTIGUOUS where
* necessary and change the default for their allocations to _NONCONTIGUOUS or
* _ALLOW_NONCONTIGUOUS.
*
* In the future RM may be updated to globally default to _NONCONTIGUOUS or
* _ALLOW_NONCONTIGUOUS, and at that point this can be removed.
*/
#define NV0080_CTRL_CMD_FB_SET_DEFAULT_VIDMEM_PHYSICALITY (0x801308) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_FB_INTERFACE_ID << 8) | NV0080_CTRL_FB_SET_DEFAULT_VIDMEM_PHYSICALITY_PARAMS_MESSAGE_ID" */
#define NV0080_CTRL_FB_SET_DEFAULT_VIDMEM_PHYSICALITY_PARAMS_MESSAGE_ID (0x8U)
typedef struct NV0080_CTRL_FB_SET_DEFAULT_VIDMEM_PHYSICALITY_PARAMS {
NvU32 value;
} NV0080_CTRL_FB_SET_DEFAULT_VIDMEM_PHYSICALITY_PARAMS;
typedef enum NV0080_CTRL_FB_DEFAULT_VIDMEM_PHYSICALITY {
NV0080_CTRL_FB_DEFAULT_VIDMEM_PHYSICALITY_DEFAULT = 0,
NV0080_CTRL_FB_DEFAULT_VIDMEM_PHYSICALITY_NONCONTIGUOUS = 1,
NV0080_CTRL_FB_DEFAULT_VIDMEM_PHYSICALITY_CONTIGUOUS = 2,
NV0080_CTRL_FB_DEFAULT_VIDMEM_PHYSICALITY_ALLOW_NONCONTIGUOUS = 3,
} NV0080_CTRL_FB_DEFAULT_VIDMEM_PHYSICALITY;
/* _ctrl0080fb_h_ */

6
src/common/shared/inc/nvdevid.h
View File

@@ -446,9 +446,13 @@
#define FOXCONN_EINSTEIN_64_DEVID 0xA1C1
#define FOXCONN_EINSTEIN_64_SSDEVID 0x7270
// Lenovo Tomcat Workstation
// Lenovo Tomcat/Falcon/Hornet Workstations
#define LENOVO_TOMCAT_DEVID 0x1B81
#define LENOVO_TOMCAT_SSDEVID 0x104e
#define LENOVO_FALCON_DEVID 0x7A8A
#define LENOVO_FALCON_SSDEVID 0x1055
#define LENOVO_HORNET_DEVID 0x7A8A
#define LENOVO_HORNET_SSDEVID 0x1056
// NVIDIA C51
#define NVIDIA_C51_DEVICE_ID_MIN 0x2F0

4
src/common/uproc/os/libos-v3.1.0/lib/liblogdecode.c
View File

@@ -477,10 +477,10 @@ static int libos_printf_a(
# if defined(NVRM)
if (logDecode->curLineBufPtr == logDecode->lineBuffer)
{
// Prefix every line with NVRM GPUn Ucode-task: filename(lineNumber):
// Prefix every line with NVRM: GPUn Ucode-task: filename(lineNumber):
snprintf(
logDecode->curLineBufPtr, LIBOS_LOG_LINE_BUFFER_SIZE - 1,
"NVRM GPU%u %s-%s: %s(%u): ", pRec->log->gpuInstance,
NV_PRINTF_ADD_PREFIX("GPU%u %s-%s: %s(%u): "), pRec->log->gpuInstance,
logDecode->sourceName, pRec->log->taskPrefix, filename, pRec->meta->lineNumber);
logDecode->curLineBufPtr += portStringLength(logDecode->curLineBufPtr);
}