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535.146.02
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@@ -24,6 +24,7 @@
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#ifndef __tu102_dev_gc6_island_h__
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#define __tu102_dev_gc6_island_h__
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#define NV_PGC6 0x118fff:0x118000 /* RW--D */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_PRIV_LEVEL_MASK 0x00118128 /* RW-4R */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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@@ -28,6 +28,10 @@
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#define NV_XVE_MSIX_CAP_HDR_ENABLE 31:31 /* RWIVF */
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#define NV_XVE_MSIX_CAP_HDR_ENABLE_ENABLED 0x00000001 /* RW--V */
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#define NV_XVE_MSIX_CAP_HDR_ENABLE_DISABLED 0x00000000 /* RWI-V */
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#define NV_XVE_PRIV_MISC_1 0x0000041C /* RW-4R */
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#define NV_XVE_PRIV_MISC_1_CYA_HIDE_MSIX_CAP 29:29 /* RWCVF */
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#define NV_XVE_PRIV_MISC_1_CYA_HIDE_MSIX_CAP_TRUE 0x00000001 /* RW--V */
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#define NV_XVE_PRIV_MISC_1_CYA_HIDE_MSIX_CAP_FALSE 0x00000000 /* RWC-V */
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#define NV_XVE_SRIOV_CAP_HDR3 0x00000BD8 /* R--4R */
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#define NV_XVE_SRIOV_CAP_HDR3_TOTAL_VFS 31:16 /* R-EVF */
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#define NV_XVE_SRIOV_CAP_HDR5 0x00000BE0 /* R--4R */
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