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This commit is contained in:
Andy Ritger
2022-11-10 08:39:33 -08:00
parent 7c345b838b
commit 758b4ee818
1323 changed files with 262135 additions and 60754 deletions
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4
src/common/displayport/inc/dp_configcaps.h
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@@ -217,7 +217,7 @@ namespace DisplayPort
NvU8 activeLaneCount) = 0;
virtual AuxRetry::status setIgnoreMSATimingParamters(bool msaTimingParamIgnoreEn) = 0;
virtual AuxRetry::status setLinkQualLaneSet(unsigned lane, LinkQualityPatternType linkQualPattern) = 0;
virtual AuxRetry::status setLinkQualLaneSet(unsigned lane, LinkQualityPatternType linkQualPattern) = 0;
virtual AuxRetry::status setLinkQualPatternSet(LinkQualityPatternType linkQualPattern, unsigned laneCount = 0) = 0;
};
@@ -486,7 +486,7 @@ namespace DisplayPort
virtual bool getDpcdMultiStreamCap(void) = 0;
// Set GPU DP support capability
virtual void setGpuDPSupportedVersions(bool supportDp1_2, bool supportDp1_4) = 0;
virtual void setGpuDPSupportedVersions(NvU32 gpuDPSupportedVersions) = 0;
// Set GPU FEC support capability
virtual void setGpuFECSupported(bool bSupportFEC) = 0;

1
src/common/displayport/inc/dp_connector.h
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@@ -262,6 +262,7 @@ namespace DisplayPort
virtual bool setPanelReplayConfig(panelReplayConfig prcfg) = 0;
virtual bool isPanelReplaySupported() = 0;
virtual bool getPanelReplayStatus(PanelReplayStatus *pPrStatus) = 0;
protected:
virtual ~Device() {}

2
src/common/displayport/inc/dp_deviceimpl.h
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@@ -439,6 +439,7 @@ namespace DisplayPort
bool isPanelReplaySupported(void);
void getPanelReplayCaps(void);
bool setPanelReplayConfig(panelReplayConfig prcfg);
bool getPanelReplayStatus(PanelReplayStatus *pPrStatus);
NvBool getDSCSupport();
bool getFECSupport();
@@ -451,6 +452,7 @@ namespace DisplayPort
bool parseDscCaps(const NvU8 *buffer, NvU32 bufferSize);
bool parseBranchSpecificDscCaps(const NvU8 *buffer, NvU32 bufferSize);
bool setDscEnable(bool enable);
bool setDscEnableDPToHDMIPCON(bool bDscEnable, bool bEnablePassThroughForPCON);
bool getDscEnable(bool *pEnable);
unsigned getDscVersionMajor();
unsigned getDscVersionMinor();

20
src/common/displayport/inc/dp_evoadapter.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 1993-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -143,8 +143,13 @@ namespace DisplayPort
bool _hasMultistream;
bool _isPC2Disabled;
bool _isEDP;
bool _isDP1_2Supported;
bool _isDP1_4Supported;
//
// Bit mask for GPU supported DP versions.
// Defines the same as NV0073_CTRL_CMD_DP_GET_CAPS_PARAMS.dpVersionsSupported
//
NvU32 _gpuSupportedDpVersions;
bool _isStreamCloningEnabled;
bool _needForceRmEdid;
bool _skipPowerdownEDPPanelWhenHeadDetach;
@@ -198,14 +203,11 @@ namespace DisplayPort
return _isPC2Disabled;
}
virtual bool isDP1_2Supported()
virtual NvU32 getGpuDpSupportedVersions()
{
return _isDP1_2Supported;
}
virtual bool isDP1_4Supported()
{
return _isDP1_4Supported;
return _gpuSupportedDpVersions;
}
virtual bool isFECSupported()
{
return _isFECSupported;

8
src/common/displayport/inc/dp_mainlink.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 1993-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -129,7 +129,7 @@ namespace DisplayPort
virtual NvU32 getSorIndex() = 0;
virtual bool isInbandStereoSignalingSupported() = 0;
virtual bool isEDP() = 0;
virtual bool supportMSAOverMST() = 0;
virtual bool isForceRmEdidRequired() = 0;
@@ -175,8 +175,8 @@ namespace DisplayPort
virtual bool hasIncreasedWatermarkLimits() = 0;
virtual bool hasMultistream() = 0;
virtual bool isPC2Disabled() = 0;
virtual bool isDP1_2Supported() = 0;
virtual bool isDP1_4Supported() = 0;
virtual NvU32 getGpuDpSupportedVersions() = 0;
virtual bool isStreamCloningEnabled() = 0;
virtual NvU32 maxLinkRateSupported() = 0;
virtual bool isLttprSupported() = 0;

14
src/common/displayport/inc/dp_messages.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2010-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2010-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -116,10 +116,6 @@ namespace DisplayPort
bool isBeingDestroyed;
bool isPaused;
// Properties from regkey
bool bNoReplyTimerForBusyWaiting;
bool bDpcdProbingForBusyWaiting;
List messageReceivers;
List notYetSentDownRequest; // Down Messages yet to be processed
List notYetSentUpReply; // Up Reply Messages yet to be processed
@@ -157,14 +153,6 @@ namespace DisplayPort
mergerDownReply.mailboxInterrupt();
}
void applyRegkeyOverrides(const DP_REGKEY_DATABASE& dpRegkeyDatabase)
{
DP_ASSERT(dpRegkeyDatabase.bInitialized &&
"All regkeys are invalid because dpRegkeyDatabase is not initialized!");
bNoReplyTimerForBusyWaiting = dpRegkeyDatabase.bNoReplyTimerForBusyWaiting;
bDpcdProbingForBusyWaiting = dpRegkeyDatabase.bDpcdProbingForBusyWaiting;
}
MessageManager(DPCDHAL * hal, Timer * timer)
: timer(timer), hal(hal),
splitterDownRequest(hal, timer),

8
src/common/displayport/inc/dp_regkeydatabase.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2020-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -65,10 +65,6 @@
//
#define NV_DP_DSC_MST_CAP_BUG_3143315 "DP_DSC_MST_CAP_BUG_3143315"
#define NV_DP_REGKEY_NO_REPLY_TIMER_FOR_BUSY_WAITING "NO_REPLY_TIMER_FOR_BUSY_WAITING"
#define NV_DP_REGKEY_DPCD_PROBING_FOR_BUSY_WAITING "DP_DPCD_PROBING_FOR_BUSY_WAITING"
//
// Data Base used to store all the regkey values.
// The actual data base is declared statically in dp_evoadapter.cpp.
@@ -100,8 +96,6 @@ struct DP_REGKEY_DATABASE
bool bOptLinkKeptAliveSst;
bool bBypassEDPRevCheck;
bool bDscMstCapBug3143315;
bool bNoReplyTimerForBusyWaiting;
bool bDpcdProbingForBusyWaiting;
};
#endif //INCLUDED_DP_REGKEYDATABASE_H

9
src/common/displayport/inc/dp_watermark.h
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@@ -54,6 +54,7 @@ namespace DisplayPort
unsigned bitsPerComponent; // Bits per component
bool bEnableDsc; // bEnableDsc=1 indicates DSC would be enabled for the mode
DSC_MODE mode; // DSC Mode
bool bEnablePassThroughForPCON;
ModesetInfo(): twoChannelAudioHz(0),
eightChannelAudioHz(0),
@@ -67,13 +68,14 @@ namespace DisplayPort
rasterBlankEndX(0),
bitsPerComponent(0),
bEnableDsc(false),
mode(DSC_SINGLE) {}
mode(DSC_SINGLE),
bEnablePassThroughForPCON(false) {}
ModesetInfo(unsigned newTwoChannelAudioHz, unsigned newEightChannelAudioHz, NvU64 newPixelClockHz,
unsigned newRasterWidth, unsigned newRasterHeight,
unsigned newSurfaceWidth, unsigned newSurfaceHeight, unsigned newDepth,
unsigned newRasterBlankStartX=0, unsigned newRasterBlankEndX=0, bool newBEnableDsc = false,
DSC_MODE newMode = DSC_SINGLE):
DSC_MODE newMode = DSC_SINGLE, bool newBEnablePassThroughForPCON = false):
twoChannelAudioHz(newTwoChannelAudioHz),
eightChannelAudioHz(newEightChannelAudioHz),
pixelClockHz(newPixelClockHz),
@@ -86,7 +88,8 @@ namespace DisplayPort
rasterBlankEndX(newRasterBlankEndX),
bitsPerComponent(0),
bEnableDsc(newBEnableDsc),
mode(newMode){}
mode(newMode),
bEnablePassThroughForPCON(newBEnablePassThroughForPCON) {}
};
struct Watermark

37
src/common/displayport/src/dp_configcaps.cpp
View File

@@ -40,8 +40,6 @@ struct DPCDHALImpl : DPCDHAL
AuxRetry bus;
Timer * timer;
bool dpcdOffline;
bool gpuDP1_2Supported;
bool gpuDP1_4Supported;
bool bGrantsPostLtRequest;
bool pc2Disabled;
bool uprequestEnable;
@@ -54,6 +52,8 @@ struct DPCDHALImpl : DPCDHAL
NvU32 overrideDpcdRev;
NvU32 overrideDpcdMaxLaneCount;
NvU32 gpuDPSupportedVersions;
struct _LegacyPort: public LegacyPort
{
DwnStreamPortType type;
@@ -226,8 +226,6 @@ struct DPCDHALImpl : DPCDHAL
DPCDHALImpl(AuxBus * bus, Timer * timer)
: bus(bus),
timer(timer),
gpuDP1_2Supported(false),
gpuDP1_4Supported(false),
bGrantsPostLtRequest(false),
uprequestEnable(false),
upstreamIsSource(false),
@@ -235,7 +233,8 @@ struct DPCDHALImpl : DPCDHAL
bGpuFECSupported(false),
bBypassILREdpRevCheck(false),
overrideDpcdMaxLinkRate(0),
overrideDpcdRev(0)
overrideDpcdRev(0),
gpuDPSupportedVersions(0)
{
// start with default caps.
populateFakeDpcd();
@@ -390,8 +389,9 @@ struct DPCDHALImpl : DPCDHAL
{
DP_ASSERT(0 && "A DPRX with DPCD Rev. 1.4 (or higher) must have Extended Receiver Capability field.");
}
caps.supportsESI = (isAtLeastVersion(1,2) && gpuDP1_2Supported); // Support ESI register space only when GPU support DP1.2MST
// Support ESI register space only when GPU support DP1.2MST
caps.supportsESI = (isAtLeastVersion(1,2) &&
FLD_TEST_DRF(0073_CTRL_CMD_DP, _GET_CAPS_DP_VERSIONS_SUPPORTED, _DP1_2, _YES, gpuDPSupportedVersions));
if (caps.eDpRevision >= NV_DPCD_EDP_REV_VAL_1_4 || this->bBypassILREdpRevCheck)
{
@@ -454,7 +454,9 @@ struct DPCDHALImpl : DPCDHAL
DP_ASSERT(0 && "A DPRX with DPCD Rev. 1.1 (or higher) must have enhanced framing capability.");
}
if (isAtLeastVersion(1,2) && gpuDP1_2Supported && caps.bPostLtAdjustmentSupport)
if (isAtLeastVersion(1,2) &&
FLD_TEST_DRF(0073_CTRL_CMD_DP, _GET_CAPS_DP_VERSIONS_SUPPORTED, _DP1_2, _YES, gpuDPSupportedVersions) &&
caps.bPostLtAdjustmentSupport)
{
// Source grants post Link training adjustment support
bGrantsPostLtRequest = true;
@@ -1033,6 +1035,9 @@ struct DPCDHALImpl : DPCDHAL
caps.pconCaps.maxBpc = 8;
break;
}
NvU8 pConColorConvCaps = basicCaps[infoByte0+3];
caps.pconCaps.bConv444To420Supported = FLD_TEST_DRF(_DPCD, _DETAILED_CAP, _CONV_YCBCR444_TO_YCBCR420_SUPPORTED, _YES, pConColorConvCaps);
break;
}
case NV_DPCD_DETAILED_CAP_INFO_DWNSTRM_PORT_TX_TYPE_OTHERS_NO_EDID:
@@ -1231,7 +1236,8 @@ struct DPCDHALImpl : DPCDHAL
// If the upstream DPTX and downstream DPRX both support TPS4,
// TPS4 shall be used instead of POST_LT_ADJ_REQ.
//
NvBool bTps4Supported = gpuDP1_4Supported && caps.bSupportsTPS4;
NvBool bTps4Supported = FLD_TEST_DRF(0073_CTRL_CMD_DP, _GET_CAPS_DP_VERSIONS_SUPPORTED, _DP1_4, _YES, gpuDPSupportedVersions) &&
caps.bSupportsTPS4;
return bGrantsPostLtRequest && !bTps4Supported;
}
@@ -2559,13 +2565,16 @@ struct DPCDHALImpl : DPCDHAL
return caps.supportsMultistream;
}
void setGpuDPSupportedVersions(bool supportDp1_2, bool supportDp1_4)
void setGpuDPSupportedVersions(NvU32 _gpuDPSupportedVersions)
{
if (supportDp1_4)
DP_ASSERT(supportDp1_2 && "GPU supports DP1.4 should also support DP1.2!");
bool bSupportDp1_2 = FLD_TEST_DRF(0073_CTRL_CMD_DP, _GET_CAPS_DP_VERSIONS_SUPPORTED, _DP1_2, _YES, gpuDPSupportedVersions);
bool bSupportDp1_4 = FLD_TEST_DRF(0073_CTRL_CMD_DP, _GET_CAPS_DP_VERSIONS_SUPPORTED, _DP1_4, _YES, gpuDPSupportedVersions);
if (bSupportDp1_4)
{
DP_ASSERT(bSupportDp1_2 && "GPU supports DP1.4 should also support DP1.2!");
}
gpuDP1_2Supported = supportDp1_2;
gpuDP1_4Supported = supportDp1_4;
gpuDPSupportedVersions = _gpuDPSupportedVersions;
}
void setGpuFECSupported(bool bSupportFEC)

61
src/common/displayport/src/dp_connectorimpl.cpp
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 1993-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -141,7 +141,7 @@ ConnectorImpl::ConnectorImpl(MainLink * main, AuxBus * auxBus, Timer * timer, Co
// If a GPU is DP1.2 or DP1.4 supported then set these capalibilities.
// This is used for accessing DP1.2/DP1.4 specific register space & features
//
hal->setGpuDPSupportedVersions(main->isDP1_2Supported(), main->isDP1_4Supported());
hal->setGpuDPSupportedVersions(main->getGpuDpSupportedVersions());
// Set if GPU supports FEC. Check panel FEC caps only if GPU supports it.
hal->setGpuFECSupported(main->isFECSupported());
@@ -657,7 +657,7 @@ create:
// where we toggle the link state. Only after this we should read DSC caps in this case.
// Following this assesslink calls fireEvents() which will report
// the new devies to clients and client will have the correct DSC caps.
//
//
bool bGpuDscSupported;
// Check GPU DSC Support
@@ -1229,14 +1229,14 @@ bool ConnectorImpl::compoundQueryAttach(Group * target,
{
//
// Bug 3692417
// Color format should only depend on device doing DSC decompression when DSC is enabled according to DP Spec.
// But when Synaptics VMM5320 is the parent of the device doing DSC decompression, if a certain color
// Color format should only depend on device doing DSC decompression when DSC is enabled according to DP Spec.
// But when Synaptics VMM5320 is the parent of the device doing DSC decompression, if a certain color
// format is not supported by Synaptics Virtual Peer Device decoder(parent), even though it is pass through mode
// and panel supports the color format, panel cannot light up. Once Synaptics fixes this issue, we will modify
// and panel supports the color format, panel cannot light up. Once Synaptics fixes this issue, we will modify
// the WAR to be applied only before the firmware version that fixes it.
//
if ((modesetParams.colorFormat == dpColorFormat_RGB && !dev->parent->dscCaps.dscDecoderColorFormatCaps.bRgb) ||
(modesetParams.colorFormat == dpColorFormat_YCbCr444 && !dev->parent->dscCaps.dscDecoderColorFormatCaps.bYCbCr444) ||
(modesetParams.colorFormat == dpColorFormat_YCbCr444 && !dev->parent->dscCaps.dscDecoderColorFormatCaps.bYCbCr444) ||
(modesetParams.colorFormat == dpColorFormat_YCbCr422 && !dev->parent->dscCaps.dscDecoderColorFormatCaps.bYCbCrSimple422))
{
if (pDscParams->forceDsc == DSC_FORCE_ENABLE)
@@ -2548,17 +2548,18 @@ bool ConnectorImpl::setDeviceDscState(Device * dev, bool bEnableDsc)
bool ConnectorImpl::notifyAttachBegin(Group * target, // Group of panels we're attaching to this head
const DpModesetParams &modesetParams)
{
unsigned twoChannelAudioHz = modesetParams.modesetInfo.twoChannelAudioHz;
unsigned eightChannelAudioHz = modesetParams.modesetInfo.eightChannelAudioHz;
NvU64 pixelClockHz = modesetParams.modesetInfo.pixelClockHz;
unsigned rasterWidth = modesetParams.modesetInfo.rasterWidth;
unsigned rasterHeight = modesetParams.modesetInfo.rasterHeight;
unsigned rasterBlankStartX = modesetParams.modesetInfo.rasterBlankStartX;
unsigned rasterBlankEndX = modesetParams.modesetInfo.rasterBlankEndX;
unsigned depth = modesetParams.modesetInfo.depth;
bool bLinkTrainingStatus = true;
bool bEnableDsc = modesetParams.modesetInfo.bEnableDsc;
unsigned twoChannelAudioHz = modesetParams.modesetInfo.twoChannelAudioHz;
unsigned eightChannelAudioHz = modesetParams.modesetInfo.eightChannelAudioHz;
NvU64 pixelClockHz = modesetParams.modesetInfo.pixelClockHz;
unsigned rasterWidth = modesetParams.modesetInfo.rasterWidth;
unsigned rasterHeight = modesetParams.modesetInfo.rasterHeight;
unsigned rasterBlankStartX = modesetParams.modesetInfo.rasterBlankStartX;
unsigned rasterBlankEndX = modesetParams.modesetInfo.rasterBlankEndX;
unsigned depth = modesetParams.modesetInfo.depth;
bool bLinkTrainingStatus = true;
bool bEnableDsc = modesetParams.modesetInfo.bEnableDsc;
bool bEnableFEC;
bool bEnablePassThroughForPCON = modesetParams.modesetInfo.bEnablePassThroughForPCON;
if(preferredLinkConfig.isValid())
{
@@ -2676,7 +2677,14 @@ bool ConnectorImpl::notifyAttachBegin(Group * target, // Gr
{
for (Device * dev = target->enumDevices(0); dev; dev = target->enumDevices(dev))
{
if(!setDeviceDscState(dev, bEnableDsc))
if (bPConConnected)
{
if (!(((DeviceImpl *)dev)->setDscEnableDPToHDMIPCON(bEnableDsc, bEnablePassThroughForPCON)))
{
DP_ASSERT(!"DP-CONN> Failed to configure DSC on DP to HDMI PCON!");
}
}
else if(!setDeviceDscState(dev, bEnableDsc))
{
DP_ASSERT(!"DP-CONN> Failed to configure DSC on Sink!");
}
@@ -3995,11 +4003,11 @@ bool ConnectorImpl::trainLinkOptimized(LinkConfiguration lConfig)
if ((groupAttached->dscModeRequest == DSC_DUAL) && (groupAttached->dscModeActive != DSC_DUAL))
{
//
// If current modeset group requires 2Head1OR and
// If current modeset group requires 2Head1OR and
// - group is not active yet (first modeset on the group)
// - group is active but not in 2Head1OR mode (last modeset on the group did not require 2Head1OR)
// then re-train the link
// This is because for 2Head1OR mode, we need to set some LT parametes for slave SOR after
// This is because for 2Head1OR mode, we need to set some LT parametes for slave SOR after
// successful LT on primary SOR without which 2Head1OR modeset will lead to HW hang.
//
bTwoHeadOneOrLinkRetrain = true;
@@ -4090,9 +4098,9 @@ bool ConnectorImpl::trainLinkOptimized(LinkConfiguration lConfig)
//
// Check if we are already trained to the desired link config?
// Make sure requested FEC state matches with the current FEC state of link.
// If 2Head1OR mode is requested, retrain if group is not active or
// last modeset on active group was not in 2Head1OR mode.
// bTwoHeadOneOrLinkRetrain tracks this requirement.
// If 2Head1OR mode is requested, retrain if group is not active or
// last modeset on active group was not in 2Head1OR mode.
// bTwoHeadOneOrLinkRetrain tracks this requirement.
//
//
@@ -4222,8 +4230,8 @@ bool ConnectorImpl::trainLinkOptimized(LinkConfiguration lConfig)
//
// Make sure link is physically active and healthy, otherwise re-train.
// Make sure requested FEC state matches with the current FEC state of link.
// If 2Head1OR mode is requested, retrain if group is not active or last modeset on active group
// was not in 2Head1OR mode. bTwoHeadOneOrLinkRetrain tracks this requirement.
// If 2Head1OR mode is requested, retrain if group is not active or last modeset on active group
// was not in 2Head1OR mode. bTwoHeadOneOrLinkRetrain tracks this requirement.
//
bRetrainToEnsureLinkStatus = (isLinkActive() && isLinkInD3()) ||
isLinkLost() ||
@@ -5670,7 +5678,7 @@ void ConnectorImpl::notifyLongPulseInternal(bool statusConnected)
if (hal->getSupportsMultistream() && main->hasMultistream())
{
bool bDeleteFirmwareVC = false;
const DP_REGKEY_DATABASE& dpRegkeyDatabase = main->getRegkeyDatabase();
DP_LOG(("DP> Multistream panel detected, building message manager"));
//
@@ -5679,7 +5687,6 @@ void ConnectorImpl::notifyLongPulseInternal(bool statusConnected)
//
messageManager = new MessageManager(hal, timer);
messageManager->registerReceiver(&ResStatus);
messageManager->applyRegkeyOverrides(dpRegkeyDatabase);
//
// Create a discovery manager to initiate detection

89
src/common/displayport/src/dp_deviceimpl.cpp
View File

@@ -1517,6 +1517,47 @@ bool DeviceImpl::setPanelReplayConfig(panelReplayConfig prcfg)
return false;
}
bool DeviceImpl::getPanelReplayStatus(PanelReplayStatus *pPrStatus)
{
NvU8 state = 0;
unsigned size = 0;
unsigned nakReason = NakUndefined;
if (pPrStatus == NULL)
{
DP_ASSERT(0);
return false;
}
if(AuxBus::success == this->getDpcdData(NV_DPCD20_PANEL_REPLAY_AND_FRAME_LOCK_STATUS,
&state, sizeof(state), &size, &nakReason))
{
switch (DRF_VAL(_DPCD20, _PANEL_REPLAY_AND_FRAME_LOCK_STATUS, _PR_STATUS, state))
{
case NV_DPCD20_PANEL_REPLAY_AND_FRAME_LOCK_STATUS_PR_STATUS_STATE_0:
pPrStatus->prState = PanelReplay_Inactive;
break;
case NV_DPCD20_PANEL_REPLAY_AND_FRAME_LOCK_STATUS_PR_STATUS_STATE_1:
pPrStatus->prState = PanelReplay_CaptureAndDisplay;
break;
case NV_DPCD20_PANEL_REPLAY_AND_FRAME_LOCK_STATUS_PR_STATUS_STATE_2:
pPrStatus->prState = PanelReplay_DisplayFromRfb;
break;
default:
pPrStatus->prState = PanelReplay_Undefined;
break;
}
return true;
}
else
{
return false;
}
}
bool DeviceImpl::getFECSupport()
{
NvU8 byte = 0;
@@ -2043,6 +2084,54 @@ bool DeviceImpl::setDscEnable(bool enable)
}
}
bool DeviceImpl::setDscEnableDPToHDMIPCON(bool bDscEnable, bool bEnablePassThroughForPCON)
{
NvU8 dscEnableByte = 0;
unsigned size = 0;
unsigned nakReason = NakUndefined;
AuxBus::status dscEnableStatus = AuxBus::success;
Address::StringBuffer buffer;
DP_USED(buffer);
if (!this->isDSCPossible())
{
DP_LOG(("DP-DEV> DSC is not supported on DP to HDMI PCON - %s"));
return false;
}
if (bDscEnable)
{
if(bEnablePassThroughForPCON)
{
dscEnableByte = FLD_SET_DRF(_DPCD20, _DSC_PASS_THROUGH, _ENABLE, _YES, dscEnableByte);
DP_LOG(("DP-DEV> Enabling DSC Pass through on DP to HDMI PCON device - %s",
this->getTopologyAddress().toString(buffer)));
}
else
{
dscEnableByte = FLD_SET_DRF(_DPCD14, _DSC_ENABLE, _SINK, _YES, dscEnableByte);
DP_LOG(("DP-DEV> Enabling DSC decompression on DP to HDMI PCON device - %s",
this->getTopologyAddress().toString(buffer)));
}
}
dscEnableStatus = this->setDpcdData(NV_DPCD14_DSC_ENABLE,
&dscEnableByte, sizeof dscEnableByte, &size, &nakReason);
if (dscEnableStatus != AuxBus::success)
{
DP_LOG(("DP-DEV> Setting DSC Enable on DP to HDMI PCON %s failed",
this->getTopologyAddress().toString(buffer)));
return false;
}
return true;
}
unsigned DeviceImpl::getDscVersionMajor()
{
return dscCaps.versionMajor;

9
src/common/displayport/src/dp_evoadapter.cpp
View File

@@ -93,9 +93,7 @@ const struct
{NV_DP_REGKEY_KEEP_OPT_LINK_ALIVE_MST, &dpRegkeyDatabase.bOptLinkKeptAliveMst, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_KEEP_OPT_LINK_ALIVE_SST, &dpRegkeyDatabase.bOptLinkKeptAliveSst, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_FORCE_EDP_ILR, &dpRegkeyDatabase.bBypassEDPRevCheck, DP_REG_VAL_BOOL},
{NV_DP_DSC_MST_CAP_BUG_3143315, &dpRegkeyDatabase.bDscMstCapBug3143315, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_NO_REPLY_TIMER_FOR_BUSY_WAITING, &dpRegkeyDatabase.bNoReplyTimerForBusyWaiting, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_DPCD_PROBING_FOR_BUSY_WAITING, &dpRegkeyDatabase.bDpcdProbingForBusyWaiting, DP_REG_VAL_BOOL}
{NV_DP_DSC_MST_CAP_BUG_3143315, &dpRegkeyDatabase.bDscMstCapBug3143315, DP_REG_VAL_BOOL}
};
EvoMainLink::EvoMainLink(EvoInterface * provider, Timer * timer) :
@@ -279,8 +277,9 @@ void EvoMainLink::queryGPUCapability()
// MST feature on particular sku, whenever requested through INF.
//
_hasMultistream = (params.bIsMultistreamSupported == NV_TRUE) && !_isMstDisabledByRegkey;
_isDP1_2Supported = (params.bIsDp12Supported == NV_TRUE) ? true : false;
_isDP1_4Supported = (params.bIsDp14Supported == NV_TRUE) ? true : false;
_gpuSupportedDpVersions = params.dpVersionsSupported;
_isStreamCloningEnabled = (params.bIsSCEnabled == NV_TRUE) ? true : false;
_hasIncreasedWatermarkLimits = (params.bHasIncreasedWatermarkLimits == NV_TRUE) ? true : false;

26
src/common/displayport/src/dp_messages.cpp
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2010-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2010-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -63,27 +63,19 @@ bool MessageManager::send(MessageManager::Message * message, NakData & nakData)
DP_USED(sb);
NvU64 startTime, elapsedTime;
if (bNoReplyTimerForBusyWaiting)
{
message->bBusyWaiting = true;
}
message->bBusyWaiting = true;
post(message, &completion);
startTime = timer->getTimeUs();
do
{
if (bDpcdProbingForBusyWaiting)
hal->updateDPCDOffline();
if (hal->isDpcdOffline())
{
hal->updateDPCDOffline();
if (hal->isDpcdOffline())
{
DP_LOG(("DP-MM> Device went offline while waiting for reply and so ignoring message %p (ID = %02X, target = %s)",
(Message*)this, ((Message*)this)->requestIdentifier, (((Message*)this)->state.target).toString(sb)));
nakData = completion.nakData;
completion.failed = true;
break;
}
DP_LOG(("DP-MM> Device went offline while waiting for reply and so ignoring message %p (ID = %02X, target = %s)",
message, message->requestIdentifier, ((message->state).target).toString(sb)));
nakData = completion.nakData;
completion.failed = true;
break;
}
hal->notifyIRQ();

15
src/common/inc/displayport/displayport.h
View File

@@ -289,6 +289,7 @@ typedef struct
{
NvBool bSourceControlModeSupported;
NvBool bConcurrentLTSupported;
NvBool bConv444To420Supported;
NvU8 maxTmdsClkRate;
NvU8 maxBpc;
NvU8 maxHdmiLinkBandwidthGbps;
@@ -458,6 +459,20 @@ typedef struct PanelReplayConfig
NvBool enablePanelReplay;
} panelReplayConfig;
// PR state
typedef enum
{
PanelReplay_Inactive = 0,
PanelReplay_CaptureAndDisplay = 1,
PanelReplay_DisplayFromRfb = 2,
PanelReplay_Undefined = 7
} PanelReplayState;
typedef struct
{
PanelReplayState prState;
} PanelReplayStatus;
// Multiplier constant to get link frequency in KHZ
// Maximum link rate of Main Link lanes = Value x 270M.
// To get it to KHz unit, we need to multiply 270K.

14
src/common/inc/displayport/dpcd20.h
View File

@@ -47,6 +47,18 @@
#define NV_DPCD20_PANEL_REPLAY_CONFIGURATION_ENABLE_PR_MODE_NO (0x00000000)
#define NV_DPCD20_PANEL_REPLAY_CONFIGURATION_ENABLE_PR_MODE_YES (0x00000001)
#define NV_DPCD20_PANEL_REPLAY_AND_FRAME_LOCK_STATUS (0x00002022)
#define NV_DPCD20_PANEL_REPLAY_AND_FRAME_LOCK_STATUS_PR_STATUS 2:0
#define NV_DPCD20_PANEL_REPLAY_AND_FRAME_LOCK_STATUS_PR_STATUS_STATE_0 (0x00000000)
#define NV_DPCD20_PANEL_REPLAY_AND_FRAME_LOCK_STATUS_PR_STATUS_STATE_1 (0x00000001)
#define NV_DPCD20_PANEL_REPLAY_AND_FRAME_LOCK_STATUS_PR_STATUS_STATE_2 (0x00000002)
#define NV_DPCD20_PANEL_REPLAY_AND_FRAME_LOCK_STATUS_PR_STATUS_STATE_ERROR (0x00000007)
#define NV_DPCD20_PANEL_REPLAY_AND_FRAME_LOCK_STATUS_SINK_FRAME_LOCKED 4:3
#define NV_DPCD20_PANEL_REPLAY_AND_FRAME_LOCK_STATUS_SINK_FRAME_LOCKED_LOCKED (0x00000000)
#define NV_DPCD20_PANEL_REPLAY_AND_FRAME_LOCK_STATUS_SINK_FRAME_LOCKED_COASTING (0x00000001)
#define NV_DPCD20_PANEL_REPLAY_AND_FRAME_LOCK_STATUS_SINK_FRAME_LOCKED_GOVERNING (0x00000002)
#define NV_DPCD20_PANEL_REPLAY_AND_FRAME_LOCK_STATUS_SINK_FRAME_LOCKED_RELOCKING (0x00000003)
// BRANCH SPECIFIC DSC CAPS
#define NV_DPCD20_BRANCH_DSC_OVERALL_THROUGHPUT_MODE_0 (0x000000A0)
#define NV_DPCD20_BRANCH_DSC_OVERALL_THROUGHPUT_MODE_0_VALUE 7:0
@@ -55,4 +67,4 @@
#define NV_DPCD20_BRANCH_DSC_OVERALL_THROUGHPUT_MODE_1_VALUE 7:0
#define NV_DPCD20_BRANCH_DSC_MAXIMUM_LINE_BUFFER_WIDTH (0x000000A2)
#define NV_DPCD20_BRANCH_DSC_MAXIMUM_LINE_BUFFER_WIDTH_VALUE 7:0
#define NV_DPCD20_BRANCH_DSC_MAXIMUM_LINE_BUFFER_WIDTH_VALUE 7:0

51
src/common/inc/gps.h Normal file
View File

@@ -0,0 +1,51 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2011-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef GPS_H
#define GPS_H
#define GPS_REVISION_ID 0x00000100
#define GPS_2X_REVISION_ID 0x00000200
#define GPS_FUNC_SUPPORT 0x00000000 // Bit list of supported functions
#define GPS_FUNC_GETOBJBYTYPE 0x00000010 // Fetch any specific Object by Type
#define GPS_FUNC_GETALLOBJS 0x00000011 // Fetch all Objects
#define GPS_FUNC_GETCALLBACKS 0x00000013 // Get system requested callbacks
#define GPS_FUNC_PCONTROL 0x0000001C // GPU power control function
#define GPS_FUNC_PSHARESTATUS 0x00000020 // Get system requested Power Steering settings
#define GPS_FUNC_GETPSS 0x00000021 // Get _PSS object
#define GPS_FUNC_SETPPC 0x00000022 // Set _PPC object
#define GPS_FUNC_GETPPC 0x00000023 // Get _PPC object
#define GPS_FUNC_GETPPL 0x00000024 // Get CPU package power limits
#define GPS_FUNC_SETPPL 0x00000025 // Set CPU package power limits
#define GPS_FUNC_GETTRL 0x00000026 // Get CPU turbo ratio limits
#define GPS_FUNC_SETTRL 0x00000027 // Set CPU turbo ratio limits
#define GPS_FUNC_GETPPM 0x00000028 // Get system power modes
#define GPS_FUNC_SETPPM 0x00000029 // Set system power modes
#define GPS_FUNC_PSHAREPARAMS 0x0000002A // Get sensor information and capabilities
#define GPS_EVENT_STATUS_CHANGE 0x000000C0 // when received call GPS_FUNC_PCONTROL,
// depends on whether system is GPS enabled.
#endif // GPS_H

94
src/common/inc/jt.h Normal file
View File

@@ -0,0 +1,94 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2012-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef JT_H
#define JT_H
//
// JT ACPI _DSM method related definitions
//
#define JT_REVISION_ID 0x00000103 // Revision number
// subfunction 0 is common use: NV_ACPI_ALL_FUNC_SUPPORT
// #define JT_FUNC_SUPPORT 0x00000000 // Function is supported?
#define JT_FUNC_CAPS 0x00000001 // Capabilities
#define JT_FUNC_POLICYSELECT 0x00000002 // Query Policy Selector Status (reserved for future use)
#define JT_FUNC_POWERCONTROL 0x00000003 // dGPU Power Control
#define JT_FUNC_PLATPOLICY 0x00000004 // Query the Platform Policies (reserved for future use)
#define JT_FUNC_DISPLAYSTATUS 0x00000005 // Query the Display Hot-Key
#define JT_FUNC_MDTL 0x00000006 // Display Hot-Key Toggle List
//
// JT_FUNC_CAPS return buffer definitions
//
#define NV_JT_FUNC_CAPS_JT_ENABLED 0:0
#define NV_JT_FUNC_CAPS_JT_ENABLED_FALSE 0x00000000
#define NV_JT_FUNC_CAPS_JT_ENABLED_TRUE 0x00000001
#define NV_JT_FUNC_CAPS_NVSR_ENABLED 2:1
#define NV_JT_FUNC_CAPS_NVSR_ENABLED_TRUE 0x00000000
#define NV_JT_FUNC_CAPS_NVSR_ENABLED_FALSE 0x00000001
#define NV_JT_FUNC_CAPS_PPR 4:3
#define NV_JT_FUNC_CAPS_PPR_GC6 0x00000000
#define NV_JT_FUNC_CAPS_PPR_GC6S3SR 0x00000002
#define NV_JT_FUNC_CAPS_SRPR 5:5
#define NV_JT_FUNC_CAPS_SRPR_PANEL 0x00000000
#define NV_JT_FUNC_CAPS_SRPR_SUSPEND 0x00000001
#define NV_JT_FUNC_CAPS_FBPR 7:6
#define NV_JT_FUNC_CAPS_FBPR_GC6_ON 0x00000000
#define NV_JT_FUNC_CAPS_FBPR_GC6_S3 0x00000002
#define NV_JT_FUNC_CAPS_GPR 9:8
#define NV_JT_FUNC_CAPS_GPR_COMBINED 0x00000000
#define NV_JT_FUNC_CAPS_GPR_PERGPU 0x00000001
#define NV_JT_FUNC_CAPS_GCR 10:10
#define NV_JT_FUNC_CAPS_GCR_EXTERNAL 0x00000000
#define NV_JT_FUNC_CAPS_GCR_INTEGRATED 0x00000001
#define NV_JT_FUNC_CAPS_PTH_ENABLED 11:11
#define NV_JT_FUNC_CAPS_PTH_ENABLED_YES 0x00000000
#define NV_JT_FUNC_CAPS_PTH_ENABLED_NO 0x00000001
#define NV_JT_FUNC_CAPS_NOT 12:12
#define NV_JT_FUNC_CAPS_NOT_GC6DONE 0x00000000
#define NV_JT_FUNC_CAPS_NOT_LINKCHANGE 0x00000001
#define NV_JT_FUNC_CAPS_MSHYB_ENABLED 13:13
#define NV_JT_FUNC_CAPS_MSHYB_ENABLED_FALSE 0x00000000
#define NV_JT_FUNC_CAPS_MSHYB_ENABLED_TRUE 0x00000001
#define NV_JT_FUNC_CAPS_RPC 14:14
#define NV_JT_FUNC_CAPS_RPC_DEFAULT 0x00000000
#define NV_JT_FUNC_CAPS_RPC_FINEGRAIN 0x00000001
#define NV_JT_FUNC_CAPS_GC6V 16:15
#define NV_JT_FUNC_CAPS_GC6V_GC6E 0x00000000
#define NV_JT_FUNC_CAPS_GC6V_GC6A 0x00000001
#define NV_JT_FUNC_CAPS_GC6V_GC6R 0x00000002
#define NV_JT_FUNC_CAPS_GEI_ENABLED 17:17
#define NV_JT_FUNC_CAPS_GEI_ENABLED_FALSE 0x00000000
#define NV_JT_FUNC_CAPS_GEI_ENABLED_TRUE 0x00000001
#define NV_JT_FUNC_CAPS_GSW_ENABLED 18:18
#define NV_JT_FUNC_CAPS_GSW_ENABLED_FALSE 0x00000000
#define NV_JT_FUNC_CAPS_GSW_ENABLED_TRUE 0x00000001
#define NV_JT_FUNC_CAPS_REVISION_ID 31:20
#define NV_JT_FUNC_CAPS_REVISION_ID_1_00 0x00000100
#define NV_JT_FUNC_CAPS_REVISION_ID_1_01 0x00000101
#define NV_JT_FUNC_CAPS_REVISION_ID_1_03 0x00000103
#define NV_JT_FUNC_CAPS_REVISION_ID_2_00 0x00000200
#endif // JT_H

46
src/common/inc/mxm_spec.h Normal file
View File

@@ -0,0 +1,46 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 1993 - 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _MXM_SPEC_H_
#define _MXM_SPEC_H_
/**************** Resource Manager Defines and Structures ******************\
* *
* Module: MXM_SPEC.H *
* Defines used for MXM *
\***************************************************************************/
// MXM3.x ACPI revision ID
#define ACPI_MXM_REVISION_ID 0x00000300 // MXM revision ID
// Subfunctions of _DSM in MXM 3.x
#define NV_ACPI_DSM_MXM_FUNC_MXSS 0x00000000 // Supported Sub-Functions
#define NV_ACPI_DSM_MXM_FUNC_MXMI 0x00000018 // Platform MXM Capabilities
#define NV_ACPI_DSM_MXM_FUNC_MXMS 0x00000010 // Get the MXM Structure
#define NV_ACPI_DSM_MXM_FUNC_MXPP 0x00000004 // Get/Set Platform Policies
#define NV_ACPI_DSM_MXM_FUNC_MXDP 0x00000005 // Get/Set Display Config
#define NV_ACPI_DSM_MXM_FUNC_MDTL 0x00000006 // Get Display Toggle List
#define NV_ACPI_DSM_MXM_FUNC_MXCB 0x00000019 // Get Callbacks
#define NV_ACPI_DSM_MXM_FUNC_GETEVENTLIST 0x00000012 // Get Event List
#endif // _MXM_SPEC_H_

48
src/common/inc/nbci.h Normal file
View File

@@ -0,0 +1,48 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 1993 - 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef NBCI_H_
#define NBCI_H_
/******************************************************************************
*
* Provides the NBCI (NoteBook Common Interface) spec defines for
* use by multiple clients.
*
******************************************************************************/
#define NBCI_REVISION_ID 0x00000102
// NBCI _DSM function codes
#define NV_NBCI_FUNC_SUPPORT 0x00000000
#define NV_NBCI_FUNC_PLATCAPS 0x00000001
#define NV_NBCI_FUNC_PLATPOLICY 0x00000004
#define NV_NBCI_FUNC_DISPLAYSTATUS 0x00000005
#define NV_NBCI_FUNC_MDTL 0x00000006
#define NV_NBCI_FUNC_GETOBJBYTYPE 0x00000010
#define NV_NBCI_FUNC_GETALLOBJS 0x00000011
#define NV_NBCI_FUNC_GETEVENTLIST 0x00000012
#define NV_NBCI_FUNC_CALLBACKS 0x00000013
#define NV_NBCI_FUNC_GETBACKLIGHT 0x00000014
#define NV_NBCI_FUNC_MSTL 0x00000015
#endif // NBCI_H_

22
src/common/inc/nvBldVer.h
View File

@@ -36,26 +36,26 @@
// and then checked back in. You cannot make changes to these sections without
// corresponding changes to the buildmeister script
#ifndef NV_BUILD_BRANCH
#define NV_BUILD_BRANCH r521_90
#define NV_BUILD_BRANCH r525_00
#endif
#ifndef NV_PUBLIC_BRANCH
#define NV_PUBLIC_BRANCH r521_90
#define NV_PUBLIC_BRANCH r525_00
#endif
#if defined(NV_LINUX) || defined(NV_BSD) || defined(NV_SUNOS)
#define NV_BUILD_BRANCH_VERSION "rel/gpu_drv/r520/r521_90-315"
#define NV_BUILD_CHANGELIST_NUM (31900380)
#define NV_BUILD_BRANCH_VERSION "rel/gpu_drv/r525/r525_00-154"
#define NV_BUILD_CHANGELIST_NUM (31993960)
#define NV_BUILD_TYPE "Official"
#define NV_BUILD_NAME "rel/gpu_drv/r520/r521_90-315"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (31900380)
#define NV_BUILD_NAME "rel/gpu_drv/r525/r525_00-154"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (31993960)
#else /* Windows builds */
#define NV_BUILD_BRANCH_VERSION "r521_90-15"
#define NV_BUILD_CHANGELIST_NUM (31900380)
#define NV_BUILD_BRANCH_VERSION "r525_00-178"
#define NV_BUILD_CHANGELIST_NUM (31990457)
#define NV_BUILD_TYPE "Official"
#define NV_BUILD_NAME "522.25"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (31900380)
#define NV_BUILD_BRANCH_BASE_VERSION R520
#define NV_BUILD_NAME "526.52"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (31990457)
#define NV_BUILD_BRANCH_BASE_VERSION R525
#endif
// End buildmeister python edited section

439
src/common/inc/nvCpuIntrinsics.h Normal file
View File

@@ -0,0 +1,439 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 1998,2015,2016 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __NV_CPU_INTRINSICS_H_
#define __NV_CPU_INTRINSICS_H_
#include <stdint.h>
#include "cpuopsys.h"
#include "nvtypes.h"
/////////////////////////////////////
// Page size
/////////////////////////////////////
#if defined(NV_UNIX) && !defined(NV_CPU_INTRINSICS_KERNEL)
// Page size is dynamic on all Unix systems
#include <unistd.h>
#define __NV_MEM_PAGE_SIZE_BYTES getpagesize()
#else
// And is static for all other known architectures.
#define __NV_MEM_PAGE_SIZE_BYTES 4096
#endif // defined(NV_UNIX)
#define __NV_MEM_PAGE_SIZE_MASK (__NV_MEM_PAGE_SIZE_BYTES - 1)
#define __NV_PAGE_PAD(x) \
(((x) + __NV_MEM_PAGE_SIZE_MASK) & ~(__NV_MEM_PAGE_SIZE_MASK))
/////////////////////////////////////
// Cache line size
/////////////////////////////////////
#if defined(NVCPU_PPC)
#define __NV_CACHE_LINE_BYTES 32
#else
#define __NV_CACHE_LINE_BYTES 64
#endif
/////////////////////////////////////
// Spin loop hint
/////////////////////////////////////
#if defined(NVCPU_X86_64)
// PAUSE (aka REP NOP) opcode is low-power on x86_64
#if defined(NV_GNU_INLINE_ASM)
#define NV_SPIN_LOOP_HINT() { \
asm(".byte 0xf3\n\t" \
".byte 0x90\n\t"); \
}
#else
#define NV_SPIN_LOOP_HINT() _mm_pause()
#endif
#elif defined(NVCPU_X86)
// PAUSE (aka REP NOP) opcode is low-power on P4's
#if defined(NV_GNU_INLINE_ASM)
#define NV_SPIN_LOOP_HINT() { \
asm(".byte 0xf3\n\t" \
".byte 0x90\n\t"); \
}
#else
#define NV_SPIN_LOOP_HINT() _mm_pause()
#endif
#elif defined(NVCPU_PPC)
#define NV_PPC_CACHE_LINE_SIZE_IN_BYTES 32
#define NV_PPC_CACHE_LINE_SIZE_IN_U32S 8
// Not implemented yet
#define NV_SPIN_LOOP_HINT()
#elif defined(NVCPU_FAMILY_ARM) || defined(NVCPU_PPC64LE)
// Not implemented yet
#define NV_SPIN_LOOP_HINT()
#else
#error Unknown CPU type
#endif
/////////////////////////////////////
// Atomic operations
/////////////////////////////////////
#if defined(__GNUC__) || defined(__clang__)
// Include stdbool.h to pick up a definition of false to use with the
// __atomic_* intrinsics below.
#if !defined(__cplusplus)
#include <stdbool.h>
#endif // !defined(__cplusplus)
// Sets a 32-bit variable to the specified value as an atomic operation.
// The function returns the initial value of the destination memory location.
static NV_FORCEINLINE int __NVatomicExchange(volatile int *location, int value)
{
return __sync_lock_test_and_set(location, value);
}
// Sets a pointer variable to the specified value as an atomic operation.
// The function returns the initial value of the destination memory location.
static NV_FORCEINLINE void* __NVatomicExchangePointer(void * volatile *location, void *value)
{
return __sync_lock_test_and_set(location, value);
}
// Performs an atomic compare-and-exchange operation on the specified values. The function compares two
// specified 32-bit values and exchanges with another 32-bit value based on the outcome of the comparison.
// The function returns the initial value of the destination memory location.
static NV_FORCEINLINE int __NVatomicCompareExchange(int volatile *location, int newValue, int oldValue)
{
return __sync_val_compare_and_swap(location, oldValue, newValue);
}
// Performs an atomic compare-and-exchange operation on the specified values. The function compares two
// specified 64-bit values and exchanges with another 64-bit value based on the outcome of the comparison.
// The function returns the initial value of the destination memory location.
static NV_FORCEINLINE NvS64 __NVatomicCompareExchange64(NvS64 volatile *location, NvS64 newValue, NvS64 oldValue)
{
#if NVCPU_IS_ARM && !defined(__clang__)
// GCC doesn't provided an ARMv7 64-bit sync-and-swap intrinsic, so define
// one using inline assembly.
NvU32 oldValLow = NvU64_LO32(oldValue);
NvU32 oldValHigh = NvU64_HI32(oldValue);
NvU32 newValLow = NvU64_LO32(newValue);
NvU32 newValHigh = NvU64_HI32(newValue);
NvU32 outValLow;
NvU32 outValHigh;
NvU32 res;
// The ldrexd and strexd instructions require use of an adjacent even/odd
// pair of registers. GCC supports quad-word register operands and
// modifiers to enable assignment of 64-bit values to two suitable 32-bit
// registers, but Clang does not. To work around this, explicitly request
// some suitable registers in the clobber list and manually shift the
// necessary data in/out of them as needed.
__asm__ __volatile__ (
"1: ldrexd r2, r3, [%[loc]]\n"
" mov %[res], #0\n"
" mov %[outLo], r2\n"
" mov %[outHi], r3\n"
" mov r2, %[newLo]\n"
" mov r3, %[newHi]\n"
" teq %[outLo], %[oldLo]\n"
" itt eq\n"
" teqeq %[outHi], %[oldHi]\n"
" strexdeq %[res], r2, r3, [%[loc]]\n"
" teq %[res], #0\n"
" bne 1b\n"
// Outputs
: [res] "=&r" (res),
[outLo] "=&r" (outValLow), [outHi] "=&r" (outValHigh),
"+Qo" (*location)
// Inputs
: [loc] "r" (location),
[oldLo] "r" (oldValLow), [oldHi] "r" (oldValHigh),
[newLo] "r" (newValLow), [newHi] "r" (newValHigh)
// Clobbers
: "memory", "cc", "r2", "r3");
__asm__ __volatile__ ("dmb" ::: "memory");
return (NvS64)(((NvU64)outValHigh << 32llu) | (NvU64)outValLow);
#else
__atomic_compare_exchange_n(location, &oldValue, newValue, false, __ATOMIC_SEQ_CST, __ATOMIC_SEQ_CST);
return oldValue;
#endif
}
// Performs an atomic compare-and-exchange operation on the specified values. The function compares two
// specified pointer values and exchanges with another pointer value based on the outcome of the comparison.
// The function returns the initial value of the destination memory location.
static NV_FORCEINLINE void* __NVatomicCompareExchangePointer(void * volatile *location, void *newValue, void *oldValue)
{
return __sync_val_compare_and_swap(location, oldValue, newValue);
}
// Increments (increases by one) the value of the specified 32-bit variable as an atomic operation.
// The function returns the resulting incremented value.
static NV_FORCEINLINE int __NVatomicIncrement(int volatile *location)
{
return __sync_add_and_fetch(location, 1);
}
// Decrements (decreases by one) the value of the specified 32-bit variable as an atomic operation.
// The function returns the resulting decremented value.
static NV_FORCEINLINE int __NVatomicDecrement(int volatile *location)
{
return __sync_sub_and_fetch(location, 1);
}
// Adds the values of the specified 32-bit variables as an atomic operation.
// The function returns the resulting added value.
static NV_FORCEINLINE int __NVatomicExchangeAdd(int volatile *location, int value)
{
return __sync_add_and_fetch(location, value);
}
#ifdef NV_CPU_QUERY_LSE_CAPS
/*
* Embedding hand coded instructions only for the inc/dec calls. These are the ones that
* get called very often. The __NVatomicCompareExchange() and other calls for example,
* are called only at init time, and a few times at most. So, keeping this hand-coding
* minimal, and to only the most used ones.
*
* Disassembly for reference:
* b820003e ldadd w0, w30, [x1]
* 0b1e0000 add w0, w0, w30
*
* x16, x17, x30 are added to the clobber list since there could be veneers that maybe
* generated.
*/
static NV_FORCEINLINE int __NVatomicIncrement_LSE(int volatile *location)
{
register int w0 asm ("w0") = 1;
register volatile int *x1 asm ("x1") = location;
asm volatile
(
".inst 0xb820003e \n"
"add w0, w0, w30"
: "+r" (w0), "+r" (x1)
: "r" (x1)
: "x16", "x17", "x30", "memory"
);
return w0;
}
static NV_FORCEINLINE int __NVatomicDecrement_LSE(int volatile *location)
{
register int w0 asm ("w0") = (int32_t)-1;
register volatile int *x1 asm ("x1") = location;
asm volatile
(
".inst 0xb820003e \n"
"add w0, w0, w30"
: "+r" (w0), "+r" (x1)
: "r" (x1)
: "x16", "x17", "x30", "memory"
);
return w0;
}
#endif
#else
#error undefined architecture
#endif
/////////////////////////////////////
// Bit scan operations
/////////////////////////////////////
// __NV_clz(mask) provides a generic count-leading-zeros. If "mask" is 0, then the return value is undefined.
// __NV_ctz(mask) provides a generic count-trailing-zeros. If "mask" is 0, then the return value is undefined.
//
// __NVbsfFirst(), __NVbsfNext(), __NVbsrFirst() and __NVbsrNext() are helper functions to implement
// generic bit scan operations over a 32 bit mask long the following template:
//
// for (__NVbsfFirst(&index, &mask, maskInit); mask; __NVbsfNext(&index, &mask)) { ... }
//
// These operations are implemented using gcc/MSVC builtins/intrinsics. A test program to verify the correct
// functionality of these routines is available at //sw/pvt/ddadap/bitscantest.c
//
// The scan process provides the next valid "index". In __NVbsfNext() the bit corresponding to the passed in
// (1 << index) will be masked out.
//
// bsf scan from the lsb to the msb, while bsr scans from the msb to the lsb.
//
// The use of inlines and defines below is dictated by insufficiencies of MSVC ...
#if defined (__GNUC__) || defined(__clang__)
static NV_FORCEINLINE int __NV_clz(unsigned int mask) {
return __builtin_clz(mask);
}
static NV_FORCEINLINE int __NV_ctz(unsigned int mask) {
return __builtin_ctz(mask);
}
static NV_FORCEINLINE int __NV_clzll(unsigned long long mask) {
return __builtin_clzll(mask);
}
static NV_FORCEINLINE int __NV_ctzll(unsigned long long mask) {
return __builtin_ctzll(mask);
}
#define __BitScanForward(_pindex, _mask) *((_pindex)) = __NV_ctz((_mask))
#define __BitScanReverse(_pindex, _mask) *((_pindex)) = 31 - __NV_clz((_mask))
#define __BitScanForward64(_pindex, _mask) *((_pindex)) = __NV_ctzll((_mask))
#define __BitScanReverse64(_pindex, _mask) *((_pindex)) = 63 - __NV_clzll((_mask))
#else
#error Unsupported compiler
#endif // MSVC_VER
#ifndef __BitScanForward64
// Implement bit scan forward for 64 bit using 32 bit instructions
static NV_FORCEINLINE void _BitScanForward64on32(unsigned int *index, NvU64 mask)
{
const unsigned int lowMask = (unsigned int)(mask & 0xFFFFFFFFULL);
if (lowMask != 0) {
__BitScanForward(index, lowMask);
} else {
const unsigned int highMask = (unsigned int)(mask >> 32);
__BitScanForward(index, highMask);
*index += 32;
}
}
#define __BitScanForward64(_pindex, _mask) _BitScanForward64on32((_pindex), (_mask))
#endif // __BitScanForward64
#ifndef __BitScanReverse64
// Implement bit scan reverse for 64 bit using 32 bit instructions
static NV_FORCEINLINE void _BitScanReverse64on32(unsigned int *index, NvU64 mask)
{
const unsigned int highMask = (unsigned int)(mask >> 32);
if (highMask != 0) {
__BitScanReverse(index, highMask);
*index += 32;
} else {
const unsigned int lowMask = (unsigned int)(mask & 0xFFFFFFFFULL);
__BitScanReverse(index, lowMask);
}
}
#define __BitScanReverse64(_pindex, _mask) _BitScanReverse64on32((_pindex), (_mask))
#endif // __BitScanReverse64
static NV_FORCEINLINE void __NVbsfFirst(unsigned int *pindex, unsigned int *pmask, unsigned int maskInit)
{
*pmask = maskInit;
__BitScanForward(pindex, maskInit);
}
static NV_FORCEINLINE void __NVbsfNext(unsigned int *pindex, unsigned int *pmask)
{
unsigned int index, mask;
index = *pindex;
mask = *pmask ^ (1ul << index);
*pmask = mask;
__BitScanForward(pindex, mask);
}
static NV_FORCEINLINE void __NVbsrFirst(unsigned int *pindex, unsigned int *pmask, unsigned int maskInit)
{
*pmask = maskInit;
__BitScanReverse(pindex, maskInit);
}
static NV_FORCEINLINE void __NVbsrNext(unsigned int *pindex, unsigned int *pmask)
{
unsigned int index, mask;
index = *pindex;
mask = *pmask ^ (1ul << index);
*pmask = mask;
__BitScanReverse(pindex, mask);
}
// Variations for 64 bit maks
static NV_FORCEINLINE void __NVbsfFirst64(unsigned int *pindex, NvU64 *pmask, NvU64 maskInit)
{
*pmask = maskInit;
__BitScanForward64(pindex, maskInit);
}
static NV_FORCEINLINE void __NVbsfNext64(unsigned int *pindex, NvU64 *pmask)
{
unsigned int index;
NvU64 mask;
index = *pindex;
mask = *pmask ^ (1ULL << index);
*pmask = mask;
__BitScanForward64(pindex, mask);
}
static NV_FORCEINLINE void __NVbsrFirst64(unsigned int *pindex, NvU64 *pmask, NvU64 maskInit)
{
*pmask = maskInit;
__BitScanReverse64(pindex, maskInit);
}
static NV_FORCEINLINE void __NVbsrNext64(unsigned int *pindex, NvU64 *pmask)
{
unsigned int index;
NvU64 mask;
index = *pindex;
mask = *pmask ^ (1ULL << index);
*pmask = mask;
__BitScanReverse64(pindex, mask);
}
#undef __BitScanForward
#undef __BitScanReverse
#undef __BitScanForward64
#undef __BitScanReverse64
#endif // __NV_CPU_INTRINSICS_H_

7
src/common/inc/nvPNPVendorIds.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2009 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2009-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -60,6 +60,7 @@ static const PNPVendorId PNPVendorIds[] =
{ "___", _VENDOR_NAME_ENTRY("Targa") },
{ "@@@", _VENDOR_NAME_ENTRY("Sangyo") },
{ "AAA", _VENDOR_NAME_ENTRY("Avolites Ltd") },
{ "AAC", _VENDOR_NAME_ENTRY("Acer") },
{ "ABC", _VENDOR_NAME_ENTRY("AboCom System Inc") },
{ "ABP", _VENDOR_NAME_ENTRY("Advanced System Products") },
@@ -109,6 +110,7 @@ static const PNPVendorId PNPVendorIds[] =
{ "ATT", _VENDOR_NAME_ENTRY("AT&T") },
{ "ATX", _VENDOR_NAME_ENTRY("Athenix") },
{ "AUO", _VENDOR_NAME_ENTRY("AU Optronics Corporation") },
{ "AUS", _VENDOR_NAME_ENTRY("Asustek Computer Inc") },
{ "AVI", _VENDOR_NAME_ENTRY("AIR") },
{ "AVO", _VENDOR_NAME_ENTRY("Avocent Corporation") },
{ "AZU", _VENDOR_NAME_ENTRY("Azura") },
@@ -249,6 +251,7 @@ static const PNPVendorId PNPVendorIds[] =
{ "HEI", _VENDOR_NAME_ENTRY("Hyundai") },
{ "HIT", _VENDOR_NAME_ENTRY("Hitachi/HINT") },
{ "HMX", _VENDOR_NAME_ENTRY("HUMAX Co., Ltd.") },
{ "HPN", _VENDOR_NAME_ENTRY("HP Inc.") },
{ "HSD", _VENDOR_NAME_ENTRY("HannStar Display Corp") },
{ "HSL", _VENDOR_NAME_ENTRY("Hansol") },
{ "HTC", _VENDOR_NAME_ENTRY("Hitachi") },
@@ -312,6 +315,7 @@ static const PNPVendorId PNPVendorIds[] =
{ "LCS", _VENDOR_NAME_ENTRY("Longshine Electronics") },
{ "LEF", _VENDOR_NAME_ENTRY("Leaf Systems") },
{ "LEN", _VENDOR_NAME_ENTRY("Lenovo Group Limited") },
{ "LGD", _VENDOR_NAME_ENTRY("LG Display") },
{ "LGE", _VENDOR_NAME_ENTRY("LG Electronics") },
{ "LKM", _VENDOR_NAME_ENTRY("Likom/LKM") },
{ "LNK", _VENDOR_NAME_ENTRY("Link Technologies") },
@@ -346,6 +350,7 @@ static const PNPVendorId PNPVendorIds[] =
{ "MMX", _VENDOR_NAME_ENTRY("MAG Technology") },
{ "MOR", _VENDOR_NAME_ENTRY("Morse Technology") },
{ "MSI", _VENDOR_NAME_ENTRY("Microstep") },
{ "MST", _VENDOR_NAME_ENTRY("MS Telematica") },
{ "MSV", _VENDOR_NAME_ENTRY("Mosgi") },
{ "MTC", _VENDOR_NAME_ENTRY("Mitac") },
{ "MTI", _VENDOR_NAME_ENTRY("Morse Technology") },

196
src/common/inc/nvSemaphoreCommon.h Normal file
View File

@@ -0,0 +1,196 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2019 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __NV_SEMAPHORE_H__
#define __NV_SEMAPHORE_H__
#include "nvtypes.h"
#include "nvCpuIntrinsics.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef volatile struct {
NvU32 payload;
NvU32 reportValue;
NvU64 timer;
} NvReportSemaphore32;
typedef volatile struct {
NvU64 reportValue;
NvU64 timer;
} NvReportSemaphore64;
typedef volatile union {
NvReportSemaphore32 sema32;
NvReportSemaphore64 sema64;
} NvReportSemaphore;
/*
* These structures can't change size. They map to the GPU and other driver
* components expect the same size.
*/
ct_assert(sizeof(NvReportSemaphore32) == 16);
ct_assert(sizeof(NvReportSemaphore64) == 16);
ct_assert(sizeof(NvReportSemaphore) == 16);
/*
* Pre-Volta GPUs can only read/write a 32-bit semaphore. Rather than try to
* use multiple semaphore writes to emulate a full 64-bit write, which is prone
* to race conditions when the value wraps, derive the full 64-bit value by
* comparing the current GPU-accessible value with the the last value written by
* the CPU or submitted to be written by the GPU, which is stashed in the
* timestamp field of the semaphore by the CPU in both these cases.
*/
static inline void NvTimeSemFermiSetMaxSubmitted(
NvReportSemaphore32 *report,
const NvU64 value)
{
NvU64 oldValue =
(NvU64)__NVatomicCompareExchange64((volatile NvS64 *)&report->timer,
0, 0);
// Atomically set report->timer to max(value, report->time).
while (oldValue < value) {
const NvU64 prevValue =
(NvU64)__NVatomicCompareExchange64((volatile NvS64 *)&report->timer,
(NvS64)value,
(NvS64)oldValue);
if (prevValue == oldValue) {
// The specified value was set. Done.
nvAssert(report->timer >= value);
break;
}
oldValue = prevValue;
}
}
static inline NvU64 NvTimeSemFermiGetPayload(
NvReportSemaphore32 *report)
{
// The ordering of the two operations below is critical. Other threads
// may be submitting GPU work that modifies the semaphore value, or
// modifying it from the CPU themselves. Both of those operations first
// set the 64-bit max submitted/timer value, then modify or submit work
// to modify the 32-bit payload value. Consider this hypothetical timeline
// if the order of operations below is reversed:
//
// thread1:
// -SetMaxSubmitted(0x1);
// -report->payload = 0x1;
//
// thread2:
// -Reads 0x1 from report->timer
//
// thread1:
// -SetMaxSubmitted(0x7fffffff);
// -report->payload = 0x7fffffff;
// -SetMaxSubmitted(0x100000000);
// -report->payload = 0x00000000;
//
// thread2:
// -Reads 0x0 from report->payload
//
// The logic below would see 0 (payload) is less than 1 (max submitted) and
// determine a wrap is outstanding, subtract one from the high 32-bits of
// the max submitted value (0x00000000 - 0x1), overflow, and return the
// current 64-bit value as 0xffffffff00000000 when the correct value is
// 0x100000000. To avoid this, we must read the payload prior to reading
// the max submitted value from the timer field. The logic can correctly
// adjust the max submitted value back down if a wrap occurs between these
// two operations, but has no way to bump the max submitted value up if a
// wrap occurs with the opposite ordering.
NvU64 current = report->payload;
// Use an atomic exchange to ensure the 64-bit read is atomic even on 32-bit
// CPUs.
NvU64 submitted = (NvU64)
__NVatomicCompareExchange64((volatile NvS64 *)&report->timer, 0ll, 0ll);
nvAssert(!(current & 0xFFFFFFFF00000000ull));
// The value is monotonically increasing, and differ by no more than
// 2^31 - 1. Hence, if the low word of the submitted value is less
// than the low word of the current value, exactly one 32-bit wrap
// occurred between the current value and the most recently
// submitted value. Walk back the high word to match the value
// associated with the current GPU-visible value.
if ((submitted & 0xFFFFFFFFull) < current) {
submitted -= 0x100000000ull;
}
current |= (submitted & 0xFFFFFFFF00000000ull);
return current;
}
static inline void NvTimeSemFermiSetPayload(
NvReportSemaphore32 *report,
const NvU64 payload)
{
// First save the actual value to the reserved/timer bits
NvTimeSemFermiSetMaxSubmitted(report, payload);
// Then write the low bits to the GPU-accessible semaphore value.
report->payload = (NvU32)(payload & 0xFFFFFFFFULL);
}
/*
* Volta and up.
*/
static inline NvU64 NvTimeSemVoltaGetPayload(
NvReportSemaphore64 *report)
{
return (NvU64)
__NVatomicCompareExchange64((volatile NvS64 *)&report->reportValue,
0, 0);
}
static inline void NvTimeSemVoltaSetPayload(
NvReportSemaphore64 *report,
const NvU64 payload)
{
NvU64 oldPayload = 0;
while (NV_TRUE) {
NvU64 prevPayload = (NvU64)
__NVatomicCompareExchange64((volatile NvS64 *)&report->reportValue,
(NvS64)payload, (NvS64)oldPayload);
if (prevPayload == oldPayload) {
break;
}
nvAssert(prevPayload < payload);
oldPayload = prevPayload;
}
}
#ifdef __cplusplus
};
#endif
#endif /* __NV_SEMAPHORE_H__ */

2
src/common/inc/nvUnixVersion.h
View File

@@ -4,7 +4,7 @@
#if defined(NV_LINUX) || defined(NV_BSD) || defined(NV_SUNOS) || defined(NV_VMWARE) || defined(NV_QNX) || defined(NV_INTEGRITY) || \
(defined(RMCFG_FEATURE_PLATFORM_GSP) && RMCFG_FEATURE_PLATFORM_GSP == 1)
#define NV_VERSION_STRING "520.56.06"
#define NV_VERSION_STRING "525.53"
#else

2
src/common/inc/nvctassert.h
View File

@@ -83,7 +83,7 @@
* e.g. msvc compiler:
* error C2118: negative subscript or subscript is too large
* e.g. gcc 2.95.3:
* size of array `_compile_time_assertion_failed_in_line_555' is negative
* size of array '_compile_time_assertion_failed_in_line_555' is negative
*
* In case the condition 'b' is not constant, the msvc compiler throws
* an error:

75
src/common/inc/nvhybridacpi.h Normal file
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@@ -0,0 +1,75 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 1993 - 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef NVHYBRID_ACPI_H
#define NVHYBRID_ACPI_H
#if defined(__cplusplus)
extern "C"
{
#endif // defined(__cplusplus)
/*****************************************************************************
*
* Module: nvAcpi.h
*
* Description:
* Header file for ACPI related things, including Hybrid and MXM
*
******************************************************************************/
#define NVHG_FUNC_SUPPORT 0x00000000 // Supported Sub-Functions
#define NVHG_FUNC_HYBRIDCAPS 0x00000001 // Capabilities & Mutex
#define NVHG_FUNC_POLICYSELECT 0x00000002 // Query Policy Selector Status
#define NVHG_FUNC_POWERCONTROL 0x00000003 // dGPU Power Control
#define NVHG_FUNC_PLATPOLICY 0x00000004 // Query/Set Platform Policy
#define NVHG_FUNC_DISPLAYSTATUS 0x00000005 // Get Display & Hot-Key information
#define NVHG_FUNC_MDTL 0x00000006 // Display Toggle List
#define NVHG_FUNC_HCSMBLIST 0x00000007 // List of available addresses (MCP7x Desktop Only)
#define NVHG_FUNC_HCSMBADDR 0x00000008 // Returns the SMBus address (MCP7x Desktop Only)
#define NVHG_FUNC_HCREADBYTE 0x00000009 // Read a byte from the EC (MCP7x Desktop Only)
#define NVHG_FUNC_HCSENDBYTE 0x0000000a // Send a command byte to the EC (MCP7x Desktop Only)
#define NVHG_FUNC_HCGETSTATUS 0x0000000b // Querying the status of the Adapters' Hybrid EC after an SMbus Host Notify (MCP7x Desktop Only)
#define NVHG_FUNC_HCTRIGDDC 0x0000000c // Trigger reading a DDC block (Montevina Hybrid & MCP7x)
#define NVHG_FUNC_HCGETDDC 0x0000000d // Get the DDC block (Montevina Hybrid & MCP7x)
#define NVHG_FUNC_GETMEMTABLE 0x0000000e // Get the system memory configuration
#define NVHG_FUNC_GETMEMCFG 0x0000000f // Get the system video memory settings
#define NVHG_FUNC_GETOBJBYTYPE 0x00000010 // Get the firmware object
#define NVHG_FUNC_GETALLOBJS 0x00000011 // Get the directory and all objects
#define NVHG_FUNC_GETEVENTLIST 0x00000012 // Get the List of required Event Notifiers and their meaning
#define NVHG_FUNC_CALLBACKS 0x00000013 // Get the list of system-required callbacks
#define NVHG_FUNC_GETBACKLIGHT 0x00000014 // Get the backlight table
#define NVHG_ERROR_SUCCESS 0x00000000 // Success
#define NVHG_ERROR_UNSPECIFIED 0x80000001 // Generic unspecified error code
#define NVHG_ERROR_UNSUPPORTED 0x80000002 // FunctionCode or SubFunctionCode not supported by this system
#define NVHG_ERROR_PARM_INVALID 0x80000003 // Parameter is invalid (i.e. start page beyond end of buffer)
#if defined(__cplusplus)
} // extern "C"
#endif // defined(__cplusplus)
#endif // _NVHYBRID_ACPI_H_

122
src/common/inc/nvop.h Normal file
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@@ -0,0 +1,122 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef NVOP_H
#define NVOP_H
#define NVOP_REVISION_ID 0x00000100
// subfunction 0 is common use: NV_ACPI_ALL_FUNC_SUPPORT
// #define NVOP_FUNC_SUPPORT 0x00000000 // Bit list of supported functions*
#define NVOP_FUNC_DISPLAYSTATUS 0x00000005 // Query the Display Hot-Key**
#define NVOP_FUNC_MDTL 0x00000006 // Query Display Toggle List**
#define NVOP_FUNC_HCSMBADDR 0x00000007 // Get the SBIOS SMBus address for hybrid uController
#define NVOP_FUNC_GETOBJBYTYPE 0x00000010 // Get the Firmware Object*
#define NVOP_FUNC_GETALLOBJS 0x00000011 // Get the directory and all Objects *
#define NVOP_FUNC_OPTIMUSCAPS 0x0000001A // Optimus Capabilities***
#define NVOP_FUNC_OPTIMUSFLAG 0x0000001B // Update GPU MultiFunction State to sbios
// * Required if any other functions are used.
// ** Required for Optimus-specific display hotkey functionality
// *** Required for Optimus-specific dGPU subsystem power control
// Function 1A: OPTIMUSCAPS
// Args
#define NVOP_FUNC_OPTIMUSCAPS_FLAGS 0:0
#define NVOP_FUNC_OPTIMUSCAPS_FLAGS_ABSENT 0x00000000
#define NVOP_FUNC_OPTIMUSCAPS_FLAGS_PRESENT 0x00000001
#define NVOP_FUNC_OPTIMUSCAPS_CFG_SPACE_OWNER_TARGET 1:1
#define NVOP_FUNC_OPTIMUSCAPS_CFG_SPACE_OWNER_TARGET_SBIOS 0x00000000
#define NVOP_FUNC_OPTIMUSCAPS_CFG_SPACE_OWNER_TARGET_DRIVER 0x00000001
#define NVOP_FUNC_OPTIMUSCAPS_CFG_SPACE_OWNER_WR_EN 2:2
#define NVOP_FUNC_OPTIMUSCAPS_CFG_SPACE_OWNER_WR_EN_FALSE 0x00000000
#define NVOP_FUNC_OPTIMUSCAPS_CFG_SPACE_OWNER_WR_EN_TRUE 0x00000001
#define NVOP_FUNC_OPTIMUSCAPS_POWER_CONTROL 25:24
#define NVOP_FUNC_OPTIMUSCAPS_POWER_CONTROL_DONOT_POWER_DOWN_DGPU 0x00000002
#define NVOP_FUNC_OPTIMUSCAPS_POWER_CONTROL_POWER_DOWN_DGPU 0x00000003
// Returns
#define NVOP_FUNC_OPTIMUSCAPS_OPTIMUS_STATE 0:0
#define NVOP_FUNC_OPTIMUSCAPS_OPTIMUS_STATE_DISABLED 0x00000000
#define NVOP_FUNC_OPTIMUSCAPS_OPTIMUS_STATE_ENABLED 0x00000001
#define NVOP_FUNC_OPTIMUSCAPS_DGPU_POWER 4:3
#define NVOP_FUNC_OPTIMUSCAPS_DGPU_POWER_OFF 0x00000000
#define NVOP_FUNC_OPTIMUSCAPS_DGPU_POWER_RESERVED1 0x00000001
#define NVOP_FUNC_OPTIMUSCAPS_DGPU_POWER_RESERVED2 0x00000002
#define NVOP_FUNC_OPTIMUSCAPS_DGPU_POWER_STABILIZED 0x00000003
#define NVOP_FUNC_OPTIMUSCAPS_DGPU_HOTPLUG_CAPABILITIES 6:6
#define NVOP_FUNC_OPTIMUSCAPS_DGPU_HOTPLUG_CAPABILITIES_COCONNECTED 0x00000001
#define NVOP_FUNC_OPTIMUSCAPS_DGPU_MUXED_DDC 7:7
#define NVOP_FUNC_OPTIMUSCAPS_DGPU_MUXED_DDC_FALSE 0x00000000
#define NVOP_FUNC_OPTIMUSCAPS_DGPU_MUXED_DDC_TRUE 0x00000001
#define NVOP_FUNC_OPTIMUSCAPS_CFG_SPACE_OWNER_ACTUAL 8:8
#define NVOP_FUNC_OPTIMUSCAPS_CFG_SPACE_OWNER_ACTUAL_SBIOS 0x00000000
#define NVOP_FUNC_OPTIMUSCAPS_CFG_SPACE_OWNER_ACTUAL_DRIVER 0x00000001
#define NVOP_FUNC_OPTIMUSCAPS_OPTIMUS_CAPABILITIES 26:24
#define NVOP_FUNC_OPTIMUSCAPS_OPTIMUS_CAPABILITIES_ABSENT 0x00000000
#define NVOP_FUNC_OPTIMUSCAPS_OPTIMUS_CAPABILITIES_DYNAMIC_POWER_CONTROL 0x00000001
#define NVOP_FUNC_OPTIMUSCAPS_OPTIMUS_HDAUDIO_CAPABILITIES 28:27
#define NVOP_FUNC_OPTIMUSCAPS_OPTIMUS_HDAUDIO_CAPABILITIES_ABSENT 0x00000000
#define NVOP_FUNC_OPTIMUSCAPS_OPTIMUS_HDAUDIO_CAPABILITIES_DISABLED 0x00000001
#define NVOP_FUNC_OPTIMUSCAPS_OPTIMUS_HDAUDIO_CAPABILITIES_PRESENT 0x00000002
// Function 1B: OPTIMUSFLAG
// Args
#define NVOP_FUNC_OPTIMUSFLAG_AUDIOCODEC_CONTROL 0:0
#define NVOP_FUNC_OPTIMUSFLAG_AUDIOCODEC_CONTROL_DISABLE 0x00000000
#define NVOP_FUNC_OPTIMUSFLAG_AUDIOCODEC_CONTROL_ENABLE 0x00000001
#define NVOP_FUNC_OPTIMUSFLAG_AUDIOCODEC_STATECHANGE_REQUEST 1:1
#define NVOP_FUNC_OPTIMUSFLAG_AUDIOCODEC_STATECHANGE_REQUEST_IGNORE 0x00000000
#define NVOP_FUNC_OPTIMUSFLAG_AUDIOCODEC_STATECHANGE_REQUEST_EXECUTE 0x00000001
#define NVOP_FUNC_OPTIMUSFLAG_APPLICATIONS_COUNT 9:2
#define NVOP_FUNC_OPTIMUSFLAG_APPLICATIONS_COUNT_CHANGE_REQUEST 10:10
#define NVOP_FUNC_OPTIMUSFLAG_APPLICATIONS_COUNT_CHANGE_REQUEST_IGNORE 0x000000000
#define NVOP_FUNC_OPTIMUSFLAG_APPLICATIONS_COUNT_CHANGE_REQUEST_EXECUTE 0x000000001
// Function 1B: OPTIMUSFLAG
// return
#define NVOP_RET_OPTIMUSFLAG_AUDIOCODEC_STATE 0:0
#define NVOP_RET_OPTIMUSFLAG_AUDIOCODEC_STATE_DISABLE 0x00000000
#define NVOP_RET_OPTIMUSFLAG_AUDIOCODEC_STATE_ENABLE 0x00000001
#define NVOP_RET_OPTIMUSFLAG_POLICY 3:2
#define NVOP_RET_OPTIMUSFLAG_POLICY_GPU_POWEROFF 0x00000000
#define NVOP_RET_OPTIMUSFLAG_POLICY_GPU_POWERON 0x00000001
#define NVOP_RET_OPTIMUSFLAG_POLICYCHANGE_REQUEST 4:4
#define NVOP_RET_OPTIMUSFLAG_POLICYCHANGE_REQUEST_IGNORE 0x00000000
#define NVOP_RET_OPTIMUSFLAG_POLICYCHANGE_REQUEST_EXECUTE 0x00000001
#define NVOP_RET_OPTIMUSFLAG_FORCE_GPU_POLICY 6:5
#define NVOP_RET_OPTIMUSFLAG_FORCE_GPU_POLICY_OPTIMUS 0x00000000
#define NVOP_RET_OPTIMUSFLAG_FORCE_GPU_POLICY_IGPU 0x00000001
#define NVOP_RET_OPTIMUSFLAG_FORCE_GPU_POLICY_DGPU 0x00000002
#define NVOP_RET_OPTIMUSFLAG_FORCE_GPU_REQUEST 7:7
#define NVOP_RET_OPTIMUSFLAG_FORCE_GPU_REQUEST_IGNORE 0x00000000
#define NVOP_RET_OPTIMUSFLAG_FORCE_GPU_REQUEST_EXECUTE 0x00000001
#endif // NVOP_H

40
src/common/inc/pex.h Normal file
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@@ -0,0 +1,40 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2012-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef PEX_H
#define PEX_H
#define PEX_REVISION_ID 0x00000002
// subfunction 0 is common use: NV_ACPI_ALL_FUNC_SUPPORT
// #define PEX_FUNC_GETSUPPORTFUNCTION 0x00000000 // Get supported function
#define PEX_FUNC_GETSLOTINFO 0x00000001 // Get PCI Express Slot Information
#define PEX_FUNC_GETSLOTNUMBER 0x00000002 // Get PCI Express Slot Number
#define PEX_FUNC_GETVENDORTOKENID 0x00000003 // Get PCI Express Vendor Specific Token ID strings
#define PEX_FUNC_GETPCIBUSCAPS 0x00000004 // Get PCI Express Root Bus Capabilities
#define PEX_FUNC_IGNOREPCIBOOTCONFIG 0x00000005 // Indication to OS that PCI Boot config can be ignored
#define PEX_FUNC_GETLTRLATENCY 0x00000006 // Get PCI Express Latency Tolerance Reporting Info
#define PEX_FUNC_NAMEPCIDEVICE 0x00000007 // Get name of PCI or PCIE device
#define PEX_FUNC_SETLTRLATENCY 0x00000008 // Set PCI Express Latency Tolerance Reporting Values
#endif // PEX_H

32
src/common/inc/swref/published/ada/ad102/dev_bus.h Normal file
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@@ -0,0 +1,32 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef ad102_dev_nv_bus_h
#define ad102_dev_nv_bus_h
#define NV_PBUS_SW_SCRATCH(i) (0x00001400+(i)*4) /* RW-4A */
#define NV_PBUS_SW_SCRATCH__SIZE_1 64 /* */
#define NV_PBUS_SW_SCRATCH_FIELD 31:0 /* RWIVF */
#define NV_PBUS_SW_SCRATCH_FIELD_INIT 0x00000000 /* RWI-V */
#endif // ad102_dev_nv_bus_h

39
src/common/inc/swref/published/ada/ad102/dev_bus_addendum.h Normal file
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@@ -0,0 +1,39 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef ad102_dev_nv_bus_addendum_h
#define ad102_dev_nv_bus_addendum_h
// Scratch bits for Global EROT Grant scratch bits
#define NV_PBUS_SW_GLOBAL_EROT_GRANT NV_PBUS_SW_SCRATCH(0)
#define NV_PBUS_SW_GLOBAL_EROT_GRANT_VALID 3:3
#define NV_PBUS_SW_GLOBAL_EROT_GRANT_VALID_YES 1
#define NV_PBUS_SW_GLOBAL_EROT_GRANT_VALID_NO 0
#define NV_PBUS_SW_GLOBAL_EROT_GRANT_REQUEST 4:4
#define NV_PBUS_SW_GLOBAL_EROT_GRANT_REQUEST_SET 1
#define NV_PBUS_SW_GLOBAL_EROT_GRANT_REQUEST_CLEAR 0
#define NV_PBUS_SW_GLOBAL_EROT_GRANT_ALLOW 5:5
#define NV_PBUS_SW_GLOBAL_EROT_GRANT_ALLOW_YES 1
#define NV_PBUS_SW_GLOBAL_EROT_GRANT_ALLOW_NO 0
#endif // ad102_dev_nv_bus_addendum_h

88
src/common/inc/swref/published/disp/v03_00/dev_disp.h
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@@ -23,45 +23,51 @@
#ifndef __v03_00_dev_disp_h__
#define __v03_00_dev_disp_h__
#define NV_PDISP_CHN_NUM_CORE 0 /* */
#define NV_PDISP_CHN_NUM_WIN(i) (1+(i)) /* */
#define NV_PDISP_CHN_NUM_WIN__SIZE_1 32 /* */
#define NV_PDISP_CHN_NUM_WINIM(i) (33+(i)) /* */
#define NV_PDISP_CHN_NUM_WINIM__SIZE_1 32 /* */
#define NV_PDISP_CHN_NUM_CURS(i) (73+(i)) /* */
#define NV_PDISP_CHN_NUM_CURS__SIZE_1 8 /* */
#define NV_PDISP_FE_HW_SYS_CAP_HEAD_EXISTS(i) (0+(i)):(0+(i)) /* R--VF */
#define NV_PDISP_FE_HW_SYS_CAP_HEAD_EXISTS__SIZE_1 8 /* */
#define NV_PDISP_FE_HW_SYS_CAP_HEAD_EXISTS_YES 0x00000001 /* R---V */
#define NV_PDISP_FE_SW 0x00640FFF:0x00640000 /* RW--D */
#define NV_PDISP_SF_USER_0 0x006F03FF:0x006F0000 /* RW--D */
#define NV_UDISP_HASH_BASE 0x00000000 /* */
#define NV_UDISP_HASH_LIMIT 0x00001FFF /* */
#define NV_UDISP_OBJ_MEM_BASE 0x00002000 /* */
#define NV_UDISP_OBJ_MEM_LIMIT 0x0000FFFF /* */
#define NV_UDISP_HASH_TBL_CLIENT_ID (1*32+13):(1*32+0) /* RWXVF */
#define NV_UDISP_HASH_TBL_INSTANCE (1*32+24):(1*32+14) /* RWXUF */
#define NV_UDISP_HASH_TBL_CHN (1*32+31):(1*32+25) /* RWXUF */
#define NV_DMA_TARGET_NODE (0*32+1):(0*32+0) /* RWXVF */
#define NV_DMA_TARGET_NODE_PHYSICAL_NVM 0x00000001 /* RW--V */
#define NV_DMA_TARGET_NODE_PHYSICAL_PCI 0x00000002 /* RW--V */
#define NV_DMA_TARGET_NODE_PHYSICAL_PCI_COHERENT 0x00000003 /* RW--V */
#define NV_DMA_ACCESS (0*32+2):(0*32+2) /* RWXVF */
#define NV_DMA_ACCESS_READ_ONLY 0x00000000 /* RW--V */
#define NV_DMA_ACCESS_READ_AND_WRITE 0x00000001 /* RW--V */
#define NV_DMA_KIND (0*32+20):(0*32+20) /* RWXVF */
#define NV_DMA_KIND_PITCH 0x00000000 /* RW--V */
#define NV_DMA_KIND_BLOCKLINEAR 0x00000001 /* RW--V */
#define NV_DMA_ADDRESS_BASE_LO (1*32+31):(1*32+0) /* RWXUF */
#define NV_DMA_ADDRESS_BASE_HI (2*32+6):(2*32+0) /* RWXUF */
#define NV_DMA_ADDRESS_LIMIT_LO (3*32+31):(3*32+0) /* RWXUF */
#define NV_DMA_ADDRESS_LIMIT_HI (4*32+6):(4*32+0) /* RWXUF */
#define NV_DMA_SIZE 20 /* */
#define NV_UDISP_FE_CHN_ASSY_BASEADR_CORE 0x00680000 /* */
#define NV_UDISP_FE_CHN_ARMED_BASEADR_CORE (0x00680000+32768) /* */
#define NV_UDISP_FE_CHN_ASSY_BASEADR_WIN(i) ((0x00690000+(i)*4096)) /* */
#define NV_UDISP_FE_CHN_ASSY_BASEADR_WINIM(i) ((0x00690000+((i+32)*4096))) /* */
#define NV_UDISP_FE_CHN_ASSY_BASEADR_CURS(i) (0x006D8000+(i)*4096) /* RW-4A */
#define NV_UDISP_FE_CHN_ASSY_BASEADR(i) ((i)>0?(((0x00690000+(i-1)*4096))):0x00680000) /* */
#define NV_UDISP_FE_CHN_ASSY_BASEADR__SIZE_1 81 /* */
#define NV_PDISP_CHN_NUM_CORE 0 /* */
#define NV_PDISP_CHN_NUM_WIN(i) (1+(i)) /* */
#define NV_PDISP_CHN_NUM_WIN__SIZE_1 32 /* */
#define NV_PDISP_CHN_NUM_WINIM(i) (33+(i)) /* */
#define NV_PDISP_CHN_NUM_WINIM__SIZE_1 32 /* */
#define NV_PDISP_CHN_NUM_CURS(i) (73+(i)) /* */
#define NV_PDISP_CHN_NUM_CURS__SIZE_1 8 /* */
#define NV_PDISP_FE_HW_SYS_CAP_HEAD_EXISTS(i) (0+(i)):(0+(i)) /* R--VF */
#define NV_PDISP_FE_HW_SYS_CAP_HEAD_EXISTS__SIZE_1 8 /* */
#define NV_PDISP_FE_HW_SYS_CAP_HEAD_EXISTS_YES 0x00000001 /* R---V */
#define NV_PDISP_FE_SW 0x00640FFF:0x00640000 /* RW--D */
#define NV_PDISP_SF_USER_0 0x006F03FF:0x006F0000 /* RW--D */
#define NV_UDISP_HASH_BASE 0x00000000 /* */
#define NV_UDISP_HASH_LIMIT 0x00001FFF /* */
#define NV_UDISP_OBJ_MEM_BASE 0x00002000 /* */
#define NV_UDISP_OBJ_MEM_LIMIT 0x0000FFFF /* */
#define NV_UDISP_HASH_TBL_CLIENT_ID (1*32+13):(1*32+0) /* RWXVF */
#define NV_UDISP_HASH_TBL_INSTANCE (1*32+24):(1*32+14) /* RWXUF */
#define NV_UDISP_HASH_TBL_CHN (1*32+31):(1*32+25) /* RWXUF */
#define NV_DMA_TARGET_NODE (0*32+1):(0*32+0) /* RWXVF */
#define NV_DMA_TARGET_NODE_PHYSICAL_NVM 0x00000001 /* RW--V */
#define NV_DMA_TARGET_NODE_PHYSICAL_PCI 0x00000002 /* RW--V */
#define NV_DMA_TARGET_NODE_PHYSICAL_PCI_COHERENT 0x00000003 /* RW--V */
#define NV_DMA_ACCESS (0*32+2):(0*32+2) /* RWXVF */
#define NV_DMA_ACCESS_READ_ONLY 0x00000000 /* RW--V */
#define NV_DMA_ACCESS_READ_AND_WRITE 0x00000001 /* RW--V */
#define NV_DMA_KIND (0*32+20):(0*32+20) /* RWXVF */
#define NV_DMA_KIND_PITCH 0x00000000 /* RW--V */
#define NV_DMA_KIND_BLOCKLINEAR 0x00000001 /* RW--V */
#define NV_DMA_ADDRESS_BASE_LO (1*32+31):(1*32+0) /* RWXUF */
#define NV_DMA_ADDRESS_BASE_HI (2*32+6):(2*32+0) /* RWXUF */
#define NV_DMA_ADDRESS_LIMIT_LO (3*32+31):(3*32+0) /* RWXUF */
#define NV_DMA_ADDRESS_LIMIT_HI (4*32+6):(4*32+0) /* RWXUF */
#define NV_DMA_SIZE 20 /* */
#define NV_UDISP_FE_CHN_ASSY_BASEADR_CORE 0x00680000 /* */
#define NV_UDISP_FE_CHN_ARMED_BASEADR_CORE (0x00680000+32768) /* */
#define NV_UDISP_FE_CHN_ASSY_BASEADR_WIN(i) ((0x00690000+(i)*4096)) /* */
#define NV_UDISP_FE_CHN_ASSY_BASEADR_WINIM(i) ((0x00690000+((i+32)*4096))) /* */
#define NV_UDISP_FE_CHN_ASSY_BASEADR_CURS(i) (0x006D8000+(i)*4096) /* RW-4A */
#define NV_UDISP_FE_CHN_ASSY_BASEADR(i) ((i)>0?(((0x00690000+(i-1)*4096))):0x00680000) /* */
#define NV_UDISP_FE_CHN_ASSY_BASEADR__SIZE_1 81 /* */
#define NV_PDISP_RG_DPCA(i) (0x00616330+(i)*2048) /* R--4A */
#define NV_PDISP_RG_DPCA__SIZE_1 8 /* */
#define NV_PDISP_RG_DPCA_LINE_CNT 15:0 /* R--UF */
#define NV_PDISP_RG_DPCA_FRM_CNT 31:16 /* R--UF */
#define NV_PDISP_FE_FLIPLOCK 0x0061206C /* RW-4R */
#define NV_PDISP_FE_FLIPLOCK_LSR_MIN_TIME 23:0 /* RWIVF */
#endif // __v03_00_dev_disp_h__

4
src/common/inc/swref/published/nv_arch.h
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@@ -103,6 +103,10 @@
#define GPU_IMPLEMENTATION_AD104 0x04
#define GPU_IMPLEMENTATION_AD106 0x06
#define GPU_IMPLEMENTATION_AD107 0x07
#define GPU_IMPLEMENTATION_T124 0x00
#define GPU_IMPLEMENTATION_T132 0x00
#define GPU_IMPLEMENTATION_T210 0x00

7
src/common/inc/swref/published/nv_ref.h
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@@ -149,6 +149,13 @@
#define NV_PMC_BOOT_42_ARCHITECTURE 28:24 /* */
#define NV_PMC_BOOT_42_CHIP_ID 28:20 /* R-XVF */
#define NV_PMC_BOOT_42_ARCHITECTURE_TU100 0x00000016 /* */
#define NV_PMC_BOOT_42_ARCHITECTURE_GA100 0x00000017 /* */
#define NV_PMC_BOOT_42_ARCHITECTURE_GH100 0x00000018 /* */
#define NV_PMC_BOOT_42_ARCHITECTURE_AD100 0x00000019 /* */
#define NV_PMC_BOOT_42_CHIP_ID_GA100 0x00000170 /* */
/* dev_arapb_misc.h */
#define NV_PAPB_MISC_GP_HIDREV_CHIPID 15:8 /* ----F */
#define NV_PAPB_MISC_GP_HIDREV_MAJORREV 7:4 /* ----F */

1
src/common/inc/swref/published/nvswitch/lr10/dev_minion_ip.h
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@@ -24,7 +24,6 @@
#ifndef __lr10_dev_minion_ip_h__
#define __lr10_dev_minion_ip_h__
/* This file is autogenerated. Do not edit */
// did not include the regs that weren't approved for Tegra
#define NV_CMINION_FALCON_CG2 0x00000134 /* RWI4R */
#define NV_CMINION_FALCON_CG2_SLCG 17:1 /* */
#define NV_CMINION_FALCON_CG2_SLCG_ENABLED 0 /* */

2
src/common/inc/swref/published/nvswitch/lr10/dev_soe_ip.h
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@@ -284,7 +284,7 @@
#define NV_SOE_FALCON_MAILBOX1 0x0044 /* RW-4R */
#define NV_SOE_FALCON_MAILBOX1_DATA 31:0 /* RWIVF */
#define NV_SOE_FALCON_MAILBOX1_DATA_INIT 0x00000000 /* RWI-V */
// check if all of these should be added
#define NV_SOE_FALCON_CPUCTL 0x0100 /* RW-4R */
#define NV_SOE_FALCON_CPUCTL_IINVAL 0:0 /* -WXVF */
#define NV_SOE_FALCON_CPUCTL_IINVAL_TRUE 0x00000001 /* -W--V */

7
src/common/inc/swref/published/nvswitch/lr10/dev_soe_ip_addendum.h
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@@ -23,13 +23,6 @@
#ifndef __lr10_dev_soe_ip_addendum_h__
#define __lr10_dev_soe_ip_addendum_h__
//
// The detail description about each of the mutex can be found in
// <branch>/drivers/resman/arch/nvalloc/common/inc/nv_mutex.h
//
// Enums in the following file will also need to be updated:
// <branch>/drivers/nvswitch/common/inc/soemutexreservation.h
//
#define NV_SOE_MUTEX_DEFINES \
NV_MUTEX_ID_SOE_EMEM_ACCESS, \

108
src/common/inc/swref/published/nvswitch/ls10/dev_cpr_ip.h Normal file
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@@ -0,0 +1,108 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the Software),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __ls10_dev_cpr_ip_h__
#define __ls10_dev_cpr_ip_h__
#define NV_CPR_SYS_NVLW_CG1 0x00000110 /* RW-4R */
#define NV_CPR_SYS_NVLW_CG1_SLCG 0:0 /* RWEVF */
#define NV_CPR_SYS_NVLW_CG1_SLCG_ENABLED 0x00000000 /* RW--V */
#define NV_CPR_SYS_NVLW_CG1_SLCG_DISABLED 0x00000001 /* RWE-V */
#define NV_CPR_SYS_NVLW_CG1_SLCG__PROD 0x00000000 /* RW--V */
#define NV_CPR_SYS_INTR_CTRL(i) (0x00000130+(i)*0x4) /* RW-4A */
#define NV_CPR_SYS_INTR_CTRL__SIZE_1 3 /* */
#define NV_CPR_SYS_INTR_CTRL_MESSAGE 31:0 /* RWEVF */
#define NV_CPR_SYS_INTR_CTRL_MESSAGE_INIT 0x00000000 /* RWE-V */
#define NV_CPR_SYS_INTR_RETRIGGER(i) (0x00000150+(i)*0x4) /* RW-4A */
#define NV_CPR_SYS_INTR_RETRIGGER__SIZE_1 3 /* */
#define NV_CPR_SYS_INTR_RETRIGGER_TRIGGER 0:0 /* RWEVF */
#define NV_CPR_SYS_INTR_RETRIGGER_TRIGGER__ONWRITE "oneToSet" /* */
#define NV_CPR_SYS_INTR_RETRIGGER_TRIGGER_INIT 0x00000000 /* RWE-V */
#define NV_CPR_SYS_INTR_RETRIGGER_TRIGGER_TRUE 0x00000001 /* RW--V */
#define NV_CPR_SYS_NVLW_INTR_0_STATUS 0x000001a0 /* R--4R */
#define NV_CPR_SYS_NVLW_INTR_0_STATUS_CPR_INTR 0:0 /* R-EVF */
#define NV_CPR_SYS_NVLW_INTR_0_STATUS_CPR_INTR_INIT 0x00000000 /* R-E-V */
#define NV_CPR_SYS_NVLW_INTR_0_STATUS_INTR0 31:31 /* R-EVF */
#define NV_CPR_SYS_NVLW_INTR_0_STATUS_INTR0_INIT 0x00000000 /* R-E-V */
#define NV_CPR_SYS_NVLW_INTR_1_STATUS 0x000001a4 /* R--4R */
#define NV_CPR_SYS_NVLW_INTR_1_STATUS_CPR_INTR 0:0 /* R-EVF */
#define NV_CPR_SYS_NVLW_INTR_1_STATUS_CPR_INTR_INIT 0x00000000 /* R-E-V */
#define NV_CPR_SYS_NVLW_INTR_1_STATUS_INTR1 31:31 /* R-EVF */
#define NV_CPR_SYS_NVLW_INTR_1_STATUS_INTR1_INIT 0x00000000 /* R-E-V */
#define NV_CPR_SYS_NVLW_INTR_2_STATUS 0x000001a8 /* R--4R */
#define NV_CPR_SYS_NVLW_INTR_2_STATUS_CPR_INTR 0:0 /* R-EVF */
#define NV_CPR_SYS_NVLW_INTR_2_STATUS_CPR_INTR_INIT 0x00000000 /* R-E-V */
#define NV_CPR_SYS_NVLW_INTR_2_STATUS_INTR2 31:31 /* R-EVF */
#define NV_CPR_SYS_NVLW_INTR_2_STATUS_INTR2_INIT 0x00000000 /* R-E-V */
#define NV_CPR_SYS_NVLW_INTR_0_MASK 0x000001c0 /* RW-4R */
#define NV_CPR_SYS_NVLW_INTR_0_MASK_CPR_INTR 0:0 /* RWEVF */
#define NV_CPR_SYS_NVLW_INTR_0_MASK_CPR_INTR_ENABLE 0x00000001 /* RW--V */
#define NV_CPR_SYS_NVLW_INTR_0_MASK_CPR_INTR_DISABLE 0x00000000 /* RWE-V */
#define NV_CPR_SYS_NVLW_INTR_0_MASK_INTR0 1:1 /* RWEVF */
#define NV_CPR_SYS_NVLW_INTR_0_MASK_INTR0_ENABLE 0x00000001 /* RW--V */
#define NV_CPR_SYS_NVLW_INTR_0_MASK_INTR0_DISABLE 0x00000000 /* RWE-V */
#define NV_CPR_SYS_NVLW_INTR_1_MASK 0x000001c4 /* RW-4R */
#define NV_CPR_SYS_NVLW_INTR_1_MASK_CPR_INTR 0:0 /* RWEVF */
#define NV_CPR_SYS_NVLW_INTR_1_MASK_CPR_INTR_ENABLE 0x00000001 /* RW--V */
#define NV_CPR_SYS_NVLW_INTR_1_MASK_CPR_INTR_DISABLE 0x00000000 /* RWE-V */
#define NV_CPR_SYS_NVLW_INTR_1_MASK_INTR1 1:1 /* RWEVF */
#define NV_CPR_SYS_NVLW_INTR_1_MASK_INTR1_ENABLE 0x00000001 /* RW--V */
#define NV_CPR_SYS_NVLW_INTR_1_MASK_INTR1_DISABLE 0x00000000 /* RWE-V */
#define NV_CPR_SYS_NVLW_INTR_2_MASK 0x000001c8 /* RW-4R */
#define NV_CPR_SYS_NVLW_INTR_2_MASK_CPR_INTR 0:0 /* RWEVF */
#define NV_CPR_SYS_NVLW_INTR_2_MASK_CPR_INTR_ENABLE 0x00000001 /* RW--V */
#define NV_CPR_SYS_NVLW_INTR_2_MASK_CPR_INTR_DISABLE 0x00000000 /* RWE-V */
#define NV_CPR_SYS_NVLW_INTR_2_MASK_INTR2 1:1 /* RWEVF */
#define NV_CPR_SYS_NVLW_INTR_2_MASK_INTR2_ENABLE 0x00000001 /* RW--V */
#define NV_CPR_SYS_NVLW_INTR_2_MASK_INTR2_DISABLE 0x00000000 /* RWE-V */
#define NV_CPR_SYS_ERR_STATUS_0 0x00000200 /* RW-4R */
#define NV_CPR_SYS_ERR_STATUS_0_ENGINE_RESET_ERR 0:0 /* RWIVF */
#define NV_CPR_SYS_ERR_STATUS_0_ENGINE_RESET_ERR__ONWRITE "oneToClear" /* */
#define NV_CPR_SYS_ERR_STATUS_0_ENGINE_RESET_ERR_NONE 0x00000000 /* RWI-V */
#define NV_CPR_SYS_ERR_STATUS_0_ENGINE_RESET_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_CPR_SYS_ERR_LOG_EN_0 0x00000204 /* RW-4R */
#define NV_CPR_SYS_ERR_LOG_EN_0_ENGINE_RESET_ERR 0:0 /* RWEVF */
#define NV_CPR_SYS_ERR_LOG_EN_0_ENGINE_RESET_ERR__PROD 0x00000001 /* RW--V */
#define NV_CPR_SYS_ERR_LOG_EN_0_ENGINE_RESET_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_CPR_SYS_ERR_LOG_EN_0_ENGINE_RESET_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_CPR_SYS_ERR_FATAL_REPORT_EN_0 0x00000208 /* RW-4R */
#define NV_CPR_SYS_ERR_FATAL_REPORT_EN_0_ENGINE_RESET_ERR 0:0 /* RWEVF */
#define NV_CPR_SYS_ERR_FATAL_REPORT_EN_0_ENGINE_RESET_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_CPR_SYS_ERR_FATAL_REPORT_EN_0_ENGINE_RESET_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_CPR_SYS_ERR_NON_FATAL_REPORT_EN_0 0x0000020c /* RW-4R */
#define NV_CPR_SYS_ERR_NON_FATAL_REPORT_EN_0_ENGINE_RESET_ERR 0:0 /* RWEVF */
#define NV_CPR_SYS_ERR_NON_FATAL_REPORT_EN_0_ENGINE_RESET_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_CPR_SYS_ERR_NON_FATAL_REPORT_EN_0_ENGINE_RESET_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_CPR_SYS_ERR_CORRECTABLE_REPORT_EN_0 0x00000210 /* RW-4R */
#define NV_CPR_SYS_ERR_CORRECTABLE_REPORT_EN_0_ENGINE_RESET_ERR 0:0 /* RWEVF */
#define NV_CPR_SYS_ERR_CORRECTABLE_REPORT_EN_0_ENGINE_RESET_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_CPR_SYS_ERR_CORRECTABLE_REPORT_EN_0_ENGINE_RESET_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_CPR_SYS_ERR_CONTAIN_EN_0 0x00000214 /* RW-4R */
#define NV_CPR_SYS_ERR_CONTAIN_EN_0_ENGINE_RESET_ERR 0:0 /* RWEVF */
#define NV_CPR_SYS_ERR_CONTAIN_EN_0_ENGINE_RESET_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_CPR_SYS_ERR_CONTAIN_EN_0_ENGINE_RESET_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_CPR_SYS_ERR_FIRST_0 0x0000021c /* RW-4R */
#define NV_CPR_SYS_ERR_FIRST_0_ENGINE_RESET_ERR 0:0 /* RWIVF */
#define NV_CPR_SYS_ERR_FIRST_0_ENGINE_RESET_ERR__ONWRITE "oneToClear" /* */
#define NV_CPR_SYS_ERR_FIRST_0_ENGINE_RESET_ERR_NONE 0x00000000 /* RWI-V */
#define NV_CPR_SYS_ERR_FIRST_0_ENGINE_RESET_ERR_CLEAR 0x00000001 /* RW--V */
#endif // __ls10_dev_cpr_ip_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the Software),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __ls10_dev_ctrl_ip_h__
#define __ls10_dev_ctrl_ip_h__
/* This file is autogenerated. Do not edit */
#define NV_CTRL 0x0001FFFF:0x00000000 /* RW--D */
#define NV_CTRL_CPU_INTR_TOP(i) (0x00013400+(i)*4) /* R--4A */
#define NV_CTRL_CPU_INTR_TOP__SIZE_1 64 /* */
#define NV_CTRL_CPU_INTR_TOP_VALUE 31:0 /* R--VF */
#define NV_CTRL_CPU_INTR_TOP_EN_SET(i) (0x00013800+(i)*4) /* RW-4A */
#define NV_CTRL_CPU_INTR_TOP_EN_SET__SIZE_1 64 /* */
#define NV_CTRL_CPU_INTR_TOP_EN_SET_VALUE 31:0 /* RWIVF */
#define NV_CTRL_CPU_INTR_TOP_EN_SET_VALUE_INIT 0x00000000 /* R-I-V */
#define NV_CTRL_CPU_INTR_TOP_EN_CLEAR(i) (0x00013C00+(i)*4) /* RW-4A */
#define NV_CTRL_CPU_INTR_TOP_EN_CLEAR__SIZE_1 64 /* */
#define NV_CTRL_CPU_INTR_TOP_EN_CLEAR_VALUE 31:0 /* RWIVF */
#define NV_CTRL_CPU_INTR_TOP_EN_CLEAR_VALUE_INIT 0x00000000 /* R-I-V */
#define NV_CTRL_CPU_INTR_LEAF(i) (0x00014000+(i)*4) /* RW-4A */
#define NV_CTRL_CPU_INTR_LEAF__SIZE_1 1024 /* */
#define NV_CTRL_CPU_INTR_LEAF_VALUE 31:0 /* RWIVF */
#define NV_CTRL_CPU_INTR_LEAF_VALUE_INIT 0x00000000 /* R-I-V */
#define NV_CTRL_CPU_INTR_LEAF_ARRAY_SIZE_PER_FN 16 /* */
#define NV_CTRL_CPU_INTR_LEAF_EN_SET(i) (0x00018000+(i)*4) /* RW-4A */
#define NV_CTRL_CPU_INTR_LEAF_EN_SET__SIZE_1 1024 /* */
#define NV_CTRL_CPU_INTR_LEAF_EN_SET_VALUE 31:0 /* RWIVF */
#define NV_CTRL_CPU_INTR_LEAF_EN_SET_VALUE_INIT 0x00000000 /* R-I-V */
#define NV_CTRL_CPU_INTR_LEAF_EN_CLEAR(i) (0x0001C000+(i)*4) /* RW-4A */
#define NV_CTRL_CPU_INTR_LEAF_EN_CLEAR__SIZE_1 1024 /* */
#define NV_CTRL_CPU_INTR_LEAF_EN_CLEAR_VALUE 31:0 /* RWIVF */
#define NV_CTRL_CPU_INTR_LEAF_EN_CLEAR_VALUE_INIT 0x00000000 /* R-I-V */
#define NV_CTRL_CPU_INTR_LEAF_TRIGGER(i) (0x00006C00+(i)*4) /* -W-4A */
#define NV_CTRL_CPU_INTR_LEAF_TRIGGER__SIZE_1 64 /* */
#define NV_CTRL_CPU_INTR_LEAF_TRIGGER_VECTOR 11:0 /* -WXVF */
#define NV_CTRL_PRI_CTRL_CG1 0x00006A00 /* RW-4R */
#define NV_CTRL_PRI_CTRL_CG1_SLCG 2:1 /* */
#define NV_CTRL_PRI_CTRL_CG1_SLCG_ENABLED 0x00000000 /* */
#define NV_CTRL_PRI_CTRL_CG1_SLCG_DISABLED 0x00000003 /* */
#define NV_CTRL_PRI_CTRL_CG1_SLCG__PROD 0x00000000 /* */
#define NV_CTRL_PRI_CTRL_CG1_SLCG_CTRLPRI 1:1 /* RWIVF */
#define NV_CTRL_PRI_CTRL_CG1_SLCG_CTRLPRI_ENABLED 0x00000000 /* RW--V */
#define NV_CTRL_PRI_CTRL_CG1_SLCG_CTRLPRI_DISABLED 0x00000001 /* RWI-V */
#define NV_CTRL_PRI_CTRL_CG1_SLCG_CTRLPRI__PROD 0x00000000 /* RW--V */
#define NV_CTRL_PRI_CTRL_CG1_SLCG_MSIX 2:2 /* RWIVF */
#define NV_CTRL_PRI_CTRL_CG1_SLCG_MSIX_ENABLED 0x00000000 /* RW--V */
#define NV_CTRL_PRI_CTRL_CG1_SLCG_MSIX_DISABLED 0x00000001 /* RWI-V */
#define NV_CTRL_PRI_CTRL_CG1_SLCG_MSIX__PROD 0x00000000 /* RW--V */
#endif // __ls10_dev_ctrl_ip_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the Software),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __ls10_dev_ctrl_ip_addendum_h__
#define __ls10_dev_ctrl_ip_addendum_h__
//
// GIN _LEAF() mapping to IP blocks
// Refer to "Table 74. Laguna interrupt sources" in Laguna Seca IAS
//
#define NV_CTRL_CPU_INTR_NVLW_FATAL_IDX 0
#define NV_CTRL_CPU_INTR_NVLW_NON_FATAL_IDX 1
#define NV_CTRL_CPU_INTR_NVLW_CORRECTABLE_IDX 2
#define NV_CTRL_CPU_INTR_NPG_FATAL_IDX 5
#define NV_CTRL_CPU_INTR_NPG_NON_FATAL_IDX 6
#define NV_CTRL_CPU_INTR_NPG_CORRECTABLE_IDX 7
#define NV_CTRL_CPU_INTR_NXBAR_FATAL_IDX 8
#define NV_CTRL_CPU_INTR_UNITS_IDX 9
#define NV_CTRL_CPU_INTR_NVLW_FATAL NV_CTRL_CPU_INTR_LEAF(NV_CTRL_CPU_INTR_NVLW_FATAL_IDX)
#define NV_CTRL_CPU_INTR_NVLW_FATAL_MASK 15:0
#define NV_CTRL_CPU_INTR_NVLW_NON_FATAL NV_CTRL_CPU_INTR_LEAF(NV_CTRL_CPU_INTR_NVLW_NON_FATAL_IDX)
#define NV_CTRL_CPU_INTR_NVLW_NON_FATAL_MASK 15:0
#define NV_CTRL_CPU_INTR_NVLW_CORRECTABLE NV_CTRL_CPU_INTR_LEAF(NV_CTRL_CPU_INTR_NVLW_CORRECTABLE_IDX)
#define NV_CTRL_CPU_INTR_NVLW_CORRECTABLE_MASK 15:0
#define NV_CTRL_CPU_INTR_NPG_FATAL NV_CTRL_CPU_INTR_LEAF(NV_CTRL_CPU_INTR_NPG_FATAL_IDX)
#define NV_CTRL_CPU_INTR_NPG_FATAL_MASK 15:0
#define NV_CTRL_CPU_INTR_NPG_NON_FATAL NV_CTRL_CPU_INTR_LEAF(NV_CTRL_CPU_INTR_NPG_NON_FATAL_IDX)
#define NV_CTRL_CPU_INTR_NPG_NON_FATAL_MASK 15:0
#define NV_CTRL_CPU_INTR_NPG_CORRECTABLE NV_CTRL_CPU_INTR_LEAF(NV_CTRL_CPU_INTR_NPG_CORRECTABLE_IDX)
#define NV_CTRL_CPU_INTR_NPG_CORRECTABLE_MASK 15:0
#define NV_CTRL_CPU_INTR_NXBAR_FATAL NV_CTRL_CPU_INTR_LEAF(NV_CTRL_CPU_INTR_NXBAR_FATAL_IDX)
#define NV_CTRL_CPU_INTR_NXBAR_FATAL_MASK 2:0
#define NV_CTRL_CPU_INTR_UNITS NV_CTRL_CPU_INTR_LEAF(NV_CTRL_CPU_INTR_UNITS_IDX)
#define NV_CTRL_CPU_INTR_UNITS_PMGR_HOST 0:0
#define NV_CTRL_CPU_INTR_UNITS_PTIMER 1:1
#define NV_CTRL_CPU_INTR_UNITS_PTIMER_ALARM 2:2
#define NV_CTRL_CPU_INTR_UNITS_SEC0_INTR0_0 7:7
#define NV_CTRL_CPU_INTR_UNITS_SEC0_NOTIFY_0 8:8
#define NV_CTRL_CPU_INTR_UNITS_SOE_SHIM_ILLEGAL_OP 11:11
#define NV_CTRL_CPU_INTR_UNITS_SOE_SHIM_FLUSH 12:12
#define NV_CTRL_CPU_INTR_UNITS_XTL_CPU 13:13
#define NV_CTRL_CPU_INTR_UNITS_XAL_EP 14:14
#define NV_CTRL_CPU_INTR_UNITS_PRIV_RING 15:15
#define NV_CTRL_CPU_INTR_UNITS_FSP 16:16
#endif // __ls10_dev_ctrl_ip_addendum_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the Software),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __ls10_dev_falcon_v4_h__
#define __ls10_dev_falcon_v4_h__
#define NV_PFALCON_FALCON_EXE_PRIV_LEVEL_MASK 0x0000028c /* RW-4R */
#define NV_PFALCON_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
#define NV_PFALCON_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
#define NV_PFALCON_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
#define NV_PFALCON_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
#define NV_PFALCON_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
#define NV_PFALCON_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
#define NV_PFALCON_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
#define NV_PFALCON_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
#define NV_PFALCON_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
#define NV_PFALCON_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
#define NV_PFALCON_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
#define NV_PFALCON_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
#define NV_PFALCON_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
#define NV_PFALCON_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
#define NV_PFALCON_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
#define NV_PFALCON_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
#define NV_PFALCON_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
#define NV_PFALCON_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
#define NV_PFALCON_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
#define NV_PFALCON_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
#define NV_PFALCON_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
#define NV_PFALCON_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
#define NV_PFALCON_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
#define NV_PFALCON_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
#define NV_PFALCON_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
#define NV_PFALCON_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
#define NV_PFALCON_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
#define NV_PFALCON_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
#define NV_PFALCON_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
#define NV_PFALCON_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
#define NV_PFALCON_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
#define NV_PFALCON_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
#define NV_PFALCON_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
#define NV_PFALCON_FALCON_EXE_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
#define NV_PFALCON_FALCON_EXE_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
#define NV_PFALCON_FALCON_EXE_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
#define NV_PFALCON_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
#define NV_PFALCON_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
#define NV_PFALCON_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
#define NV_PFALCON_FALCON_EXE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
#define NV_PFALCON_FALCON_EXE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
#define NV_PFALCON_FALCON_EXE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
#define NV_PFALCON_FALCON_EXE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
#define NV_PFALCON_FALCON_EXE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
#define NV_PFALCON_FALCON_EXE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
#define NV_PFALCON_FALCON_EXE_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
#define NV_PFALCON_FALCON_EXE_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
#define NV_PFALCON_FALCON_RESET_PRIV_LEVEL_MASK 0x000003c4 /* RW-4R */
#define NV_PFALCON_FALCON_RESET_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
#define NV_PFALCON_FALCON_RESET_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
#define NV_PFALCON_FALCON_RESET_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
#define NV_PFALCON_FALCON_RESET_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
#define NV_PFALCON_FALCON_RESET_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
#define NV_PFALCON_FALCON_RESET_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
#define NV_PFALCON_FALCON_RESET_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
#define NV_PFALCON_FALCON_RESET_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
#define NV_PFALCON_FALCON_RESET_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
#define NV_PFALCON_FALCON_RESET_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
#define NV_PFALCON_FALCON_RESET_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
#define NV_PFALCON_FALCON_RESET_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
#define NV_PFALCON_FALCON_RESET_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
#define NV_PFALCON_FALCON_RESET_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
#define NV_PFALCON_FALCON_RESET_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
#define NV_PFALCON_FALCON_RESET_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
#define NV_PFALCON_FALCON_RESET_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
#define NV_PFALCON_FALCON_RESET_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
#define NV_PFALCON_FALCON_RESET_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
#define NV_PFALCON_FALCON_RESET_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
#define NV_PFALCON_FALCON_RESET_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
#define NV_PFALCON_FALCON_RESET_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
#define NV_PFALCON_FALCON_RESET_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
#define NV_PFALCON_FALCON_RESET_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
#define NV_PFALCON_FALCON_RESET_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
#define NV_PFALCON_FALCON_RESET_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
#define NV_PFALCON_FALCON_RESET_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
#define NV_PFALCON_FALCON_RESET_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
#define NV_PFALCON_FALCON_RESET_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
#define NV_PFALCON_FALCON_RESET_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
#define NV_PFALCON_FALCON_RESET_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
#define NV_PFALCON_FALCON_RESET_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
#define NV_PFALCON_FALCON_RESET_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
#define NV_PFALCON_FALCON_RESET_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
#define NV_PFALCON_FALCON_RESET_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
#define NV_PFALCON_FALCON_RESET_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
#define NV_PFALCON_FALCON_RESET_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
#define NV_PFALCON_FALCON_RESET_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
#define NV_PFALCON_FALCON_RESET_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
#define NV_PFALCON_FALCON_RESET_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
#define NV_PFALCON_FALCON_RESET_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
#define NV_PFALCON_FALCON_RESET_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
#define NV_PFALCON_FALCON_RESET_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
#define NV_PFALCON_FALCON_RESET_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
#define NV_PFALCON_FALCON_RESET_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
#define NV_PFALCON_FALCON_RESET_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
#define NV_PFALCON_FALCON_RESET_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
#define NV_PFALCON_FALCON_IRQSSET 0x00000000 /* -W-4R */
#define NV_PFALCON_FALCON_IRQSSET_GPTMR 0:0 /* -WXVF */
#define NV_PFALCON_FALCON_IRQSSET_GPTMR_SET 0x00000001 /* -W--V */
#define NV_PFALCON_FALCON_IRQSSET_WDTMR 1:1 /* -WXVF */
#define NV_PFALCON_FALCON_IRQSSET_WDTMR_SET 0x00000001 /* -W--V */
#define NV_PFALCON_FALCON_IRQSSET_MTHD 2:2 /* -WXVF */
#define NV_PFALCON_FALCON_IRQSSET_MTHD_SET 0x00000001 /* -W--V */
#define NV_PFALCON_FALCON_IRQSSET_CTXSW 3:3 /* -WXVF */
#define NV_PFALCON_FALCON_IRQSSET_CTXSW_SET 0x00000001 /* -W--V */
#define NV_PFALCON_FALCON_IRQSSET_HALT 4:4 /* -WXVF */
#define NV_PFALCON_FALCON_IRQSSET_HALT_SET 0x00000001 /* -W--V */
#define NV_PFALCON_FALCON_IRQSSET_EXTERR 5:5 /* -WXVF */
#define NV_PFALCON_FALCON_IRQSSET_EXTERR_SET 0x00000001 /* -W--V */
#define NV_PFALCON_FALCON_IRQSSET_SWGEN0 6:6 /* -WXVF */
#define NV_PFALCON_FALCON_IRQSSET_SWGEN0_SET 0x00000001 /* -W--V */
#define NV_PFALCON_FALCON_IRQSSET_SWGEN1 7:7 /* -WXVF */
#define NV_PFALCON_FALCON_IRQSSET_SWGEN1_SET 0x00000001 /* -W--V */
#define NV_PFALCON_FALCON_IRQSSET_EXT 15:8 /* -WXVF */
#define NV_PFALCON_FALCON_IRQSSET_DMA 16:16 /* -WXVF */
#define NV_PFALCON_FALCON_IRQSSET_DMA_SET 0x00000001 /* -W--V */
#define NV_PFALCON_FALCON_IRQSSET_SHA 17:17 /* -WXVF */
#define NV_PFALCON_FALCON_IRQSSET_SHA_SET 0x00000001 /* -W--V */
#define NV_PFALCON_FALCON_IRQSSET_MEMERR 18:18 /* -WXVF */
#define NV_PFALCON_FALCON_IRQSSET_MEMERR_SET 0x00000001 /* -W--V */
#define NV_PFALCON_FALCON_IRQSSET_CTXSW_ERROR 19:19 /* -WXVF */
#define NV_PFALCON_FALCON_IRQSSET_CTXSW_ERROR_SET 0x00000001 /* -W--V */
#define NV_PFALCON_FALCON_IRQSSET_ICD 22:22 /* -WXVF */
#define NV_PFALCON_FALCON_IRQSSET_ICD_SET 0x00000001 /* -W--V */
#define NV_PFALCON_FALCON_IRQSSET_IOPMP 23:23 /* -WXVF */
#define NV_PFALCON_FALCON_IRQSSET_IOPMP_SET 0x00000001 /* -W--V */
#define NV_PFALCON_FALCON_IRQSSET_CORE_MISMATCH 24:24 /* -WXVF */
#define NV_PFALCON_FALCON_IRQSSET_CORE_MISMATCH_SET 0x00000001 /* -W--V */
#define NV_PFALCON_FALCON_IRQSCLR 0x00000004 /* -W-4R */
#define NV_PFALCON_FALCON_IRQSCLR_GPTMR 0:0 /* -WXVF */
#define NV_PFALCON_FALCON_IRQSCLR_GPTMR_SET 0x00000001 /* -W--V */
#define NV_PFALCON_FALCON_IRQSCLR_WDTMR 1:1 /* -WXVF */
#define NV_PFALCON_FALCON_IRQSCLR_WDTMR_SET 0x00000001 /* -W--V */
#define NV_PFALCON_FALCON_IRQSCLR_MTHD 2:2 /* -WXVF */
#define NV_PFALCON_FALCON_IRQSCLR_MTHD_SET 0x00000001 /* -W--V */
#define NV_PFALCON_FALCON_IRQSCLR_CTXSW 3:3 /* -WXVF */
#define NV_PFALCON_FALCON_IRQSCLR_CTXSW_SET 0x00000001 /* -W--V */
#define NV_PFALCON_FALCON_IRQSCLR_HALT 4:4 /* -WXVF */
#define NV_PFALCON_FALCON_IRQSCLR_HALT_SET 0x00000001 /* -W--V */
#define NV_PFALCON_FALCON_IRQSCLR_EXTERR 5:5 /* -WXVF */
#define NV_PFALCON_FALCON_IRQSCLR_EXTERR_SET 0x00000001 /* -W--V */
#define NV_PFALCON_FALCON_IRQSCLR_SWGEN0 6:6 /* -WXVF */
#define NV_PFALCON_FALCON_IRQSCLR_SWGEN0_SET 0x00000001 /* -W--V */
#define NV_PFALCON_FALCON_IRQSCLR_SWGEN1 7:7 /* -WXVF */
#define NV_PFALCON_FALCON_IRQSCLR_SWGEN1_SET 0x00000001 /* -W--V */
#define NV_PFALCON_FALCON_IRQSCLR_EXT 15:8 /* */
#define NV_PFALCON_FALCON_IRQSCLR_DMA 16:16 /* -WXVF */
#define NV_PFALCON_FALCON_IRQSCLR_DMA_SET 0x00000001 /* -W--V */
#define NV_PFALCON_FALCON_IRQSCLR_SHA 17:17 /* -WXVF */
#define NV_PFALCON_FALCON_IRQSCLR_SHA_SET 0x00000001 /* -W--V */
#define NV_PFALCON_FALCON_IRQSCLR_MEMERR 18:18 /* -WXVF */
#define NV_PFALCON_FALCON_IRQSCLR_MEMERR_SET 0x00000001 /* -W--V */
#define NV_PFALCON_FALCON_IRQSCLR_CTXSW_ERROR 19:19 /* -WXVF */
#define NV_PFALCON_FALCON_IRQSCLR_CTXSW_ERROR_SET 0x00000001 /* -W--V */
#define NV_PFALCON_FALCON_IRQSCLR_ICD 22:22 /* -WXVF */
#define NV_PFALCON_FALCON_IRQSCLR_ICD_SET 0x00000001 /* -W--V */
#define NV_PFALCON_FALCON_IRQSCLR_IOPMP 23:23 /* -WXVF */
#define NV_PFALCON_FALCON_IRQSCLR_IOPMP_SET 0x00000001 /* -W--V */
#define NV_PFALCON_FALCON_IRQSCLR_CORE_MISMATCH 24:24 /* -WXVF */
#define NV_PFALCON_FALCON_IRQSCLR_CORE_MISMATCH_SET 0x00000001 /* -W--V */
#define NV_PFALCON_FALCON_IRQSTAT 0x00000008 /* R--4R */
#define NV_PFALCON_FALCON_IRQSTAT_GPTMR 0:0 /* R-IVF */
#define NV_PFALCON_FALCON_IRQSTAT_GPTMR_FALSE 0x00000000 /* R-I-V */
#define NV_PFALCON_FALCON_IRQSTAT_GPTMR_TRUE 0x00000001 /* R---V */
#define NV_PFALCON_FALCON_IRQSTAT_WDTMR 1:1 /* R-IVF */
#define NV_PFALCON_FALCON_IRQSTAT_WDTMR_FALSE 0x00000000 /* R-I-V */
#define NV_PFALCON_FALCON_IRQSTAT_WDTMR_TRUE 0x00000001 /* R---V */
#define NV_PFALCON_FALCON_IRQSTAT_MTHD 2:2 /* R-IVF */
#define NV_PFALCON_FALCON_IRQSTAT_MTHD_FALSE 0x00000000 /* R-I-V */
#define NV_PFALCON_FALCON_IRQSTAT_MTHD_TRUE 0x00000001 /* R---V */
#define NV_PFALCON_FALCON_IRQSTAT_CTXSW 3:3 /* R-IVF */
#define NV_PFALCON_FALCON_IRQSTAT_CTXSW_FALSE 0x00000000 /* R-I-V */
#define NV_PFALCON_FALCON_IRQSTAT_CTXSW_TRUE 0x00000001 /* R---V */
#define NV_PFALCON_FALCON_IRQSTAT_HALT 4:4 /* R-IVF */
#define NV_PFALCON_FALCON_IRQSTAT_HALT_FALSE 0x00000000 /* R-I-V */
#define NV_PFALCON_FALCON_IRQSTAT_HALT_TRUE 0x00000001 /* R---V */
#define NV_PFALCON_FALCON_IRQSTAT_EXTERR 5:5 /* R-IVF */
#define NV_PFALCON_FALCON_IRQSTAT_EXTERR_FALSE 0x00000000 /* R-I-V */
#define NV_PFALCON_FALCON_IRQSTAT_EXTERR_TRUE 0x00000001 /* R---V */
#define NV_PFALCON_FALCON_IRQSTAT_SWGEN0 6:6 /* R-IVF */
#define NV_PFALCON_FALCON_IRQSTAT_SWGEN0_FALSE 0x00000000 /* R-I-V */
#define NV_PFALCON_FALCON_IRQSTAT_SWGEN0_TRUE 0x00000001 /* R---V */
#define NV_PFALCON_FALCON_IRQSTAT_SWGEN1 7:7 /* R-IVF */
#define NV_PFALCON_FALCON_IRQSTAT_SWGEN1_FALSE 0x00000000 /* R-I-V */
#define NV_PFALCON_FALCON_IRQSTAT_SWGEN1_TRUE 0x00000001 /* R---V */
#define NV_PFALCON_FALCON_IRQSTAT_EXT 15:8 /* */
#define NV_PFALCON_FALCON_IRQSTAT_DMA 16:16 /* R-IVF */
#define NV_PFALCON_FALCON_IRQSTAT_DMA_TRUE 0x00000001 /* R---V */
#define NV_PFALCON_FALCON_IRQSTAT_DMA_FALSE 0x00000000 /* R-I-V */
#define NV_PFALCON_FALCON_IRQSTAT_SHA 17:17 /* R-IVF */
#define NV_PFALCON_FALCON_IRQSTAT_SHA_TRUE 0x00000001 /* R---V */
#define NV_PFALCON_FALCON_IRQSTAT_SHA_FALSE 0x00000000 /* R-I-V */
#define NV_PFALCON_FALCON_IRQSTAT_MEMERR 18:18 /* R-IVF */
#define NV_PFALCON_FALCON_IRQSTAT_MEMERR_TRUE 0x00000001 /* R---V */
#define NV_PFALCON_FALCON_IRQSTAT_MEMERR_FALSE 0x00000000 /* R-I-V */
#define NV_PFALCON_FALCON_IRQSTAT_CTXSW_ERROR 19:19 /* R-XVF */
#define NV_PFALCON_FALCON_IRQSTAT_CTXSW_ERROR_TRUE 0x00000001 /* R---V */
#define NV_PFALCON_FALCON_IRQSTAT_CTXSW_ERROR_FALSE 0x00000000 /* R---V */
#define NV_PFALCON_FALCON_IRQSTAT_ICD 22:22 /* R-XVF */
#define NV_PFALCON_FALCON_IRQSTAT_ICD_TRUE 0x00000001 /* R---V */
#define NV_PFALCON_FALCON_IRQSTAT_ICD_FALSE 0x00000000 /* R---V */
#define NV_PFALCON_FALCON_IRQSTAT_IOPMP 23:23 /* R-XVF */
#define NV_PFALCON_FALCON_IRQSTAT_IOPMP_TRUE 0x00000001 /* R---V */
#define NV_PFALCON_FALCON_IRQSTAT_IOPMP_FALSE 0x00000000 /* R---V */
#define NV_PFALCON_FALCON_IRQSTAT_CORE_MISMATCH 24:24 /* R-XVF */
#define NV_PFALCON_FALCON_IRQSTAT_CORE_MISMATCH_TRUE 0x00000001 /* R---V */
#define NV_PFALCON_FALCON_IRQSTAT_CORE_MISMATCH_FALSE 0x00000000 /* R---V */
#define NV_PFALCON_FALCON_IRQMODE 0x0000000c /* RW-4R */
#define NV_PFALCON_FALCON_IRQMASK 0x00000018 /* R--4R */
#define NV_PFALCON_FALCON_MAILBOX0 0x00000040 /* RW-4R */
#define NV_PFALCON_FALCON_MAILBOX0_DATA 31:0 /* RWIVF */
#define NV_PFALCON_FALCON_MAILBOX0_DATA_INIT 0x00000000 /* RWI-V */
#define NV_PFALCON_FALCON_MAILBOX1 0x00000044 /* RW-4R */
#define NV_PFALCON_FALCON_MAILBOX1_DATA 31:0 /* RWIVF */
#define NV_PFALCON_FALCON_MAILBOX1_DATA_INIT 0x00000000 /* RWI-V */
#define NV_PFALCON_FALCON_IDLESTATE 0x0000004c /* RW-4R */
#define NV_PFALCON_FALCON_DMACTL 0x0000010c /* RW-4R */
#define NV_PFALCON_FALCON_DMATRFBASE 0x00000110 /* RW-4R */
#define NV_PFALCON_FALCON_DMATRFBASE_BASE 31:0 /* RWIVF */
#define NV_PFALCON_FALCON_DMATRFBASE_BASE_INIT 0x00000000 /* RWI-V */
#define NV_PFALCON_FALCON_DMATRFMOFFS 0x00000114 /* RW-4R */
#define NV_PFALCON_FALCON_DMATRFMOFFS_OFFS 23:0 /* RWIVF */
#define NV_PFALCON_FALCON_DMATRFMOFFS_OFFS_INIT 0x00000000 /* RWI-V */
#define NV_PFALCON_FALCON_DMATRFCMD 0x00000118 /* RW-4R */
#define NV_PFALCON_FALCON_DMATRFFBOFFS 0x0000011c /* RW-4R */
#define NV_PFALCON_FALCON_DMATRFFBOFFS_OFFS 31:0 /* RWIVF */
#define NV_PFALCON_FALCON_DMATRFFBOFFS_OFFS_INIT 0x00000000 /* RWI-V */
#define NV_PFALCON_FALCON_DMEMC(i) (0x000001c0+(i)*8) /* RW-4A */
#define NV_PFALCON_FALCON_DMEMC__SIZE_1 4 /* */
#define NV_PFALCON_FALCON_DMEMC__DEVICE_MAP 0x00000006 /* */
#define NV_PFALCON_FALCON_DMEMC__PRIV_LEVEL_MASK NV_PFALCON_FALCON_PMB_DMEM_PRIV_LEVEL_MASK /* */
#define NV_PFALCON_FALCON_DMEMC_ADDRESS 23:0 /* RWIVF */
#define NV_PFALCON_FALCON_DMEMC_ADDRESS_INIT 0x00000000 /* RWI-V */
#define NV_PFALCON_FALCON_DMEMC_OFFS 7:2 /* */
#define NV_PFALCON_FALCON_DMEMC_OFFS_INIT 0 /* */
#define NV_PFALCON_FALCON_DMEMC_BLK 23:8 /* */
#define NV_PFALCON_FALCON_DMEMC_BLK_INIT 0 /* */
#define NV_PFALCON_FALCON_DMEMC_AINCW 24:24 /* RWIVF */
#define NV_PFALCON_FALCON_DMEMC_AINCW_INIT 0x00000000 /* RWI-V */
#define NV_PFALCON_FALCON_DMEMC_AINCW_TRUE 0x00000001 /* RW--V */
#define NV_PFALCON_FALCON_DMEMC_AINCW_FALSE 0x00000000 /* RW--V */
#define NV_PFALCON_FALCON_DMEMC_AINCR 25:25 /* RWIVF */
#define NV_PFALCON_FALCON_DMEMC_AINCR_INIT 0x00000000 /* RWI-V */
#define NV_PFALCON_FALCON_DMEMC_AINCR_TRUE 0x00000001 /* RW--V */
#define NV_PFALCON_FALCON_DMEMC_AINCR_FALSE 0x00000000 /* RW--V */
#define NV_PFALCON_FALCON_DMEMC_SETTAG 26:26 /* RWIVF */
#define NV_PFALCON_FALCON_DMEMC_SETTAG_INIT 0x00000000 /* RWI-V */
#define NV_PFALCON_FALCON_DMEMC_SETTAG_TRUE 0x00000001 /* RW--V */
#define NV_PFALCON_FALCON_DMEMC_SETTAG_FALSE 0x00000000 /* RW--V */
#define NV_PFALCON_FALCON_DMEMC_SETLVL 27:27 /* RWIVF */
#define NV_PFALCON_FALCON_DMEMC_SETLVL_INIT 0x00000000 /* RWI-V */
#define NV_PFALCON_FALCON_DMEMC_SETLVL_TRUE 0x00000001 /* RW--V */
#define NV_PFALCON_FALCON_DMEMC_SETLVL_FALSE 0x00000000 /* RW--V */
#define NV_PFALCON_FALCON_DMEMC_VA 28:28 /* RWIVF */
#define NV_PFALCON_FALCON_DMEMC_VA_INIT 0x00000000 /* RWI-V */
#define NV_PFALCON_FALCON_DMEMC_VA_TRUE 0x00000001 /* RW--V */
#define NV_PFALCON_FALCON_DMEMC_VA_FALSE 0x00000000 /* RW--V */
#define NV_PFALCON_FALCON_DMEMC_MISS 29:29 /* R-IVF */
#define NV_PFALCON_FALCON_DMEMC_MISS_TRUE 0x00000001 /* R---V */
#define NV_PFALCON_FALCON_DMEMC_MISS_FALSE 0x00000000 /* R-I-V */
#define NV_PFALCON_FALCON_DMEMC_MULTIHIT 30:30 /* R-IVF */
#define NV_PFALCON_FALCON_DMEMC_MULTIHIT_TRUE 0x00000001 /* R---V */
#define NV_PFALCON_FALCON_DMEMC_MULTIHIT_FALSE 0x00000000 /* R-I-V */
#define NV_PFALCON_FALCON_DMEMC_LVLERR 31:31 /* R-IVF */
#define NV_PFALCON_FALCON_DMEMC_LVLERR_TRUE 0x00000001 /* R---V */
#define NV_PFALCON_FALCON_DMEMC_LVLERR_FALSE 0x00000000 /* R-I-V */
#define NV_PFALCON_FALCON_DMEMD(i) (0x000001c4+(i)*8) /* RW-4A */
#define NV_PFALCON_FALCON_DMEMD__SIZE_1 4 /* */
#define NV_PFALCON_FALCON_DMEMD__DEVICE_MAP 0x00000006 /* */
#define NV_PFALCON_FALCON_DMEMD__PRIV_LEVEL_MASK NV_PFALCON_FALCON_PMB_DMEM_PRIV_LEVEL_MASK /* */
#define NV_PFALCON_FALCON_DMEMD_DATA 31:0 /* RWXVF */
#define NV_PFALCON_FALCON_HWCFG3 0x00000278 /* R--4R */
#define NV_PFALCON_FALCON_HWCFG3_IMEM_TOTAL_SIZE 11:0 /* R--VF */
#define NV_PFALCON_FALCON_HWCFG3_DMEM_TOTAL_SIZE 27:16 /* R--VF */
#define NV_PFALCON_FALCON_OS 0x00000080 /* RW-4R */
#define NV_PFALCON_FALCON_OS_VERSION 31:0 /* RWIVF */
#define NV_PFALCON_FALCON_OS_VERSION_INIT 0x00000000 /* RWI-V */
#define NV_PFALCON_FALCON_CPUCTL 0x00000100 /* RW-4R */
#define NV_PFALCON_FALCON_CPUCTL_IINVAL 0:0 /* -WXVF */
#define NV_PFALCON_FALCON_CPUCTL_IINVAL_TRUE 0x00000001 /* -W--V */
#define NV_PFALCON_FALCON_CPUCTL_IINVAL_FALSE 0x00000000 /* -W--V */
#define NV_PFALCON_FALCON_CPUCTL_STARTCPU 1:1 /* -WXVF */
#define NV_PFALCON_FALCON_CPUCTL_STARTCPU_TRUE 0x00000001 /* -W--V */
#define NV_PFALCON_FALCON_CPUCTL_STARTCPU_FALSE 0x00000000 /* -W--V */
#define NV_PFALCON_FALCON_CPUCTL_SRESET 2:2 /* -WXVF */
#define NV_PFALCON_FALCON_CPUCTL_SRESET_TRUE 0x00000001 /* -W--V */
#define NV_PFALCON_FALCON_CPUCTL_SRESET_FALSE 0x00000000 /* -W--V */
#define NV_PFALCON_FALCON_CPUCTL_HRESET 3:3 /* -WXVF */
#define NV_PFALCON_FALCON_CPUCTL_HRESET_TRUE 0x00000001 /* -W--V */
#define NV_PFALCON_FALCON_CPUCTL_HRESET_FALSE 0x00000000 /* -W--V */
#define NV_PFALCON_FALCON_CPUCTL_HALTED 4:4 /* R-XVF */
#define NV_PFALCON_FALCON_CPUCTL_HALTED_TRUE 0x00000001 /* R---V */
#define NV_PFALCON_FALCON_CPUCTL_HALTED_FALSE 0x00000000 /* R---V */
#define NV_PFALCON_FALCON_CPUCTL_STOPPED 5:5 /* R-XVF */
#define NV_PFALCON_FALCON_CPUCTL_STOPPED_TRUE 0x00000001 /* R---V */
#define NV_PFALCON_FALCON_CPUCTL_STOPPED_FALSE 0x00000000 /* R---V */
#define NV_PFALCON_FALCON_CPUCTL_ALIAS_EN 6:6 /* RWIVF */
#define NV_PFALCON_FALCON_CPUCTL_ALIAS_EN_TRUE 0x00000001 /* RW--V */
#define NV_PFALCON_FALCON_CPUCTL_ALIAS_EN_FALSE 0x00000000 /* RW--V */
#define NV_PFALCON_FALCON_CPUCTL_ALIAS_EN_INIT 0x00000000 /* RWI-V */
#define NV_PFALCON_FALCON_CPUCTL_ALIAS 0x00000130 /* -W-4R */
#define NV_PFALCON_FALCON_CPUCTL_ALIAS_STARTCPU 1:1 /* -WXVF */
#define NV_PFALCON_FALCON_CPUCTL_ALIAS_STARTCPU_TRUE 0x00000001 /* -W--V */
#define NV_PFALCON_FALCON_CPUCTL_ALIAS_STARTCPU_FALSE 0x00000000 /* -W--V */
#endif // __ls10_dev_falcon_v4_h__

33
src/common/inc/swref/published/nvswitch/ls10/dev_fsp_pri.h Normal file
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@@ -0,0 +1,33 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the Software),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __ls10_dev_fsp_pri_h__
#define __ls10_dev_fsp_pri_h__
/* This file is autogenerated. Do not edit */
#define NV_PFSP 0x8F3FFF:0x8F0000 /* RW--D */
#define NV_PFSP_FALCON_COMMON_SCRATCH_GROUP_2(i) (0x008f0320+(i)*4) /* RW-4A */
#define NV_PFSP_FALCON_COMMON_SCRATCH_GROUP_2__SIZE_1 4 /* */
#define NV_PFSP_FALCON_COMMON_SCRATCH_GROUP_2__DEVICE_MAP 0x00000016 /* */
#define NV_PFSP_FALCON_COMMON_SCRATCH_GROUP_2_VAL 31:0 /* RWIVF */
#define NV_PFSP_FALCON_COMMON_SCRATCH_GROUP_2_VAL_INIT 0x00000000 /* RWI-V */
#endif // __ls10_dev_fsp_pri_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the Software),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __ls10_dev_master_h__
#define __ls10_dev_master_h__
/* This file is autogenerated. Do not edit */
#define NV_PMC 0x00000fff:0x00000000 /* RW--D */
#define NV_PMC_BOOT_42 0x00000A00 /* R--4R */
#define NV_PMC_BOOT_42_CHIP_ID 28:20 /* R-XVF */
#define NV_PMC_BOOT_42_CHIP_ID_SVNP01 0x00000005 /* R---V */
#define NV_PMC_BOOT_42_CHIP_ID_LR10 0x00000006 /* R---V */
#define NV_PMC_BOOT_42_CHIP_ID_LS10 0x00000007 /* R---V */
#endif // __ls10_dev_master_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the Software),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __ls10_dev_minion_ip_h__
#define __ls10_dev_minion_ip_h__
/* This file is autogenerated. Do not edit */
#define NV_CMINION_FALCON 0x000006ff:0x00000000 /* RW--D */
#define NV_CMINION_RISCV 0x00000fff:0x00000700 /* RW--D */
#define NV_MINION 0x00003FFF:0x00002000 /* RW--D */
#define NV_CMINION_FALCON_IRQSCLR 0x00000004 /* -W-4R */
#define NV_CMINION_FALCON_IRQSCLR_GPTMR 0:0 /* -WXVF */
#define NV_CMINION_FALCON_IRQSCLR_GPTMR_SET 0x00000001 /* -W--V */
#define NV_CMINION_FALCON_IRQSCLR_WDTMR 1:1 /* -WXVF */
#define NV_CMINION_FALCON_IRQSCLR_WDTMR_SET 0x00000001 /* -W--V */
#define NV_CMINION_FALCON_IRQSCLR_MTHD 2:2 /* -WXVF */
#define NV_CMINION_FALCON_IRQSCLR_MTHD_SET 0x00000001 /* -W--V */
#define NV_CMINION_FALCON_IRQSCLR_CTXSW 3:3 /* -WXVF */
#define NV_CMINION_FALCON_IRQSCLR_CTXSW_SET 0x00000001 /* -W--V */
#define NV_CMINION_FALCON_IRQSCLR_HALT 4:4 /* -WXVF */
#define NV_CMINION_FALCON_IRQSCLR_HALT_SET 0x00000001 /* -W--V */
#define NV_CMINION_FALCON_IRQSCLR_EXTERR 5:5 /* -WXVF */
#define NV_CMINION_FALCON_IRQSCLR_EXTERR_SET 0x00000001 /* -W--V */
#define NV_CMINION_FALCON_IRQSCLR_SWGEN0 6:6 /* -WXVF */
#define NV_CMINION_FALCON_IRQSCLR_SWGEN0_SET 0x00000001 /* -W--V */
#define NV_CMINION_FALCON_IRQSCLR_SWGEN1 7:7 /* -WXVF */
#define NV_CMINION_FALCON_IRQSCLR_SWGEN1_SET 0x00000001 /* -W--V */
#define NV_CMINION_FALCON_IRQSCLR_EXT 15:8 /* */
#define NV_CMINION_FALCON_IRQSCLR_EXT_EXTIRQ1 8:8 /* -WXVF */
#define NV_CMINION_FALCON_IRQSCLR_EXT_EXTIRQ1_SET 0x00000001 /* -W--V */
#define NV_CMINION_FALCON_IRQSCLR_EXT_EXTIRQ2 9:9 /* -WXVF */
#define NV_CMINION_FALCON_IRQSCLR_EXT_EXTIRQ2_SET 0x00000001 /* -W--V */
#define NV_CMINION_FALCON_IRQSCLR_EXT_EXTIRQ3 10:10 /* -WXVF */
#define NV_CMINION_FALCON_IRQSCLR_EXT_EXTIRQ3_SET 0x00000001 /* -W--V */
#define NV_CMINION_FALCON_IRQSCLR_EXT_EXTIRQ4 11:11 /* -WXVF */
#define NV_CMINION_FALCON_IRQSCLR_EXT_EXTIRQ4_SET 0x00000001 /* -W--V */
#define NV_CMINION_FALCON_IRQSCLR_EXT_EXTIRQ5 12:12 /* -WXVF */
#define NV_CMINION_FALCON_IRQSCLR_EXT_EXTIRQ5_SET 0x00000001 /* -W--V */
#define NV_CMINION_FALCON_IRQSCLR_EXT_EXTIRQ6 13:13 /* -WXVF */
#define NV_CMINION_FALCON_IRQSCLR_EXT_EXTIRQ6_SET 0x00000001 /* -W--V */
#define NV_CMINION_FALCON_IRQSCLR_EXT_EXTIRQ7 14:14 /* -WXVF */
#define NV_CMINION_FALCON_IRQSCLR_EXT_EXTIRQ7_SET 0x00000001 /* -W--V */
#define NV_CMINION_FALCON_IRQSCLR_EXT_EXTIRQ8 15:15 /* -WXVF */
#define NV_CMINION_FALCON_IRQSCLR_EXT_EXTIRQ8_SET 0x00000001 /* -W--V */
#define NV_CMINION_FALCON_IRQSCLR_DMA 16:16 /* -WXVF */
#define NV_CMINION_FALCON_IRQSCLR_DMA_SET 0x00000001 /* -W--V */
#define NV_CMINION_FALCON_IRQSCLR_SHA 17:17 /* -WXVF */
#define NV_CMINION_FALCON_IRQSCLR_SHA_SET 0x00000001 /* -W--V */
#define NV_CMINION_FALCON_IRQSCLR_MEMERR 18:18 /* -WXVF */
#define NV_CMINION_FALCON_IRQSCLR_MEMERR_SET 0x00000001 /* -W--V */
#define NV_CMINION_FALCON_IRQSCLR_CTXSW_ERROR 19:19 /* -WXVF */
#define NV_CMINION_FALCON_IRQSCLR_CTXSW_ERROR_SET 0x00000001 /* -W--V */
#define NV_CMINION_FALCON_IRQSCLR_ICD 22:22 /* -WXVF */
#define NV_CMINION_FALCON_IRQSCLR_ICD_SET 0x00000001 /* -W--V */
#define NV_CMINION_FALCON_IRQSCLR_IOPMP 23:23 /* -WXVF */
#define NV_CMINION_FALCON_IRQSCLR_IOPMP_SET 0x00000001 /* -W--V */
#define NV_CMINION_FALCON_IRQSTAT 0x00000008 /* R--4R */
#define NV_CMINION_FALCON_IRQSTAT_GPTMR 0:0 /* R-IVF */
#define NV_CMINION_FALCON_IRQSTAT_GPTMR_FALSE 0x00000000 /* R-I-V */
#define NV_CMINION_FALCON_IRQSTAT_GPTMR_TRUE 0x00000001 /* R---V */
#define NV_CMINION_FALCON_IRQSTAT_WDTMR 1:1 /* R-IVF */
#define NV_CMINION_FALCON_IRQSTAT_WDTMR_FALSE 0x00000000 /* R-I-V */
#define NV_CMINION_FALCON_IRQSTAT_WDTMR_TRUE 0x00000001 /* R---V */
#define NV_CMINION_FALCON_IRQSTAT_MTHD 2:2 /* R-IVF */
#define NV_CMINION_FALCON_IRQSTAT_MTHD_FALSE 0x00000000 /* R-I-V */
#define NV_CMINION_FALCON_IRQSTAT_MTHD_TRUE 0x00000001 /* R---V */
#define NV_CMINION_FALCON_IRQSTAT_CTXSW 3:3 /* R-IVF */
#define NV_CMINION_FALCON_IRQSTAT_CTXSW_FALSE 0x00000000 /* R-I-V */
#define NV_CMINION_FALCON_IRQSTAT_CTXSW_TRUE 0x00000001 /* R---V */
#define NV_CMINION_FALCON_IRQSTAT_HALT 4:4 /* R-IVF */
#define NV_CMINION_FALCON_IRQSTAT_HALT_FALSE 0x00000000 /* R-I-V */
#define NV_CMINION_FALCON_IRQSTAT_HALT_TRUE 0x00000001 /* R---V */
#define NV_CMINION_FALCON_IRQSTAT_EXTERR 5:5 /* R-IVF */
#define NV_CMINION_FALCON_IRQSTAT_EXTERR_FALSE 0x00000000 /* R-I-V */
#define NV_CMINION_FALCON_IRQSTAT_EXTERR_TRUE 0x00000001 /* R---V */
#define NV_CMINION_FALCON_IRQSTAT_SWGEN0 6:6 /* R-IVF */
#define NV_CMINION_FALCON_IRQSTAT_SWGEN0_FALSE 0x00000000 /* R-I-V */
#define NV_CMINION_FALCON_IRQSTAT_SWGEN0_TRUE 0x00000001 /* R---V */
#define NV_CMINION_FALCON_IRQSTAT_SWGEN1 7:7 /* R-IVF */
#define NV_CMINION_FALCON_IRQSTAT_SWGEN1_FALSE 0x00000000 /* R-I-V */
#define NV_CMINION_FALCON_IRQSTAT_SWGEN1_TRUE 0x00000001 /* R---V */
#define NV_CMINION_FALCON_IRQSTAT_EXT 15:8 /* */
#define NV_CMINION_FALCON_IRQSTAT_EXT_EXTIRQ1 8:8 /* R-IVF */
#define NV_CMINION_FALCON_IRQSTAT_EXT_EXTIRQ1_TRUE 0x00000001 /* R---V */
#define NV_CMINION_FALCON_IRQSTAT_EXT_EXTIRQ1_FALSE 0x00000000 /* R-I-V */
#define NV_CMINION_FALCON_IRQSTAT_EXT_EXTIRQ2 9:9 /* R-IVF */
#define NV_CMINION_FALCON_IRQSTAT_EXT_EXTIRQ2_TRUE 0x00000001 /* R---V */
#define NV_CMINION_FALCON_IRQSTAT_EXT_EXTIRQ2_FALSE 0x00000000 /* R-I-V */
#define NV_CMINION_FALCON_IRQSTAT_EXT_EXTIRQ3 10:10 /* R-IVF */
#define NV_CMINION_FALCON_IRQSTAT_EXT_EXTIRQ3_TRUE 0x00000001 /* R---V */
#define NV_CMINION_FALCON_IRQSTAT_EXT_EXTIRQ3_FALSE 0x00000000 /* R-I-V */
#define NV_CMINION_FALCON_IRQSTAT_EXT_EXTIRQ4 11:11 /* R-IVF */
#define NV_CMINION_FALCON_IRQSTAT_EXT_EXTIRQ4_TRUE 0x00000001 /* R---V */
#define NV_CMINION_FALCON_IRQSTAT_EXT_EXTIRQ4_FALSE 0x00000000 /* R-I-V */
#define NV_CMINION_FALCON_IRQSTAT_EXT_EXTIRQ5 12:12 /* R-IVF */
#define NV_CMINION_FALCON_IRQSTAT_EXT_EXTIRQ5_TRUE 0x00000001 /* R---V */
#define NV_CMINION_FALCON_IRQSTAT_EXT_EXTIRQ5_FALSE 0x00000000 /* R-I-V */
#define NV_CMINION_FALCON_IRQSTAT_EXT_EXTIRQ6 13:13 /* R-IVF */
#define NV_CMINION_FALCON_IRQSTAT_EXT_EXTIRQ6_TRUE 0x00000001 /* R---V */
#define NV_CMINION_FALCON_IRQSTAT_EXT_EXTIRQ6_FALSE 0x00000000 /* R-I-V */
#define NV_CMINION_FALCON_IRQSTAT_EXT_EXTIRQ7 14:14 /* R-IVF */
#define NV_CMINION_FALCON_IRQSTAT_EXT_EXTIRQ7_TRUE 0x00000001 /* R---V */
#define NV_CMINION_FALCON_IRQSTAT_EXT_EXTIRQ7_FALSE 0x00000000 /* R-I-V */
#define NV_CMINION_FALCON_IRQSTAT_EXT_EXTIRQ8 15:15 /* R-IVF */
#define NV_CMINION_FALCON_IRQSTAT_EXT_EXTIRQ8_TRUE 0x00000001 /* R---V */
#define NV_CMINION_FALCON_IRQSTAT_EXT_EXTIRQ8_FALSE 0x00000000 /* R-I-V */
#define NV_CMINION_FALCON_IRQSTAT_DMA 16:16 /* R-IVF */
#define NV_CMINION_FALCON_IRQSTAT_DMA_TRUE 0x00000001 /* R---V */
#define NV_CMINION_FALCON_IRQSTAT_DMA_FALSE 0x00000000 /* R-I-V */
#define NV_CMINION_FALCON_IRQSTAT_SHA 17:17 /* R-IVF */
#define NV_CMINION_FALCON_IRQSTAT_SHA_TRUE 0x00000001 /* R---V */
#define NV_CMINION_FALCON_IRQSTAT_SHA_FALSE 0x00000000 /* R-I-V */
#define NV_CMINION_FALCON_IRQSTAT_MEMERR 18:18 /* R-IVF */
#define NV_CMINION_FALCON_IRQSTAT_MEMERR_TRUE 0x00000001 /* R---V */
#define NV_CMINION_FALCON_IRQSTAT_MEMERR_FALSE 0x00000000 /* R-I-V */
#define NV_CMINION_FALCON_IRQSTAT_CTXSW_ERROR 19:19 /* R-XVF */
#define NV_CMINION_FALCON_IRQSTAT_CTXSW_ERROR_TRUE 0x00000001 /* R---V */
#define NV_CMINION_FALCON_IRQSTAT_CTXSW_ERROR_FALSE 0x00000000 /* R---V */
#define NV_CMINION_FALCON_IRQSTAT_ICD 22:22 /* R-XVF */
#define NV_CMINION_FALCON_IRQSTAT_ICD_TRUE 0x00000001 /* R---V */
#define NV_CMINION_FALCON_IRQSTAT_ICD_FALSE 0x00000000 /* R---V */
#define NV_CMINION_FALCON_IRQSTAT_IOPMP 23:23 /* R-XVF */
#define NV_CMINION_FALCON_IRQSTAT_IOPMP_TRUE 0x00000001 /* R---V */
#define NV_CMINION_FALCON_IRQSTAT_IOPMP_FALSE 0x00000000 /* R---V */
#define NV_CMINION_FALCON_IRQMASK 0x00000018 /* R--4R */
#define NV_CMINION_FALCON_IRQMASK_GPTMR 0:0 /* R-IVF */
#define NV_CMINION_FALCON_IRQMASK_GPTMR_DISABLE 0x00000000 /* R-I-V */
#define NV_CMINION_FALCON_IRQMASK_GPTMR_ENABLE 0x00000001 /* R---V */
#define NV_CMINION_FALCON_IRQMASK_WDTMR 1:1 /* R-IVF */
#define NV_CMINION_FALCON_IRQMASK_WDTMR_DISABLE 0x00000000 /* R-I-V */
#define NV_CMINION_FALCON_IRQMASK_WDTMR_ENABLE 0x00000001 /* R---V */
#define NV_CMINION_FALCON_IRQMASK_MTHD 2:2 /* R-IVF */
#define NV_CMINION_FALCON_IRQMASK_MTHD_DISABLE 0x00000000 /* R-I-V */
#define NV_CMINION_FALCON_IRQMASK_MTHD_ENABLE 0x00000001 /* R---V */
#define NV_CMINION_FALCON_IRQMASK_CTXSW 3:3 /* R-IVF */
#define NV_CMINION_FALCON_IRQMASK_CTXSW_DISABLE 0x00000000 /* R-I-V */
#define NV_CMINION_FALCON_IRQMASK_CTXSW_ENABLE 0x00000001 /* R---V */
#define NV_CMINION_FALCON_IRQMASK_HALT 4:4 /* R-IVF */
#define NV_CMINION_FALCON_IRQMASK_HALT_DISABLE 0x00000000 /* R-I-V */
#define NV_CMINION_FALCON_IRQMASK_HALT_ENABLE 0x00000001 /* R---V */
#define NV_CMINION_FALCON_IRQMASK_EXTERR 5:5 /* R-IVF */
#define NV_CMINION_FALCON_IRQMASK_EXTERR_DISABLE 0x00000000 /* R-I-V */
#define NV_CMINION_FALCON_IRQMASK_EXTERR_ENABLE 0x00000001 /* R---V */
#define NV_CMINION_FALCON_IRQMASK_SWGEN0 6:6 /* R-IVF */
#define NV_CMINION_FALCON_IRQMASK_SWGEN0_DISABLE 0x00000000 /* R-I-V */
#define NV_CMINION_FALCON_IRQMASK_SWGEN0_ENABLE 0x00000001 /* R---V */
#define NV_CMINION_FALCON_IRQMASK_SWGEN1 7:7 /* R-IVF */
#define NV_CMINION_FALCON_IRQMASK_SWGEN1_DISABLE 0x00000000 /* R-I-V */
#define NV_CMINION_FALCON_IRQMASK_SWGEN1_ENABLE 0x00000001 /* R---V */
#define NV_CMINION_FALCON_IRQMASK_EXT 15:8 /* */
#define NV_CMINION_FALCON_IRQMASK_EXT_EXTIRQ1 8:8 /* R-IVF */
#define NV_CMINION_FALCON_IRQMASK_EXT_EXTIRQ1_ENABLE 0x00000001 /* R---V */
#define NV_CMINION_FALCON_IRQMASK_EXT_EXTIRQ1_DISABLE 0x00000000 /* R-I-V */
#define NV_CMINION_FALCON_IRQMASK_EXT_EXTIRQ2 9:9 /* R-IVF */
#define NV_CMINION_FALCON_IRQMASK_EXT_EXTIRQ2_ENABLE 0x00000001 /* R---V */
#define NV_CMINION_FALCON_IRQMASK_EXT_EXTIRQ2_DISABLE 0x00000000 /* R-I-V */
#define NV_CMINION_FALCON_IRQMASK_EXT_EXTIRQ3 10:10 /* R-IVF */
#define NV_CMINION_FALCON_IRQMASK_EXT_EXTIRQ3_ENABLE 0x00000001 /* R---V */
#define NV_CMINION_FALCON_IRQMASK_EXT_EXTIRQ3_DISABLE 0x00000000 /* R-I-V */
#define NV_CMINION_FALCON_IRQMASK_EXT_EXTIRQ4 11:11 /* R-IVF */
#define NV_CMINION_FALCON_IRQMASK_EXT_EXTIRQ4_ENABLE 0x00000001 /* R---V */
#define NV_CMINION_FALCON_IRQMASK_EXT_EXTIRQ4_DISABLE 0x00000000 /* R-I-V */
#define NV_CMINION_FALCON_IRQMASK_EXT_EXTIRQ5 12:12 /* R-IVF */
#define NV_CMINION_FALCON_IRQMASK_EXT_EXTIRQ5_ENABLE 0x00000001 /* R---V */
#define NV_CMINION_FALCON_IRQMASK_EXT_EXTIRQ5_DISABLE 0x00000000 /* R-I-V */
#define NV_CMINION_FALCON_IRQMASK_EXT_EXTIRQ6 13:13 /* R-IVF */
#define NV_CMINION_FALCON_IRQMASK_EXT_EXTIRQ6_ENABLE 0x00000001 /* R---V */
#define NV_CMINION_FALCON_IRQMASK_EXT_EXTIRQ6_DISABLE 0x00000000 /* R-I-V */
#define NV_CMINION_FALCON_IRQMASK_EXT_EXTIRQ7 14:14 /* R-IVF */
#define NV_CMINION_FALCON_IRQMASK_EXT_EXTIRQ7_ENABLE 0x00000001 /* R---V */
#define NV_CMINION_FALCON_IRQMASK_EXT_EXTIRQ7_DISABLE 0x00000000 /* R-I-V */
#define NV_CMINION_FALCON_IRQMASK_EXT_EXTIRQ8 15:15 /* R-IVF */
#define NV_CMINION_FALCON_IRQMASK_EXT_EXTIRQ8_ENABLE 0x00000001 /* R---V */
#define NV_CMINION_FALCON_IRQMASK_EXT_EXTIRQ8_DISABLE 0x00000000 /* R-I-V */
#define NV_CMINION_FALCON_IRQMASK_DMA 16:16 /* R-IVF */
#define NV_CMINION_FALCON_IRQMASK_DMA_ENABLE 0x00000001 /* R---V */
#define NV_CMINION_FALCON_IRQMASK_DMA_DISABLE 0x00000000 /* R-I-V */
#define NV_CMINION_FALCON_IRQMASK_SHA 17:17 /* R-IVF */
#define NV_CMINION_FALCON_IRQMASK_SHA_ENABLE 0x00000001 /* R---V */
#define NV_CMINION_FALCON_IRQMASK_SHA_DISABLE 0x00000000 /* R-I-V */
#define NV_CMINION_FALCON_IRQMASK_MEMERR 18:18 /* R-IVF */
#define NV_CMINION_FALCON_IRQMASK_MEMERR_ENABLE 0x00000001 /* R---V */
#define NV_CMINION_FALCON_IRQMASK_MEMERR_DISABLE 0x00000000 /* R-I-V */
#define NV_CMINION_FALCON_IRQMASK_CTXSW_ERROR 19:19 /* R-IVF */
#define NV_CMINION_FALCON_IRQMASK_CTXSW_ERROR_ENABLE 0x00000001 /* R-I-V */
#define NV_CMINION_FALCON_IRQMASK_CTXSW_ERROR_DISABLE 0x00000000 /* R---V */
#define NV_CMINION_FALCON_IRQMASK_ICD 22:22 /* R-XVF */
#define NV_CMINION_FALCON_IRQMASK_ICD_ENABLE 0x00000001 /* R---V */
#define NV_CMINION_FALCON_IRQMASK_ICD_DISABLE 0x00000000 /* R---V */
#define NV_CMINION_FALCON_IRQMASK_IOPMP 23:23 /* R-XVF */
#define NV_CMINION_FALCON_IRQMASK_IOPMP_ENABLE 0x00000001 /* R---V */
#define NV_CMINION_FALCON_IRQMASK_IOPMP_DISABLE 0x00000000 /* R---V */
#define NV_CMINION_RISCV_CPUCTL 0x00000788 /* RW-4R */
#define NV_CMINION_RISCV_CPUCTL_STARTCPU 0:0 /* -WIVF */
#define NV_CMINION_RISCV_CPUCTL_STARTCPU_FALSE 0x00000000 /* -WI-V */
#define NV_CMINION_RISCV_CPUCTL_STARTCPU_TRUE 0x00000001 /* -W--V */
#define NV_CMINION_RISCV_CPUCTL_HALTED 4:4 /* R-IVF */
#define NV_CMINION_RISCV_CPUCTL_HALTED_INIT 0x00000001 /* R-I-V */
#define NV_CMINION_RISCV_CPUCTL_HALTED_TRUE 0x00000001 /* R---V */
#define NV_CMINION_RISCV_CPUCTL_HALTED_FALSE 0x00000000 /* R---V */
#define NV_CMINION_RISCV_CPUCTL_STOPPED 5:5 /* R-IVF */
#define NV_CMINION_RISCV_CPUCTL_STOPPED_INIT 0x00000000 /* R-I-V */
#define NV_CMINION_RISCV_CPUCTL_ACTIVE_STAT 7:7 /* R-IVF */
#define NV_CMINION_RISCV_CPUCTL_ACTIVE_STAT_INACTIVE 0x00000000 /* R-I-V */
#define NV_CMINION_RISCV_CPUCTL_ACTIVE_STAT_ACTIVE 0x00000001 /* R---V */
#define NV_MINION_MINION_INTR 0x00002810 /* RW-4R */
#define NV_MINION_MINION_INTR_FATAL 0:0 /* RWEVF */
#define NV_MINION_MINION_INTR_FATAL_INIT 0x00000000 /* RWE-V */
#define NV_MINION_MINION_INTR_NONFATAL 1:1 /* RWEVF */
#define NV_MINION_MINION_INTR_NONFATAL_INIT 0x00000000 /* RWE-V */
#define NV_MINION_MINION_INTR_FALCON_STALL 2:2 /* R-EVF */
#define NV_MINION_MINION_INTR_FALCON_STALL_INIT 0x00000000 /* R-E-V */
#define NV_MINION_MINION_INTR_FALCON_NOSTALL 3:3 /* R-EVF */
#define NV_MINION_MINION_INTR_FALCON_NOSTALL_INIT 0x00000000 /* R-E-V */
#define NV_MINION_MINION_INTR_LINK 31:16 /* R-EVF */
#define NV_MINION_MINION_INTR_LINK_INIT 0x00000000 /* R-E-V */
#define NV_MINION_MINION_INTR_STALL_EN 0x00002818 /* RW-4R */
#define NV_MINION_MINION_INTR_STALL_EN_FATAL 0:0 /* RWEVF */
#define NV_MINION_MINION_INTR_STALL_EN_FATAL_DISABLE 0x00000000 /* RWE-V */
#define NV_MINION_MINION_INTR_STALL_EN_FATAL_ENABLE 0x00000001 /* RW--V */
#define NV_MINION_MINION_INTR_STALL_EN_NONFATAL 1:1 /* RWEVF */
#define NV_MINION_MINION_INTR_STALL_EN_NONFATAL_DISABLE 0x00000000 /* RWE-V */
#define NV_MINION_MINION_INTR_STALL_EN_NONFATAL_ENABLE 0x00000001 /* RW--V */
#define NV_MINION_MINION_INTR_STALL_EN_FALCON_STALL 2:2 /* RWEVF */
#define NV_MINION_MINION_INTR_STALL_EN_FALCON_STALL_DISABLE 0x00000000 /* RW--V */
#define NV_MINION_MINION_INTR_STALL_EN_FALCON_STALL_ENABLE 0x00000001 /* RWE-V */
#define NV_MINION_MINION_INTR_STALL_EN_FALCON_NOSTALL 3:3 /* RWEVF */
#define NV_MINION_MINION_INTR_STALL_EN_FALCON_NOSTALL_DISABLE 0x00000000 /* RWE-V */
#define NV_MINION_MINION_INTR_STALL_EN_FALCON_NOSTALL_ENABLE 0x00000001 /* RW--V */
#define NV_MINION_MINION_INTR_STALL_EN_LINK 31:16 /* RWEVF */
#define NV_MINION_MINION_INTR_STALL_EN_LINK_DISABLE_ALL 0x00000000 /* RWE-V */
#define NV_MINION_MINION_INTR_STALL_EN_LINK_ENABLE_ALL 0x0000ffff /* RW--V */
#define NV_MINION_MINION_INTR_NONSTALL_EN 0x0000281c /* RW-4R */
#define NV_MINION_MINION_INTR_NONSTALL_EN_FATAL 0:0 /* RWEVF */
#define NV_MINION_MINION_INTR_NONSTALL_EN_FATAL_DISABLE 0x00000000 /* RWE-V */
#define NV_MINION_MINION_INTR_NONSTALL_EN_FATAL_ENABLE 0x00000001 /* RW--V */
#define NV_MINION_MINION_INTR_NONSTALL_EN_NONFATAL 1:1 /* RWEVF */
#define NV_MINION_MINION_INTR_NONSTALL_EN_NONFATAL_DISABLE 0x00000000 /* RWE-V */
#define NV_MINION_MINION_INTR_NONSTALL_EN_NONFATAL_ENABLE 0x00000001 /* RW--V */
#define NV_MINION_MINION_INTR_NONSTALL_EN_FALCON_STALL 2:2 /* RWEVF */
#define NV_MINION_MINION_INTR_NONSTALL_EN_FALCON_STALL_DISABLE 0x00000000 /* RWE-V */
#define NV_MINION_MINION_INTR_NONSTALL_EN_FALCON_STALL_ENABLE 0x00000001 /* RW--V */
#define NV_MINION_MINION_INTR_NONSTALL_EN_FALCON_NOSTALL 3:3 /* RWEVF */
#define NV_MINION_MINION_INTR_NONSTALL_EN_FALCON_NOSTALL_DISABLE 0x00000000 /* RW--V */
#define NV_MINION_MINION_INTR_NONSTALL_EN_FALCON_NOSTALL_ENABLE 0x00000001 /* RWE-V */
#define NV_MINION_MINION_INTR_NONSTALL_EN_LINK 31:16 /* RWEVF */
#define NV_MINION_MINION_INTR_NONSTALL_EN_LINK_DISABLE_ALL 0x00000000 /* RWE-V */
#define NV_MINION_MINION_INTR_NONSTALL_EN_LINK_ENABLE_ALL 0x0000ffff /* RW--V */
#define NV_MINION_MINION_STATUS 0x00002830 /* RW-4R */
#define NV_MINION_MINION_STATUS_STATUS 7:0 /* RWEVF */
#define NV_MINION_MINION_STATUS_STATUS_INIT 0x00000000 /* RW--V */
#define NV_MINION_MINION_STATUS_STATUS_NOTBOOT 0x00000000 /* RWE-V */
#define NV_MINION_MINION_STATUS_STATUS_BOOT 0x00000001 /* RW--V */
#define NV_MINION_MINION_STATUS_INTR_CODE 31:8 /* RWEVF */
#define NV_MINION_MINION_STATUS_INTR_CODE_INIT 0x00000000 /* RWE-V */
#define NV_MINION_MISC_0 0x000028b0 /* RW-4R */
#define NV_MINION_MISC_0_SCRATCH_SWRW_0 31:0 /* RWEVF */
#define NV_MINION_MISC_0_SCRATCH_SWRW_0_INIT 0x00000000 /* RWE-V */
#define NV_MINION_NVLINK_DL_CMD(i) (0x00002900+(i)*0x4) /* RW-4A */
#define NV_MINION_NVLINK_DL_CMD__SIZE_1 4 /* */
#define NV_MINION_NVLINK_DL_CMD_COMMAND 7:0 /* RWEVF */
#define NV_MINION_NVLINK_DL_CMD_COMMAND_NOP 0x00000000 /* RWE-V */
#define NV_MINION_NVLINK_DL_CMD_COMMAND_INITPHY 0x00000001 /* RW--V */
#define NV_MINION_NVLINK_DL_CMD_COMMAND_SWINTR 0x00000002 /* RW--V */
#define NV_MINION_NVLINK_DL_CMD_COMMAND_INITLANEENABLE 0x00000003 /* RW--V */
#define NV_MINION_NVLINK_DL_CMD_COMMAND_INITDLPL 0x00000004 /* RW--V */
#define NV_MINION_NVLINK_DL_CMD_COMMAND_INITRXTERM 0x00000005 /* RW--V */
#define NV_MINION_NVLINK_DL_CMD_COMMAND_INITTL 0x00000006 /* RW--V */
#define NV_MINION_NVLINK_DL_CMD_COMMAND_INITPLL 0x00000007 /* RW--V */
#define NV_MINION_NVLINK_DL_CMD_COMMAND_LANEDISABLE 0x00000008 /* RW--V */
#define NV_MINION_NVLINK_DL_CMD_COMMAND_LANESHUTDOWN 0x0000000c /* RW--V */
#define NV_MINION_NVLINK_DL_CMD_COMMAND_INITPHASE1 0x0000000d /* RW--V */
#define NV_MINION_NVLINK_DL_CMD_COMMAND_INITNEGOTIATE 0x0000000e /* RW--V */
#define NV_MINION_NVLINK_DL_CMD_COMMAND_INITOPTIMIZE 0x0000000f /* RW--V */
#define NV_MINION_NVLINK_DL_CMD_COMMAND_ENABLEPM 0x00000010 /* RW--V */
#define NV_MINION_NVLINK_DL_CMD_COMMAND_DISABLEPM 0x00000011 /* RW--V */
#define NV_MINION_NVLINK_DL_CMD_COMMAND_TXCLKSWITCH_PLL 0x00000014 /* RW--V */
#define NV_MINION_NVLINK_DL_CMD_COMMAND_TXCLKSWITCH_ALT 0x00000015 /* RW--V */
#define NV_MINION_NVLINK_DL_CMD_COMMAND_CLEARRESTORESTATE 0x00000017 /* RW--V */
#define NV_MINION_NVLINK_DL_CMD_COMMAND_SAVESTATE 0x00000018 /* RW--V */
#define NV_MINION_NVLINK_DL_CMD_COMMAND_READ_PHY_TRAINING_PARAMS 0x00000020 /* RW--V */
#define NV_MINION_NVLINK_DL_CMD_COMMAND_WRITE_PHY_TRAINING_PARAMS 0x00000021 /* RW--V */
#define NV_MINION_NVLINK_DL_CMD_COMMAND_INITPHASE5A 0x00000022 /* RW--V */
#define NV_MINION_NVLINK_DL_CMD_COMMAND_RESERVED1 0x00000023 /* RW--V */
#define NV_MINION_NVLINK_DL_CMD_COMMAND_RESERVED2 0x00000024 /* RW--V */
#define NV_MINION_NVLINK_DL_CMD_COMMAND_RESERVED3 0x00000025 /* RW--V */
#define NV_MINION_NVLINK_DL_CMD_COMMAND_READ_RX_BUFFER_START 0x00000030 /* RW--V */
#define NV_MINION_NVLINK_DL_CMD_COMMAND_READ_RX_BUFFER_MIDDLE 0x00000031 /* RW--V */
#define NV_MINION_NVLINK_DL_CMD_COMMAND_READ_RX_BUFFER_END 0x00000032 /* RW--V */
#define NV_MINION_NVLINK_DL_CMD_COMMAND_WRITE_TX_BUFFER_START 0x00000033 /* RW--V */
#define NV_MINION_NVLINK_DL_CMD_COMMAND_WRITE_TX_BUFFER_MIDDLE 0x00000034 /* RW--V */
#define NV_MINION_NVLINK_DL_CMD_COMMAND_WRITE_TX_BUFFER_END 0x00000035 /* RW--V */
#define NV_MINION_NVLINK_DL_CMD_COMMAND_CLEAR_RX_BUFFER 0x00000036 /* RW--V */
#define NV_MINION_NVLINK_DL_CMD_COMMAND_CLEAR_TX_BUFFER 0x00000037 /* RW--V */
#define NV_MINION_NVLINK_DL_CMD_COMMAND_CONFIGEOM 0x00000040 /* RW--V */
#define NV_MINION_NVLINK_DL_CMD_COMMAND_SETNEA 0x00000041 /* RW--V */
#define NV_MINION_NVLINK_DL_CMD_COMMAND_SETNEDR 0x00000042 /* RW--V */
#define NV_MINION_NVLINK_DL_CMD_COMMAND_SETNEDW 0x00000043 /* RW--V */
#define NV_MINION_NVLINK_DL_CMD_COMMAND_STARTEOM 0x00000044 /* RW--V */
#define NV_MINION_NVLINK_DL_CMD_COMMAND_ENDEOM 0x00000045 /* RW--V */
#define NV_MINION_NVLINK_DL_CMD_COMMAND_XAVIER_PLLOVERRIDE_ON 0x00000050 /* RW--V */
#define NV_MINION_NVLINK_DL_CMD_COMMAND_XAVIER_PLLOVERRIDE_OFF 0x00000051 /* RW--V */
#define NV_MINION_NVLINK_DL_CMD_COMMAND_XAVIER_CALIBRATEPLL 0x00000052 /* RW--V */
#define NV_MINION_NVLINK_DL_CMD_COMMAND_TURING_RXDET 0x00000058 /* RW--V */
#define NV_MINION_NVLINK_DL_CMD_COMMAND_ABORTRXDET 0x00000059 /* RW--V */
#define NV_MINION_NVLINK_DL_CMD_COMMAND_SET_BUFFER_READY 0x00000060 /* RW--V */
#define NV_MINION_NVLINK_DL_CMD_COMMAND_DLSTAT_CLR_DLERRCNT 0x00000070 /* RW--V */
#define NV_MINION_NVLINK_DL_CMD_COMMAND_DLSTAT_CLR_DLLPCNT 0x00000071 /* RW--V */
#define NV_MINION_NVLINK_DL_CMD_COMMAND_DLSTAT_CLR_DLTHROUGHPUTCNT 0x00000072 /* RW--V */
#define NV_MINION_NVLINK_DL_CMD_COMMAND_DLSTAT_CLR_MINION_MISCCNT 0x00000073 /* RW--V */
#define NV_MINION_NVLINK_DL_CMD_COMMAND_RESERVED4 0x00000074 /* RW--V */
#define NV_MINION_NVLINK_DL_CMD_COMMAND_RESERVED5 0x00000075 /* RW--V */
#define NV_MINION_NVLINK_DL_CMD_COMMAND_DBG_SETSIMMODE_FAST 0x00000080 /* RW--V */
#define NV_MINION_NVLINK_DL_CMD_COMMAND_DBG_SETSIMMODE_MEDIUM 0x00000081 /* RW--V */
#define NV_MINION_NVLINK_DL_CMD_COMMAND_DBG_SETSIMMODE_SLOW 0x00000082 /* RW--V */
#define NV_MINION_NVLINK_DL_CMD_COMMAND_DBG_SETSIMMODE_DEFAULT 0x00000083 /* RW--V */
#define NV_MINION_NVLINK_DL_CMD_COMMAND_DBG_SETSIMMODE_RXCAL_EN_ALARM 0x00000084 /* RW--V */
#define NV_MINION_NVLINK_DL_CMD_COMMAND_DBG_SETSIMMODE_INIT_CAL_DONE 0x00000085 /* RW--V */
#define NV_MINION_NVLINK_DL_CMD_COMMAND_DBG_SETSIMMODE_SMF_VALUES_SLOW 0x00000086 /* RW--V */
#define NV_MINION_NVLINK_DL_CMD_COMMAND_DBG_SETSIMMODE_SMF_VALUES_MEDIUM 0x00000087 /* RW--V */
#define NV_MINION_NVLINK_DL_CMD_COMMAND_DBG_SETSIMMODE_SMF_VALUES_MEDIUM_SERIAL 0x00000088 /* RW--V */
#define NV_MINION_NVLINK_DL_CMD_COMMAND_DBG_SETSIMMODE_SMF_VALUES_FAST 0x00000089 /* RW--V */
#define NV_MINION_NVLINK_DL_CMD_COMMAND_DBG_SETSIMMODE_SMF_VALUES_FAST_ERRORS 0x0000008a /* RW--V */
#define NV_MINION_NVLINK_DL_CMD_COMMAND_DBG_SETSIMMODE_PLL_TIMEOUT 0x0000008b /* RW--V */
#define NV_MINION_NVLINK_DL_CMD_COMMAND_DBG_SETSIMMODE_UPHY_TABLES_DEFAULT 0x0000008c /* RW--V */
#define NV_MINION_NVLINK_DL_CMD_COMMAND_DBG_SETSIMMODE_UPHY_TABLES_SHORT 0x0000008d /* RW--V */
#define NV_MINION_NVLINK_DL_CMD_COMMAND_DBG_SETSIMMODE_UPHY_TABLES_FAST 0x0000008e /* RW--V */
#define NV_MINION_NVLINK_DL_CMD_COMMAND_DBG_SETSIMMODE_IOBIST_ECC 0x0000008f /* RW--V */
#define NV_MINION_NVLINK_DL_CMD_COMMAND_RESERVED6 0x00000090 /* RW--V */
#define NV_MINION_NVLINK_DL_CMD_COMMAND_RESERVED7 0x00000091 /* RW--V */
#define NV_MINION_NVLINK_DL_CMD_COMMAND_DBG_SETSIMMODE_SET_TIEBREAK_GT 0x00000092 /* RW--V */
#define NV_MINION_NVLINK_DL_CMD_COMMAND_DBG_PROTECTIONS_OFF 0x000000f0 /* RW--V */
#define NV_MINION_NVLINK_DL_CMD_COMMAND_DBG_SETSIMMODE 0x000000f1 /* RW--V */
#define NV_MINION_NVLINK_DL_CMD_COMMAND_ALWAYSFAULT 0x000000ff /* RW--V */
#define NV_MINION_NVLINK_DL_CMD_FAULT 30:30 /* RWEVF */
#define NV_MINION_NVLINK_DL_CMD_FAULT_FAULT_CLEAR 0x00000001 /* RW--V */
#define NV_MINION_NVLINK_DL_CMD_FAULT_NOFAULT_NOCLEAR 0x00000000 /* RWE-V */
#define NV_MINION_NVLINK_DL_CMD_READY 31:31 /* RWEVF */
#define NV_MINION_NVLINK_DL_CMD_READY_TRUE 0x00000001 /* RW--V */
#define NV_MINION_NVLINK_DL_CMD_READY_FALSE 0x00000000 /* RWE-V */
#define NV_MINION_NVLINK_DL_CMD_DATA(i) (0x00002920+(i)*0x4) /* RW-4A */
#define NV_MINION_NVLINK_DL_CMD_DATA__SIZE_1 4 /* */
#define NV_MINION_NVLINK_DL_CMD_DATA_DATA 31:0 /* RWEVF */
#define NV_MINION_NVLINK_DL_CMD_DATA_DATA_INIT 0x00000000 /* RWE-V */
#define NV_MINION_NVLINK_DL_CMD_DATA_DATA_SET_BUFFER_READY_TX 0x00000001 /* RW--V */
#define NV_MINION_NVLINK_DL_CMD_DATA_DATA_SET_BUFFER_READY_RX 0x00000002 /* RW--V */
#define NV_MINION_NVLINK_DL_CMD_DATA_DATA_SET_BUFFER_READY_TX_AND_RX 0x00000003 /* RW--V */
#define NV_MINION_NVLINK_DL_STAT(i) (0x00002980+(i)*0x4) /* RW-4A */
#define NV_MINION_NVLINK_DL_STAT__SIZE_1 4 /* */
#define NV_MINION_NVLINK_DL_STAT_ARGS 15:0 /* RWEVF */
#define NV_MINION_NVLINK_DL_STAT_ARGS_INIT 0x00000000 /* RWE-V */
#define NV_MINION_NVLINK_DL_STAT_STATUSIDX 23:16 /* RWEVF */
#define NV_MINION_NVLINK_DL_STAT_STATUSIDX_INIT 0x00000000 /* RWE-V */
#define NV_MINION_NVLINK_DL_STAT_READY 31:31 /* RWEVF */
#define NV_MINION_NVLINK_DL_STAT_READY_TRUE 0x00000001 /* RW--V */
#define NV_MINION_NVLINK_DL_STAT_READY_FALSE 0x00000000 /* RWE-V */
#define NV_MINION_NVLINK_DL_STATDATA(i) (0x000029c0+(i)*0x4) /* RW-4A */
#define NV_MINION_NVLINK_DL_STATDATA__SIZE_1 4 /* */
#define NV_MINION_NVLINK_DL_STATDATA_DATA 31:0 /* RWEVF */
#define NV_MINION_NVLINK_DL_STATDATA_DATA_INIT 0x00000000 /* RWE-V */
#define NV_MINION_NVLINK_LINK_INTR(i) (0x00002a00+(i)*0x4) /* RW-4A */
#define NV_MINION_NVLINK_LINK_INTR__SIZE_1 4 /* */
#define NV_MINION_NVLINK_LINK_INTR_CODE 7:0 /* RWEVF */
#define NV_MINION_NVLINK_LINK_INTR_CODE_NA 0x00000000 /* RWE-V */
#define NV_MINION_NVLINK_LINK_INTR_CODE_SWREQ 0x00000001 /* RW--V */
#define NV_MINION_NVLINK_LINK_INTR_CODE_DLREQ 0x00000002 /* RW--V */
#define NV_MINION_NVLINK_LINK_INTR_CODE_PMDISABLED 0x00000003 /* RW--V */
#define NV_MINION_NVLINK_LINK_INTR_CODE_DLCMDFAULT 0x00000004 /* RW--V */
#define NV_MINION_NVLINK_LINK_INTR_CODE_TLREQ 0x00000005 /* RW--V */
#define NV_MINION_NVLINK_LINK_INTR_CODE_NOINIT 0x00000010 /* RW--V */
#define NV_MINION_NVLINK_LINK_INTR_CODE_NOTIFY 0x00000017 /* RW--V */
#define NV_MINION_NVLINK_LINK_INTR_CODE_LOCAL_CONFIG_ERR 0x00000018 /* RW--V */
#define NV_MINION_NVLINK_LINK_INTR_CODE_NEGOTIATION_CONFIG_ERR 0x00000019 /* RW--V */
#define NV_MINION_NVLINK_LINK_INTR_CODE_BADINIT 0x00000020 /* RW--V */
#define NV_MINION_NVLINK_LINK_INTR_CODE_PMFAIL 0x00000021 /* RW--V */
#define NV_MINION_NVLINK_LINK_INTR_CODE_INBAND_BUFFER_AVAILABLE 0x00000022 /* RW--V */
#define NV_MINION_NVLINK_LINK_INTR_CODE_INBAND_BUFFER_COMPLETE 0x00000023 /* RW--V */
#define NV_MINION_NVLINK_LINK_INTR_CODE_INBAND_BUFFER_FAIL 0x00000024 /* RW--V */
#define NV_MINION_NVLINK_LINK_INTR_SUBCODE 15:8 /* RWEVF */
#define NV_MINION_NVLINK_LINK_INTR_SUBCODE_INIT 0x00000000 /* RWE-V */
#define NV_MINION_NVLINK_LINK_INTR_STATE 31:31 /* RWEVF */
#define NV_MINION_NVLINK_LINK_INTR_STATE_INIT 0x00000000 /* RWE-V */
#define NV_MINION_ERR_STATUS_0 0x00002d00 /* RW-4R */
#define NV_MINION_ERR_STATUS_0_MINION_IMEM_PARITY_ERR 0:0 /* RWIVF */
#define NV_MINION_ERR_STATUS_0_MINION_IMEM_PARITY_ERR__ONWRITE "oneToClear" /* */
#define NV_MINION_ERR_STATUS_0_MINION_IMEM_PARITY_ERR_NONE 0x00000000 /* RWI-V */
#define NV_MINION_ERR_STATUS_0_MINION_IMEM_PARITY_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_MINION_ERR_STATUS_0_MINION_DMEM_PARITY_ERR 4:4 /* RWIVF */
#define NV_MINION_ERR_STATUS_0_MINION_DMEM_PARITY_ERR__ONWRITE "oneToClear" /* */
#define NV_MINION_ERR_STATUS_0_MINION_DMEM_PARITY_ERR_NONE 0x00000000 /* RWI-V */
#define NV_MINION_ERR_STATUS_0_MINION_DMEM_PARITY_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_MINION_ERR_STATUS_0_MINION_MPU_PARITY_ERR 8:8 /* RWIVF */
#define NV_MINION_ERR_STATUS_0_MINION_MPU_PARITY_ERR__ONWRITE "oneToClear" /* */
#define NV_MINION_ERR_STATUS_0_MINION_MPU_PARITY_ERR_NONE 0x00000000 /* RWI-V */
#define NV_MINION_ERR_STATUS_0_MINION_MPU_PARITY_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_MINION_ERR_STATUS_0_MINION_REG_PARITY_ERR 12:12 /* RWIVF */
#define NV_MINION_ERR_STATUS_0_MINION_REG_PARITY_ERR__ONWRITE "oneToClear" /* */
#define NV_MINION_ERR_STATUS_0_MINION_REG_PARITY_ERR_NONE 0x00000000 /* RWI-V */
#define NV_MINION_ERR_STATUS_0_MINION_REG_PARITY_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_MINION_ERR_LOG_EN_0 0x00002d04 /* RW-4R */
#define NV_MINION_ERR_LOG_EN_0_MINION_IMEM_PARITY_ERR 0:0 /* RWEVF */
#define NV_MINION_ERR_LOG_EN_0_MINION_IMEM_PARITY_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_MINION_ERR_LOG_EN_0_MINION_IMEM_PARITY_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_MINION_ERR_LOG_EN_0_MINION_DMEM_PARITY_ERR 4:4 /* RWEVF */
#define NV_MINION_ERR_LOG_EN_0_MINION_DMEM_PARITY_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_MINION_ERR_LOG_EN_0_MINION_DMEM_PARITY_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_MINION_ERR_LOG_EN_0_MINION_MPU_PARITY_ERR 8:8 /* RWEVF */
#define NV_MINION_ERR_LOG_EN_0_MINION_MPU_PARITY_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_MINION_ERR_LOG_EN_0_MINION_MPU_PARITY_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_MINION_ERR_LOG_EN_0_MINION_REG_PARITY_ERR 12:12 /* RWEVF */
#define NV_MINION_ERR_LOG_EN_0_MINION_REG_PARITY_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_MINION_ERR_LOG_EN_0_MINION_REG_PARITY_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_MINION_ERR_FATAL_REPORT_EN_0 0x00002d08 /* RW-4R */
#define NV_MINION_ERR_FATAL_REPORT_EN_0_MINION_IMEM_PARITY_ERR 0:0 /* RWEVF */
#define NV_MINION_ERR_FATAL_REPORT_EN_0_MINION_IMEM_PARITY_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_MINION_ERR_FATAL_REPORT_EN_0_MINION_IMEM_PARITY_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_MINION_ERR_FATAL_REPORT_EN_0_MINION_DMEM_PARITY_ERR 4:4 /* RWEVF */
#define NV_MINION_ERR_FATAL_REPORT_EN_0_MINION_DMEM_PARITY_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_MINION_ERR_FATAL_REPORT_EN_0_MINION_DMEM_PARITY_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_MINION_ERR_FATAL_REPORT_EN_0_MINION_MPU_PARITY_ERR 8:8 /* RWEVF */
#define NV_MINION_ERR_FATAL_REPORT_EN_0_MINION_MPU_PARITY_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_MINION_ERR_FATAL_REPORT_EN_0_MINION_MPU_PARITY_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_MINION_ERR_FATAL_REPORT_EN_0_MINION_REG_PARITY_ERR 12:12 /* RWEVF */
#define NV_MINION_ERR_FATAL_REPORT_EN_0_MINION_REG_PARITY_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_MINION_ERR_FATAL_REPORT_EN_0_MINION_REG_PARITY_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_MINION_ERR_NON_FATAL_REPORT_EN_0 0x00002d0c /* RW-4R */
#define NV_MINION_ERR_NON_FATAL_REPORT_EN_0_MINION_IMEM_PARITY_ERR 0:0 /* RWEVF */
#define NV_MINION_ERR_NON_FATAL_REPORT_EN_0_MINION_IMEM_PARITY_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_MINION_ERR_NON_FATAL_REPORT_EN_0_MINION_IMEM_PARITY_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_MINION_ERR_NON_FATAL_REPORT_EN_0_MINION_DMEM_PARITY_ERR 4:4 /* RWEVF */
#define NV_MINION_ERR_NON_FATAL_REPORT_EN_0_MINION_DMEM_PARITY_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_MINION_ERR_NON_FATAL_REPORT_EN_0_MINION_DMEM_PARITY_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_MINION_ERR_NON_FATAL_REPORT_EN_0_MINION_MPU_PARITY_ERR 8:8 /* RWEVF */
#define NV_MINION_ERR_NON_FATAL_REPORT_EN_0_MINION_MPU_PARITY_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_MINION_ERR_NON_FATAL_REPORT_EN_0_MINION_MPU_PARITY_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_MINION_ERR_NON_FATAL_REPORT_EN_0_MINION_REG_PARITY_ERR 12:12 /* RWEVF */
#define NV_MINION_ERR_NON_FATAL_REPORT_EN_0_MINION_REG_PARITY_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_MINION_ERR_NON_FATAL_REPORT_EN_0_MINION_REG_PARITY_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_MINION_ERR_CORRECTABLE_REPORT_EN_0 0x00002d10 /* RW-4R */
#define NV_MINION_ERR_CONTAIN_EN_0 0x00002d14 /* RW-4R */
#define NV_MINION_ERR_CONTAIN_EN_0_MINION_IMEM_PARITY_ERR 0:0 /* RWEVF */
#define NV_MINION_ERR_CONTAIN_EN_0_MINION_IMEM_PARITY_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_MINION_ERR_CONTAIN_EN_0_MINION_IMEM_PARITY_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_MINION_ERR_CONTAIN_EN_0_MINION_DMEM_PARITY_ERR 4:4 /* RWEVF */
#define NV_MINION_ERR_CONTAIN_EN_0_MINION_DMEM_PARITY_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_MINION_ERR_CONTAIN_EN_0_MINION_DMEM_PARITY_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_MINION_ERR_CONTAIN_EN_0_MINION_MPU_PARITY_ERR 8:8 /* RWEVF */
#define NV_MINION_ERR_CONTAIN_EN_0_MINION_MPU_PARITY_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_MINION_ERR_CONTAIN_EN_0_MINION_MPU_PARITY_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_MINION_ERR_CONTAIN_EN_0_MINION_REG_PARITY_ERR 12:12 /* RWEVF */
#define NV_MINION_ERR_CONTAIN_EN_0_MINION_REG_PARITY_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_MINION_ERR_CONTAIN_EN_0_MINION_REG_PARITY_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_MINION_ERR_FIRST_0 0x00002d1c /* RW-4R */
#define NV_MINION_ERR_FIRST_0_MINION_IMEM_PARITY_ERR 0:0 /* RWIVF */
#define NV_MINION_ERR_FIRST_0_MINION_IMEM_PARITY_ERR__ONWRITE "oneToClear" /* */
#define NV_MINION_ERR_FIRST_0_MINION_IMEM_PARITY_ERR_NONE 0x00000000 /* RWI-V */
#define NV_MINION_ERR_FIRST_0_MINION_IMEM_PARITY_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_MINION_ERR_FIRST_0_MINION_DMEM_PARITY_ERR 4:4 /* RWIVF */
#define NV_MINION_ERR_FIRST_0_MINION_DMEM_PARITY_ERR__ONWRITE "oneToClear" /* */
#define NV_MINION_ERR_FIRST_0_MINION_DMEM_PARITY_ERR_NONE 0x00000000 /* RWI-V */
#define NV_MINION_ERR_FIRST_0_MINION_DMEM_PARITY_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_MINION_ERR_FIRST_0_MINION_MPU_PARITY_ERR 8:8 /* RWIVF */
#define NV_MINION_ERR_FIRST_0_MINION_MPU_PARITY_ERR__ONWRITE "oneToClear" /* */
#define NV_MINION_ERR_FIRST_0_MINION_MPU_PARITY_ERR_NONE 0x00000000 /* RWI-V */
#define NV_MINION_ERR_FIRST_0_MINION_MPU_PARITY_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_MINION_ERR_FIRST_0_MINION_REG_PARITY_ERR 12:12 /* RWIVF */
#define NV_MINION_ERR_FIRST_0_MINION_REG_PARITY_ERR__ONWRITE "oneToClear" /* */
#define NV_MINION_ERR_FIRST_0_MINION_REG_PARITY_ERR_NONE 0x00000000 /* RWI-V */
#define NV_MINION_ERR_FIRST_0_MINION_REG_PARITY_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_MINION_ERR_IMEM_ERROR_ADDRESS 0x00002d20 /* R--4R */
#define NV_MINION_ERR_IMEM_ERROR_ADDRESS_ERROR_ADDRESS 15:0 /* R-IVF */
#define NV_MINION_ERR_IMEM_ERROR_ADDRESS_ERROR_ADDRESS_INIT 0x00000000 /* R-I-V */
#define NV_MINION_ERR_DMEM_ERROR_ADDRESS 0x00002d24 /* R--4R */
#define NV_MINION_ERR_DMEM_ERROR_ADDRESS_ERROR_ADDRESS 15:0 /* R-IVF */
#define NV_MINION_ERR_DMEM_ERROR_ADDRESS_ERROR_ADDRESS_INIT 0x00000000 /* R-I-V */
#define NV_MINION_ERR_MPU_ERROR_ADDRESS 0x00002d28 /* R--4R */
#define NV_MINION_ERR_MPU_ERROR_ADDRESS_ERROR_ADDRESS 15:0 /* R-IVF */
#define NV_MINION_ERR_MPU_ERROR_ADDRESS_ERROR_ADDRESS_INIT 0x00000000 /* R-I-V */
#endif // __ls10_dev_minion_ip_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the Software),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __ls10_dev_minion_ip_addendum_h__
#define __ls10_dev_minion_ip_addendum_h__
// ALARM Timings needed for EMU
#define NV_MINION_DL_CMD_DATA_RXCAL_EN_ALARM 0x50
#define NV_MINION_DL_CMD_DATA_INIT_CAL_DONE 0x26
// filtering dev_minion_dlstat.ref for pattern (CMINION|MINION|NVLSTAT|PMINION|SWMINION)
#define NV_NVLSTAT 0x00000103:0x00000000 /* RW--D */
#define NV_NVLSTAT_UC01 0x00000001 /* R--4R */
#define NV_NVLSTAT_UC01_PM_STATE 31:31 /* R---F */
#define NV_NVLSTAT_UC01_ACMODE_STATE 30:30 /* R---F */
#define NV_NVLSTAT_UC01_LANES_ENABLED 29:29 /* R---F */
#define NV_NVLSTAT_UC01_LANES_ENABLED_TRUE 0x1 /* R---V */
#define NV_NVLSTAT_UC01_LANES_ENABLED_FALSE 0x0 /* R---V */
#define NV_NVLSTAT_UC01_INBAND_BUFFER_FAIL 26:26 /* R---F */
#define NV_NVLSTAT_UC01_INBAND_BUFFER_FAIL_TRUE 0x1 /* R---F */
#define NV_NVLSTAT_UC01_INBAND_BUFFER_FAIL_FALSE 0x0 /* R---F */
#define NV_NVLSTAT_UC01_INBAND_BUFFER_COMPLETE 25:25 /* R---F */
#define NV_NVLSTAT_UC01_INBAND_BUFFER_COMPLETE_TRUE 0x1 /* R---F */
#define NV_NVLSTAT_UC01_INBAND_BUFFER_COMPLETE_FALSE 0x0 /* R---F */
#define NV_NVLSTAT_UC01_L2EXIT_DONE 24:24 /* R---F */
#define NV_NVLSTAT_UC01_L2EXIT_DONE_SUCCESS 0x1 /* R---V */
#define NV_NVLSTAT_UC01_L2EXIT_DONE_UNKNOWN 0x0 /* R---V */
#define NV_NVLSTAT_UC01_TRAINING_BUFFER_STATUS 23:20 /* R---F */
#define NV_NVLSTAT_UC01_SEARCH_ERROR 19:19 /* R---F */
#define NV_NVLSTAT_UC01_TRAINING_GOOD 18:18 /* R---F */
#define NV_NVLSTAT_UC01_TRAINING_GOOD_SUCCESS 0x1 /* R---V */
#define NV_NVLSTAT_UC01_TRAINING_GOOD_UNKNOWN 0x0 /* R---V */
#define NV_NVLSTAT_UC01_AUTOINIT_DONE 17:17 /* R---F */
#define NV_NVLSTAT_UC01_AUTOINIT_DONE_SUCCESS 0x1 /* R---V */
#define NV_NVLSTAT_UC01_AUTOINIT_DONE_UNKNOWN 0x0 /* R---V */
#define NV_NVLSTAT_UC01_CONFIG_GOOD 16:16 /* R---F */
#define NV_NVLSTAT_UC01_CONFIG_GOOD_SUCCESS 0x1 /* R---V */
#define NV_NVLSTAT_UC01_CONFIG_GOOD_UNKNOWN 0x0 /* R---V */
#define NV_NVLSTAT_UC01_LINK_STATE 15:0 /* R---F */
#define NV_NVLSTAT_LNK0 0x00000010 /* R--4R */
#define NV_NVLSTAT_LNK0_INTR_TX_FAULT_RAM 4:4 /* R---F */
#define NV_NVLSTAT_LNK0_INTR_TX_FAULT_INTERFACE 5:5 /* R---F */
#define NV_NVLSTAT_LNK0_INTR_TX_FAULT_SUBLINK_CHANGE 8:8 /* R---F */
#define NV_NVLSTAT_LNK0_INTR_RX_FAULT_SUBLINK_CHANGE 16:16 /* R---F */
#define NV_NVLSTAT_LNK0_INTR_RX_FAULT_DL_PROTOCOL 20:20 /* R---F */
#define NV_NVLSTAT_LNK0_INTR_RX_FAULT_SHORT_ERROR_RATE 21:21 /* R---F */
#define NV_NVLSTAT_LNK0_INTR_RX_FAULT_LONG_ERROR_RATE 22:22 /* R---F */
#define NV_NVLSTAT_LNK0_INTR_LTSSM_PROTOCOL 29:29 /* R---F */
#define NV_NVLSTAT_LNK1 0x00000011 /* R--4R */
#define NV_NVLSTAT_LNK1_ERROR_COUNT1_RECOVERY_EVENTS_VALUE 30:0 /* R---F */
#define NV_NVLSTAT_LNK1_ERROR_COUNT1_RECOVERY_EVENTS_VALUE_SRCOVF 0x000003ff /* R---V */
#define NV_NVLSTAT_LNK1_ERROR_COUNT1_RECOVERY_EVENTS_OVER 31:31 /* R---F */
#define NV_NVLSTAT_LNK1_ERROR_COUNT1_RECOVERY_EVENTS_OVER_OVER 0x1 /* R---V */
#define NV_NVLSTAT_LNK1_ERROR_COUNT1_RECOVERY_EVENTS_OVER_OKAY 0x0 /* R---V */
#define NV_NVLSTAT_LNK2 0x00000012 /* R--4R */
#define NV_NVLSTAT_LNK2_RXDET_LINK_STATUS 9:8 /* R---F */
#define NV_NVLSTAT_LNK2_RXDET_LINK_STATUS_UNINITIALIZED 0x0 /* R---V */
#define NV_NVLSTAT_LNK2_RXDET_LINK_STATUS_SEARCH 0x1 /* R---V */
#define NV_NVLSTAT_LNK2_RXDET_LINK_STATUS_FOUND 0x2 /* R---V */
#define NV_NVLSTAT_LNK2_RXDET_LINK_STATUS_TIMEOUT 0x3 /* R---V */
#define NV_NVLSTAT_LNK2_RXDET_LANE_STATUS 7:0 /* R---F */
#define NV_NVLSTAT_LNK2_RXDET_LANE_STATUS_FOUND 0x0f /* R---V */
#define NV_NVLSTAT_LNK3 0x00000013 /* R--4R */
#define NV_NVLSTAT_LNK3_LINERATE 23:0 /* R---F */
#define NV_NVLSTAT_LNK4 0x00000014 /* R--4R */
#define NV_NVLSTAT_LNK4_LINKCLOCK 15:0 /* R---F */
#define NV_NVLSTAT_LNK5 0x00000015 /* R--4R */
#define NV_NVLSTAT_LNK5_DATARATE 31:0 /* R---F */
#define NV_NVLSTAT_TX01 0x00000021 /* R--4R */
#define NV_NVLSTAT_TX01_COUNT_TX_STATE_NVHS_VALUE 30:0 /* R---F */
#define NV_NVLSTAT_TX01_COUNT_TX_STATE_NVHS_VALUE_SRCOVF 0x0000ffff /* R---V */
#define NV_NVLSTAT_TX01_COUNT_TX_STATE_NVHS_OVER 31:31 /* R---F */
#define NV_NVLSTAT_TX01_COUNT_TX_STATE_NVHS_OVER_OVER 0x1 /* R---V */
#define NV_NVLSTAT_TX01_COUNT_TX_STATE_NVHS_OVER_OKAY 0x0 /* R---V */
#define NV_NVLSTAT_TX02 0x00000022 /* R--4R */
#define NV_NVLSTAT_TX02_COUNT_TX_STATE_OTHER_VALUE 30:0 /* R---F */
#define NV_NVLSTAT_TX02_COUNT_TX_STATE_OTHER_VALUE_SRCOVF 0x0000ffff /* R---V */
#define NV_NVLSTAT_TX02_COUNT_TX_STATE_OTHER_OVER 31:31 /* R---F */
#define NV_NVLSTAT_TX02_COUNT_TX_STATE_OTHER_OVER_OVER 0x1 /* R---V */
#define NV_NVLSTAT_TX02_COUNT_TX_STATE_OTHER_OVER_OKAY 0x0 /* R---V */
#define NV_NVLSTAT_TX03 0x00000023 /* R--4R */
#define NV_NVLSTAT_TX03_DELAY_LCL_LP_ENTER_VALUE 30:0 /* R---F */
#define NV_NVLSTAT_TX03_DELAY_LCL_LP_ENTER_VALUE_SRCOVF 0x000000ff /* R---V */
#define NV_NVLSTAT_TX03_DELAY_LCL_LP_ENTER_OVER 31:31 /* R---F */
#define NV_NVLSTAT_TX03_DELAY_LCL_LP_ENTER_OVER_OVER 0x1 /* R---V */
#define NV_NVLSTAT_TX03_DELAY_LCL_LP_ENTER_OVER_OKAY 0x0 /* R---V */
#define NV_NVLSTAT_TX04 0x00000024 /* R--4R */
#define NV_NVLSTAT_TX04_DELAY_LCL_LP_EXIT_VALUE 30:0 /* R---F */
#define NV_NVLSTAT_TX04_DELAY_LCL_LP_EXIT_VALUE_SRCOVF 0x000000ff /* R---V */
#define NV_NVLSTAT_TX04_DELAY_LCL_LP_EXIT_OVER 31:31 /* R---F */
#define NV_NVLSTAT_TX04_DELAY_LCL_LP_EXIT_OVER_OVER 0x1 /* R---V */
#define NV_NVLSTAT_TX04_DELAY_LCL_LP_EXIT_OVER_OKAY 0x0 /* R---V */
#define NV_NVLSTAT_TX05 0x00000025 /* R--4R */
#define NV_NVLSTAT_TX05_NUM_LCL_LP_EXIT_VALUE 30:0 /* R---F */
#define NV_NVLSTAT_TX05_NUM_LCL_LP_EXIT_VALUE_SRCOVF 0x0000ffff /* R---V */
#define NV_NVLSTAT_TX05_NUM_LCL_LP_EXIT_OVER 31:31 /* R---F */
#define NV_NVLSTAT_TX05_NUM_LCL_LP_EXIT_OVER_OVER 0x1 /* R---V */
#define NV_NVLSTAT_TX05_NUM_LCL_LP_EXIT_OVER_OKAY 0x0 /* R---V */
#define NV_NVLSTAT_TX06 0x00000026 /* R--4R */
#define NV_NVLSTAT_TX06_NUM_LCL_LP_ENTER_VALUE 30:0 /* R---F */
#define NV_NVLSTAT_TX06_NUM_LCL_LP_ENTER_VALUE_SRCOVF 0x0000ffff /* R---V */
#define NV_NVLSTAT_TX06_NUM_LCL_LP_ENTER_OVER 31:31 /* R---F */
#define NV_NVLSTAT_TX06_NUM_LCL_LP_ENTER_OVER_OVER 0x1 /* R---V */
#define NV_NVLSTAT_TX06_NUM_LCL_LP_ENTER_OVER_OKAY 0x0 /* R---V */
#define NV_NVLSTAT_TX07 0x00000027 /* R--4R */
#define NV_NVLSTAT_TX07_DELAY_LCL_FB_EXIT_OTHER_VALUE 30:0 /* R---F */
#define NV_NVLSTAT_TX07_DELAY_LCL_FB_EXIT_OTHER_VALUE_SRCOVF 0x000000ff /* R---V */
#define NV_NVLSTAT_TX07_DELAY_LCL_FB_EXIT_OTHER_OVER 31:31 /* R---F */
#define NV_NVLSTAT_TX07_DELAY_LCL_FB_EXIT_OTHER_OVER_OVER 0x1 /* R---V */
#define NV_NVLSTAT_TX07_DELAY_LCL_FB_EXIT_OTHER_OVER_OKAY 0x0 /* R---V */
#define NV_NVLSTAT_TX08 0x00000028 /* R--4R */
#define NV_NVLSTAT_TX08_DELAY_LCL_FB_ENTER_OTHER_VALUE 30:0 /* R---F */
#define NV_NVLSTAT_TX08_DELAY_LCL_FB_ENTER_OTHER_VALUE_SRCOVF 0x000000ff /* R---V */
#define NV_NVLSTAT_TX08_DELAY_LCL_FB_ENTER_OTHER_OVER 31:31 /* R---F */
#define NV_NVLSTAT_TX08_DELAY_LCL_FB_ENTER_OTHER_OVER_OVER 0x1 /* R---V */
#define NV_NVLSTAT_TX08_DELAY_LCL_FB_ENTER_OTHER_OVER_OKAY 0x0 /* R---V */
#define NV_NVLSTAT_TX09 0x00000029 /* R--4R */
#define NV_NVLSTAT_TX09_REPLAY_EVENTS_VALUE 30:0 /* R---F */
#define NV_NVLSTAT_TX09_REPLAY_EVENTS_VALUE_SRCOVF 0x000000ff /* R---V */
#define NV_NVLSTAT_TX09_REPLAY_EVENTS_OVER 31:31 /* R---F */
#define NV_NVLSTAT_TX09_REPLAY_EVENTS_OVER_OVER 0x1 /* R---V */
#define NV_NVLSTAT_TX09_REPLAY_EVENTS_OVER_OKAY 0x0 /* R---V */
#define NV_NVLSTAT_TX10 0x0000002a /* R--4R */
#define NV_NVLSTAT_TX10_COUNT_TX_STATE_SLEEP_VALUE 30:0 /* R---F */
#define NV_NVLSTAT_TX10_COUNT_TX_STATE_SLEEP_VALUE_SRCOVF 0x0000ffff /* R---V */
#define NV_NVLSTAT_TX10_COUNT_TX_STATE_SLEEP_OVER 31:31 /* R---F */
#define NV_NVLSTAT_TX10_COUNT_TX_STATE_SLEEP_OVER_OVER 0x1 /* R---V */
#define NV_NVLSTAT_TX10_COUNT_TX_STATE_SLEEP_OVER_OKAY 0x0 /* R---V */
#define NV_NVLSTAT_TX11 0x0000002b /* R--4R */
#define NV_NVLSTAT_TX11_NUM_RMT_LP_EXIT_VALUE 30:0 /* R---F */
#define NV_NVLSTAT_TX11_NUM_RMT_LP_EXIT_VALUE_SRCOVF 0x0000ffff /* R---V */
#define NV_NVLSTAT_TX11_NUM_RMT_LP_EXIT_OVER 31:31 /* R---F */
#define NV_NVLSTAT_TX11_NUM_RMT_LP_EXIT_OVER_OVER 0x1 /* R---V */
#define NV_NVLSTAT_TX11_NUM_RMT_LP_EXIT_OVER_OKAY 0x0 /* R---V */
#define NV_NVLSTAT_TX12 0x0000002c /* R--4R */
#define NV_NVLSTAT_TX12_TX_LPOCC_HIST 31:0 /* R---F */
#define NV_NVLSTAT_TX13 0x0000002d /* R--4R */
#define NV_NVLSTAT_TX13_TX_LPOCC_HIST 31:0 /* R---F */
#define NV_NVLSTAT_TX14 0x0000002e /* R--4R */
#define NV_NVLSTAT_TX14_TX_LPEXIT_HIST 31:0 /* R---F */
#define NV_NVLSTAT_TX15 0x0000002f /* R--4R */
#define NV_NVLSTAT_TX15_TX_LPEXIT_HIST 31:0 /* R---F */
#define NV_NVLSTAT_RX00 0x00000040 /* R--4R */
#define NV_NVLSTAT_RX00_REPLAY_EVENTS_VALUE 30:0 /* R---F */
#define NV_NVLSTAT_RX00_REPLAY_EVENTS_VALUE_SRCOVF 0x0000ffff /* R---V */
#define NV_NVLSTAT_RX00_REPLAY_EVENTS_OVER 31:31 /* R---F */
#define NV_NVLSTAT_RX00_REPLAY_EVENTS_OVER_OVER 0x1 /* R---V */
#define NV_NVLSTAT_RX00_REPLAY_EVENTS_OVER_OKAY 0x0 /* R---V */
#define NV_NVLSTAT_RX01 0x00000041 /* R--4R */
#define NV_NVLSTAT_RX01_FLIT_CRC_ERRORS_VALUE 30:0 /* R---F */
#define NV_NVLSTAT_RX01_FLIT_CRC_ERRORS_VALUE_SRCOVF 0x7fffffff /* R---V */
#define NV_NVLSTAT_RX01_FLIT_CRC_ERRORS_OVER 31:31 /* R---F */
#define NV_NVLSTAT_RX01_FLIT_CRC_ERRORS_OVER_OVER 0x1 /* R---V */
#define NV_NVLSTAT_RX01_FLIT_CRC_ERRORS_OVER_OKAY 0x0 /* R---V */
#define NV_NVLSTAT_RX02 0x00000042 /* R--4R */
#define NV_NVLSTAT_RX02_MASKED_CRC_ERRORS_VALUE 30:0 /* R---F */
#define NV_NVLSTAT_RX02_MASKED_CRC_ERRORS_VALUE_SRCOVF 0x7fffffff /* R---V */
#define NV_NVLSTAT_RX02_MASKED_CRC_ERRORS_OVER 31:31 /* R---F */
#define NV_NVLSTAT_RX02_MASKED_CRC_ERRORS_OVER_OVER 0x1 /* R---V */
#define NV_NVLSTAT_RX02_MASKED_CRC_ERRORS_OVER_OKAY 0x0 /* R---V */
#define NV_NVLSTAT_RX03 0x00000043 /* R--4R */
#define NV_NVLSTAT_RX03_DELAY_RMT_LP_ENTER_VALUE 30:0 /* R---F */
#define NV_NVLSTAT_RX03_DELAY_RMT_LP_ENTER_VALUE_SRCOVF 0x000000ff /* R---V */
#define NV_NVLSTAT_RX03_DELAY_RMT_LP_ENTER_OVER 31:31 /* R---F */
#define NV_NVLSTAT_RX03_DELAY_RMT_LP_ENTER_OVER_OVER 0x1 /* R---V */
#define NV_NVLSTAT_RX03_DELAY_RMT_LP_ENTER_OVER_OKAY 0x0 /* R---V */
#define NV_NVLSTAT_RX04 0x00000044 /* R--4R */
#define NV_NVLSTAT_RX04_DELAY_RMT_LP_EXIT_VALUE 30:0 /* R---F */
#define NV_NVLSTAT_RX04_DELAY_RMT_LP_EXIT_VALUE_SRCOVF 0x000000ff /* R---V */
#define NV_NVLSTAT_RX04_DELAY_RMT_LP_EXIT_OVER 31:31 /* R---F */
#define NV_NVLSTAT_RX04_DELAY_RMT_LP_EXIT_OVER_OVER 0x1 /* R---V */
#define NV_NVLSTAT_RX04_DELAY_RMT_LP_EXIT_OVER_OKAY 0x0 /* R---V */
#define NV_NVLSTAT_RX05 0x00000045 /* R--4R */
#define NV_NVLSTAT_RX05_DELAY_RMT_FB_ENTER_VALUE 30:0 /* R---F */
#define NV_NVLSTAT_RX05_DELAY_RMT_FB_ENTER_VALUE_SRCOVF 0x000000ff /* R---V */
#define NV_NVLSTAT_RX05_DELAY_RMT_FB_ENTER_OVER 31:31 /* R---F */
#define NV_NVLSTAT_RX05_DELAY_RMT_FB_ENTER_OVER_OVER 0x1 /* R---V */
#define NV_NVLSTAT_RX05_DELAY_RMT_FB_ENTER_OVER_OKAY 0x0 /* R---V */
#define NV_NVLSTAT_RX06 0x00000046 /* R--4R */
#define NV_NVLSTAT_RX06_DELAY_RMT_FB_EXIT_VALUE 30:0 /* R---F */
#define NV_NVLSTAT_RX06_DELAY_RMT_FB_EXIT_VALUE_SRCOVF 0x000000ff /* R---V */
#define NV_NVLSTAT_RX06_DELAY_RMT_FB_EXIT_OVER 31:31 /* R---F */
#define NV_NVLSTAT_RX06_DELAY_RMT_FB_EXIT_OVER_OVER 0x1 /* R---V */
#define NV_NVLSTAT_RX06_DELAY_RMT_FB_EXIT_OVER_OKAY 0x0 /* R---V */
#define NV_NVLSTAT_RX08 0x00000048 /* R--4R */
#define NV_NVLSTAT_RX08_ERRORLOG_ERR_CNT_MULTI 7:0 /* R---F */
#define NV_NVLSTAT_RX09 0x00000049 /* R--4R */
#define NV_NVLSTAT_RX09_ERRORLOG_ERR_CNT_7 31:24 /* R---F */
#define NV_NVLSTAT_RX09_ERRORLOG_ERR_CNT_6 23:16 /* R---F */
#define NV_NVLSTAT_RX09_ERRORLOG_ERR_CNT_5 15:8 /* R---F */
#define NV_NVLSTAT_RX09_ERRORLOG_ERR_CNT_4 7:0 /* R---F */
#define NV_NVLSTAT_RX10 0x0000004a /* R--4R */
#define NV_NVLSTAT_RX10_ERRORLOG_ERR_CNT_3 31:24 /* R---F */
#define NV_NVLSTAT_RX10_ERRORLOG_ERR_CNT_2 23:16 /* R---F */
#define NV_NVLSTAT_RX10_ERRORLOG_ERR_CNT_1 15:8 /* R---F */
#define NV_NVLSTAT_RX10_ERRORLOG_ERR_CNT_0 7:0 /* R---F */
#define NV_NVLSTAT_RX11 0x0000004b /* R--4R */
#define NV_NVLSTAT_RX11_ECC_DEC_FAILED_VALUE 30:0 /* R---F */
#define NV_NVLSTAT_RX11_ECC_DEC_FAILED_VALUE_SRCOVF 0x00ffffff /* R---V */
#define NV_NVLSTAT_RX11_ECC_DEC_FAILED_OVER 31:31 /* R---F */
#define NV_NVLSTAT_RX11_ECC_DEC_FAILED_OVER_OVER 0x1 /* R---V */
#define NV_NVLSTAT_RX11_ECC_DEC_FAILED_OVER_OKAY 0x0 /* R---V */
#define NV_NVLSTAT_RX12 0x0000004c /* R--4R */
#define NV_NVLSTAT_RX12_ECC_CORRECTED_ERR_L0_VALUE 30:0 /* R---F */
#define NV_NVLSTAT_RX12_ECC_CORRECTED_ERR_L0_VALUE_SRCOVF 0x7fffffff /* R---V */
#define NV_NVLSTAT_RX12_ECC_CORRECTED_ERR_L0_OVER 31:31 /* R---F */
#define NV_NVLSTAT_RX12_ECC_CORRECTED_ERR_L0_OVER_OVER 0x1 /* R---V */
#define NV_NVLSTAT_RX12_ECC_CORRECTED_ERR_L0_OVER_OKAY 0x0 /* R---V */
#define NV_NVLSTAT_RX13 0x0000004d /* R--4R */
#define NV_NVLSTAT_RX13_ECC_CORRECTED_ERR_L1_VALUE 30:0 /* R---F */
#define NV_NVLSTAT_RX13_ECC_CORRECTED_ERR_L1_VALUE_SRCOVF 0x7fffffff /* R---V */
#define NV_NVLSTAT_RX13_ECC_CORRECTED_ERR_L1_OVER 31:31 /* R---F */
#define NV_NVLSTAT_RX13_ECC_CORRECTED_ERR_L1_OVER_OVER 0x1 /* R---V */
#define NV_NVLSTAT_RX13_ECC_CORRECTED_ERR_L1_OVER_OKAY 0x0 /* R---V */
#define NV_NVLSTAT_TR00 0x00000090 /* R--4R */
#define NV_NVLSTAT_TR00_DATA 31:0 /* R---F */
#define NV_NVLSTAT_TR01 0x00000091 /* R--4R */
#define NV_NVLSTAT_TR01_DATA 31:0 /* R---F */
#define NV_NVLSTAT_TR02 0x00000092 /* R--4R */
#define NV_NVLSTAT_TR02_DATA 31:0 /* R---F */
#define NV_NVLSTAT_TR03 0x00000093 /* R--4R */
#define NV_NVLSTAT_TR03_DATA 31:0 /* R---F */
#define NV_NVLSTAT_TR04 0x00000094 /* R--4R */
#define NV_NVLSTAT_TR04_DATA 31:0 /* R---F */
#define NV_NVLSTAT_TR05 0x00000095 /* R--4R */
#define NV_NVLSTAT_TR05_DATA 31:0 /* R---F */
#define NV_NVLSTAT_TR06 0x00000096 /* R--4R */
#define NV_NVLSTAT_TR06_DATA 31:0 /* R---F */
#define NV_NVLSTAT_TR07 0x00000097 /* R--4R */
#define NV_NVLSTAT_TR07_DATA 31:0 /* R---F */
#define NV_NVLSTAT_TR08 0x00000098 /* R--4R */
#define NV_NVLSTAT_TR08_DATA 31:0 /* R---F */
#define NV_NVLSTAT_TR09 0x00000099 /* R--4R */
#define NV_NVLSTAT_TR09_DATA 31:0 /* R---F */
#define NV_NVLSTAT_TR10 0x0000009a /* R--4R */
#define NV_NVLSTAT_TR10_DATA 31:0 /* R---F */
#define NV_NVLSTAT_TR11 0x0000009b /* R--4R */
#define NV_NVLSTAT_TR11_DATA 31:0 /* R---F */
#define NV_NVLSTAT_TR12 0x0000009c /* R--4R */
#define NV_NVLSTAT_TR12_DATA 31:0 /* R---F */
#define NV_NVLSTAT_TR13 0x0000009d /* R--4R */
#define NV_NVLSTAT_TR13_DATA 31:0 /* R---F */
#define NV_NVLSTAT_TR14 0x0000009e /* R--4R */
#define NV_NVLSTAT_TR14_DATA 31:0 /* R---F */
#define NV_NVLSTAT_TR15 0x0000009f /* R--4R */
#define NV_NVLSTAT_TR15_DATA 31:0 /* R---F */
#define NV_NVLSTAT_TR16 0x000000a0 /* R--4R */
#define NV_NVLSTAT_TR16_L0FOM 15:0 /* R---F */
#define NV_NVLSTAT_TR16_L1FOM 31:16 /* R---F */
#define NV_NVLSTAT_TR17 0x000000a1 /* R--4R */
#define NV_NVLSTAT_TR17_L2FOM 15:0 /* R---F */
#define NV_NVLSTAT_TR17_L3FOM 31:16 /* R---F */
#define NV_NVLSTAT_DB00 0x00000080 /* R--4R */
#define NV_NVLSTAT_DB00_ERRORS_INJECTED_VALUE 30:0 /* R---F */
#define NV_NVLSTAT_DB00_ERRORS_INJECTED_VALUE_SRCOVF 0x7fffffff /* R---V */
#define NV_NVLSTAT_DB00_ERRORS_INJECTED_OVER 31:31 /* R---F */
#define NV_NVLSTAT_DB00_ERRORS_INJECTED_OVER_OVER 0x1 /* R---V */
#define NV_NVLSTAT_DB00_ERRORS_INJECTED_OVER_OKAY 0x0 /* R---V */
#define NV_NVLSTAT_DB01 0x00000081 /* R--4R */
#define NV_NVLSTAT_DB01_ERROR_COUNT_ERR_LANECRC_L3 31:24 /* R---F */
#define NV_NVLSTAT_DB01_ERROR_COUNT_ERR_LANECRC_L2 23:16 /* R---F */
#define NV_NVLSTAT_DB01_ERROR_COUNT_ERR_LANECRC_L1 15:8 /* R---F */
#define NV_NVLSTAT_DB01_ERROR_COUNT_ERR_LANECRC_L0 7:0 /* R---F */
#define NV_NVLSTAT_DB02 0x00000082 /* R--4R */
#define NV_NVLSTAT_DB02_ERROR_COUNT_ERR_LANECRC_L7 31:24 /* R---F */
#define NV_NVLSTAT_DB02_ERROR_COUNT_ERR_LANECRC_L6 23:16 /* R---F */
#define NV_NVLSTAT_DB02_ERROR_COUNT_ERR_LANECRC_L5 15:8 /* R---F */
#define NV_NVLSTAT_DB02_ERROR_COUNT_ERR_LANECRC_L4 7:0 /* R---F */
#define NV_NVLSTAT_DB03 0x00000083 /* R--4R */
#define NV_NVLSTAT_DB03_RXSLSM_ERR_CNTL_CLK_SWITCH_ERR 31:31 /* R---F */
#define NV_NVLSTAT_DB03_RXSLSM_ERR_CNTL_OFF2SAFE_LINK_DET_ERR 2:2 /* R---F */
#define NV_NVLSTAT_DB03_RXSLSM_ERR_CNTL_CONST_DET_ERR 1:1 /* R---F */
#define NV_NVLSTAT_DB04 0x00000084 /* R--4R */
#define NV_NVLSTAT_DB04_RXSLSM_ERR_CNTL_E2S_STROBE_NO_LD_ERR 23:23 /* R---F */
#define NV_NVLSTAT_DB04_RXSLSM_ERR_CNTL_H2S_STROBE_NO_LD_ERR 22:22 /* R---F */
#define NV_NVLSTAT_DB04_RXSLSM_ERR_CNTL_02S_STROBE_NO_LD_ERR 21:21 /* R---F */
#define NV_NVLSTAT_DB04_RXSLSM_ERR_CNTL_E2S_SD_NO_LD_ERR 20:20 /* R---F */
#define NV_NVLSTAT_DB04_RXSLSM_ERR_CNTL_H2S_SD_NO_LD_ERR 19:19 /* R---F */
#define NV_NVLSTAT_DB04_RXSLSM_ERR_CNTL_O2S_SD_NO_LD_ERR 18:18 /* R---F */
#define NV_NVLSTAT_DB04_RXSLSM_ERR_CNTL_RC_DEADLINE_ERR 15:15 /* R---F */
#define NV_NVLSTAT_DB04_RXSLSM_ERR_CNTL_RC_TXPWR_ERR 14:14 /* R---F */
#define NV_NVLSTAT_DB04_RXSLSM_ERR_CNTL_RC_RXPWR_ERR 13:13 /* R---F */
#define NV_NVLSTAT_DB04_RXSLSM_ERR_CNTL_E2SAFE_LD_ERR 12:12 /* R---F */
#define NV_NVLSTAT_DB04_RXSLSM_ERR_CNTL_SAFE_NO_LD_ERR 11:11 /* R---F */
#define NV_NVLSTAT_DB04_RXSLSM_ERR_CNTL_FENCE_ERR 10:10 /* R---F */
#define NV_NVLSTAT_DB04_RXSLSM_ERR_CNTL_HS2SAFE_LINK_DET_ERR 9:9 /* R---F */
#define NV_NVLSTAT_DB04_RXSLSM_ERR_CNTL_TRAIN2SAFE_LINK_DET_ERR 8:8 /* R---F */
#define NV_NVLSTAT_DB04_RXSLSM_ERR_CNTL_FIFO_SKEW_ERR 7:7 /* R---F */
#define NV_NVLSTAT_DB04_RXSLSM_ERR_CNTL_SYM_ALIGN_END_ERR 6:6 /* R---F */
#define NV_NVLSTAT_DB04_RXSLSM_ERR_CNTL_SYM_LOCK_ERR 5:5 /* R---F */
#define NV_NVLSTAT_DB04_RXSLSM_ERR_CNTL_SCRAM_LOCK_ERR 4:4 /* R---F */
#define NV_NVLSTAT_DB04_RXSLSM_ERR_CNTL_SAFE2NO_LINK_DET_ERR 3:3 /* R---F */
#define NV_NVLSTAT_DB04_RXSLSM_ERR_CNTL_OFF2SAFE_LINK_DET_ERR 2:2 /* R---F */
#define NV_NVLSTAT_DB04_RXSLSM_ERR_CNTL_CONST_DET_ERR 1:1 /* R---F */
#define NV_NVLSTAT_DB04_RXSLSM_ERR_CNTL_FIFO_DRAIN_ERR 0:0 /* R---F */
#define NV_NVLSTAT_DB05 0x00000085 /* R--4R */
#define NV_NVLSTAT_DB05_TIMEOUT_LOG_SYM_LOCK_LANE 31:24 /* R---F */
#define NV_NVLSTAT_DB05_TIMEOUT_LOG_SCRAM_LOCK_LANE 23:16 /* R---F */
#define NV_NVLSTAT_DB05_TIMEOUT_LOG_CONST_DET_LANE 15:8 /* R---F */
#define NV_NVLSTAT_DB05_TIMEOUT_LOG_FIFO_DRAIN_LANE 7:0 /* R---F */
#define NV_NVLSTAT_DB06 0x00000086 /* R--4R */
#define NV_NVLSTAT_DB06_TIMEOUT_LOG_SYM_ALIGN_END_LANE 31:24 /* R---F */
#define NV_NVLSTAT_DB06_TIMEOUT_LOG_FIFO_SKEW_LANE 23:16 /* R---F */
#define NV_NVLSTAT_DB07 0x00000087 /* R--4R */
#define NV_NVLSTAT_DB07_FIFO_STATUS_RX_0_ENTRIES_USED_3 29:24 /* R---F */
#define NV_NVLSTAT_DB07_FIFO_STATUS_RX_0_ENTRIES_USED_2 21:16 /* R---F */
#define NV_NVLSTAT_DB07_FIFO_STATUS_RX_0_ENTRIES_USED_1 13:8 /* R---F */
#define NV_NVLSTAT_DB07_FIFO_STATUS_RX_0_ENTRIES_USED_0 5:0 /* R---F */
#define NV_NVLSTAT_DB08 0x00000088 /* R--4R */
#define NV_NVLSTAT_DB08_FIFO_STATUS_RX_0_ENTRIES_USED_7 29:24 /* R---F */
#define NV_NVLSTAT_DB08_FIFO_STATUS_RX_0_ENTRIES_USED_6 21:16 /* R---F */
#define NV_NVLSTAT_DB08_FIFO_STATUS_RX_0_ENTRIES_USED_5 13:8 /* R---F */
#define NV_NVLSTAT_DB08_FIFO_STATUS_RX_0_ENTRIES_USED_4 5:0 /* R---F */
#define NV_NVLSTAT_DB09 0x00000089 /* R--4R */
#define NV_NVLSTAT_DB09_SLSM_STATUS_RX_SURPRISE_LD_CNT_VALUE 30:0 /* R---F */
#define NV_NVLSTAT_DB09_SLSM_STATUS_RX_SURPRISE_LD_CNT_VALUE_SRCOVF 0x000000ff /* R---V */
#define NV_NVLSTAT_DB09_SLSM_STATUS_RX_SURPRISE_LD_CNT_OVER 31:31 /* R---F */
#define NV_NVLSTAT_DB09_SLSM_STATUS_RX_SURPRISE_LD_CNT_OVER_OVER 0x1 /* R---V */
#define NV_NVLSTAT_DB09_SLSM_STATUS_RX_SURPRISE_LD_CNT_OVER_OKAY 0x0 /* R---V */
#define NV_NVLSTAT_DB10 0x0000008a /* R--4R */
#define NV_NVLSTAT_DB10_DATA 31:0 /* R---F */
#define NV_NVLSTAT_DB11 0x0000008b /* R--4R */
#define NV_NVLSTAT_DB11_COUNT_PHY_REFRESH_PASS 15:0 /* R---F */
#define NV_NVLSTAT_DB11_COUNT_PHY_REFRESH_FAIL 31:16 /* R---F */
#define NV_NVLSTAT_MN00 0x000000ff /* R--4R */
#define NV_NVLSTAT_MN00_LINK_INTR_SUBCODE 15:8 /* R---F */
#define NV_NVLSTAT_MN00_LINK_INTR_CODE 7:0 /* R---F */
#define NV_MINION_INBAND_SEND_DATA_BUFFER_SIZE 7:0
#define NV_MINION_INBAND_SEND_DATA_FLAGS 23:16
#endif // __ls10_dev_minion_ip_addendum_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the Software),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __ls10_dev_multicasttstate_ip_h__
#define __ls10_dev_multicasttstate_ip_h__
/* This file is autogenerated. Do not edit */
#define NV_MULTICASTTSTATE 0x000027ff:0x00002000 /* RW--D */
#define NV_MULTICASTTSTATE_ERR_STATUS_0 0x00002400 /* RW-4R */
#define NV_MULTICASTTSTATE_ERR_STATUS_0_TAGPOOL_ECC_LIMIT_ERR 2:2 /* RWDVF */
#define NV_MULTICASTTSTATE_ERR_STATUS_0_TAGPOOL_ECC_LIMIT_ERR__ONWRITE "oneToClear" /* */
#define NV_MULTICASTTSTATE_ERR_STATUS_0_TAGPOOL_ECC_LIMIT_ERR_NONE 0x00000000 /* RWD-V */
#define NV_MULTICASTTSTATE_ERR_STATUS_0_TAGPOOL_ECC_LIMIT_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_MULTICASTTSTATE_ERR_STATUS_0_TAGPOOL_ECC_DBE_ERR 3:3 /* RWDVF */
#define NV_MULTICASTTSTATE_ERR_STATUS_0_TAGPOOL_ECC_DBE_ERR__ONWRITE "oneToClear" /* */
#define NV_MULTICASTTSTATE_ERR_STATUS_0_TAGPOOL_ECC_DBE_ERR_NONE 0x00000000 /* RWD-V */
#define NV_MULTICASTTSTATE_ERR_STATUS_0_TAGPOOL_ECC_DBE_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_MULTICASTTSTATE_ERR_STATUS_0_CRUMBSTORE_BUF_OVERWRITE_ERR 16:16 /* RWDVF */
#define NV_MULTICASTTSTATE_ERR_STATUS_0_CRUMBSTORE_BUF_OVERWRITE_ERR__ONWRITE "oneToClear" /* */
#define NV_MULTICASTTSTATE_ERR_STATUS_0_CRUMBSTORE_BUF_OVERWRITE_ERR_NONE 0x00000000 /* RWD-V */
#define NV_MULTICASTTSTATE_ERR_STATUS_0_CRUMBSTORE_BUF_OVERWRITE_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_MULTICASTTSTATE_ERR_STATUS_0_CRUMBSTORE_ECC_LIMIT_ERR 18:18 /* RWDVF */
#define NV_MULTICASTTSTATE_ERR_STATUS_0_CRUMBSTORE_ECC_LIMIT_ERR__ONWRITE "oneToClear" /* */
#define NV_MULTICASTTSTATE_ERR_STATUS_0_CRUMBSTORE_ECC_LIMIT_ERR_NONE 0x00000000 /* RWD-V */
#define NV_MULTICASTTSTATE_ERR_STATUS_0_CRUMBSTORE_ECC_LIMIT_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_MULTICASTTSTATE_ERR_STATUS_0_CRUMBSTORE_ECC_DBE_ERR 19:19 /* RWDVF */
#define NV_MULTICASTTSTATE_ERR_STATUS_0_CRUMBSTORE_ECC_DBE_ERR__ONWRITE "oneToClear" /* */
#define NV_MULTICASTTSTATE_ERR_STATUS_0_CRUMBSTORE_ECC_DBE_ERR_NONE 0x00000000 /* RWD-V */
#define NV_MULTICASTTSTATE_ERR_STATUS_0_CRUMBSTORE_ECC_DBE_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_MULTICASTTSTATE_ERR_STATUS_0_CRUMBSTORE_MCTO_ERR 20:20 /* RWDVF */
#define NV_MULTICASTTSTATE_ERR_STATUS_0_CRUMBSTORE_MCTO_ERR__ONWRITE "oneToClear" /* */
#define NV_MULTICASTTSTATE_ERR_STATUS_0_CRUMBSTORE_MCTO_ERR_NONE 0x00000000 /* RWD-V */
#define NV_MULTICASTTSTATE_ERR_STATUS_0_CRUMBSTORE_MCTO_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_MULTICASTTSTATE_ERR_LOG_EN_0 0x00002404 /* RW-4R */
#define NV_MULTICASTTSTATE_ERR_LOG_EN_0_TAGPOOL_ECC_LIMIT_ERR 2:2 /* RWEVF */
#define NV_MULTICASTTSTATE_ERR_LOG_EN_0_TAGPOOL_ECC_LIMIT_ERR__PROD 0x00000001 /* RW--V */
#define NV_MULTICASTTSTATE_ERR_LOG_EN_0_TAGPOOL_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_MULTICASTTSTATE_ERR_LOG_EN_0_TAGPOOL_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_MULTICASTTSTATE_ERR_LOG_EN_0_TAGPOOL_ECC_DBE_ERR 3:3 /* RWEVF */
#define NV_MULTICASTTSTATE_ERR_LOG_EN_0_TAGPOOL_ECC_DBE_ERR__PROD 0x00000001 /* RW--V */
#define NV_MULTICASTTSTATE_ERR_LOG_EN_0_TAGPOOL_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_MULTICASTTSTATE_ERR_LOG_EN_0_TAGPOOL_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_MULTICASTTSTATE_ERR_LOG_EN_0_CRUMBSTORE_BUF_OVERWRITE_ERR 16:16 /* RWEVF */
#define NV_MULTICASTTSTATE_ERR_LOG_EN_0_CRUMBSTORE_BUF_OVERWRITE_ERR__PROD 0x00000001 /* RW--V */
#define NV_MULTICASTTSTATE_ERR_LOG_EN_0_CRUMBSTORE_BUF_OVERWRITE_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_MULTICASTTSTATE_ERR_LOG_EN_0_CRUMBSTORE_BUF_OVERWRITE_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_MULTICASTTSTATE_ERR_LOG_EN_0_CRUMBSTORE_ECC_LIMIT_ERR 18:18 /* RWEVF */
#define NV_MULTICASTTSTATE_ERR_LOG_EN_0_CRUMBSTORE_ECC_LIMIT_ERR__PROD 0x00000001 /* RW--V */
#define NV_MULTICASTTSTATE_ERR_LOG_EN_0_CRUMBSTORE_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_MULTICASTTSTATE_ERR_LOG_EN_0_CRUMBSTORE_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_MULTICASTTSTATE_ERR_LOG_EN_0_CRUMBSTORE_ECC_DBE_ERR 19:19 /* RWEVF */
#define NV_MULTICASTTSTATE_ERR_LOG_EN_0_CRUMBSTORE_ECC_DBE_ERR__PROD 0x00000001 /* RW--V */
#define NV_MULTICASTTSTATE_ERR_LOG_EN_0_CRUMBSTORE_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_MULTICASTTSTATE_ERR_LOG_EN_0_CRUMBSTORE_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_MULTICASTTSTATE_ERR_LOG_EN_0_CRUMBSTORE_MCTO_ERR 20:20 /* RWEVF */
#define NV_MULTICASTTSTATE_ERR_LOG_EN_0_CRUMBSTORE_MCTO_ERR__PROD 0x00000001 /* RW--V */
#define NV_MULTICASTTSTATE_ERR_LOG_EN_0_CRUMBSTORE_MCTO_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_MULTICASTTSTATE_ERR_LOG_EN_0_CRUMBSTORE_MCTO_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_MULTICASTTSTATE_ERR_FATAL_REPORT_EN_0 0x00002408 /* RW-4R */
#define NV_MULTICASTTSTATE_ERR_FATAL_REPORT_EN_0_TAGPOOL_ECC_LIMIT_ERR 2:2 /* RWEVF */
#define NV_MULTICASTTSTATE_ERR_FATAL_REPORT_EN_0_TAGPOOL_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_MULTICASTTSTATE_ERR_FATAL_REPORT_EN_0_TAGPOOL_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_MULTICASTTSTATE_ERR_FATAL_REPORT_EN_0_TAGPOOL_ECC_DBE_ERR 3:3 /* RWEVF */
#define NV_MULTICASTTSTATE_ERR_FATAL_REPORT_EN_0_TAGPOOL_ECC_DBE_ERR__PROD 0x00000001 /* RW--V */
#define NV_MULTICASTTSTATE_ERR_FATAL_REPORT_EN_0_TAGPOOL_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_MULTICASTTSTATE_ERR_FATAL_REPORT_EN_0_TAGPOOL_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_MULTICASTTSTATE_ERR_FATAL_REPORT_EN_0_CRUMBSTORE_BUF_OVERWRITE_ERR 16:16 /* RWEVF */
#define NV_MULTICASTTSTATE_ERR_FATAL_REPORT_EN_0_CRUMBSTORE_BUF_OVERWRITE_ERR__PROD 0x00000001 /* RW--V */
#define NV_MULTICASTTSTATE_ERR_FATAL_REPORT_EN_0_CRUMBSTORE_BUF_OVERWRITE_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_MULTICASTTSTATE_ERR_FATAL_REPORT_EN_0_CRUMBSTORE_BUF_OVERWRITE_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_MULTICASTTSTATE_ERR_FATAL_REPORT_EN_0_CRUMBSTORE_ECC_LIMIT_ERR 18:18 /* RWEVF */
#define NV_MULTICASTTSTATE_ERR_FATAL_REPORT_EN_0_CRUMBSTORE_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_MULTICASTTSTATE_ERR_FATAL_REPORT_EN_0_CRUMBSTORE_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_MULTICASTTSTATE_ERR_FATAL_REPORT_EN_0_CRUMBSTORE_ECC_DBE_ERR 19:19 /* RWEVF */
#define NV_MULTICASTTSTATE_ERR_FATAL_REPORT_EN_0_CRUMBSTORE_ECC_DBE_ERR__PROD 0x00000001 /* RW--V */
#define NV_MULTICASTTSTATE_ERR_FATAL_REPORT_EN_0_CRUMBSTORE_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_MULTICASTTSTATE_ERR_FATAL_REPORT_EN_0_CRUMBSTORE_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_MULTICASTTSTATE_ERR_FATAL_REPORT_EN_0_CRUMBSTORE_MCTO_ERR 20:20 /* RWEVF */
#define NV_MULTICASTTSTATE_ERR_FATAL_REPORT_EN_0_CRUMBSTORE_MCTO_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_MULTICASTTSTATE_ERR_FATAL_REPORT_EN_0_CRUMBSTORE_MCTO_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_MULTICASTTSTATE_ERR_NON_FATAL_REPORT_EN_0 0x0000240c /* RW-4R */
#define NV_MULTICASTTSTATE_ERR_NON_FATAL_REPORT_EN_0_TAGPOOL_ECC_LIMIT_ERR 2:2 /* RWEVF */
#define NV_MULTICASTTSTATE_ERR_NON_FATAL_REPORT_EN_0_TAGPOOL_ECC_LIMIT_ERR__PROD 0x00000001 /* RW--V */
#define NV_MULTICASTTSTATE_ERR_NON_FATAL_REPORT_EN_0_TAGPOOL_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_MULTICASTTSTATE_ERR_NON_FATAL_REPORT_EN_0_TAGPOOL_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_MULTICASTTSTATE_ERR_NON_FATAL_REPORT_EN_0_TAGPOOL_ECC_DBE_ERR 3:3 /* RWEVF */
#define NV_MULTICASTTSTATE_ERR_NON_FATAL_REPORT_EN_0_TAGPOOL_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_MULTICASTTSTATE_ERR_NON_FATAL_REPORT_EN_0_TAGPOOL_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_MULTICASTTSTATE_ERR_NON_FATAL_REPORT_EN_0_CRUMBSTORE_BUF_OVERWRITE_ERR 16:16 /* RWEVF */
#define NV_MULTICASTTSTATE_ERR_NON_FATAL_REPORT_EN_0_CRUMBSTORE_BUF_OVERWRITE_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_MULTICASTTSTATE_ERR_NON_FATAL_REPORT_EN_0_CRUMBSTORE_BUF_OVERWRITE_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_MULTICASTTSTATE_ERR_NON_FATAL_REPORT_EN_0_CRUMBSTORE_ECC_LIMIT_ERR 18:18 /* RWEVF */
#define NV_MULTICASTTSTATE_ERR_NON_FATAL_REPORT_EN_0_CRUMBSTORE_ECC_LIMIT_ERR__PROD 0x00000001 /* RW--V */
#define NV_MULTICASTTSTATE_ERR_NON_FATAL_REPORT_EN_0_CRUMBSTORE_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_MULTICASTTSTATE_ERR_NON_FATAL_REPORT_EN_0_CRUMBSTORE_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_MULTICASTTSTATE_ERR_NON_FATAL_REPORT_EN_0_CRUMBSTORE_ECC_DBE_ERR 19:19 /* RWEVF */
#define NV_MULTICASTTSTATE_ERR_NON_FATAL_REPORT_EN_0_CRUMBSTORE_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_MULTICASTTSTATE_ERR_NON_FATAL_REPORT_EN_0_CRUMBSTORE_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_MULTICASTTSTATE_ERR_NON_FATAL_REPORT_EN_0_CRUMBSTORE_MCTO_ERR 20:20 /* RWEVF */
#define NV_MULTICASTTSTATE_ERR_NON_FATAL_REPORT_EN_0_CRUMBSTORE_MCTO_ERR__PROD 0x00000001 /* RW--V */
#define NV_MULTICASTTSTATE_ERR_NON_FATAL_REPORT_EN_0_CRUMBSTORE_MCTO_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_MULTICASTTSTATE_ERR_NON_FATAL_REPORT_EN_0_CRUMBSTORE_MCTO_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_MULTICASTTSTATE_ERR_CORRECTABLE_REPORT_EN_0 0x00002410 /* RW-4R */
#define NV_MULTICASTTSTATE_ERR_CONTAIN_EN_0 0x00002414 /* RW-4R */
#define NV_MULTICASTTSTATE_ERR_CONTAIN_EN_0_TAGPOOL_ECC_LIMIT_ERR 2:2 /* RWEVF */
#define NV_MULTICASTTSTATE_ERR_CONTAIN_EN_0_TAGPOOL_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_MULTICASTTSTATE_ERR_CONTAIN_EN_0_TAGPOOL_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_MULTICASTTSTATE_ERR_CONTAIN_EN_0_TAGPOOL_ECC_DBE_ERR 3:3 /* RWEVF */
#define NV_MULTICASTTSTATE_ERR_CONTAIN_EN_0_TAGPOOL_ECC_DBE_ERR__PROD 0x00000001 /* RW--V */
#define NV_MULTICASTTSTATE_ERR_CONTAIN_EN_0_TAGPOOL_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_MULTICASTTSTATE_ERR_CONTAIN_EN_0_TAGPOOL_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_MULTICASTTSTATE_ERR_CONTAIN_EN_0_CRUMBSTORE_BUF_OVERWRITE_ERR 16:16 /* RWEVF */
#define NV_MULTICASTTSTATE_ERR_CONTAIN_EN_0_CRUMBSTORE_BUF_OVERWRITE_ERR__PROD 0x00000001 /* RW--V */
#define NV_MULTICASTTSTATE_ERR_CONTAIN_EN_0_CRUMBSTORE_BUF_OVERWRITE_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_MULTICASTTSTATE_ERR_CONTAIN_EN_0_CRUMBSTORE_BUF_OVERWRITE_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_MULTICASTTSTATE_ERR_CONTAIN_EN_0_CRUMBSTORE_ECC_LIMIT_ERR 18:18 /* RWEVF */
#define NV_MULTICASTTSTATE_ERR_CONTAIN_EN_0_CRUMBSTORE_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_MULTICASTTSTATE_ERR_CONTAIN_EN_0_CRUMBSTORE_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_MULTICASTTSTATE_ERR_CONTAIN_EN_0_CRUMBSTORE_ECC_DBE_ERR 19:19 /* RWEVF */
#define NV_MULTICASTTSTATE_ERR_CONTAIN_EN_0_CRUMBSTORE_ECC_DBE_ERR__PROD 0x00000001 /* RW--V */
#define NV_MULTICASTTSTATE_ERR_CONTAIN_EN_0_CRUMBSTORE_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_MULTICASTTSTATE_ERR_CONTAIN_EN_0_CRUMBSTORE_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_MULTICASTTSTATE_ERR_CONTAIN_EN_0_CRUMBSTORE_MCTO_ERR 20:20 /* RWEVF */
#define NV_MULTICASTTSTATE_ERR_CONTAIN_EN_0_CRUMBSTORE_MCTO_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_MULTICASTTSTATE_ERR_CONTAIN_EN_0_CRUMBSTORE_MCTO_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_MULTICASTTSTATE_ERR_FIRST_0 0x0000241c /* RW-4R */
#define NV_MULTICASTTSTATE_ERR_FIRST_0_TAGPOOL_ECC_LIMIT_ERR 2:2 /* RWDVF */
#define NV_MULTICASTTSTATE_ERR_FIRST_0_TAGPOOL_ECC_LIMIT_ERR__ONWRITE "oneToClear" /* */
#define NV_MULTICASTTSTATE_ERR_FIRST_0_TAGPOOL_ECC_LIMIT_ERR_NONE 0x00000000 /* RWD-V */
#define NV_MULTICASTTSTATE_ERR_FIRST_0_TAGPOOL_ECC_LIMIT_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_MULTICASTTSTATE_ERR_FIRST_0_TAGPOOL_ECC_DBE_ERR 3:3 /* RWDVF */
#define NV_MULTICASTTSTATE_ERR_FIRST_0_TAGPOOL_ECC_DBE_ERR__ONWRITE "oneToClear" /* */
#define NV_MULTICASTTSTATE_ERR_FIRST_0_TAGPOOL_ECC_DBE_ERR_NONE 0x00000000 /* RWD-V */
#define NV_MULTICASTTSTATE_ERR_FIRST_0_TAGPOOL_ECC_DBE_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_MULTICASTTSTATE_ERR_FIRST_0_CRUMBSTORE_BUF_OVERWRITE_ERR 16:16 /* RWDVF */
#define NV_MULTICASTTSTATE_ERR_FIRST_0_CRUMBSTORE_BUF_OVERWRITE_ERR__ONWRITE "oneToClear" /* */
#define NV_MULTICASTTSTATE_ERR_FIRST_0_CRUMBSTORE_BUF_OVERWRITE_ERR_NONE 0x00000000 /* RWD-V */
#define NV_MULTICASTTSTATE_ERR_FIRST_0_CRUMBSTORE_BUF_OVERWRITE_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_MULTICASTTSTATE_ERR_FIRST_0_CRUMBSTORE_ECC_LIMIT_ERR 18:18 /* RWDVF */
#define NV_MULTICASTTSTATE_ERR_FIRST_0_CRUMBSTORE_ECC_LIMIT_ERR__ONWRITE "oneToClear" /* */
#define NV_MULTICASTTSTATE_ERR_FIRST_0_CRUMBSTORE_ECC_LIMIT_ERR_NONE 0x00000000 /* RWD-V */
#define NV_MULTICASTTSTATE_ERR_FIRST_0_CRUMBSTORE_ECC_LIMIT_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_MULTICASTTSTATE_ERR_FIRST_0_CRUMBSTORE_ECC_DBE_ERR 19:19 /* RWDVF */
#define NV_MULTICASTTSTATE_ERR_FIRST_0_CRUMBSTORE_ECC_DBE_ERR__ONWRITE "oneToClear" /* */
#define NV_MULTICASTTSTATE_ERR_FIRST_0_CRUMBSTORE_ECC_DBE_ERR_NONE 0x00000000 /* RWD-V */
#define NV_MULTICASTTSTATE_ERR_FIRST_0_CRUMBSTORE_ECC_DBE_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_MULTICASTTSTATE_ERR_FIRST_0_CRUMBSTORE_MCTO_ERR 20:20 /* RWDVF */
#define NV_MULTICASTTSTATE_ERR_FIRST_0_CRUMBSTORE_MCTO_ERR__ONWRITE "oneToClear" /* */
#define NV_MULTICASTTSTATE_ERR_FIRST_0_CRUMBSTORE_MCTO_ERR_NONE 0x00000000 /* RWD-V */
#define NV_MULTICASTTSTATE_ERR_FIRST_0_CRUMBSTORE_MCTO_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_MULTICASTTSTATE_ERR_TIMESTAMP_LOG 0x00002450 /* R--4R */
#define NV_MULTICASTTSTATE_ERR_TIMESTAMP_LOG_TIMESTAMP 23:0 /* R-DVF */
#define NV_MULTICASTTSTATE_ERR_TIMESTAMP_LOG_TIMESTAMP_INIT 0x00000000 /* R-D-V */
#define NV_MULTICASTTSTATE_ERR_ECC_CTRL 0x00002500 /* RW-4R */
#define NV_MULTICASTTSTATE_ERR_ECC_CTRL_TAGPOOL_ECC_ENABLE 0:0 /* RWEVF */
#define NV_MULTICASTTSTATE_ERR_ECC_CTRL_TAGPOOL_ECC_ENABLE_ENABLE 0x00000001 /* RW--V */
#define NV_MULTICASTTSTATE_ERR_ECC_CTRL_TAGPOOL_ECC_ENABLE_DISABLE 0x00000000 /* RWE-V */
#define NV_MULTICASTTSTATE_ERR_ECC_CTRL_TAGPOOL_ECC_ENABLE__PROD 0x00000001 /* RW--V */
#define NV_MULTICASTTSTATE_ERR_ECC_CTRL_CRUMBSTORE_ECC_ENABLE 1:1 /* RWEVF */
#define NV_MULTICASTTSTATE_ERR_ECC_CTRL_CRUMBSTORE_ECC_ENABLE_ENABLE 0x00000001 /* RW--V */
#define NV_MULTICASTTSTATE_ERR_ECC_CTRL_CRUMBSTORE_ECC_ENABLE_DISABLE 0x00000000 /* RWE-V */
#define NV_MULTICASTTSTATE_ERR_ECC_CTRL_CRUMBSTORE_ECC_ENABLE__PROD 0x00000001 /* RW--V */
#define NV_MULTICASTTSTATE_ERR_TAGPOOL_ECC_ERROR_COUNTER 0x00002520 /* RW-4R */
#define NV_MULTICASTTSTATE_ERR_TAGPOOL_ECC_ERROR_COUNTER_ERROR_COUNT 23:0 /* RWDVF */
#define NV_MULTICASTTSTATE_ERR_TAGPOOL_ECC_ERROR_COUNTER_ERROR_COUNT_INIT 0x00000000 /* RWD-V */
#define NV_MULTICASTTSTATE_ERR_TAGPOOL_ECC_ERROR_COUNTER_LIMIT 0x00002540 /* RW-4R */
#define NV_MULTICASTTSTATE_ERR_TAGPOOL_ECC_ERROR_COUNTER_LIMIT_ERROR_LIMIT 23:0 /* RWDVF */
#define NV_MULTICASTTSTATE_ERR_TAGPOOL_ECC_ERROR_COUNTER_LIMIT_ERROR_LIMIT_INIT 0x00ffffff /* RWD-V */
#define NV_MULTICASTTSTATE_ERR_TAGPOOL_ECC_ERROR_ADDRESS 0x00002560 /* R--4R */
#define NV_MULTICASTTSTATE_ERR_TAGPOOL_ECC_ERROR_ADDRESS_ERROR_ADDRESS 7:0 /* R-DVF */
#define NV_MULTICASTTSTATE_ERR_TAGPOOL_ECC_ERROR_ADDRESS_ERROR_ADDRESS_INIT 0x00000000 /* R-D-V */
#define NV_MULTICASTTSTATE_ERR_TAGPOOL_ECC_ERROR_ADDRESS_VALID 0x00002580 /* R--4R */
#define NV_MULTICASTTSTATE_ERR_TAGPOOL_ECC_ERROR_ADDRESS_VALID_VALID 0:0 /* R-DVF */
#define NV_MULTICASTTSTATE_ERR_TAGPOOL_ECC_ERROR_ADDRESS_VALID_VALID_INVALID 0x00000000 /* R-D-V */
#define NV_MULTICASTTSTATE_ERR_TAGPOOL_ECC_ERROR_ADDRESS_VALID_VALID_VALID 0x00000001 /* R---V */
#define NV_MULTICASTTSTATE_ERR_CRUMBSTORE_ECC_ERROR_COUNTER 0x00002600 /* RW-4R */
#define NV_MULTICASTTSTATE_ERR_CRUMBSTORE_ECC_ERROR_COUNTER_ERROR_COUNT 23:0 /* RWDVF */
#define NV_MULTICASTTSTATE_ERR_CRUMBSTORE_ECC_ERROR_COUNTER_ERROR_COUNT_INIT 0x00000000 /* RWD-V */
#define NV_MULTICASTTSTATE_ERR_CRUMBSTORE_ECC_ERROR_COUNTER_LIMIT 0x00002620 /* RW-4R */
#define NV_MULTICASTTSTATE_ERR_CRUMBSTORE_ECC_ERROR_COUNTER_LIMIT_ERROR_LIMIT 23:0 /* RWDVF */
#define NV_MULTICASTTSTATE_ERR_CRUMBSTORE_ECC_ERROR_COUNTER_LIMIT_ERROR_LIMIT_INIT 0x00ffffff /* RWD-V */
#define NV_MULTICASTTSTATE_ERR_CRUMBSTORE_ECC_ERROR_ADDRESS 0x00002640 /* R--4R */
#define NV_MULTICASTTSTATE_ERR_CRUMBSTORE_ECC_ERROR_ADDRESS_ERROR_ADDRESS 7:0 /* R-DVF */
#define NV_MULTICASTTSTATE_ERR_CRUMBSTORE_ECC_ERROR_ADDRESS_ERROR_ADDRESS_INIT 0x00000000 /* R-D-V */
#define NV_MULTICASTTSTATE_ERR_CRUMBSTORE_ECC_ERROR_ADDRESS_VALID 0x00002660 /* R--4R */
#define NV_MULTICASTTSTATE_ERR_CRUMBSTORE_ECC_ERROR_ADDRESS_VALID_VALID 0:0 /* R-DVF */
#define NV_MULTICASTTSTATE_ERR_CRUMBSTORE_ECC_ERROR_ADDRESS_VALID_VALID_INVALID 0x00000000 /* R-D-V */
#define NV_MULTICASTTSTATE_ERR_CRUMBSTORE_ECC_ERROR_ADDRESS_VALID_VALID_VALID 0x00000001 /* R---V */
#define NV_MULTICASTTSTATE_STAT_STALL_BUSY_CONTROL 0x00002700 /* RW-4R */
#define NV_MULTICASTTSTATE_STAT_STALL_BUSY_CONTROL_ENABLE_TIMER 0:0 /* RWEVF */
#define NV_MULTICASTTSTATE_STAT_STALL_BUSY_CONTROL_ENABLE_TIMER_DISABLE 0x00000000 /* RWE-V */
#define NV_MULTICASTTSTATE_STAT_STALL_BUSY_CONTROL_ENABLE_TIMER_ENABLE 0x00000001 /* RW--V */
#define NV_MULTICASTTSTATE_STAT_STALL_BUSY_CONTROL_SNAP_ON_DEMAND 1:1 /* RWEVF */
#define NV_MULTICASTTSTATE_STAT_STALL_BUSY_CONTROL_SNAP_ON_DEMAND__ONWRITE "oneToSet" /* */
#define NV_MULTICASTTSTATE_STAT_STALL_BUSY_CONTROL_SNAP_ON_DEMAND_DISABLE 0x00000000 /* RWE-V */
#define NV_MULTICASTTSTATE_STAT_STALL_BUSY_CONTROL_SNAP_ON_DEMAND_ENABLE 0x00000001 /* RW--V */
#define NV_MULTICASTTSTATE_STAT_WINDOW_0_HIGH 0x00002704 /* RW-4R */
#define NV_MULTICASTTSTATE_STAT_WINDOW_0_HIGH_VALUE 15:0 /* RWEVF */
#define NV_MULTICASTTSTATE_STAT_WINDOW_0_HIGH_VALUE_INIT 0x00000000 /* RWE-V */
#define NV_MULTICASTTSTATE_STAT_WINDOW_0_LOW 0x00002708 /* RW-4R */
#define NV_MULTICASTTSTATE_STAT_WINDOW_0_LOW_VALUE 31:0 /* RWEVF */
#define NV_MULTICASTTSTATE_STAT_WINDOW_0_LOW_VALUE_INIT 0x00000000 /* RWE-V */
#define NV_MULTICASTTSTATE_STAT_BUSY_TIMER_0_HIGH 0x0000270c /* RW-4R */
#define NV_MULTICASTTSTATE_STAT_BUSY_TIMER_0_HIGH_VALUE 15:0 /* RWEVF */
#define NV_MULTICASTTSTATE_STAT_BUSY_TIMER_0_HIGH_VALUE_INIT 0x00000000 /* RWE-V */
#define NV_MULTICASTTSTATE_STAT_BUSY_TIMER_0_LOW 0x00002710 /* RW-4R */
#define NV_MULTICASTTSTATE_STAT_BUSY_TIMER_0_LOW_VALUE 31:0 /* RWEVF */
#define NV_MULTICASTTSTATE_STAT_BUSY_TIMER_0_LOW_VALUE_INIT 0x00000000 /* RWE-V */
#define NV_MULTICASTTSTATE_STAT_STALL_TIMER_0_HIGH 0x00002714 /* RW-4R */
#define NV_MULTICASTTSTATE_STAT_STALL_TIMER_0_HIGH_VALUE 15:0 /* RWEVF */
#define NV_MULTICASTTSTATE_STAT_STALL_TIMER_0_HIGH_VALUE_INIT 0x00000000 /* RWE-V */
#define NV_MULTICASTTSTATE_STAT_STALL_TIMER_0_LOW 0x00002718 /* RW-4R */
#define NV_MULTICASTTSTATE_STAT_STALL_TIMER_0_LOW_VALUE 31:0 /* RWEVF */
#define NV_MULTICASTTSTATE_STAT_STALL_TIMER_0_LOW_VALUE_INIT 0x00000000 /* RWE-V */
#define NV_MULTICASTTSTATE_STAT_WINDOW_1_HIGH 0x0000271c /* RW-4R */
#define NV_MULTICASTTSTATE_STAT_WINDOW_1_HIGH_VALUE 15:0 /* RWEVF */
#define NV_MULTICASTTSTATE_STAT_WINDOW_1_HIGH_VALUE_INIT 0x00000000 /* RWE-V */
#define NV_MULTICASTTSTATE_STAT_WINDOW_1_LOW 0x00002720 /* RW-4R */
#define NV_MULTICASTTSTATE_STAT_WINDOW_1_LOW_VALUE 31:0 /* RWEVF */
#define NV_MULTICASTTSTATE_STAT_WINDOW_1_LOW_VALUE_INIT 0x00000000 /* RWE-V */
#define NV_MULTICASTTSTATE_STAT_BUSY_TIMER_1_HIGH 0x00002724 /* RW-4R */
#define NV_MULTICASTTSTATE_STAT_BUSY_TIMER_1_HIGH_VALUE 15:0 /* RWEVF */
#define NV_MULTICASTTSTATE_STAT_BUSY_TIMER_1_HIGH_VALUE_INIT 0x00000000 /* RWE-V */
#define NV_MULTICASTTSTATE_STAT_BUSY_TIMER_1_LOW 0x00002728 /* RW-4R */
#define NV_MULTICASTTSTATE_STAT_BUSY_TIMER_1_LOW_VALUE 31:0 /* RWEVF */
#define NV_MULTICASTTSTATE_STAT_BUSY_TIMER_1_LOW_VALUE_INIT 0x00000000 /* RWE-V */
#define NV_MULTICASTTSTATE_STAT_STALL_TIMER_1_HIGH 0x0000272c /* RW-4R */
#define NV_MULTICASTTSTATE_STAT_STALL_TIMER_1_HIGH_VALUE 15:0 /* RWEVF */
#define NV_MULTICASTTSTATE_STAT_STALL_TIMER_1_HIGH_VALUE_INIT 0x00000000 /* RWE-V */
#define NV_MULTICASTTSTATE_STAT_STALL_TIMER_1_LOW 0x00002730 /* RW-4R */
#define NV_MULTICASTTSTATE_STAT_STALL_TIMER_1_LOW_VALUE 31:0 /* RWEVF */
#define NV_MULTICASTTSTATE_STAT_STALL_TIMER_1_LOW_VALUE_INIT 0x00000000 /* RWE-V */
#define NV_MULTICASTTSTATE_STAT_RESIDENCY_CONTROL 0x00002734 /* RW-4R */
#define NV_MULTICASTTSTATE_STAT_RESIDENCY_CONTROL_ENABLE_TIMER 0:0 /* RWEVF */
#define NV_MULTICASTTSTATE_STAT_RESIDENCY_CONTROL_ENABLE_TIMER_DISABLE 0x00000000 /* RWE-V */
#define NV_MULTICASTTSTATE_STAT_RESIDENCY_CONTROL_ENABLE_TIMER_ENABLE 0x00000001 /* RW--V */
#define NV_MULTICASTTSTATE_STAT_RESIDENCY_CONTROL_SNAP_ON_DEMAND 1:1 /* RWEVF */
#define NV_MULTICASTTSTATE_STAT_RESIDENCY_CONTROL_SNAP_ON_DEMAND__ONWRITE "oneToSet" /* */
#define NV_MULTICASTTSTATE_STAT_RESIDENCY_CONTROL_SNAP_ON_DEMAND_DISABLE 0x00000000 /* RWE-V */
#define NV_MULTICASTTSTATE_STAT_RESIDENCY_CONTROL_SNAP_ON_DEMAND_ENABLE 0x00000001 /* RW--V */
#define NV_MULTICASTTSTATE_STAT_RESIDENCY_BIN_CTRL_LOW 0x00002738 /* RW-4R */
#define NV_MULTICASTTSTATE_STAT_RESIDENCY_BIN_CTRL_LOW_LIMIT 23:0 /* RWEVF */
#define NV_MULTICASTTSTATE_STAT_RESIDENCY_BIN_CTRL_LOW_LIMIT_INIT 0x0028b0ab /* RWE-V */
#define NV_MULTICASTTSTATE_STAT_RESIDENCY_BIN_CTRL_HIGH 0x0000273c /* RW-4R */
#define NV_MULTICASTTSTATE_STAT_RESIDENCY_BIN_CTRL_HIGH_LIMIT 23:0 /* RWEVF */
#define NV_MULTICASTTSTATE_STAT_RESIDENCY_BIN_CTRL_HIGH_LIMIT_INIT 0x00cb7355 /* RWE-V */
#define NV_MULTICASTTSTATE_STAT_RESIDENCY_COUNT_CTRL 0x00002740 /* RW-4R */
#define NV_MULTICASTTSTATE_STAT_RESIDENCY_COUNT_CTRL_INDEX 9:0 /* RWEVF */
#define NV_MULTICASTTSTATE_STAT_RESIDENCY_COUNT_CTRL_INDEX_MIN 0x00000000 /* RWE-V */
#define NV_MULTICASTTSTATE_STAT_RESIDENCY_COUNT_CTRL_INDEX_MAX 0x000002ff /* RW--V */
#define NV_MULTICASTTSTATE_STAT_RESIDENCY_COUNT_CTRL_INDEX_MCID_STRIDE 0x00000006 /* */
#define NV_MULTICASTTSTATE_STAT_RESIDENCY_COUNT_CTRL_INDEX_BIN_LOW_31_0 0x00000000 /* */
#define NV_MULTICASTTSTATE_STAT_RESIDENCY_COUNT_CTRL_INDEX_BIN_LOW_47_31 0x00000001 /* */
#define NV_MULTICASTTSTATE_STAT_RESIDENCY_COUNT_CTRL_INDEX_BIN_MED_31_0 0x00000002 /* */
#define NV_MULTICASTTSTATE_STAT_RESIDENCY_COUNT_CTRL_INDEX_BIN_MED_47_31 0x00000003 /* */
#define NV_MULTICASTTSTATE_STAT_RESIDENCY_COUNT_CTRL_INDEX_BIN_HIGH_31_0 0x00000004 /* */
#define NV_MULTICASTTSTATE_STAT_RESIDENCY_COUNT_CTRL_INDEX_BIN_HIGH_47_31 0x00000005 /* */
#define NV_MULTICASTTSTATE_STAT_RESIDENCY_COUNT_CTRL_AUTOINCR 31:31 /* RWEVF */
#define NV_MULTICASTTSTATE_STAT_RESIDENCY_COUNT_CTRL_AUTOINCR_OFF 0x00000000 /* RW--V */
#define NV_MULTICASTTSTATE_STAT_RESIDENCY_COUNT_CTRL_AUTOINCR_ON 0x00000001 /* RWE-V */
#define NV_MULTICASTTSTATE_STAT_RESIDENCY_COUNT_DATA 0x00002744 /* R--4R */
#define NV_MULTICASTTSTATE_STAT_RESIDENCY_COUNT_DATA_COUNT 31:0 /* R-XVF */
#define NV_MULTICASTTSTATE_STAT_RESIDENCY_COUNT_DATA__APERTURE_INDEX_OFFSET -0x00000004 /* */
#endif // __ls10_dev_multicasttstate_ip_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the Software),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __ls10_dev_npg_ip_h__
#define __ls10_dev_npg_ip_h__
/* This file is autogenerated. Do not edit */
#define NV_NPG 0x000007FFFF:0x00000000 /* RW--D */
#define NV_NPG_CTRL_CLOCK_GATING 0x000000c8 /* RW-4R */
#define NV_NPG_CTRL_CLOCK_GATING_CG1_SLCG 3:0 /* RWEVF */
#define NV_NPG_CTRL_CLOCK_GATING_CG1_SLCG_INIT 0x0000000f /* RWE-V */
#define NV_NPG_CTRL_CLOCK_GATING_CG1_SLCG__PROD 0x00000000 /* RW--V */
#define NV_NPG_CTRL_CLOCK_GATING_CG1_BLCG 8:4 /* RWEVF */
#define NV_NPG_CTRL_CLOCK_GATING_CG1_BLCG_INIT 0x0000001f /* RWE-V */
#define NV_NPG_CTRL_CLOCK_GATING_CG1_BLCG__PROD 0x00000000 /* RW--V */
#define NV_NPG_CONFIG_CLOCK_GATING 0x000000cc /* RW-4R */
#define NV_NPG_CONFIG_CLOCK_GATING_CG1_BLCG_IDLE_DLY_CNT 5:0 /* RWEVF */
#define NV_NPG_CONFIG_CLOCK_GATING_CG1_BLCG_IDLE_DLY_CNT_INIT 0x00000000 /* RWE-V */
#define NV_NPG_CONFIG_CLOCK_GATING_CG1_BLCG_IDLE_CG_EN 6:6 /* RWEVF */
#define NV_NPG_CONFIG_CLOCK_GATING_CG1_BLCG_IDLE_CG_EN_INIT 0x00000001 /* RWE-V */
#define NV_NPG_CONFIG_CLOCK_GATING_CG1_BLCG_STALL_CG_EN 7:7 /* RWEVF */
#define NV_NPG_CONFIG_CLOCK_GATING_CG1_BLCG_STALL_CG_EN_INIT 0x00000000 /* RWE-V */
#define NV_NPG_CONFIG_CLOCK_GATING_CG1_BLCG_MONITOR_CG_EN 8:8 /* RWEVF */
#define NV_NPG_CONFIG_CLOCK_GATING_CG1_BLCG_MONITOR_CG_EN_INIT 0x00000000 /* RWE-V */
#define NV_NPG_CONFIG_CLOCK_GATING_CG1_BLCG_WAKEUP_DLY_CNT 12:9 /* RWEVF */
#define NV_NPG_CONFIG_CLOCK_GATING_CG1_BLCG_WAKEUP_DLY_CNT_INIT 0x00000000 /* RWE-V */
#define NV_NPG_NPG_INTERRUPT_STATUS 0x00000400 /* R--4R */
#define NV_NPG_NPG_INTERRUPT_STATUS_DEV0_FNC_OR 0:0 /* R-EVF */
#define NV_NPG_NPG_INTERRUPT_STATUS_DEV0_FNC_OR_INIT 0x00000000 /* R-E-V */
#define NV_NPG_NPG_INTERRUPT_STATUS_DEV0_INT_STATUS 3:1 /* R-EVF */
#define NV_NPG_NPG_INTERRUPT_STATUS_DEV0_INT_STATUS_INIT 0x00000000 /* R-E-V */
#define NV_NPG_NPG_INTERRUPT_STATUS_DEV0_INT_STATUS_FATAL 0x00000001 /* R---V */
#define NV_NPG_NPG_INTERRUPT_STATUS_DEV0_INT_STATUS_NONFATAL 0x00000002 /* R---V */
#define NV_NPG_NPG_INTERRUPT_STATUS_DEV0_INT_STATUS_CORRECTABLE 0x00000004 /* R---V */
#define NV_NPG_NPG_INTERRUPT_STATUS_DEV1_FNC_OR 4:4 /* R-EVF */
#define NV_NPG_NPG_INTERRUPT_STATUS_DEV1_FNC_OR_INIT 0x00000000 /* R-E-V */
#define NV_NPG_NPG_INTERRUPT_STATUS_DEV1_INT_STATUS 7:5 /* R-EVF */
#define NV_NPG_NPG_INTERRUPT_STATUS_DEV1_INT_STATUS_INIT 0x00000000 /* R-E-V */
#define NV_NPG_NPG_INTERRUPT_STATUS_DEV1_INT_STATUS_FATAL 0x00000001 /* R---V */
#define NV_NPG_NPG_INTERRUPT_STATUS_DEV1_INT_STATUS_NONFATAL 0x00000002 /* R---V */
#define NV_NPG_NPG_INTERRUPT_STATUS_DEV1_INT_STATUS_CORRECTABLE 0x00000004 /* R---V */
#define NV_NPG_NPG_INTERRUPT_STATUS_DEV2_FNC_OR 8:8 /* R-EVF */
#define NV_NPG_NPG_INTERRUPT_STATUS_DEV2_FNC_OR_INIT 0x00000000 /* R-E-V */
#define NV_NPG_NPG_INTERRUPT_STATUS_DEV2_INT_STATUS 11:9 /* R-EVF */
#define NV_NPG_NPG_INTERRUPT_STATUS_DEV2_INT_STATUS_INIT 0x00000000 /* R-E-V */
#define NV_NPG_NPG_INTERRUPT_STATUS_DEV2_INT_STATUS_FATAL 0x00000001 /* R---V */
#define NV_NPG_NPG_INTERRUPT_STATUS_DEV2_INT_STATUS_NONFATAL 0x00000002 /* R---V */
#define NV_NPG_NPG_INTERRUPT_STATUS_DEV2_INT_STATUS_CORRECTABLE 0x00000004 /* R---V */
#define NV_NPG_NPG_INTERRUPT_STATUS_DEV3_FNC_OR 12:12 /* R-EVF */
#define NV_NPG_NPG_INTERRUPT_STATUS_DEV3_FNC_OR_INIT 0x00000000 /* R-E-V */
#define NV_NPG_NPG_INTERRUPT_STATUS_DEV3_INT_STATUS 15:13 /* R-EVF */
#define NV_NPG_NPG_INTERRUPT_STATUS_DEV3_INT_STATUS_INIT 0x00000000 /* R-E-V */
#define NV_NPG_NPG_INTERRUPT_STATUS_DEV3_INT_STATUS_FATAL 0x00000001 /* R---V */
#define NV_NPG_NPG_INTERRUPT_STATUS_DEV3_INT_STATUS_NONFATAL 0x00000002 /* R---V */
#define NV_NPG_NPG_INTERRUPT_STATUS_DEV3_INT_STATUS_CORRECTABLE 0x00000004 /* R---V */
#define NV_NPG_INTR_RETRIGGER(i) (0x00000580+(i)*0x4) /* RW-4A */
#define NV_NPG_INTR_RETRIGGER__SIZE_1 3 /* */
#define NV_NPG_INTR_RETRIGGER_TRIGGER 0:0 /* RWEVF */
#define NV_NPG_INTR_RETRIGGER_TRIGGER__ONWRITE "oneToSet" /* */
#define NV_NPG_INTR_RETRIGGER_TRIGGER_INIT 0x00000000 /* RWE-V */
#endif // __ls10_dev_npg_ip_h__

40
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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the Software),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __ls10_dev_npgperf_ip_h__
#define __ls10_dev_npgperf_ip_h__
/* This file is autogenerated. Do not edit */
#define NV_NPGPERF 0x000003FF:0x00000000 /* RW--D */
#define NV_NPGPERF_CTRL_CLOCK_GATING 0x000000c8 /* RW-4R */
#define NV_NPGPERF_CTRL_CLOCK_GATING_CG1_SLCG 3:0 /* RWEVF */
#define NV_NPGPERF_CTRL_CLOCK_GATING_CG1_SLCG_INIT 0x0000000f /* RWE-V */
#define NV_NPGPERF_CTRL_CLOCK_GATING_CG1_SLCG__PROD 0x00000000 /* RW--V */
#define NV_NPGPERF_PERF_CTRL_CLOCK_GATING 0x000000cc /* RW-4R */
#define NV_NPGPERF_PERF_CTRL_CLOCK_GATING_CG1_SLCG 3:0 /* RWEVF */
#define NV_NPGPERF_PERF_CTRL_CLOCK_GATING_CG1_SLCG_INIT 0x0000000f /* RWE-V */
#define NV_NPGPERF_PERF_CTRL_CLOCK_GATING_CG1_SLCG__PROD 0x00000000 /* RW--V */
#define NV_NPGPERF_PERF_CTRL_CLOCK_GATING_CONTEXT_FREEZE 7:4 /* RWEVF */
#define NV_NPGPERF_PERF_CTRL_CLOCK_GATING_CONTEXT_FREEZE_DISABLED 0x00000000 /* RWE-V */
#define NV_NPGPERF_PERF_CTRL_CLOCK_GATING_CONTEXT_FREEZE_ENABLED 0x00000001 /* RW--V */
#define NV_NPGPERF_PERF_CTRL_CLOCK_GATING_CONTEXT_FREEZE__PROD 0x00000000 /* RW--V */
#endif // __ls10_dev_npgperf_ip_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the Software),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __ls10_dev_nport_ip_h__
#define __ls10_dev_nport_ip_h__
/* This file is autogenerated. Do not edit */
#define NV_NPORT 0x00007fff:0x00000000 /* RW--D */
#define NV_NPORT_CTRL 0x00000040 /* RW-4R */
#define NV_NPORT_CTRL_TRUNKLINKENB 0:0 /* RWEVF */
#define NV_NPORT_CTRL_TRUNKLINKENB_TRUNKLINK 0x00000001 /* RW--V */
#define NV_NPORT_CTRL_TRUNKLINKENB_ACCESSLINK 0x00000000 /* RWE-V */
#define NV_NPORT_CTRL_TRUNKLINKENB__TPROD 0x00000001 /* RW--V */
#define NV_NPORT_CTRL_EGDRAINENB 1:1 /* RWEVF */
#define NV_NPORT_CTRL_EGDRAINENB_ENABLE 0x00000001 /* RW--V */
#define NV_NPORT_CTRL_EGDRAINENB_DISABLE 0x00000000 /* RWE-V */
#define NV_NPORT_CTRL_RTDRAINENB 2:2 /* RWEVF */
#define NV_NPORT_CTRL_RTDRAINENB_ENABLE 0x00000001 /* RW--V */
#define NV_NPORT_CTRL_RTDRAINENB_DISABLE 0x00000000 /* RWE-V */
#define NV_NPORT_CTRL_SPARE 13:9 /* RWEVF */
#define NV_NPORT_CTRL_SPARE_INIT 0x00000000 /* RWE-V */
#define NV_NPORT_CTRL_ENROUTEDBI 16:16 /* RWEVF */
#define NV_NPORT_CTRL_ENROUTEDBI_ENABLE 0x00000001 /* RWE-V */
#define NV_NPORT_CTRL_ENROUTEDBI_DISABLE 0x00000000 /* RW--V */
#define NV_NPORT_CTRL_ENEGRESSDBI 17:17 /* RWEVF */
#define NV_NPORT_CTRL_ENEGRESSDBI_ENABLE 0x00000001 /* RWE-V */
#define NV_NPORT_CTRL_ENEGRESSDBI_DISABLE 0x00000000 /* RW--V */
#define NV_NPORT_CTRL_BUFFER_READY 0x00000044 /* RW-4R */
#define NV_NPORT_CTRL_BUFFER_READY_BUFFERRDY 0:0 /* RWEVF */
#define NV_NPORT_CTRL_BUFFER_READY_BUFFERRDY_ENABLE 0x00000001 /* RW--V */
#define NV_NPORT_CTRL_BUFFER_READY_BUFFERRDY_DISABLE 0x00000000 /* RWE-V */
#define NV_NPORT_CTRL_STOP 0x00000048 /* RW-4R */
#define NV_NPORT_CTRL_STOP_INGRESS_STOP 0:0 /* RWEVF */
#define NV_NPORT_CTRL_STOP_INGRESS_STOP_STOP 0x00000001 /* RW--V */
#define NV_NPORT_CTRL_STOP_INGRESS_STOP_ALLOWTRAFFIC 0x00000000 /* RWE-V */
#define NV_NPORT_CTRL_STOP_EGRESS_STOP 8:8 /* RWEVF */
#define NV_NPORT_CTRL_STOP_EGRESS_STOP_STOP 0x00000001 /* RW--V */
#define NV_NPORT_CTRL_STOP_EGRESS_STOP_ALLOWTRAFFIC 0x00000000 /* RWE-V */
#define NV_NPORT_CTRL_STOP_ROUTE_STOP_VC 23:16 /* RWEVF */
#define NV_NPORT_CTRL_STOP_ROUTE_STOP_VC_ALLOWTRAFFIC 0x00000000 /* RWE-V */
#define NV_NPORT_CTRL_STOP_ROUTE_STOP_VC_STOPVC0 0x00000001 /* RW--V */
#define NV_NPORT_CTRL_STOP_ROUTE_STOP_VC_STOPVC1 0x00000002 /* RW--V */
#define NV_NPORT_CTRL_STOP_ROUTE_STOP_VC_STOPVC2 0x00000004 /* RW--V */
#define NV_NPORT_CTRL_STOP_ROUTE_STOP_VC_STOPVC3 0x00000008 /* RW--V */
#define NV_NPORT_CTRL_STOP_ROUTE_STOP_VC_STOPVC4 0x00000010 /* RW--V */
#define NV_NPORT_CTRL_STOP_ROUTE_STOP_VC_STOPVC5 0x00000020 /* RW--V */
#define NV_NPORT_CTRL_STOP_ROUTE_STOP_VC_STOPVC6 0x00000040 /* RW--V */
#define NV_NPORT_CTRL_STOP_ROUTE_STOP_VC_STOPVC7 0x00000080 /* RW--V */
#define NV_NPORT_INITIALIZATION 0x0000004c /* RW-4R */
#define NV_NPORT_INITIALIZATION_TAGPOOLINIT_0 0:0 /* RWEVF */
#define NV_NPORT_INITIALIZATION_TAGPOOLINIT_0__ONWRITE "oneToClear" /* */
#define NV_NPORT_INITIALIZATION_TAGPOOLINIT_0_INIT 0x00000000 /* RWE-V */
#define NV_NPORT_INITIALIZATION_TAGPOOLINIT_0_HWINIT 0x00000001 /* RW--V */
#define NV_NPORT_INITIALIZATION_TAGPOOLINIT_1 1:1 /* RWEVF */
#define NV_NPORT_INITIALIZATION_TAGPOOLINIT_1__ONWRITE "oneToClear" /* */
#define NV_NPORT_INITIALIZATION_TAGPOOLINIT_1_INIT 0x00000000 /* RWE-V */
#define NV_NPORT_INITIALIZATION_TAGPOOLINIT_1_HWINIT 0x00000001 /* RW--V */
#define NV_NPORT_INITIALIZATION_TAGPOOLINIT_2 2:2 /* RWEVF */
#define NV_NPORT_INITIALIZATION_TAGPOOLINIT_2__ONWRITE "oneToClear" /* */
#define NV_NPORT_INITIALIZATION_TAGPOOLINIT_2_INIT 0x00000000 /* RWE-V */
#define NV_NPORT_INITIALIZATION_TAGPOOLINIT_2_HWINIT 0x00000001 /* RW--V */
#define NV_NPORT_INITIALIZATION_TAGPOOLINIT_3 3:3 /* RWEVF */
#define NV_NPORT_INITIALIZATION_TAGPOOLINIT_3__ONWRITE "oneToClear" /* */
#define NV_NPORT_INITIALIZATION_TAGPOOLINIT_3_INIT 0x00000000 /* RWE-V */
#define NV_NPORT_INITIALIZATION_TAGPOOLINIT_3_HWINIT 0x00000001 /* RW--V */
#define NV_NPORT_INITIALIZATION_TAGPOOLINIT_4 4:4 /* RWEVF */
#define NV_NPORT_INITIALIZATION_TAGPOOLINIT_4__ONWRITE "oneToClear" /* */
#define NV_NPORT_INITIALIZATION_TAGPOOLINIT_4_INIT 0x00000000 /* RWE-V */
#define NV_NPORT_INITIALIZATION_TAGPOOLINIT_4_HWINIT 0x00000001 /* RW--V */
#define NV_NPORT_INITIALIZATION_TAGPOOLINIT_5 5:5 /* RWEVF */
#define NV_NPORT_INITIALIZATION_TAGPOOLINIT_5__ONWRITE "oneToClear" /* */
#define NV_NPORT_INITIALIZATION_TAGPOOLINIT_5_INIT 0x00000000 /* RWE-V */
#define NV_NPORT_INITIALIZATION_TAGPOOLINIT_5_HWINIT 0x00000001 /* RW--V */
#define NV_NPORT_INITIALIZATION_TAGPOOLINIT_6 6:6 /* RWEVF */
#define NV_NPORT_INITIALIZATION_TAGPOOLINIT_6__ONWRITE "oneToClear" /* */
#define NV_NPORT_INITIALIZATION_TAGPOOLINIT_6_INIT 0x00000000 /* RWE-V */
#define NV_NPORT_INITIALIZATION_TAGPOOLINIT_6_HWINIT 0x00000001 /* RW--V */
#define NV_NPORT_INITIALIZATION_LINKTABLEINIT 8:8 /* RWEVF */
#define NV_NPORT_INITIALIZATION_LINKTABLEINIT__ONWRITE "oneToClear" /* */
#define NV_NPORT_INITIALIZATION_LINKTABLEINIT_INIT 0x00000000 /* RWE-V */
#define NV_NPORT_INITIALIZATION_LINKTABLEINIT_HWINIT 0x00000001 /* RW--V */
#define NV_NPORT_INITIALIZATION_REMAPTABINIT 9:9 /* RWEVF */
#define NV_NPORT_INITIALIZATION_REMAPTABINIT__ONWRITE "oneToClear" /* */
#define NV_NPORT_INITIALIZATION_REMAPTABINIT_INIT 0x00000000 /* RWE-V */
#define NV_NPORT_INITIALIZATION_REMAPTABINIT_HWINIT 0x00000001 /* RW--V */
#define NV_NPORT_INITIALIZATION_RIDTABINIT 10:10 /* RWEVF */
#define NV_NPORT_INITIALIZATION_RIDTABINIT__ONWRITE "oneToClear" /* */
#define NV_NPORT_INITIALIZATION_RIDTABINIT_INIT 0x00000000 /* RWE-V */
#define NV_NPORT_INITIALIZATION_RIDTABINIT_HWINIT 0x00000001 /* RW--V */
#define NV_NPORT_INITIALIZATION_RLANTABINIT 11:11 /* RWEVF */
#define NV_NPORT_INITIALIZATION_RLANTABINIT__ONWRITE "oneToClear" /* */
#define NV_NPORT_INITIALIZATION_RLANTABINIT_INIT 0x00000000 /* RWE-V */
#define NV_NPORT_INITIALIZATION_RLANTABINIT_HWINIT 0x00000001 /* RW--V */
#define NV_NPORT_INITIALIZATION_MCREMAPTABINIT 12:12 /* RWEVF */
#define NV_NPORT_INITIALIZATION_MCREMAPTABINIT__ONWRITE "oneToClear" /* */
#define NV_NPORT_INITIALIZATION_MCREMAPTABINIT_INIT 0x00000000 /* RWE-V */
#define NV_NPORT_INITIALIZATION_MCREMAPTABINIT_HWINIT 0x00000001 /* RW--V */
#define NV_NPORT_INITIALIZATION_MCTAGSTATEINIT 13:13 /* RWEVF */
#define NV_NPORT_INITIALIZATION_MCTAGSTATEINIT__ONWRITE "oneToClear" /* */
#define NV_NPORT_INITIALIZATION_MCTAGSTATEINIT_INIT 0x00000000 /* RWE-V */
#define NV_NPORT_INITIALIZATION_MCTAGSTATEINIT_HWINIT 0x00000001 /* RW--V */
#define NV_NPORT_INITIALIZATION_RDTAGSTATEINIT 14:14 /* RWEVF */
#define NV_NPORT_INITIALIZATION_RDTAGSTATEINIT__ONWRITE "oneToClear" /* */
#define NV_NPORT_INITIALIZATION_RDTAGSTATEINIT_INIT 0x00000000 /* RWE-V */
#define NV_NPORT_INITIALIZATION_RDTAGSTATEINIT_HWINIT 0x00000001 /* RW--V */
#define NV_NPORT_INITIALIZATION_MCREDSGTINIT 15:15 /* RWEVF */
#define NV_NPORT_INITIALIZATION_MCREDSGTINIT__ONWRITE "oneToClear" /* */
#define NV_NPORT_INITIALIZATION_MCREDSGTINIT_INIT 0x00000000 /* RWE-V */
#define NV_NPORT_INITIALIZATION_MCREDSGTINIT_HWINIT 0x00000001 /* RW--V */
#define NV_NPORT_INITIALIZATION_MCREDBUFINIT 16:16 /* RWEVF */
#define NV_NPORT_INITIALIZATION_MCREDBUFINIT__ONWRITE "oneToClear" /* */
#define NV_NPORT_INITIALIZATION_MCREDBUFINIT_INIT 0x00000000 /* RWE-V */
#define NV_NPORT_INITIALIZATION_MCREDBUFINIT_HWINIT 0x00000001 /* RW--V */
#define NV_NPORT_INITIALIZATION_MCRIDINIT 17:17 /* RWEVF */
#define NV_NPORT_INITIALIZATION_MCRIDINIT__ONWRITE "oneToClear" /* */
#define NV_NPORT_INITIALIZATION_MCRIDINIT_INIT 0x00000000 /* RWE-V */
#define NV_NPORT_INITIALIZATION_MCRIDINIT_HWINIT 0x00000001 /* RW--V */
#define NV_NPORT_INITIALIZATION_EXTMCRIDINIT 18:18 /* RWEVF */
#define NV_NPORT_INITIALIZATION_EXTMCRIDINIT__ONWRITE "oneToClear" /* */
#define NV_NPORT_INITIALIZATION_EXTMCRIDINIT_INIT 0x00000000 /* RWE-V */
#define NV_NPORT_INITIALIZATION_EXTMCRIDINIT_HWINIT 0x00000001 /* RW--V */
#define NV_NPORT_CTRL_SLCG 0x00000050 /* RW-4R */
#define NV_NPORT_CTRL_SLCG_DIS_CG_INGRESS 0:0 /* RWEVF */
#define NV_NPORT_CTRL_SLCG_DIS_CG_INGRESS_ENABLE 0x00000001 /* RWE-V */
#define NV_NPORT_CTRL_SLCG_DIS_CG_INGRESS_DISABLE 0x00000000 /* RW--V */
#define NV_NPORT_CTRL_SLCG_DIS_CG_INGRESS__PROD 0x00000000 /* RW--V */
#define NV_NPORT_CTRL_SLCG_DIS_CG_ROUTE 1:1 /* RWEVF */
#define NV_NPORT_CTRL_SLCG_DIS_CG_ROUTE_ENABLE 0x00000001 /* RWE-V */
#define NV_NPORT_CTRL_SLCG_DIS_CG_ROUTE_DISABLE 0x00000000 /* RW--V */
#define NV_NPORT_CTRL_SLCG_DIS_CG_ROUTE__PROD 0x00000000 /* RW--V */
#define NV_NPORT_CTRL_SLCG_DIS_CG_EGRESS 2:2 /* RWEVF */
#define NV_NPORT_CTRL_SLCG_DIS_CG_EGRESS_ENABLE 0x00000001 /* RWE-V */
#define NV_NPORT_CTRL_SLCG_DIS_CG_EGRESS_DISABLE 0x00000000 /* RW--V */
#define NV_NPORT_CTRL_SLCG_DIS_CG_EGRESS__PROD 0x00000000 /* RW--V */
#define NV_NPORT_CTRL_SLCG_DIS_CG_STRACK 3:3 /* RWEVF */
#define NV_NPORT_CTRL_SLCG_DIS_CG_STRACK_ENABLE 0x00000001 /* RWE-V */
#define NV_NPORT_CTRL_SLCG_DIS_CG_STRACK_DISABLE 0x00000000 /* RW--V */
#define NV_NPORT_CTRL_SLCG_DIS_CG_STRACK__PROD 0x00000000 /* RW--V */
#define NV_NPORT_CTRL_SLCG_DIS_CG_TAGSTATE 4:4 /* RWEVF */
#define NV_NPORT_CTRL_SLCG_DIS_CG_TAGSTATE_ENABLE 0x00000001 /* RWE-V */
#define NV_NPORT_CTRL_SLCG_DIS_CG_TAGSTATE_DISABLE 0x00000000 /* RW--V */
#define NV_NPORT_CTRL_SLCG_DIS_CG_TAGSTATE__PROD 0x00000000 /* RW--V */
#define NV_NPORT_CTRL_SLCG_DIS_CG_TREX 5:5 /* RWEVF */
#define NV_NPORT_CTRL_SLCG_DIS_CG_TREX_ENABLE 0x00000001 /* RWE-V */
#define NV_NPORT_CTRL_SLCG_DIS_CG_TREX_DISABLE 0x00000000 /* RW--V */
#define NV_NPORT_CTRL_SLCG_DIS_CG_TREX__PROD 0x00000000 /* RW--V */
#define NV_NPORT_CTRL_SLCG_DIS_CG_MCTAGSTATE 6:6 /* RWEVF */
#define NV_NPORT_CTRL_SLCG_DIS_CG_MCTAGSTATE_ENABLE 0x00000001 /* RWE-V */
#define NV_NPORT_CTRL_SLCG_DIS_CG_MCTAGSTATE_DISABLE 0x00000000 /* RW--V */
#define NV_NPORT_CTRL_SLCG_DIS_CG_MCTAGSTATE__PROD 0x00000000 /* RW--V */
#define NV_NPORT_CTRL_SLCG_DIS_CG_RDTAGSTATE 7:7 /* RWEVF */
#define NV_NPORT_CTRL_SLCG_DIS_CG_RDTAGSTATE_ENABLE 0x00000001 /* RWE-V */
#define NV_NPORT_CTRL_SLCG_DIS_CG_RDTAGSTATE_DISABLE 0x00000000 /* RW--V */
#define NV_NPORT_CTRL_SLCG_DIS_CG_RDTAGSTATE__PROD 0x00000000 /* RW--V */
#define NV_NPORT_CTRL_SLCG_DIS_CG_WATCHPOINT 31:31 /* RWEVF */
#define NV_NPORT_CTRL_SLCG_DIS_CG_WATCHPOINT_ENABLE 0x00000001 /* RWE-V */
#define NV_NPORT_CTRL_SLCG_DIS_CG_WATCHPOINT_DISABLE 0x00000000 /* RW--V */
#define NV_NPORT_CTRL_SLCG_DIS_CG_WATCHPOINT__PROD 0x00000000 /* RW--V */
#define NV_NPORT_REQLINKID 0x00000054 /* RW-4R */
#define NV_NPORT_REQLINKID_REQROUTINGID 8:0 /* RWEVF */
#define NV_NPORT_REQLINKID_REQROUTINGID_INIT 0x00000000 /* RWE-V */
#define NV_NPORT_REQLINKID_REQROUTINGID_UPPER 10:9 /* RWEVF */
#define NV_NPORT_REQLINKID_REQROUTINGID_UPPER_INIT 0x00000000 /* RWE-V */
#define NV_NPORT_REQLINKID_REQROUTINGLAN 18:15 /* RWEVF */
#define NV_NPORT_REQLINKID_REQROUTINGLAN_INIT 0x00000000 /* RWE-V */
#define NV_NPORT_CONTAIN_AND_DRAIN 0x0000005c /* RW-4R */
#define NV_NPORT_CONTAIN_AND_DRAIN_CLEAR 18:18 /* RWIVF */
#define NV_NPORT_CONTAIN_AND_DRAIN_CLEAR__ONWRITE "oneToClear" /* */
#define NV_NPORT_CONTAIN_AND_DRAIN_CLEAR_ENABLE 0x00000001 /* RW--V */
#define NV_NPORT_CONTAIN_AND_DRAIN_CLEAR_DISABLE 0x00000000 /* RWI-V */
#define NV_NPORT_CONTAIN_AND_DRAIN_DIRTY 19:19 /* R-IVF */
#define NV_NPORT_CONTAIN_AND_DRAIN_DIRTY_DIRTY 0x00000001 /* R---V */
#define NV_NPORT_CONTAIN_AND_DRAIN_DIRTY_CLEAN 0x00000000 /* R-I-V */
#define NV_NPORT_SRC_PORT_TYPE0 0x00000074 /* RW-4R */
#define NV_NPORT_SRC_PORT_TYPE0_TRUNKPORT 31:0 /* RWEVF */
#define NV_NPORT_SRC_PORT_TYPE0_TRUNKPORT_TRUNKPORT 0x00000001 /* RW--V */
#define NV_NPORT_SRC_PORT_TYPE0_TRUNKPORT_ACCESSPORT 0x00000000 /* RWE-V */
#define NV_NPORT_SRC_PORT_TYPE1 0x00000078 /* RW-4R */
#define NV_NPORT_SRC_PORT_TYPE1_TRUNKPORT 31:0 /* RWEVF */
#define NV_NPORT_SRC_PORT_TYPE1_TRUNKPORT_TRUNKPORT 0x00000001 /* RW--V */
#define NV_NPORT_SRC_PORT_TYPE1_TRUNKPORT_ACCESSPORT 0x00000000 /* RWE-V */
#define NV_NPORT_PORTSTAT_CONTROL 0x00000100 /* RW-4R */
#define NV_NPORT_PORTSTAT_CONTROL_RANGESELECT 3:0 /* RWEVF */
#define NV_NPORT_PORTSTAT_CONTROL_RANGESELECT_BITS13TO0 0x00000000 /* RWE-V */
#define NV_NPORT_PORTSTAT_CONTROL_RANGESELECT_BITS15TO2 0x00000001 /* RW--V */
#define NV_NPORT_PORTSTAT_CONTROL_RANGESELECT_BITS17TO4 0x00000002 /* RW--V */
#define NV_NPORT_PORTSTAT_CONTROL_RANGESELECT_BITS19TO6 0x00000003 /* RW--V */
#define NV_NPORT_PORTSTAT_CONTROL_RANGESELECT_BITS21TO8 0x00000004 /* RW--V */
#define NV_NPORT_PORTSTAT_CONTROL_RANGESELECT_BITS23TO10 0x00000005 /* RW--V */
#define NV_NPORT_PORTSTAT_SNAP_CONTROL 0x00000104 /* RW-4R */
#define NV_NPORT_PORTSTAT_SNAP_CONTROL_STARTCOUNTER 0:0 /* RWEVF */
#define NV_NPORT_PORTSTAT_SNAP_CONTROL_STARTCOUNTER_ENABLE 0x00000001 /* RW--V */
#define NV_NPORT_PORTSTAT_SNAP_CONTROL_STARTCOUNTER_DISABLE 0x00000000 /* RWE-V */
#define NV_NPORT_PORTSTAT_SNAP_CONTROL_SNAPONDEMAND 4:4 /* RWEVF */
#define NV_NPORT_PORTSTAT_SNAP_CONTROL_SNAPONDEMAND_ENABLE 0x00000001 /* RW--V */
#define NV_NPORT_PORTSTAT_SNAP_CONTROL_SNAPONDEMAND_DISABLE 0x00000000 /* RWE-V */
#define NV_NPORT_PORTSTAT_LIMIT_LOW_0 0x00000108 /* RW-4R */
#define NV_NPORT_PORTSTAT_LIMIT_LOW_0_LIMIT 23:0 /* RWEVF */
#define NV_NPORT_PORTSTAT_LIMIT_LOW_0_LIMIT_INIT 0x000000c0 /* RWE-V */
#define NV_NPORT_PORTSTAT_LIMIT_MEDIUM_0 0x0000010c /* RW-4R */
#define NV_NPORT_PORTSTAT_LIMIT_MEDIUM_0_LIMIT 23:0 /* RWEVF */
#define NV_NPORT_PORTSTAT_LIMIT_MEDIUM_0_LIMIT_INIT 0x00000140 /* RWE-V */
#define NV_NPORT_PORTSTAT_LIMIT_HIGH_0 0x00000110 /* RW-4R */
#define NV_NPORT_PORTSTAT_LIMIT_HIGH_0_LIMIT 23:0 /* RWEVF */
#define NV_NPORT_PORTSTAT_LIMIT_HIGH_0_LIMIT_INIT 0x00000680 /* RWE-V */
#define NV_NPORT_PORTSTAT_PACKET_COUNT_0_0 0x00000114 /* RW-4R */
#define NV_NPORT_PORTSTAT_PACKET_COUNT_0_0_PACKETCOUNT 31:0 /* RWXVF */
#define NV_NPORT_PORTSTAT_PACKET_COUNT_0_1 0x00000118 /* RW-4R */
#define NV_NPORT_PORTSTAT_PACKET_COUNT_0_1_PACKETCOUNT 15:0 /* RWXVF */
#define NV_NPORT_PORTSTAT_COUNT_LOW_0_0 0x0000011c /* RW-4R */
#define NV_NPORT_PORTSTAT_COUNT_LOW_0_0_PACKETCOUNT 31:0 /* RWXVF */
#define NV_NPORT_PORTSTAT_COUNT_LOW_0_1 0x00000120 /* RW-4R */
#define NV_NPORT_PORTSTAT_COUNT_LOW_0_1_PACKETCOUNT 15:0 /* RWXVF */
#define NV_NPORT_PORTSTAT_COUNT_MEDIUM_0_0 0x00000124 /* RW-4R */
#define NV_NPORT_PORTSTAT_COUNT_MEDIUM_0_0_PACKETCOUNT 31:0 /* RWXVF */
#define NV_NPORT_PORTSTAT_COUNT_MEDIUM_0_1 0x00000128 /* RW-4R */
#define NV_NPORT_PORTSTAT_COUNT_MEDIUM_0_1_PACKETCOUNT 15:0 /* RWXVF */
#define NV_NPORT_PORTSTAT_COUNT_HIGH_0_0 0x0000012c /* RW-4R */
#define NV_NPORT_PORTSTAT_COUNT_HIGH_0_0_PACKETCOUNT 31:0 /* RWXVF */
#define NV_NPORT_PORTSTAT_COUNT_HIGH_0_1 0x00000130 /* RW-4R */
#define NV_NPORT_PORTSTAT_COUNT_HIGH_0_1_PACKETCOUNT 15:0 /* RWXVF */
#define NV_NPORT_PORTSTAT_COUNT_PANIC_0_0 0x00000134 /* RW-4R */
#define NV_NPORT_PORTSTAT_COUNT_PANIC_0_0_PACKETCOUNT 31:0 /* RWXVF */
#define NV_NPORT_PORTSTAT_COUNT_PANIC_0_1 0x00000138 /* RW-4R */
#define NV_NPORT_PORTSTAT_COUNT_PANIC_0_1_PACKETCOUNT 15:0 /* RWXVF */
#define NV_NPORT_PORTSTAT_LIMIT_LOW_1 0x0000013c /* RW-4R */
#define NV_NPORT_PORTSTAT_LIMIT_LOW_1_LIMIT 23:0 /* RWEVF */
#define NV_NPORT_PORTSTAT_LIMIT_LOW_1_LIMIT_INIT 0x000000c0 /* RWE-V */
#define NV_NPORT_PORTSTAT_LIMIT_MEDIUM_1 0x00000140 /* RW-4R */
#define NV_NPORT_PORTSTAT_LIMIT_MEDIUM_1_LIMIT 23:0 /* RWEVF */
#define NV_NPORT_PORTSTAT_LIMIT_MEDIUM_1_LIMIT_INIT 0x00000140 /* RWE-V */
#define NV_NPORT_PORTSTAT_LIMIT_HIGH_1 0x00000144 /* RW-4R */
#define NV_NPORT_PORTSTAT_LIMIT_HIGH_1_LIMIT 23:0 /* RWEVF */
#define NV_NPORT_PORTSTAT_LIMIT_HIGH_1_LIMIT_INIT 0x00000680 /* RWE-V */
#define NV_NPORT_PORTSTAT_PACKET_COUNT_1_0 0x00000148 /* RW-4R */
#define NV_NPORT_PORTSTAT_PACKET_COUNT_1_0_PACKETCOUNT 31:0 /* RWXVF */
#define NV_NPORT_PORTSTAT_PACKET_COUNT_1_1 0x0000014c /* RW-4R */
#define NV_NPORT_PORTSTAT_PACKET_COUNT_1_1_PACKETCOUNT 15:0 /* RWXVF */
#define NV_NPORT_PORTSTAT_COUNT_LOW_1_0 0x00000150 /* RW-4R */
#define NV_NPORT_PORTSTAT_COUNT_LOW_1_0_PACKETCOUNT 31:0 /* RWXVF */
#define NV_NPORT_PORTSTAT_COUNT_LOW_1_1 0x00000154 /* RW-4R */
#define NV_NPORT_PORTSTAT_COUNT_LOW_1_1_PACKETCOUNT 15:0 /* RWXVF */
#define NV_NPORT_PORTSTAT_COUNT_MEDIUM_1_0 0x00000158 /* RW-4R */
#define NV_NPORT_PORTSTAT_COUNT_MEDIUM_1_0_PACKETCOUNT 31:0 /* RWXVF */
#define NV_NPORT_PORTSTAT_COUNT_MEDIUM_1_1 0x0000015c /* RW-4R */
#define NV_NPORT_PORTSTAT_COUNT_MEDIUM_1_1_PACKETCOUNT 15:0 /* RWXVF */
#define NV_NPORT_PORTSTAT_COUNT_HIGH_1_0 0x00000160 /* RW-4R */
#define NV_NPORT_PORTSTAT_COUNT_HIGH_1_0_PACKETCOUNT 31:0 /* RWXVF */
#define NV_NPORT_PORTSTAT_COUNT_HIGH_1_1 0x00000164 /* RW-4R */
#define NV_NPORT_PORTSTAT_COUNT_HIGH_1_1_PACKETCOUNT 15:0 /* RWXVF */
#define NV_NPORT_PORTSTAT_COUNT_PANIC_1_0 0x00000168 /* RW-4R */
#define NV_NPORT_PORTSTAT_COUNT_PANIC_1_0_PACKETCOUNT 31:0 /* RWXVF */
#define NV_NPORT_PORTSTAT_COUNT_PANIC_1_1 0x0000016c /* RW-4R */
#define NV_NPORT_PORTSTAT_COUNT_PANIC_1_1_PACKETCOUNT 15:0 /* RWXVF */
#define NV_NPORT_PORTSTAT_LIMIT_LOW_2 0x00000170 /* RW-4R */
#define NV_NPORT_PORTSTAT_LIMIT_LOW_2_LIMIT 23:0 /* RWEVF */
#define NV_NPORT_PORTSTAT_LIMIT_LOW_2_LIMIT_INIT 0x000000c0 /* RWE-V */
#define NV_NPORT_PORTSTAT_LIMIT_MEDIUM_2 0x00000174 /* RW-4R */
#define NV_NPORT_PORTSTAT_LIMIT_MEDIUM_2_LIMIT 23:0 /* RWEVF */
#define NV_NPORT_PORTSTAT_LIMIT_MEDIUM_2_LIMIT_INIT 0x00000140 /* RWE-V */
#define NV_NPORT_PORTSTAT_LIMIT_HIGH_2 0x00000178 /* RW-4R */
#define NV_NPORT_PORTSTAT_LIMIT_HIGH_2_LIMIT 23:0 /* RWEVF */
#define NV_NPORT_PORTSTAT_LIMIT_HIGH_2_LIMIT_INIT 0x00000680 /* RWE-V */
#define NV_NPORT_PORTSTAT_PACKET_COUNT_2_0 0x0000017c /* RW-4R */
#define NV_NPORT_PORTSTAT_PACKET_COUNT_2_0_PACKETCOUNT 31:0 /* RWXVF */
#define NV_NPORT_PORTSTAT_PACKET_COUNT_2_1 0x00000180 /* RW-4R */
#define NV_NPORT_PORTSTAT_PACKET_COUNT_2_1_PACKETCOUNT 15:0 /* RWXVF */
#define NV_NPORT_PORTSTAT_COUNT_LOW_2_0 0x00000184 /* RW-4R */
#define NV_NPORT_PORTSTAT_COUNT_LOW_2_0_PACKETCOUNT 31:0 /* RWXVF */
#define NV_NPORT_PORTSTAT_COUNT_LOW_2_1 0x00000188 /* RW-4R */
#define NV_NPORT_PORTSTAT_COUNT_LOW_2_1_PACKETCOUNT 15:0 /* RWXVF */
#define NV_NPORT_PORTSTAT_COUNT_MEDIUM_2_0 0x0000018c /* RW-4R */
#define NV_NPORT_PORTSTAT_COUNT_MEDIUM_2_0_PACKETCOUNT 31:0 /* RWXVF */
#define NV_NPORT_PORTSTAT_COUNT_MEDIUM_2_1 0x00000190 /* RW-4R */
#define NV_NPORT_PORTSTAT_COUNT_MEDIUM_2_1_PACKETCOUNT 15:0 /* RWXVF */
#define NV_NPORT_PORTSTAT_COUNT_HIGH_2_0 0x00000194 /* RW-4R */
#define NV_NPORT_PORTSTAT_COUNT_HIGH_2_0_PACKETCOUNT 31:0 /* RWXVF */
#define NV_NPORT_PORTSTAT_COUNT_HIGH_2_1 0x00000198 /* RW-4R */
#define NV_NPORT_PORTSTAT_COUNT_HIGH_2_1_PACKETCOUNT 15:0 /* RWXVF */
#define NV_NPORT_PORTSTAT_COUNT_PANIC_2_0 0x0000019c /* RW-4R */
#define NV_NPORT_PORTSTAT_COUNT_PANIC_2_0_PACKETCOUNT 31:0 /* RWXVF */
#define NV_NPORT_PORTSTAT_COUNT_PANIC_2_1 0x000001a0 /* RW-4R */
#define NV_NPORT_PORTSTAT_COUNT_PANIC_2_1_PACKETCOUNT 15:0 /* RWXVF */
#define NV_NPORT_PORTSTAT_LIMIT_LOW_3 0x000001a4 /* RW-4R */
#define NV_NPORT_PORTSTAT_LIMIT_LOW_3_LIMIT 23:0 /* RWEVF */
#define NV_NPORT_PORTSTAT_LIMIT_LOW_3_LIMIT_INIT 0x000000c0 /* RWE-V */
#define NV_NPORT_PORTSTAT_LIMIT_MEDIUM_3 0x000001a8 /* RW-4R */
#define NV_NPORT_PORTSTAT_LIMIT_MEDIUM_3_LIMIT 23:0 /* RWEVF */
#define NV_NPORT_PORTSTAT_LIMIT_MEDIUM_3_LIMIT_INIT 0x00000140 /* RWE-V */
#define NV_NPORT_PORTSTAT_LIMIT_HIGH_3 0x000001ac /* RW-4R */
#define NV_NPORT_PORTSTAT_LIMIT_HIGH_3_LIMIT 23:0 /* RWEVF */
#define NV_NPORT_PORTSTAT_LIMIT_HIGH_3_LIMIT_INIT 0x00000680 /* RWE-V */
#define NV_NPORT_PORTSTAT_PACKET_COUNT_3_0 0x000001b0 /* RW-4R */
#define NV_NPORT_PORTSTAT_PACKET_COUNT_3_0_PACKETCOUNT 31:0 /* RWXVF */
#define NV_NPORT_PORTSTAT_PACKET_COUNT_3_1 0x000001b4 /* RW-4R */
#define NV_NPORT_PORTSTAT_PACKET_COUNT_3_1_PACKETCOUNT 15:0 /* RWXVF */
#define NV_NPORT_PORTSTAT_COUNT_LOW_3_0 0x000001b8 /* RW-4R */
#define NV_NPORT_PORTSTAT_COUNT_LOW_3_0_PACKETCOUNT 31:0 /* RWXVF */
#define NV_NPORT_PORTSTAT_COUNT_LOW_3_1 0x000001bc /* RW-4R */
#define NV_NPORT_PORTSTAT_COUNT_LOW_3_1_PACKETCOUNT 15:0 /* RWXVF */
#define NV_NPORT_PORTSTAT_COUNT_MEDIUM_3_0 0x000001c0 /* RW-4R */
#define NV_NPORT_PORTSTAT_COUNT_MEDIUM_3_0_PACKETCOUNT 31:0 /* RWXVF */
#define NV_NPORT_PORTSTAT_COUNT_MEDIUM_3_1 0x000001c4 /* RW-4R */
#define NV_NPORT_PORTSTAT_COUNT_MEDIUM_3_1_PACKETCOUNT 15:0 /* RWXVF */
#define NV_NPORT_PORTSTAT_COUNT_HIGH_3_0 0x000001c8 /* RW-4R */
#define NV_NPORT_PORTSTAT_COUNT_HIGH_3_0_PACKETCOUNT 31:0 /* RWXVF */
#define NV_NPORT_PORTSTAT_COUNT_HIGH_3_1 0x000001cc /* RW-4R */
#define NV_NPORT_PORTSTAT_COUNT_HIGH_3_1_PACKETCOUNT 15:0 /* RWXVF */
#define NV_NPORT_PORTSTAT_COUNT_PANIC_3_0 0x000001d0 /* RW-4R */
#define NV_NPORT_PORTSTAT_COUNT_PANIC_3_0_PACKETCOUNT 31:0 /* RWXVF */
#define NV_NPORT_PORTSTAT_COUNT_PANIC_3_1 0x000001d4 /* RW-4R */
#define NV_NPORT_PORTSTAT_COUNT_PANIC_3_1_PACKETCOUNT 15:0 /* RWXVF */
#define NV_NPORT_PORTSTAT_LIMIT_LOW_4 0x000001d8 /* RW-4R */
#define NV_NPORT_PORTSTAT_LIMIT_LOW_4_LIMIT 23:0 /* RWEVF */
#define NV_NPORT_PORTSTAT_LIMIT_LOW_4_LIMIT_INIT 0x000000c0 /* RWE-V */
#define NV_NPORT_PORTSTAT_LIMIT_MEDIUM_4 0x000001dc /* RW-4R */
#define NV_NPORT_PORTSTAT_LIMIT_MEDIUM_4_LIMIT 23:0 /* RWEVF */
#define NV_NPORT_PORTSTAT_LIMIT_MEDIUM_4_LIMIT_INIT 0x00000140 /* RWE-V */
#define NV_NPORT_PORTSTAT_LIMIT_HIGH_4 0x000001e0 /* RW-4R */
#define NV_NPORT_PORTSTAT_LIMIT_HIGH_4_LIMIT 23:0 /* RWEVF */
#define NV_NPORT_PORTSTAT_LIMIT_HIGH_4_LIMIT_INIT 0x00000680 /* RWE-V */
#define NV_NPORT_PORTSTAT_PACKET_COUNT_4_0 0x000001e4 /* RW-4R */
#define NV_NPORT_PORTSTAT_PACKET_COUNT_4_0_PACKETCOUNT 31:0 /* RWXVF */
#define NV_NPORT_PORTSTAT_PACKET_COUNT_4_1 0x000001e8 /* RW-4R */
#define NV_NPORT_PORTSTAT_PACKET_COUNT_4_1_PACKETCOUNT 15:0 /* RWXVF */
#define NV_NPORT_PORTSTAT_COUNT_LOW_4_0 0x000001ec /* RW-4R */
#define NV_NPORT_PORTSTAT_COUNT_LOW_4_0_PACKETCOUNT 31:0 /* RWXVF */
#define NV_NPORT_PORTSTAT_COUNT_LOW_4_1 0x000001f0 /* RW-4R */
#define NV_NPORT_PORTSTAT_COUNT_LOW_4_1_PACKETCOUNT 15:0 /* RWXVF */
#define NV_NPORT_PORTSTAT_COUNT_MEDIUM_4_0 0x000001f4 /* RW-4R */
#define NV_NPORT_PORTSTAT_COUNT_MEDIUM_4_0_PACKETCOUNT 31:0 /* RWXVF */
#define NV_NPORT_PORTSTAT_COUNT_MEDIUM_4_1 0x000001f8 /* RW-4R */
#define NV_NPORT_PORTSTAT_COUNT_MEDIUM_4_1_PACKETCOUNT 15:0 /* RWXVF */
#define NV_NPORT_PORTSTAT_COUNT_HIGH_4_0 0x000001fc /* RW-4R */
#define NV_NPORT_PORTSTAT_COUNT_HIGH_4_0_PACKETCOUNT 31:0 /* RWXVF */
#define NV_NPORT_PORTSTAT_COUNT_HIGH_4_1 0x00000200 /* RW-4R */
#define NV_NPORT_PORTSTAT_COUNT_HIGH_4_1_PACKETCOUNT 15:0 /* RWXVF */
#define NV_NPORT_PORTSTAT_COUNT_PANIC_4_0 0x00000204 /* RW-4R */
#define NV_NPORT_PORTSTAT_COUNT_PANIC_4_0_PACKETCOUNT 31:0 /* RWXVF */
#define NV_NPORT_PORTSTAT_COUNT_PANIC_4_1 0x00000208 /* RW-4R */
#define NV_NPORT_PORTSTAT_COUNT_PANIC_4_1_PACKETCOUNT 15:0 /* RWXVF */
#define NV_NPORT_PORTSTAT_LIMIT_LOW_5 0x0000020c /* RW-4R */
#define NV_NPORT_PORTSTAT_LIMIT_LOW_5_LIMIT 23:0 /* RWEVF */
#define NV_NPORT_PORTSTAT_LIMIT_LOW_5_LIMIT_INIT 0x000000c0 /* RWE-V */
#define NV_NPORT_PORTSTAT_LIMIT_MEDIUM_5 0x00000210 /* RW-4R */
#define NV_NPORT_PORTSTAT_LIMIT_MEDIUM_5_LIMIT 23:0 /* RWEVF */
#define NV_NPORT_PORTSTAT_LIMIT_MEDIUM_5_LIMIT_INIT 0x00000140 /* RWE-V */
#define NV_NPORT_PORTSTAT_LIMIT_HIGH_5 0x00000214 /* RW-4R */
#define NV_NPORT_PORTSTAT_LIMIT_HIGH_5_LIMIT 23:0 /* RWEVF */
#define NV_NPORT_PORTSTAT_LIMIT_HIGH_5_LIMIT_INIT 0x00000680 /* RWE-V */
#define NV_NPORT_PORTSTAT_PACKET_COUNT_5_0 0x00000218 /* RW-4R */
#define NV_NPORT_PORTSTAT_PACKET_COUNT_5_0_PACKETCOUNT 31:0 /* RWXVF */
#define NV_NPORT_PORTSTAT_PACKET_COUNT_5_1 0x0000021c /* RW-4R */
#define NV_NPORT_PORTSTAT_PACKET_COUNT_5_1_PACKETCOUNT 15:0 /* RWXVF */
#define NV_NPORT_PORTSTAT_COUNT_LOW_5_0 0x00000220 /* RW-4R */
#define NV_NPORT_PORTSTAT_COUNT_LOW_5_0_PACKETCOUNT 31:0 /* RWXVF */
#define NV_NPORT_PORTSTAT_COUNT_LOW_5_1 0x00000224 /* RW-4R */
#define NV_NPORT_PORTSTAT_COUNT_LOW_5_1_PACKETCOUNT 15:0 /* RWXVF */
#define NV_NPORT_PORTSTAT_COUNT_MEDIUM_5_0 0x00000228 /* RW-4R */
#define NV_NPORT_PORTSTAT_COUNT_MEDIUM_5_0_PACKETCOUNT 31:0 /* RWXVF */
#define NV_NPORT_PORTSTAT_COUNT_MEDIUM_5_1 0x0000022c /* RW-4R */
#define NV_NPORT_PORTSTAT_COUNT_MEDIUM_5_1_PACKETCOUNT 15:0 /* RWXVF */
#define NV_NPORT_PORTSTAT_COUNT_HIGH_5_0 0x00000230 /* RW-4R */
#define NV_NPORT_PORTSTAT_COUNT_HIGH_5_0_PACKETCOUNT 31:0 /* RWXVF */
#define NV_NPORT_PORTSTAT_COUNT_HIGH_5_1 0x00000234 /* RW-4R */
#define NV_NPORT_PORTSTAT_COUNT_HIGH_5_1_PACKETCOUNT 15:0 /* RWXVF */
#define NV_NPORT_PORTSTAT_COUNT_PANIC_5_0 0x00000238 /* RW-4R */
#define NV_NPORT_PORTSTAT_COUNT_PANIC_5_0_PACKETCOUNT 31:0 /* RWXVF */
#define NV_NPORT_PORTSTAT_COUNT_PANIC_5_1 0x0000023c /* RW-4R */
#define NV_NPORT_PORTSTAT_COUNT_PANIC_5_1_PACKETCOUNT 15:0 /* RWXVF */
#define NV_NPORT_PORTSTAT_LIMIT_LOW_6 0x00000240 /* RW-4R */
#define NV_NPORT_PORTSTAT_LIMIT_LOW_6_LIMIT 23:0 /* RWEVF */
#define NV_NPORT_PORTSTAT_LIMIT_LOW_6_LIMIT_INIT 0x000000c0 /* RWE-V */
#define NV_NPORT_PORTSTAT_LIMIT_MEDIUM_6 0x00000244 /* RW-4R */
#define NV_NPORT_PORTSTAT_LIMIT_MEDIUM_6_LIMIT 23:0 /* RWEVF */
#define NV_NPORT_PORTSTAT_LIMIT_MEDIUM_6_LIMIT_INIT 0x00000140 /* RWE-V */
#define NV_NPORT_PORTSTAT_LIMIT_HIGH_6 0x00000248 /* RW-4R */
#define NV_NPORT_PORTSTAT_LIMIT_HIGH_6_LIMIT 23:0 /* RWEVF */
#define NV_NPORT_PORTSTAT_LIMIT_HIGH_6_LIMIT_INIT 0x00000680 /* RWE-V */
#define NV_NPORT_PORTSTAT_PACKET_COUNT_6_0 0x0000024c /* RW-4R */
#define NV_NPORT_PORTSTAT_PACKET_COUNT_6_0_PACKETCOUNT 31:0 /* RWXVF */
#define NV_NPORT_PORTSTAT_PACKET_COUNT_6_1 0x00000250 /* RW-4R */
#define NV_NPORT_PORTSTAT_PACKET_COUNT_6_1_PACKETCOUNT 15:0 /* RWXVF */
#define NV_NPORT_PORTSTAT_COUNT_LOW_6_0 0x00000254 /* RW-4R */
#define NV_NPORT_PORTSTAT_COUNT_LOW_6_0_PACKETCOUNT 31:0 /* RWXVF */
#define NV_NPORT_PORTSTAT_COUNT_LOW_6_1 0x00000258 /* RW-4R */
#define NV_NPORT_PORTSTAT_COUNT_LOW_6_1_PACKETCOUNT 15:0 /* RWXVF */
#define NV_NPORT_PORTSTAT_COUNT_MEDIUM_6_0 0x0000025c /* RW-4R */
#define NV_NPORT_PORTSTAT_COUNT_MEDIUM_6_0_PACKETCOUNT 31:0 /* RWXVF */
#define NV_NPORT_PORTSTAT_COUNT_MEDIUM_6_1 0x00000260 /* RW-4R */
#define NV_NPORT_PORTSTAT_COUNT_MEDIUM_6_1_PACKETCOUNT 15:0 /* RWXVF */
#define NV_NPORT_PORTSTAT_COUNT_HIGH_6_0 0x00000264 /* RW-4R */
#define NV_NPORT_PORTSTAT_COUNT_HIGH_6_0_PACKETCOUNT 31:0 /* RWXVF */
#define NV_NPORT_PORTSTAT_COUNT_HIGH_6_1 0x00000268 /* RW-4R */
#define NV_NPORT_PORTSTAT_COUNT_HIGH_6_1_PACKETCOUNT 15:0 /* RWXVF */
#define NV_NPORT_PORTSTAT_COUNT_PANIC_6_0 0x0000026c /* RW-4R */
#define NV_NPORT_PORTSTAT_COUNT_PANIC_6_0_PACKETCOUNT 31:0 /* RWXVF */
#define NV_NPORT_PORTSTAT_COUNT_PANIC_6_1 0x00000270 /* RW-4R */
#define NV_NPORT_PORTSTAT_COUNT_PANIC_6_1_PACKETCOUNT 15:0 /* RWXVF */
#define NV_NPORT_PORTSTAT_LIMIT_LOW_7 0x00000274 /* RW-4R */
#define NV_NPORT_PORTSTAT_LIMIT_LOW_7_LIMIT 23:0 /* RWEVF */
#define NV_NPORT_PORTSTAT_LIMIT_LOW_7_LIMIT_INIT 0x000000c0 /* RWE-V */
#define NV_NPORT_PORTSTAT_LIMIT_MEDIUM_7 0x00000278 /* RW-4R */
#define NV_NPORT_PORTSTAT_LIMIT_MEDIUM_7_LIMIT 23:0 /* RWEVF */
#define NV_NPORT_PORTSTAT_LIMIT_MEDIUM_7_LIMIT_INIT 0x00000140 /* RWE-V */
#define NV_NPORT_PORTSTAT_LIMIT_HIGH_7 0x0000027c /* RW-4R */
#define NV_NPORT_PORTSTAT_LIMIT_HIGH_7_LIMIT 23:0 /* RWEVF */
#define NV_NPORT_PORTSTAT_LIMIT_HIGH_7_LIMIT_INIT 0x00000680 /* RWE-V */
#define NV_NPORT_PORTSTAT_PACKET_COUNT_7_0 0x00000280 /* RW-4R */
#define NV_NPORT_PORTSTAT_PACKET_COUNT_7_0_PACKETCOUNT 31:0 /* RWXVF */
#define NV_NPORT_PORTSTAT_PACKET_COUNT_7_1 0x00000284 /* RW-4R */
#define NV_NPORT_PORTSTAT_PACKET_COUNT_7_1_PACKETCOUNT 15:0 /* RWXVF */
#define NV_NPORT_PORTSTAT_COUNT_LOW_7_0 0x00000288 /* RW-4R */
#define NV_NPORT_PORTSTAT_COUNT_LOW_7_0_PACKETCOUNT 31:0 /* RWXVF */
#define NV_NPORT_PORTSTAT_COUNT_LOW_7_1 0x0000028c /* RW-4R */
#define NV_NPORT_PORTSTAT_COUNT_LOW_7_1_PACKETCOUNT 15:0 /* RWXVF */
#define NV_NPORT_PORTSTAT_COUNT_MEDIUM_7_0 0x00000290 /* RW-4R */
#define NV_NPORT_PORTSTAT_COUNT_MEDIUM_7_0_PACKETCOUNT 31:0 /* RWXVF */
#define NV_NPORT_PORTSTAT_COUNT_MEDIUM_7_1 0x00000294 /* RW-4R */
#define NV_NPORT_PORTSTAT_COUNT_MEDIUM_7_1_PACKETCOUNT 15:0 /* RWXVF */
#define NV_NPORT_PORTSTAT_COUNT_HIGH_7_0 0x00000298 /* RW-4R */
#define NV_NPORT_PORTSTAT_COUNT_HIGH_7_0_PACKETCOUNT 31:0 /* RWXVF */
#define NV_NPORT_PORTSTAT_COUNT_HIGH_7_1 0x0000029c /* RW-4R */
#define NV_NPORT_PORTSTAT_COUNT_HIGH_7_1_PACKETCOUNT 15:0 /* RWXVF */
#define NV_NPORT_PORTSTAT_COUNT_PANIC_7_0 0x000002a0 /* RW-4R */
#define NV_NPORT_PORTSTAT_COUNT_PANIC_7_0_PACKETCOUNT 31:0 /* RWXVF */
#define NV_NPORT_PORTSTAT_COUNT_PANIC_7_1 0x000002a4 /* RW-4R */
#define NV_NPORT_PORTSTAT_COUNT_PANIC_7_1_PACKETCOUNT 15:0 /* RWXVF */
#define NV_NPORT_PORTSTAT_SOURCE_FILTER_0 0x000002a8 /* RW-4R */
#define NV_NPORT_PORTSTAT_SOURCE_FILTER_0_SRCFILTERBIT 31:0 /* RWEVF */
#define NV_NPORT_PORTSTAT_SOURCE_FILTER_0_SRCFILTERBIT_INIT 0x00000000 /* RWE-V */
#define NV_NPORT_PORTSTAT_SOURCE_FILTER_1 0x000002ac /* RW-4R */
#define NV_NPORT_PORTSTAT_SOURCE_FILTER_1_SRCFILTERBIT 31:0 /* RWEVF */
#define NV_NPORT_PORTSTAT_SOURCE_FILTER_1_SRCFILTERBIT_INIT 0x00000000 /* RWE-V */
#define NV_NPORT_ERR_CONTROL_COMMON_NPORT 0x00000470 /* RW-4R */
#define NV_NPORT_ERR_CONTROL_COMMON_NPORT_CORRECTABLEENABLE 0:0 /* RWEVF */
#define NV_NPORT_ERR_CONTROL_COMMON_NPORT_CORRECTABLEENABLE_INIT 0x00000001 /* RWE-V */
#define NV_NPORT_ERR_CONTROL_COMMON_NPORT_FATALENABLE 1:1 /* RWEVF */
#define NV_NPORT_ERR_CONTROL_COMMON_NPORT_FATALENABLE_INIT 0x00000001 /* RWE-V */
#define NV_NPORT_ERR_CONTROL_COMMON_NPORT_NONFATALENABLE 2:2 /* RWEVF */
#define NV_NPORT_ERR_CONTROL_COMMON_NPORT_NONFATALENABLE_INIT 0x00000001 /* RWE-V */
#define NV_NPORT_MCID_ERROR_VECTOR(i) (0x00000480+(i)*0x4) /* RW-4A */
#define NV_NPORT_MCID_ERROR_VECTOR__SIZE_1 4 /* */
#define NV_NPORT_MCID_ERROR_VECTOR_STATUS 31:0 /* RWEVF */
#define NV_NPORT_MCID_ERROR_VECTOR_STATUS__ONWRITE "oneToClear" /* */
#define NV_NPORT_MCID_ERROR_VECTOR_STATUS_INIT 0x00000000 /* RWE-V */
#define NV_NPORT_MCID_ERROR_VECTOR_STATUS_CLEAR 0x00000001 /* RW--V */
#define NV_NPORT_SCRATCH_WARM 0x00000fc0 /* RW-4R */
#define NV_NPORT_SCRATCH_WARM_DATA 31:0 /* RWEVF */
#define NV_NPORT_SCRATCH_WARM_DATA_INIT 0xdeadbaad /* RWE-V */
#endif // __ls10_dev_nport_ip_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the Software),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __ls10_dev_nport_ip_addendum_h__
#define __ls10_dev_nport_ip_addendum_h__
// VC mapping
#define NV_NPORT_VC_MAPPING_CREQ0 0x0
#define NV_NPORT_VC_MAPPING_RSP0 0x5
#define NV_NPORT_VC_MAPPING_CREQ1 0x6
#define NV_NPORT_VC_MAPPING_RSP1 0x7
#define NV_NPORT_SCRATCH_WARM_PORT_RESET_REQUIRED 0:0
#endif // __ls10_dev_nport_ip_addendum_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the Software),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __ls10_dev_nv_xal_ep_h__
#define __ls10_dev_nv_xal_ep_h__
/* This file is autogenerated. Do not edit */
#define NV_XAL_EP 0x00000FFF:0x00000000 /* RW--D */
#define NV_XAL_EP_CG 0x00000A00 /* RW-4R */
#define NV_XAL_EP_CG_IDLE_CG_DLY_CNT 5:0 /* RWIVF */
#define NV_XAL_EP_CG_IDLE_CG_DLY_CNT_HWINIT 0x00000000 /* RWI-V */
#define NV_XAL_EP_CG_IDLE_CG_DLY_CNT__PROD 0x00000002 /* ----V */
#define NV_XAL_EP_CG_IDLE_CG_EN 6:6 /* RWIVF */
#define NV_XAL_EP_CG_IDLE_CG_EN_ENABLED 0x00000001 /* RW--V */
#define NV_XAL_EP_CG_IDLE_CG_EN_DISABLED 0x00000000 /* RWI-V */
#define NV_XAL_EP_CG_IDLE_CG_EN__PROD 0x00000001 /* ----V */
#define NV_XAL_EP_CG_STATE_CG_EN 7:7 /* */
#define NV_XAL_EP_CG_STATE_CG_EN_ENABLED 0x00000001 /* */
#define NV_XAL_EP_CG_STATE_CG_EN_DISABLED 0x00000000 /* */
#define NV_XAL_EP_CG_STATE_CG_EN__PROD 0x00000001 /* */
#define NV_XAL_EP_CG_STALL_CG_DLY_CNT 13:8 /* */
#define NV_XAL_EP_CG_STALL_CG_DLY_CNT_HWINIT 0x00000000 /* */
#define NV_XAL_EP_CG_STALL_CG_DLY_CNT__PROD 0x00000000 /* */
#define NV_XAL_EP_CG_STALL_CG_EN 14:14 /* RWIVF */
#define NV_XAL_EP_CG_STALL_CG_EN_ENABLED 0x00000001 /* RW--V */
#define NV_XAL_EP_CG_STALL_CG_EN_DISABLED 0x00000000 /* RWI-V */
#define NV_XAL_EP_CG_STALL_CG_EN__PROD 0x00000000 /* RW--V */
#define NV_XAL_EP_CG_QUIESCENT_CG_EN 15:15 /* */
#define NV_XAL_EP_CG_QUIESCENT_CG_EN_ENABLED 0x00000001 /* */
#define NV_XAL_EP_CG_QUIESCENT_CG_EN_DISABLED 0x00000000 /* */
#define NV_XAL_EP_CG_QUIESCENT_CG_EN__PROD 0x00000000 /* */
#define NV_XAL_EP_CG_WAKEUP_DLY_CNT 19:16 /* RWIVF */
#define NV_XAL_EP_CG_WAKEUP_DLY_CNT_HWINIT 0x00000000 /* RWI-V */
#define NV_XAL_EP_CG_WAKEUP_DLY_CNT__PROD 0x00000000 /* RW--V */
#define NV_XAL_EP_CG_THROT_CLK_CNT 23:20 /* */
#define NV_XAL_EP_CG_THROT_CLK_CNT_FULLSPEED 0x0000000f /* */
#define NV_XAL_EP_CG_THROT_CLK_CNT__PROD 0x00000000 /* */
#define NV_XAL_EP_CG_DI_DT_SKEW_VAL 27:24 /* */
#define NV_XAL_EP_CG_DI_DT_SKEW_VAL_HWINIT 0x00000000 /* */
#define NV_XAL_EP_CG_DI_DT_SKEW_VAL__PROD 0x00000000 /* */
#define NV_XAL_EP_CG_THROT_CLK_EN 28:28 /* */
#define NV_XAL_EP_CG_THROT_CLK_EN_ENABLED 0x00000001 /* */
#define NV_XAL_EP_CG_THROT_CLK_EN_DISABLED 0x00000000 /* */
#define NV_XAL_EP_CG_THROT_CLK_EN__PROD 0x00000000 /* */
#define NV_XAL_EP_CG_THROT_CLK_SW_OVER 29:29 /* */
#define NV_XAL_EP_CG_THROT_CLK_SW_OVER_EN 0x00000001 /* */
#define NV_XAL_EP_CG_THROT_CLK_SW_OVER_DIS 0x00000000 /* */
#define NV_XAL_EP_CG_THROT_CLK_SW_OVER__PROD 0x00000000 /* */
#define NV_XAL_EP_CG_PAUSE_CG_EN 30:30 /* */
#define NV_XAL_EP_CG_PAUSE_CG_EN_ENABLED 0x00000001 /* */
#define NV_XAL_EP_CG_PAUSE_CG_EN_DISABLED 0x00000000 /* */
#define NV_XAL_EP_CG_PAUSE_CG_EN__PROD 0x00000000 /* */
#define NV_XAL_EP_CG_HALT_CG_EN 31:31 /* */
#define NV_XAL_EP_CG_HALT_CG_EN_ENABLED 0x00000001 /* */
#define NV_XAL_EP_CG_HALT_CG_EN_DISABLED 0x00000000 /* */
#define NV_XAL_EP_CG_HALT_CG_EN__PROD 0x00000000 /* */
#define NV_XAL_EP_CG1 0x00000A04 /* RW-4R */
#define NV_XAL_EP_CG1_MONITOR_CG_EN 0:0 /* RWIVF */
#define NV_XAL_EP_CG1_MONITOR_CG_EN_ENABLED 0x00000001 /* RW--V */
#define NV_XAL_EP_CG1_MONITOR_CG_EN_DISABLED 0x00000000 /* RWI-V */
#define NV_XAL_EP_CG1_MONITOR_CG_EN__PROD 0x00000000 /* RW--V */
#define NV_XAL_EP_CG1_SLCG 24:2 /* */
#define NV_XAL_EP_CG1_SLCG_ENABLED 0x00000000 /* */
#define NV_XAL_EP_CG1_SLCG_DISABLED 0x007fffff /* */
#define NV_XAL_EP_CG1_SLCG__PROD 0x00000000 /* */
#define NV_XAL_EP_CG1_SLCG_DOWNARB 2:2 /* RWIVF */
#define NV_XAL_EP_CG1_SLCG_DOWNARB_ENABLED 0x00000000 /* RW--V */
#define NV_XAL_EP_CG1_SLCG_DOWNARB_DISABLED 0x00000001 /* RWI-V */
#define NV_XAL_EP_CG1_SLCG_DOWNARB__PROD 0x00000000 /* RW--V */
#define NV_XAL_EP_CG1_SLCG_UPARB 3:3 /* RWIVF */
#define NV_XAL_EP_CG1_SLCG_UPARB_ENABLED 0x00000000 /* RW--V */
#define NV_XAL_EP_CG1_SLCG_UPARB_DISABLED 0x00000001 /* RWI-V */
#define NV_XAL_EP_CG1_SLCG_UPARB__PROD 0x00000000 /* RW--V */
#define NV_XAL_EP_CG1_SLCG_PRIREQ 4:4 /* RWIVF */
#define NV_XAL_EP_CG1_SLCG_PRIREQ_ENABLED 0x00000000 /* RW--V */
#define NV_XAL_EP_CG1_SLCG_PRIREQ_DISABLED 0x00000001 /* RWI-V */
#define NV_XAL_EP_CG1_SLCG_PRIREQ__PROD 0x00000000 /* RW--V */
#define NV_XAL_EP_CG1_SLCG_PRIRSP 5:5 /* RWIVF */
#define NV_XAL_EP_CG1_SLCG_PRIRSP_ENABLED 0x00000000 /* RW--V */
#define NV_XAL_EP_CG1_SLCG_PRIRSP_DISABLED 0x00000001 /* RWI-V */
#define NV_XAL_EP_CG1_SLCG_PRIRSP__PROD 0x00000000 /* RW--V */
#define NV_XAL_EP_CG1_SLCG_JOIN 6:6 /* RWIVF */
#define NV_XAL_EP_CG1_SLCG_JOIN_ENABLED 0x00000000 /* RW--V */
#define NV_XAL_EP_CG1_SLCG_JOIN_DISABLED 0x00000001 /* RWI-V */
#define NV_XAL_EP_CG1_SLCG_JOIN__PROD 0x00000000 /* RW--V */
#define NV_XAL_EP_CG1_SLCG_JTAG 7:7 /* RWIVF */
#define NV_XAL_EP_CG1_SLCG_JTAG_ENABLED 0x00000000 /* RW--V */
#define NV_XAL_EP_CG1_SLCG_JTAG_DISABLED 0x00000001 /* RWI-V */
#define NV_XAL_EP_CG1_SLCG_JTAG__PROD 0x00000000 /* RW--V */
#define NV_XAL_EP_CG1_SLCG_PM 9:9 /* RWIVF */
#define NV_XAL_EP_CG1_SLCG_PM_ENABLED 0x00000000 /* RW--V */
#define NV_XAL_EP_CG1_SLCG_PM_DISABLED 0x00000001 /* RWI-V */
#define NV_XAL_EP_CG1_SLCG_PM__PROD 0x00000000 /* RW--V */
#define NV_XAL_EP_CG1_SLCG_UNROLL_MEM 10:10 /* RWIVF */
#define NV_XAL_EP_CG1_SLCG_UNROLL_MEM_ENABLED 0x00000000 /* RW--V */
#define NV_XAL_EP_CG1_SLCG_UNROLL_MEM_DISABLED 0x00000001 /* RWI-V */
#define NV_XAL_EP_CG1_SLCG_UNROLL_MEM__PROD 0x00000000 /* RW--V */
#define NV_XAL_EP_CG1_SLCG_MEMOP 11:11 /* RWIVF */
#define NV_XAL_EP_CG1_SLCG_MEMOP_ENABLED 0x00000000 /* RW--V */
#define NV_XAL_EP_CG1_SLCG_MEMOP_DISABLED 0x00000001 /* RWI-V */
#define NV_XAL_EP_CG1_SLCG_MEMOP__PROD 0x00000000 /* RW--V */
#define NV_XAL_EP_CG1_SLCG_MEMRSP 12:12 /* RWIVF */
#define NV_XAL_EP_CG1_SLCG_MEMRSP_ENABLED 0x00000000 /* RW--V */
#define NV_XAL_EP_CG1_SLCG_MEMRSP_DISABLED 0x00000001 /* RWI-V */
#define NV_XAL_EP_CG1_SLCG_MEMRSP__PROD 0x00000000 /* RW--V */
#define NV_XAL_EP_CG1_SLCG_MSIX 13:13 /* RWIVF */
#define NV_XAL_EP_CG1_SLCG_MSIX_ENABLED 0x00000000 /* RW--V */
#define NV_XAL_EP_CG1_SLCG_MSIX_DISABLED 0x00000001 /* RWI-V */
#define NV_XAL_EP_CG1_SLCG_MSIX__PROD 0x00000000 /* RW--V */
#define NV_XAL_EP_CG1_SLCG_RXMAP 14:14 /* RWIVF */
#define NV_XAL_EP_CG1_SLCG_RXMAP_ENABLED 0x00000000 /* RW--V */
#define NV_XAL_EP_CG1_SLCG_RXMAP_DISABLED 0x00000001 /* RWI-V */
#define NV_XAL_EP_CG1_SLCG_RXMAP__PROD 0x00000000 /* RW--V */
#define NV_XAL_EP_CG1_SLCG_FBI_UP 15:15 /* RWIVF */
#define NV_XAL_EP_CG1_SLCG_FBI_UP_ENABLED 0x00000000 /* RW--V */
#define NV_XAL_EP_CG1_SLCG_FBI_UP_DISABLED 0x00000001 /* RWI-V */
#define NV_XAL_EP_CG1_SLCG_FBI_UP__PROD 0x00000000 /* RW--V */
#define NV_XAL_EP_CG1_SLCG_TXMAP 16:16 /* RWIVF */
#define NV_XAL_EP_CG1_SLCG_TXMAP_ENABLED 0x00000000 /* RW--V */
#define NV_XAL_EP_CG1_SLCG_TXMAP_DISABLED 0x00000001 /* RWI-V */
#define NV_XAL_EP_CG1_SLCG_TXMAP__PROD 0x00000000 /* RW--V */
#define NV_XAL_EP_CG1_SLCG_PRI_TRACKER 21:21 /* RWIVF */
#define NV_XAL_EP_CG1_SLCG_PRI_TRACKER_ENABLED 0x00000000 /* RW--V */
#define NV_XAL_EP_CG1_SLCG_PRI_TRACKER_DISABLED 0x00000001 /* RWI-V */
#define NV_XAL_EP_CG1_SLCG_PRI_TRACKER__PROD 0x00000000 /* RW--V */
#define NV_XAL_EP_CG1_SLCG_FASTFLUSH 23:23 /* RWIVF */
#define NV_XAL_EP_CG1_SLCG_FASTFLUSH_ENABLED 0x00000000 /* RW--V */
#define NV_XAL_EP_CG1_SLCG_FASTFLUSH_DISABLED 0x00000001 /* RWI-V */
#define NV_XAL_EP_CG1_SLCG_FASTFLUSH__PROD 0x00000000 /* RW--V */
#define NV_XAL_EP_CG1_SLCG_DFD 24:24 /* RWIVF */
#define NV_XAL_EP_CG1_SLCG_DFD_ENABLED 0x00000000 /* RW--V */
#define NV_XAL_EP_CG1_SLCG_DFD_DISABLED 0x00000001 /* RWI-V */
#define NV_XAL_EP_CG1_SLCG_DFD__PROD 0x00000000 /* RW--V */
#endif // __ls10_dev_nv_xal_ep_h__

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src/common/inc/swref/published/nvswitch/ls10/dev_nv_xpl.h Normal file
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@@ -0,0 +1,256 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the Software),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __ls10_dev_nv_xpl_h__
#define __ls10_dev_nv_xpl_h__
/* This file is autogenerated. Do not edit */
#define NV_XPL 0x00003fff:0x00000000 /* RW--D */
#define NV_XPL_PL_PAD_CTL_PRI_XPL_XCLK_CG 0x00002700 /* RWE4R */
#define NV_XPL_PL_PAD_CTL_PRI_XPL_XCLK_CG_IDLE_CG_DLY_CNT 5:0 /* RWEVF */
#define NV_XPL_PL_PAD_CTL_PRI_XPL_XCLK_CG_IDLE_CG_DLY_CNT_HWINIT 0x00 /* RWE-V */
#define NV_XPL_PL_PAD_CTL_PRI_XPL_XCLK_CG_IDLE_CG_DLY_CNT__PROD 0x00 /* RW--V */
#define NV_XPL_PL_PAD_CTL_PRI_XPL_XCLK_CG_IDLE_CG_EN 6:6 /* RWEVF */
#define NV_XPL_PL_PAD_CTL_PRI_XPL_XCLK_CG_IDLE_CG_EN_ENABLED 0x1 /* RW--V */
#define NV_XPL_PL_PAD_CTL_PRI_XPL_XCLK_CG_IDLE_CG_EN_DISABLED 0x0 /* RWE-V */
#define NV_XPL_PL_PAD_CTL_PRI_XPL_XCLK_CG_IDLE_CG_EN__PROD 0x1 /* RW--V */
#define NV_XPL_PL_PAD_CTL_PRI_XPL_XCLK_CG_STATE_CG_EN 7:7 /* */
#define NV_XPL_PL_PAD_CTL_PRI_XPL_XCLK_CG_STATE_CG_EN_ENABLED 0x1 /* */
#define NV_XPL_PL_PAD_CTL_PRI_XPL_XCLK_CG_STATE_CG_EN_DISABLED 0x0 /* */
#define NV_XPL_PL_PAD_CTL_PRI_XPL_XCLK_CG_STATE_CG_EN__PROD 0x0 /* */
#define NV_XPL_PL_PAD_CTL_PRI_XPL_XCLK_CG_STALL_CG_DLY_CNT 13:8 /* */
#define NV_XPL_PL_PAD_CTL_PRI_XPL_XCLK_CG_STALL_CG_DLY_CNT_HWINIT 0x00 /* */
#define NV_XPL_PL_PAD_CTL_PRI_XPL_XCLK_CG_STALL_CG_DLY_CNT__PROD 0x00 /* */
#define NV_XPL_PL_PAD_CTL_PRI_XPL_XCLK_CG_STALL_CG_EN 14:14 /* RWEVF */
#define NV_XPL_PL_PAD_CTL_PRI_XPL_XCLK_CG_STALL_CG_EN_ENABLED 0x1 /* RW--V */
#define NV_XPL_PL_PAD_CTL_PRI_XPL_XCLK_CG_STALL_CG_EN_DISABLED 0x0 /* RWE-V */
#define NV_XPL_PL_PAD_CTL_PRI_XPL_XCLK_CG_STALL_CG_EN__PROD 0x0 /* RW--V */
#define NV_XPL_PL_PAD_CTL_PRI_XPL_XCLK_CG_QUIESCENT_CG_EN 15:15 /* */
#define NV_XPL_PL_PAD_CTL_PRI_XPL_XCLK_CG_QUIESCENT_CG_EN_ENABLED 0x1 /* */
#define NV_XPL_PL_PAD_CTL_PRI_XPL_XCLK_CG_QUIESCENT_CG_EN_DISABLED 0x0 /* */
#define NV_XPL_PL_PAD_CTL_PRI_XPL_XCLK_CG_QUIESCENT_CG_EN__PROD 0x0 /* */
#define NV_XPL_PL_PAD_CTL_PRI_XPL_XCLK_CG_WAKEUP_DLY_CNT 19:16 /* RWEVF */
#define NV_XPL_PL_PAD_CTL_PRI_XPL_XCLK_CG_WAKEUP_DLY_CNT_HWINIT 0x0 /* RWE-V */
#define NV_XPL_PL_PAD_CTL_PRI_XPL_XCLK_CG_WAKEUP_DLY_CNT__PROD 0x0 /* RW--V */
#define NV_XPL_PL_PAD_CTL_PRI_XPL_XCLK_CG_THROT_CLK_CNT 23:20 /* */
#define NV_XPL_PL_PAD_CTL_PRI_XPL_XCLK_CG_THROT_CLK_CNT_FULLSPEED 0xf /* */
#define NV_XPL_PL_PAD_CTL_PRI_XPL_XCLK_CG_THROT_CLK_CNT__PROD 0x0 /* */
#define NV_XPL_PL_PAD_CTL_PRI_XPL_XCLK_CG_DI_DT_SKEW_VAL 27:24 /* */
#define NV_XPL_PL_PAD_CTL_PRI_XPL_XCLK_CG_DI_DT_SKEW_VAL_HWINIT 0x0 /* */
#define NV_XPL_PL_PAD_CTL_PRI_XPL_XCLK_CG_DI_DT_SKEW_VAL__PROD 0x0 /* */
#define NV_XPL_PL_PAD_CTL_PRI_XPL_XCLK_CG_THROT_CLK_EN 28:28 /* */
#define NV_XPL_PL_PAD_CTL_PRI_XPL_XCLK_CG_THROT_CLK_EN_ENABLED 0x1 /* */
#define NV_XPL_PL_PAD_CTL_PRI_XPL_XCLK_CG_THROT_CLK_EN_DISABLED 0x0 /* */
#define NV_XPL_PL_PAD_CTL_PRI_XPL_XCLK_CG_THROT_CLK_EN__PROD 0x0 /* */
#define NV_XPL_PL_PAD_CTL_PRI_XPL_XCLK_CG_THROT_CLK_SW_OVER 29:29 /* */
#define NV_XPL_PL_PAD_CTL_PRI_XPL_XCLK_CG_THROT_CLK_SW_OVER_EN 0x1 /* */
#define NV_XPL_PL_PAD_CTL_PRI_XPL_XCLK_CG_THROT_CLK_SW_OVER_DIS 0x0 /* */
#define NV_XPL_PL_PAD_CTL_PRI_XPL_XCLK_CG_THROT_CLK_SW_OVER__PROD 0x0 /* */
#define NV_XPL_PL_PAD_CTL_PRI_XPL_XCLK_CG_PAUSE_CG_EN 30:30 /* */
#define NV_XPL_PL_PAD_CTL_PRI_XPL_XCLK_CG_PAUSE_CG_EN_ENABLED 0x1 /* */
#define NV_XPL_PL_PAD_CTL_PRI_XPL_XCLK_CG_PAUSE_CG_EN_DISABLED 0x0 /* */
#define NV_XPL_PL_PAD_CTL_PRI_XPL_XCLK_CG_PAUSE_CG_EN__PROD 0x0 /* */
#define NV_XPL_PL_PAD_CTL_PRI_XPL_XCLK_CG_HALT_CG_EN 31:31 /* */
#define NV_XPL_PL_PAD_CTL_PRI_XPL_XCLK_CG_HALT_CG_EN_ENABLED 0x1 /* */
#define NV_XPL_PL_PAD_CTL_PRI_XPL_XCLK_CG_HALT_CG_EN_DISABLED 0x0 /* */
#define NV_XPL_PL_PAD_CTL_PRI_XPL_XCLK_CG_HALT_CG_EN__PROD 0x0 /* */
#define NV_XPL_PL_PAD_CTL_PRI_XPL_XCLK_CG1 0x00002704 /* RWE4R */
#define NV_XPL_PL_PAD_CTL_PRI_XPL_XCLK_CG1_MONITOR_CG_EN 0:0 /* RWEVF */
#define NV_XPL_PL_PAD_CTL_PRI_XPL_XCLK_CG1_MONITOR_CG_EN_ENABLED 0x1 /* RW--V */
#define NV_XPL_PL_PAD_CTL_PRI_XPL_XCLK_CG1_MONITOR_CG_EN_DISABLED 0x0 /* RWE-V */
#define NV_XPL_PL_PAD_CTL_PRI_XPL_XCLK_CG1_MONITOR_CG_EN__PROD 0x0 /* RW--V */
#define NV_XPL_PL_PAD_CTL_PRI_XPL_XCLK_CG1_SLCG 18:1 /* RWEVF */
#define NV_XPL_PL_PAD_CTL_PRI_XPL_XCLK_CG1_SLCG_ENABLED 0x00000 /* RW--V */
#define NV_XPL_PL_PAD_CTL_PRI_XPL_XCLK_CG1_SLCG_DISABLED 0x3ffff /* RWE-V */
#define NV_XPL_PL_PAD_CTL_PRI_XPL_XCLK_CG1_SLCG__PROD 0x00000 /* RW--V */
#define NV_XPL_PL_PAD_CTL_PRI_XPL_TXCLK_CG 0x00002710 /* RWE4R */
#define NV_XPL_PL_PAD_CTL_PRI_XPL_TXCLK_CG_IDLE_CG_DLY_CNT 5:0 /* RWEVF */
#define NV_XPL_PL_PAD_CTL_PRI_XPL_TXCLK_CG_IDLE_CG_DLY_CNT_HWINIT 0x00 /* RWE-V */
#define NV_XPL_PL_PAD_CTL_PRI_XPL_TXCLK_CG_IDLE_CG_DLY_CNT__PROD 0x00 /* RW--V */
#define NV_XPL_PL_PAD_CTL_PRI_XPL_TXCLK_CG_IDLE_CG_EN 6:6 /* RWEVF */
#define NV_XPL_PL_PAD_CTL_PRI_XPL_TXCLK_CG_IDLE_CG_EN_ENABLED 0x1 /* RW--V */
#define NV_XPL_PL_PAD_CTL_PRI_XPL_TXCLK_CG_IDLE_CG_EN_DISABLED 0x0 /* RWE-V */
#define NV_XPL_PL_PAD_CTL_PRI_XPL_TXCLK_CG_IDLE_CG_EN__PROD 0x1 /* RW--V */
#define NV_XPL_PL_PAD_CTL_PRI_XPL_TXCLK_CG_STATE_CG_EN 7:7 /* */
#define NV_XPL_PL_PAD_CTL_PRI_XPL_TXCLK_CG_STATE_CG_EN_ENABLED 0x1 /* */
#define NV_XPL_PL_PAD_CTL_PRI_XPL_TXCLK_CG_STATE_CG_EN_DISABLED 0x0 /* */
#define NV_XPL_PL_PAD_CTL_PRI_XPL_TXCLK_CG_STATE_CG_EN__PROD 0x0 /* */
#define NV_XPL_PL_PAD_CTL_PRI_XPL_TXCLK_CG_STALL_CG_DLY_CNT 13:8 /* */
#define NV_XPL_PL_PAD_CTL_PRI_XPL_TXCLK_CG_STALL_CG_DLY_CNT_HWINIT 0x00 /* */
#define NV_XPL_PL_PAD_CTL_PRI_XPL_TXCLK_CG_STALL_CG_DLY_CNT__PROD 0x00 /* */
#define NV_XPL_PL_PAD_CTL_PRI_XPL_TXCLK_CG_STALL_CG_EN 14:14 /* RWEVF */
#define NV_XPL_PL_PAD_CTL_PRI_XPL_TXCLK_CG_STALL_CG_EN_ENABLED 0x1 /* RW--V */
#define NV_XPL_PL_PAD_CTL_PRI_XPL_TXCLK_CG_STALL_CG_EN_DISABLED 0x0 /* RWE-V */
#define NV_XPL_PL_PAD_CTL_PRI_XPL_TXCLK_CG_STALL_CG_EN__PROD 0x0 /* RW--V */
#define NV_XPL_PL_PAD_CTL_PRI_XPL_TXCLK_CG_QUIESCENT_CG_EN 15:15 /* */
#define NV_XPL_PL_PAD_CTL_PRI_XPL_TXCLK_CG_QUIESCENT_CG_EN_ENABLED 0x1 /* */
#define NV_XPL_PL_PAD_CTL_PRI_XPL_TXCLK_CG_QUIESCENT_CG_EN_DISABLED 0x0 /* */
#define NV_XPL_PL_PAD_CTL_PRI_XPL_TXCLK_CG_QUIESCENT_CG_EN__PROD 0x0 /* */
#define NV_XPL_PL_PAD_CTL_PRI_XPL_TXCLK_CG_WAKEUP_DLY_CNT 19:16 /* RWEVF */
#define NV_XPL_PL_PAD_CTL_PRI_XPL_TXCLK_CG_WAKEUP_DLY_CNT_HWINIT 0x0 /* RWE-V */
#define NV_XPL_PL_PAD_CTL_PRI_XPL_TXCLK_CG_WAKEUP_DLY_CNT__PROD 0x0 /* RW--V */
#define NV_XPL_PL_PAD_CTL_PRI_XPL_TXCLK_CG_THROT_CLK_CNT 23:20 /* */
#define NV_XPL_PL_PAD_CTL_PRI_XPL_TXCLK_CG_THROT_CLK_CNT_FULLSPEED 0xf /* */
#define NV_XPL_PL_PAD_CTL_PRI_XPL_TXCLK_CG_THROT_CLK_CNT__PROD 0x0 /* */
#define NV_XPL_PL_PAD_CTL_PRI_XPL_TXCLK_CG_DI_DT_SKEW_VAL 27:24 /* */
#define NV_XPL_PL_PAD_CTL_PRI_XPL_TXCLK_CG_DI_DT_SKEW_VAL_HWINIT 0x0 /* */
#define NV_XPL_PL_PAD_CTL_PRI_XPL_TXCLK_CG_DI_DT_SKEW_VAL__PROD 0x0 /* */
#define NV_XPL_PL_PAD_CTL_PRI_XPL_TXCLK_CG_THROT_CLK_EN 28:28 /* */
#define NV_XPL_PL_PAD_CTL_PRI_XPL_TXCLK_CG_THROT_CLK_EN_ENABLED 0x1 /* */
#define NV_XPL_PL_PAD_CTL_PRI_XPL_TXCLK_CG_THROT_CLK_EN_DISABLED 0x0 /* */
#define NV_XPL_PL_PAD_CTL_PRI_XPL_TXCLK_CG_THROT_CLK_EN__PROD 0x0 /* */
#define NV_XPL_PL_PAD_CTL_PRI_XPL_TXCLK_CG_THROT_CLK_SW_OVER 29:29 /* */
#define NV_XPL_PL_PAD_CTL_PRI_XPL_TXCLK_CG_THROT_CLK_SW_OVER_EN 0x1 /* */
#define NV_XPL_PL_PAD_CTL_PRI_XPL_TXCLK_CG_THROT_CLK_SW_OVER_DIS 0x0 /* */
#define NV_XPL_PL_PAD_CTL_PRI_XPL_TXCLK_CG_THROT_CLK_SW_OVER__PROD 0x0 /* */
#define NV_XPL_PL_PAD_CTL_PRI_XPL_TXCLK_CG_PAUSE_CG_EN 30:30 /* */
#define NV_XPL_PL_PAD_CTL_PRI_XPL_TXCLK_CG_PAUSE_CG_EN_ENABLED 0x1 /* */
#define NV_XPL_PL_PAD_CTL_PRI_XPL_TXCLK_CG_PAUSE_CG_EN_DISABLED 0x0 /* */
#define NV_XPL_PL_PAD_CTL_PRI_XPL_TXCLK_CG_PAUSE_CG_EN__PROD 0x0 /* */
#define NV_XPL_PL_PAD_CTL_PRI_XPL_TXCLK_CG_HALT_CG_EN 31:31 /* */
#define NV_XPL_PL_PAD_CTL_PRI_XPL_TXCLK_CG_HALT_CG_EN_ENABLED 0x1 /* */
#define NV_XPL_PL_PAD_CTL_PRI_XPL_TXCLK_CG_HALT_CG_EN_DISABLED 0x0 /* */
#define NV_XPL_PL_PAD_CTL_PRI_XPL_TXCLK_CG_HALT_CG_EN__PROD 0x0 /* */
#define NV_XPL_PL_PAD_CTL_PRI_XPL_TXCLK_CG1 0x00002714 /* RWE4R */
#define NV_XPL_PL_PAD_CTL_PRI_XPL_TXCLK_CG1_MONITOR_CG_EN 0:0 /* RWEVF */
#define NV_XPL_PL_PAD_CTL_PRI_XPL_TXCLK_CG1_MONITOR_CG_EN_ENABLED 0x1 /* RW--V */
#define NV_XPL_PL_PAD_CTL_PRI_XPL_TXCLK_CG1_MONITOR_CG_EN_DISABLED 0x0 /* RWE-V */
#define NV_XPL_PL_PAD_CTL_PRI_XPL_TXCLK_CG1_MONITOR_CG_EN__PROD 0x0 /* RW--V */
#define NV_XPL_PL_PAD_CTL_PRI_XPL_TXCLK_CG1_SLCG 2:1 /* RWEVF */
#define NV_XPL_PL_PAD_CTL_PRI_XPL_TXCLK_CG1_SLCG_ENABLED 0x0 /* RW--V */
#define NV_XPL_PL_PAD_CTL_PRI_XPL_TXCLK_CG1_SLCG_DISABLED 0x3 /* RWE-V */
#define NV_XPL_PL_PAD_CTL_PRI_XPL_TXCLK_CG1_SLCG__PROD 0x0 /* RW--V */
#define NV_XPL_PL_PAD_CTL_PRI_XPL_RXCLK_CG 0x00002720 /* RWE4R */
#define NV_XPL_PL_PAD_CTL_PRI_XPL_RXCLK_CG_IDLE_CG_DLY_CNT 5:0 /* RWEVF */
#define NV_XPL_PL_PAD_CTL_PRI_XPL_RXCLK_CG_IDLE_CG_DLY_CNT_HWINIT 0x00 /* RWE-V */
#define NV_XPL_PL_PAD_CTL_PRI_XPL_RXCLK_CG_IDLE_CG_DLY_CNT__PROD 0x00 /* RW--V */
#define NV_XPL_PL_PAD_CTL_PRI_XPL_RXCLK_CG_IDLE_CG_EN 6:6 /* RWEVF */
#define NV_XPL_PL_PAD_CTL_PRI_XPL_RXCLK_CG_IDLE_CG_EN_ENABLED 0x1 /* RW--V */
#define NV_XPL_PL_PAD_CTL_PRI_XPL_RXCLK_CG_IDLE_CG_EN_DISABLED 0x0 /* RWE-V */
#define NV_XPL_PL_PAD_CTL_PRI_XPL_RXCLK_CG_IDLE_CG_EN__PROD 0x1 /* RW--V */
#define NV_XPL_PL_PAD_CTL_PRI_XPL_RXCLK_CG_STATE_CG_EN 7:7 /* */
#define NV_XPL_PL_PAD_CTL_PRI_XPL_RXCLK_CG_STATE_CG_EN_ENABLED 0x1 /* */
#define NV_XPL_PL_PAD_CTL_PRI_XPL_RXCLK_CG_STATE_CG_EN_DISABLED 0x0 /* */
#define NV_XPL_PL_PAD_CTL_PRI_XPL_RXCLK_CG_STATE_CG_EN__PROD 0x0 /* */
#define NV_XPL_PL_PAD_CTL_PRI_XPL_RXCLK_CG_STALL_CG_DLY_CNT 13:8 /* */
#define NV_XPL_PL_PAD_CTL_PRI_XPL_RXCLK_CG_STALL_CG_DLY_CNT_HWINIT 0x00 /* */
#define NV_XPL_PL_PAD_CTL_PRI_XPL_RXCLK_CG_STALL_CG_DLY_CNT__PROD 0x00 /* */
#define NV_XPL_PL_PAD_CTL_PRI_XPL_RXCLK_CG_STALL_CG_EN 14:14 /* RWEVF */
#define NV_XPL_PL_PAD_CTL_PRI_XPL_RXCLK_CG_STALL_CG_EN_ENABLED 0x1 /* RW--V */
#define NV_XPL_PL_PAD_CTL_PRI_XPL_RXCLK_CG_STALL_CG_EN_DISABLED 0x0 /* RWE-V */
#define NV_XPL_PL_PAD_CTL_PRI_XPL_RXCLK_CG_STALL_CG_EN__PROD 0x0 /* RW--V */
#define NV_XPL_PL_PAD_CTL_PRI_XPL_RXCLK_CG_QUIESCENT_CG_EN 15:15 /* */
#define NV_XPL_PL_PAD_CTL_PRI_XPL_RXCLK_CG_QUIESCENT_CG_EN_ENABLED 0x1 /* */
#define NV_XPL_PL_PAD_CTL_PRI_XPL_RXCLK_CG_QUIESCENT_CG_EN_DISABLED 0x0 /* */
#define NV_XPL_PL_PAD_CTL_PRI_XPL_RXCLK_CG_QUIESCENT_CG_EN__PROD 0x0 /* */
#define NV_XPL_PL_PAD_CTL_PRI_XPL_RXCLK_CG_WAKEUP_DLY_CNT 19:16 /* RWEVF */
#define NV_XPL_PL_PAD_CTL_PRI_XPL_RXCLK_CG_WAKEUP_DLY_CNT_HWINIT 0x0 /* RWE-V */
#define NV_XPL_PL_PAD_CTL_PRI_XPL_RXCLK_CG_WAKEUP_DLY_CNT__PROD 0x0 /* RW--V */
#define NV_XPL_PL_PAD_CTL_PRI_XPL_RXCLK_CG_THROT_CLK_CNT 23:20 /* */
#define NV_XPL_PL_PAD_CTL_PRI_XPL_RXCLK_CG_THROT_CLK_CNT_FULLSPEED 0xf /* */
#define NV_XPL_PL_PAD_CTL_PRI_XPL_RXCLK_CG_THROT_CLK_CNT__PROD 0x0 /* */
#define NV_XPL_PL_PAD_CTL_PRI_XPL_RXCLK_CG_DI_DT_SKEW_VAL 27:24 /* */
#define NV_XPL_PL_PAD_CTL_PRI_XPL_RXCLK_CG_DI_DT_SKEW_VAL_HWINIT 0x0 /* */
#define NV_XPL_PL_PAD_CTL_PRI_XPL_RXCLK_CG_DI_DT_SKEW_VAL__PROD 0x0 /* */
#define NV_XPL_PL_PAD_CTL_PRI_XPL_RXCLK_CG_THROT_CLK_EN 28:28 /* */
#define NV_XPL_PL_PAD_CTL_PRI_XPL_RXCLK_CG_THROT_CLK_EN_ENABLED 0x1 /* */
#define NV_XPL_PL_PAD_CTL_PRI_XPL_RXCLK_CG_THROT_CLK_EN_DISABLED 0x0 /* */
#define NV_XPL_PL_PAD_CTL_PRI_XPL_RXCLK_CG_THROT_CLK_EN__PROD 0x0 /* */
#define NV_XPL_PL_PAD_CTL_PRI_XPL_RXCLK_CG_THROT_CLK_SW_OVER 29:29 /* */
#define NV_XPL_PL_PAD_CTL_PRI_XPL_RXCLK_CG_THROT_CLK_SW_OVER_EN 0x1 /* */
#define NV_XPL_PL_PAD_CTL_PRI_XPL_RXCLK_CG_THROT_CLK_SW_OVER_DIS 0x0 /* */
#define NV_XPL_PL_PAD_CTL_PRI_XPL_RXCLK_CG_THROT_CLK_SW_OVER__PROD 0x0 /* */
#define NV_XPL_PL_PAD_CTL_PRI_XPL_RXCLK_CG_PAUSE_CG_EN 30:30 /* */
#define NV_XPL_PL_PAD_CTL_PRI_XPL_RXCLK_CG_PAUSE_CG_EN_ENABLED 0x1 /* */
#define NV_XPL_PL_PAD_CTL_PRI_XPL_RXCLK_CG_PAUSE_CG_EN_DISABLED 0x0 /* */
#define NV_XPL_PL_PAD_CTL_PRI_XPL_RXCLK_CG_PAUSE_CG_EN__PROD 0x0 /* */
#define NV_XPL_PL_PAD_CTL_PRI_XPL_RXCLK_CG_HALT_CG_EN 31:31 /* */
#define NV_XPL_PL_PAD_CTL_PRI_XPL_RXCLK_CG_HALT_CG_EN_ENABLED 0x1 /* */
#define NV_XPL_PL_PAD_CTL_PRI_XPL_RXCLK_CG_HALT_CG_EN_DISABLED 0x0 /* */
#define NV_XPL_PL_PAD_CTL_PRI_XPL_RXCLK_CG_HALT_CG_EN__PROD 0x0 /* */
#define NV_XPL_PL_PAD_CTL_PRI_XPL_RXCLK_CG1 0x00002724 /* RWE4R */
#define NV_XPL_PL_PAD_CTL_PRI_XPL_RXCLK_CG1_MONITOR_CG_EN 0:0 /* RWEVF */
#define NV_XPL_PL_PAD_CTL_PRI_XPL_RXCLK_CG1_MONITOR_CG_EN_ENABLED 0x1 /* RW--V */
#define NV_XPL_PL_PAD_CTL_PRI_XPL_RXCLK_CG1_MONITOR_CG_EN_DISABLED 0x0 /* RWE-V */
#define NV_XPL_PL_PAD_CTL_PRI_XPL_RXCLK_CG1_MONITOR_CG_EN__PROD 0x0 /* RW--V */
#define NV_XPL_PL_PAD_CTL_PRI_XPL_RXCLK_CG1_SLCG 3:1 /* RWEVF */
#define NV_XPL_PL_PAD_CTL_PRI_XPL_RXCLK_CG1_SLCG_ENABLED 0x0 /* RW--V */
#define NV_XPL_PL_PAD_CTL_PRI_XPL_RXCLK_CG1_SLCG_DISABLED 0x7 /* RWE-V */
#define NV_XPL_PL_PAD_CTL_PRI_XPL_RXCLK_CG1_SLCG__PROD 0x0 /* RW--V */
#define NV_XPL_XTLQ_PRI_XTL_Q_CG 0x00003a00 /* RWE4R */
#define NV_XPL_XTLQ_PRI_XTL_Q_CG_IDLE_CG_DLY_CNT 5:0 /* RWEVF */
#define NV_XPL_XTLQ_PRI_XTL_Q_CG_IDLE_CG_DLY_CNT_HWINIT 0x0b /* RWE-V */
#define NV_XPL_XTLQ_PRI_XTL_Q_CG_IDLE_CG_DLY_CNT__PROD 0x0b /* RW--V */
#define NV_XPL_XTLQ_PRI_XTL_Q_CG_IDLE_CG_EN 6:6 /* RWEVF */
#define NV_XPL_XTLQ_PRI_XTL_Q_CG_IDLE_CG_EN_ENABLED 0x1 /* RW--V */
#define NV_XPL_XTLQ_PRI_XTL_Q_CG_IDLE_CG_EN_DISABLED 0x0 /* RWE-V */
#define NV_XPL_XTLQ_PRI_XTL_Q_CG_IDLE_CG_EN__PROD 0x0 /* RW--V */
#define NV_XPL_XTLQ_PRI_XTL_Q_CG_STATE_CG_EN 7:7 /* */
#define NV_XPL_XTLQ_PRI_XTL_Q_CG_STATE_CG_EN_ENABLED 0x1 /* */
#define NV_XPL_XTLQ_PRI_XTL_Q_CG_STATE_CG_EN_DISABLED 0x0 /* */
#define NV_XPL_XTLQ_PRI_XTL_Q_CG_STATE_CG_EN__PROD 0x0 /* */
#define NV_XPL_XTLQ_PRI_XTL_Q_CG_STALL_CG_DLY_CNT 13:8 /* */
#define NV_XPL_XTLQ_PRI_XTL_Q_CG_STALL_CG_DLY_CNT_HWINIT 0x00 /* */
#define NV_XPL_XTLQ_PRI_XTL_Q_CG_STALL_CG_DLY_CNT__PROD 0x00 /* */
#define NV_XPL_XTLQ_PRI_XTL_Q_CG_STALL_CG_EN 14:14 /* RWEVF */
#define NV_XPL_XTLQ_PRI_XTL_Q_CG_STALL_CG_EN_ENABLED 0x1 /* RW--V */
#define NV_XPL_XTLQ_PRI_XTL_Q_CG_STALL_CG_EN_DISABLED 0x0 /* RWE-V */
#define NV_XPL_XTLQ_PRI_XTL_Q_CG_STALL_CG_EN__PROD 0x0 /* RW--V */
#define NV_XPL_XTLQ_PRI_XTL_Q_CG_QUIESCENT_CG_EN 15:15 /* */
#define NV_XPL_XTLQ_PRI_XTL_Q_CG_QUIESCENT_CG_EN_ENABLED 0x1 /* */
#define NV_XPL_XTLQ_PRI_XTL_Q_CG_QUIESCENT_CG_EN_DISABLED 0x0 /* */
#define NV_XPL_XTLQ_PRI_XTL_Q_CG_QUIESCENT_CG_EN__PROD 0x0 /* */
#define NV_XPL_XTLQ_PRI_XTL_Q_CG_WAKEUP_DLY_CNT 19:16 /* RWEVF */
#define NV_XPL_XTLQ_PRI_XTL_Q_CG_WAKEUP_DLY_CNT_HWINIT 0xb /* RWE-V */
#define NV_XPL_XTLQ_PRI_XTL_Q_CG_WAKEUP_DLY_CNT__PROD 0xb /* RW--V */
#define NV_XPL_XTLQ_PRI_XTL_Q_CG_THROT_CLK_CNT 23:20 /* */
#define NV_XPL_XTLQ_PRI_XTL_Q_CG_THROT_CLK_CNT_FULLSPEED 0xf /* */
#define NV_XPL_XTLQ_PRI_XTL_Q_CG_THROT_CLK_CNT__PROD 0x0 /* */
#define NV_XPL_XTLQ_PRI_XTL_Q_CG_DI_DT_SKEW_VAL 27:24 /* */
#define NV_XPL_XTLQ_PRI_XTL_Q_CG_DI_DT_SKEW_VAL_HWINIT 0x0 /* */
#define NV_XPL_XTLQ_PRI_XTL_Q_CG_DI_DT_SKEW_VAL__PROD 0x0 /* */
#define NV_XPL_XTLQ_PRI_XTL_Q_CG_THROT_CLK_EN 28:28 /* */
#define NV_XPL_XTLQ_PRI_XTL_Q_CG_THROT_CLK_EN_ENABLED 0x1 /* */
#define NV_XPL_XTLQ_PRI_XTL_Q_CG_THROT_CLK_EN_DISABLED 0x0 /* */
#define NV_XPL_XTLQ_PRI_XTL_Q_CG_THROT_CLK_EN__PROD 0x0 /* */
#define NV_XPL_XTLQ_PRI_XTL_Q_CG_THROT_CLK_SW_OVER 29:29 /* */
#define NV_XPL_XTLQ_PRI_XTL_Q_CG_THROT_CLK_SW_OVER_EN 0x1 /* */
#define NV_XPL_XTLQ_PRI_XTL_Q_CG_THROT_CLK_SW_OVER_DIS 0x0 /* */
#define NV_XPL_XTLQ_PRI_XTL_Q_CG_THROT_CLK_SW_OVER__PROD 0x0 /* */
#define NV_XPL_XTLQ_PRI_XTL_Q_CG_PAUSE_CG_EN 30:30 /* */
#define NV_XPL_XTLQ_PRI_XTL_Q_CG_PAUSE_CG_EN_ENABLED 0x1 /* */
#define NV_XPL_XTLQ_PRI_XTL_Q_CG_PAUSE_CG_EN_DISABLED 0x0 /* */
#define NV_XPL_XTLQ_PRI_XTL_Q_CG_PAUSE_CG_EN__PROD 0x0 /* */
#define NV_XPL_XTLQ_PRI_XTL_Q_CG_HALT_CG_EN 31:31 /* */
#define NV_XPL_XTLQ_PRI_XTL_Q_CG_HALT_CG_EN_ENABLED 0x1 /* */
#define NV_XPL_XTLQ_PRI_XTL_Q_CG_HALT_CG_EN_DISABLED 0x0 /* */
#define NV_XPL_XTLQ_PRI_XTL_Q_CG_HALT_CG_EN__PROD 0x0 /* */
#define NV_XPL_XTLQ_PRI_XTL_Q_CG1 0x00003a04 /* RWE4R */
#define NV_XPL_XTLQ_PRI_XTL_Q_CG1_MONITOR_CG_EN 0:0 /* RWEVF */
#define NV_XPL_XTLQ_PRI_XTL_Q_CG1_MONITOR_CG_EN_ENABLED 0x1 /* RW--V */
#define NV_XPL_XTLQ_PRI_XTL_Q_CG1_MONITOR_CG_EN_DISABLED 0x0 /* RWE-V */
#define NV_XPL_XTLQ_PRI_XTL_Q_CG1_MONITOR_CG_EN__PROD 0x0 /* RW--V */
#define NV_XPL_XTLQ_PRI_XTL_Q_CG1_SLCG 9:1 /* RWEVF */
#define NV_XPL_XTLQ_PRI_XTL_Q_CG1_SLCG_ENABLED 0x000 /* RW--V */
#define NV_XPL_XTLQ_PRI_XTL_Q_CG1_SLCG_DISABLED 0x1ff /* RWE-V */
#define NV_XPL_XTLQ_PRI_XTL_Q_CG1_SLCG__PROD 0x000 /* RW--V */
#endif // __ls10_dev_nv_xpl_h__

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src/common/inc/swref/published/nvswitch/ls10/dev_nvldl_ip.h Normal file
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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the Software),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __ls10_dev_nvldl_ip_h__
#define __ls10_dev_nvldl_ip_h__
/* This file is autogenerated. Do not edit */
#define NV_NVLDL_TOP 0x00001FFF:0x00000000 /* RW--D */
#define NV_NVLDL_TX 0x000027FF:0x00002000 /* RW--D */
#define NV_NVLDL_RX 0x000037FF:0x00003000 /* RW--D */
#define NV_NVLDL_TOP_LINK_STATE 0x00000000 /* R--4R */
#define NV_NVLDL_TOP_LINK_STATE_STATE 7:0 /* R-XVF */
#define NV_NVLDL_TOP_LINK_STATE_STATE_INIT 0x00000000 /* R---V */
#define NV_NVLDL_TOP_LINK_STATE_STATE_HWPCFG 0x0000000c /* R---V */
#define NV_NVLDL_TOP_LINK_STATE_STATE_HWCFG 0x00000001 /* R---V */
#define NV_NVLDL_TOP_LINK_STATE_STATE_SWCFG 0x00000002 /* R---V */
#define NV_NVLDL_TOP_LINK_STATE_STATE_ACTIVE 0x00000003 /* R---V */
#define NV_NVLDL_TOP_LINK_STATE_STATE_FAULT 0x00000004 /* R---V */
#define NV_NVLDL_TOP_LINK_STATE_STATE_SLEEP 0x00000005 /* R---V */
#define NV_NVLDL_TOP_LINK_STATE_STATE_RCVY_AC 0x00000008 /* R---V */
#define NV_NVLDL_TOP_LINK_STATE_STATE_RCVY_RX 0x0000000a /* R---V */
#define NV_NVLDL_TOP_LINK_STATE_STATE_TRAIN 0x0000000b /* R---V */
#define NV_NVLDL_TOP_LINK_STATE_STATE_TEST 0x0000000d /* R---V */
#define NV_NVLDL_TOP_LINK_STATE_AN0_BUSY 12:12 /* R-XVF */
#define NV_NVLDL_TOP_LINK_STATE_TL_BUSY 13:13 /* R-XVF */
#define NV_NVLDL_TOP_LINK_STATE_DBG_SUBSTATE 31:16 /* R-XVF */
#define NV_NVLDL_TOP_INTR 0x00000050 /* RW-4R */
#define NV_NVLDL_TOP_INTR_TX_REPLAY 0:0 /* RWEVF */
#define NV_NVLDL_TOP_INTR_TX_REPLAY__ONWRITE "oneToClear" /* */
#define NV_NVLDL_TOP_INTR_TX_REPLAY_INIT 0x00000000 /* RWE-V */
#define NV_NVLDL_TOP_INTR_TX_RECOVERY_SHORT 1:1 /* RWEVF */
#define NV_NVLDL_TOP_INTR_TX_RECOVERY_SHORT__ONWRITE "oneToClear" /* */
#define NV_NVLDL_TOP_INTR_TX_RECOVERY_SHORT_INIT 0x00000000 /* RWE-V */
#define NV_NVLDL_TOP_INTR_TX_FAULT_RAM 4:4 /* RWEVF */
#define NV_NVLDL_TOP_INTR_TX_FAULT_RAM__ONWRITE "oneToClear" /* */
#define NV_NVLDL_TOP_INTR_TX_FAULT_RAM_INIT 0x00000000 /* RWE-V */
#define NV_NVLDL_TOP_INTR_TX_FAULT_INTERFACE 5:5 /* RWEVF */
#define NV_NVLDL_TOP_INTR_TX_FAULT_INTERFACE__ONWRITE "oneToClear" /* */
#define NV_NVLDL_TOP_INTR_TX_FAULT_INTERFACE_INIT 0x00000000 /* RWE-V */
#define NV_NVLDL_TOP_INTR_TX_FAULT_SUBLINK_CHANGE 8:8 /* RWEVF */
#define NV_NVLDL_TOP_INTR_TX_FAULT_SUBLINK_CHANGE__ONWRITE "oneToClear" /* */
#define NV_NVLDL_TOP_INTR_TX_FAULT_SUBLINK_CHANGE_INIT 0x00000000 /* RWE-V */
#define NV_NVLDL_TOP_INTR_TX_PL_ERROR 9:9 /* RWEVF */
#define NV_NVLDL_TOP_INTR_TX_PL_ERROR__ONWRITE "oneToClear" /* */
#define NV_NVLDL_TOP_INTR_TX_PL_ERROR_INIT 0x00000000 /* RWE-V */
#define NV_NVLDL_TOP_INTR_PHY_A 12:12 /* RWEVF */
#define NV_NVLDL_TOP_INTR_PHY_A__ONWRITE "oneToClear" /* */
#define NV_NVLDL_TOP_INTR_PHY_A_INIT 0x00000000 /* RWE-V */
#define NV_NVLDL_TOP_INTR_PHY_B 13:13 /* RWEVF */
#define NV_NVLDL_TOP_INTR_PHY_B__ONWRITE "oneToClear" /* */
#define NV_NVLDL_TOP_INTR_PHY_B_INIT 0x00000000 /* RWE-V */
#define NV_NVLDL_TOP_INTR_RX_FAULT_SUBLINK_CHANGE 16:16 /* RWEVF */
#define NV_NVLDL_TOP_INTR_RX_FAULT_SUBLINK_CHANGE__ONWRITE "oneToClear" /* */
#define NV_NVLDL_TOP_INTR_RX_FAULT_SUBLINK_CHANGE_INIT 0x00000000 /* RWE-V */
#define NV_NVLDL_TOP_INTR_RX_PL_ERROR 17:17 /* RWEVF */
#define NV_NVLDL_TOP_INTR_RX_PL_ERROR__ONWRITE "oneToClear" /* */
#define NV_NVLDL_TOP_INTR_RX_PL_ERROR_INIT 0x00000000 /* RWE-V */
#define NV_NVLDL_TOP_INTR_RX_FAULT_DL_PROTOCOL 20:20 /* RWEVF */
#define NV_NVLDL_TOP_INTR_RX_FAULT_DL_PROTOCOL__ONWRITE "oneToClear" /* */
#define NV_NVLDL_TOP_INTR_RX_FAULT_DL_PROTOCOL_INIT 0x00000000 /* RWE-V */
#define NV_NVLDL_TOP_INTR_RX_SHORT_ERROR_RATE 21:21 /* RWEVF */
#define NV_NVLDL_TOP_INTR_RX_SHORT_ERROR_RATE__ONWRITE "oneToClear" /* */
#define NV_NVLDL_TOP_INTR_RX_SHORT_ERROR_RATE_INIT 0x00000000 /* RWE-V */
#define NV_NVLDL_TOP_INTR_RX_LONG_ERROR_RATE 22:22 /* RWEVF */
#define NV_NVLDL_TOP_INTR_RX_LONG_ERROR_RATE__ONWRITE "oneToClear" /* */
#define NV_NVLDL_TOP_INTR_RX_LONG_ERROR_RATE_INIT 0x00000000 /* RWE-V */
#define NV_NVLDL_TOP_INTR_RX_ILA_TRIGGER 23:23 /* RWEVF */
#define NV_NVLDL_TOP_INTR_RX_ILA_TRIGGER__ONWRITE "oneToClear" /* */
#define NV_NVLDL_TOP_INTR_RX_ILA_TRIGGER_INIT 0x00000000 /* RWE-V */
#define NV_NVLDL_TOP_INTR_RX_CRC_COUNTER 24:24 /* RWEVF */
#define NV_NVLDL_TOP_INTR_RX_CRC_COUNTER__ONWRITE "oneToClear" /* */
#define NV_NVLDL_TOP_INTR_RX_CRC_COUNTER_INIT 0x00000000 /* RWE-V */
#define NV_NVLDL_TOP_INTR_LTSSM_FAULT_DOWN 27:27 /* RWEVF */
#define NV_NVLDL_TOP_INTR_LTSSM_FAULT_DOWN__ONWRITE "oneToClear" /* */
#define NV_NVLDL_TOP_INTR_LTSSM_FAULT_DOWN_INIT 0x00000000 /* RWE-V */
#define NV_NVLDL_TOP_INTR_LTSSM_FAULT_UP 28:28 /* RWEVF */
#define NV_NVLDL_TOP_INTR_LTSSM_FAULT_UP__ONWRITE "oneToClear" /* */
#define NV_NVLDL_TOP_INTR_LTSSM_FAULT_UP_INIT 0x00000000 /* RWE-V */
#define NV_NVLDL_TOP_INTR_LTSSM_PROTOCOL 29:29 /* RWEVF */
#define NV_NVLDL_TOP_INTR_LTSSM_PROTOCOL__ONWRITE "oneToClear" /* */
#define NV_NVLDL_TOP_INTR_LTSSM_PROTOCOL_INIT 0x00000000 /* RWE-V */
#define NV_NVLDL_TOP_INTR_MINION_REQUEST 30:30 /* RWEVF */
#define NV_NVLDL_TOP_INTR_MINION_REQUEST__ONWRITE "oneToClear" /* */
#define NV_NVLDL_TOP_INTR_MINION_REQUEST_INIT 0x00000000 /* RWE-V */
#define NV_NVLDL_TOP_INTR_SW2 0x00000054 /* RW-4R */
#define NV_NVLDL_TOP_INTR_SW2_TX_REPLAY 0:0 /* RWEVF */
#define NV_NVLDL_TOP_INTR_SW2_TX_REPLAY__ONWRITE "oneToClear" /* */
#define NV_NVLDL_TOP_INTR_SW2_TX_REPLAY_INIT 0x00000000 /* RWE-V */
#define NV_NVLDL_TOP_INTR_SW2_TX_RECOVERY_SHORT 1:1 /* RWEVF */
#define NV_NVLDL_TOP_INTR_SW2_TX_RECOVERY_SHORT__ONWRITE "oneToClear" /* */
#define NV_NVLDL_TOP_INTR_SW2_TX_RECOVERY_SHORT_INIT 0x00000000 /* RWE-V */
#define NV_NVLDL_TOP_INTR_SW2_TX_FAULT_RAM 4:4 /* RWEVF */
#define NV_NVLDL_TOP_INTR_SW2_TX_FAULT_RAM__ONWRITE "oneToClear" /* */
#define NV_NVLDL_TOP_INTR_SW2_TX_FAULT_RAM_INIT 0x00000000 /* RWE-V */
#define NV_NVLDL_TOP_INTR_SW2_TX_FAULT_INTERFACE 5:5 /* RWEVF */
#define NV_NVLDL_TOP_INTR_SW2_TX_FAULT_INTERFACE__ONWRITE "oneToClear" /* */
#define NV_NVLDL_TOP_INTR_SW2_TX_FAULT_INTERFACE_INIT 0x00000000 /* RWE-V */
#define NV_NVLDL_TOP_INTR_SW2_TX_FAULT_SUBLINK_CHANGE 8:8 /* RWEVF */
#define NV_NVLDL_TOP_INTR_SW2_TX_FAULT_SUBLINK_CHANGE__ONWRITE "oneToClear" /* */
#define NV_NVLDL_TOP_INTR_SW2_TX_FAULT_SUBLINK_CHANGE_INIT 0x00000000 /* RWE-V */
#define NV_NVLDL_TOP_INTR_SW2_TX_PL_ERROR 9:9 /* RWEVF */
#define NV_NVLDL_TOP_INTR_SW2_TX_PL_ERROR__ONWRITE "oneToClear" /* */
#define NV_NVLDL_TOP_INTR_SW2_TX_PL_ERROR_INIT 0x00000000 /* RWE-V */
#define NV_NVLDL_TOP_INTR_SW2_PHY_A 12:12 /* RWEVF */
#define NV_NVLDL_TOP_INTR_SW2_PHY_A__ONWRITE "oneToClear" /* */
#define NV_NVLDL_TOP_INTR_SW2_PHY_A_INIT 0x00000000 /* RWE-V */
#define NV_NVLDL_TOP_INTR_SW2_PHY_B 13:13 /* RWEVF */
#define NV_NVLDL_TOP_INTR_SW2_PHY_B__ONWRITE "oneToClear" /* */
#define NV_NVLDL_TOP_INTR_SW2_PHY_B_INIT 0x00000000 /* RWE-V */
#define NV_NVLDL_TOP_INTR_SW2_RX_FAULT_SUBLINK_CHANGE 16:16 /* RWEVF */
#define NV_NVLDL_TOP_INTR_SW2_RX_FAULT_SUBLINK_CHANGE__ONWRITE "oneToClear" /* */
#define NV_NVLDL_TOP_INTR_SW2_RX_FAULT_SUBLINK_CHANGE_INIT 0x00000000 /* RWE-V */
#define NV_NVLDL_TOP_INTR_SW2_RX_PL_ERROR 17:17 /* RWEVF */
#define NV_NVLDL_TOP_INTR_SW2_RX_PL_ERROR__ONWRITE "oneToClear" /* */
#define NV_NVLDL_TOP_INTR_SW2_RX_PL_ERROR_INIT 0x00000000 /* RWE-V */
#define NV_NVLDL_TOP_INTR_SW2_RX_FAULT_DL_PROTOCOL 20:20 /* RWEVF */
#define NV_NVLDL_TOP_INTR_SW2_RX_FAULT_DL_PROTOCOL__ONWRITE "oneToClear" /* */
#define NV_NVLDL_TOP_INTR_SW2_RX_FAULT_DL_PROTOCOL_INIT 0x00000000 /* RWE-V */
#define NV_NVLDL_TOP_INTR_SW2_RX_SHORT_ERROR_RATE 21:21 /* RWEVF */
#define NV_NVLDL_TOP_INTR_SW2_RX_SHORT_ERROR_RATE__ONWRITE "oneToClear" /* */
#define NV_NVLDL_TOP_INTR_SW2_RX_SHORT_ERROR_RATE_INIT 0x00000000 /* RWE-V */
#define NV_NVLDL_TOP_INTR_SW2_RX_LONG_ERROR_RATE 22:22 /* RWEVF */
#define NV_NVLDL_TOP_INTR_SW2_RX_LONG_ERROR_RATE__ONWRITE "oneToClear" /* */
#define NV_NVLDL_TOP_INTR_SW2_RX_LONG_ERROR_RATE_INIT 0x00000000 /* RWE-V */
#define NV_NVLDL_TOP_INTR_SW2_RX_ILA_TRIGGER 23:23 /* RWEVF */
#define NV_NVLDL_TOP_INTR_SW2_RX_ILA_TRIGGER__ONWRITE "oneToClear" /* */
#define NV_NVLDL_TOP_INTR_SW2_RX_ILA_TRIGGER_INIT 0x00000000 /* RWE-V */
#define NV_NVLDL_TOP_INTR_SW2_RX_CRC_COUNTER 24:24 /* RWEVF */
#define NV_NVLDL_TOP_INTR_SW2_RX_CRC_COUNTER__ONWRITE "oneToClear" /* */
#define NV_NVLDL_TOP_INTR_SW2_RX_CRC_COUNTER_INIT 0x00000000 /* RWE-V */
#define NV_NVLDL_TOP_INTR_SW2_LTSSM_FAULT_DOWN 27:27 /* RWEVF */
#define NV_NVLDL_TOP_INTR_SW2_LTSSM_FAULT_DOWN__ONWRITE "oneToClear" /* */
#define NV_NVLDL_TOP_INTR_SW2_LTSSM_FAULT_DOWN_INIT 0x00000000 /* RWE-V */
#define NV_NVLDL_TOP_INTR_SW2_LTSSM_FAULT_UP 28:28 /* RWEVF */
#define NV_NVLDL_TOP_INTR_SW2_LTSSM_FAULT_UP__ONWRITE "oneToClear" /* */
#define NV_NVLDL_TOP_INTR_SW2_LTSSM_FAULT_UP_INIT 0x00000000 /* RWE-V */
#define NV_NVLDL_TOP_INTR_SW2_LTSSM_PROTOCOL 29:29 /* RWEVF */
#define NV_NVLDL_TOP_INTR_SW2_LTSSM_PROTOCOL__ONWRITE "oneToClear" /* */
#define NV_NVLDL_TOP_INTR_SW2_LTSSM_PROTOCOL_INIT 0x00000000 /* RWE-V */
#define NV_NVLDL_TOP_INTR_SW2_MINION_REQUEST 30:30 /* RWEVF */
#define NV_NVLDL_TOP_INTR_SW2_MINION_REQUEST__ONWRITE "oneToClear" /* */
#define NV_NVLDL_TOP_INTR_SW2_MINION_REQUEST_INIT 0x00000000 /* RWE-V */
#define NV_NVLDL_TOP_INTR_STALL_EN 0x00000058 /* RW-4R */
#define NV_NVLDL_TOP_INTR_STALL_EN_TX_REPLAY 0:0 /* RWEVF */
#define NV_NVLDL_TOP_INTR_STALL_EN_TX_REPLAY_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLDL_TOP_INTR_STALL_EN_TX_RECOVERY_SHORT 1:1 /* RWEVF */
#define NV_NVLDL_TOP_INTR_STALL_EN_TX_RECOVERY_SHORT_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLDL_TOP_INTR_STALL_EN_TX_RECOVERY_SHORT_ENABLE 0x00000001 /* RW--V */
#define NV_NVLDL_TOP_INTR_STALL_EN_TX_FAULT_RAM 4:4 /* RWEVF */
#define NV_NVLDL_TOP_INTR_STALL_EN_TX_FAULT_RAM_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLDL_TOP_INTR_STALL_EN_TX_FAULT_RAM_ENABLE 0x00000001 /* RW--V */
#define NV_NVLDL_TOP_INTR_STALL_EN_TX_FAULT_INTERFACE 5:5 /* RWEVF */
#define NV_NVLDL_TOP_INTR_STALL_EN_TX_FAULT_INTERFACE_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLDL_TOP_INTR_STALL_EN_TX_FAULT_INTERFACE_ENABLE 0x00000001 /* RW--V */
#define NV_NVLDL_TOP_INTR_STALL_EN_TX_FAULT_SUBLINK_CHANGE 8:8 /* RWEVF */
#define NV_NVLDL_TOP_INTR_STALL_EN_TX_FAULT_SUBLINK_CHANGE_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLDL_TOP_INTR_STALL_EN_TX_FAULT_SUBLINK_CHANGE_ENABLE 0x00000001 /* RW--V */
#define NV_NVLDL_TOP_INTR_STALL_EN_TX_PL_ERROR 9:9 /* RWEVF */
#define NV_NVLDL_TOP_INTR_STALL_EN_TX_PL_ERROR_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLDL_TOP_INTR_STALL_EN_TX_PL_ERROR_ENABLE 0x00000001 /* RW--V */
#define NV_NVLDL_TOP_INTR_STALL_EN_PHY_A 12:12 /* RWEVF */
#define NV_NVLDL_TOP_INTR_STALL_EN_PHY_A_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLDL_TOP_INTR_STALL_EN_PHY_A_ENABLE 0x00000001 /* RW--V */
#define NV_NVLDL_TOP_INTR_STALL_EN_PHY_B 13:13 /* RWEVF */
#define NV_NVLDL_TOP_INTR_STALL_EN_PHY_B_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLDL_TOP_INTR_STALL_EN_PHY_B_ENABLE 0x00000001 /* RW--V */
#define NV_NVLDL_TOP_INTR_STALL_EN_RX_FAULT_SUBLINK_CHANGE 16:16 /* RWEVF */
#define NV_NVLDL_TOP_INTR_STALL_EN_RX_FAULT_SUBLINK_CHANGE_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLDL_TOP_INTR_STALL_EN_RX_FAULT_SUBLINK_CHANGE_ENABLE 0x00000001 /* RW--V */
#define NV_NVLDL_TOP_INTR_STALL_EN_RX_PL_ERROR 17:17 /* RWEVF */
#define NV_NVLDL_TOP_INTR_STALL_EN_RX_PL_ERROR_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLDL_TOP_INTR_STALL_EN_RX_PL_ERROR_ENABLE 0x00000001 /* RW--V */
#define NV_NVLDL_TOP_INTR_STALL_EN_RX_FAULT_DL_PROTOCOL 20:20 /* RWEVF */
#define NV_NVLDL_TOP_INTR_STALL_EN_RX_FAULT_DL_PROTOCOL_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLDL_TOP_INTR_STALL_EN_RX_FAULT_DL_PROTOCOL_ENABLE 0x00000001 /* RW--V */
#define NV_NVLDL_TOP_INTR_STALL_EN_RX_SHORT_ERROR_RATE 21:21 /* RWEVF */
#define NV_NVLDL_TOP_INTR_STALL_EN_RX_SHORT_ERROR_RATE_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLDL_TOP_INTR_STALL_EN_RX_SHORT_ERROR_RATE_ENABLE 0x00000001 /* RW--V */
#define NV_NVLDL_TOP_INTR_STALL_EN_RX_LONG_ERROR_RATE 22:22 /* RWEVF */
#define NV_NVLDL_TOP_INTR_STALL_EN_RX_LONG_ERROR_RATE_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLDL_TOP_INTR_STALL_EN_RX_LONG_ERROR_RATE_ENABLE 0x00000001 /* RW--V */
#define NV_NVLDL_TOP_INTR_STALL_EN_RX_ILA_TRIGGER 23:23 /* RWEVF */
#define NV_NVLDL_TOP_INTR_STALL_EN_RX_ILA_TRIGGER_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLDL_TOP_INTR_STALL_EN_RX_ILA_TRIGGER_ENABLE 0x00000001 /* RW--V */
#define NV_NVLDL_TOP_INTR_STALL_EN_RX_CRC_COUNTER 24:24 /* RWEVF */
#define NV_NVLDL_TOP_INTR_STALL_EN_RX_CRC_COUNTER_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLDL_TOP_INTR_STALL_EN_RX_CRC_COUNTER_ENABLE 0x00000001 /* RW--V */
#define NV_NVLDL_TOP_INTR_STALL_EN_LTSSM_FAULT_DOWN 27:27 /* RWEVF */
#define NV_NVLDL_TOP_INTR_STALL_EN_LTSSM_FAULT_DOWN_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLDL_TOP_INTR_STALL_EN_LTSSM_FAULT_DOWN_ENABLE 0x00000001 /* RW--V */
#define NV_NVLDL_TOP_INTR_STALL_EN_LTSSM_FAULT_UP 28:28 /* RWEVF */
#define NV_NVLDL_TOP_INTR_STALL_EN_LTSSM_FAULT_UP_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLDL_TOP_INTR_STALL_EN_LTSSM_FAULT_UP_ENABLE 0x00000001 /* RW--V */
#define NV_NVLDL_TOP_INTR_STALL_EN_LTSSM_PROTOCOL 29:29 /* RWEVF */
#define NV_NVLDL_TOP_INTR_STALL_EN_LTSSM_PROTOCOL_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLDL_TOP_INTR_STALL_EN_LTSSM_PROTOCOL_ENABLE 0x00000001 /* RW--V */
#define NV_NVLDL_TOP_INTR_STALL_EN_MINION_REQUEST 30:30 /* RWEVF */
#define NV_NVLDL_TOP_INTR_STALL_EN_MINION_REQUEST_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLDL_TOP_INTR_STALL_EN_MINION_REQUEST_ENABLE 0x00000001 /* RW--V */
#define NV_NVLDL_TOP_INTR_NONSTALL_EN 0x0000005c /* RW-4R */
#define NV_NVLDL_TOP_INTR_NONSTALL_EN_TX_REPLAY 0:0 /* RWEVF */
#define NV_NVLDL_TOP_INTR_NONSTALL_EN_TX_REPLAY_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLDL_TOP_INTR_NONSTALL_EN_TX_RECOVERY_SHORT 1:1 /* RWEVF */
#define NV_NVLDL_TOP_INTR_NONSTALL_EN_TX_RECOVERY_SHORT_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLDL_TOP_INTR_NONSTALL_EN_TX_RECOVERY_SHORT_ENABLE 0x00000001 /* RW--V */
#define NV_NVLDL_TOP_INTR_NONSTALL_EN_TX_FAULT_RAM 4:4 /* RWEVF */
#define NV_NVLDL_TOP_INTR_NONSTALL_EN_TX_FAULT_RAM_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLDL_TOP_INTR_NONSTALL_EN_TX_FAULT_RAM_ENABLE 0x00000001 /* RW--V */
#define NV_NVLDL_TOP_INTR_NONSTALL_EN_TX_FAULT_INTERFACE 5:5 /* RWEVF */
#define NV_NVLDL_TOP_INTR_NONSTALL_EN_TX_FAULT_INTERFACE_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLDL_TOP_INTR_NONSTALL_EN_TX_FAULT_INTERFACE_ENABLE 0x00000001 /* RW--V */
#define NV_NVLDL_TOP_INTR_NONSTALL_EN_TX_FAULT_SUBLINK_CHANGE 8:8 /* RWEVF */
#define NV_NVLDL_TOP_INTR_NONSTALL_EN_TX_FAULT_SUBLINK_CHANGE_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLDL_TOP_INTR_NONSTALL_EN_TX_FAULT_SUBLINK_CHANGE_ENABLE 0x00000001 /* RW--V */
#define NV_NVLDL_TOP_INTR_NONSTALL_EN_TX_PL_ERROR 9:9 /* RWEVF */
#define NV_NVLDL_TOP_INTR_NONSTALL_EN_TX_PL_ERROR_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLDL_TOP_INTR_NONSTALL_EN_TX_PL_ERROR_ENABLE 0x00000001 /* RW--V */
#define NV_NVLDL_TOP_INTR_NONSTALL_EN_PHY_A 12:12 /* RWEVF */
#define NV_NVLDL_TOP_INTR_NONSTALL_EN_PHY_A_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLDL_TOP_INTR_NONSTALL_EN_PHY_A_ENABLE 0x00000001 /* RW--V */
#define NV_NVLDL_TOP_INTR_NONSTALL_EN_PHY_B 13:13 /* RWEVF */
#define NV_NVLDL_TOP_INTR_NONSTALL_EN_PHY_B_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLDL_TOP_INTR_NONSTALL_EN_PHY_B_ENABLE 0x00000001 /* RW--V */
#define NV_NVLDL_TOP_INTR_NONSTALL_EN_RX_FAULT_SUBLINK_CHANGE 16:16 /* RWEVF */
#define NV_NVLDL_TOP_INTR_NONSTALL_EN_RX_FAULT_SUBLINK_CHANGE_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLDL_TOP_INTR_NONSTALL_EN_RX_FAULT_SUBLINK_CHANGE_ENABLE 0x00000001 /* RW--V */
#define NV_NVLDL_TOP_INTR_NONSTALL_EN_RX_PL_ERROR 17:17 /* RWEVF */
#define NV_NVLDL_TOP_INTR_NONSTALL_EN_RX_PL_ERROR_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLDL_TOP_INTR_NONSTALL_EN_RX_PL_ERROR_ENABLE 0x00000001 /* RW--V */
#define NV_NVLDL_TOP_INTR_NONSTALL_EN_RX_FAULT_DL_PROTOCOL 20:20 /* RWEVF */
#define NV_NVLDL_TOP_INTR_NONSTALL_EN_RX_FAULT_DL_PROTOCOL_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLDL_TOP_INTR_NONSTALL_EN_RX_FAULT_DL_PROTOCOL_ENABLE 0x00000001 /* RW--V */
#define NV_NVLDL_TOP_INTR_NONSTALL_EN_RX_SHORT_ERROR_RATE 21:21 /* RWEVF */
#define NV_NVLDL_TOP_INTR_NONSTALL_EN_RX_SHORT_ERROR_RATE_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLDL_TOP_INTR_NONSTALL_EN_RX_SHORT_ERROR_RATE_ENABLE 0x00000001 /* RW--V */
#define NV_NVLDL_TOP_INTR_NONSTALL_EN_RX_LONG_ERROR_RATE 22:22 /* RWEVF */
#define NV_NVLDL_TOP_INTR_NONSTALL_EN_RX_LONG_ERROR_RATE_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLDL_TOP_INTR_NONSTALL_EN_RX_LONG_ERROR_RATE_ENABLE 0x00000001 /* RW--V */
#define NV_NVLDL_TOP_INTR_NONSTALL_EN_RX_ILA_TRIGGER 23:23 /* RWEVF */
#define NV_NVLDL_TOP_INTR_NONSTALL_EN_RX_ILA_TRIGGER_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLDL_TOP_INTR_NONSTALL_EN_RX_ILA_TRIGGER_ENABLE 0x00000001 /* RW--V */
#define NV_NVLDL_TOP_INTR_NONSTALL_EN_RX_CRC_COUNTER 24:24 /* RWEVF */
#define NV_NVLDL_TOP_INTR_NONSTALL_EN_RX_CRC_COUNTER_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLDL_TOP_INTR_NONSTALL_EN_RX_CRC_COUNTER_ENABLE 0x00000001 /* RW--V */
#define NV_NVLDL_TOP_INTR_NONSTALL_EN_LTSSM_FAULT_DOWN 27:27 /* RWEVF */
#define NV_NVLDL_TOP_INTR_NONSTALL_EN_LTSSM_FAULT_DOWN_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLDL_TOP_INTR_NONSTALL_EN_LTSSM_FAULT_DOWN_ENABLE 0x00000001 /* RW--V */
#define NV_NVLDL_TOP_INTR_NONSTALL_EN_LTSSM_FAULT_UP 28:28 /* RWEVF */
#define NV_NVLDL_TOP_INTR_NONSTALL_EN_LTSSM_FAULT_UP_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLDL_TOP_INTR_NONSTALL_EN_LTSSM_FAULT_UP_ENABLE 0x00000001 /* RW--V */
#define NV_NVLDL_TOP_INTR_NONSTALL_EN_LTSSM_PROTOCOL 29:29 /* RWEVF */
#define NV_NVLDL_TOP_INTR_NONSTALL_EN_LTSSM_PROTOCOL_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLDL_TOP_INTR_NONSTALL_EN_LTSSM_PROTOCOL_ENABLE 0x00000001 /* RW--V */
#define NV_NVLDL_TOP_INTR_NONSTALL_EN_MINION_REQUEST 30:30 /* RWEVF */
#define NV_NVLDL_TOP_INTR_NONSTALL_EN_MINION_REQUEST_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLDL_TOP_INTR_NONSTALL_EN_MINION_REQUEST_ENABLE 0x00000001 /* RW--V */
#define NV_NVLDL_TOP_ERROR_COUNT_CTRL 0x00000080 /* RW-4R */
#define NV_NVLDL_TOP_ERROR_COUNT_CTRL_CLEAR_RECOVERY 2:2 /* -WXVF */
#define NV_NVLDL_TOP_ERROR_COUNT_CTRL_CLEAR_RECOVERY_CLEAR 0x00000001 /* -W--V */
#define NV_NVLDL_TOP_ERROR_COUNT_CTRL_MASK_SEL 21:16 /* RWEVF */
#define NV_NVLDL_TOP_ERROR_COUNT_CTRL_MASK_SEL_SAFEMODE 0x00000001 /* RW--V */
#define NV_NVLDL_TOP_ERROR_COUNT_CTRL_MASK_SEL_STEADYHS 0x00000002 /* RWE-V */
#define NV_NVLDL_TOP_ERROR_COUNT_CTRL_MASK_SEL_EARLYINITHS 0x00000004 /* RW--V */
#define NV_NVLDL_TOP_ERROR_COUNT_CTRL_MASK_SEL_EARLYL1HS 0x00000008 /* RW--V */
#define NV_NVLDL_TOP_ERROR_COUNT_CTRL_MASK_SEL_EARLYRCVYHS 0x00000010 /* RW--V */
#define NV_NVLDL_TOP_ERROR_COUNT_CTRL_MASK_SEL_RSVD20 0x00000020 /* RW--V */
#define NV_NVLDL_TOP_ERROR_COUNT_CTRL_MASK_DELAY 27:24 /* RWEUF */
#define NV_NVLDL_TOP_ERROR_COUNT_CTRL_MASK_DELAY_INIT 0x00000001 /* RWE-V */
#define NV_NVLDL_TX_SLSM_STATUS_TX 0x00002024 /* R--4R */
#define NV_NVLDL_TX_SLSM_STATUS_TX_SUBSTATE 3:0 /* R-XVF */
#define NV_NVLDL_TX_SLSM_STATUS_TX_SUBSTATE_STABLE 0x00000000 /* R---V */
#define NV_NVLDL_TX_SLSM_STATUS_TX_PRIMARY_STATE 7:4 /* R-XVF */
#define NV_NVLDL_TX_SLSM_STATUS_TX_PRIMARY_STATE_HS 0x00000000 /* R---V */
#define NV_NVLDL_TX_SLSM_STATUS_TX_PRIMARY_STATE_TRAIN 0x00000005 /* R---V */
#define NV_NVLDL_TX_SLSM_STATUS_TX_PRIMARY_STATE_SAFE 0x00000006 /* R---V */
#define NV_NVLDL_TX_SLSM_STATUS_TX_PRIMARY_STATE_OFF 0x00000007 /* R---V */
#define NV_NVLDL_TX_SLSM_STATUS_TX_PRIMARY_STATE_TEST 0x00000008 /* R---V */
#define NV_NVLDL_TX_SLSM_STATUS_TX_PRIMARY_STATE_UNKNOWN 0x0000000d /* R---V */
#define NV_NVLDL_TX_ERROR_COUNT_CTRL 0x00002280 /* -W-4R */
#define NV_NVLDL_TX_ERROR_COUNT_CTRL_CLEAR_R4_RETRY 0:0 /* -WXVF */
#define NV_NVLDL_TX_ERROR_COUNT_CTRL_CLEAR_R4_RETRY_CLEAR 0x00000001 /* -W--V */
#define NV_NVLDL_TX_ERROR_COUNT_CTRL_CLEAR_REPLAY 8:8 /* -WXVF */
#define NV_NVLDL_TX_ERROR_COUNT_CTRL_CLEAR_REPLAY_CLEAR 0x00000001 /* -W--V */
#define NV_NVLDL_RX_SLSM_STATUS_RX 0x00003014 /* R--4R */
#define NV_NVLDL_RX_SLSM_STATUS_RX_SUBSTATE 3:0 /* R-EVF */
#define NV_NVLDL_RX_SLSM_STATUS_RX_SUBSTATE_STABLE 0x00000000 /* R-E-V */
#define NV_NVLDL_RX_SLSM_STATUS_RX_PRIMARY_STATE 7:4 /* R-XVF */
#define NV_NVLDL_RX_SLSM_STATUS_RX_PRIMARY_STATE_HS 0x00000000 /* R---V */
#define NV_NVLDL_RX_SLSM_STATUS_RX_PRIMARY_STATE_TRAIN 0x00000005 /* R---V */
#define NV_NVLDL_RX_SLSM_STATUS_RX_PRIMARY_STATE_SAFE 0x00000006 /* R---V */
#define NV_NVLDL_RX_SLSM_STATUS_RX_PRIMARY_STATE_OFF 0x00000007 /* R---V */
#define NV_NVLDL_RX_SLSM_STATUS_RX_PRIMARY_STATE_TEST 0x00000008 /* R---V */
#define NV_NVLDL_RX_SLSM_STATUS_RX_PRIMARY_STATE_UNKNOWN 0x0000000d /* R---V */
#define NV_NVLDL_RX_SLSM_STATUS_RX_PRIMARY_STATE_FAULT 0x0000000e /* R---V */
#define NV_NVLDL_RX_SLSM_STATUS_RX_UNEXPECTED_REMOTE_STATE_CNT 15:8 /* R-EVF */
#define NV_NVLDL_RX_SLSM_STATUS_RX_UNEXPECTED_REMOTE_STATE_CNT_INIT 0x00000000 /* R-E-V */
#define NV_NVLDL_RX_SLSM_STATUS_RX_FENCE_STATUS 31:31 /* R-EVF */
#define NV_NVLDL_RX_SLSM_STATUS_RX_FENCE_STATUS_OFF 0x00000000 /* R-E-V */
#define NV_NVLDL_RX_SLSM_STATUS_RX_FENCE_STATUS_ON 0x00000001 /* R---V */
#define NV_NVLDL_RX_RXSLSM_ERR_CNTL 0x00003028 /* RW-4R */
#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_CONST_DET_ERR 1:1 /* RWEVF */
#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_CONST_DET_ERR__ONWRITE "oneToClear" /* */
#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_CONST_DET_ERR_OFF 0x00000000 /* RWE-V */
#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_CONST_DET_ERR_ON 0x00000001 /* RW--V */
#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_OFF2SAFE_LINK_DET_ERR 2:2 /* RWEVF */
#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_OFF2SAFE_LINK_DET_ERR__ONWRITE "oneToClear" /* */
#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_OFF2SAFE_LINK_DET_ERR_OFF 0x00000000 /* RWE-V */
#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_OFF2SAFE_LINK_DET_ERR_ON 0x00000001 /* RW--V */
#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_SAFE_FINISH_ERR 3:3 /* RWEVF */
#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_SAFE_FINISH_ERR__ONWRITE "oneToClear" /* */
#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_SAFE_FINISH_ERR_OFF 0x00000000 /* RWE-V */
#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_SAFE_FINISH_ERR_ON 0x00000001 /* RW--V */
#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_SCRAM_LOCK_ERR 4:4 /* RWEVF */
#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_SCRAM_LOCK_ERR__ONWRITE "oneToClear" /* */
#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_SCRAM_LOCK_ERR_OFF 0x00000000 /* RWE-V */
#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_SCRAM_LOCK_ERR_ON 0x00000001 /* RW--V */
#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_SYM_LOCK_ERR 5:5 /* RWEVF */
#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_SYM_LOCK_ERR__ONWRITE "oneToClear" /* */
#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_SYM_LOCK_ERR_OFF 0x00000000 /* RWE-V */
#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_SYM_LOCK_ERR_ON 0x00000001 /* RW--V */
#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_SYM_ALIGN_END_ERR 6:6 /* RWEVF */
#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_SYM_ALIGN_END_ERR__ONWRITE "oneToClear" /* */
#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_SYM_ALIGN_END_ERR_OFF 0x00000000 /* RWE-V */
#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_SYM_ALIGN_END_ERR_ON 0x00000001 /* RW--V */
#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_FIFO_SKEW_ERR 7:7 /* RWEVF */
#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_FIFO_SKEW_ERR__ONWRITE "oneToClear" /* */
#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_FIFO_SKEW_ERR_OFF 0x00000000 /* RWE-V */
#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_FIFO_SKEW_ERR_ON 0x00000001 /* RW--V */
#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_TRAIN2SAFE_LINK_DET_ERR 8:8 /* RWEVF */
#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_TRAIN2SAFE_LINK_DET_ERR__ONWRITE "oneToClear" /* */
#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_TRAIN2SAFE_LINK_DET_ERR_OFF 0x00000000 /* RWE-V */
#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_TRAIN2SAFE_LINK_DET_ERR_ON 0x00000001 /* RW--V */
#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_HS2SAFE_LINK_DET_ERR 9:9 /* RWEVF */
#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_HS2SAFE_LINK_DET_ERR__ONWRITE "oneToClear" /* */
#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_HS2SAFE_LINK_DET_ERR_OFF 0x00000000 /* RWE-V */
#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_HS2SAFE_LINK_DET_ERR_ON 0x00000001 /* RW--V */
#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_FENCE_ERR 10:10 /* RWEVF */
#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_FENCE_ERR__ONWRITE "oneToClear" /* */
#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_FENCE_ERR_OFF 0x00000000 /* RWE-V */
#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_FENCE_ERR_ON 0x00000001 /* RW--V */
#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_FAULT2SAFE_LINK_DET_ERR 11:11 /* RWEVF */
#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_FAULT2SAFE_LINK_DET_ERR__ONWRITE "oneToClear" /* */
#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_FAULT2SAFE_LINK_DET_ERR_OFF 0x00000000 /* RWE-V */
#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_FAULT2SAFE_LINK_DET_ERR_ON 0x00000001 /* RW--V */
#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_FAULT2SAFE_SAFE_DET_ERR 12:12 /* RWEVF */
#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_FAULT2SAFE_SAFE_DET_ERR__ONWRITE "oneToClear" /* */
#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_FAULT2SAFE_SAFE_DET_ERR_OFF 0x00000000 /* RWE-V */
#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_FAULT2SAFE_SAFE_DET_ERR_ON 0x00000001 /* RW--V */
#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_SAFE_RETRY_ERR 13:13 /* RWEVF */
#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_SAFE_RETRY_ERR__ONWRITE "oneToClear" /* */
#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_SAFE_RETRY_ERR_OFF 0x00000000 /* RWE-V */
#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_SAFE_RETRY_ERR_ON 0x00000001 /* RW--V */
#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_RC_DEADLINE_ERR 15:15 /* RWEVF */
#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_RC_DEADLINE_ERR__ONWRITE "oneToClear" /* */
#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_RC_DEADLINE_ERR_OFF 0x00000000 /* RWE-V */
#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_RC_DEADLINE_ERR_ON 0x00000001 /* RW--V */
#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_IOBIST_ECC_ALIGN_DONE_ERR 16:16 /* RWEVF */
#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_IOBIST_ECC_ALIGN_DONE_ERR__ONWRITE "oneToClear" /* */
#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_IOBIST_ECC_ALIGN_DONE_ERR_OFF 0x00000000 /* RWE-V */
#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_IOBIST_ECC_ALIGN_DONE_ERR_ON 0x00000001 /* RW--V */
#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_O2S_SD_NO_LD_ERR 18:18 /* RWEVF */
#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_O2S_SD_NO_LD_ERR__ONWRITE "oneToClear" /* */
#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_O2S_SD_NO_LD_ERR_OFF 0x00000000 /* RWE-V */
#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_O2S_SD_NO_LD_ERR_ON 0x00000001 /* RW--V */
#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_H2S_SD_NO_LD_ERR 19:19 /* RWEVF */
#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_H2S_SD_NO_LD_ERR__ONWRITE "oneToClear" /* */
#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_H2S_SD_NO_LD_ERR_OFF 0x00000000 /* RWE-V */
#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_H2S_SD_NO_LD_ERR_ON 0x00000001 /* RW--V */
#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_O2S_STROBE_NO_SD_ERR 21:21 /* RWEVF */
#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_O2S_STROBE_NO_SD_ERR__ONWRITE "oneToClear" /* */
#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_O2S_STROBE_NO_SD_ERR_OFF 0x00000000 /* RWE-V */
#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_O2S_STROBE_NO_SD_ERR_ON 0x00000001 /* RW--V */
#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_H2S_STROBE_NO_SD_ERR 22:22 /* RWEVF */
#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_H2S_STROBE_NO_SD_ERR__ONWRITE "oneToClear" /* */
#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_H2S_STROBE_NO_SD_ERR_OFF 0x00000000 /* RWE-V */
#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_H2S_STROBE_NO_SD_ERR_ON 0x00000001 /* RW--V */
#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_HS2SAFE_SAFE_DET_ERR 24:24 /* RWEVF */
#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_HS2SAFE_SAFE_DET_ERR__ONWRITE "oneToClear" /* */
#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_HS2SAFE_SAFE_DET_ERR_OFF 0x00000000 /* RWE-V */
#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_HS2SAFE_SAFE_DET_ERR_ON 0x00000001 /* RW--V */
#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_TRAIN2SAFE_SAFE_DET_ERR 25:25 /* RWEVF */
#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_TRAIN2SAFE_SAFE_DET_ERR__ONWRITE "oneToClear" /* */
#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_TRAIN2SAFE_SAFE_DET_ERR_OFF 0x00000000 /* RWE-V */
#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_TRAIN2SAFE_SAFE_DET_ERR_ON 0x00000001 /* RW--V */
#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_S2S_SAFE_DET_ERR 26:26 /* RWEVF */
#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_S2S_SAFE_DET_ERR__ONWRITE "oneToClear" /* */
#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_S2S_SAFE_DET_ERR_OFF 0x00000000 /* RWE-V */
#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_S2S_SAFE_DET_ERR_ON 0x00000001 /* RW--V */
#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_OFF2SAFE_SAFE_DET_ERR 27:27 /* RWEVF */
#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_OFF2SAFE_SAFE_DET_ERR__ONWRITE "oneToClear" /* */
#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_OFF2SAFE_SAFE_DET_ERR_OFF 0x00000000 /* RWE-V */
#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_OFF2SAFE_SAFE_DET_ERR_ON 0x00000001 /* RW--V */
#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_L2_FENCE_ERR 29:29 /* RWEVF */
#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_L2_FENCE_ERR__ONWRITE "oneToClear" /* */
#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_L2_FENCE_ERR_OFF 0x00000000 /* RWE-V */
#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_L2_FENCE_ERR_ON 0x00000001 /* RW--V */
#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_IOBIST_ECC_SCRAM_LOCK_ERR 30:30 /* RWEVF */
#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_IOBIST_ECC_SCRAM_LOCK_ERR__ONWRITE "oneToClear" /* */
#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_IOBIST_ECC_SCRAM_LOCK_ERR_OFF 0x00000000 /* RWE-V */
#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_IOBIST_ECC_SCRAM_LOCK_ERR_ON 0x00000001 /* RW--V */
#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_IOBIST_ECC_ALIGN_LOCK_ERR 31:31 /* RWEVF */
#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_IOBIST_ECC_ALIGN_LOCK_ERR__ONWRITE "oneToClear" /* */
#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_IOBIST_ECC_ALIGN_LOCK_ERR_OFF 0x00000000 /* RWE-V */
#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_IOBIST_ECC_ALIGN_LOCK_ERR_ON 0x00000001 /* RW--V */
#define NV_NVLDL_RX_ERROR_COUNT_CTRL 0x00003280 /* RW-4R */
#define NV_NVLDL_RX_ERROR_COUNT_CTRL_CLEAR_FLIT_CRC 0:0 /* -WEVF */
#define NV_NVLDL_RX_ERROR_COUNT_CTRL_CLEAR_FLIT_CRC_INIT 0x00000000 /* -WE-V */
#define NV_NVLDL_RX_ERROR_COUNT_CTRL_CLEAR_FLIT_CRC_CLEAR 0x00000001 /* -W--V */
#define NV_NVLDL_RX_ERROR_COUNT_CTRL_CLEAR_LANE_CRC 1:1 /* -WEVF */
#define NV_NVLDL_RX_ERROR_COUNT_CTRL_CLEAR_LANE_CRC_INIT 0x00000000 /* -WE-V */
#define NV_NVLDL_RX_ERROR_COUNT_CTRL_CLEAR_LANE_CRC_CLEAR 0x00000001 /* -W--V */
#define NV_NVLDL_RX_ERROR_COUNT_CTRL_CLEAR_RATES 2:2 /* -WEVF */
#define NV_NVLDL_RX_ERROR_COUNT_CTRL_CLEAR_RATES_INIT 0x00000000 /* -WE-V */
#define NV_NVLDL_RX_ERROR_COUNT_CTRL_CLEAR_RATES_CLEAR 0x00000001 /* -W--V */
#define NV_NVLDL_RX_ERROR_COUNT_CTRL_CLEAR_REPLAY 3:3 /* -WEVF */
#define NV_NVLDL_RX_ERROR_COUNT_CTRL_CLEAR_REPLAY_INIT 0x00000000 /* -WE-V */
#define NV_NVLDL_RX_ERROR_COUNT_CTRL_CLEAR_REPLAY_CLEAR 0x00000001 /* -W--V */
#define NV_NVLDL_RX_ERROR_COUNT_CTRL_CLEAR_ECC_COUNTS 4:4 /* -WEVF */
#define NV_NVLDL_RX_ERROR_COUNT_CTRL_CLEAR_ECC_COUNTS_INIT 0x00000000 /* -WE-V */
#define NV_NVLDL_RX_ERROR_COUNT_CTRL_CLEAR_ECC_COUNTS_CLEAR 0x00000001 /* -W--V */
#define NV_NVLDL_RX_ERROR_COUNT_CTRL_SHORT_RATE 8:8 /* RWEVF */
#define NV_NVLDL_RX_ERROR_COUNT_CTRL_SHORT_RATE_ENABLE 0x00000001 /* RWE-V */
#define NV_NVLDL_RX_ERROR_COUNT_CTRL_SHORT_RATE_DISABLE 0x00000000 /* RW--V */
#define NV_NVLDL_RX_ERROR_COUNT_CTRL_LONG_RATE 9:9 /* RWEVF */
#define NV_NVLDL_RX_ERROR_COUNT_CTRL_LONG_RATE_ENABLE 0x00000001 /* RWE-V */
#define NV_NVLDL_RX_ERROR_COUNT_CTRL_LONG_RATE_DISABLE 0x00000000 /* RW--V */
#define NV_NVLDL_RX_ERROR_COUNT_CTRL_RATE_COUNT_MODE 10:10 /* RWEVF */
#define NV_NVLDL_RX_ERROR_COUNT_CTRL_RATE_COUNT_MODE_FLIT 0x00000000 /* RWE-V */
#define NV_NVLDL_RX_ERROR_COUNT_CTRL_RATE_COUNT_MODE_SEQUENCE 0x00000001 /* RW--V */
#define NV_NVLDL_RX_ERROR_COUNT_CTRL_FLIT_COUNT_MODE 11:11 /* RWEVF */
#define NV_NVLDL_RX_ERROR_COUNT_CTRL_FLIT_COUNT_MODE_FLIT 0x00000000 /* RW--V */
#define NV_NVLDL_RX_ERROR_COUNT_CTRL_FLIT_COUNT_MODE_SEQUENCE 0x00000001 /* RWE-V */
#define NV_NVLDL_RX_ERROR_COUNT_CTRL_RATE_COUNT_SRC 13:12 /* RWEVF */
#define NV_NVLDL_RX_ERROR_COUNT_CTRL_RATE_COUNT_SRC_FLITCRC 0x00000000 /* RWE-V */
#define NV_NVLDL_RX_ERROR_COUNT_CTRL_RATE_COUNT_SRC_ECCFAIL 0x00000001 /* RW--V */
#define NV_NVLDL_RX_ERROR_COUNT_CTRL_RATE_COUNT_SRC_ECCCORR 0x00000002 /* RW--V */
#define NV_NVLDL_RX_ERROR_RATE_CTRL 0x00003284 /* RW-4R */
#define NV_NVLDL_RX_ERROR_RATE_CTRL_SHORT_THRESHOLD_MAN 2:0 /* RWEUF */
#define NV_NVLDL_RX_ERROR_RATE_CTRL_SHORT_THRESHOLD_MAN_INIT 0x00000001 /* RWE-V */
#define NV_NVLDL_RX_ERROR_RATE_CTRL_SHORT_THRESHOLD_EXP 3:3 /* RWEUF */
#define NV_NVLDL_RX_ERROR_RATE_CTRL_SHORT_THRESHOLD_EXP_INIT 0x00000000 /* RWE-V */
#define NV_NVLDL_RX_ERROR_RATE_CTRL_SHORT_TIMESCALE_MAN 6:4 /* RWEUF */
#define NV_NVLDL_RX_ERROR_RATE_CTRL_SHORT_TIMESCALE_MAN_INIT 0x00000000 /* RWE-V */
#define NV_NVLDL_RX_ERROR_RATE_CTRL_SHORT_TIMESCALE_EXP 11:8 /* RWEUF */
#define NV_NVLDL_RX_ERROR_RATE_CTRL_SHORT_TIMESCALE_EXP_INIT 0x00000006 /* RWE-V */
#define NV_NVLDL_RX_ERROR_RATE_CTRL_LONG_THRESHOLD_MAN 18:16 /* RWEUF */
#define NV_NVLDL_RX_ERROR_RATE_CTRL_LONG_THRESHOLD_MAN_INIT 0x00000001 /* RWE-V */
#define NV_NVLDL_RX_ERROR_RATE_CTRL_LONG_THRESHOLD_EXP 19:19 /* RWEUF */
#define NV_NVLDL_RX_ERROR_RATE_CTRL_LONG_THRESHOLD_EXP_INIT 0x00000000 /* RWE-V */
#define NV_NVLDL_RX_ERROR_RATE_CTRL_LONG_TIMESCALE_MAN 22:20 /* RWEUF */
#define NV_NVLDL_RX_ERROR_RATE_CTRL_LONG_TIMESCALE_MAN_INIT 0x00000000 /* RWE-V */
#define NV_NVLDL_RX_ERROR_RATE_CTRL_LONG_TIMESCALE_EXP 28:24 /* RWEUF */
#define NV_NVLDL_RX_ERROR_RATE_CTRL_LONG_TIMESCALE_EXP_INIT 0x00000006 /* RWE-V */
#endif // __ls10_dev_nvldl_ip_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the Software),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __ls10_dev_nvldl_ip_addendum_h__
#define __ls10_dev_nvldl_ip_addendum_h__
#define NV_NVLDL_CRC_BIT_ERROR_RATE_SHORT_THRESHOLD_MAN 2:0
#define NV_NVLDL_CRC_BIT_ERROR_RATE_SHORT_THRESHOLD_MAN_DEFAULT 0x00000007
#define NV_NVLDL_CRC_BIT_ERROR_RATE_SHORT_THRESHOLD_EXP 3:3
#define NV_NVLDL_CRC_BIT_ERROR_RATE_SHORT_THRESHOLD_EXP_DEFAULT 0x00000000
#define NV_NVLDL_CRC_BIT_ERROR_RATE_SHORT_TIMESCALE_MAN 6:4
#define NV_NVLDL_CRC_BIT_ERROR_RATE_SHORT_TIMESCALE_MAN_DEFAULT 0x00000005
#define NV_NVLDL_CRC_BIT_ERROR_RATE_SHORT_TIMESCALE_EXP 12:8
#define NV_NVLDL_CRC_BIT_ERROR_RATE_SHORT_TIMESCALE_EXP_DEFAULT 0x00000005
#endif // __ls10_dev_nvldl_ip_addendum_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the Software),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __ls10_dev_nvlipt_ip_h__
#define __ls10_dev_nvlipt_ip_h__
/* This file is autogenerated. Do not edit */
#define NV_NVLIPT_COMMON 0x000007FF:0x00000000 /* RW--D */
#define NV_NVLIPT_COMMON_TOPOLOGY_LOCAL_CHIP_SID_LO 0x00000108 /* R--4R */
#define NV_NVLIPT_COMMON_TOPOLOGY_LOCAL_CHIP_SID_LO_SID_31_0 31:0 /* R-IVF */
#define NV_NVLIPT_COMMON_TOPOLOGY_LOCAL_CHIP_SID_LO_SID_31_0_INIT 0x00000000 /* R-I-V */
#define NV_NVLIPT_COMMON_TOPOLOGY_LOCAL_CHIP_SID_HI 0x0000010c /* R--4R */
#define NV_NVLIPT_COMMON_TOPOLOGY_LOCAL_CHIP_SID_HI_SID_63_32 31:0 /* R-IVF */
#define NV_NVLIPT_COMMON_TOPOLOGY_LOCAL_CHIP_SID_HI_SID_63_32_INIT 0x00000000 /* R-I-V */
#define NV_NVLIPT_COMMON_TOPOLOGY_LOCAL_LINK_CONFIGURATION 0x00000114 /* RW-4R */
#define NV_NVLIPT_COMMON_TOPOLOGY_LOCAL_LINK_CONFIGURATION_NUM_LINKS_PER_NVLIPT 7:0 /* R-IVF */
#define NV_NVLIPT_COMMON_TOPOLOGY_LOCAL_LINK_CONFIGURATION_NUM_LINKS_PER_NVLIPT_INIT 0x00000004 /* R-I-V */
#define NV_NVLIPT_COMMON_TOPOLOGY_LOCAL_LINK_CONFIGURATION_NUM_LANES_PER_LINK 15:8 /* R-IVF */
#define NV_NVLIPT_COMMON_TOPOLOGY_LOCAL_LINK_CONFIGURATION_NUM_LANES_PER_LINK_INIT 0x00000002 /* R-I-V */
#define NV_NVLIPT_COMMON_TOPOLOGY_LOCAL_LINK_CONFIGURATION_NUM_USABLE_LINKS 26:24 /* RWIVF */
#define NV_NVLIPT_COMMON_TOPOLOGY_LOCAL_LINK_CONFIGURATION_NUM_USABLE_LINKS_INIT 0x00000004 /* RWI-V */
#define NV_NVLIPT_COMMON_ERR_STATUS_0 0x00000280 /* RW-4R */
#define NV_NVLIPT_COMMON_ERR_STATUS_0_CLKCTL_ILLEGAL_REQUEST 0:0 /* RWIVF */
#define NV_NVLIPT_COMMON_ERR_STATUS_0_CLKCTL_ILLEGAL_REQUEST__ONWRITE "oneToClear" /* */
#define NV_NVLIPT_COMMON_ERR_STATUS_0_CLKCTL_ILLEGAL_REQUEST_NONE 0x00000000 /* RWI-V */
#define NV_NVLIPT_COMMON_ERR_STATUS_0_CLKCTL_ILLEGAL_REQUEST_CLEAR 0x00000001 /* RW--V */
#define NV_NVLIPT_COMMON_ERR_FATAL_REPORT_EN_0 0x00000288 /* RW-4R */
#define NV_NVLIPT_COMMON_ERR_FATAL_REPORT_EN_0_CLKCTL_ILLEGAL_REQUEST 0:0 /* RWEVF */
#define NV_NVLIPT_COMMON_ERR_FATAL_REPORT_EN_0_CLKCTL_ILLEGAL_REQUEST_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLIPT_COMMON_ERR_FATAL_REPORT_EN_0_CLKCTL_ILLEGAL_REQUEST_ENABLE 0x00000001 /* RW--V */
#define NV_NVLIPT_COMMON_ERR_CONTAIN_EN_0 0x00000294 /* RW-4R */
#define NV_NVLIPT_COMMON_ERR_CONTAIN_EN_0_CLKCTL_ILLEGAL_REQUEST 0:0 /* RWEVF */
#define NV_NVLIPT_COMMON_ERR_CONTAIN_EN_0_CLKCTL_ILLEGAL_REQUEST_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLIPT_COMMON_ERR_CONTAIN_EN_0_CLKCTL_ILLEGAL_REQUEST_ENABLE 0x00000001 /* RW--V */
#define NV_NVLIPT_COMMON_ERR_FIRST_0 0x0000029c /* RW-4R */
#define NV_NVLIPT_COMMON_ERR_FIRST_0_CLKCTL_ILLEGAL_REQUEST 0:0 /* RWIVF */
#define NV_NVLIPT_COMMON_ERR_FIRST_0_CLKCTL_ILLEGAL_REQUEST__ONWRITE "oneToClear" /* */
#define NV_NVLIPT_COMMON_ERR_FIRST_0_CLKCTL_ILLEGAL_REQUEST_NONE 0x00000000 /* RWI-V */
#define NV_NVLIPT_COMMON_ERR_FIRST_0_CLKCTL_ILLEGAL_REQUEST_CLEAR 0x00000001 /* RW--V */
#define NV_NVLIPT_COMMON_INTR_CONTROL_COMMON 0x00000300 /* RW-4R */
#define NV_NVLIPT_COMMON_INTR_CONTROL_COMMON_INT0_EN 0:0 /* RWEVF */
#define NV_NVLIPT_COMMON_INTR_CONTROL_COMMON_INT0_EN_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLIPT_COMMON_INTR_CONTROL_COMMON_INT0_EN_ENABLE 0x00000001 /* RW--V */
#define NV_NVLIPT_COMMON_INTR_CONTROL_COMMON_INT1_EN 1:1 /* RWEVF */
#define NV_NVLIPT_COMMON_INTR_CONTROL_COMMON_INT1_EN_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLIPT_COMMON_INTR_CONTROL_COMMON_INT1_EN_ENABLE 0x00000001 /* RW--V */
#endif // __ls10_dev_nvlipt_ip_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the Software),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __ls10_dev_nvlipt_lnk_ip_h__
#define __ls10_dev_nvlipt_lnk_ip_h__
/* This file is autogenerated. Do not edit */
#define NV_NVLIPT_LNK 0x000007FF:0x00000000 /* RW--D */
#define NV_NVLIPT_LNK_CTRL_PRI_CLOCK_GATING_LINK 0x0000008c /* RW-4R */
#define NV_NVLIPT_LNK_CTRL_PRI_CLOCK_GATING_LINK_TL_CG1_SLCG 0:0 /* RWEVF */
#define NV_NVLIPT_LNK_CTRL_PRI_CLOCK_GATING_LINK_TL_CG1_SLCG_ENABLED 0x00000000 /* RW--V */
#define NV_NVLIPT_LNK_CTRL_PRI_CLOCK_GATING_LINK_TL_CG1_SLCG_DISABLED 0x00000001 /* RWE-V */
#define NV_NVLIPT_LNK_CTRL_PRI_CLOCK_GATING_LINK_DL_CG1_SLCG 8:8 /* RWEVF */
#define NV_NVLIPT_LNK_CTRL_PRI_CLOCK_GATING_LINK_DL_CG1_SLCG_ENABLED 0x00000000 /* RW--V */
#define NV_NVLIPT_LNK_CTRL_PRI_CLOCK_GATING_LINK_DL_CG1_SLCG_DISABLED 0x00000001 /* RWE-V */
#define NV_NVLIPT_LNK_CTRL_CLK_CTRL 0x00000090 /* RW-4R */
#define NV_NVLIPT_LNK_CTRL_CLK_CTRL_RXCLK_SEL 1:0 /* RWEVF */
#define NV_NVLIPT_LNK_CTRL_CLK_CTRL_RXCLK_SEL_LANE_CLK 0x00000000 /* RW--V */
#define NV_NVLIPT_LNK_CTRL_CLK_CTRL_RXCLK_SEL_TX_CLK 0x00000002 /* RW--V */
#define NV_NVLIPT_LNK_CTRL_CLK_CTRL_RXCLK_SEL_OFF 0x00000003 /* RWE-V */
#define NV_NVLIPT_LNK_CTRL_CLK_CTRL_TXCLK_SEL 4:3 /* RWEVF */
#define NV_NVLIPT_LNK_CTRL_CLK_CTRL_TXCLK_SEL_PLL_CLK 0x00000000 /* RW--V */
#define NV_NVLIPT_LNK_CTRL_CLK_CTRL_TXCLK_SEL_ALT_CLK 0x00000001 /* RW--V */
#define NV_NVLIPT_LNK_CTRL_CLK_CTRL_TXCLK_SEL_OFF 0x00000003 /* RWE-V */
#define NV_NVLIPT_LNK_CTRL_CLK_CTRL_NCISOCCLK_SEL 6:6 /* RWEVF */
#define NV_NVLIPT_LNK_CTRL_CLK_CTRL_NCISOCCLK_SEL_OFF 0x00000000 /* RWE-V */
#define NV_NVLIPT_LNK_CTRL_CLK_CTRL_NCISOCCLK_SEL_ON 0x00000001 /* RW--V */
#define NV_NVLIPT_LNK_CTRL_CLK_CTRL_RXCLK_STS 17:16 /* R-EVF */
#define NV_NVLIPT_LNK_CTRL_CLK_CTRL_RXCLK_STS_LANE_CLK 0x00000000 /* R---V */
#define NV_NVLIPT_LNK_CTRL_CLK_CTRL_RXCLK_STS_TX_CLK 0x00000002 /* R---V */
#define NV_NVLIPT_LNK_CTRL_CLK_CTRL_RXCLK_STS_OFF 0x00000003 /* R-E-V */
#define NV_NVLIPT_LNK_CTRL_CLK_CTRL_TXCLK_STS 20:19 /* R-EVF */
#define NV_NVLIPT_LNK_CTRL_CLK_CTRL_TXCLK_STS_PLL_CLK 0x00000000 /* R---V */
#define NV_NVLIPT_LNK_CTRL_CLK_CTRL_TXCLK_STS_ALT_CLK 0x00000001 /* R---V */
#define NV_NVLIPT_LNK_CTRL_CLK_CTRL_TXCLK_STS_OFF 0x00000003 /* R-E-V */
#define NV_NVLIPT_LNK_CTRL_CLK_CTRL_NCISOCCLK_STS 21:21 /* R-EVF */
#define NV_NVLIPT_LNK_CTRL_CLK_CTRL_NCISOCCLK_STS_OFF 0x00000000 /* R---V */
#define NV_NVLIPT_LNK_CTRL_CLK_CTRL_NCISOCCLK_STS_ON 0x00000001 /* R-E-V */
#define NV_NVLIPT_LNK_CTRL_CLK_CTRL_PLL_PWR 24:24 /* RWEVF */
#define NV_NVLIPT_LNK_CTRL_CLK_CTRL_PLL_PWR_OFF 0x00000000 /* RWE-V */
#define NV_NVLIPT_LNK_CTRL_CLK_CTRL_PLL_PWR_ON 0x00000001 /* RW--V */
#define NV_NVLIPT_LNK_CTRL_CLK_CTRL_PLL_PWR_STS 25:25 /* R-EVF */
#define NV_NVLIPT_LNK_CTRL_CLK_CTRL_PLL_PWR_STS_OFF 0x00000000 /* R-E-V */
#define NV_NVLIPT_LNK_CTRL_CLK_CTRL_PLL_PWR_STS_ON 0x00000001 /* R---V */
#define NV_NVLIPT_LNK_CTRL_CLK_CTRL_PLL_PWR_ACK 26:26 /* R-EVF */
#define NV_NVLIPT_LNK_CTRL_CLK_CTRL_PLL_PWR_ACK_OFF 0x00000000 /* R-E-V */
#define NV_NVLIPT_LNK_CTRL_CLK_CTRL_PLL_PWR_ACK_ON 0x00000001 /* R---V */
#define NV_NVLIPT_LNK_CTRL_CLK_CTRL_PLL_HW_DISABLE 29:29 /* RWEVF */
#define NV_NVLIPT_LNK_CTRL_CLK_CTRL_PLL_HW_DISABLE_HW_CONTROL_ENABLED 0x00000000 /* RW--V */
#define NV_NVLIPT_LNK_CTRL_CLK_CTRL_PLL_HW_DISABLE_HW_CONTROL_DISABLED 0x00000001 /* RWE-V */
#define NV_NVLIPT_LNK_CTRL_CLK_CTRL_TXCLK_HW_DISABLE 30:30 /* RWEVF */
#define NV_NVLIPT_LNK_CTRL_CLK_CTRL_TXCLK_HW_DISABLE_HW_CONTROL_ENABLED 0x00000000 /* RW--V */
#define NV_NVLIPT_LNK_CTRL_CLK_CTRL_TXCLK_HW_DISABLE_HW_CONTROL_DISABLED 0x00000001 /* RWE-V */
#define NV_NVLIPT_LNK_CTRL_CLK_CTRL_RXCLK_HW_DISABLE 31:31 /* RWEVF */
#define NV_NVLIPT_LNK_CTRL_CLK_CTRL_RXCLK_HW_DISABLE_HW_CONTROL_ENABLED 0x00000000 /* RW--V */
#define NV_NVLIPT_LNK_CTRL_CLK_CTRL_RXCLK_HW_DISABLE_HW_CONTROL_DISABLED 0x00000001 /* RWE-V */
#define NV_NVLIPT_LNK_TOPOLOGY_REMOTE_CHIP_INFO 0x00000100 /* RW-4R */
#define NV_NVLIPT_LNK_TOPOLOGY_REMOTE_CHIP_INFO_CHIP_INFO 31:0 /* RWIVF */
#define NV_NVLIPT_LNK_TOPOLOGY_REMOTE_CHIP_INFO_CHIP_INFO_INIT 0x00000000 /* RWI-V */
#define NV_NVLIPT_LNK_TOPOLOGY_REMOTE_CHIP_TYPE 0x00000104 /* RW-4R */
#define NV_NVLIPT_LNK_TOPOLOGY_REMOTE_CHIP_TYPE_TYPE 7:0 /* RWIVF */
#define NV_NVLIPT_LNK_TOPOLOGY_REMOTE_CHIP_TYPE_TYPE_INIT 0x00000000 /* RWI-V */
#define NV_NVLIPT_LNK_TOPOLOGY_REMOTE_CHIP_TYPE_TYPE_NV2P1TUR 0x00000001 /* RW--V */
#define NV_NVLIPT_LNK_TOPOLOGY_REMOTE_CHIP_TYPE_TYPE_NV3P0AMP 0x00000002 /* RW--V */
#define NV_NVLIPT_LNK_TOPOLOGY_REMOTE_CHIP_TYPE_TYPE_NV3P0LRK 0x00000003 /* RW--V */
#define NV_NVLIPT_LNK_TOPOLOGY_REMOTE_CHIP_TYPE_TYPE_BB3P0P9P 0x00000004 /* RW--V */
#define NV_NVLIPT_LNK_TOPOLOGY_REMOTE_CHIP_TYPE_TYPE_BB3P0P10 0x00000005 /* RW--V */
#define NV_NVLIPT_LNK_TOPOLOGY_REMOTE_CHIP_TYPE_TYPE_NV3P1AMP 0x00000006 /* RW--V */
#define NV_NVLIPT_LNK_TOPOLOGY_REMOTE_CHIP_TYPE_TYPE_NV4P0HOP 0x00000007 /* RW--V */
#define NV_NVLIPT_LNK_TOPOLOGY_REMOTE_CHIP_TYPE_TYPE_NV4P0LAG 0x00000008 /* RW--V */
#define NV_NVLIPT_LNK_TOPOLOGY_REMOTE_CHIP_TYPE_TYPE_NV4P1GRC 0x00000009 /* RW--V */
#define NV_NVLIPT_LNK_TOPOLOGY_REMOTE_CHIP_TYPE_TYPE_NV4P2HOP 0x0000000a /* RW--V */
#define NV_NVLIPT_LNK_TOPOLOGY_REMOTE_CHIP_SID_LO 0x00000108 /* RW-4R */
#define NV_NVLIPT_LNK_TOPOLOGY_REMOTE_CHIP_SID_LO_SID_31_0 31:0 /* RWIVF */
#define NV_NVLIPT_LNK_TOPOLOGY_REMOTE_CHIP_SID_LO_SID_31_0_INIT 0x00000000 /* RWI-V */
#define NV_NVLIPT_LNK_TOPOLOGY_REMOTE_CHIP_SID_HI 0x0000010c /* RW-4R */
#define NV_NVLIPT_LNK_TOPOLOGY_REMOTE_CHIP_SID_HI_SID_63_32 31:0 /* RWIVF */
#define NV_NVLIPT_LNK_TOPOLOGY_REMOTE_CHIP_SID_HI_SID_63_32_INIT 0x00000000 /* RWI-V */
#define NV_NVLIPT_LNK_TOPOLOGY_REMOTE_LINK_INFO 0x00000110 /* RW-4R */
#define NV_NVLIPT_LNK_TOPOLOGY_REMOTE_LINK_INFO_LINK_NUMBER 7:0 /* RWIVF */
#define NV_NVLIPT_LNK_TOPOLOGY_REMOTE_LINK_INFO_LINK_NUMBER_INIT 0x000000ff /* RWI-V */
#define NV_NVLIPT_LNK_TOPOLOGY_LOCAL_LINK_INFO 0x00000114 /* R--4R */
#define NV_NVLIPT_LNK_TOPOLOGY_LOCAL_LINK_INFO_LINK_NUMBER 7:0 /* R-IVF */
#define NV_NVLIPT_LNK_TOPOLOGY_LOCAL_LINK_INFO_LINK_NUMBER_INIT 0x000000ff /* R-I-V */
#define NV_NVLIPT_LNK_ERR_STATUS_0 0x00000280 /* RW-4R */
#define NV_NVLIPT_LNK_ERR_STATUS_0_SLEEPWHILEACTIVELINK 0:0 /* RWIVF */
#define NV_NVLIPT_LNK_ERR_STATUS_0_SLEEPWHILEACTIVELINK__ONWRITE "oneToClear" /* */
#define NV_NVLIPT_LNK_ERR_STATUS_0_SLEEPWHILEACTIVELINK_NONE 0x00000000 /* RWI-V */
#define NV_NVLIPT_LNK_ERR_STATUS_0_SLEEPWHILEACTIVELINK_CLEAR 0x00000001 /* RW--V */
#define NV_NVLIPT_LNK_ERR_STATUS_0_ILLEGALLINKSTATEREQUEST 1:1 /* RWIVF */
#define NV_NVLIPT_LNK_ERR_STATUS_0_ILLEGALLINKSTATEREQUEST__ONWRITE "oneToClear" /* */
#define NV_NVLIPT_LNK_ERR_STATUS_0_ILLEGALLINKSTATEREQUEST_NONE 0x00000000 /* RWI-V */
#define NV_NVLIPT_LNK_ERR_STATUS_0_ILLEGALLINKSTATEREQUEST_CLEAR 0x00000001 /* RW--V */
#define NV_NVLIPT_LNK_ERR_STATUS_0_FAILEDMINIONREQUEST 2:2 /* RWIVF */
#define NV_NVLIPT_LNK_ERR_STATUS_0_FAILEDMINIONREQUEST__ONWRITE "oneToClear" /* */
#define NV_NVLIPT_LNK_ERR_STATUS_0_FAILEDMINIONREQUEST_NONE 0x00000000 /* RWI-V */
#define NV_NVLIPT_LNK_ERR_STATUS_0_FAILEDMINIONREQUEST_CLEAR 0x00000001 /* RW--V */
#define NV_NVLIPT_LNK_ERR_STATUS_0_RESERVEDREQUESTVALUE 3:3 /* RWIVF */
#define NV_NVLIPT_LNK_ERR_STATUS_0_RESERVEDREQUESTVALUE__ONWRITE "oneToClear" /* */
#define NV_NVLIPT_LNK_ERR_STATUS_0_RESERVEDREQUESTVALUE_NONE 0x00000000 /* RWI-V */
#define NV_NVLIPT_LNK_ERR_STATUS_0_RESERVEDREQUESTVALUE_CLEAR 0x00000001 /* RW--V */
#define NV_NVLIPT_LNK_ERR_STATUS_0_LINKSTATEWRITEWHILEBUSY 4:4 /* RWIVF */
#define NV_NVLIPT_LNK_ERR_STATUS_0_LINKSTATEWRITEWHILEBUSY__ONWRITE "oneToClear" /* */
#define NV_NVLIPT_LNK_ERR_STATUS_0_LINKSTATEWRITEWHILEBUSY_NONE 0x00000000 /* RWI-V */
#define NV_NVLIPT_LNK_ERR_STATUS_0_LINKSTATEWRITEWHILEBUSY_CLEAR 0x00000001 /* RW--V */
#define NV_NVLIPT_LNK_ERR_STATUS_0_LINK_STATE_REQUEST_TIMEOUT 5:5 /* RWIVF */
#define NV_NVLIPT_LNK_ERR_STATUS_0_LINK_STATE_REQUEST_TIMEOUT__ONWRITE "oneToClear" /* */
#define NV_NVLIPT_LNK_ERR_STATUS_0_LINK_STATE_REQUEST_TIMEOUT_NONE 0x00000000 /* RWI-V */
#define NV_NVLIPT_LNK_ERR_STATUS_0_LINK_STATE_REQUEST_TIMEOUT_CLEAR 0x00000001 /* RW--V */
#define NV_NVLIPT_LNK_ERR_STATUS_0_WRITE_TO_LOCKED_SYSTEM_REG_ERR 6:6 /* RWIVF */
#define NV_NVLIPT_LNK_ERR_STATUS_0_WRITE_TO_LOCKED_SYSTEM_REG_ERR__ONWRITE "oneToClear" /* */
#define NV_NVLIPT_LNK_ERR_STATUS_0_WRITE_TO_LOCKED_SYSTEM_REG_ERR_NONE 0x00000000 /* RWI-V */
#define NV_NVLIPT_LNK_ERR_STATUS_0_WRITE_TO_LOCKED_SYSTEM_REG_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_NVLIPT_LNK_ERR_STATUS_0_RSTSEQ_PHYCTL_TIMEOUT 7:7 /* RWIVF */
#define NV_NVLIPT_LNK_ERR_STATUS_0_RSTSEQ_PHYCTL_TIMEOUT__ONWRITE "oneToClear" /* */
#define NV_NVLIPT_LNK_ERR_STATUS_0_RSTSEQ_PHYCTL_TIMEOUT_NONE 0x00000000 /* RWI-V */
#define NV_NVLIPT_LNK_ERR_STATUS_0_RSTSEQ_PHYCTL_TIMEOUT_CLEAR 0x00000001 /* RW--V */
#define NV_NVLIPT_LNK_ERR_STATUS_0_RSTSEQ_CLKCTL_TIMEOUT 8:8 /* RWIVF */
#define NV_NVLIPT_LNK_ERR_STATUS_0_RSTSEQ_CLKCTL_TIMEOUT__ONWRITE "oneToClear" /* */
#define NV_NVLIPT_LNK_ERR_STATUS_0_RSTSEQ_CLKCTL_TIMEOUT_NONE 0x00000000 /* RWI-V */
#define NV_NVLIPT_LNK_ERR_STATUS_0_RSTSEQ_CLKCTL_TIMEOUT_CLEAR 0x00000001 /* RW--V */
#define NV_NVLIPT_LNK_ERR_STATUS_0_CLKCTL_REQUEST_TIMEOUT 9:9 /* RWIVF */
#define NV_NVLIPT_LNK_ERR_STATUS_0_CLKCTL_REQUEST_TIMEOUT__ONWRITE "oneToClear" /* */
#define NV_NVLIPT_LNK_ERR_STATUS_0_CLKCTL_REQUEST_TIMEOUT_NONE 0x00000000 /* RWI-V */
#define NV_NVLIPT_LNK_ERR_STATUS_0_CLKCTL_REQUEST_TIMEOUT_CLEAR 0x00000001 /* RW--V */
#define NV_NVLIPT_LNK_ERR_FATAL_REPORT_EN_0 0x00000288 /* RW-4R */
#define NV_NVLIPT_LNK_ERR_FATAL_REPORT_EN_0_SLEEPWHILEACTIVELINK 0:0 /* RWEVF */
#define NV_NVLIPT_LNK_ERR_FATAL_REPORT_EN_0_SLEEPWHILEACTIVELINK_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLIPT_LNK_ERR_FATAL_REPORT_EN_0_SLEEPWHILEACTIVELINK_ENABLE 0x00000001 /* RW--V */
#define NV_NVLIPT_LNK_ERR_FATAL_REPORT_EN_0_ILLEGALLINKSTATEREQUEST 1:1 /* RWEVF */
#define NV_NVLIPT_LNK_ERR_FATAL_REPORT_EN_0_ILLEGALLINKSTATEREQUEST_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLIPT_LNK_ERR_FATAL_REPORT_EN_0_ILLEGALLINKSTATEREQUEST_ENABLE 0x00000001 /* RW--V */
#define NV_NVLIPT_LNK_ERR_FATAL_REPORT_EN_0_FAILEDMINIONREQUEST 2:2 /* RWEVF */
#define NV_NVLIPT_LNK_ERR_FATAL_REPORT_EN_0_FAILEDMINIONREQUEST_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLIPT_LNK_ERR_FATAL_REPORT_EN_0_FAILEDMINIONREQUEST_ENABLE 0x00000001 /* RW--V */
#define NV_NVLIPT_LNK_ERR_FATAL_REPORT_EN_0_RESERVEDREQUESTVALUE 3:3 /* RWEVF */
#define NV_NVLIPT_LNK_ERR_FATAL_REPORT_EN_0_RESERVEDREQUESTVALUE_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLIPT_LNK_ERR_FATAL_REPORT_EN_0_RESERVEDREQUESTVALUE_ENABLE 0x00000001 /* RW--V */
#define NV_NVLIPT_LNK_ERR_FATAL_REPORT_EN_0_LINKSTATEWRITEWHILEBUSY 4:4 /* RWEVF */
#define NV_NVLIPT_LNK_ERR_FATAL_REPORT_EN_0_LINKSTATEWRITEWHILEBUSY_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLIPT_LNK_ERR_FATAL_REPORT_EN_0_LINKSTATEWRITEWHILEBUSY_ENABLE 0x00000001 /* RW--V */
#define NV_NVLIPT_LNK_ERR_FATAL_REPORT_EN_0_LINK_STATE_REQUEST_TIMEOUT 5:5 /* RWEVF */
#define NV_NVLIPT_LNK_ERR_FATAL_REPORT_EN_0_LINK_STATE_REQUEST_TIMEOUT_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLIPT_LNK_ERR_FATAL_REPORT_EN_0_LINK_STATE_REQUEST_TIMEOUT_ENABLE 0x00000001 /* RW--V */
#define NV_NVLIPT_LNK_ERR_FATAL_REPORT_EN_0_WRITE_TO_LOCKED_SYSTEM_REG_ERR 6:6 /* RWEVF */
#define NV_NVLIPT_LNK_ERR_FATAL_REPORT_EN_0_WRITE_TO_LOCKED_SYSTEM_REG_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLIPT_LNK_ERR_FATAL_REPORT_EN_0_WRITE_TO_LOCKED_SYSTEM_REG_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_NVLIPT_LNK_ERR_FATAL_REPORT_EN_0_RSTSEQ_PHYCTL_TIMEOUT 7:7 /* RWEVF */
#define NV_NVLIPT_LNK_ERR_FATAL_REPORT_EN_0_RSTSEQ_PHYCTL_TIMEOUT_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLIPT_LNK_ERR_FATAL_REPORT_EN_0_RSTSEQ_PHYCTL_TIMEOUT_ENABLE 0x00000001 /* RW--V */
#define NV_NVLIPT_LNK_ERR_FATAL_REPORT_EN_0_RSTSEQ_CLKCTL_TIMEOUT 8:8 /* RWEVF */
#define NV_NVLIPT_LNK_ERR_FATAL_REPORT_EN_0_RSTSEQ_CLKCTL_TIMEOUT_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLIPT_LNK_ERR_FATAL_REPORT_EN_0_RSTSEQ_CLKCTL_TIMEOUT_ENABLE 0x00000001 /* RW--V */
#define NV_NVLIPT_LNK_ERR_FATAL_REPORT_EN_0_CLKCTL_REQUEST_TIMEOUT 9:9 /* RWEVF */
#define NV_NVLIPT_LNK_ERR_FATAL_REPORT_EN_0_CLKCTL_REQUEST_TIMEOUT_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLIPT_LNK_ERR_FATAL_REPORT_EN_0_CLKCTL_REQUEST_TIMEOUT_ENABLE 0x00000001 /* RW--V */
#define NV_NVLIPT_LNK_ERR_NON_FATAL_REPORT_EN_0 0x0000028c /* RW-4R */
#define NV_NVLIPT_LNK_ERR_NON_FATAL_REPORT_EN_0_SLEEPWHILEACTIVELINK 0:0 /* RWEVF */
#define NV_NVLIPT_LNK_ERR_NON_FATAL_REPORT_EN_0_SLEEPWHILEACTIVELINK_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLIPT_LNK_ERR_NON_FATAL_REPORT_EN_0_SLEEPWHILEACTIVELINK_ENABLE 0x00000001 /* RW--V */
#define NV_NVLIPT_LNK_ERR_NON_FATAL_REPORT_EN_0_ILLEGALLINKSTATEREQUEST 1:1 /* RWEVF */
#define NV_NVLIPT_LNK_ERR_NON_FATAL_REPORT_EN_0_ILLEGALLINKSTATEREQUEST_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLIPT_LNK_ERR_NON_FATAL_REPORT_EN_0_ILLEGALLINKSTATEREQUEST_ENABLE 0x00000001 /* RW--V */
#define NV_NVLIPT_LNK_ERR_NON_FATAL_REPORT_EN_0_FAILEDMINIONREQUEST 2:2 /* RWEVF */
#define NV_NVLIPT_LNK_ERR_NON_FATAL_REPORT_EN_0_FAILEDMINIONREQUEST_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLIPT_LNK_ERR_NON_FATAL_REPORT_EN_0_FAILEDMINIONREQUEST_ENABLE 0x00000001 /* RW--V */
#define NV_NVLIPT_LNK_ERR_NON_FATAL_REPORT_EN_0_RESERVEDREQUESTVALUE 3:3 /* RWEVF */
#define NV_NVLIPT_LNK_ERR_NON_FATAL_REPORT_EN_0_RESERVEDREQUESTVALUE_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLIPT_LNK_ERR_NON_FATAL_REPORT_EN_0_RESERVEDREQUESTVALUE_ENABLE 0x00000001 /* RW--V */
#define NV_NVLIPT_LNK_ERR_NON_FATAL_REPORT_EN_0_LINKSTATEWRITEWHILEBUSY 4:4 /* RWEVF */
#define NV_NVLIPT_LNK_ERR_NON_FATAL_REPORT_EN_0_LINKSTATEWRITEWHILEBUSY_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLIPT_LNK_ERR_NON_FATAL_REPORT_EN_0_LINKSTATEWRITEWHILEBUSY_ENABLE 0x00000001 /* RW--V */
#define NV_NVLIPT_LNK_ERR_NON_FATAL_REPORT_EN_0_LINK_STATE_REQUEST_TIMEOUT 5:5 /* RWEVF */
#define NV_NVLIPT_LNK_ERR_NON_FATAL_REPORT_EN_0_LINK_STATE_REQUEST_TIMEOUT_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLIPT_LNK_ERR_NON_FATAL_REPORT_EN_0_LINK_STATE_REQUEST_TIMEOUT_ENABLE 0x00000001 /* RW--V */
#define NV_NVLIPT_LNK_ERR_NON_FATAL_REPORT_EN_0_WRITE_TO_LOCKED_SYSTEM_REG_ERR 6:6 /* RWEVF */
#define NV_NVLIPT_LNK_ERR_NON_FATAL_REPORT_EN_0_WRITE_TO_LOCKED_SYSTEM_REG_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLIPT_LNK_ERR_NON_FATAL_REPORT_EN_0_WRITE_TO_LOCKED_SYSTEM_REG_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_NVLIPT_LNK_ERR_NON_FATAL_REPORT_EN_0_RSTSEQ_PHYCTL_TIMEOUT 7:7 /* RWEVF */
#define NV_NVLIPT_LNK_ERR_NON_FATAL_REPORT_EN_0_RSTSEQ_PHYCTL_TIMEOUT_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLIPT_LNK_ERR_NON_FATAL_REPORT_EN_0_RSTSEQ_PHYCTL_TIMEOUT_ENABLE 0x00000001 /* RW--V */
#define NV_NVLIPT_LNK_ERR_NON_FATAL_REPORT_EN_0_RSTSEQ_CLKCTL_TIMEOUT 8:8 /* RWEVF */
#define NV_NVLIPT_LNK_ERR_NON_FATAL_REPORT_EN_0_RSTSEQ_CLKCTL_TIMEOUT_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLIPT_LNK_ERR_NON_FATAL_REPORT_EN_0_RSTSEQ_CLKCTL_TIMEOUT_ENABLE 0x00000001 /* RW--V */
#define NV_NVLIPT_LNK_ERR_NON_FATAL_REPORT_EN_0_CLKCTL_REQUEST_TIMEOUT 9:9 /* RWEVF */
#define NV_NVLIPT_LNK_ERR_NON_FATAL_REPORT_EN_0_CLKCTL_REQUEST_TIMEOUT_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLIPT_LNK_ERR_NON_FATAL_REPORT_EN_0_CLKCTL_REQUEST_TIMEOUT_ENABLE 0x00000001 /* RW--V */
#define NV_NVLIPT_LNK_ERR_CORRECTABLE_REPORT_EN_0 0x00000290 /* RW-4R */
#define NV_NVLIPT_LNK_ERR_FIRST_0 0x0000029c /* RW-4R */
#define NV_NVLIPT_LNK_ERR_FIRST_0_SLEEPWHILEACTIVELINK 0:0 /* RWIVF */
#define NV_NVLIPT_LNK_ERR_FIRST_0_SLEEPWHILEACTIVELINK__ONWRITE "oneToClear" /* */
#define NV_NVLIPT_LNK_ERR_FIRST_0_SLEEPWHILEACTIVELINK_NONE 0x00000000 /* RWI-V */
#define NV_NVLIPT_LNK_ERR_FIRST_0_SLEEPWHILEACTIVELINK_CLEAR 0x00000001 /* RW--V */
#define NV_NVLIPT_LNK_ERR_FIRST_0_ILLEGALLINKSTATEREQUEST 1:1 /* RWIVF */
#define NV_NVLIPT_LNK_ERR_FIRST_0_ILLEGALLINKSTATEREQUEST__ONWRITE "oneToClear" /* */
#define NV_NVLIPT_LNK_ERR_FIRST_0_ILLEGALLINKSTATEREQUEST_NONE 0x00000000 /* RWI-V */
#define NV_NVLIPT_LNK_ERR_FIRST_0_ILLEGALLINKSTATEREQUEST_CLEAR 0x00000001 /* RW--V */
#define NV_NVLIPT_LNK_ERR_FIRST_0_FAILEDMINIONREQUEST 2:2 /* RWIVF */
#define NV_NVLIPT_LNK_ERR_FIRST_0_FAILEDMINIONREQUEST__ONWRITE "oneToClear" /* */
#define NV_NVLIPT_LNK_ERR_FIRST_0_FAILEDMINIONREQUEST_NONE 0x00000000 /* RWI-V */
#define NV_NVLIPT_LNK_ERR_FIRST_0_FAILEDMINIONREQUEST_CLEAR 0x00000001 /* RW--V */
#define NV_NVLIPT_LNK_ERR_FIRST_0_RESERVEDREQUESTVALUE 3:3 /* RWIVF */
#define NV_NVLIPT_LNK_ERR_FIRST_0_RESERVEDREQUESTVALUE__ONWRITE "oneToClear" /* */
#define NV_NVLIPT_LNK_ERR_FIRST_0_RESERVEDREQUESTVALUE_NONE 0x00000000 /* RWI-V */
#define NV_NVLIPT_LNK_ERR_FIRST_0_RESERVEDREQUESTVALUE_CLEAR 0x00000001 /* RW--V */
#define NV_NVLIPT_LNK_ERR_FIRST_0_LINKSTATEWRITEWHILEBUSY 4:4 /* RWIVF */
#define NV_NVLIPT_LNK_ERR_FIRST_0_LINKSTATEWRITEWHILEBUSY__ONWRITE "oneToClear" /* */
#define NV_NVLIPT_LNK_ERR_FIRST_0_LINKSTATEWRITEWHILEBUSY_NONE 0x00000000 /* RWI-V */
#define NV_NVLIPT_LNK_ERR_FIRST_0_LINKSTATEWRITEWHILEBUSY_CLEAR 0x00000001 /* RW--V */
#define NV_NVLIPT_LNK_ERR_FIRST_0_LINK_STATE_REQUEST_TIMEOUT 5:5 /* RWIVF */
#define NV_NVLIPT_LNK_ERR_FIRST_0_LINK_STATE_REQUEST_TIMEOUT__ONWRITE "oneToClear" /* */
#define NV_NVLIPT_LNK_ERR_FIRST_0_LINK_STATE_REQUEST_TIMEOUT_NONE 0x00000000 /* RWI-V */
#define NV_NVLIPT_LNK_ERR_FIRST_0_LINK_STATE_REQUEST_TIMEOUT_CLEAR 0x00000001 /* RW--V */
#define NV_NVLIPT_LNK_ERR_FIRST_0_WRITE_TO_LOCKED_SYSTEM_REG_ERR 6:6 /* RWIVF */
#define NV_NVLIPT_LNK_ERR_FIRST_0_WRITE_TO_LOCKED_SYSTEM_REG_ERR__ONWRITE "oneToClear" /* */
#define NV_NVLIPT_LNK_ERR_FIRST_0_WRITE_TO_LOCKED_SYSTEM_REG_ERR_NONE 0x00000000 /* RWI-V */
#define NV_NVLIPT_LNK_ERR_FIRST_0_WRITE_TO_LOCKED_SYSTEM_REG_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_NVLIPT_LNK_ERR_FIRST_0_RSTSEQ_PHYCTL_TIMEOUT 7:7 /* RWIVF */
#define NV_NVLIPT_LNK_ERR_FIRST_0_RSTSEQ_PHYCTL_TIMEOUT__ONWRITE "oneToClear" /* */
#define NV_NVLIPT_LNK_ERR_FIRST_0_RSTSEQ_PHYCTL_TIMEOUT_NONE 0x00000000 /* RWI-V */
#define NV_NVLIPT_LNK_ERR_FIRST_0_RSTSEQ_PHYCTL_TIMEOUT_CLEAR 0x00000001 /* RW--V */
#define NV_NVLIPT_LNK_ERR_FIRST_0_RSTSEQ_CLKCTL_TIMEOUT 8:8 /* RWIVF */
#define NV_NVLIPT_LNK_ERR_FIRST_0_RSTSEQ_CLKCTL_TIMEOUT__ONWRITE "oneToClear" /* */
#define NV_NVLIPT_LNK_ERR_FIRST_0_RSTSEQ_CLKCTL_TIMEOUT_NONE 0x00000000 /* RWI-V */
#define NV_NVLIPT_LNK_ERR_FIRST_0_RSTSEQ_CLKCTL_TIMEOUT_CLEAR 0x00000001 /* RW--V */
#define NV_NVLIPT_LNK_ERR_FIRST_0_CLKCTL_REQUEST_TIMEOUT 9:9 /* RWIVF */
#define NV_NVLIPT_LNK_ERR_FIRST_0_CLKCTL_REQUEST_TIMEOUT__ONWRITE "oneToClear" /* */
#define NV_NVLIPT_LNK_ERR_FIRST_0_CLKCTL_REQUEST_TIMEOUT_NONE 0x00000000 /* RWI-V */
#define NV_NVLIPT_LNK_ERR_FIRST_0_CLKCTL_REQUEST_TIMEOUT_CLEAR 0x00000001 /* RW--V */
#define NV_NVLIPT_LNK_INTR_CONTROL_LINK 0x00000300 /* RW-4R */
#define NV_NVLIPT_LNK_INTR_CONTROL_LINK_INT0_EN 0:0 /* RWEVF */
#define NV_NVLIPT_LNK_INTR_CONTROL_LINK_INT0_EN_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLIPT_LNK_INTR_CONTROL_LINK_INT0_EN_ENABLE 0x00000001 /* RW--V */
#define NV_NVLIPT_LNK_INTR_CONTROL_LINK_INT1_EN 1:1 /* RWEVF */
#define NV_NVLIPT_LNK_INTR_CONTROL_LINK_INT1_EN_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLIPT_LNK_INTR_CONTROL_LINK_INT1_EN_ENABLE 0x00000001 /* RW--V */
#define NV_NVLIPT_LNK_INTR_STATUS 0x00000304 /* RW-4R */
#define NV_NVLIPT_LNK_INTR_STATUS_LINKSTATEREQUESTREADYSET 0:0 /* RWEVF */
#define NV_NVLIPT_LNK_INTR_STATUS_LINKSTATEREQUESTREADYSET__ONWRITE "oneToClear" /* */
#define NV_NVLIPT_LNK_INTR_STATUS_LINKSTATEREQUESTREADYSET_PENDING 0x00000001 /* RW--V */
#define NV_NVLIPT_LNK_INTR_STATUS_LINKSTATEREQUESTREADYSET_CLEAR 0x00000000 /* RW--V */
#define NV_NVLIPT_LNK_INTR_STATUS_LINKSTATEREQUESTREADYSET_INIT 0x00000000 /* RWE-V */
#define NV_NVLIPT_LNK_INTR_STATUS_MINIONREQUEST 1:1 /* RWEVF */
#define NV_NVLIPT_LNK_INTR_STATUS_MINIONREQUEST__ONWRITE "oneToClear" /* */
#define NV_NVLIPT_LNK_INTR_STATUS_MINIONREQUEST_PENDING 0x00000001 /* RW--V */
#define NV_NVLIPT_LNK_INTR_STATUS_MINIONREQUEST_CLEAR 0x00000000 /* RW--V */
#define NV_NVLIPT_LNK_INTR_STATUS_MINIONREQUEST_INIT 0x00000000 /* RWE-V */
#define NV_NVLIPT_LNK_INTR_INT0_EN 0x00000308 /* RW-4R */
#define NV_NVLIPT_LNK_INTR_INT0_EN_LINKSTATEREQUESTREADYSET 0:0 /* RWEVF */
#define NV_NVLIPT_LNK_INTR_INT0_EN_LINKSTATEREQUESTREADYSET_PENDING 0x00000001 /* RW--V */
#define NV_NVLIPT_LNK_INTR_INT0_EN_LINKSTATEREQUESTREADYSET_DISABLE 0x00000000 /* RW--V */
#define NV_NVLIPT_LNK_INTR_INT0_EN_LINKSTATEREQUESTREADYSET_INIT 0x00000000 /* RWE-V */
#define NV_NVLIPT_LNK_INTR_INT0_EN_MINIONREQUEST 1:1 /* RWEVF */
#define NV_NVLIPT_LNK_INTR_INT0_EN_MINIONREQUEST_PENDING 0x00000001 /* RW--V */
#define NV_NVLIPT_LNK_INTR_INT0_EN_MINIONREQUEST_DISABLE 0x00000000 /* RW--V */
#define NV_NVLIPT_LNK_INTR_INT0_EN_MINIONREQUEST_INIT 0x00000000 /* RWE-V */
#define NV_NVLIPT_LNK_INTR_INT1_EN 0x0000030c /* RW-4R */
#define NV_NVLIPT_LNK_INTR_INT1_EN_LINKSTATEREQUESTREADYSET 0:0 /* RWEVF */
#define NV_NVLIPT_LNK_INTR_INT1_EN_LINKSTATEREQUESTREADYSET_ENABLE 0x00000001 /* RW--V */
#define NV_NVLIPT_LNK_INTR_INT1_EN_LINKSTATEREQUESTREADYSET_DISABLE 0x00000000 /* RW--V */
#define NV_NVLIPT_LNK_INTR_INT1_EN_LINKSTATEREQUESTREADYSET_INIT 0x00000000 /* RWE-V */
#define NV_NVLIPT_LNK_INTR_INT1_EN_MINIONREQUEST 1:1 /* RWEVF */
#define NV_NVLIPT_LNK_INTR_INT1_EN_MINIONREQUEST_ENABLE 0x00000001 /* RW--V */
#define NV_NVLIPT_LNK_INTR_INT1_EN_MINIONREQUEST_DISABLE 0x00000000 /* RW--V */
#define NV_NVLIPT_LNK_INTR_INT1_EN_MINIONREQUEST_INIT 0x00000000 /* RWE-V */
#define NV_NVLIPT_LNK_INTR_MINION_STATUS 0x00000314 /* RW-4R */
#define NV_NVLIPT_LNK_RESET_RSTSEQ_LINK_RESET 0x00000380 /* RW-4R */
#define NV_NVLIPT_LNK_RESET_RSTSEQ_LINK_RESET_LINK_RESET 0:0 /* RWEVF */
#define NV_NVLIPT_LNK_RESET_RSTSEQ_LINK_RESET_LINK_RESET_DEASSERT 0x00000000 /* RW--V */
#define NV_NVLIPT_LNK_RESET_RSTSEQ_LINK_RESET_LINK_RESET_ASSERT 0x00000001 /* RWE-V */
#define NV_NVLIPT_LNK_RESET_RSTSEQ_LINK_RESET_LINK_RESET_STATUS 1:1 /* R-EVF */
#define NV_NVLIPT_LNK_RESET_RSTSEQ_LINK_RESET_LINK_RESET_STATUS_DEASSERTED 0x00000000 /* R---V */
#define NV_NVLIPT_LNK_RESET_RSTSEQ_LINK_RESET_LINK_RESET_STATUS_ASSERTED 0x00000001 /* R-E-V */
#define NV_NVLIPT_LNK_PWRM_CTRL 0x00000400 /* RW-4R */
#define NV_NVLIPT_LNK_PWRM_CTRL_L1_CURRENT_STATE 2:2 /* R-EVF */
#define NV_NVLIPT_LNK_PWRM_CTRL_L1_CURRENT_STATE_L1 0x00000001 /* R---V */
#define NV_NVLIPT_LNK_PWRM_CTRL_L1_CURRENT_STATE_NOT_L1 0x00000000 /* R-E-V */
#define NV_NVLIPT_LNK_PWRM_CTRL_L1_REMOTE_DESIRED 3:3 /* R-EVF */
#define NV_NVLIPT_LNK_PWRM_CTRL_L1_REMOTE_DESIRED_L1 0x00000001 /* R---V */
#define NV_NVLIPT_LNK_PWRM_CTRL_L1_REMOTE_DESIRED_ACTIVE 0x00000000 /* R-E-V */
#define NV_NVLIPT_LNK_PWRM_CTRL_L1_HARDWARE_DESIRED 4:4 /* R-EVF */
#define NV_NVLIPT_LNK_PWRM_CTRL_L1_HARDWARE_DESIRED_L1 0x00000001 /* R---V */
#define NV_NVLIPT_LNK_PWRM_CTRL_L1_HARDWARE_DESIRED_ACTIVE 0x00000000 /* R-E-V */
#define NV_NVLIPT_LNK_PWRM_CTRL_L1_SOFTWARE_DESIRED 8:8 /* RWEVF */
#define NV_NVLIPT_LNK_PWRM_CTRL_L1_SOFTWARE_DESIRED_L1 0x00000001 /* RW--V */
#define NV_NVLIPT_LNK_PWRM_CTRL_L1_SOFTWARE_DESIRED_ACTIVE 0x00000000 /* RWE-V */
#define NV_NVLIPT_LNK_PWRM_CTRL_L1_HARDWARE_DISABLE 9:9 /* RWEVF */
#define NV_NVLIPT_LNK_PWRM_CTRL_L1_HARDWARE_DISABLE_HW_MONITOR_DISABLE 0x00000001 /* RW--V */
#define NV_NVLIPT_LNK_PWRM_CTRL_L1_HARDWARE_DISABLE_HW_MONITOR_ENABLED 0x00000000 /* RWE-V */
#define NV_NVLIPT_LNK_PWRM_CTRL_L1_COUNT_ENABLE 10:10 /* RWEVF */
#define NV_NVLIPT_LNK_PWRM_CTRL_L1_COUNT_ENABLE_ENABLE 0x00000001 /* RW--V */
#define NV_NVLIPT_LNK_PWRM_CTRL_L1_COUNT_ENABLE_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLIPT_LNK_PWRM_CTRL_L1D_ENABLE 11:11 /* RWEVF */
#define NV_NVLIPT_LNK_PWRM_CTRL_L1D_ENABLE_ENABLE 0x00000001 /* RW--V */
#define NV_NVLIPT_LNK_PWRM_CTRL_L1D_ENABLE_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLIPT_LNK_PWRM_L1_ENTER_THRESHOLD 0x0000040c /* RW-4R */
#define NV_NVLIPT_LNK_PWRM_L1_ENTER_THRESHOLD_THRESHOLD 12:0 /* RWEVF */
#define NV_NVLIPT_LNK_PWRM_L1_ENTER_THRESHOLD_THRESHOLD_INIT 0x000001ff /* RWE-V */
#define NV_NVLIPT_LNK_CTRL_LINK_STATE_REQUEST 0x00000480 /* RW-4R */
#define NV_NVLIPT_LNK_CTRL_LINK_STATE_REQUEST_REQUEST 3:0 /* RWEVF */
#define NV_NVLIPT_LNK_CTRL_LINK_STATE_REQUEST_REQUEST_NOP 0x00000000 /* RWE-V */
#define NV_NVLIPT_LNK_CTRL_LINK_STATE_REQUEST_REQUEST_ACTIVE 0x00000001 /* RW--V */
#define NV_NVLIPT_LNK_CTRL_LINK_STATE_REQUEST_REQUEST_L2 0x00000002 /* RW--V */
#define NV_NVLIPT_LNK_CTRL_LINK_STATE_REQUEST_REQUEST_EMPTY 0x00000008 /* RW--V */
#define NV_NVLIPT_LNK_CTRL_LINK_STATE_REQUEST_REQUEST_RESET 0x00000009 /* RW--V */
#define NV_NVLIPT_LNK_CTRL_LINK_STATE_REQUEST_REQUEST_SHUTDOWN 0x0000000d /* RW--V */
#define NV_NVLIPT_LNK_CTRL_LINK_STATE_REQUEST_STATUS 15:8 /* R-EVF */
#define NV_NVLIPT_LNK_CTRL_LINK_STATE_REQUEST_STATUS_INIT 0x00000000 /* R-E-V */
#define NV_NVLIPT_LNK_CTRL_LINK_STATE_REQUEST_STATUS_REQUEST_SUCCESSFUL 0x00000001 /* R---V */
#define NV_NVLIPT_LNK_CTRL_LINK_STATE_REQUEST_STATUS_ILLEGAL_STATE_REQUEST 0x00000002 /* R---V */
#define NV_NVLIPT_LNK_CTRL_LINK_STATE_REQUEST_STATUS_RESET_SEQ_TIMEOUT 0x00000003 /* R---V */
#define NV_NVLIPT_LNK_CTRL_LINK_STATE_REQUEST_STATUS_MINION_REQUEST_NOT_ENABLED 0x00000004 /* R---V */
#define NV_NVLIPT_LNK_CTRL_LINK_STATE_REQUEST_STATUS_REQUEST_TIMEOUT 0x00000005 /* R---V */
#define NV_NVLIPT_LNK_CTRL_LINK_STATE_REQUEST_STATUS_MINION_REQUEST_FAIL 0x00000080 /* R---V */
#define NV_NVLIPT_LNK_CTRL_LINK_STATE_REQUEST_STATUS_MINION_REQUEST_FAIL_FATAL 0x000000ff /* R---V */
#define NV_NVLIPT_LNK_CTRL_LINK_STATE_REQUEST_STATUS_ACTIVE_FAIL_BAD_STATE 0x00000081 /* R---V */
#define NV_NVLIPT_LNK_CTRL_LINK_STATE_REQUEST_STATUS_ACTIVE_FAIL_RXDET 0x00000082 /* R---V */
#define NV_NVLIPT_LNK_CTRL_LINK_STATE_REQUEST_STATUS_ACTIVE_FAIL_NEGOTIATION 0x00000083 /* R---V */
#define NV_NVLIPT_LNK_CTRL_LINK_STATE_REQUEST_STATUS_ACTIVE_FAIL_HS 0x00000084 /* R---V */
#define NV_NVLIPT_LNK_CTRL_LINK_STATE_REQUEST_ERR 30:30 /* R-EVF */
#define NV_NVLIPT_LNK_CTRL_LINK_STATE_REQUEST_ERR_NOERR 0x00000000 /* R-E-V */
#define NV_NVLIPT_LNK_CTRL_LINK_STATE_REQUEST_ERR_ERR 0x00000001 /* R---V */
#define NV_NVLIPT_LNK_CTRL_LINK_STATE_REQUEST_READY 31:31 /* R-EVF */
#define NV_NVLIPT_LNK_CTRL_LINK_STATE_REQUEST_READY_INIT 0x00000001 /* R-E-V */
#define NV_NVLIPT_LNK_CTRL_LINK_STATE_STATUS 0x00000484 /* R--4R */
#define NV_NVLIPT_LNK_CTRL_LINK_STATE_STATUS_CURRENTLINKSTATE 3:0 /* R-EVF */
#define NV_NVLIPT_LNK_CTRL_LINK_STATE_STATUS_CURRENTLINKSTATE_ACTIVE 0x00000001 /* R---V */
#define NV_NVLIPT_LNK_CTRL_LINK_STATE_STATUS_CURRENTLINKSTATE_L2 0x00000002 /* R---V */
#define NV_NVLIPT_LNK_CTRL_LINK_STATE_STATUS_CURRENTLINKSTATE_ACTIVE_PENDING 0x00000005 /* R---V */
#define NV_NVLIPT_LNK_CTRL_LINK_STATE_STATUS_CURRENTLINKSTATE_EMPTY 0x00000008 /* R---V */
#define NV_NVLIPT_LNK_CTRL_LINK_STATE_STATUS_CURRENTLINKSTATE_RESET 0x00000009 /* R-E-V */
#define NV_NVLIPT_LNK_CTRL_LINK_STATE_STATUS_CURRENTLINKSTATE_SHUTDOWN 0x0000000d /* R---V */
#define NV_NVLIPT_LNK_CTRL_LINK_STATE_STATUS_CURRENTLINKSTATE_CONTAIN 0x0000000e /* R---V */
#define NV_NVLIPT_LNK_CTRL_LINK_STATE_STATUS_CURRENTLINKSTATE_DISABLE 0x0000000f /* R---V */
#define NV_NVLIPT_LNK_CTRL_LINK_STATE_STATUS_TXTLBUFFEREMPTY 8:8 /* R-EVF */
#define NV_NVLIPT_LNK_CTRL_LINK_STATE_STATUS_TXTLBUFFEREMPTY_INIT 0x00000000 /* R-E-V */
#define NV_NVLIPT_LNK_CTRL_LINK_STATE_STATUS_TXREPLAYBUFFEREMPTY 9:9 /* R-EVF */
#define NV_NVLIPT_LNK_CTRL_LINK_STATE_STATUS_TXREPLAYBUFFEREMPTY_INIT 0x00000000 /* R-E-V */
#define NV_NVLIPT_LNK_CTRL_LINK_STATE_STATUS_RXTLBUFFEREMPTY 11:11 /* R-EVF */
#define NV_NVLIPT_LNK_CTRL_LINK_STATE_STATUS_RXTLBUFFEREMPTY_INIT 0x00000000 /* R-E-V */
#define NV_NVLIPT_LNK_CTRL_LINK_STATE_STATUS_RMTTXBUFFEREMPTY 13:13 /* R-EVF */
#define NV_NVLIPT_LNK_CTRL_LINK_STATE_STATUS_RMTTXBUFFEREMPTY_INIT 0x00000000 /* R-E-V */
#define NV_NVLIPT_LNK_CTRL_LINK_STATE_STATUS_RMTRXBUFFEREMPTY 14:14 /* R-EVF */
#define NV_NVLIPT_LNK_CTRL_LINK_STATE_STATUS_RMTRXBUFFEREMPTY_INIT 0x00000000 /* R-E-V */
#define NV_NVLIPT_LNK_DEBUG_CLEAR 0x00000504 /* RW-4R */
#define NV_NVLIPT_LNK_DEBUG_CLEAR_CLEAR 0:0 /* RWIVF */
#define NV_NVLIPT_LNK_DEBUG_CLEAR_CLEAR_ASSERT 0x00000001 /* RW--V */
#define NV_NVLIPT_LNK_DEBUG_CLEAR_CLEAR_DEASSERT 0x00000000 /* RWI-V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CLK_CTRL 0x0000060c /* RW-4R */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CLK_CTRL_LINE_RATE 15:8 /* RWIVF */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CLK_CTRL_LINE_RATE_100_00000_GBPS 0x00000009 /* RW--V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CLK_CTRL_LINE_RATE_106_25000_GBPS 0x0000000a /* RWI-V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CLK_CTRL_LINE_RATE_ILLEGAL_LINE_RATE 0x000000ff /* RW--V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL 0x00000618 /* RW-4R */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL_AC_DC_MODE 0:0 /* RWIVF */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL_AC_DC_MODE_AC 0x00000001 /* RWI-V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL_AC_DC_MODE_DC 0x00000000 /* RW--V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL_LINE_CODE_MODE 2:1 /* RWIVF */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL_LINE_CODE_MODE_NRZ 0x00000000 /* RW--V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL_LINE_CODE_MODE_PAM4 0x00000003 /* RWI-V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL_RECEIVER_DETECT_ENABLE 3:3 /* RWIVF */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL_RECEIVER_DETECT_ENABLE_ENABLE 0x00000001 /* RWI-V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL_RECEIVER_DETECT_ENABLE_DISABLE 0x00000000 /* RW--V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL_BLOCK_CODE_MODE 7:6 /* RWIVF */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL_BLOCK_CODE_MODE_OFF 0x00000000 /* RW--V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL_BLOCK_CODE_MODE_ECC89_ENABLED 0x00000001 /* RWI-V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL_TXTRAIN_FOM_FORMAT 10:8 /* RWIVF */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL_TXTRAIN_FOM_FORMAT_INIT 0x00000005 /* RWI-V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL_TXTRAIN_FOM_FORMAT_FOMA 0x00000001 /* RW--V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL_TXTRAIN_FOM_FORMAT_FOMB 0x00000002 /* RW--V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL_TXTRAIN_FOM_FORMAT_FOMC 0x00000004 /* RW--V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL_TXTRAIN_OPTIMIZATION_ALGORITHM 18:11 /* RWIVF */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL_TXTRAIN_OPTIMIZATION_ALGORITHM_INIT 0x00000017 /* RWI-V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL_TXTRAIN_OPTIMIZATION_ALGORITHM_A0 0x00000001 /* RW--V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL_TXTRAIN_OPTIMIZATION_ALGORITHM_A1 0x00000002 /* RW--V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL_TXTRAIN_OPTIMIZATION_ALGORITHM_A2 0x00000004 /* RW--V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL_TXTRAIN_OPTIMIZATION_ALGORITHM_A3 0x00000008 /* RW--V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL_TXTRAIN_OPTIMIZATION_ALGORITHM_A4 0x00000010 /* RW--V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL_TXTRAIN_OPTIMIZATION_ALGORITHM_A5 0x00000020 /* RW--V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL_TXTRAIN_OPTIMIZATION_ALGORITHM_A6 0x00000040 /* RW--V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL_TXTRAIN_OPTIMIZATION_ALGORITHM_A7 0x00000080 /* RW--V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL_TXTRAIN_ADJUSTMENT_ALGORITHM 23:19 /* RWIVF */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL_TXTRAIN_ADJUSTMENT_ALGORITHM_B0 0x00000001 /* RWI-V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL_TXTRAIN_ADJUSTMENT_ALGORITHM_B1 0x00000002 /* RW--V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL_TXTRAIN_ADJUSTMENT_ALGORITHM_B2 0x00000004 /* RW--V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL_TXTRAIN_ADJUSTMENT_ALGORITHM_B3 0x00000008 /* RW--V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL_TXTRAIN_MINIMUM_TRAIN_TIME_MANTISSA 27:24 /* RWIVF */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL_TXTRAIN_MINIMUM_TRAIN_TIME_MANTISSA_INIT 0x00000002 /* RWI-V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL_TXTRAIN_MINIMUM_TRAIN_TIME_EXPONENT 31:28 /* RWIVF */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL_TXTRAIN_MINIMUM_TRAIN_TIME_EXPONENT_INIT 0x00000003 /* RWI-V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2 0x00000624 /* RW-4R */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_RESTORE_PHY_TRAINING_PARAMS 0:0 /* RWIVF */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_RESTORE_PHY_TRAINING_PARAMS_ENABLE 0x00000001 /* RWI-V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_RESTORE_PHY_TRAINING_PARAMS_DISABLE 0x00000000 /* RW--V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_ALI_ENABLE 1:1 /* RWIVF */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_ALI_ENABLE_ENABLE 0x00000001 /* RWI-V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_ALI_ENABLE_DISABLE 0x00000000 /* RW--V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_L1_MINIMUM_RECALIBRATION_TIME_MANTISSA 6:2 /* RWIVF */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_L1_MINIMUM_RECALIBRATION_TIME_MANTISSA_INIT 0x00000001 /* RWI-V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_L1_MINIMUM_RECALIBRATION_TIME_EXPONENT 11:8 /* RWIVF */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_L1_MINIMUM_RECALIBRATION_TIME_EXPONENT_INIT 0x00000004 /* RWI-V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_L1_MAXIMUM_RECALIBRATION_PERIOD_MANTISSA 17:13 /* RWIVF */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_L1_MAXIMUM_RECALIBRATION_PERIOD_MANTISSA_INIT 0x00000019 /* RWI-V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_L1_MAXIMUM_RECALIBRATION_PERIOD_EXPONENT 22:19 /* RWIVF */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_L1_MAXIMUM_RECALIBRATION_PERIOD_EXPONENT_INIT 0x00000004 /* RWI-V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_DISABLE_UPHY_MICROCODE_LOAD 24:24 /* RWIVF */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_DISABLE_UPHY_MICROCODE_LOAD_UPHY_MICROCODE_LOAD_DISABLED 0x00000001 /* RW--V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_DISABLE_UPHY_MICROCODE_LOAD_UPHY_MICROCODE_LOAD_ENABLED 0x00000000 /* RWI-V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_CHANNEL_TYPE 28:25 /* RWIVF */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_CHANNEL_TYPE_GENERIC 0x00000000 /* RWI-V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_CHANNEL_TYPE_ACTIVE_0 0x00000004 /* RW--V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_CHANNEL_TYPE_ACTIVE_1 0x00000005 /* RW--V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_CHANNEL_TYPE_ACTIVE_CABLE_0 0x00000008 /* RW--V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_CHANNEL_TYPE_ACTIVE_CABLE_1 0x00000009 /* RW--V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_CHANNEL_TYPE_OPTICAL_CABLE_0 0x0000000c /* RW--V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_CHANNEL_TYPE_OPTICAL_CABLE_1 0x0000000d /* RW--V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_CHANNEL_TYPE_DIRECT_0 0x0000000e /* RW--V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_RESERVED_29 29:29 /* RWIVF */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_RESERVED_29_INIT 0x00000000 /* RWI-V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_RESERVED_30 30:30 /* RWIVF */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_RESERVED_30_INIT 0x00000000 /* RWI-V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_RESERVED_31 31:31 /* RWIVF */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_RESERVED_31_INIT 0x00000000 /* RWI-V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_LOCK 0x00000628 /* RW-4R */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_LOCK_RESTORE_PHY_TRAINING_PARAMS 0:0 /* RWIVF */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_LOCK_RESTORE_PHY_TRAINING_PARAMS__ONWRITE "oneToSet" /* */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_LOCK_RESTORE_PHY_TRAINING_PARAMS_UNLOCKED 0x00000000 /* RWI-V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_LOCK_RESTORE_PHY_TRAINING_PARAMS_LOCKED 0x00000001 /* RW--V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_LOCK_ALI_ENABLE 1:1 /* RWIVF */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_LOCK_ALI_ENABLE__ONWRITE "oneToSet" /* */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_LOCK_ALI_ENABLE_UNLOCKED 0x00000000 /* RWI-V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_LOCK_ALI_ENABLE_LOCKED 0x00000001 /* RW--V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_LOCK_L1_MINIMUM_RECALIBRATION_TIME_MANTISSA 2:2 /* RWIVF */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_LOCK_L1_MINIMUM_RECALIBRATION_TIME_MANTISSA__ONWRITE "oneToSet" /* */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_LOCK_L1_MINIMUM_RECALIBRATION_TIME_MANTISSA_UNLOCKED 0x00000000 /* RWI-V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_LOCK_L1_MINIMUM_RECALIBRATION_TIME_MANTISSA_LOCKED 0x00000001 /* RW--V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_LOCK_L1_MINIMUM_RECALIBRATION_TIME_EXPONENT 3:3 /* RWIVF */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_LOCK_L1_MINIMUM_RECALIBRATION_TIME_EXPONENT__ONWRITE "oneToSet" /* */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_LOCK_L1_MINIMUM_RECALIBRATION_TIME_EXPONENT_UNLOCKED 0x00000000 /* RWI-V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_LOCK_L1_MINIMUM_RECALIBRATION_TIME_EXPONENT_LOCKED 0x00000001 /* RW--V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_LOCK_L1_MAXIMUM_RECALIBRATION_PERIOD_MANTISSA 4:4 /* RWIVF */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_LOCK_L1_MAXIMUM_RECALIBRATION_PERIOD_MANTISSA__ONWRITE "oneToSet" /* */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_LOCK_L1_MAXIMUM_RECALIBRATION_PERIOD_MANTISSA_UNLOCKED 0x00000000 /* RWI-V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_LOCK_L1_MAXIMUM_RECALIBRATION_PERIOD_MANTISSA_LOCKED 0x00000001 /* RW--V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_LOCK_L1_MAXIMUM_RECALIBRATION_PERIOD_EXPONENT 5:5 /* RWIVF */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_LOCK_L1_MAXIMUM_RECALIBRATION_PERIOD_EXPONENT__ONWRITE "oneToSet" /* */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_LOCK_L1_MAXIMUM_RECALIBRATION_PERIOD_EXPONENT_UNLOCKED 0x00000000 /* RWI-V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_LOCK_L1_MAXIMUM_RECALIBRATION_PERIOD_EXPONENT_LOCKED 0x00000001 /* RW--V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_LOCK_DISABLE_UPHY_MICROCODE_LOAD 6:6 /* RWIVF */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_LOCK_DISABLE_UPHY_MICROCODE_LOAD__ONWRITE "oneToSet" /* */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_LOCK_DISABLE_UPHY_MICROCODE_LOAD_UNLOCKED 0x00000000 /* RW--V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_LOCK_DISABLE_UPHY_MICROCODE_LOAD_LOCKED 0x00000001 /* RWI-V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_LOCK_CHANNEL_TYPE 7:7 /* RWIVF */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_LOCK_CHANNEL_TYPE__ONWRITE "oneToSet" /* */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_LOCK_CHANNEL_TYPE_UNLOCKED 0x00000000 /* RW--V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_LOCK_CHANNEL_TYPE_LOCKED 0x00000001 /* RWI-V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_LOCK_RESERVED_29 8:8 /* RWIVF */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_LOCK_RESERVED_29__ONWRITE "oneToSet" /* */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_LOCK_RESERVED_29_UNLOCKED 0x00000000 /* RWI-V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_LOCK_RESERVED_29_LOCKED 0x00000001 /* RW--V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_LOCK_RESERVED_30 9:9 /* RWIVF */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_LOCK_RESERVED_30__ONWRITE "oneToSet" /* */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_LOCK_RESERVED_30_UNLOCKED 0x00000000 /* RWI-V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_LOCK_RESERVED_30_LOCKED 0x00000001 /* RW--V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_LOCK_RESERVED_31 10:10 /* RWIVF */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_LOCK_RESERVED_31__ONWRITE "oneToSet" /* */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_LOCK_RESERVED_31_UNLOCKED 0x00000000 /* RWI-V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_LOCK_RESERVED_31_LOCKED 0x00000001 /* RW--V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_LOCK_CLEAR 0x0000062c /* RW-4R */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_LOCK_CLEAR_RESTORE_PHY_TRAINING_PARAMS 0:0 /* RWIVF */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_LOCK_CLEAR_RESTORE_PHY_TRAINING_PARAMS__ONWRITE "oneToClear" /* */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_LOCK_CLEAR_RESTORE_PHY_TRAINING_PARAMS_INIT 0x00000000 /* RWI-V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_LOCK_CLEAR_RESTORE_PHY_TRAINING_PARAMS_UNLOCK 0x00000001 /* RW--V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_LOCK_CLEAR_ALI_ENABLE 1:1 /* RWIVF */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_LOCK_CLEAR_ALI_ENABLE__ONWRITE "oneToClear" /* */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_LOCK_CLEAR_ALI_ENABLE_INIT 0x00000000 /* RWI-V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_LOCK_CLEAR_ALI_ENABLE_UNLOCK 0x00000001 /* RW--V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_LOCK_CLEAR_L1_MINIMUM_RECALIBRATION_TIME_MANTISSA 2:2 /* RWIVF */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_LOCK_CLEAR_L1_MINIMUM_RECALIBRATION_TIME_MANTISSA__ONWRITE "oneToClear" /* */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_LOCK_CLEAR_L1_MINIMUM_RECALIBRATION_TIME_MANTISSA_INIT 0x00000000 /* RWI-V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_LOCK_CLEAR_L1_MINIMUM_RECALIBRATION_TIME_MANTISSA_UNLOCK 0x00000001 /* RW--V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_LOCK_CLEAR_L1_MINIMUM_RECALIBRATION_TIME_EXPONENT 3:3 /* RWIVF */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_LOCK_CLEAR_L1_MINIMUM_RECALIBRATION_TIME_EXPONENT__ONWRITE "oneToClear" /* */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_LOCK_CLEAR_L1_MINIMUM_RECALIBRATION_TIME_EXPONENT_INIT 0x00000000 /* RWI-V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_LOCK_CLEAR_L1_MINIMUM_RECALIBRATION_TIME_EXPONENT_UNLOCK 0x00000001 /* RW--V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_LOCK_CLEAR_L1_MAXIMUM_RECALIBRATION_PERIOD_MANTISSA 4:4 /* RWIVF */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_LOCK_CLEAR_L1_MAXIMUM_RECALIBRATION_PERIOD_MANTISSA__ONWRITE "oneToClear" /* */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_LOCK_CLEAR_L1_MAXIMUM_RECALIBRATION_PERIOD_MANTISSA_INIT 0x00000000 /* RWI-V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_LOCK_CLEAR_L1_MAXIMUM_RECALIBRATION_PERIOD_MANTISSA_UNLOCK 0x00000001 /* RW--V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_LOCK_CLEAR_L1_MAXIMUM_RECALIBRATION_PERIOD_EXPONENT 5:5 /* RWIVF */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_LOCK_CLEAR_L1_MAXIMUM_RECALIBRATION_PERIOD_EXPONENT__ONWRITE "oneToClear" /* */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_LOCK_CLEAR_L1_MAXIMUM_RECALIBRATION_PERIOD_EXPONENT_INIT 0x00000000 /* RWI-V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_LOCK_CLEAR_L1_MAXIMUM_RECALIBRATION_PERIOD_EXPONENT_UNLOCK 0x00000001 /* RW--V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_LOCK_CLEAR_DISABLE_UPHY_MICROCODE_LOAD 6:6 /* RWIVF */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_LOCK_CLEAR_DISABLE_UPHY_MICROCODE_LOAD__ONWRITE "oneToClear" /* */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_LOCK_CLEAR_DISABLE_UPHY_MICROCODE_LOAD_INIT 0x00000000 /* RWI-V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_LOCK_CLEAR_DISABLE_UPHY_MICROCODE_LOAD_UNLOCK 0x00000001 /* RW--V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_LOCK_CLEAR_CHANNEL_TYPE 7:7 /* RWIVF */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_LOCK_CLEAR_CHANNEL_TYPE__ONWRITE "oneToClear" /* */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_LOCK_CLEAR_CHANNEL_TYPE_INIT 0x00000000 /* RWI-V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_LOCK_CLEAR_CHANNEL_TYPE_UNLOCK 0x00000001 /* RW--V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_LOCK_CLEAR_RESERVED_29 8:8 /* RWIVF */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_LOCK_CLEAR_RESERVED_29__ONWRITE "oneToClear" /* */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_LOCK_CLEAR_RESERVED_29_INIT 0x00000000 /* RWI-V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_LOCK_CLEAR_RESERVED_29_UNLOCK 0x00000001 /* RW--V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_LOCK_CLEAR_RESERVED_30 9:9 /* RWIVF */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_LOCK_CLEAR_RESERVED_30__ONWRITE "oneToClear" /* */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_LOCK_CLEAR_RESERVED_30_INIT 0x00000000 /* RWI-V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_LOCK_CLEAR_RESERVED_30_UNLOCK 0x00000001 /* RW--V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_LOCK_CLEAR_RESERVED_31 10:10 /* RWIVF */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_LOCK_CLEAR_RESERVED_31__ONWRITE "oneToClear" /* */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_LOCK_CLEAR_RESERVED_31_INIT 0x00000000 /* RWI-V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_LOCK_CLEAR_RESERVED_31_UNLOCK 0x00000001 /* RW--V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_AN1_CTRL 0x00000638 /* RW-4R */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_AN1_CTRL_PWRM_L1_ENABLE 1:1 /* RWIVF */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_AN1_CTRL_PWRM_L1_ENABLE_ENABLE 0x00000001 /* RWI-V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_AN1_CTRL_PWRM_L1_ENABLE_DISABLE 0x00000000 /* RW--V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_AN1_CTRL_PWRM_L2_ENABLE 2:2 /* RWIVF */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_AN1_CTRL_PWRM_L2_ENABLE_ENABLE 0x00000001 /* RWI-V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_AN1_CTRL_PWRM_L2_ENABLE_DISABLE 0x00000000 /* RW--V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_AN1_CTRL_RESERVED_3 3:3 /* RWIVF */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_AN1_CTRL_RESERVED_3_INIT 0x00000000 /* RWI-V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_AN1_CTRL_RESERVED_4 4:4 /* RWIVF */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_AN1_CTRL_RESERVED_4_INIT 0x00000000 /* RWI-V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_AN1_CTRL_RESERVED_5 5:5 /* RWIVF */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_AN1_CTRL_RESERVED_5_INIT 0x00000000 /* RWI-V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_AN1_CTRL_RESERVED_6 6:6 /* RWIVF */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_AN1_CTRL_RESERVED_6_INIT 0x00000000 /* RWI-V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_AN1_CTRL_RESERVED_7 7:7 /* RWIVF */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_AN1_CTRL_RESERVED_7_INIT 0x00000000 /* RWI-V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_AN1_CTRL_RESERVED_8 8:8 /* RWIVF */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_AN1_CTRL_RESERVED_8_INIT 0x00000000 /* RWI-V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_AN1_CTRL_RESERVED_9 9:9 /* RWIVF */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_AN1_CTRL_RESERVED_9_INIT 0x00000000 /* RWI-V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_AN1_CTRL_RESERVED_10 10:10 /* RWIVF */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_AN1_CTRL_RESERVED_10_INIT 0x00000000 /* RWI-V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_AN1_CTRL_RESERVED_11 11:11 /* RWIVF */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_AN1_CTRL_RESERVED_11_INIT 0x00000000 /* RWI-V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_AN1_CTRL_RESERVED_12 12:12 /* RWIVF */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_AN1_CTRL_RESERVED_12_INIT 0x00000000 /* RWI-V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_AN1_CTRL_RESERVED_13 13:13 /* RWIVF */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_AN1_CTRL_RESERVED_13_INIT 0x00000000 /* RWI-V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_AN1_CTRL_RESERVED_14 14:14 /* RWIVF */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_AN1_CTRL_RESERVED_14_INIT 0x00000000 /* RWI-V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_AN1_CTRL_RESERVED_15 15:15 /* RWIVF */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_AN1_CTRL_RESERVED_15_INIT 0x00000000 /* RWI-V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_AN1_CTRL_RESERVED_16 16:16 /* RWIVF */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_AN1_CTRL_RESERVED_16_INIT 0x00000000 /* RWI-V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_AN1_CTRL_RESERVED_17 17:17 /* RWIVF */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_AN1_CTRL_RESERVED_17_INIT 0x00000000 /* RWI-V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_AN1_CTRL_RESERVED_18 18:18 /* RWIVF */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_AN1_CTRL_RESERVED_18_INIT 0x00000000 /* RWI-V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_AN1_CTRL_RESERVED_19 19:19 /* RWIVF */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_AN1_CTRL_RESERVED_19_INIT 0x00000000 /* RWI-V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_AN1_CTRL_RESERVED_20 20:20 /* RWIVF */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_AN1_CTRL_RESERVED_20_INIT 0x00000000 /* RWI-V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_AN1_CTRL_RESERVED_21 21:21 /* RWIVF */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_AN1_CTRL_RESERVED_21_INIT 0x00000000 /* RWI-V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_AN1_CTRL_RESERVED_22 22:22 /* RWIVF */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_AN1_CTRL_RESERVED_22_INIT 0x00000000 /* RWI-V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_AN1_CTRL_RESERVED_23 23:23 /* RWIVF */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_AN1_CTRL_RESERVED_23_INIT 0x00000000 /* RWI-V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_AN1_CTRL_RESERVED_24 24:24 /* RWIVF */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_AN1_CTRL_RESERVED_24_INIT 0x00000000 /* RWI-V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_AN1_CTRL_RESERVED_25 25:25 /* RWIVF */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_AN1_CTRL_RESERVED_25_INIT 0x00000000 /* RWI-V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_AN1_CTRL_RESERVED_26 26:26 /* RWIVF */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_AN1_CTRL_RESERVED_26_INIT 0x00000000 /* RWI-V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_AN1_CTRL_RESERVED_27 27:27 /* RWIVF */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_AN1_CTRL_RESERVED_27_INIT 0x00000000 /* RWI-V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_AN1_CTRL_RESERVED_28 28:28 /* RWIVF */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_AN1_CTRL_RESERVED_28_INIT 0x00000000 /* RWI-V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_AN1_CTRL_RESERVED_29 29:29 /* RWIVF */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_AN1_CTRL_RESERVED_29_INIT 0x00000000 /* RWI-V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_AN1_CTRL_RESERVED_30 30:30 /* RWIVF */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_AN1_CTRL_RESERVED_30_INIT 0x00000000 /* RWI-V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_AN1_CTRL_RESERVED_31 31:31 /* RWIVF */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_AN1_CTRL_RESERVED_31_INIT 0x00000000 /* RWI-V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_AN1_CTRL_LOCK 0x0000063c /* RW-4R */
#define NV_NVLIPT_LNK_CTRL_CAP_LOCAL_LINK_CHANNEL 0x00000680 /* RW-4R */
#define NV_NVLIPT_LNK_CTRL_CAP_LOCAL_LINK_CHANNEL_AC_DC_SUPPORT 1:0 /* RWIVF */
#define NV_NVLIPT_LNK_CTRL_CAP_LOCAL_LINK_CHANNEL_AC_DC_SUPPORT_DC 0x00000001 /* RW--V */
#define NV_NVLIPT_LNK_CTRL_CAP_LOCAL_LINK_CHANNEL_AC_DC_SUPPORT_AC 0x00000002 /* RW--V */
#define NV_NVLIPT_LNK_CTRL_CAP_LOCAL_LINK_CHANNEL_AC_DC_SUPPORT_AC_AND_DC 0x00000003 /* RWI-V */
#define NV_NVLIPT_LNK_CTRL_CAP_LOCAL_LINK_CHANNEL_LINE_CODE_SUPPORT 5:2 /* RWIVF */
#define NV_NVLIPT_LNK_CTRL_CAP_LOCAL_LINK_CHANNEL_LINE_CODE_SUPPORT_INIT 0x00000009 /* RWI-V */
#define NV_NVLIPT_LNK_CTRL_CAP_LOCAL_LINK_CHANNEL_LINE_CODE_SUPPORT_NRZ 0x00000001 /* RW--V */
#define NV_NVLIPT_LNK_CTRL_CAP_LOCAL_LINK_CHANNEL_LINE_CODE_SUPPORT_PAM4 0x00000008 /* RW--V */
#define NV_NVLIPT_LNK_CTRL_CAP_LOCAL_LINK_CHANNEL_RECEIVER_DETECT_SUPPORT 6:6 /* RWIVF */
#define NV_NVLIPT_LNK_CTRL_CAP_LOCAL_LINK_CHANNEL_RECEIVER_DETECT_SUPPORT_SUPPORTED 0x00000001 /* RWI-V */
#define NV_NVLIPT_LNK_CTRL_CAP_LOCAL_LINK_CHANNEL_RECEIVER_DETECT_SUPPORT_NOT_SUPPORTED 0x00000000 /* RW--V */
#define NV_NVLIPT_LNK_CTRL_CAP_LOCAL_LINK_CHANNEL_BLOCK_CODE_SUPPORT 9:7 /* RWIVF */
#define NV_NVLIPT_LNK_CTRL_CAP_LOCAL_LINK_CHANNEL_BLOCK_CODE_SUPPORT_INIT 0x00000003 /* RWI-V */
#define NV_NVLIPT_LNK_CTRL_CAP_LOCAL_LINK_CHANNEL_BLOCK_CODE_SUPPORT_NONE 0x00000001 /* RW--V */
#define NV_NVLIPT_LNK_CTRL_CAP_LOCAL_LINK_CHANNEL_BLOCK_CODE_SUPPORT_ECC89 0x00000002 /* RW--V */
#define NV_NVLIPT_LNK_CTRL_CAP_LOCAL_LINK_CHANNEL_TXTRAIN_FOM_FORMAT_SUPPORT 12:10 /* RWIVF */
#define NV_NVLIPT_LNK_CTRL_CAP_LOCAL_LINK_CHANNEL_TXTRAIN_FOM_FORMAT_SUPPORT_INIT 0x00000005 /* RWI-V */
#define NV_NVLIPT_LNK_CTRL_CAP_LOCAL_LINK_CHANNEL_TXTRAIN_FOM_FORMAT_SUPPORT_FOMA 0x00000001 /* RW--V */
#define NV_NVLIPT_LNK_CTRL_CAP_LOCAL_LINK_CHANNEL_TXTRAIN_FOM_FORMAT_SUPPORT_FOMB 0x00000002 /* RW--V */
#define NV_NVLIPT_LNK_CTRL_CAP_LOCAL_LINK_CHANNEL_TXTRAIN_FOM_FORMAT_SUPPORT_FOMC 0x00000004 /* RW--V */
#define NV_NVLIPT_LNK_CTRL_CAP_LOCAL_LINK_CHANNEL_TXTRAIN_OPTIMIZATION_ALGORITHM_SUPPORT 22:15 /* RWIVF */
#define NV_NVLIPT_LNK_CTRL_CAP_LOCAL_LINK_CHANNEL_TXTRAIN_OPTIMIZATION_ALGORITHM_SUPPORT_INIT 0x00000017 /* RWI-V */
#define NV_NVLIPT_LNK_CTRL_CAP_LOCAL_LINK_CHANNEL_TXTRAIN_OPTIMIZATION_ALGORITHM_SUPPORT_A0 0x00000001 /* RW--V */
#define NV_NVLIPT_LNK_CTRL_CAP_LOCAL_LINK_CHANNEL_TXTRAIN_OPTIMIZATION_ALGORITHM_SUPPORT_A1 0x00000002 /* RW--V */
#define NV_NVLIPT_LNK_CTRL_CAP_LOCAL_LINK_CHANNEL_TXTRAIN_OPTIMIZATION_ALGORITHM_SUPPORT_A2 0x00000004 /* RW--V */
#define NV_NVLIPT_LNK_CTRL_CAP_LOCAL_LINK_CHANNEL_TXTRAIN_OPTIMIZATION_ALGORITHM_SUPPORT_A3 0x00000008 /* RW--V */
#define NV_NVLIPT_LNK_CTRL_CAP_LOCAL_LINK_CHANNEL_TXTRAIN_OPTIMIZATION_ALGORITHM_SUPPORT_A4 0x00000010 /* RW--V */
#define NV_NVLIPT_LNK_CTRL_CAP_LOCAL_LINK_CHANNEL_TXTRAIN_OPTIMIZATION_ALGORITHM_SUPPORT_A5 0x00000020 /* RW--V */
#define NV_NVLIPT_LNK_CTRL_CAP_LOCAL_LINK_CHANNEL_TXTRAIN_OPTIMIZATION_ALGORITHM_SUPPORT_A6 0x00000040 /* RW--V */
#define NV_NVLIPT_LNK_CTRL_CAP_LOCAL_LINK_CHANNEL_TXTRAIN_OPTIMIZATION_ALGORITHM_SUPPORT_A7 0x00000080 /* RW--V */
#define NV_NVLIPT_LNK_CTRL_CAP_LOCAL_LINK_CHANNEL_TXTRAIN_ADJUSTMENT_ALGORITHM_SUPPORT 27:23 /* RWIVF */
#define NV_NVLIPT_LNK_CTRL_CAP_LOCAL_LINK_CHANNEL_TXTRAIN_ADJUSTMENT_ALGORITHM_SUPPORT_B0 0x00000001 /* RWI-V */
#define NV_NVLIPT_LNK_CTRL_CAP_LOCAL_LINK_CHANNEL_TXTRAIN_ADJUSTMENT_ALGORITHM_SUPPORT_B1 0x00000002 /* RW--V */
#define NV_NVLIPT_LNK_CTRL_CAP_LOCAL_LINK_CHANNEL_TXTRAIN_ADJUSTMENT_ALGORITHM_SUPPORT_B2 0x00000004 /* RW--V */
#define NV_NVLIPT_LNK_CTRL_CAP_LOCAL_LINK_CHANNEL_TXTRAIN_ADJUSTMENT_ALGORITHM_SUPPORT_B3 0x00000008 /* RW--V */
#define NV_NVLIPT_LNK_CTRL_CAP_LOCAL_LINK_CHANNEL_ALI_SUPPORT 28:28 /* RWIVF */
#define NV_NVLIPT_LNK_CTRL_CAP_LOCAL_LINK_CHANNEL_ALI_SUPPORT_SUPPORTED 0x00000001 /* RWI-V */
#define NV_NVLIPT_LNK_CTRL_CAP_LOCAL_LINK_CHANNEL_ALI_SUPPORT_NOT_SUPPORTED 0x00000000 /* RW--V */
#endif // __ls10_dev_nvlipt_lnk_ip_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the Software),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __ls10_dev_nvlphyctl_ip_h__
#define __ls10_dev_nvlphyctl_ip_h__
/* This file is autogenerated. Do not edit */
#define NV_NVLPHYCTL 0x00002DFF:0x00002800 /* RW--D */
#define NV_NVLPHYCTL_COMMON_PSAVE_UCODE_CTRL_STS 0x00002840 /* RW-4R */
#define NV_NVLPHYCTL_COMMON_PSAVE_UCODE_CTRL_STS_PMREQ 3:0 /* RWEVF */
#define NV_NVLPHYCTL_COMMON_PSAVE_UCODE_CTRL_STS_PMREQ_NOP 0x00000000 /* RWE-V */
#define NV_NVLPHYCTL_COMMON_PSAVE_UCODE_CTRL_STS_PMREQ_TO_PSDI 0x00000002 /* RW--V */
#define NV_NVLPHYCTL_COMMON_PSAVE_UCODE_CTRL_STS_PMREQ_TO_PSL0 0x00000004 /* RW--V */
#define NV_NVLPHYCTL_COMMON_PSAVE_UCODE_CTRL_STS_PMREQ_TO_PSL1 0x00000006 /* RW--V */
#define NV_NVLPHYCTL_COMMON_PSAVE_UCODE_CTRL_STS_PMREQ_TO_PSL2 0x00000008 /* RW--V */
#define NV_NVLPHYCTL_COMMON_PSAVE_UCODE_CTRL_STS_PMSTS 7:4 /* R-EVF */
#define NV_NVLPHYCTL_COMMON_PSAVE_UCODE_CTRL_STS_PMSTS_NOP 0x00000000 /* R---V */
#define NV_NVLPHYCTL_COMMON_PSAVE_UCODE_CTRL_STS_PMSTS_PSDI 0x00000002 /* R---V */
#define NV_NVLPHYCTL_COMMON_PSAVE_UCODE_CTRL_STS_PMSTS_PSL0 0x00000004 /* R---V */
#define NV_NVLPHYCTL_COMMON_PSAVE_UCODE_CTRL_STS_PMSTS_PSL1 0x00000006 /* R---V */
#define NV_NVLPHYCTL_COMMON_PSAVE_UCODE_CTRL_STS_PMSTS_PSL2 0x00000008 /* R-E-V */
#define NV_NVLPHYCTL_COMMON_PSAVE_UCODE_CTRL_STS_PMSTS_PSERR 0x0000000a /* R---V */
#define NV_NVLPHYCTL_COMMON_PSAVE_UCODE_CTRL_STS_PMBUSY 8:8 /* R-EVF */
#define NV_NVLPHYCTL_COMMON_PSAVE_UCODE_CTRL_STS_PMBUSY_OFF 0x00000000 /* R-E-V */
#define NV_NVLPHYCTL_COMMON_PSAVE_UCODE_CTRL_STS_PMBUSY_ON 0x00000001 /* R---V */
#define NV_NVLPHYCTL_COMMON_PSAVE_UCODE_CTRL_STS_PSL1TXSLEEPVAL 10:9 /* RWEVF */
#define NV_NVLPHYCTL_COMMON_PSAVE_UCODE_CTRL_STS_PSL1TXSLEEPVAL_INIT 0x00000002 /* RWE-V */
#define NV_NVLPHYCTL_COMMON_PSAVE_UCODE_CTRL_STS_PSL1RXSLEEPVAL 12:11 /* RWEVF */
#define NV_NVLPHYCTL_COMMON_PSAVE_UCODE_CTRL_STS_PSL1RXSLEEPVAL_INIT 0x00000003 /* RWE-V */
#define NV_NVLPHYCTL_COMMON_PSAVE_UCODE_CTRL_STS_PSDITXSLEEPVAL 14:13 /* RWEVF */
#define NV_NVLPHYCTL_COMMON_PSAVE_UCODE_CTRL_STS_PSDITXSLEEPVAL_INIT 0x00000000 /* RWE-V */
#define NV_NVLPHYCTL_COMMON_PSAVE_UCODE_CTRL_STS_PSDIRXSLEEPVAL 16:15 /* RWEVF */
#define NV_NVLPHYCTL_COMMON_PSAVE_UCODE_CTRL_STS_PSDIRXSLEEPVAL_INIT 0x00000000 /* RWE-V */
#define NV_NVLPHYCTL_COMMON_PSAVE_UCODE_CTRL_STS_TXCLK_SWITCH_TIMEOUT_ERR 17:17 /* RWEVF */
#define NV_NVLPHYCTL_COMMON_PSAVE_UCODE_CTRL_STS_TXCLK_SWITCH_TIMEOUT_ERR__ONWRITE "oneToClear" /* */
#define NV_NVLPHYCTL_COMMON_PSAVE_UCODE_CTRL_STS_TXCLK_SWITCH_TIMEOUT_ERR_OFF 0x00000000 /* RWE-V */
#define NV_NVLPHYCTL_COMMON_PSAVE_UCODE_CTRL_STS_TXCLK_SWITCH_TIMEOUT_ERR_ON 0x00000001 /* RW--V */
#define NV_NVLPHYCTL_COMMON_PSAVE_UCODE_CTRL_STS_PHYARB_TIMEOUT_ERR 18:18 /* RWEVF */
#define NV_NVLPHYCTL_COMMON_PSAVE_UCODE_CTRL_STS_PHYARB_TIMEOUT_ERR__ONWRITE "oneToClear" /* */
#define NV_NVLPHYCTL_COMMON_PSAVE_UCODE_CTRL_STS_PHYARB_TIMEOUT_ERR_OFF 0x00000000 /* RWE-V */
#define NV_NVLPHYCTL_COMMON_PSAVE_UCODE_CTRL_STS_PHYARB_TIMEOUT_ERR_ON 0x00000001 /* RW--V */
#define NV_NVLPHYCTL_COMMON_PSAVE_UCODE_CTRL_STS_INVLD_PMREQ_ERR 19:19 /* RWEVF */
#define NV_NVLPHYCTL_COMMON_PSAVE_UCODE_CTRL_STS_INVLD_PMREQ_ERR__ONWRITE "oneToClear" /* */
#define NV_NVLPHYCTL_COMMON_PSAVE_UCODE_CTRL_STS_INVLD_PMREQ_ERR_OFF 0x00000000 /* RWE-V */
#define NV_NVLPHYCTL_COMMON_PSAVE_UCODE_CTRL_STS_INVLD_PMREQ_ERR_ON 0x00000001 /* RW--V */
#define NV_NVLPHYCTL_COMMON_PSAVE_UCODE_CTRL_STS_RSTPWRDN_DLY 20:20 /* RWEVF */
#define NV_NVLPHYCTL_COMMON_PSAVE_UCODE_CTRL_STS_RSTPWRDN_DLY_DIS 0x00000000 /* RWE-V */
#define NV_NVLPHYCTL_COMMON_PSAVE_UCODE_CTRL_STS_RSTPWRDN_DLY_EN 0x00000001 /* RW--V */
#define NV_NVLPHYCTL_COMMON_PSAVE_UCODE_CTRL_STS_RSTPWRDN_PSL2DLY 21:21 /* RWEVF */
#define NV_NVLPHYCTL_COMMON_PSAVE_UCODE_CTRL_STS_RSTPWRDN_PSL2DLY_DIS 0x00000000 /* RW--V */
#define NV_NVLPHYCTL_COMMON_PSAVE_UCODE_CTRL_STS_RSTPWRDN_PSL2DLY_EN 0x00000001 /* RWE-V */
#endif // __ls10_dev_nvlphyctl_ip_h__

99
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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the Software),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __ls10_dev_nvlsaw_ip_h__
#define __ls10_dev_nvlsaw_ip_h__
/* This file is autogenerated. Do not edit */
#define NV_NVLSAW 0x000007FF:0x00000000 /* RW--D */
#define NV_NVLSAW_GLBLLATENCYTIMERCTRL 0x00000040 /* RW-4R */
#define NV_NVLSAW_GLBLLATENCYTIMERCTRL_ENABLE 0:0 /* RWEVF */
#define NV_NVLSAW_GLBLLATENCYTIMERCTRL_ENABLE_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLSAW_GLBLLATENCYTIMERCTRL_ENABLE_ENABLE 0x00000001 /* RW--V */
#define NV_NVLSAW_GLBLLATENCYTIMERCTRL_ENABLE__PROD 0x00000001 /* RW--V */
#define NV_NVLSAW_CTRL_CLOCK_GATING 0x00000064 /* RW-4R */
#define NV_NVLSAW_CTRL_CLOCK_GATING_CG1_SLCG_SAW 0:0 /* RWEVF */
#define NV_NVLSAW_CTRL_CLOCK_GATING_CG1_SLCG_SAW_ENABLED 0x00000000 /* RW--V */
#define NV_NVLSAW_CTRL_CLOCK_GATING_CG1_SLCG_SAW_DISABLED 0x00000001 /* RWE-V */
#define NV_NVLSAW_CTRL_CLOCK_GATING_CG1_SLCG_SAW__PROD 0x00000000 /* RW--V */
#define NV_NVLSAW_CTRL_CLOCK_GATING_CG1_SLCG_PCIE 2:2 /* RWEVF */
#define NV_NVLSAW_CTRL_CLOCK_GATING_CG1_SLCG_PCIE_ENABLED 0x00000000 /* RW--V */
#define NV_NVLSAW_CTRL_CLOCK_GATING_CG1_SLCG_PCIE_DISABLED 0x00000001 /* RWE-V */
#define NV_NVLSAW_CTRL_CLOCK_GATING_CG1_SLCG_PCIE__PROD 0x00000000 /* RW--V */
#define NV_NVLSAW_SW_SCRATCH_0 0x000004e0 /* RW-4R */
#define NV_NVLSAW_SW_SCRATCH_0_VALUE 31:0 /* RWEVF */
#define NV_NVLSAW_SW_SCRATCH_0_VALUE_INIT 0x00000000 /* RWE-V */
#define NV_NVLSAW_SW_SCRATCH_1 0x000004e4 /* RW-4R */
#define NV_NVLSAW_SW_SCRATCH_1_VALUE 31:0 /* RWEVF */
#define NV_NVLSAW_SW_SCRATCH_1_VALUE_INIT 0x00000000 /* RWE-V */
#define NV_NVLSAW_SW_SCRATCH_2 0x000004e8 /* RW-4R */
#define NV_NVLSAW_SW_SCRATCH_2_VALUE 31:0 /* RWEVF */
#define NV_NVLSAW_SW_SCRATCH_2_VALUE_INIT 0x00000000 /* RWE-V */
#define NV_NVLSAW_SW_SCRATCH_3 0x000004ec /* RW-4R */
#define NV_NVLSAW_SW_SCRATCH_3_VALUE 31:0 /* RWEVF */
#define NV_NVLSAW_SW_SCRATCH_3_VALUE_INIT 0x00000000 /* RWE-V */
#define NV_NVLSAW_SW_SCRATCH_4 0x000004f0 /* RW-4R */
#define NV_NVLSAW_SW_SCRATCH_4_VALUE 31:0 /* RWEVF */
#define NV_NVLSAW_SW_SCRATCH_4_VALUE_INIT 0x00000000 /* RWE-V */
#define NV_NVLSAW_SW_SCRATCH_5 0x000004f4 /* RW-4R */
#define NV_NVLSAW_SW_SCRATCH_5_VALUE 31:0 /* RWEVF */
#define NV_NVLSAW_SW_SCRATCH_5_VALUE_INIT 0x00000000 /* RWE-V */
#define NV_NVLSAW_SW_SCRATCH_6 0x000004f8 /* RW-4R */
#define NV_NVLSAW_SW_SCRATCH_6_VALUE 31:0 /* RWEVF */
#define NV_NVLSAW_SW_SCRATCH_6_VALUE_INIT 0x00000000 /* RWE-V */
#define NV_NVLSAW_SW_SCRATCH_7 0x000004fc /* RW-4R */
#define NV_NVLSAW_SW_SCRATCH_7_VALUE 31:0 /* RWEVF */
#define NV_NVLSAW_SW_SCRATCH_7_VALUE_INIT 0x00000000 /* RWE-V */
#define NV_NVLSAW_SW_SCRATCH_8 0x00000500 /* RW-4R */
#define NV_NVLSAW_SW_SCRATCH_8_VALUE 31:0 /* RWEVF */
#define NV_NVLSAW_SW_SCRATCH_8_VALUE_INIT 0x00000000 /* RWE-V */
#define NV_NVLSAW_SW_SCRATCH_9 0x00000504 /* RW-4R */
#define NV_NVLSAW_SW_SCRATCH_9_VALUE 31:0 /* RWEVF */
#define NV_NVLSAW_SW_SCRATCH_9_VALUE_INIT 0x00000000 /* RWE-V */
#define NV_NVLSAW_SW_SCRATCH_10 0x00000508 /* RW-4R */
#define NV_NVLSAW_SW_SCRATCH_10_VALUE 31:0 /* RWEVF */
#define NV_NVLSAW_SW_SCRATCH_10_VALUE_INIT 0x00000000 /* RWE-V */
#define NV_NVLSAW_SW_SCRATCH_11 0x0000050c /* RW-4R */
#define NV_NVLSAW_SW_SCRATCH_11_VALUE 31:0 /* RWEVF */
#define NV_NVLSAW_SW_SCRATCH_11_VALUE_INIT 0x00000000 /* RWE-V */
#define NV_NVLSAW_SW_SCRATCH_12 0x00000510 /* RW-4R */
#define NV_NVLSAW_SW_SCRATCH_12_VALUE 31:0 /* RWEVF */
#define NV_NVLSAW_SW_SCRATCH_12_VALUE_INIT 0x00000000 /* RWE-V */
#define NV_NVLSAW_SW_SCRATCH_13 0x00000514 /* RW-4R */
#define NV_NVLSAW_SW_SCRATCH_13_VALUE 31:0 /* RWEVF */
#define NV_NVLSAW_SW_SCRATCH_13_VALUE_INIT 0x00000000 /* RWE-V */
#define NV_NVLSAW_SW_SCRATCH_14 0x00000518 /* RW-4R */
#define NV_NVLSAW_SW_SCRATCH_14_VALUE 31:0 /* RWEVF */
#define NV_NVLSAW_SW_SCRATCH_14_VALUE_INIT 0x00000000 /* RWE-V */
#define NV_NVLSAW_SW_SCRATCH_15 0x0000051c /* RW-4R */
#define NV_NVLSAW_SW_SCRATCH_15_VALUE 31:0 /* RWEVF */
#define NV_NVLSAW_SW_SCRATCH_15_VALUE_INIT 0x00000000 /* RWE-V */
#define NV_NVLSAW_PCIE_PRI_CLOCK_GATING 0x00000530 /* RW-4R */
#define NV_NVLSAW_PCIE_PRI_CLOCK_GATING_CG1_SLCG 0:0 /* RWEVF */
#define NV_NVLSAW_PCIE_PRI_CLOCK_GATING_CG1_SLCG_ENABLED 0x00000000 /* RW--V */
#define NV_NVLSAW_PCIE_PRI_CLOCK_GATING_CG1_SLCG_DISABLED 0x00000001 /* RWE-V */
#define NV_NVLSAW_PCIE_PRI_CLOCK_GATING_CG1_SLCG__PROD 0x00000000 /* RW--V */
#define NV_NVLSAW_SECURE_SCRATCH_WARM_GROUP_1(i) (0x00000c30+(i)*0x4) /* RW-4A */
#define NV_NVLSAW_SECURE_SCRATCH_WARM_GROUP_1__SIZE_1 4 /* */
#define NV_NVLSAW_SECURE_SCRATCH_WARM_GROUP_1_VALUE 31:0 /* RWEVF */
#define NV_NVLSAW_SECURE_SCRATCH_WARM_GROUP_1_VALUE_INIT 0x00000000 /* RWE-V */
#endif // __ls10_dev_nvlsaw_ip_h__

55
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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the Software),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
/*!
* @file dev_nvlsaw_ip_addendum.h
* @brief NVSwitch specific defines that are missing in the dev_nvlsaw_ip.h manual.
*/
#ifndef __ls10_dev_nvlsaw_ip_addendum_h__
#define __ls10_dev_nvlsaw_ip_addendum_h__
/*
* SOE ATTACH-DETACH registers to track SOE & Driver
* status for load and shutdown.
*
* SCRATCH_13 tracks status of SOE &
* SCRATCH_3 tracks status of driver
*/
#define NV_NVLSAW_SOE_ATTACH_DETACH NV_NVLSAW_SW_SCRATCH_3
#define NV_NVLSAW_SOE_ATTACH_DETACH_STATUS 0:0
#define NV_NVLSAW_SOE_ATTACH_DETACH_STATUS_ATTACHED 0x1
#define NV_NVLSAW_SOE_ATTACH_DETACH_STATUS_DETACHED 0x0
#define NV_NVLSAW_DRIVER_ATTACH_DETACH NV_NVLSAW_SW_SCRATCH_13
#define NV_NVLSAW_DRIVER_ATTACH_DETACH_STATUS 0:0
#define NV_NVLSAW_DRIVER_ATTACH_DETACH_STATUS_ATTACHED 0x1
#define NV_NVLSAW_DRIVER_ATTACH_DETACH_STATUS_DETACHED 0x0
#define NV_NVLSAW_DRIVER_ATTACH_DETACH_DEVICE_RESET_REQUIRED 5:5
#define NV_NVLSAW_DRIVER_ATTACH_DETACH_DEVICE_BLACKLIST_REASON 10:6
#define NV_NVLSAW_DRIVER_ATTACH_DETACH_DEVICE_FABRIC_STATE 13:11
#define NV_NVLSAW_DRIVER_ATTACH_DETACH_DRIVER_FABRIC_STATE 16:14
#define NV_NVLSAW_DRIVER_ATTACH_DETACH_FABRIC_MANAGER_ERROR 23:17
#define NV_NVLSAW_DRIVER_ATTACH_DETACH_EVENT_MESSAGE_COUNT 31:24
#endif //__ls10_dev_nvlsaw_ip_addendum_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the Software),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __ls10_dev_nvltlc_ip_h__
#define __ls10_dev_nvltlc_ip_h__
/* This file is autogenerated. Do not edit */
#define NV_NVLTLC_TX_SYS 0x000007FF:0x00000000 /* RW--D */
#define NV_NVLTLC_RX_SYS 0x00000FFF:0x00000800 /* RW--D */
#define NV_NVLTLC_TX_LNK 0x000017FF:0x00001000 /* RW--D */
#define NV_NVLTLC_RX_LNK 0x00001FFF:0x00001800 /* RW--D */
#define NV_NVLTLC_TX_SYS_CTRL_BUFFER_READY 0x00000124 /* RW-4R */
#define NV_NVLTLC_TX_SYS_CTRL_BUFFER_READY_BUFFERRDY 0:0 /* RWEVF */
#define NV_NVLTLC_TX_SYS_CTRL_BUFFER_READY_BUFFERRDY__ONWRITE "oneToSet" /* */
#define NV_NVLTLC_TX_SYS_CTRL_BUFFER_READY_BUFFERRDY_ENABLE 0x00000001 /* RW--V */
#define NV_NVLTLC_TX_SYS_CTRL_BUFFER_READY_BUFFERRDY_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLTLC_TX_SYS_ERR_STATUS_0 0x00000280 /* RW-4R */
#define NV_NVLTLC_TX_SYS_ERR_STATUS_0_NCISOC_PARITY_ERR 0:0 /* RWDVF */
#define NV_NVLTLC_TX_SYS_ERR_STATUS_0_NCISOC_PARITY_ERR__ONWRITE "oneToClear" /* */
#define NV_NVLTLC_TX_SYS_ERR_STATUS_0_NCISOC_PARITY_ERR_NONE 0x00000000 /* RWD-V */
#define NV_NVLTLC_TX_SYS_ERR_STATUS_0_NCISOC_PARITY_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_NVLTLC_TX_SYS_ERR_STATUS_0_NCISOC_HDR_ECC_DBE_ERR 8:8 /* RWDVF */
#define NV_NVLTLC_TX_SYS_ERR_STATUS_0_NCISOC_HDR_ECC_DBE_ERR__ONWRITE "oneToClear" /* */
#define NV_NVLTLC_TX_SYS_ERR_STATUS_0_NCISOC_HDR_ECC_DBE_ERR_NONE 0x00000000 /* RWD-V */
#define NV_NVLTLC_TX_SYS_ERR_STATUS_0_NCISOC_HDR_ECC_DBE_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_NVLTLC_TX_SYS_ERR_STATUS_0_NCISOC_DAT_ECC_DBE_ERR 9:9 /* RWDVF */
#define NV_NVLTLC_TX_SYS_ERR_STATUS_0_NCISOC_DAT_ECC_DBE_ERR__ONWRITE "oneToClear" /* */
#define NV_NVLTLC_TX_SYS_ERR_STATUS_0_NCISOC_DAT_ECC_DBE_ERR_NONE 0x00000000 /* RWD-V */
#define NV_NVLTLC_TX_SYS_ERR_STATUS_0_NCISOC_DAT_ECC_DBE_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_NVLTLC_TX_SYS_ERR_STATUS_0_NCISOC_ECC_LIMIT_ERR 10:10 /* RWDVF */
#define NV_NVLTLC_TX_SYS_ERR_STATUS_0_NCISOC_ECC_LIMIT_ERR__ONWRITE "oneToClear" /* */
#define NV_NVLTLC_TX_SYS_ERR_STATUS_0_NCISOC_ECC_LIMIT_ERR_NONE 0x00000000 /* RWD-V */
#define NV_NVLTLC_TX_SYS_ERR_STATUS_0_NCISOC_ECC_LIMIT_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_NVLTLC_TX_SYS_ERR_STATUS_0_TXPOISONDET 23:23 /* RWDVF */
#define NV_NVLTLC_TX_SYS_ERR_STATUS_0_TXPOISONDET__ONWRITE "oneToClear" /* */
#define NV_NVLTLC_TX_SYS_ERR_STATUS_0_TXPOISONDET_NONE 0x00000000 /* RWD-V */
#define NV_NVLTLC_TX_SYS_ERR_STATUS_0_TXPOISONDET_CLEAR 0x00000001 /* RW--V */
#define NV_NVLTLC_TX_SYS_ERR_STATUS_0_TXRSPSTATUS_HW_ERR 24:24 /* RWDVF */
#define NV_NVLTLC_TX_SYS_ERR_STATUS_0_TXRSPSTATUS_HW_ERR__ONWRITE "oneToClear" /* */
#define NV_NVLTLC_TX_SYS_ERR_STATUS_0_TXRSPSTATUS_HW_ERR_NONE 0x00000000 /* RWD-V */
#define NV_NVLTLC_TX_SYS_ERR_STATUS_0_TXRSPSTATUS_HW_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_NVLTLC_TX_SYS_ERR_STATUS_0_TXRSPSTATUS_UR_ERR 25:25 /* RWDVF */
#define NV_NVLTLC_TX_SYS_ERR_STATUS_0_TXRSPSTATUS_UR_ERR__ONWRITE "oneToClear" /* */
#define NV_NVLTLC_TX_SYS_ERR_STATUS_0_TXRSPSTATUS_UR_ERR_NONE 0x00000000 /* RWD-V */
#define NV_NVLTLC_TX_SYS_ERR_STATUS_0_TXRSPSTATUS_UR_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_NVLTLC_TX_SYS_ERR_STATUS_0_TXRSPSTATUS_PRIV_ERR 26:26 /* RWDVF */
#define NV_NVLTLC_TX_SYS_ERR_STATUS_0_TXRSPSTATUS_PRIV_ERR__ONWRITE "oneToClear" /* */
#define NV_NVLTLC_TX_SYS_ERR_STATUS_0_TXRSPSTATUS_PRIV_ERR_NONE 0x00000000 /* RWD-V */
#define NV_NVLTLC_TX_SYS_ERR_STATUS_0_TXRSPSTATUS_PRIV_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_NVLTLC_TX_SYS_ERR_FATAL_REPORT_EN_0 0x00000288 /* RW-4R */
#define NV_NVLTLC_TX_SYS_ERR_FATAL_REPORT_EN_0_NCISOC_PARITY_ERR 0:0 /* RWEVF */
#define NV_NVLTLC_TX_SYS_ERR_FATAL_REPORT_EN_0_NCISOC_PARITY_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLTLC_TX_SYS_ERR_FATAL_REPORT_EN_0_NCISOC_PARITY_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_NVLTLC_TX_SYS_ERR_FATAL_REPORT_EN_0_NCISOC_HDR_ECC_DBE_ERR 8:8 /* RWEVF */
#define NV_NVLTLC_TX_SYS_ERR_FATAL_REPORT_EN_0_NCISOC_HDR_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLTLC_TX_SYS_ERR_FATAL_REPORT_EN_0_NCISOC_HDR_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_NVLTLC_TX_SYS_ERR_FATAL_REPORT_EN_0_NCISOC_DAT_ECC_DBE_ERR 9:9 /* RWEVF */
#define NV_NVLTLC_TX_SYS_ERR_FATAL_REPORT_EN_0_NCISOC_DAT_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLTLC_TX_SYS_ERR_FATAL_REPORT_EN_0_NCISOC_DAT_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_NVLTLC_TX_SYS_ERR_FATAL_REPORT_EN_0_NCISOC_ECC_LIMIT_ERR 10:10 /* RWEVF */
#define NV_NVLTLC_TX_SYS_ERR_FATAL_REPORT_EN_0_NCISOC_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLTLC_TX_SYS_ERR_FATAL_REPORT_EN_0_NCISOC_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_NVLTLC_TX_SYS_ERR_FATAL_REPORT_EN_0_TXPOISONDET 23:23 /* RWEVF */
#define NV_NVLTLC_TX_SYS_ERR_FATAL_REPORT_EN_0_TXPOISONDET_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLTLC_TX_SYS_ERR_FATAL_REPORT_EN_0_TXPOISONDET_ENABLE 0x00000001 /* RW--V */
#define NV_NVLTLC_TX_SYS_ERR_FATAL_REPORT_EN_0_TXRSPSTATUS_HW_ERR 24:24 /* RWEVF */
#define NV_NVLTLC_TX_SYS_ERR_FATAL_REPORT_EN_0_TXRSPSTATUS_HW_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLTLC_TX_SYS_ERR_FATAL_REPORT_EN_0_TXRSPSTATUS_HW_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_NVLTLC_TX_SYS_ERR_FATAL_REPORT_EN_0_TXRSPSTATUS_UR_ERR 25:25 /* RWEVF */
#define NV_NVLTLC_TX_SYS_ERR_FATAL_REPORT_EN_0_TXRSPSTATUS_UR_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLTLC_TX_SYS_ERR_FATAL_REPORT_EN_0_TXRSPSTATUS_UR_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_NVLTLC_TX_SYS_ERR_FATAL_REPORT_EN_0_TXRSPSTATUS_PRIV_ERR 26:26 /* RWEVF */
#define NV_NVLTLC_TX_SYS_ERR_FATAL_REPORT_EN_0_TXRSPSTATUS_PRIV_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLTLC_TX_SYS_ERR_FATAL_REPORT_EN_0_TXRSPSTATUS_PRIV_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_NVLTLC_TX_SYS_ERR_FIRST_0 0x0000029c /* RW-4R */
#define NV_NVLTLC_TX_SYS_ERR_FIRST_0_NCISOC_PARITY_ERR 0:0 /* RWDVF */
#define NV_NVLTLC_TX_SYS_ERR_FIRST_0_NCISOC_PARITY_ERR__ONWRITE "oneToClear" /* */
#define NV_NVLTLC_TX_SYS_ERR_FIRST_0_NCISOC_PARITY_ERR_NONE 0x00000000 /* RWD-V */
#define NV_NVLTLC_TX_SYS_ERR_FIRST_0_NCISOC_PARITY_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_NVLTLC_TX_SYS_ERR_FIRST_0_NCISOC_HDR_ECC_DBE_ERR 8:8 /* RWDVF */
#define NV_NVLTLC_TX_SYS_ERR_FIRST_0_NCISOC_HDR_ECC_DBE_ERR__ONWRITE "oneToClear" /* */
#define NV_NVLTLC_TX_SYS_ERR_FIRST_0_NCISOC_HDR_ECC_DBE_ERR_NONE 0x00000000 /* RWD-V */
#define NV_NVLTLC_TX_SYS_ERR_FIRST_0_NCISOC_HDR_ECC_DBE_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_NVLTLC_TX_SYS_ERR_FIRST_0_NCISOC_DAT_ECC_DBE_ERR 9:9 /* RWDVF */
#define NV_NVLTLC_TX_SYS_ERR_FIRST_0_NCISOC_DAT_ECC_DBE_ERR__ONWRITE "oneToClear" /* */
#define NV_NVLTLC_TX_SYS_ERR_FIRST_0_NCISOC_DAT_ECC_DBE_ERR_NONE 0x00000000 /* RWD-V */
#define NV_NVLTLC_TX_SYS_ERR_FIRST_0_NCISOC_DAT_ECC_DBE_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_NVLTLC_TX_SYS_ERR_FIRST_0_NCISOC_ECC_LIMIT_ERR 10:10 /* RWDVF */
#define NV_NVLTLC_TX_SYS_ERR_FIRST_0_NCISOC_ECC_LIMIT_ERR__ONWRITE "oneToClear" /* */
#define NV_NVLTLC_TX_SYS_ERR_FIRST_0_NCISOC_ECC_LIMIT_ERR_NONE 0x00000000 /* RWD-V */
#define NV_NVLTLC_TX_SYS_ERR_FIRST_0_NCISOC_ECC_LIMIT_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_NVLTLC_TX_SYS_ERR_FIRST_0_TXPOISONDET 23:23 /* RWDVF */
#define NV_NVLTLC_TX_SYS_ERR_FIRST_0_TXPOISONDET__ONWRITE "oneToClear" /* */
#define NV_NVLTLC_TX_SYS_ERR_FIRST_0_TXPOISONDET_NONE 0x00000000 /* RWD-V */
#define NV_NVLTLC_TX_SYS_ERR_FIRST_0_TXPOISONDET_CLEAR 0x00000001 /* RW--V */
#define NV_NVLTLC_TX_SYS_ERR_FIRST_0_TXRSPSTATUS_HW_ERR 24:24 /* RWDVF */
#define NV_NVLTLC_TX_SYS_ERR_FIRST_0_TXRSPSTATUS_HW_ERR__ONWRITE "oneToClear" /* */
#define NV_NVLTLC_TX_SYS_ERR_FIRST_0_TXRSPSTATUS_HW_ERR_NONE 0x00000000 /* RWD-V */
#define NV_NVLTLC_TX_SYS_ERR_FIRST_0_TXRSPSTATUS_HW_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_NVLTLC_TX_SYS_ERR_FIRST_0_TXRSPSTATUS_UR_ERR 25:25 /* RWDVF */
#define NV_NVLTLC_TX_SYS_ERR_FIRST_0_TXRSPSTATUS_UR_ERR__ONWRITE "oneToClear" /* */
#define NV_NVLTLC_TX_SYS_ERR_FIRST_0_TXRSPSTATUS_UR_ERR_NONE 0x00000000 /* RWD-V */
#define NV_NVLTLC_TX_SYS_ERR_FIRST_0_TXRSPSTATUS_UR_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_NVLTLC_TX_SYS_ERR_FIRST_0_TXRSPSTATUS_PRIV_ERR 26:26 /* RWDVF */
#define NV_NVLTLC_TX_SYS_ERR_FIRST_0_TXRSPSTATUS_PRIV_ERR__ONWRITE "oneToClear" /* */
#define NV_NVLTLC_TX_SYS_ERR_FIRST_0_TXRSPSTATUS_PRIV_ERR_NONE 0x00000000 /* RWD-V */
#define NV_NVLTLC_TX_SYS_ERR_FIRST_0_TXRSPSTATUS_PRIV_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_NVLTLC_RX_SYS_CTRL_BUFFER_READY 0x00000924 /* RW-4R */
#define NV_NVLTLC_RX_SYS_CTRL_BUFFER_READY_BUFFERRDY 0:0 /* RWEVF */
#define NV_NVLTLC_RX_SYS_CTRL_BUFFER_READY_BUFFERRDY__ONWRITE "oneToSet" /* */
#define NV_NVLTLC_RX_SYS_CTRL_BUFFER_READY_BUFFERRDY_ENABLE 0x00000001 /* RW--V */
#define NV_NVLTLC_RX_SYS_CTRL_BUFFER_READY_BUFFERRDY_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLTLC_RX_SYS_ERR_STATUS_0 0x00000a80 /* RW-4R */
#define NV_NVLTLC_RX_SYS_ERR_STATUS_0_NCISOC_PARITY_ERR 0:0 /* RWDVF */
#define NV_NVLTLC_RX_SYS_ERR_STATUS_0_NCISOC_PARITY_ERR__ONWRITE "oneToClear" /* */
#define NV_NVLTLC_RX_SYS_ERR_STATUS_0_NCISOC_PARITY_ERR_NONE 0x00000000 /* RWD-V */
#define NV_NVLTLC_RX_SYS_ERR_STATUS_0_NCISOC_PARITY_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_NVLTLC_RX_SYS_ERR_STATUS_0_HDR_RAM_ECC_DBE_ERR 1:1 /* RWDVF */
#define NV_NVLTLC_RX_SYS_ERR_STATUS_0_HDR_RAM_ECC_DBE_ERR__ONWRITE "oneToClear" /* */
#define NV_NVLTLC_RX_SYS_ERR_STATUS_0_HDR_RAM_ECC_DBE_ERR_NONE 0x00000000 /* RWD-V */
#define NV_NVLTLC_RX_SYS_ERR_STATUS_0_HDR_RAM_ECC_DBE_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_NVLTLC_RX_SYS_ERR_STATUS_0_HDR_RAM_ECC_LIMIT_ERR 2:2 /* RWDVF */
#define NV_NVLTLC_RX_SYS_ERR_STATUS_0_HDR_RAM_ECC_LIMIT_ERR__ONWRITE "oneToClear" /* */
#define NV_NVLTLC_RX_SYS_ERR_STATUS_0_HDR_RAM_ECC_LIMIT_ERR_NONE 0x00000000 /* RWD-V */
#define NV_NVLTLC_RX_SYS_ERR_STATUS_0_HDR_RAM_ECC_LIMIT_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_NVLTLC_RX_SYS_ERR_STATUS_0_DAT0_RAM_ECC_DBE_ERR 3:3 /* RWDVF */
#define NV_NVLTLC_RX_SYS_ERR_STATUS_0_DAT0_RAM_ECC_DBE_ERR__ONWRITE "oneToClear" /* */
#define NV_NVLTLC_RX_SYS_ERR_STATUS_0_DAT0_RAM_ECC_DBE_ERR_NONE 0x00000000 /* RWD-V */
#define NV_NVLTLC_RX_SYS_ERR_STATUS_0_DAT0_RAM_ECC_DBE_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_NVLTLC_RX_SYS_ERR_STATUS_0_DAT0_RAM_ECC_LIMIT_ERR 4:4 /* RWDVF */
#define NV_NVLTLC_RX_SYS_ERR_STATUS_0_DAT0_RAM_ECC_LIMIT_ERR__ONWRITE "oneToClear" /* */
#define NV_NVLTLC_RX_SYS_ERR_STATUS_0_DAT0_RAM_ECC_LIMIT_ERR_NONE 0x00000000 /* RWD-V */
#define NV_NVLTLC_RX_SYS_ERR_STATUS_0_DAT0_RAM_ECC_LIMIT_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_NVLTLC_RX_SYS_ERR_STATUS_0_DAT1_RAM_ECC_DBE_ERR 5:5 /* RWDVF */
#define NV_NVLTLC_RX_SYS_ERR_STATUS_0_DAT1_RAM_ECC_DBE_ERR__ONWRITE "oneToClear" /* */
#define NV_NVLTLC_RX_SYS_ERR_STATUS_0_DAT1_RAM_ECC_DBE_ERR_NONE 0x00000000 /* RWD-V */
#define NV_NVLTLC_RX_SYS_ERR_STATUS_0_DAT1_RAM_ECC_DBE_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_NVLTLC_RX_SYS_ERR_STATUS_0_DAT1_RAM_ECC_LIMIT_ERR 6:6 /* RWDVF */
#define NV_NVLTLC_RX_SYS_ERR_STATUS_0_DAT1_RAM_ECC_LIMIT_ERR__ONWRITE "oneToClear" /* */
#define NV_NVLTLC_RX_SYS_ERR_STATUS_0_DAT1_RAM_ECC_LIMIT_ERR_NONE 0x00000000 /* RWD-V */
#define NV_NVLTLC_RX_SYS_ERR_STATUS_0_DAT1_RAM_ECC_LIMIT_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_NVLTLC_RX_SYS_ERR_FATAL_REPORT_EN_0 0x00000a88 /* RW-4R */
#define NV_NVLTLC_RX_SYS_ERR_FATAL_REPORT_EN_0_NCISOC_PARITY_ERR 0:0 /* RWEVF */
#define NV_NVLTLC_RX_SYS_ERR_FATAL_REPORT_EN_0_NCISOC_PARITY_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLTLC_RX_SYS_ERR_FATAL_REPORT_EN_0_NCISOC_PARITY_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_NVLTLC_RX_SYS_ERR_FATAL_REPORT_EN_0_HDR_RAM_ECC_DBE_ERR 1:1 /* RWEVF */
#define NV_NVLTLC_RX_SYS_ERR_FATAL_REPORT_EN_0_HDR_RAM_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLTLC_RX_SYS_ERR_FATAL_REPORT_EN_0_HDR_RAM_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_NVLTLC_RX_SYS_ERR_FATAL_REPORT_EN_0_HDR_RAM_ECC_LIMIT_ERR 2:2 /* RWEVF */
#define NV_NVLTLC_RX_SYS_ERR_FATAL_REPORT_EN_0_HDR_RAM_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLTLC_RX_SYS_ERR_FATAL_REPORT_EN_0_HDR_RAM_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_NVLTLC_RX_SYS_ERR_FATAL_REPORT_EN_0_DAT0_RAM_ECC_DBE_ERR 3:3 /* RWEVF */
#define NV_NVLTLC_RX_SYS_ERR_FATAL_REPORT_EN_0_DAT0_RAM_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLTLC_RX_SYS_ERR_FATAL_REPORT_EN_0_DAT0_RAM_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_NVLTLC_RX_SYS_ERR_FATAL_REPORT_EN_0_DAT0_RAM_ECC_LIMIT_ERR 4:4 /* RWEVF */
#define NV_NVLTLC_RX_SYS_ERR_FATAL_REPORT_EN_0_DAT0_RAM_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLTLC_RX_SYS_ERR_FATAL_REPORT_EN_0_DAT0_RAM_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_NVLTLC_RX_SYS_ERR_FATAL_REPORT_EN_0_DAT1_RAM_ECC_DBE_ERR 5:5 /* RWEVF */
#define NV_NVLTLC_RX_SYS_ERR_FATAL_REPORT_EN_0_DAT1_RAM_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLTLC_RX_SYS_ERR_FATAL_REPORT_EN_0_DAT1_RAM_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_NVLTLC_RX_SYS_ERR_FATAL_REPORT_EN_0_DAT1_RAM_ECC_LIMIT_ERR 6:6 /* RWEVF */
#define NV_NVLTLC_RX_SYS_ERR_FATAL_REPORT_EN_0_DAT1_RAM_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLTLC_RX_SYS_ERR_FATAL_REPORT_EN_0_DAT1_RAM_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_NVLTLC_RX_SYS_ERR_FIRST_0 0x00000a9c /* RW-4R */
#define NV_NVLTLC_RX_SYS_ERR_FIRST_0_NCISOC_PARITY_ERR 0:0 /* RWDVF */
#define NV_NVLTLC_RX_SYS_ERR_FIRST_0_NCISOC_PARITY_ERR__ONWRITE "oneToClear" /* */
#define NV_NVLTLC_RX_SYS_ERR_FIRST_0_NCISOC_PARITY_ERR_NONE 0x00000000 /* RWD-V */
#define NV_NVLTLC_RX_SYS_ERR_FIRST_0_NCISOC_PARITY_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_NVLTLC_RX_SYS_ERR_FIRST_0_HDR_RAM_ECC_DBE_ERR 1:1 /* RWDVF */
#define NV_NVLTLC_RX_SYS_ERR_FIRST_0_HDR_RAM_ECC_DBE_ERR__ONWRITE "oneToClear" /* */
#define NV_NVLTLC_RX_SYS_ERR_FIRST_0_HDR_RAM_ECC_DBE_ERR_NONE 0x00000000 /* RWD-V */
#define NV_NVLTLC_RX_SYS_ERR_FIRST_0_HDR_RAM_ECC_DBE_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_NVLTLC_RX_SYS_ERR_FIRST_0_HDR_RAM_ECC_LIMIT_ERR 2:2 /* RWDVF */
#define NV_NVLTLC_RX_SYS_ERR_FIRST_0_HDR_RAM_ECC_LIMIT_ERR__ONWRITE "oneToClear" /* */
#define NV_NVLTLC_RX_SYS_ERR_FIRST_0_HDR_RAM_ECC_LIMIT_ERR_NONE 0x00000000 /* RWD-V */
#define NV_NVLTLC_RX_SYS_ERR_FIRST_0_HDR_RAM_ECC_LIMIT_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_NVLTLC_RX_SYS_ERR_FIRST_0_DAT0_RAM_ECC_DBE_ERR 3:3 /* RWDVF */
#define NV_NVLTLC_RX_SYS_ERR_FIRST_0_DAT0_RAM_ECC_DBE_ERR__ONWRITE "oneToClear" /* */
#define NV_NVLTLC_RX_SYS_ERR_FIRST_0_DAT0_RAM_ECC_DBE_ERR_NONE 0x00000000 /* RWD-V */
#define NV_NVLTLC_RX_SYS_ERR_FIRST_0_DAT0_RAM_ECC_DBE_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_NVLTLC_RX_SYS_ERR_FIRST_0_DAT0_RAM_ECC_LIMIT_ERR 4:4 /* RWDVF */
#define NV_NVLTLC_RX_SYS_ERR_FIRST_0_DAT0_RAM_ECC_LIMIT_ERR__ONWRITE "oneToClear" /* */
#define NV_NVLTLC_RX_SYS_ERR_FIRST_0_DAT0_RAM_ECC_LIMIT_ERR_NONE 0x00000000 /* RWD-V */
#define NV_NVLTLC_RX_SYS_ERR_FIRST_0_DAT0_RAM_ECC_LIMIT_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_NVLTLC_RX_SYS_ERR_FIRST_0_DAT1_RAM_ECC_DBE_ERR 5:5 /* RWDVF */
#define NV_NVLTLC_RX_SYS_ERR_FIRST_0_DAT1_RAM_ECC_DBE_ERR__ONWRITE "oneToClear" /* */
#define NV_NVLTLC_RX_SYS_ERR_FIRST_0_DAT1_RAM_ECC_DBE_ERR_NONE 0x00000000 /* RWD-V */
#define NV_NVLTLC_RX_SYS_ERR_FIRST_0_DAT1_RAM_ECC_DBE_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_NVLTLC_RX_SYS_ERR_FIRST_0_DAT1_RAM_ECC_LIMIT_ERR 6:6 /* RWDVF */
#define NV_NVLTLC_RX_SYS_ERR_FIRST_0_DAT1_RAM_ECC_LIMIT_ERR__ONWRITE "oneToClear" /* */
#define NV_NVLTLC_RX_SYS_ERR_FIRST_0_DAT1_RAM_ECC_LIMIT_ERR_NONE 0x00000000 /* RWD-V */
#define NV_NVLTLC_RX_SYS_ERR_FIRST_0_DAT1_RAM_ECC_LIMIT_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_NVLTLC_TX_LNK_ERR_STATUS_0 0x00001280 /* RW-4R */
#define NV_NVLTLC_TX_LNK_ERR_STATUS_0_TXDLCREDITPARITYERR 17:17 /* RWDVF */
#define NV_NVLTLC_TX_LNK_ERR_STATUS_0_TXDLCREDITPARITYERR__ONWRITE "oneToClear" /* */
#define NV_NVLTLC_TX_LNK_ERR_STATUS_0_TXDLCREDITPARITYERR_NONE 0x00000000 /* RWD-V */
#define NV_NVLTLC_TX_LNK_ERR_STATUS_0_TXDLCREDITPARITYERR_CLEAR 0x00000001 /* RW--V */
#define NV_NVLTLC_TX_LNK_ERR_STATUS_0_CREQ_RAM_HDR_ECC_DBE_ERR 18:18 /* RWDVF */
#define NV_NVLTLC_TX_LNK_ERR_STATUS_0_CREQ_RAM_HDR_ECC_DBE_ERR__ONWRITE "oneToClear" /* */
#define NV_NVLTLC_TX_LNK_ERR_STATUS_0_CREQ_RAM_HDR_ECC_DBE_ERR_NONE 0x00000000 /* RWD-V */
#define NV_NVLTLC_TX_LNK_ERR_STATUS_0_CREQ_RAM_HDR_ECC_DBE_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_NVLTLC_TX_LNK_ERR_STATUS_0_CREQ_RAM_DAT_ECC_DBE_ERR 19:19 /* RWDVF */
#define NV_NVLTLC_TX_LNK_ERR_STATUS_0_CREQ_RAM_DAT_ECC_DBE_ERR__ONWRITE "oneToClear" /* */
#define NV_NVLTLC_TX_LNK_ERR_STATUS_0_CREQ_RAM_DAT_ECC_DBE_ERR_NONE 0x00000000 /* RWD-V */
#define NV_NVLTLC_TX_LNK_ERR_STATUS_0_CREQ_RAM_DAT_ECC_DBE_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_NVLTLC_TX_LNK_ERR_STATUS_0_CREQ_RAM_ECC_LIMIT_ERR 20:20 /* RWDVF */
#define NV_NVLTLC_TX_LNK_ERR_STATUS_0_CREQ_RAM_ECC_LIMIT_ERR__ONWRITE "oneToClear" /* */
#define NV_NVLTLC_TX_LNK_ERR_STATUS_0_CREQ_RAM_ECC_LIMIT_ERR_NONE 0x00000000 /* RWD-V */
#define NV_NVLTLC_TX_LNK_ERR_STATUS_0_CREQ_RAM_ECC_LIMIT_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_NVLTLC_TX_LNK_ERR_STATUS_0_RSP_RAM_HDR_ECC_DBE_ERR 21:21 /* RWDVF */
#define NV_NVLTLC_TX_LNK_ERR_STATUS_0_RSP_RAM_HDR_ECC_DBE_ERR__ONWRITE "oneToClear" /* */
#define NV_NVLTLC_TX_LNK_ERR_STATUS_0_RSP_RAM_HDR_ECC_DBE_ERR_NONE 0x00000000 /* RWD-V */
#define NV_NVLTLC_TX_LNK_ERR_STATUS_0_RSP_RAM_HDR_ECC_DBE_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_NVLTLC_TX_LNK_ERR_STATUS_0_RSP_RAM_DAT_ECC_DBE_ERR 22:22 /* RWDVF */
#define NV_NVLTLC_TX_LNK_ERR_STATUS_0_RSP_RAM_DAT_ECC_DBE_ERR__ONWRITE "oneToClear" /* */
#define NV_NVLTLC_TX_LNK_ERR_STATUS_0_RSP_RAM_DAT_ECC_DBE_ERR_NONE 0x00000000 /* RWD-V */
#define NV_NVLTLC_TX_LNK_ERR_STATUS_0_RSP_RAM_DAT_ECC_DBE_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_NVLTLC_TX_LNK_ERR_STATUS_0_RSP_RAM_ECC_LIMIT_ERR 23:23 /* RWDVF */
#define NV_NVLTLC_TX_LNK_ERR_STATUS_0_RSP_RAM_ECC_LIMIT_ERR__ONWRITE "oneToClear" /* */
#define NV_NVLTLC_TX_LNK_ERR_STATUS_0_RSP_RAM_ECC_LIMIT_ERR_NONE 0x00000000 /* RWD-V */
#define NV_NVLTLC_TX_LNK_ERR_STATUS_0_RSP_RAM_ECC_LIMIT_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_NVLTLC_TX_LNK_ERR_STATUS_0_COM_RAM_HDR_ECC_DBE_ERR 24:24 /* RWDVF */
#define NV_NVLTLC_TX_LNK_ERR_STATUS_0_COM_RAM_HDR_ECC_DBE_ERR__ONWRITE "oneToClear" /* */
#define NV_NVLTLC_TX_LNK_ERR_STATUS_0_COM_RAM_HDR_ECC_DBE_ERR_NONE 0x00000000 /* RWD-V */
#define NV_NVLTLC_TX_LNK_ERR_STATUS_0_COM_RAM_HDR_ECC_DBE_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_NVLTLC_TX_LNK_ERR_STATUS_0_COM_RAM_DAT_ECC_DBE_ERR 25:25 /* RWDVF */
#define NV_NVLTLC_TX_LNK_ERR_STATUS_0_COM_RAM_DAT_ECC_DBE_ERR__ONWRITE "oneToClear" /* */
#define NV_NVLTLC_TX_LNK_ERR_STATUS_0_COM_RAM_DAT_ECC_DBE_ERR_NONE 0x00000000 /* RWD-V */
#define NV_NVLTLC_TX_LNK_ERR_STATUS_0_COM_RAM_DAT_ECC_DBE_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_NVLTLC_TX_LNK_ERR_STATUS_0_COM_RAM_ECC_LIMIT_ERR 26:26 /* RWDVF */
#define NV_NVLTLC_TX_LNK_ERR_STATUS_0_COM_RAM_ECC_LIMIT_ERR__ONWRITE "oneToClear" /* */
#define NV_NVLTLC_TX_LNK_ERR_STATUS_0_COM_RAM_ECC_LIMIT_ERR_NONE 0x00000000 /* RWD-V */
#define NV_NVLTLC_TX_LNK_ERR_STATUS_0_COM_RAM_ECC_LIMIT_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_NVLTLC_TX_LNK_ERR_STATUS_0_RSP1_RAM_HDR_ECC_DBE_ERR 27:27 /* RWDVF */
#define NV_NVLTLC_TX_LNK_ERR_STATUS_0_RSP1_RAM_HDR_ECC_DBE_ERR__ONWRITE "oneToClear" /* */
#define NV_NVLTLC_TX_LNK_ERR_STATUS_0_RSP1_RAM_HDR_ECC_DBE_ERR_NONE 0x00000000 /* RWD-V */
#define NV_NVLTLC_TX_LNK_ERR_STATUS_0_RSP1_RAM_HDR_ECC_DBE_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_NVLTLC_TX_LNK_ERR_STATUS_0_RSP1_RAM_DAT_ECC_DBE_ERR 28:28 /* RWDVF */
#define NV_NVLTLC_TX_LNK_ERR_STATUS_0_RSP1_RAM_DAT_ECC_DBE_ERR__ONWRITE "oneToClear" /* */
#define NV_NVLTLC_TX_LNK_ERR_STATUS_0_RSP1_RAM_DAT_ECC_DBE_ERR_NONE 0x00000000 /* RWD-V */
#define NV_NVLTLC_TX_LNK_ERR_STATUS_0_RSP1_RAM_DAT_ECC_DBE_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_NVLTLC_TX_LNK_ERR_STATUS_0_RSP1_RAM_ECC_LIMIT_ERR 29:29 /* RWDVF */
#define NV_NVLTLC_TX_LNK_ERR_STATUS_0_RSP1_RAM_ECC_LIMIT_ERR__ONWRITE "oneToClear" /* */
#define NV_NVLTLC_TX_LNK_ERR_STATUS_0_RSP1_RAM_ECC_LIMIT_ERR_NONE 0x00000000 /* RWD-V */
#define NV_NVLTLC_TX_LNK_ERR_STATUS_0_RSP1_RAM_ECC_LIMIT_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_NVLTLC_TX_LNK_ERR_FATAL_REPORT_EN_0 0x00001288 /* RW-4R */
#define NV_NVLTLC_TX_LNK_ERR_FATAL_REPORT_EN_0_TXDLCREDITPARITYERR 17:17 /* RWEVF */
#define NV_NVLTLC_TX_LNK_ERR_FATAL_REPORT_EN_0_TXDLCREDITPARITYERR_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLTLC_TX_LNK_ERR_FATAL_REPORT_EN_0_TXDLCREDITPARITYERR_ENABLE 0x00000001 /* RW--V */
#define NV_NVLTLC_TX_LNK_ERR_FATAL_REPORT_EN_0_CREQ_RAM_HDR_ECC_DBE_ERR 18:18 /* RWEVF */
#define NV_NVLTLC_TX_LNK_ERR_FATAL_REPORT_EN_0_CREQ_RAM_HDR_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLTLC_TX_LNK_ERR_FATAL_REPORT_EN_0_CREQ_RAM_HDR_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_NVLTLC_TX_LNK_ERR_FATAL_REPORT_EN_0_CREQ_RAM_DAT_ECC_DBE_ERR 19:19 /* RWEVF */
#define NV_NVLTLC_TX_LNK_ERR_FATAL_REPORT_EN_0_CREQ_RAM_DAT_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLTLC_TX_LNK_ERR_FATAL_REPORT_EN_0_CREQ_RAM_DAT_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_NVLTLC_TX_LNK_ERR_FATAL_REPORT_EN_0_CREQ_RAM_ECC_LIMIT_ERR 20:20 /* RWEVF */
#define NV_NVLTLC_TX_LNK_ERR_FATAL_REPORT_EN_0_CREQ_RAM_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLTLC_TX_LNK_ERR_FATAL_REPORT_EN_0_CREQ_RAM_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_NVLTLC_TX_LNK_ERR_FATAL_REPORT_EN_0_RSP_RAM_HDR_ECC_DBE_ERR 21:21 /* RWEVF */
#define NV_NVLTLC_TX_LNK_ERR_FATAL_REPORT_EN_0_RSP_RAM_HDR_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLTLC_TX_LNK_ERR_FATAL_REPORT_EN_0_RSP_RAM_HDR_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_NVLTLC_TX_LNK_ERR_FATAL_REPORT_EN_0_RSP_RAM_DAT_ECC_DBE_ERR 22:22 /* RWEVF */
#define NV_NVLTLC_TX_LNK_ERR_FATAL_REPORT_EN_0_RSP_RAM_DAT_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLTLC_TX_LNK_ERR_FATAL_REPORT_EN_0_RSP_RAM_DAT_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_NVLTLC_TX_LNK_ERR_FATAL_REPORT_EN_0_RSP_RAM_ECC_LIMIT_ERR 23:23 /* RWEVF */
#define NV_NVLTLC_TX_LNK_ERR_FATAL_REPORT_EN_0_RSP_RAM_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLTLC_TX_LNK_ERR_FATAL_REPORT_EN_0_RSP_RAM_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_NVLTLC_TX_LNK_ERR_FATAL_REPORT_EN_0_COM_RAM_HDR_ECC_DBE_ERR 24:24 /* RWEVF */
#define NV_NVLTLC_TX_LNK_ERR_FATAL_REPORT_EN_0_COM_RAM_HDR_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLTLC_TX_LNK_ERR_FATAL_REPORT_EN_0_COM_RAM_HDR_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_NVLTLC_TX_LNK_ERR_FATAL_REPORT_EN_0_COM_RAM_DAT_ECC_DBE_ERR 25:25 /* RWEVF */
#define NV_NVLTLC_TX_LNK_ERR_FATAL_REPORT_EN_0_COM_RAM_DAT_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLTLC_TX_LNK_ERR_FATAL_REPORT_EN_0_COM_RAM_DAT_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_NVLTLC_TX_LNK_ERR_FATAL_REPORT_EN_0_COM_RAM_ECC_LIMIT_ERR 26:26 /* RWEVF */
#define NV_NVLTLC_TX_LNK_ERR_FATAL_REPORT_EN_0_COM_RAM_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLTLC_TX_LNK_ERR_FATAL_REPORT_EN_0_COM_RAM_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_NVLTLC_TX_LNK_ERR_FATAL_REPORT_EN_0_RSP1_RAM_HDR_ECC_DBE_ERR 27:27 /* RWEVF */
#define NV_NVLTLC_TX_LNK_ERR_FATAL_REPORT_EN_0_RSP1_RAM_HDR_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLTLC_TX_LNK_ERR_FATAL_REPORT_EN_0_RSP1_RAM_HDR_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_NVLTLC_TX_LNK_ERR_FATAL_REPORT_EN_0_RSP1_RAM_DAT_ECC_DBE_ERR 28:28 /* RWEVF */
#define NV_NVLTLC_TX_LNK_ERR_FATAL_REPORT_EN_0_RSP1_RAM_DAT_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLTLC_TX_LNK_ERR_FATAL_REPORT_EN_0_RSP1_RAM_DAT_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_NVLTLC_TX_LNK_ERR_FATAL_REPORT_EN_0_RSP1_RAM_ECC_LIMIT_ERR 29:29 /* RWEVF */
#define NV_NVLTLC_TX_LNK_ERR_FATAL_REPORT_EN_0_RSP1_RAM_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLTLC_TX_LNK_ERR_FATAL_REPORT_EN_0_RSP1_RAM_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_NVLTLC_TX_LNK_ERR_NON_FATAL_REPORT_EN_0 0x0000128c /* RW-4R */
#define NV_NVLTLC_TX_LNK_ERR_NON_FATAL_REPORT_EN_0_TXDLCREDITPARITYERR 17:17 /* RWEVF */
#define NV_NVLTLC_TX_LNK_ERR_NON_FATAL_REPORT_EN_0_TXDLCREDITPARITYERR_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLTLC_TX_LNK_ERR_NON_FATAL_REPORT_EN_0_TXDLCREDITPARITYERR_ENABLE 0x00000001 /* RW--V */
#define NV_NVLTLC_TX_LNK_ERR_NON_FATAL_REPORT_EN_0_CREQ_RAM_HDR_ECC_DBE_ERR 18:18 /* RWEVF */
#define NV_NVLTLC_TX_LNK_ERR_NON_FATAL_REPORT_EN_0_CREQ_RAM_HDR_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLTLC_TX_LNK_ERR_NON_FATAL_REPORT_EN_0_CREQ_RAM_HDR_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_NVLTLC_TX_LNK_ERR_NON_FATAL_REPORT_EN_0_CREQ_RAM_DAT_ECC_DBE_ERR 19:19 /* RWEVF */
#define NV_NVLTLC_TX_LNK_ERR_NON_FATAL_REPORT_EN_0_CREQ_RAM_DAT_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLTLC_TX_LNK_ERR_NON_FATAL_REPORT_EN_0_CREQ_RAM_DAT_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_NVLTLC_TX_LNK_ERR_NON_FATAL_REPORT_EN_0_CREQ_RAM_ECC_LIMIT_ERR 20:20 /* RWEVF */
#define NV_NVLTLC_TX_LNK_ERR_NON_FATAL_REPORT_EN_0_CREQ_RAM_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLTLC_TX_LNK_ERR_NON_FATAL_REPORT_EN_0_CREQ_RAM_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_NVLTLC_TX_LNK_ERR_NON_FATAL_REPORT_EN_0_RSP_RAM_HDR_ECC_DBE_ERR 21:21 /* RWEVF */
#define NV_NVLTLC_TX_LNK_ERR_NON_FATAL_REPORT_EN_0_RSP_RAM_HDR_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLTLC_TX_LNK_ERR_NON_FATAL_REPORT_EN_0_RSP_RAM_HDR_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_NVLTLC_TX_LNK_ERR_NON_FATAL_REPORT_EN_0_RSP_RAM_DAT_ECC_DBE_ERR 22:22 /* RWEVF */
#define NV_NVLTLC_TX_LNK_ERR_NON_FATAL_REPORT_EN_0_RSP_RAM_DAT_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLTLC_TX_LNK_ERR_NON_FATAL_REPORT_EN_0_RSP_RAM_DAT_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_NVLTLC_TX_LNK_ERR_NON_FATAL_REPORT_EN_0_RSP_RAM_ECC_LIMIT_ERR 23:23 /* RWEVF */
#define NV_NVLTLC_TX_LNK_ERR_NON_FATAL_REPORT_EN_0_RSP_RAM_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLTLC_TX_LNK_ERR_NON_FATAL_REPORT_EN_0_RSP_RAM_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_NVLTLC_TX_LNK_ERR_NON_FATAL_REPORT_EN_0_COM_RAM_HDR_ECC_DBE_ERR 24:24 /* RWEVF */
#define NV_NVLTLC_TX_LNK_ERR_NON_FATAL_REPORT_EN_0_COM_RAM_HDR_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLTLC_TX_LNK_ERR_NON_FATAL_REPORT_EN_0_COM_RAM_HDR_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_NVLTLC_TX_LNK_ERR_NON_FATAL_REPORT_EN_0_COM_RAM_DAT_ECC_DBE_ERR 25:25 /* RWEVF */
#define NV_NVLTLC_TX_LNK_ERR_NON_FATAL_REPORT_EN_0_COM_RAM_DAT_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLTLC_TX_LNK_ERR_NON_FATAL_REPORT_EN_0_COM_RAM_DAT_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_NVLTLC_TX_LNK_ERR_NON_FATAL_REPORT_EN_0_COM_RAM_ECC_LIMIT_ERR 26:26 /* RWEVF */
#define NV_NVLTLC_TX_LNK_ERR_NON_FATAL_REPORT_EN_0_COM_RAM_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLTLC_TX_LNK_ERR_NON_FATAL_REPORT_EN_0_COM_RAM_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_NVLTLC_TX_LNK_ERR_NON_FATAL_REPORT_EN_0_RSP1_RAM_HDR_ECC_DBE_ERR 27:27 /* RWEVF */
#define NV_NVLTLC_TX_LNK_ERR_NON_FATAL_REPORT_EN_0_RSP1_RAM_HDR_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLTLC_TX_LNK_ERR_NON_FATAL_REPORT_EN_0_RSP1_RAM_HDR_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_NVLTLC_TX_LNK_ERR_NON_FATAL_REPORT_EN_0_RSP1_RAM_DAT_ECC_DBE_ERR 28:28 /* RWEVF */
#define NV_NVLTLC_TX_LNK_ERR_NON_FATAL_REPORT_EN_0_RSP1_RAM_DAT_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLTLC_TX_LNK_ERR_NON_FATAL_REPORT_EN_0_RSP1_RAM_DAT_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_NVLTLC_TX_LNK_ERR_NON_FATAL_REPORT_EN_0_RSP1_RAM_ECC_LIMIT_ERR 29:29 /* RWEVF */
#define NV_NVLTLC_TX_LNK_ERR_NON_FATAL_REPORT_EN_0_RSP1_RAM_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLTLC_TX_LNK_ERR_NON_FATAL_REPORT_EN_0_RSP1_RAM_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_NVLTLC_TX_LNK_ERR_FIRST_0 0x0000129c /* RW-4R */
#define NV_NVLTLC_TX_LNK_ERR_FIRST_0_TXDLCREDITPARITYERR 17:17 /* RWDVF */
#define NV_NVLTLC_TX_LNK_ERR_FIRST_0_TXDLCREDITPARITYERR__ONWRITE "oneToClear" /* */
#define NV_NVLTLC_TX_LNK_ERR_FIRST_0_TXDLCREDITPARITYERR_NONE 0x00000000 /* RWD-V */
#define NV_NVLTLC_TX_LNK_ERR_FIRST_0_TXDLCREDITPARITYERR_CLEAR 0x00000001 /* RW--V */
#define NV_NVLTLC_TX_LNK_ERR_FIRST_0_CREQ_RAM_HDR_ECC_DBE_ERR 18:18 /* RWDVF */
#define NV_NVLTLC_TX_LNK_ERR_FIRST_0_CREQ_RAM_HDR_ECC_DBE_ERR__ONWRITE "oneToClear" /* */
#define NV_NVLTLC_TX_LNK_ERR_FIRST_0_CREQ_RAM_HDR_ECC_DBE_ERR_NONE 0x00000000 /* RWD-V */
#define NV_NVLTLC_TX_LNK_ERR_FIRST_0_CREQ_RAM_HDR_ECC_DBE_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_NVLTLC_TX_LNK_ERR_FIRST_0_CREQ_RAM_DAT_ECC_DBE_ERR 19:19 /* RWDVF */
#define NV_NVLTLC_TX_LNK_ERR_FIRST_0_CREQ_RAM_DAT_ECC_DBE_ERR__ONWRITE "oneToClear" /* */
#define NV_NVLTLC_TX_LNK_ERR_FIRST_0_CREQ_RAM_DAT_ECC_DBE_ERR_NONE 0x00000000 /* RWD-V */
#define NV_NVLTLC_TX_LNK_ERR_FIRST_0_CREQ_RAM_DAT_ECC_DBE_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_NVLTLC_TX_LNK_ERR_FIRST_0_CREQ_RAM_ECC_LIMIT_ERR 20:20 /* RWDVF */
#define NV_NVLTLC_TX_LNK_ERR_FIRST_0_CREQ_RAM_ECC_LIMIT_ERR__ONWRITE "oneToClear" /* */
#define NV_NVLTLC_TX_LNK_ERR_FIRST_0_CREQ_RAM_ECC_LIMIT_ERR_NONE 0x00000000 /* RWD-V */
#define NV_NVLTLC_TX_LNK_ERR_FIRST_0_CREQ_RAM_ECC_LIMIT_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_NVLTLC_TX_LNK_ERR_FIRST_0_RSP_RAM_HDR_ECC_DBE_ERR 21:21 /* RWDVF */
#define NV_NVLTLC_TX_LNK_ERR_FIRST_0_RSP_RAM_HDR_ECC_DBE_ERR__ONWRITE "oneToClear" /* */
#define NV_NVLTLC_TX_LNK_ERR_FIRST_0_RSP_RAM_HDR_ECC_DBE_ERR_NONE 0x00000000 /* RWD-V */
#define NV_NVLTLC_TX_LNK_ERR_FIRST_0_RSP_RAM_HDR_ECC_DBE_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_NVLTLC_TX_LNK_ERR_FIRST_0_RSP_RAM_DAT_ECC_DBE_ERR 22:22 /* RWDVF */
#define NV_NVLTLC_TX_LNK_ERR_FIRST_0_RSP_RAM_DAT_ECC_DBE_ERR__ONWRITE "oneToClear" /* */
#define NV_NVLTLC_TX_LNK_ERR_FIRST_0_RSP_RAM_DAT_ECC_DBE_ERR_NONE 0x00000000 /* RWD-V */
#define NV_NVLTLC_TX_LNK_ERR_FIRST_0_RSP_RAM_DAT_ECC_DBE_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_NVLTLC_TX_LNK_ERR_FIRST_0_RSP_RAM_ECC_LIMIT_ERR 23:23 /* RWDVF */
#define NV_NVLTLC_TX_LNK_ERR_FIRST_0_RSP_RAM_ECC_LIMIT_ERR__ONWRITE "oneToClear" /* */
#define NV_NVLTLC_TX_LNK_ERR_FIRST_0_RSP_RAM_ECC_LIMIT_ERR_NONE 0x00000000 /* RWD-V */
#define NV_NVLTLC_TX_LNK_ERR_FIRST_0_RSP_RAM_ECC_LIMIT_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_NVLTLC_TX_LNK_ERR_FIRST_0_COM_RAM_HDR_ECC_DBE_ERR 24:24 /* RWDVF */
#define NV_NVLTLC_TX_LNK_ERR_FIRST_0_COM_RAM_HDR_ECC_DBE_ERR__ONWRITE "oneToClear" /* */
#define NV_NVLTLC_TX_LNK_ERR_FIRST_0_COM_RAM_HDR_ECC_DBE_ERR_NONE 0x00000000 /* RWD-V */
#define NV_NVLTLC_TX_LNK_ERR_FIRST_0_COM_RAM_HDR_ECC_DBE_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_NVLTLC_TX_LNK_ERR_FIRST_0_COM_RAM_DAT_ECC_DBE_ERR 25:25 /* RWDVF */
#define NV_NVLTLC_TX_LNK_ERR_FIRST_0_COM_RAM_DAT_ECC_DBE_ERR__ONWRITE "oneToClear" /* */
#define NV_NVLTLC_TX_LNK_ERR_FIRST_0_COM_RAM_DAT_ECC_DBE_ERR_NONE 0x00000000 /* RWD-V */
#define NV_NVLTLC_TX_LNK_ERR_FIRST_0_COM_RAM_DAT_ECC_DBE_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_NVLTLC_TX_LNK_ERR_FIRST_0_COM_RAM_ECC_LIMIT_ERR 26:26 /* RWDVF */
#define NV_NVLTLC_TX_LNK_ERR_FIRST_0_COM_RAM_ECC_LIMIT_ERR__ONWRITE "oneToClear" /* */
#define NV_NVLTLC_TX_LNK_ERR_FIRST_0_COM_RAM_ECC_LIMIT_ERR_NONE 0x00000000 /* RWD-V */
#define NV_NVLTLC_TX_LNK_ERR_FIRST_0_COM_RAM_ECC_LIMIT_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_NVLTLC_TX_LNK_ERR_FIRST_0_RSP1_RAM_HDR_ECC_DBE_ERR 27:27 /* RWDVF */
#define NV_NVLTLC_TX_LNK_ERR_FIRST_0_RSP1_RAM_HDR_ECC_DBE_ERR__ONWRITE "oneToClear" /* */
#define NV_NVLTLC_TX_LNK_ERR_FIRST_0_RSP1_RAM_HDR_ECC_DBE_ERR_NONE 0x00000000 /* RWD-V */
#define NV_NVLTLC_TX_LNK_ERR_FIRST_0_RSP1_RAM_HDR_ECC_DBE_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_NVLTLC_TX_LNK_ERR_FIRST_0_RSP1_RAM_DAT_ECC_DBE_ERR 28:28 /* RWDVF */
#define NV_NVLTLC_TX_LNK_ERR_FIRST_0_RSP1_RAM_DAT_ECC_DBE_ERR__ONWRITE "oneToClear" /* */
#define NV_NVLTLC_TX_LNK_ERR_FIRST_0_RSP1_RAM_DAT_ECC_DBE_ERR_NONE 0x00000000 /* RWD-V */
#define NV_NVLTLC_TX_LNK_ERR_FIRST_0_RSP1_RAM_DAT_ECC_DBE_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_NVLTLC_TX_LNK_ERR_FIRST_0_RSP1_RAM_ECC_LIMIT_ERR 29:29 /* RWDVF */
#define NV_NVLTLC_TX_LNK_ERR_FIRST_0_RSP1_RAM_ECC_LIMIT_ERR__ONWRITE "oneToClear" /* */
#define NV_NVLTLC_TX_LNK_ERR_FIRST_0_RSP1_RAM_ECC_LIMIT_ERR_NONE 0x00000000 /* RWD-V */
#define NV_NVLTLC_TX_LNK_ERR_FIRST_0_RSP1_RAM_ECC_LIMIT_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_NVLTLC_TX_LNK_ERR_STATUS_1 0x000012a0 /* RW-4R */
#define NV_NVLTLC_TX_LNK_ERR_STATUS_1_TIMEOUT_VC0 0:0 /* RWDVF */
#define NV_NVLTLC_TX_LNK_ERR_STATUS_1_TIMEOUT_VC0__ONWRITE "oneToClear" /* */
#define NV_NVLTLC_TX_LNK_ERR_STATUS_1_TIMEOUT_VC0_NONE 0x00000000 /* RWD-V */
#define NV_NVLTLC_TX_LNK_ERR_STATUS_1_TIMEOUT_VC0_CLEAR 0x00000001 /* RW--V */
#define NV_NVLTLC_TX_LNK_ERR_STATUS_1_TIMEOUT_VC1 1:1 /* RWDVF */
#define NV_NVLTLC_TX_LNK_ERR_STATUS_1_TIMEOUT_VC1__ONWRITE "oneToClear" /* */
#define NV_NVLTLC_TX_LNK_ERR_STATUS_1_TIMEOUT_VC1_NONE 0x00000000 /* RWD-V */
#define NV_NVLTLC_TX_LNK_ERR_STATUS_1_TIMEOUT_VC1_CLEAR 0x00000001 /* RW--V */
#define NV_NVLTLC_TX_LNK_ERR_STATUS_1_TIMEOUT_VC2 2:2 /* RWDVF */
#define NV_NVLTLC_TX_LNK_ERR_STATUS_1_TIMEOUT_VC2__ONWRITE "oneToClear" /* */
#define NV_NVLTLC_TX_LNK_ERR_STATUS_1_TIMEOUT_VC2_NONE 0x00000000 /* RWD-V */
#define NV_NVLTLC_TX_LNK_ERR_STATUS_1_TIMEOUT_VC2_CLEAR 0x00000001 /* RW--V */
#define NV_NVLTLC_TX_LNK_ERR_STATUS_1_TIMEOUT_VC3 3:3 /* RWDVF */
#define NV_NVLTLC_TX_LNK_ERR_STATUS_1_TIMEOUT_VC3__ONWRITE "oneToClear" /* */
#define NV_NVLTLC_TX_LNK_ERR_STATUS_1_TIMEOUT_VC3_NONE 0x00000000 /* RWD-V */
#define NV_NVLTLC_TX_LNK_ERR_STATUS_1_TIMEOUT_VC3_CLEAR 0x00000001 /* RW--V */
#define NV_NVLTLC_TX_LNK_ERR_STATUS_1_TIMEOUT_VC4 4:4 /* RWDVF */
#define NV_NVLTLC_TX_LNK_ERR_STATUS_1_TIMEOUT_VC4__ONWRITE "oneToClear" /* */
#define NV_NVLTLC_TX_LNK_ERR_STATUS_1_TIMEOUT_VC4_NONE 0x00000000 /* RWD-V */
#define NV_NVLTLC_TX_LNK_ERR_STATUS_1_TIMEOUT_VC4_CLEAR 0x00000001 /* RW--V */
#define NV_NVLTLC_TX_LNK_ERR_STATUS_1_TIMEOUT_VC5 5:5 /* RWDVF */
#define NV_NVLTLC_TX_LNK_ERR_STATUS_1_TIMEOUT_VC5__ONWRITE "oneToClear" /* */
#define NV_NVLTLC_TX_LNK_ERR_STATUS_1_TIMEOUT_VC5_NONE 0x00000000 /* RWD-V */
#define NV_NVLTLC_TX_LNK_ERR_STATUS_1_TIMEOUT_VC5_CLEAR 0x00000001 /* RW--V */
#define NV_NVLTLC_TX_LNK_ERR_STATUS_1_TIMEOUT_VC6 6:6 /* RWDVF */
#define NV_NVLTLC_TX_LNK_ERR_STATUS_1_TIMEOUT_VC6__ONWRITE "oneToClear" /* */
#define NV_NVLTLC_TX_LNK_ERR_STATUS_1_TIMEOUT_VC6_NONE 0x00000000 /* RWD-V */
#define NV_NVLTLC_TX_LNK_ERR_STATUS_1_TIMEOUT_VC6_CLEAR 0x00000001 /* RW--V */
#define NV_NVLTLC_TX_LNK_ERR_STATUS_1_TIMEOUT_VC7 7:7 /* RWDVF */
#define NV_NVLTLC_TX_LNK_ERR_STATUS_1_TIMEOUT_VC7__ONWRITE "oneToClear" /* */
#define NV_NVLTLC_TX_LNK_ERR_STATUS_1_TIMEOUT_VC7_NONE 0x00000000 /* RWD-V */
#define NV_NVLTLC_TX_LNK_ERR_STATUS_1_TIMEOUT_VC7_CLEAR 0x00000001 /* RW--V */
#define NV_NVLTLC_TX_LNK_ERR_NON_FATAL_REPORT_EN_1 0x000012ac /* RW-4R */
#define NV_NVLTLC_TX_LNK_ERR_NON_FATAL_REPORT_EN_1_TIMEOUT_VC0 0:0 /* RWEVF */
#define NV_NVLTLC_TX_LNK_ERR_NON_FATAL_REPORT_EN_1_TIMEOUT_VC0_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLTLC_TX_LNK_ERR_NON_FATAL_REPORT_EN_1_TIMEOUT_VC0_ENABLE 0x00000001 /* RW--V */
#define NV_NVLTLC_TX_LNK_ERR_NON_FATAL_REPORT_EN_1_TIMEOUT_VC1 1:1 /* RWEVF */
#define NV_NVLTLC_TX_LNK_ERR_NON_FATAL_REPORT_EN_1_TIMEOUT_VC1_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLTLC_TX_LNK_ERR_NON_FATAL_REPORT_EN_1_TIMEOUT_VC1_ENABLE 0x00000001 /* RW--V */
#define NV_NVLTLC_TX_LNK_ERR_NON_FATAL_REPORT_EN_1_TIMEOUT_VC2 2:2 /* RWEVF */
#define NV_NVLTLC_TX_LNK_ERR_NON_FATAL_REPORT_EN_1_TIMEOUT_VC2_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLTLC_TX_LNK_ERR_NON_FATAL_REPORT_EN_1_TIMEOUT_VC2_ENABLE 0x00000001 /* RW--V */
#define NV_NVLTLC_TX_LNK_ERR_NON_FATAL_REPORT_EN_1_TIMEOUT_VC3 3:3 /* RWEVF */
#define NV_NVLTLC_TX_LNK_ERR_NON_FATAL_REPORT_EN_1_TIMEOUT_VC3_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLTLC_TX_LNK_ERR_NON_FATAL_REPORT_EN_1_TIMEOUT_VC3_ENABLE 0x00000001 /* RW--V */
#define NV_NVLTLC_TX_LNK_ERR_NON_FATAL_REPORT_EN_1_TIMEOUT_VC4 4:4 /* RWEVF */
#define NV_NVLTLC_TX_LNK_ERR_NON_FATAL_REPORT_EN_1_TIMEOUT_VC4_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLTLC_TX_LNK_ERR_NON_FATAL_REPORT_EN_1_TIMEOUT_VC4_ENABLE 0x00000001 /* RW--V */
#define NV_NVLTLC_TX_LNK_ERR_NON_FATAL_REPORT_EN_1_TIMEOUT_VC5 5:5 /* RWEVF */
#define NV_NVLTLC_TX_LNK_ERR_NON_FATAL_REPORT_EN_1_TIMEOUT_VC5_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLTLC_TX_LNK_ERR_NON_FATAL_REPORT_EN_1_TIMEOUT_VC5_ENABLE 0x00000001 /* RW--V */
#define NV_NVLTLC_TX_LNK_ERR_NON_FATAL_REPORT_EN_1_TIMEOUT_VC6 6:6 /* RWEVF */
#define NV_NVLTLC_TX_LNK_ERR_NON_FATAL_REPORT_EN_1_TIMEOUT_VC6_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLTLC_TX_LNK_ERR_NON_FATAL_REPORT_EN_1_TIMEOUT_VC6_ENABLE 0x00000001 /* RW--V */
#define NV_NVLTLC_TX_LNK_ERR_NON_FATAL_REPORT_EN_1_TIMEOUT_VC7 7:7 /* RWEVF */
#define NV_NVLTLC_TX_LNK_ERR_NON_FATAL_REPORT_EN_1_TIMEOUT_VC7_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLTLC_TX_LNK_ERR_NON_FATAL_REPORT_EN_1_TIMEOUT_VC7_ENABLE 0x00000001 /* RW--V */
#define NV_NVLTLC_TX_LNK_ERR_FIRST_1 0x000012bc /* RW-4R */
#define NV_NVLTLC_TX_LNK_ERR_FIRST_1_TIMEOUT_VC0 0:0 /* RWDVF */
#define NV_NVLTLC_TX_LNK_ERR_FIRST_1_TIMEOUT_VC0__ONWRITE "oneToClear" /* */
#define NV_NVLTLC_TX_LNK_ERR_FIRST_1_TIMEOUT_VC0_NONE 0x00000000 /* RWD-V */
#define NV_NVLTLC_TX_LNK_ERR_FIRST_1_TIMEOUT_VC0_CLEAR 0x00000001 /* RW--V */
#define NV_NVLTLC_TX_LNK_ERR_FIRST_1_TIMEOUT_VC1 1:1 /* RWDVF */
#define NV_NVLTLC_TX_LNK_ERR_FIRST_1_TIMEOUT_VC1__ONWRITE "oneToClear" /* */
#define NV_NVLTLC_TX_LNK_ERR_FIRST_1_TIMEOUT_VC1_NONE 0x00000000 /* RWD-V */
#define NV_NVLTLC_TX_LNK_ERR_FIRST_1_TIMEOUT_VC1_CLEAR 0x00000001 /* RW--V */
#define NV_NVLTLC_TX_LNK_ERR_FIRST_1_TIMEOUT_VC2 2:2 /* RWDVF */
#define NV_NVLTLC_TX_LNK_ERR_FIRST_1_TIMEOUT_VC2__ONWRITE "oneToClear" /* */
#define NV_NVLTLC_TX_LNK_ERR_FIRST_1_TIMEOUT_VC2_NONE 0x00000000 /* RWD-V */
#define NV_NVLTLC_TX_LNK_ERR_FIRST_1_TIMEOUT_VC2_CLEAR 0x00000001 /* RW--V */
#define NV_NVLTLC_TX_LNK_ERR_FIRST_1_TIMEOUT_VC3 3:3 /* RWDVF */
#define NV_NVLTLC_TX_LNK_ERR_FIRST_1_TIMEOUT_VC3__ONWRITE "oneToClear" /* */
#define NV_NVLTLC_TX_LNK_ERR_FIRST_1_TIMEOUT_VC3_NONE 0x00000000 /* RWD-V */
#define NV_NVLTLC_TX_LNK_ERR_FIRST_1_TIMEOUT_VC3_CLEAR 0x00000001 /* RW--V */
#define NV_NVLTLC_TX_LNK_ERR_FIRST_1_TIMEOUT_VC4 4:4 /* RWDVF */
#define NV_NVLTLC_TX_LNK_ERR_FIRST_1_TIMEOUT_VC4__ONWRITE "oneToClear" /* */
#define NV_NVLTLC_TX_LNK_ERR_FIRST_1_TIMEOUT_VC4_NONE 0x00000000 /* RWD-V */
#define NV_NVLTLC_TX_LNK_ERR_FIRST_1_TIMEOUT_VC4_CLEAR 0x00000001 /* RW--V */
#define NV_NVLTLC_TX_LNK_ERR_FIRST_1_TIMEOUT_VC5 5:5 /* RWDVF */
#define NV_NVLTLC_TX_LNK_ERR_FIRST_1_TIMEOUT_VC5__ONWRITE "oneToClear" /* */
#define NV_NVLTLC_TX_LNK_ERR_FIRST_1_TIMEOUT_VC5_NONE 0x00000000 /* RWD-V */
#define NV_NVLTLC_TX_LNK_ERR_FIRST_1_TIMEOUT_VC5_CLEAR 0x00000001 /* RW--V */
#define NV_NVLTLC_TX_LNK_ERR_FIRST_1_TIMEOUT_VC6 6:6 /* RWDVF */
#define NV_NVLTLC_TX_LNK_ERR_FIRST_1_TIMEOUT_VC6__ONWRITE "oneToClear" /* */
#define NV_NVLTLC_TX_LNK_ERR_FIRST_1_TIMEOUT_VC6_NONE 0x00000000 /* RWD-V */
#define NV_NVLTLC_TX_LNK_ERR_FIRST_1_TIMEOUT_VC6_CLEAR 0x00000001 /* RW--V */
#define NV_NVLTLC_TX_LNK_ERR_FIRST_1_TIMEOUT_VC7 7:7 /* RWDVF */
#define NV_NVLTLC_TX_LNK_ERR_FIRST_1_TIMEOUT_VC7__ONWRITE "oneToClear" /* */
#define NV_NVLTLC_TX_LNK_ERR_FIRST_1_TIMEOUT_VC7_NONE 0x00000000 /* RWD-V */
#define NV_NVLTLC_TX_LNK_ERR_FIRST_1_TIMEOUT_VC7_CLEAR 0x00000001 /* RW--V */
#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_CTRL_0(i) (0x0000150c+(i)*0x54) /* RW-4A */
#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_CTRL_0__SIZE_1 4 /* */
#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_CTRL_0_UNIT 2:1 /* RWDVF */
#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_CTRL_0_UNIT_CYCLES 0x00000000 /* RW--V */
#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_CTRL_0_UNIT_PACKETS 0x00000001 /* RW--V */
#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_CTRL_0_UNIT_FLITS 0x00000002 /* RW--V */
#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_CTRL_0_UNIT_BYTES 0x00000003 /* RWD-V */
#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_CTRL_0_FLITFILTER 7:3 /* RWDVF */
#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_CTRL_0_FLITFILTER_INIT 0x00000000 /* RWD-V */
#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_CTRL_0_FLITFILTER_HEAD 0x00000001 /* RW--V */
#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_CTRL_0_FLITFILTER_AE 0x00000002 /* RW--V */
#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_CTRL_0_FLITFILTER_BE 0x00000004 /* RW--V */
#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_CTRL_0_FLITFILTER_DATA 0x00000008 /* RW--V */
#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_CTRL_0_FLITFILTER_IDLE 0x00000010 /* RW--V */
#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_CTRL_0_VCSETFILTERMODE 9:8 /* RWDVF */
#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_CTRL_0_VCSETFILTERMODE_INIT 0x00000003 /* RWD-V */
#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_CTRL_0_VCSETFILTERMODE_NONE 0x00000000 /* RW--V */
#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_CTRL_0_VCSETFILTERMODE_VCSET0 0x00000001 /* RW--V */
#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_CTRL_0_VCSETFILTERMODE_VCSET1 0x00000002 /* RW--V */
#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_CTRL_0_AN_FILTER 13:12 /* RWDVF */
#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_CTRL_0_AN_FILTER_AN1 0x00000001 /* RWD-V */
#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_CTRL_0_AN_FILTER_AN2 0x00000002 /* RW--V */
#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_CTRL_0_AN_FILTER_AN1_AND_AN2 0x00000003 /* RW--V */
#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_CTRL_0_PMSIZE 19:17 /* RWDVF */
#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_CTRL_0_PMSIZE_ONE 0x00000000 /* RWD-V */
#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_CTRL_0_PMSIZE_TWO 0x00000001 /* RW--V */
#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_CTRL_0_PMSIZE_FOUR 0x00000002 /* RW--V */
#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_CTRL_0_PMSIZE_EIGHT 0x00000003 /* RW--V */
#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_CTRL_0_PMSIZE_SIXTEEN 0x00000004 /* RW--V */
#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_CTRL_0_PMSIZE_THIRTYTWO 0x00000005 /* RW--V */
#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_CTRL_0_PMSIZE_SIXTYFOUR 0x00000006 /* RW--V */
#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_CTRL_0_PMSIZE_ONETWENTYEIGHT 0x00000007 /* RW--V */
#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_CTRL_0_ENABLE 24:24 /* RWDVF */
#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_CTRL_0_ENABLE_ENABLE 0x00000001 /* RW--V */
#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_CTRL_0_ENABLE_DISABLE 0x00000000 /* RWD-V */
#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_CTRL_0_RESET 25:25 /* RWDVF */
#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_CTRL_0_RESET__ONWRITE "oneToSet" /* */
#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_CTRL_0_RESET_INIT 0x00000000 /* RWD-V */
#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_CTRL_0_CAPTURE 26:26 /* RWDVF */
#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_CTRL_0_CAPTURE__ONWRITE "oneToSet" /* */
#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_CTRL_0_CAPTURE_INIT 0x00000000 /* RWD-V */
#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_CTRL_0_HW_TP_ENABLE 30:30 /* RWDVF */
#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_CTRL_0_HW_TP_ENABLE_ENABLE 0x00000001 /* RW--V */
#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_CTRL_0_HW_TP_ENABLE_DISABLE 0x00000000 /* RWD-V */
#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_CTRL_0_HW_TP_CAPTURE_ENABLE 31:31 /* RWDVF */
#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_CTRL_0_HW_TP_CAPTURE_ENABLE_ENABLE 0x00000001 /* RW--V */
#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_CTRL_0_HW_TP_CAPTURE_ENABLE_DISABLE 0x00000000 /* RWD-V */
#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_LO(i) (0x0000154c+(i)*0x54) /* RW-4A */
#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_LO__SIZE_1 4 /* */
#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_LO_COUNT 31:0 /* RWDVF */
#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_LO_COUNT_INIT 0x00000000 /* RWD-V */
#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_HI(i) (0x00001550+(i)*0x54) /* RW-4A */
#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_HI__SIZE_1 4 /* */
#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_HI_COUNT 30:0 /* RWDVF */
#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_HI_COUNT_INIT 0x00000000 /* RWD-V */
#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_HI_ROLLOVER 31:31 /* RWDVF */
#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_HI_ROLLOVER_INIT 0x00000000 /* RWD-V */
#define NV_NVLTLC_RX_LNK_ERR_STATUS_0 0x00001a80 /* RW-4R */
#define NV_NVLTLC_RX_LNK_ERR_STATUS_0_RXDLHDRPARITYERR 0:0 /* RWDVF */
#define NV_NVLTLC_RX_LNK_ERR_STATUS_0_RXDLHDRPARITYERR__ONWRITE "oneToClear" /* */
#define NV_NVLTLC_RX_LNK_ERR_STATUS_0_RXDLHDRPARITYERR_NONE 0x00000000 /* RWD-V */
#define NV_NVLTLC_RX_LNK_ERR_STATUS_0_RXDLHDRPARITYERR_CLEAR 0x00000001 /* RW--V */
#define NV_NVLTLC_RX_LNK_ERR_STATUS_0_RXDLDATAPARITYERR 1:1 /* RWDVF */
#define NV_NVLTLC_RX_LNK_ERR_STATUS_0_RXDLDATAPARITYERR__ONWRITE "oneToClear" /* */
#define NV_NVLTLC_RX_LNK_ERR_STATUS_0_RXDLDATAPARITYERR_NONE 0x00000000 /* RWD-V */
#define NV_NVLTLC_RX_LNK_ERR_STATUS_0_RXDLDATAPARITYERR_CLEAR 0x00000001 /* RW--V */
#define NV_NVLTLC_RX_LNK_ERR_STATUS_0_RXDLCTRLPARITYERR 2:2 /* RWDVF */
#define NV_NVLTLC_RX_LNK_ERR_STATUS_0_RXDLCTRLPARITYERR__ONWRITE "oneToClear" /* */
#define NV_NVLTLC_RX_LNK_ERR_STATUS_0_RXDLCTRLPARITYERR_NONE 0x00000000 /* RWD-V */
#define NV_NVLTLC_RX_LNK_ERR_STATUS_0_RXDLCTRLPARITYERR_CLEAR 0x00000001 /* RW--V */
#define NV_NVLTLC_RX_LNK_ERR_STATUS_0_RXPKTLENERR 6:6 /* RWDVF */
#define NV_NVLTLC_RX_LNK_ERR_STATUS_0_RXPKTLENERR__ONWRITE "oneToClear" /* */
#define NV_NVLTLC_RX_LNK_ERR_STATUS_0_RXPKTLENERR_NONE 0x00000000 /* RWD-V */
#define NV_NVLTLC_RX_LNK_ERR_STATUS_0_RXPKTLENERR_CLEAR 0x00000001 /* RW--V */
#define NV_NVLTLC_RX_LNK_ERR_STATUS_0_RSVCACHEATTRPROBEREQERR 10:10 /* RWDVF */
#define NV_NVLTLC_RX_LNK_ERR_STATUS_0_RSVCACHEATTRPROBEREQERR__ONWRITE "oneToClear" /* */
#define NV_NVLTLC_RX_LNK_ERR_STATUS_0_RSVCACHEATTRPROBEREQERR_NONE 0x00000000 /* RWD-V */
#define NV_NVLTLC_RX_LNK_ERR_STATUS_0_RSVCACHEATTRPROBEREQERR_CLEAR 0x00000001 /* RW--V */
#define NV_NVLTLC_RX_LNK_ERR_STATUS_0_RSVCACHEATTRPROBERSPERR 11:11 /* RWDVF */
#define NV_NVLTLC_RX_LNK_ERR_STATUS_0_RSVCACHEATTRPROBERSPERR__ONWRITE "oneToClear" /* */
#define NV_NVLTLC_RX_LNK_ERR_STATUS_0_RSVCACHEATTRPROBERSPERR_NONE 0x00000000 /* RWD-V */
#define NV_NVLTLC_RX_LNK_ERR_STATUS_0_RSVCACHEATTRPROBERSPERR_CLEAR 0x00000001 /* RW--V */
#define NV_NVLTLC_RX_LNK_ERR_STATUS_0_DATLENGTRMWREQMAXERR 12:12 /* RWDVF */
#define NV_NVLTLC_RX_LNK_ERR_STATUS_0_DATLENGTRMWREQMAXERR__ONWRITE "oneToClear" /* */
#define NV_NVLTLC_RX_LNK_ERR_STATUS_0_DATLENGTRMWREQMAXERR_NONE 0x00000000 /* RWD-V */
#define NV_NVLTLC_RX_LNK_ERR_STATUS_0_DATLENGTRMWREQMAXERR_CLEAR 0x00000001 /* RW--V */
#define NV_NVLTLC_RX_LNK_ERR_STATUS_0_DATLENLTATRRSPMINERR 13:13 /* RWDVF */
#define NV_NVLTLC_RX_LNK_ERR_STATUS_0_DATLENLTATRRSPMINERR__ONWRITE "oneToClear" /* */
#define NV_NVLTLC_RX_LNK_ERR_STATUS_0_DATLENLTATRRSPMINERR_NONE 0x00000000 /* RWD-V */
#define NV_NVLTLC_RX_LNK_ERR_STATUS_0_DATLENLTATRRSPMINERR_CLEAR 0x00000001 /* RW--V */
#define NV_NVLTLC_RX_LNK_ERR_STATUS_0_INVALIDCACHEATTRPOERR 14:14 /* RWDVF */
#define NV_NVLTLC_RX_LNK_ERR_STATUS_0_INVALIDCACHEATTRPOERR__ONWRITE "oneToClear" /* */
#define NV_NVLTLC_RX_LNK_ERR_STATUS_0_INVALIDCACHEATTRPOERR_NONE 0x00000000 /* RWD-V */
#define NV_NVLTLC_RX_LNK_ERR_STATUS_0_INVALIDCACHEATTRPOERR_CLEAR 0x00000001 /* RW--V */
#define NV_NVLTLC_RX_LNK_ERR_STATUS_0_RXRSPSTATUS_HW_ERR 16:16 /* RWDVF */
#define NV_NVLTLC_RX_LNK_ERR_STATUS_0_RXRSPSTATUS_HW_ERR__ONWRITE "oneToClear" /* */
#define NV_NVLTLC_RX_LNK_ERR_STATUS_0_RXRSPSTATUS_HW_ERR_NONE 0x00000000 /* RWD-V */
#define NV_NVLTLC_RX_LNK_ERR_STATUS_0_RXRSPSTATUS_HW_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_NVLTLC_RX_LNK_ERR_STATUS_0_RXRSPSTATUS_UR_ERR 17:17 /* RWDVF */
#define NV_NVLTLC_RX_LNK_ERR_STATUS_0_RXRSPSTATUS_UR_ERR__ONWRITE "oneToClear" /* */
#define NV_NVLTLC_RX_LNK_ERR_STATUS_0_RXRSPSTATUS_UR_ERR_NONE 0x00000000 /* RWD-V */
#define NV_NVLTLC_RX_LNK_ERR_STATUS_0_RXRSPSTATUS_UR_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_NVLTLC_RX_LNK_ERR_STATUS_0_RXRSPSTATUS_PRIV_ERR 18:18 /* RWDVF */
#define NV_NVLTLC_RX_LNK_ERR_STATUS_0_RXRSPSTATUS_PRIV_ERR__ONWRITE "oneToClear" /* */
#define NV_NVLTLC_RX_LNK_ERR_STATUS_0_RXRSPSTATUS_PRIV_ERR_NONE 0x00000000 /* RWD-V */
#define NV_NVLTLC_RX_LNK_ERR_STATUS_0_RXRSPSTATUS_PRIV_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_NVLTLC_RX_LNK_ERR_STATUS_0_INVALID_COLLAPSED_RESPONSE_ERR 19:19 /* RWDVF */
#define NV_NVLTLC_RX_LNK_ERR_STATUS_0_INVALID_COLLAPSED_RESPONSE_ERR__ONWRITE "oneToClear" /* */
#define NV_NVLTLC_RX_LNK_ERR_STATUS_0_INVALID_COLLAPSED_RESPONSE_ERR_NONE 0x00000000 /* RWD-V */
#define NV_NVLTLC_RX_LNK_ERR_STATUS_0_INVALID_COLLAPSED_RESPONSE_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_NVLTLC_RX_LNK_ERR_STATUS_0_RXRSPSTATUS_DATA_HW_ERR 20:20 /* RWDVF */
#define NV_NVLTLC_RX_LNK_ERR_STATUS_0_RXRSPSTATUS_DATA_HW_ERR__ONWRITE "oneToClear" /* */
#define NV_NVLTLC_RX_LNK_ERR_STATUS_0_RXRSPSTATUS_DATA_HW_ERR_NONE 0x00000000 /* RWD-V */
#define NV_NVLTLC_RX_LNK_ERR_STATUS_0_RXRSPSTATUS_DATA_HW_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_NVLTLC_RX_LNK_ERR_STATUS_0_RXRSPSTATUS_DATA_UR_ERR 21:21 /* RWDVF */
#define NV_NVLTLC_RX_LNK_ERR_STATUS_0_RXRSPSTATUS_DATA_UR_ERR__ONWRITE "oneToClear" /* */
#define NV_NVLTLC_RX_LNK_ERR_STATUS_0_RXRSPSTATUS_DATA_UR_ERR_NONE 0x00000000 /* RWD-V */
#define NV_NVLTLC_RX_LNK_ERR_STATUS_0_RXRSPSTATUS_DATA_UR_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_NVLTLC_RX_LNK_ERR_STATUS_0_RXRSPSTATUS_DATA_PRIV_ERR 22:22 /* RWDVF */
#define NV_NVLTLC_RX_LNK_ERR_STATUS_0_RXRSPSTATUS_DATA_PRIV_ERR__ONWRITE "oneToClear" /* */
#define NV_NVLTLC_RX_LNK_ERR_STATUS_0_RXRSPSTATUS_DATA_PRIV_ERR_NONE 0x00000000 /* RWD-V */
#define NV_NVLTLC_RX_LNK_ERR_STATUS_0_RXRSPSTATUS_DATA_PRIV_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_NVLTLC_RX_LNK_ERR_STATUS_0_DATLEN192PACKETERR 23:23 /* RWDVF */
#define NV_NVLTLC_RX_LNK_ERR_STATUS_0_DATLEN192PACKETERR__ONWRITE "oneToClear" /* */
#define NV_NVLTLC_RX_LNK_ERR_STATUS_0_DATLEN192PACKETERR_NONE 0x00000000 /* RWD-V */
#define NV_NVLTLC_RX_LNK_ERR_STATUS_0_DATLEN192PACKETERR_CLEAR 0x00000001 /* RW--V */
#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_0 0x00001a88 /* RW-4R */
#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_0_RXDLHDRPARITYERR 0:0 /* RWEVF */
#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_0_RXDLHDRPARITYERR_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_0_RXDLHDRPARITYERR_ENABLE 0x00000001 /* RW--V */
#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_0_RXDLDATAPARITYERR 1:1 /* RWEVF */
#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_0_RXDLDATAPARITYERR_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_0_RXDLDATAPARITYERR_ENABLE 0x00000001 /* RW--V */
#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_0_RXDLCTRLPARITYERR 2:2 /* RWEVF */
#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_0_RXDLCTRLPARITYERR_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_0_RXDLCTRLPARITYERR_ENABLE 0x00000001 /* RW--V */
#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_0_RXPKTLENERR 6:6 /* RWEVF */
#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_0_RXPKTLENERR_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_0_RXPKTLENERR_ENABLE 0x00000001 /* RW--V */
#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_0_RSVCACHEATTRPROBEREQERR 10:10 /* RWEVF */
#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_0_RSVCACHEATTRPROBEREQERR_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_0_RSVCACHEATTRPROBEREQERR_ENABLE 0x00000001 /* RW--V */
#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_0_RSVCACHEATTRPROBERSPERR 11:11 /* RWEVF */
#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_0_RSVCACHEATTRPROBERSPERR_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_0_RSVCACHEATTRPROBERSPERR_ENABLE 0x00000001 /* RW--V */
#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_0_DATLENGTRMWREQMAXERR 12:12 /* RWEVF */
#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_0_DATLENGTRMWREQMAXERR_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_0_DATLENGTRMWREQMAXERR_ENABLE 0x00000001 /* RW--V */
#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_0_DATLENLTATRRSPMINERR 13:13 /* RWEVF */
#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_0_DATLENLTATRRSPMINERR_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_0_DATLENLTATRRSPMINERR_ENABLE 0x00000001 /* RW--V */
#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_0_INVALIDCACHEATTRPOERR 14:14 /* RWEVF */
#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_0_INVALIDCACHEATTRPOERR_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_0_INVALIDCACHEATTRPOERR_ENABLE 0x00000001 /* RW--V */
#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_0_RXRSPSTATUS_HW_ERR 16:16 /* RWEVF */
#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_0_RXRSPSTATUS_HW_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_0_RXRSPSTATUS_HW_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_0_RXRSPSTATUS_UR_ERR 17:17 /* RWEVF */
#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_0_RXRSPSTATUS_UR_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_0_RXRSPSTATUS_UR_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_0_RXRSPSTATUS_PRIV_ERR 18:18 /* RWEVF */
#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_0_RXRSPSTATUS_PRIV_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_0_RXRSPSTATUS_PRIV_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_0_INVALID_COLLAPSED_RESPONSE_ERR 19:19 /* RWEVF */
#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_0_INVALID_COLLAPSED_RESPONSE_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_0_INVALID_COLLAPSED_RESPONSE_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_0_RXRSPSTATUS_DATA_HW_ERR 20:20 /* RWEVF */
#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_0_RXRSPSTATUS_DATA_HW_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_0_RXRSPSTATUS_DATA_HW_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_0_RXRSPSTATUS_DATA_UR_ERR 21:21 /* RWEVF */
#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_0_RXRSPSTATUS_DATA_UR_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_0_RXRSPSTATUS_DATA_UR_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_0_RXRSPSTATUS_DATA_PRIV_ERR 22:22 /* RWEVF */
#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_0_RXRSPSTATUS_DATA_PRIV_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_0_RXRSPSTATUS_DATA_PRIV_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_0_DATLEN192PACKETERR 23:23 /* RWEVF */
#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_0_DATLEN192PACKETERR_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_0_DATLEN192PACKETERR_ENABLE 0x00000001 /* RW--V */
#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_0 0x00001a8c /* RW-4R */
#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_0_RXDLHDRPARITYERR 0:0 /* RWEVF */
#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_0_RXDLHDRPARITYERR_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_0_RXDLHDRPARITYERR_ENABLE 0x00000001 /* RW--V */
#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_0_RXDLDATAPARITYERR 1:1 /* RWEVF */
#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_0_RXDLDATAPARITYERR_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_0_RXDLDATAPARITYERR_ENABLE 0x00000001 /* RW--V */
#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_0_RXDLCTRLPARITYERR 2:2 /* RWEVF */
#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_0_RXDLCTRLPARITYERR_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_0_RXDLCTRLPARITYERR_ENABLE 0x00000001 /* RW--V */
#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_0_RXPKTLENERR 6:6 /* RWEVF */
#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_0_RXPKTLENERR_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_0_RXPKTLENERR_ENABLE 0x00000001 /* RW--V */
#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_0_RSVCACHEATTRPROBEREQERR 10:10 /* RWEVF */
#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_0_RSVCACHEATTRPROBEREQERR_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_0_RSVCACHEATTRPROBEREQERR_ENABLE 0x00000001 /* RW--V */
#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_0_RSVCACHEATTRPROBERSPERR 11:11 /* RWEVF */
#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_0_RSVCACHEATTRPROBERSPERR_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_0_RSVCACHEATTRPROBERSPERR_ENABLE 0x00000001 /* RW--V */
#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_0_DATLENGTRMWREQMAXERR 12:12 /* RWEVF */
#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_0_DATLENGTRMWREQMAXERR_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_0_DATLENGTRMWREQMAXERR_ENABLE 0x00000001 /* RW--V */
#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_0_DATLENLTATRRSPMINERR 13:13 /* RWEVF */
#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_0_DATLENLTATRRSPMINERR_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_0_DATLENLTATRRSPMINERR_ENABLE 0x00000001 /* RW--V */
#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_0_INVALIDCACHEATTRPOERR 14:14 /* RWEVF */
#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_0_INVALIDCACHEATTRPOERR_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_0_INVALIDCACHEATTRPOERR_ENABLE 0x00000001 /* RW--V */
#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_0_RXRSPSTATUS_HW_ERR 16:16 /* RWEVF */
#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_0_RXRSPSTATUS_HW_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_0_RXRSPSTATUS_HW_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_0_RXRSPSTATUS_UR_ERR 17:17 /* RWEVF */
#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_0_RXRSPSTATUS_UR_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_0_RXRSPSTATUS_UR_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_0_RXRSPSTATUS_PRIV_ERR 18:18 /* RWEVF */
#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_0_RXRSPSTATUS_PRIV_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_0_RXRSPSTATUS_PRIV_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_0_INVALID_COLLAPSED_RESPONSE_ERR 19:19 /* RWEVF */
#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_0_INVALID_COLLAPSED_RESPONSE_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_0_INVALID_COLLAPSED_RESPONSE_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_0_RXRSPSTATUS_DATA_HW_ERR 20:20 /* RWEVF */
#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_0_RXRSPSTATUS_DATA_HW_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_0_RXRSPSTATUS_DATA_HW_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_0_RXRSPSTATUS_DATA_UR_ERR 21:21 /* RWEVF */
#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_0_RXRSPSTATUS_DATA_UR_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_0_RXRSPSTATUS_DATA_UR_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_0_RXRSPSTATUS_DATA_PRIV_ERR 22:22 /* RWEVF */
#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_0_RXRSPSTATUS_DATA_PRIV_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_0_RXRSPSTATUS_DATA_PRIV_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_0_DATLEN192PACKETERR 23:23 /* RWEVF */
#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_0_DATLEN192PACKETERR_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_0_DATLEN192PACKETERR_ENABLE 0x00000001 /* RW--V */
#define NV_NVLTLC_RX_LNK_ERR_FIRST_0 0x00001a9c /* RW-4R */
#define NV_NVLTLC_RX_LNK_ERR_FIRST_0_RXDLHDRPARITYERR 0:0 /* RWDVF */
#define NV_NVLTLC_RX_LNK_ERR_FIRST_0_RXDLHDRPARITYERR__ONWRITE "oneToClear" /* */
#define NV_NVLTLC_RX_LNK_ERR_FIRST_0_RXDLHDRPARITYERR_NONE 0x00000000 /* RWD-V */
#define NV_NVLTLC_RX_LNK_ERR_FIRST_0_RXDLHDRPARITYERR_CLEAR 0x00000001 /* RW--V */
#define NV_NVLTLC_RX_LNK_ERR_FIRST_0_RXDLDATAPARITYERR 1:1 /* RWDVF */
#define NV_NVLTLC_RX_LNK_ERR_FIRST_0_RXDLDATAPARITYERR__ONWRITE "oneToClear" /* */
#define NV_NVLTLC_RX_LNK_ERR_FIRST_0_RXDLDATAPARITYERR_NONE 0x00000000 /* RWD-V */
#define NV_NVLTLC_RX_LNK_ERR_FIRST_0_RXDLDATAPARITYERR_CLEAR 0x00000001 /* RW--V */
#define NV_NVLTLC_RX_LNK_ERR_FIRST_0_RXDLCTRLPARITYERR 2:2 /* RWDVF */
#define NV_NVLTLC_RX_LNK_ERR_FIRST_0_RXDLCTRLPARITYERR__ONWRITE "oneToClear" /* */
#define NV_NVLTLC_RX_LNK_ERR_FIRST_0_RXDLCTRLPARITYERR_NONE 0x00000000 /* RWD-V */
#define NV_NVLTLC_RX_LNK_ERR_FIRST_0_RXDLCTRLPARITYERR_CLEAR 0x00000001 /* RW--V */
#define NV_NVLTLC_RX_LNK_ERR_FIRST_0_RXPKTLENERR 6:6 /* RWDVF */
#define NV_NVLTLC_RX_LNK_ERR_FIRST_0_RXPKTLENERR__ONWRITE "oneToClear" /* */
#define NV_NVLTLC_RX_LNK_ERR_FIRST_0_RXPKTLENERR_NONE 0x00000000 /* RWD-V */
#define NV_NVLTLC_RX_LNK_ERR_FIRST_0_RXPKTLENERR_CLEAR 0x00000001 /* RW--V */
#define NV_NVLTLC_RX_LNK_ERR_FIRST_0_RSVCACHEATTRPROBEREQERR 10:10 /* RWDVF */
#define NV_NVLTLC_RX_LNK_ERR_FIRST_0_RSVCACHEATTRPROBEREQERR__ONWRITE "oneToClear" /* */
#define NV_NVLTLC_RX_LNK_ERR_FIRST_0_RSVCACHEATTRPROBEREQERR_NONE 0x00000000 /* RWD-V */
#define NV_NVLTLC_RX_LNK_ERR_FIRST_0_RSVCACHEATTRPROBEREQERR_CLEAR 0x00000001 /* RW--V */
#define NV_NVLTLC_RX_LNK_ERR_FIRST_0_RSVCACHEATTRPROBERSPERR 11:11 /* RWDVF */
#define NV_NVLTLC_RX_LNK_ERR_FIRST_0_RSVCACHEATTRPROBERSPERR__ONWRITE "oneToClear" /* */
#define NV_NVLTLC_RX_LNK_ERR_FIRST_0_RSVCACHEATTRPROBERSPERR_NONE 0x00000000 /* RWD-V */
#define NV_NVLTLC_RX_LNK_ERR_FIRST_0_RSVCACHEATTRPROBERSPERR_CLEAR 0x00000001 /* RW--V */
#define NV_NVLTLC_RX_LNK_ERR_FIRST_0_DATLENGTRMWREQMAXERR 12:12 /* RWDVF */
#define NV_NVLTLC_RX_LNK_ERR_FIRST_0_DATLENGTRMWREQMAXERR__ONWRITE "oneToClear" /* */
#define NV_NVLTLC_RX_LNK_ERR_FIRST_0_DATLENGTRMWREQMAXERR_NONE 0x00000000 /* RWD-V */
#define NV_NVLTLC_RX_LNK_ERR_FIRST_0_DATLENGTRMWREQMAXERR_CLEAR 0x00000001 /* RW--V */
#define NV_NVLTLC_RX_LNK_ERR_FIRST_0_DATLENLTATRRSPMINERR 13:13 /* RWDVF */
#define NV_NVLTLC_RX_LNK_ERR_FIRST_0_DATLENLTATRRSPMINERR__ONWRITE "oneToClear" /* */
#define NV_NVLTLC_RX_LNK_ERR_FIRST_0_DATLENLTATRRSPMINERR_NONE 0x00000000 /* RWD-V */
#define NV_NVLTLC_RX_LNK_ERR_FIRST_0_DATLENLTATRRSPMINERR_CLEAR 0x00000001 /* RW--V */
#define NV_NVLTLC_RX_LNK_ERR_FIRST_0_INVALIDCACHEATTRPOERR 14:14 /* RWDVF */
#define NV_NVLTLC_RX_LNK_ERR_FIRST_0_INVALIDCACHEATTRPOERR__ONWRITE "oneToClear" /* */
#define NV_NVLTLC_RX_LNK_ERR_FIRST_0_INVALIDCACHEATTRPOERR_NONE 0x00000000 /* RWD-V */
#define NV_NVLTLC_RX_LNK_ERR_FIRST_0_INVALIDCACHEATTRPOERR_CLEAR 0x00000001 /* RW--V */
#define NV_NVLTLC_RX_LNK_ERR_FIRST_0_RXRSPSTATUS_HW_ERR 16:16 /* RWDVF */
#define NV_NVLTLC_RX_LNK_ERR_FIRST_0_RXRSPSTATUS_HW_ERR__ONWRITE "oneToClear" /* */
#define NV_NVLTLC_RX_LNK_ERR_FIRST_0_RXRSPSTATUS_HW_ERR_NONE 0x00000000 /* RWD-V */
#define NV_NVLTLC_RX_LNK_ERR_FIRST_0_RXRSPSTATUS_HW_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_NVLTLC_RX_LNK_ERR_FIRST_0_RXRSPSTATUS_UR_ERR 17:17 /* RWDVF */
#define NV_NVLTLC_RX_LNK_ERR_FIRST_0_RXRSPSTATUS_UR_ERR__ONWRITE "oneToClear" /* */
#define NV_NVLTLC_RX_LNK_ERR_FIRST_0_RXRSPSTATUS_UR_ERR_NONE 0x00000000 /* RWD-V */
#define NV_NVLTLC_RX_LNK_ERR_FIRST_0_RXRSPSTATUS_UR_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_NVLTLC_RX_LNK_ERR_FIRST_0_RXRSPSTATUS_PRIV_ERR 18:18 /* RWDVF */
#define NV_NVLTLC_RX_LNK_ERR_FIRST_0_RXRSPSTATUS_PRIV_ERR__ONWRITE "oneToClear" /* */
#define NV_NVLTLC_RX_LNK_ERR_FIRST_0_RXRSPSTATUS_PRIV_ERR_NONE 0x00000000 /* RWD-V */
#define NV_NVLTLC_RX_LNK_ERR_FIRST_0_RXRSPSTATUS_PRIV_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_NVLTLC_RX_LNK_ERR_FIRST_0_INVALID_COLLAPSED_RESPONSE_ERR 19:19 /* RWDVF */
#define NV_NVLTLC_RX_LNK_ERR_FIRST_0_INVALID_COLLAPSED_RESPONSE_ERR__ONWRITE "oneToClear" /* */
#define NV_NVLTLC_RX_LNK_ERR_FIRST_0_INVALID_COLLAPSED_RESPONSE_ERR_NONE 0x00000000 /* RWD-V */
#define NV_NVLTLC_RX_LNK_ERR_FIRST_0_INVALID_COLLAPSED_RESPONSE_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_NVLTLC_RX_LNK_ERR_FIRST_0_RXRSPSTATUS_DATA_HW_ERR 20:20 /* RWDVF */
#define NV_NVLTLC_RX_LNK_ERR_FIRST_0_RXRSPSTATUS_DATA_HW_ERR__ONWRITE "oneToClear" /* */
#define NV_NVLTLC_RX_LNK_ERR_FIRST_0_RXRSPSTATUS_DATA_HW_ERR_NONE 0x00000000 /* RWD-V */
#define NV_NVLTLC_RX_LNK_ERR_FIRST_0_RXRSPSTATUS_DATA_HW_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_NVLTLC_RX_LNK_ERR_FIRST_0_RXRSPSTATUS_DATA_UR_ERR 21:21 /* RWDVF */
#define NV_NVLTLC_RX_LNK_ERR_FIRST_0_RXRSPSTATUS_DATA_UR_ERR__ONWRITE "oneToClear" /* */
#define NV_NVLTLC_RX_LNK_ERR_FIRST_0_RXRSPSTATUS_DATA_UR_ERR_NONE 0x00000000 /* RWD-V */
#define NV_NVLTLC_RX_LNK_ERR_FIRST_0_RXRSPSTATUS_DATA_UR_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_NVLTLC_RX_LNK_ERR_FIRST_0_RXRSPSTATUS_DATA_PRIV_ERR 22:22 /* RWDVF */
#define NV_NVLTLC_RX_LNK_ERR_FIRST_0_RXRSPSTATUS_DATA_PRIV_ERR__ONWRITE "oneToClear" /* */
#define NV_NVLTLC_RX_LNK_ERR_FIRST_0_RXRSPSTATUS_DATA_PRIV_ERR_NONE 0x00000000 /* RWD-V */
#define NV_NVLTLC_RX_LNK_ERR_FIRST_0_RXRSPSTATUS_DATA_PRIV_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_NVLTLC_RX_LNK_ERR_FIRST_0_DATLEN192PACKETERR 23:23 /* RWDVF */
#define NV_NVLTLC_RX_LNK_ERR_FIRST_0_DATLEN192PACKETERR__ONWRITE "oneToClear" /* */
#define NV_NVLTLC_RX_LNK_ERR_FIRST_0_DATLEN192PACKETERR_NONE 0x00000000 /* RWD-V */
#define NV_NVLTLC_RX_LNK_ERR_FIRST_0_DATLEN192PACKETERR_CLEAR 0x00000001 /* RW--V */
#define NV_NVLTLC_RX_LNK_ERR_STATUS_1 0x00001aa0 /* RW-4R */
#define NV_NVLTLC_RX_LNK_ERR_STATUS_1_RXHDROVFERR 7:0 /* RWDVF */
#define NV_NVLTLC_RX_LNK_ERR_STATUS_1_RXHDROVFERR__ONWRITE "oneToClear" /* */
#define NV_NVLTLC_RX_LNK_ERR_STATUS_1_RXHDROVFERR_NONE 0x00000000 /* RWD-V */
#define NV_NVLTLC_RX_LNK_ERR_STATUS_1_RXHDROVFERR_CLEAR 0x00000001 /* RW--V */
#define NV_NVLTLC_RX_LNK_ERR_STATUS_1_RXDATAOVFERR 15:8 /* RWDVF */
#define NV_NVLTLC_RX_LNK_ERR_STATUS_1_RXDATAOVFERR__ONWRITE "oneToClear" /* */
#define NV_NVLTLC_RX_LNK_ERR_STATUS_1_RXDATAOVFERR_NONE 0x00000000 /* RWD-V */
#define NV_NVLTLC_RX_LNK_ERR_STATUS_1_RXDATAOVFERR_CLEAR 0x00000001 /* RW--V */
#define NV_NVLTLC_RX_LNK_ERR_STATUS_1_STOMPDETERR 16:16 /* RWDVF */
#define NV_NVLTLC_RX_LNK_ERR_STATUS_1_STOMPDETERR__ONWRITE "oneToClear" /* */
#define NV_NVLTLC_RX_LNK_ERR_STATUS_1_STOMPDETERR_NONE 0x00000000 /* RWD-V */
#define NV_NVLTLC_RX_LNK_ERR_STATUS_1_STOMPDETERR_CLEAR 0x00000001 /* RW--V */
#define NV_NVLTLC_RX_LNK_ERR_STATUS_1_RXPOISONERR 17:17 /* RWDVF */
#define NV_NVLTLC_RX_LNK_ERR_STATUS_1_RXPOISONERR__ONWRITE "oneToClear" /* */
#define NV_NVLTLC_RX_LNK_ERR_STATUS_1_RXPOISONERR_NONE 0x00000000 /* RWD-V */
#define NV_NVLTLC_RX_LNK_ERR_STATUS_1_RXPOISONERR_CLEAR 0x00000001 /* RW--V */
#define NV_NVLTLC_RX_LNK_ERR_STATUS_1_HEARTBEAT_TIMEOUT_ERR 18:18 /* RWDVF */
#define NV_NVLTLC_RX_LNK_ERR_STATUS_1_HEARTBEAT_TIMEOUT_ERR__ONWRITE "oneToClear" /* */
#define NV_NVLTLC_RX_LNK_ERR_STATUS_1_HEARTBEAT_TIMEOUT_ERR_NONE 0x00000000 /* RWD-V */
#define NV_NVLTLC_RX_LNK_ERR_STATUS_1_HEARTBEAT_TIMEOUT_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_1 0x00001aa8 /* RW-4R */
#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_1_RXHDROVFERR 7:0 /* RWEVF */
#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_1_RXHDROVFERR_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_1_RXHDROVFERR_ENABLE 0x00000001 /* RW--V */
#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_1_RXDATAOVFERR 15:8 /* RWEVF */
#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_1_RXDATAOVFERR_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_1_RXDATAOVFERR_ENABLE 0x00000001 /* RW--V */
#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_1_STOMPDETERR 16:16 /* RWEVF */
#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_1_STOMPDETERR_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_1_STOMPDETERR_ENABLE 0x00000001 /* RW--V */
#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_1_RXPOISONERR 17:17 /* RWEVF */
#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_1_RXPOISONERR_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_1_RXPOISONERR_ENABLE 0x00000001 /* RW--V */
#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_1_HEARTBEAT_TIMEOUT_ERR 18:18 /* RWEVF */
#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_1_HEARTBEAT_TIMEOUT_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_1_HEARTBEAT_TIMEOUT_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_1 0x00001aac /* RW-4R */
#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_1_RXHDROVFERR 7:0 /* RWEVF */
#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_1_RXHDROVFERR_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_1_RXHDROVFERR_ENABLE 0x00000001 /* RW--V */
#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_1_RXDATAOVFERR 15:8 /* RWEVF */
#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_1_RXDATAOVFERR_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_1_RXDATAOVFERR_ENABLE 0x00000001 /* RW--V */
#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_1_STOMPDETERR 16:16 /* RWEVF */
#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_1_STOMPDETERR_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_1_STOMPDETERR_ENABLE 0x00000001 /* RW--V */
#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_1_RXPOISONERR 17:17 /* RWEVF */
#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_1_RXPOISONERR_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_1_RXPOISONERR_ENABLE 0x00000001 /* RW--V */
#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_1_HEARTBEAT_TIMEOUT_ERR 18:18 /* RWEVF */
#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_1_HEARTBEAT_TIMEOUT_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_1_HEARTBEAT_TIMEOUT_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_NVLTLC_RX_LNK_ERR_REPORT_INJECT_1 0x00001ab8 /* RW-4R */
#define NV_NVLTLC_RX_LNK_ERR_REPORT_INJECT_1_RXHDROVFERR 7:0 /* RWDVF */
#define NV_NVLTLC_RX_LNK_ERR_REPORT_INJECT_1_RXHDROVFERR__ONWRITE "oneToSet" /* */
#define NV_NVLTLC_RX_LNK_ERR_REPORT_INJECT_1_RXHDROVFERR_INIT 0x00000000 /* RWD-V */
#define NV_NVLTLC_RX_LNK_ERR_REPORT_INJECT_1_RXHDROVFERR_INSERT 0x00000001 /* RW--V */
#define NV_NVLTLC_RX_LNK_ERR_REPORT_INJECT_1_RXDATAOVFERR 15:8 /* RWDVF */
#define NV_NVLTLC_RX_LNK_ERR_REPORT_INJECT_1_RXDATAOVFERR__ONWRITE "oneToSet" /* */
#define NV_NVLTLC_RX_LNK_ERR_REPORT_INJECT_1_RXDATAOVFERR_INIT 0x00000000 /* RWD-V */
#define NV_NVLTLC_RX_LNK_ERR_REPORT_INJECT_1_RXDATAOVFERR_INSERT 0x00000001 /* RW--V */
#define NV_NVLTLC_RX_LNK_ERR_REPORT_INJECT_1_STOMPDETERR 16:16 /* RWDVF */
#define NV_NVLTLC_RX_LNK_ERR_REPORT_INJECT_1_STOMPDETERR__ONWRITE "oneToSet" /* */
#define NV_NVLTLC_RX_LNK_ERR_REPORT_INJECT_1_STOMPDETERR_INIT 0x00000000 /* RWD-V */
#define NV_NVLTLC_RX_LNK_ERR_REPORT_INJECT_1_STOMPDETERR_INSERT 0x00000001 /* RW--V */
#define NV_NVLTLC_RX_LNK_ERR_REPORT_INJECT_1_RXPOISONERR 17:17 /* RWDVF */
#define NV_NVLTLC_RX_LNK_ERR_REPORT_INJECT_1_RXPOISONERR__ONWRITE "oneToSet" /* */
#define NV_NVLTLC_RX_LNK_ERR_REPORT_INJECT_1_RXPOISONERR_INIT 0x00000000 /* RWD-V */
#define NV_NVLTLC_RX_LNK_ERR_REPORT_INJECT_1_RXPOISONERR_INSERT 0x00000001 /* RW--V */
#define NV_NVLTLC_RX_LNK_ERR_REPORT_INJECT_1_HEARTBEAT_TIMEOUT_ERR 18:18 /* RWDVF */
#define NV_NVLTLC_RX_LNK_ERR_REPORT_INJECT_1_HEARTBEAT_TIMEOUT_ERR__ONWRITE "oneToSet" /* */
#define NV_NVLTLC_RX_LNK_ERR_REPORT_INJECT_1_HEARTBEAT_TIMEOUT_ERR_INIT 0x00000000 /* RWD-V */
#define NV_NVLTLC_RX_LNK_ERR_REPORT_INJECT_1_HEARTBEAT_TIMEOUT_ERR_INSERT 0x00000001 /* RW--V */
#define NV_NVLTLC_RX_LNK_ERR_FIRST_1 0x00001abc /* RW-4R */
#define NV_NVLTLC_RX_LNK_ERR_FIRST_1_RXHDROVFERR 7:0 /* RWDVF */
#define NV_NVLTLC_RX_LNK_ERR_FIRST_1_RXHDROVFERR__ONWRITE "oneToClear" /* */
#define NV_NVLTLC_RX_LNK_ERR_FIRST_1_RXHDROVFERR_NONE 0x00000000 /* RWD-V */
#define NV_NVLTLC_RX_LNK_ERR_FIRST_1_RXHDROVFERR_CLEAR 0x00000001 /* RW--V */
#define NV_NVLTLC_RX_LNK_ERR_FIRST_1_RXDATAOVFERR 15:8 /* RWDVF */
#define NV_NVLTLC_RX_LNK_ERR_FIRST_1_RXDATAOVFERR__ONWRITE "oneToClear" /* */
#define NV_NVLTLC_RX_LNK_ERR_FIRST_1_RXDATAOVFERR_NONE 0x00000000 /* RWD-V */
#define NV_NVLTLC_RX_LNK_ERR_FIRST_1_RXDATAOVFERR_CLEAR 0x00000001 /* RW--V */
#define NV_NVLTLC_RX_LNK_ERR_FIRST_1_STOMPDETERR 16:16 /* RWDVF */
#define NV_NVLTLC_RX_LNK_ERR_FIRST_1_STOMPDETERR__ONWRITE "oneToClear" /* */
#define NV_NVLTLC_RX_LNK_ERR_FIRST_1_STOMPDETERR_NONE 0x00000000 /* RWD-V */
#define NV_NVLTLC_RX_LNK_ERR_FIRST_1_STOMPDETERR_CLEAR 0x00000001 /* RW--V */
#define NV_NVLTLC_RX_LNK_ERR_FIRST_1_RXPOISONERR 17:17 /* RWDVF */
#define NV_NVLTLC_RX_LNK_ERR_FIRST_1_RXPOISONERR__ONWRITE "oneToClear" /* */
#define NV_NVLTLC_RX_LNK_ERR_FIRST_1_RXPOISONERR_NONE 0x00000000 /* RWD-V */
#define NV_NVLTLC_RX_LNK_ERR_FIRST_1_RXPOISONERR_CLEAR 0x00000001 /* RW--V */
#define NV_NVLTLC_RX_LNK_ERR_FIRST_1_HEARTBEAT_TIMEOUT_ERR 18:18 /* RWDVF */
#define NV_NVLTLC_RX_LNK_ERR_FIRST_1_HEARTBEAT_TIMEOUT_ERR__ONWRITE "oneToClear" /* */
#define NV_NVLTLC_RX_LNK_ERR_FIRST_1_HEARTBEAT_TIMEOUT_ERR_NONE 0x00000000 /* RWD-V */
#define NV_NVLTLC_RX_LNK_ERR_FIRST_1_HEARTBEAT_TIMEOUT_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_CTRL_0(i) (0x00001d0c+(i)*0x54) /* RW-4A */
#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_CTRL_0__SIZE_1 4 /* */
#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_CTRL_0_UNIT 2:1 /* RWDVF */
#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_CTRL_0_UNIT_CYCLES 0x00000000 /* RW--V */
#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_CTRL_0_UNIT_PACKETS 0x00000001 /* RW--V */
#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_CTRL_0_UNIT_FLITS 0x00000002 /* RW--V */
#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_CTRL_0_UNIT_BYTES 0x00000003 /* RWD-V */
#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_CTRL_0_FLITFILTER 7:3 /* RWDVF */
#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_CTRL_0_FLITFILTER_INIT 0x00000000 /* RWD-V */
#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_CTRL_0_FLITFILTER_HEAD 0x00000001 /* RW--V */
#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_CTRL_0_FLITFILTER_AE 0x00000002 /* RW--V */
#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_CTRL_0_FLITFILTER_BE 0x00000004 /* RW--V */
#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_CTRL_0_FLITFILTER_DATA 0x00000008 /* RW--V */
#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_CTRL_0_FLITFILTER_IDLE 0x00000010 /* RW--V */
#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_CTRL_0_VCSETFILTERMODE 9:8 /* RWDVF */
#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_CTRL_0_VCSETFILTERMODE_INIT 0x00000003 /* RWD-V */
#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_CTRL_0_VCSETFILTERMODE_NONE 0x00000000 /* RW--V */
#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_CTRL_0_VCSETFILTERMODE_VCSET0 0x00000001 /* RW--V */
#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_CTRL_0_VCSETFILTERMODE_VCSET1 0x00000002 /* RW--V */
#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_CTRL_0_AN_FILTER 13:12 /* RWDVF */
#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_CTRL_0_AN_FILTER_AN1 0x00000001 /* RWD-V */
#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_CTRL_0_AN_FILTER_AN2 0x00000002 /* RW--V */
#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_CTRL_0_AN_FILTER_AN1_AND_AN2 0x00000003 /* RW--V */
#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_CTRL_0_PMSIZE 19:17 /* RWDVF */
#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_CTRL_0_PMSIZE_ONE 0x00000000 /* RWD-V */
#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_CTRL_0_PMSIZE_TWO 0x00000001 /* RW--V */
#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_CTRL_0_PMSIZE_FOUR 0x00000002 /* RW--V */
#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_CTRL_0_PMSIZE_EIGHT 0x00000003 /* RW--V */
#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_CTRL_0_PMSIZE_SIXTEEN 0x00000004 /* RW--V */
#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_CTRL_0_PMSIZE_THIRTYTWO 0x00000005 /* RW--V */
#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_CTRL_0_PMSIZE_SIXTYFOUR 0x00000006 /* RW--V */
#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_CTRL_0_PMSIZE_ONETWENTYEIGHT 0x00000007 /* RW--V */
#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_CTRL_0_ENABLE 24:24 /* RWDVF */
#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_CTRL_0_ENABLE_ENABLE 0x00000001 /* RW--V */
#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_CTRL_0_ENABLE_DISABLE 0x00000000 /* RWD-V */
#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_CTRL_0_RESET 25:25 /* RWDVF */
#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_CTRL_0_RESET__ONWRITE "oneToSet" /* */
#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_CTRL_0_RESET_INIT 0x00000000 /* RWD-V */
#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_CTRL_0_CAPTURE 26:26 /* RWDVF */
#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_CTRL_0_CAPTURE__ONWRITE "oneToSet" /* */
#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_CTRL_0_CAPTURE_INIT 0x00000000 /* RWD-V */
#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_CTRL_0_HW_TP_ENABLE 30:30 /* RWDVF */
#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_CTRL_0_HW_TP_ENABLE_ENABLE 0x00000001 /* RW--V */
#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_CTRL_0_HW_TP_ENABLE_DISABLE 0x00000000 /* RWD-V */
#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_CTRL_0_HW_TP_CAPTURE_ENABLE 31:31 /* RWDVF */
#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_CTRL_0_HW_TP_CAPTURE_ENABLE_ENABLE 0x00000001 /* RW--V */
#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_CTRL_0_HW_TP_CAPTURE_ENABLE_DISABLE 0x00000000 /* RWD-V */
#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_LO(i) (0x00001d4c+(i)*0x54) /* RW-4A */
#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_LO__SIZE_1 4 /* */
#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_LO_COUNT 31:0 /* RWDVF */
#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_LO_COUNT_INIT 0x00000000 /* RWD-V */
#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_HI(i) (0x00001d50+(i)*0x54) /* RW-4A */
#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_HI__SIZE_1 4 /* */
#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_HI_COUNT 30:0 /* RWDVF */
#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_HI_COUNT_INIT 0x00000000 /* RWD-V */
#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_HI_ROLLOVER 31:31 /* RWDVF */
#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_HI_ROLLOVER_INIT 0x00000000 /* RWD-V */
#endif // __ls10_dev_nvltlc_ip_h__

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src/common/inc/swref/published/nvswitch/ls10/dev_nvlw_ip.h Normal file
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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the Software),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __ls10_dev_nvlw_ip_h__
#define __ls10_dev_nvlw_ip_h__
/* This file is autogenerated. Do not edit */
#define NV_NVLW 0x0000FFF:0x00000000 /* RW--D */
#define NV_NVLW_TOP_INTR_0_STATUS 0x00000200 /* R--4R */
#define NV_NVLW_TOP_INTR_0_STATUS_LINK 3:0 /* R-EVF */
#define NV_NVLW_TOP_INTR_0_STATUS_LINK_INIT 0x00000000 /* R-E-V */
#define NV_NVLW_TOP_INTR_0_STATUS_COMMON 31:31 /* R-EVF */
#define NV_NVLW_TOP_INTR_0_STATUS_COMMON_INIT 0x00000000 /* R-E-V */
#define NV_NVLW_TOP_INTR_1_STATUS 0x00000204 /* R--4R */
#define NV_NVLW_TOP_INTR_1_STATUS_LINK 3:0 /* R-EVF */
#define NV_NVLW_TOP_INTR_1_STATUS_LINK_INIT 0x00000000 /* R-E-V */
#define NV_NVLW_TOP_INTR_1_STATUS_COMMON 31:31 /* R-EVF */
#define NV_NVLW_TOP_INTR_1_STATUS_COMMON_INIT 0x00000000 /* R-E-V */
#define NV_NVLW_TOP_INTR_2_STATUS 0x00000208 /* R--4R */
#define NV_NVLW_TOP_INTR_2_STATUS_LINK 3:0 /* R-EVF */
#define NV_NVLW_TOP_INTR_2_STATUS_LINK_INIT 0x00000000 /* R-E-V */
#define NV_NVLW_TOP_INTR_2_STATUS_COMMON 31:31 /* R-EVF */
#define NV_NVLW_TOP_INTR_2_STATUS_COMMON_INIT 0x00000000 /* R-E-V */
#define NV_NVLW_COMMON_INTR_0_MASK 0x00000220 /* RW-4R */
#define NV_NVLW_COMMON_INTR_0_MASK_FATAL 0:0 /* RWEVF */
#define NV_NVLW_COMMON_INTR_0_MASK_FATAL_ENABLE 0x00000001 /* RW--V */
#define NV_NVLW_COMMON_INTR_0_MASK_FATAL_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLW_COMMON_INTR_0_MASK_NONFATAL 1:1 /* RWEVF */
#define NV_NVLW_COMMON_INTR_0_MASK_NONFATAL_ENABLE 0x00000001 /* RW--V */
#define NV_NVLW_COMMON_INTR_0_MASK_NONFATAL_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLW_COMMON_INTR_0_MASK_CORRECTABLE 2:2 /* RWEVF */
#define NV_NVLW_COMMON_INTR_0_MASK_CORRECTABLE_ENABLE 0x00000001 /* RW--V */
#define NV_NVLW_COMMON_INTR_0_MASK_CORRECTABLE_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLW_COMMON_INTR_0_MASK_INTR0 3:3 /* RWEVF */
#define NV_NVLW_COMMON_INTR_0_MASK_INTR0_ENABLE 0x00000001 /* RW--V */
#define NV_NVLW_COMMON_INTR_0_MASK_INTR0_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLW_COMMON_INTR_0_MASK_INTR1 4:4 /* RWEVF */
#define NV_NVLW_COMMON_INTR_0_MASK_INTR1_ENABLE 0x00000001 /* RW--V */
#define NV_NVLW_COMMON_INTR_0_MASK_INTR1_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLW_COMMON_INTR_0_STATUS 0x00000224 /* R--4R */
#define NV_NVLW_COMMON_INTR_0_STATUS_FATAL 0:0 /* R-EVF */
#define NV_NVLW_COMMON_INTR_0_STATUS_FATAL_INIT 0x00000000 /* R-E-V */
#define NV_NVLW_COMMON_INTR_0_STATUS_NONFATAL 1:1 /* R-EVF */
#define NV_NVLW_COMMON_INTR_0_STATUS_NONFATAL_INIT 0x00000000 /* R-E-V */
#define NV_NVLW_COMMON_INTR_0_STATUS_CORRECTABLE 2:2 /* R-EVF */
#define NV_NVLW_COMMON_INTR_0_STATUS_CORRECTABLE_INIT 0x00000000 /* R-E-V */
#define NV_NVLW_COMMON_INTR_0_STATUS_INTR0 3:3 /* R-EVF */
#define NV_NVLW_COMMON_INTR_0_STATUS_INTR0_INIT 0x00000000 /* R-E-V */
#define NV_NVLW_COMMON_INTR_0_STATUS_INTR1 4:4 /* R-EVF */
#define NV_NVLW_COMMON_INTR_0_STATUS_INTR1_INIT 0x00000000 /* R-E-V */
#define NV_NVLW_COMMON_INTR_1_MASK 0x00000228 /* RW-4R */
#define NV_NVLW_COMMON_INTR_1_MASK_FATAL 0:0 /* RWEVF */
#define NV_NVLW_COMMON_INTR_1_MASK_FATAL_ENABLE 0x00000001 /* RW--V */
#define NV_NVLW_COMMON_INTR_1_MASK_FATAL_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLW_COMMON_INTR_1_MASK_NONFATAL 1:1 /* RWEVF */
#define NV_NVLW_COMMON_INTR_1_MASK_NONFATAL_ENABLE 0x00000001 /* RW--V */
#define NV_NVLW_COMMON_INTR_1_MASK_NONFATAL_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLW_COMMON_INTR_1_MASK_CORRECTABLE 2:2 /* RWEVF */
#define NV_NVLW_COMMON_INTR_1_MASK_CORRECTABLE_ENABLE 0x00000001 /* RW--V */
#define NV_NVLW_COMMON_INTR_1_MASK_CORRECTABLE_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLW_COMMON_INTR_1_MASK_INTR0 3:3 /* RWEVF */
#define NV_NVLW_COMMON_INTR_1_MASK_INTR0_ENABLE 0x00000001 /* RW--V */
#define NV_NVLW_COMMON_INTR_1_MASK_INTR0_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLW_COMMON_INTR_1_MASK_INTR1 4:4 /* RWEVF */
#define NV_NVLW_COMMON_INTR_1_MASK_INTR1_ENABLE 0x00000001 /* RW--V */
#define NV_NVLW_COMMON_INTR_1_MASK_INTR1_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLW_COMMON_INTR_1_STATUS 0x0000022c /* R--4R */
#define NV_NVLW_COMMON_INTR_1_STATUS_FATAL 0:0 /* R-EVF */
#define NV_NVLW_COMMON_INTR_1_STATUS_FATAL_INIT 0x00000000 /* R-E-V */
#define NV_NVLW_COMMON_INTR_1_STATUS_NONFATAL 1:1 /* R-EVF */
#define NV_NVLW_COMMON_INTR_1_STATUS_NONFATAL_INIT 0x00000000 /* R-E-V */
#define NV_NVLW_COMMON_INTR_1_STATUS_CORRECTABLE 2:2 /* R-EVF */
#define NV_NVLW_COMMON_INTR_1_STATUS_CORRECTABLE_INIT 0x00000000 /* R-E-V */
#define NV_NVLW_COMMON_INTR_1_STATUS_INTR0 3:3 /* R-EVF */
#define NV_NVLW_COMMON_INTR_1_STATUS_INTR0_INIT 0x00000000 /* R-E-V */
#define NV_NVLW_COMMON_INTR_1_STATUS_INTR1 4:4 /* R-EVF */
#define NV_NVLW_COMMON_INTR_1_STATUS_INTR1_INIT 0x00000000 /* R-E-V */
#define NV_NVLW_COMMON_INTR_2_MASK 0x00000230 /* RW-4R */
#define NV_NVLW_COMMON_INTR_2_MASK_FATAL 0:0 /* RWEVF */
#define NV_NVLW_COMMON_INTR_2_MASK_FATAL_ENABLE 0x00000001 /* RW--V */
#define NV_NVLW_COMMON_INTR_2_MASK_FATAL_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLW_COMMON_INTR_2_MASK_NONFATAL 1:1 /* RWEVF */
#define NV_NVLW_COMMON_INTR_2_MASK_NONFATAL_ENABLE 0x00000001 /* RW--V */
#define NV_NVLW_COMMON_INTR_2_MASK_NONFATAL_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLW_COMMON_INTR_2_MASK_CORRECTABLE 2:2 /* RWEVF */
#define NV_NVLW_COMMON_INTR_2_MASK_CORRECTABLE_ENABLE 0x00000001 /* RW--V */
#define NV_NVLW_COMMON_INTR_2_MASK_CORRECTABLE_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLW_COMMON_INTR_2_MASK_INTR0 3:3 /* RWEVF */
#define NV_NVLW_COMMON_INTR_2_MASK_INTR0_ENABLE 0x00000001 /* RW--V */
#define NV_NVLW_COMMON_INTR_2_MASK_INTR0_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLW_COMMON_INTR_2_MASK_INTR1 4:4 /* RWEVF */
#define NV_NVLW_COMMON_INTR_2_MASK_INTR1_ENABLE 0x00000001 /* RW--V */
#define NV_NVLW_COMMON_INTR_2_MASK_INTR1_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLW_COMMON_INTR_2_STATUS 0x00000234 /* R--4R */
#define NV_NVLW_COMMON_INTR_2_STATUS_FATAL 0:0 /* R-EVF */
#define NV_NVLW_COMMON_INTR_2_STATUS_FATAL_INIT 0x00000000 /* R-E-V */
#define NV_NVLW_COMMON_INTR_2_STATUS_NONFATAL 1:1 /* R-EVF */
#define NV_NVLW_COMMON_INTR_2_STATUS_NONFATAL_INIT 0x00000000 /* R-E-V */
#define NV_NVLW_COMMON_INTR_2_STATUS_CORRECTABLE 2:2 /* R-EVF */
#define NV_NVLW_COMMON_INTR_2_STATUS_CORRECTABLE_INIT 0x00000000 /* R-E-V */
#define NV_NVLW_COMMON_INTR_2_STATUS_INTR0 3:3 /* R-EVF */
#define NV_NVLW_COMMON_INTR_2_STATUS_INTR0_INIT 0x00000000 /* R-E-V */
#define NV_NVLW_COMMON_INTR_2_STATUS_INTR1 4:4 /* R-EVF */
#define NV_NVLW_COMMON_INTR_2_STATUS_INTR1_INIT 0x00000000 /* R-E-V */
#define NV_NVLW_LINK_INTR_0_MASK(i) (0x00000300+(i)*0x40) /* RW-4A */
#define NV_NVLW_LINK_INTR_0_MASK__SIZE_1 4 /* */
#define NV_NVLW_LINK_INTR_0_MASK_FATAL 0:0 /* RWEVF */
#define NV_NVLW_LINK_INTR_0_MASK_FATAL_ENABLE 0x00000001 /* RW--V */
#define NV_NVLW_LINK_INTR_0_MASK_FATAL_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLW_LINK_INTR_0_MASK_NONFATAL 1:1 /* RWEVF */
#define NV_NVLW_LINK_INTR_0_MASK_NONFATAL_ENABLE 0x00000001 /* RW--V */
#define NV_NVLW_LINK_INTR_0_MASK_NONFATAL_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLW_LINK_INTR_0_MASK_CORRECTABLE 2:2 /* RWEVF */
#define NV_NVLW_LINK_INTR_0_MASK_CORRECTABLE_ENABLE 0x00000001 /* RW--V */
#define NV_NVLW_LINK_INTR_0_MASK_CORRECTABLE_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLW_LINK_INTR_0_MASK_INTR0 3:3 /* RWEVF */
#define NV_NVLW_LINK_INTR_0_MASK_INTR0_ENABLE 0x00000001 /* RW--V */
#define NV_NVLW_LINK_INTR_0_MASK_INTR0_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLW_LINK_INTR_0_MASK_INTR1 4:4 /* RWEVF */
#define NV_NVLW_LINK_INTR_0_MASK_INTR1_ENABLE 0x00000001 /* RW--V */
#define NV_NVLW_LINK_INTR_0_MASK_INTR1_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLW_LINK_INTR_0_STATUS(i) (0x00000304+(i)*0x40) /* R--4A */
#define NV_NVLW_LINK_INTR_0_STATUS__SIZE_1 4 /* */
#define NV_NVLW_LINK_INTR_0_STATUS_FATAL 0:0 /* R-EVF */
#define NV_NVLW_LINK_INTR_0_STATUS_FATAL_INIT 0x00000000 /* R-E-V */
#define NV_NVLW_LINK_INTR_0_STATUS_NONFATAL 1:1 /* R-EVF */
#define NV_NVLW_LINK_INTR_0_STATUS_NONFATAL_INIT 0x00000000 /* R-E-V */
#define NV_NVLW_LINK_INTR_0_STATUS_CORRECTABLE 2:2 /* R-EVF */
#define NV_NVLW_LINK_INTR_0_STATUS_CORRECTABLE_INIT 0x00000000 /* R-E-V */
#define NV_NVLW_LINK_INTR_0_STATUS_INTR0 3:3 /* R-EVF */
#define NV_NVLW_LINK_INTR_0_STATUS_INTR0_INIT 0x00000000 /* R-E-V */
#define NV_NVLW_LINK_INTR_0_STATUS_INTR1 4:4 /* R-EVF */
#define NV_NVLW_LINK_INTR_0_STATUS_INTR1_INIT 0x00000000 /* R-E-V */
#define NV_NVLW_LINK_INTR_1_MASK(i) (0x00000308+(i)*0x40) /* RW-4A */
#define NV_NVLW_LINK_INTR_1_MASK__SIZE_1 4 /* */
#define NV_NVLW_LINK_INTR_1_MASK_FATAL 0:0 /* RWEVF */
#define NV_NVLW_LINK_INTR_1_MASK_FATAL_ENABLE 0x00000001 /* RW--V */
#define NV_NVLW_LINK_INTR_1_MASK_FATAL_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLW_LINK_INTR_1_MASK_NONFATAL 1:1 /* RWEVF */
#define NV_NVLW_LINK_INTR_1_MASK_NONFATAL_ENABLE 0x00000001 /* RW--V */
#define NV_NVLW_LINK_INTR_1_MASK_NONFATAL_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLW_LINK_INTR_1_MASK_CORRECTABLE 2:2 /* RWEVF */
#define NV_NVLW_LINK_INTR_1_MASK_CORRECTABLE_ENABLE 0x00000001 /* RW--V */
#define NV_NVLW_LINK_INTR_1_MASK_CORRECTABLE_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLW_LINK_INTR_1_MASK_INTR0 3:3 /* RWEVF */
#define NV_NVLW_LINK_INTR_1_MASK_INTR0_ENABLE 0x00000001 /* RW--V */
#define NV_NVLW_LINK_INTR_1_MASK_INTR0_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLW_LINK_INTR_1_MASK_INTR1 4:4 /* RWEVF */
#define NV_NVLW_LINK_INTR_1_MASK_INTR1_ENABLE 0x00000001 /* RW--V */
#define NV_NVLW_LINK_INTR_1_MASK_INTR1_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLW_LINK_INTR_1_STATUS(i) (0x0000030c+(i)*0x40) /* R--4A */
#define NV_NVLW_LINK_INTR_1_STATUS__SIZE_1 4 /* */
#define NV_NVLW_LINK_INTR_1_STATUS_FATAL 0:0 /* R-EVF */
#define NV_NVLW_LINK_INTR_1_STATUS_FATAL_INIT 0x00000000 /* R-E-V */
#define NV_NVLW_LINK_INTR_1_STATUS_NONFATAL 1:1 /* R-EVF */
#define NV_NVLW_LINK_INTR_1_STATUS_NONFATAL_INIT 0x00000000 /* R-E-V */
#define NV_NVLW_LINK_INTR_1_STATUS_CORRECTABLE 2:2 /* R-EVF */
#define NV_NVLW_LINK_INTR_1_STATUS_CORRECTABLE_INIT 0x00000000 /* R-E-V */
#define NV_NVLW_LINK_INTR_1_STATUS_INTR0 3:3 /* R-EVF */
#define NV_NVLW_LINK_INTR_1_STATUS_INTR0_INIT 0x00000000 /* R-E-V */
#define NV_NVLW_LINK_INTR_1_STATUS_INTR1 4:4 /* R-EVF */
#define NV_NVLW_LINK_INTR_1_STATUS_INTR1_INIT 0x00000000 /* R-E-V */
#define NV_NVLW_LINK_INTR_2_MASK(i) (0x00000310+(i)*0x40) /* RW-4A */
#define NV_NVLW_LINK_INTR_2_MASK__SIZE_1 4 /* */
#define NV_NVLW_LINK_INTR_2_MASK_FATAL 0:0 /* RWEVF */
#define NV_NVLW_LINK_INTR_2_MASK_FATAL_ENABLE 0x00000001 /* RW--V */
#define NV_NVLW_LINK_INTR_2_MASK_FATAL_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLW_LINK_INTR_2_MASK_NONFATAL 1:1 /* RWEVF */
#define NV_NVLW_LINK_INTR_2_MASK_NONFATAL_ENABLE 0x00000001 /* RW--V */
#define NV_NVLW_LINK_INTR_2_MASK_NONFATAL_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLW_LINK_INTR_2_MASK_CORRECTABLE 2:2 /* RWEVF */
#define NV_NVLW_LINK_INTR_2_MASK_CORRECTABLE_ENABLE 0x00000001 /* RW--V */
#define NV_NVLW_LINK_INTR_2_MASK_CORRECTABLE_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLW_LINK_INTR_2_MASK_INTR0 3:3 /* RWEVF */
#define NV_NVLW_LINK_INTR_2_MASK_INTR0_ENABLE 0x00000001 /* RW--V */
#define NV_NVLW_LINK_INTR_2_MASK_INTR0_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLW_LINK_INTR_2_MASK_INTR1 4:4 /* RWEVF */
#define NV_NVLW_LINK_INTR_2_MASK_INTR1_ENABLE 0x00000001 /* RW--V */
#define NV_NVLW_LINK_INTR_2_MASK_INTR1_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLW_LINK_INTR_2_STATUS(i) (0x00000314+(i)*0x40) /* R--4A */
#define NV_NVLW_LINK_INTR_2_STATUS__SIZE_1 4 /* */
#define NV_NVLW_LINK_INTR_2_STATUS_FATAL 0:0 /* R-EVF */
#define NV_NVLW_LINK_INTR_2_STATUS_FATAL_INIT 0x00000000 /* R-E-V */
#define NV_NVLW_LINK_INTR_2_STATUS_NONFATAL 1:1 /* R-EVF */
#define NV_NVLW_LINK_INTR_2_STATUS_NONFATAL_INIT 0x00000000 /* R-E-V */
#define NV_NVLW_LINK_INTR_2_STATUS_CORRECTABLE 2:2 /* R-EVF */
#define NV_NVLW_LINK_INTR_2_STATUS_CORRECTABLE_INIT 0x00000000 /* R-E-V */
#define NV_NVLW_LINK_INTR_2_STATUS_INTR0 3:3 /* R-EVF */
#define NV_NVLW_LINK_INTR_2_STATUS_INTR0_INIT 0x00000000 /* R-E-V */
#define NV_NVLW_LINK_INTR_2_STATUS_INTR1 4:4 /* R-EVF */
#define NV_NVLW_LINK_INTR_2_STATUS_INTR1_INIT 0x00000000 /* R-E-V */
#endif // __ls10_dev_nvlw_ip_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the Software),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __ls10_dev_nvs_top_h__
#define __ls10_dev_nvs_top_h__
/* This file is autogenerated. Do not edit */
#define NV_SWPTOP /* R--4P */
#define NV_SWPTOP_TABLE_BASE_ADDRESS_OFFSET 0x0002c000 /* */
#define NV_SWPTOP_ENTRY 1:0 /* R-EVF */
#define NV_SWPTOP_ENTRY_INVALID 0x00000000 /* R-E-V */
#define NV_SWPTOP_ENTRY_ENUM 0x00000001 /* R---V */
#define NV_SWPTOP_ENTRY_DATA1 0x00000002 /* R---V */
#define NV_SWPTOP_ENTRY_DATA2 0x00000003 /* R---V */
#define NV_SWPTOP_CONTENTS 30:2 /* R-EVF */
#define NV_SWPTOP_CONTENTS_INIT 0x00000000 /* R-E-V */
#define NV_SWPTOP_CHAIN 31:31 /* R-EVF */
#define NV_SWPTOP_CHAIN_DISABLE 0x00000000 /* R-E-V */
#define NV_SWPTOP_CHAIN_ENABLE 0x00000001 /* R---V */
#define NV_SWPTOP_ENUM_DEVICE 9:2 /* R--UF */
#define NV_SWPTOP_ENUM_DEVICE_INVALID 0x0 /* R---V */
#define NV_SWPTOP_ENUM_DEVICE_PTOP 0x1 /* R---V */
#define NV_SWPTOP_ENUM_DEVICE_SIOCTRL 0x2 /* R---V */
#define NV_SWPTOP_ENUM_DEVICE_SIOCTRL_BCAST 0x3 /* R---V */
#define NV_SWPTOP_ENUM_DEVICE_NPG 0x4 /* R---V */
#define NV_SWPTOP_ENUM_DEVICE_NPG_BCAST 0x5 /* R---V */
#define NV_SWPTOP_ENUM_DEVICE_SWX 0x6 /* R---V */
#define NV_SWPTOP_ENUM_DEVICE_SWX_BCAST 0x7 /* R---V */
#define NV_SWPTOP_ENUM_DEVICE_CLKS 0x8 /* R---V */
#define NV_SWPTOP_ENUM_DEVICE_FUSE 0x9 /* R---V */
#define NV_SWPTOP_ENUM_DEVICE_JTAG 0xa /* R---V */
#define NV_SWPTOP_ENUM_DEVICE_PMGR 0xb /* R---V */
#define NV_SWPTOP_ENUM_DEVICE_SAW 0xc /* R---V */
#define NV_SWPTOP_ENUM_DEVICE_XP3G 0xd /* R---V */
#define NV_SWPTOP_ENUM_DEVICE_XVE 0xe /* R---V */
#define NV_SWPTOP_ENUM_DEVICE_ROM 0xf /* R---V */
#define NV_SWPTOP_ENUM_DEVICE_EXTDEV 0x10 /* R---V */
#define NV_SWPTOP_ENUM_DEVICE_PRIVMAIN 0x11 /* R---V */
#define NV_SWPTOP_ENUM_DEVICE_PRIVLOC 0x12 /* R---V */
#define NV_SWPTOP_ENUM_DEVICE_NVLW 0x13 /* R---V */
#define NV_SWPTOP_ENUM_DEVICE_NVLW_BCAST 0x14 /* R---V */
#define NV_SWPTOP_ENUM_DEVICE_NXBAR 0x15 /* R---V */
#define NV_SWPTOP_ENUM_DEVICE_NXBAR_BCAST 0x16 /* R---V */
#define NV_SWPTOP_ENUM_DEVICE_PXBAR 0x17 /* R---V */
#define NV_SWPTOP_ENUM_DEVICE_PXBAR_BCAST 0x18 /* R---V */
#define NV_SWPTOP_ENUM_DEVICE_PCIE 0x19 /* R---V */
#define NV_SWPTOP_ENUM_DEVICE_PCIE_BCAST 0x1a /* R---V */
#define NV_SWPTOP_ENUM_DEVICE_PTIMER 0x1b /* R---V */
#define NV_SWPTOP_ENUM_DEVICE_TSENSE 0x1c /* R---V */
#define NV_SWPTOP_ENUM_DEVICE_SOE 0x1d /* R---V */
#define NV_SWPTOP_ENUM_DEVICE_SMR 0x1e /* R---V */
#define NV_SWPTOP_ENUM_DEVICE_I2C 0x1f /* R---V */
#define NV_SWPTOP_ENUM_DEVICE_SMBPBI 0x20 /* R---V */
#define NV_SWPTOP_ENUM_DEVICE_SE 0x21 /* R---V */
#define NV_SWPTOP_ENUM_DEVICE_THERM 0x22 /* R---V */
#define NV_SWPTOP_ENUM_DEVICE_XAL 0x23 /* R---V */
#define NV_SWPTOP_ENUM_DEVICE_XPL 0x24 /* R---V */
#define NV_SWPTOP_ENUM_DEVICE_XTL 0x25 /* R---V */
#define NV_SWPTOP_ENUM_DEVICE_GIN 0x26 /* R---V */
#define NV_SWPTOP_ENUM_DEVICE_GPU_PTOP 0x27 /* R---V */
#define NV_SWPTOP_ENUM_DEVICE_PRISEQ 0x28 /* R---V */
#define NV_SWPTOP_ENUM_DEVICE_UXL 0x29 /* R---V */
#define NV_SWPTOP_ENUM_DEVICE_PMC 0x2a /* R---V */
#define NV_SWPTOP_ENUM_DEVICE_PBUS 0x2b /* R---V */
#define NV_SWPTOP_ENUM_DEVICE_ROM2 0x2c /* R---V */
#define NV_SWPTOP_ENUM_DEVICE_GPIO 0x2d /* R---V */
#define NV_SWPTOP_ENUM_DEVICE_XAL_FUNC 0x2e /* R---V */
#define NV_SWPTOP_ENUM_DEVICE_XTL_CONFIG 0x2f /* R---V */
#define NV_SWPTOP_ENUM_DEVICE_FSP 0x30 /* R---V */
#define NV_SWPTOP_ENUM_DEVICE_CLKS_SYS 0x31 /* R---V */
#define NV_SWPTOP_ENUM_DEVICE_CLKS_SYSB 0x32 /* R---V */
#define NV_SWPTOP_ENUM_DEVICE_CLKS_P0 0x33 /* R---V */
#define NV_SWPTOP_ENUM_DEVICE_CLKS_P0_BCAST 0x34 /* R---V */
#define NV_SWPTOP_ENUM_DEVICE_SAW_PM 0x35 /* R---V */
#define NV_SWPTOP_ENUM_DEVICE_PCIE_PM 0x36 /* R---V */
#define NV_SWPTOP_ENUM_DEVICE_PRT_PRI_HUB 0x37 /* R---V */
#define NV_SWPTOP_ENUM_DEVICE_PRT_PRI_RS_CTRL 0x38 /* R---V */
#define NV_SWPTOP_ENUM_DEVICE_PRT_PRI_HUB_BCAST 0x39 /* R---V */
#define NV_SWPTOP_ENUM_DEVICE_PRT_PRI_RS_CTRL_BCAST 0x3a /* R---V */
#define NV_SWPTOP_ENUM_DEVICE_SYS_PRI_HUB 0x3b /* R---V */
#define NV_SWPTOP_ENUM_DEVICE_SYS_PRI_RS_CTRL 0x3c /* R---V */
#define NV_SWPTOP_ENUM_DEVICE_SYSB_PRI_HUB 0x3d /* R---V */
#define NV_SWPTOP_ENUM_DEVICE_SYSB_PRI_RS_CTRL 0x3e /* R---V */
#define NV_SWPTOP_ENUM_DEVICE_PRI_MASTER_RS 0x3f /* R---V */
#define NV_SWPTOP_ENUM_ID 17:10 /* R--UF */
#define NV_SWPTOP_ENUM_MANUALS_TYPE 19:18 /* R--UF */
#define NV_SWPTOP_ENUM_MANUALS_TYPE_ZERO_OFFSET 0x0 /* R---V */
#define NV_SWPTOP_ENUM_MANUALS_TYPE_BAR0_OFFSET 0x1 /* R---V */
#define NV_SWPTOP_ENUM_VERSION 30:20 /* R--UF */
#define NV_SWPTOP_ENUM_VERSION_1 0x1 /* R---V */
#define NV_SWPTOP_ENUM_VERSION_2 0x2 /* R---V */
#define NV_SWPTOP_ENUM_VERSION_3 0x3 /* R---V */
#define NV_SWPTOP_DATA1_RESET 6:2 /* R--UF */
#define NV_SWPTOP_DATA1_INTR 11:7 /* R--UF */
#define NV_SWPTOP_DATA1_RESERVED2 11:2 /* R--UF */
#define NV_SWPTOP_DATA1_CLUSTER_TYPE 16:12 /* R--UF */
#define NV_SWPTOP_DATA1_CLUSTER_TYPE_INVALID 0x0 /* R---V */
#define NV_SWPTOP_DATA1_CLUSTER_TYPE_SYS 0x1 /* R---V */
#define NV_SWPTOP_DATA1_CLUSTER_TYPE_PRT 0x2 /* R---V */
#define NV_SWPTOP_DATA1_CLUSTER_TYPE_SYSB 0x3 /* R---V */
#define NV_SWPTOP_DATA1_CLUSTER_NUMBER 21:17 /* R--UF */
#define NV_SWPTOP_DATA1_RESERVED 30:22 /* R--UF */
#define NV_SWPTOP_DATA1_PTOP_LENGTH 30:2 /* R--UF */
#define NV_SWPTOP_DATA2_TYPE 30:26 /* R--UF */
#define NV_SWPTOP_DATA2_TYPE_INVALID 0x0 /* R---V */
#define NV_SWPTOP_DATA2_TYPE_RESERVED 0x1 /* R---V */
#define NV_SWPTOP_DATA2_TYPE_RESETREG 0x2 /* R---V */
#define NV_SWPTOP_DATA2_TYPE_INTRREG 0x3 /* R---V */
#define NV_SWPTOP_DATA2_TYPE_DISCOVERY 0x4 /* R---V */
#define NV_SWPTOP_DATA2_TYPE_UNICAST 0x5 /* R---V */
#define NV_SWPTOP_DATA2_TYPE_BROADCAST 0x6 /* R---V */
#define NV_SWPTOP_DATA2_TYPE_MULTICAST0 0x7 /* R---V */
#define NV_SWPTOP_DATA2_TYPE_MULTICAST1 0x8 /* R---V */
#define NV_SWPTOP_DATA2_TYPE_MULTICAST2 0x9 /* R---V */
#define NV_SWPTOP_DATA2_ADDR 25:2 /* R--UF */
#endif // __ls10_dev_nvs_top_h__

75
src/common/inc/swref/published/nvswitch/ls10/dev_nxbar_tcp_global_ip.h Normal file
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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the Software),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __ls10_dev_nxbar_tcp_global_ip_h__
#define __ls10_dev_nxbar_tcp_global_ip_h__
/* This file is autogenerated. Do not edit */
#define NV_NXBAR_TCP 0x0001FFFF:0x0000000 /* RW--D */
#define NV_NXBAR_TCP_ERROR_STATUS 0x00000090 /* R--4R */
#define NV_NXBAR_TCP_ERROR_STATUS_TILE0 0:0 /* R--VF */
#define NV_NXBAR_TCP_ERROR_STATUS_TILE0_DEFAULT 0x00000000 /* R---V */
#define NV_NXBAR_TCP_ERROR_STATUS_TILE1 1:1 /* R--VF */
#define NV_NXBAR_TCP_ERROR_STATUS_TILE1_DEFAULT 0x00000000 /* R---V */
#define NV_NXBAR_TCP_ERROR_STATUS_TILE2 2:2 /* R--VF */
#define NV_NXBAR_TCP_ERROR_STATUS_TILE2_DEFAULT 0x00000000 /* R---V */
#define NV_NXBAR_TCP_ERROR_STATUS_TILE3 3:3 /* R--VF */
#define NV_NXBAR_TCP_ERROR_STATUS_TILE3_DEFAULT 0x00000000 /* R---V */
#define NV_NXBAR_TCP_ERROR_STATUS_TILE4 4:4 /* R--VF */
#define NV_NXBAR_TCP_ERROR_STATUS_TILE4_DEFAULT 0x00000000 /* R---V */
#define NV_NXBAR_TCP_ERROR_STATUS_TILE5 5:5 /* R--VF */
#define NV_NXBAR_TCP_ERROR_STATUS_TILE5_DEFAULT 0x00000000 /* R---V */
#define NV_NXBAR_TCP_ERROR_STATUS_TILE6 6:6 /* R--VF */
#define NV_NXBAR_TCP_ERROR_STATUS_TILE6_DEFAULT 0x00000000 /* R---V */
#define NV_NXBAR_TCP_ERROR_STATUS_TILE7 7:7 /* R--VF */
#define NV_NXBAR_TCP_ERROR_STATUS_TILE7_DEFAULT 0x00000000 /* R---V */
#define NV_NXBAR_TCP_ERROR_STATUS_TILE8 8:8 /* R--VF */
#define NV_NXBAR_TCP_ERROR_STATUS_TILE8_DEFAULT 0x00000000 /* R---V */
#define NV_NXBAR_TCP_ERROR_STATUS_TILE9 9:9 /* R--VF */
#define NV_NXBAR_TCP_ERROR_STATUS_TILE9_DEFAULT 0x00000000 /* R---V */
#define NV_NXBAR_TCP_ERROR_STATUS_TILE10 10:10 /* R--VF */
#define NV_NXBAR_TCP_ERROR_STATUS_TILE10_DEFAULT 0x00000000 /* R---V */
#define NV_NXBAR_TCP_ERROR_STATUS_TILE11 11:11 /* R--VF */
#define NV_NXBAR_TCP_ERROR_STATUS_TILE11_DEFAULT 0x00000000 /* R---V */
#define NV_NXBAR_TCP_ERROR_STATUS_TILEOUT0 16:16 /* R--VF */
#define NV_NXBAR_TCP_ERROR_STATUS_TILEOUT0_DEFAULT 0x00000000 /* R---V */
#define NV_NXBAR_TCP_ERROR_STATUS_TILEOUT1 17:17 /* R--VF */
#define NV_NXBAR_TCP_ERROR_STATUS_TILEOUT1_DEFAULT 0x00000000 /* R---V */
#define NV_NXBAR_TCP_ERROR_STATUS_TILEOUT2 18:18 /* R--VF */
#define NV_NXBAR_TCP_ERROR_STATUS_TILEOUT2_DEFAULT 0x00000000 /* R---V */
#define NV_NXBAR_TCP_ERROR_STATUS_TILEOUT3 19:19 /* R--VF */
#define NV_NXBAR_TCP_ERROR_STATUS_TILEOUT3_DEFAULT 0x00000000 /* R---V */
#define NV_NXBAR_TCP_ERROR_STATUS_TILEOUT4 20:20 /* R--VF */
#define NV_NXBAR_TCP_ERROR_STATUS_TILEOUT4_DEFAULT 0x00000000 /* R---V */
#define NV_NXBAR_TCP_ERROR_STATUS_TILEOUT5 21:21 /* R--VF */
#define NV_NXBAR_TCP_ERROR_STATUS_TILEOUT5_DEFAULT 0x00000000 /* R---V */
#define NV_NXBAR_TCP_ERROR_STATUS_TILEOUT6 22:22 /* R--VF */
#define NV_NXBAR_TCP_ERROR_STATUS_TILEOUT6_DEFAULT 0x00000000 /* R---V */
#define NV_NXBAR_TCP_ERROR_STATUS_TILEOUT7 23:23 /* R--VF */
#define NV_NXBAR_TCP_ERROR_STATUS_TILEOUT7_DEFAULT 0x00000000 /* R---V */
#define NV_NXBAR_TCP_ERROR_STATUS_TILEOUT8 24:24 /* R--VF */
#define NV_NXBAR_TCP_ERROR_STATUS_TILEOUT8_DEFAULT 0x00000000 /* R---V */
#define NV_NXBAR_TCP_ERROR_STATUS_TILEOUT9 25:25 /* R--VF */
#define NV_NXBAR_TCP_ERROR_STATUS_TILEOUT9_DEFAULT 0x00000000 /* R---V */
#define NV_NXBAR_TCP_ERROR_STATUS_TILEOUT10 26:26 /* R--VF */
#define NV_NXBAR_TCP_ERROR_STATUS_TILEOUT10_DEFAULT 0x00000000 /* R---V */
#endif // __ls10_dev_nxbar_tcp_global_ip_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the Software),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __ls10_dev_nxbar_tile_ip_h__
#define __ls10_dev_nxbar_tile_ip_h__
/* This file is autogenerated. Do not edit */
#define NV_NXBAR_TILE 0x00000FFF:0x00000000 /* RW--D */
#define NV_NXBAR_TILE_CTRL0 0x00000040 /* RW-4R */
#define NV_NXBAR_TILE_CTRL0_MULTI_VALID_XFN_CTRL 0:0 /* RWEVF */
#define NV_NXBAR_TILE_CTRL0_MULTI_VALID_XFN_CTRL_ENABLE 0x00000000 /* RWE-V */
#define NV_NXBAR_TILE_CTRL0_MULTI_VALID_XFN_CTRL_DISABLE 0x00000001 /* RW--V */
#define NV_NXBAR_TILE_CTRL0_PARTIAL_RAM_WR_CTRL 8:8 /* RWEVF */
#define NV_NXBAR_TILE_CTRL0_PARTIAL_RAM_WR_CTRL_ENABLE 0x00000000 /* RWE-V */
#define NV_NXBAR_TILE_CTRL0_PARTIAL_RAM_WR_CTRL_DISABLE 0x00000001 /* RW--V */
#define NV_NXBAR_TILE_CTRL0_PRI_FGCG_CTRL 16:16 /* RWEVF */
#define NV_NXBAR_TILE_CTRL0_PRI_FGCG_CTRL_ENABLE 0x00000001 /* RW--V */
#define NV_NXBAR_TILE_CTRL0_PRI_FGCG_CTRL_DISABLE 0x00000000 /* RWE-V */
#define NV_NXBAR_TILE_CTRL0_PRI_FGCG_CTRL__PROD 0x00000001 /* RW--V */
#define NV_NXBAR_TILE_ERR_STATUS 0x00000064 /* RW-4R */
#define NV_NXBAR_TILE_ERR_STATUS_INGRESS_BUFFER_OVERFLOW 0:0 /* RWIVF */
#define NV_NXBAR_TILE_ERR_STATUS_INGRESS_BUFFER_OVERFLOW_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TILE_ERR_STATUS_INGRESS_BUFFER_UNDERFLOW 1:1 /* RWIVF */
#define NV_NXBAR_TILE_ERR_STATUS_INGRESS_BUFFER_UNDERFLOW_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TILE_ERR_STATUS_EGRESS_CREDIT_OVERFLOW 2:2 /* RWIVF */
#define NV_NXBAR_TILE_ERR_STATUS_EGRESS_CREDIT_OVERFLOW_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TILE_ERR_STATUS_EGRESS_CREDIT_UNDERFLOW 3:3 /* RWIVF */
#define NV_NXBAR_TILE_ERR_STATUS_EGRESS_CREDIT_UNDERFLOW_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TILE_ERR_STATUS_INGRESS_NON_BURSTY_PKT 4:4 /* RWIVF */
#define NV_NXBAR_TILE_ERR_STATUS_INGRESS_NON_BURSTY_PKT_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TILE_ERR_STATUS_INGRESS_NON_STICKY_PKT 5:5 /* RWIVF */
#define NV_NXBAR_TILE_ERR_STATUS_INGRESS_NON_STICKY_PKT_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TILE_ERR_STATUS_INGRESS_BURST_GT_9_DATA_VC 6:6 /* RWIVF */
#define NV_NXBAR_TILE_ERR_STATUS_INGRESS_BURST_GT_9_DATA_VC_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TILE_ERR_STATUS_INGRESS_PKT_INVALID_DST 7:7 /* RWIVF */
#define NV_NXBAR_TILE_ERR_STATUS_INGRESS_PKT_INVALID_DST_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TILE_ERR_STATUS_INGRESS_PKT_PARITY_ERROR 8:8 /* RWIVF */
#define NV_NXBAR_TILE_ERR_STATUS_INGRESS_PKT_PARITY_ERROR_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TILE_ERR_STATUS_INGRESS_SIDEBAND_PARITY_ERROR 9:9 /* RWIVF */
#define NV_NXBAR_TILE_ERR_STATUS_INGRESS_SIDEBAND_PARITY_ERROR_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TILE_ERR_STATUS_INGRESS_REDUCTION_PKT_ERROR 10:10 /* RWIVF */
#define NV_NXBAR_TILE_ERR_STATUS_INGRESS_REDUCTION_PKT_ERROR_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TILE_ERR_FATAL_INTR_EN 0x0000006c /* RW-4R */
#define NV_NXBAR_TILE_ERR_FATAL_INTR_EN_INGRESS_BUFFER_OVERFLOW 0:0 /* RWIVF */
#define NV_NXBAR_TILE_ERR_FATAL_INTR_EN_INGRESS_BUFFER_OVERFLOW_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TILE_ERR_FATAL_INTR_EN_INGRESS_BUFFER_OVERFLOW_ENABLED 0x00000001 /* RW--V */
#define NV_NXBAR_TILE_ERR_FATAL_INTR_EN_INGRESS_BUFFER_OVERFLOW__PROD 0x00000001 /* RW--V */
#define NV_NXBAR_TILE_ERR_FATAL_INTR_EN_INGRESS_BUFFER_UNDERFLOW 1:1 /* RWIVF */
#define NV_NXBAR_TILE_ERR_FATAL_INTR_EN_INGRESS_BUFFER_UNDERFLOW_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TILE_ERR_FATAL_INTR_EN_INGRESS_BUFFER_UNDERFLOW_ENABLED 0x00000001 /* RW--V */
#define NV_NXBAR_TILE_ERR_FATAL_INTR_EN_INGRESS_BUFFER_UNDERFLOW__PROD 0x00000001 /* RW--V */
#define NV_NXBAR_TILE_ERR_FATAL_INTR_EN_EGRESS_CREDIT_OVERFLOW 2:2 /* RWIVF */
#define NV_NXBAR_TILE_ERR_FATAL_INTR_EN_EGRESS_CREDIT_OVERFLOW_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TILE_ERR_FATAL_INTR_EN_EGRESS_CREDIT_OVERFLOW_ENABLED 0x00000001 /* RW--V */
#define NV_NXBAR_TILE_ERR_FATAL_INTR_EN_EGRESS_CREDIT_OVERFLOW__PROD 0x00000001 /* RW--V */
#define NV_NXBAR_TILE_ERR_FATAL_INTR_EN_EGRESS_CREDIT_UNDERFLOW 3:3 /* RWIVF */
#define NV_NXBAR_TILE_ERR_FATAL_INTR_EN_EGRESS_CREDIT_UNDERFLOW_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TILE_ERR_FATAL_INTR_EN_EGRESS_CREDIT_UNDERFLOW_ENABLED 0x00000001 /* RW--V */
#define NV_NXBAR_TILE_ERR_FATAL_INTR_EN_EGRESS_CREDIT_UNDERFLOW__PROD 0x00000001 /* RW--V */
#define NV_NXBAR_TILE_ERR_FATAL_INTR_EN_INGRESS_NON_BURSTY_PKT 4:4 /* RWIVF */
#define NV_NXBAR_TILE_ERR_FATAL_INTR_EN_INGRESS_NON_BURSTY_PKT_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TILE_ERR_FATAL_INTR_EN_INGRESS_NON_BURSTY_PKT_ENABLED 0x00000001 /* RW--V */
#define NV_NXBAR_TILE_ERR_FATAL_INTR_EN_INGRESS_NON_BURSTY_PKT__PROD 0x00000001 /* RW--V */
#define NV_NXBAR_TILE_ERR_FATAL_INTR_EN_INGRESS_NON_STICKY_PKT 5:5 /* RWIVF */
#define NV_NXBAR_TILE_ERR_FATAL_INTR_EN_INGRESS_NON_STICKY_PKT_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TILE_ERR_FATAL_INTR_EN_INGRESS_NON_STICKY_PKT_ENABLED 0x00000001 /* RW--V */
#define NV_NXBAR_TILE_ERR_FATAL_INTR_EN_INGRESS_NON_STICKY_PKT__PROD 0x00000001 /* RW--V */
#define NV_NXBAR_TILE_ERR_FATAL_INTR_EN_INGRESS_BURST_GT_9_DATA_VC 6:6 /* RWIVF */
#define NV_NXBAR_TILE_ERR_FATAL_INTR_EN_INGRESS_BURST_GT_9_DATA_VC_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TILE_ERR_FATAL_INTR_EN_INGRESS_BURST_GT_9_DATA_VC_ENABLED 0x00000001 /* RW--V */
#define NV_NXBAR_TILE_ERR_FATAL_INTR_EN_INGRESS_BURST_GT_9_DATA_VC__PROD 0x00000001 /* RW--V */
#define NV_NXBAR_TILE_ERR_FATAL_INTR_EN_INGRESS_PKT_INVALID_DST 7:7 /* RWIVF */
#define NV_NXBAR_TILE_ERR_FATAL_INTR_EN_INGRESS_PKT_INVALID_DST_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TILE_ERR_FATAL_INTR_EN_INGRESS_PKT_INVALID_DST_ENABLED 0x00000001 /* RW--V */
#define NV_NXBAR_TILE_ERR_FATAL_INTR_EN_INGRESS_PKT_INVALID_DST__PROD 0x00000001 /* RW--V */
#define NV_NXBAR_TILE_ERR_FATAL_INTR_EN_INGRESS_PKT_PARITY_ERROR 8:8 /* RWIVF */
#define NV_NXBAR_TILE_ERR_FATAL_INTR_EN_INGRESS_PKT_PARITY_ERROR_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TILE_ERR_FATAL_INTR_EN_INGRESS_PKT_PARITY_ERROR_ENABLED 0x00000001 /* RW--V */
#define NV_NXBAR_TILE_ERR_FATAL_INTR_EN_INGRESS_PKT_PARITY_ERROR__PROD 0x00000001 /* RW--V */
#define NV_NXBAR_TILE_ERR_FATAL_INTR_EN_INGRESS_SIDEBAND_PARITY_ERROR 9:9 /* RWIVF */
#define NV_NXBAR_TILE_ERR_FATAL_INTR_EN_INGRESS_SIDEBAND_PARITY_ERROR_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TILE_ERR_FATAL_INTR_EN_INGRESS_SIDEBAND_PARITY_ERROR_ENABLED 0x00000001 /* RW--V */
#define NV_NXBAR_TILE_ERR_FATAL_INTR_EN_INGRESS_SIDEBAND_PARITY_ERROR__PROD 0x00000001 /* RW--V */
#define NV_NXBAR_TILE_ERR_FATAL_INTR_EN_INGRESS_REDUCTION_PKT_ERROR 10:10 /* RWIVF */
#define NV_NXBAR_TILE_ERR_FATAL_INTR_EN_INGRESS_REDUCTION_PKT_ERROR_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TILE_ERR_FATAL_INTR_EN_INGRESS_REDUCTION_PKT_ERROR_ENABLED 0x00000001 /* RW--V */
#define NV_NXBAR_TILE_ERR_FATAL_INTR_EN_INGRESS_REDUCTION_PKT_ERROR__PROD 0x00000001 /* RW--V */
#define NV_NXBAR_TILE_ERR_FIRST 0x00000070 /* RW-4R */
#define NV_NXBAR_TILE_ERR_FIRST_INGRESS_BUFFER_OVERFLOW 0:0 /* RWIVF */
#define NV_NXBAR_TILE_ERR_FIRST_INGRESS_BUFFER_OVERFLOW_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TILE_ERR_FIRST_INGRESS_BUFFER_UNDERFLOW 1:1 /* RWIVF */
#define NV_NXBAR_TILE_ERR_FIRST_INGRESS_BUFFER_UNDERFLOW_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TILE_ERR_FIRST_EGRESS_CREDIT_OVERFLOW 2:2 /* RWIVF */
#define NV_NXBAR_TILE_ERR_FIRST_EGRESS_CREDIT_OVERFLOW_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TILE_ERR_FIRST_EGRESS_CREDIT_UNDERFLOW 3:3 /* RWIVF */
#define NV_NXBAR_TILE_ERR_FIRST_EGRESS_CREDIT_UNDERFLOW_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TILE_ERR_FIRST_INGRESS_NON_BURSTY_PKT 4:4 /* RWIVF */
#define NV_NXBAR_TILE_ERR_FIRST_INGRESS_NON_BURSTY_PKT_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TILE_ERR_FIRST_INGRESS_NON_STICKY_PKT 5:5 /* RWIVF */
#define NV_NXBAR_TILE_ERR_FIRST_INGRESS_NON_STICKY_PKT_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TILE_ERR_FIRST_INGRESS_BURST_GT_9_DATA_VC 6:6 /* RWIVF */
#define NV_NXBAR_TILE_ERR_FIRST_INGRESS_BURST_GT_9_DATA_VC_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TILE_ERR_FIRST_INGRESS_PKT_INVALID_DST 7:7 /* RWIVF */
#define NV_NXBAR_TILE_ERR_FIRST_INGRESS_PKT_INVALID_DST_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TILE_ERR_FIRST_INGRESS_PKT_PARITY_ERROR 8:8 /* RWIVF */
#define NV_NXBAR_TILE_ERR_FIRST_INGRESS_PKT_PARITY_ERROR_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TILE_ERR_FIRST_INGRESS_SIDEBAND_PARITY_ERROR 9:9 /* RWIVF */
#define NV_NXBAR_TILE_ERR_FIRST_INGRESS_SIDEBAND_PARITY_ERROR_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TILE_ERR_FIRST_INGRESS_REDUCTION_PKT_ERROR 10:10 /* RWIVF */
#define NV_NXBAR_TILE_ERR_FIRST_INGRESS_REDUCTION_PKT_ERROR_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TILE_ERR_FIRST_LOG_VC 15:12 /* RWIVF */
#define NV_NXBAR_TILE_ERR_FIRST_LOG_VC_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TILE_ERR_FIRST_LOG_SRC 19:16 /* RWIVF */
#define NV_NXBAR_TILE_ERR_FIRST_LOG_SRC_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TILE_ERR_FIRST_LOG_DST 27:24 /* RWIVF */
#define NV_NXBAR_TILE_ERR_FIRST_LOG_DST_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TILE_PRI_NXBAR_TILE_CG 0x00000048 /* RWE4R */
#define NV_NXBAR_TILE_PRI_NXBAR_TILE_CG_IDLE_CG_DLY_CNT 5:0 /* RWEVF */
#define NV_NXBAR_TILE_PRI_NXBAR_TILE_CG_IDLE_CG_DLY_CNT_HWINIT 0x00000000 /* RWE-V */
#define NV_NXBAR_TILE_PRI_NXBAR_TILE_CG_IDLE_CG_DLY_CNT__PROD 0x00000008 /* RW--V */
#define NV_NXBAR_TILE_PRI_NXBAR_TILE_CG_IDLE_CG_EN 6:6 /* RWEVF */
#define NV_NXBAR_TILE_PRI_NXBAR_TILE_CG_IDLE_CG_EN_ENABLED 0x00000001 /* RW--V */
#define NV_NXBAR_TILE_PRI_NXBAR_TILE_CG_IDLE_CG_EN_DISABLED 0x00000000 /* RWE-V */
#define NV_NXBAR_TILE_PRI_NXBAR_TILE_CG_IDLE_CG_EN__PROD 0x00000001 /* RW--V */
#define NV_NXBAR_TILE_PRI_NXBAR_TILE_CG_STATE_CG_EN 7:7 /* */
#define NV_NXBAR_TILE_PRI_NXBAR_TILE_CG_STATE_CG_EN_ENABLED 0x00000001 /* */
#define NV_NXBAR_TILE_PRI_NXBAR_TILE_CG_STATE_CG_EN_DISABLED 0x00000000 /* */
#define NV_NXBAR_TILE_PRI_NXBAR_TILE_CG_STATE_CG_EN__PROD 0x00000000 /* */
#define NV_NXBAR_TILE_PRI_NXBAR_TILE_CG_STALL_CG_DLY_CNT 13:8 /* */
#define NV_NXBAR_TILE_PRI_NXBAR_TILE_CG_STALL_CG_DLY_CNT_HWINIT 0x00000000 /* */
#define NV_NXBAR_TILE_PRI_NXBAR_TILE_CG_STALL_CG_DLY_CNT__PROD 0x00000000 /* */
#define NV_NXBAR_TILE_PRI_NXBAR_TILE_CG_STALL_CG_EN 14:14 /* RWEVF */
#define NV_NXBAR_TILE_PRI_NXBAR_TILE_CG_STALL_CG_EN_ENABLED 0x00000001 /* RW--V */
#define NV_NXBAR_TILE_PRI_NXBAR_TILE_CG_STALL_CG_EN_DISABLED 0x00000000 /* RWE-V */
#define NV_NXBAR_TILE_PRI_NXBAR_TILE_CG_STALL_CG_EN__PROD 0x00000000 /* RW--V */
#define NV_NXBAR_TILE_PRI_NXBAR_TILE_CG_QUIESCENT_CG_EN 15:15 /* */
#define NV_NXBAR_TILE_PRI_NXBAR_TILE_CG_QUIESCENT_CG_EN_ENABLED 0x00000001 /* */
#define NV_NXBAR_TILE_PRI_NXBAR_TILE_CG_QUIESCENT_CG_EN_DISABLED 0x00000000 /* */
#define NV_NXBAR_TILE_PRI_NXBAR_TILE_CG_QUIESCENT_CG_EN__PROD 0x00000000 /* */
#define NV_NXBAR_TILE_PRI_NXBAR_TILE_CG_WAKEUP_DLY_CNT 19:16 /* RWEVF */
#define NV_NXBAR_TILE_PRI_NXBAR_TILE_CG_WAKEUP_DLY_CNT_HWINIT 0x00000000 /* RWE-V */
#define NV_NXBAR_TILE_PRI_NXBAR_TILE_CG_WAKEUP_DLY_CNT__PROD 0x00000000 /* RW--V */
#define NV_NXBAR_TILE_PRI_NXBAR_TILE_CG_THROT_CLK_CNT 23:20 /* */
#define NV_NXBAR_TILE_PRI_NXBAR_TILE_CG_THROT_CLK_CNT_FULLSPEED 0x0000000f /* */
#define NV_NXBAR_TILE_PRI_NXBAR_TILE_CG_THROT_CLK_CNT__PROD 0x00000000 /* */
#define NV_NXBAR_TILE_PRI_NXBAR_TILE_CG_DI_DT_SKEW_VAL 27:24 /* */
#define NV_NXBAR_TILE_PRI_NXBAR_TILE_CG_DI_DT_SKEW_VAL_HWINIT 0x00000000 /* */
#define NV_NXBAR_TILE_PRI_NXBAR_TILE_CG_DI_DT_SKEW_VAL__PROD 0x00000000 /* */
#define NV_NXBAR_TILE_PRI_NXBAR_TILE_CG_THROT_CLK_EN 28:28 /* */
#define NV_NXBAR_TILE_PRI_NXBAR_TILE_CG_THROT_CLK_EN_ENABLED 0x00000001 /* */
#define NV_NXBAR_TILE_PRI_NXBAR_TILE_CG_THROT_CLK_EN_DISABLED 0x00000000 /* */
#define NV_NXBAR_TILE_PRI_NXBAR_TILE_CG_THROT_CLK_EN__PROD 0x00000000 /* */
#define NV_NXBAR_TILE_PRI_NXBAR_TILE_CG_THROT_CLK_SW_OVER 29:29 /* */
#define NV_NXBAR_TILE_PRI_NXBAR_TILE_CG_THROT_CLK_SW_OVER_EN 0x00000001 /* */
#define NV_NXBAR_TILE_PRI_NXBAR_TILE_CG_THROT_CLK_SW_OVER_DIS 0x00000000 /* */
#define NV_NXBAR_TILE_PRI_NXBAR_TILE_CG_THROT_CLK_SW_OVER__PROD 0x00000000 /* */
#define NV_NXBAR_TILE_PRI_NXBAR_TILE_CG_PAUSE_CG_EN 30:30 /* */
#define NV_NXBAR_TILE_PRI_NXBAR_TILE_CG_PAUSE_CG_EN_ENABLED 0x00000001 /* */
#define NV_NXBAR_TILE_PRI_NXBAR_TILE_CG_PAUSE_CG_EN_DISABLED 0x00000000 /* */
#define NV_NXBAR_TILE_PRI_NXBAR_TILE_CG_PAUSE_CG_EN__PROD 0x00000000 /* */
#define NV_NXBAR_TILE_PRI_NXBAR_TILE_CG_HALT_CG_EN 31:31 /* */
#define NV_NXBAR_TILE_PRI_NXBAR_TILE_CG_HALT_CG_EN_ENABLED 0x00000001 /* */
#define NV_NXBAR_TILE_PRI_NXBAR_TILE_CG_HALT_CG_EN_DISABLED 0x00000000 /* */
#define NV_NXBAR_TILE_PRI_NXBAR_TILE_CG_HALT_CG_EN__PROD 0x00000000 /* */
#define NV_NXBAR_TILE_PRI_NXBAR_TILE_CG1 0x0000004C /* RWE4R */
#define NV_NXBAR_TILE_PRI_NXBAR_TILE_CG1_MONITOR_CG_EN 0:0 /* RWEVF */
#define NV_NXBAR_TILE_PRI_NXBAR_TILE_CG1_MONITOR_CG_EN_ENABLED 0x00000001 /* RW--V */
#define NV_NXBAR_TILE_PRI_NXBAR_TILE_CG1_MONITOR_CG_EN_DISABLED 0x00000000 /* RWE-V */
#define NV_NXBAR_TILE_PRI_NXBAR_TILE_CG1_MONITOR_CG_EN__PROD 0x00000000 /* RW--V */
#endif // __ls10_dev_nxbar_tile_ip_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the Software),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __ls10_dev_nxbar_tileout_ip_h__
#define __ls10_dev_nxbar_tileout_ip_h__
/* This file is autogenerated. Do not edit */
#define NV_NXBAR_TILEOUT 0x00000FFF:0x0000000 /* RW--D */
#define NV_NXBAR_TILEOUT_CTRL0 0x00000040 /* RW-4R */
#define NV_NXBAR_TILEOUT_CTRL0_MULTI_VALID_XFN_CTRL 0:0 /* RWEVF */
#define NV_NXBAR_TILEOUT_CTRL0_MULTI_VALID_XFN_CTRL_ENABLE 0x00000000 /* RWE-V */
#define NV_NXBAR_TILEOUT_CTRL0_MULTI_VALID_XFN_CTRL_DISABLE 0x00000001 /* RW--V */
#define NV_NXBAR_TILEOUT_CTRL0_PARTIAL_RAM_WR_CTRL 8:8 /* RWEVF */
#define NV_NXBAR_TILEOUT_CTRL0_PARTIAL_RAM_WR_CTRL_ENABLE 0x00000000 /* RWE-V */
#define NV_NXBAR_TILEOUT_CTRL0_PARTIAL_RAM_WR_CTRL_DISABLE 0x00000001 /* RW--V */
#define NV_NXBAR_TILEOUT_CTRL0_PRI_FGCG_CTRL 16:16 /* RWEVF */
#define NV_NXBAR_TILEOUT_CTRL0_PRI_FGCG_CTRL_ENABLE 0x00000001 /* RW--V */
#define NV_NXBAR_TILEOUT_CTRL0_PRI_FGCG_CTRL_DISABLE 0x00000000 /* RWE-V */
#define NV_NXBAR_TILEOUT_CTRL0_PRI_FGCG_CTRL__PROD 0x00000001 /* RW--V */
#define NV_NXBAR_TILEOUT_ERR_STATUS 0x00000064 /* RW-4R */
#define NV_NXBAR_TILEOUT_ERR_STATUS_INGRESS_BUFFER_OVERFLOW 0:0 /* RWIVF */
#define NV_NXBAR_TILEOUT_ERR_STATUS_INGRESS_BUFFER_OVERFLOW_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TILEOUT_ERR_STATUS_INGRESS_BUFFER_UNDERFLOW 1:1 /* RWIVF */
#define NV_NXBAR_TILEOUT_ERR_STATUS_INGRESS_BUFFER_UNDERFLOW_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TILEOUT_ERR_STATUS_EGRESS_CREDIT_OVERFLOW 2:2 /* RWIVF */
#define NV_NXBAR_TILEOUT_ERR_STATUS_EGRESS_CREDIT_OVERFLOW_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TILEOUT_ERR_STATUS_EGRESS_CREDIT_UNDERFLOW 3:3 /* RWIVF */
#define NV_NXBAR_TILEOUT_ERR_STATUS_EGRESS_CREDIT_UNDERFLOW_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TILEOUT_ERR_STATUS_INGRESS_NON_BURSTY_PKT 4:4 /* RWIVF */
#define NV_NXBAR_TILEOUT_ERR_STATUS_INGRESS_NON_BURSTY_PKT_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TILEOUT_ERR_STATUS_INGRESS_NON_STICKY_PKT 5:5 /* RWIVF */
#define NV_NXBAR_TILEOUT_ERR_STATUS_INGRESS_NON_STICKY_PKT_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TILEOUT_ERR_STATUS_INGRESS_BURST_GT_9_DATA_VC 6:6 /* RWIVF */
#define NV_NXBAR_TILEOUT_ERR_STATUS_INGRESS_BURST_GT_9_DATA_VC_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TILEOUT_ERR_STATUS_EGRESS_CDT_PARITY_ERROR 7:7 /* RWIVF */
#define NV_NXBAR_TILEOUT_ERR_STATUS_EGRESS_CDT_PARITY_ERROR_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TILEOUT_ERR_FATAL_INTR_EN 0x0000006c /* RW-4R */
#define NV_NXBAR_TILEOUT_ERR_FATAL_INTR_EN_INGRESS_BUFFER_OVERFLOW 0:0 /* RWIVF */
#define NV_NXBAR_TILEOUT_ERR_FATAL_INTR_EN_INGRESS_BUFFER_OVERFLOW_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TILEOUT_ERR_FATAL_INTR_EN_INGRESS_BUFFER_OVERFLOW_ENABLED 0x00000001 /* RW--V */
#define NV_NXBAR_TILEOUT_ERR_FATAL_INTR_EN_INGRESS_BUFFER_OVERFLOW__PROD 0x00000001 /* RW--V */
#define NV_NXBAR_TILEOUT_ERR_FATAL_INTR_EN_INGRESS_BUFFER_UNDERFLOW 1:1 /* RWIVF */
#define NV_NXBAR_TILEOUT_ERR_FATAL_INTR_EN_INGRESS_BUFFER_UNDERFLOW_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TILEOUT_ERR_FATAL_INTR_EN_INGRESS_BUFFER_UNDERFLOW_ENABLED 0x00000001 /* RW--V */
#define NV_NXBAR_TILEOUT_ERR_FATAL_INTR_EN_INGRESS_BUFFER_UNDERFLOW__PROD 0x00000001 /* RW--V */
#define NV_NXBAR_TILEOUT_ERR_FATAL_INTR_EN_EGRESS_CREDIT_OVERFLOW 2:2 /* RWIVF */
#define NV_NXBAR_TILEOUT_ERR_FATAL_INTR_EN_EGRESS_CREDIT_OVERFLOW_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TILEOUT_ERR_FATAL_INTR_EN_EGRESS_CREDIT_OVERFLOW_ENABLED 0x00000001 /* RW--V */
#define NV_NXBAR_TILEOUT_ERR_FATAL_INTR_EN_EGRESS_CREDIT_OVERFLOW__PROD 0x00000001 /* RW--V */
#define NV_NXBAR_TILEOUT_ERR_FATAL_INTR_EN_EGRESS_CREDIT_UNDERFLOW 3:3 /* RWIVF */
#define NV_NXBAR_TILEOUT_ERR_FATAL_INTR_EN_EGRESS_CREDIT_UNDERFLOW_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TILEOUT_ERR_FATAL_INTR_EN_EGRESS_CREDIT_UNDERFLOW_ENABLED 0x00000001 /* RW--V */
#define NV_NXBAR_TILEOUT_ERR_FATAL_INTR_EN_EGRESS_CREDIT_UNDERFLOW__PROD 0x00000001 /* RW--V */
#define NV_NXBAR_TILEOUT_ERR_FATAL_INTR_EN_INGRESS_NON_BURSTY_PKT 4:4 /* RWIVF */
#define NV_NXBAR_TILEOUT_ERR_FATAL_INTR_EN_INGRESS_NON_BURSTY_PKT_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TILEOUT_ERR_FATAL_INTR_EN_INGRESS_NON_BURSTY_PKT_ENABLED 0x00000001 /* RW--V */
#define NV_NXBAR_TILEOUT_ERR_FATAL_INTR_EN_INGRESS_NON_BURSTY_PKT__PROD 0x00000001 /* RW--V */
#define NV_NXBAR_TILEOUT_ERR_FATAL_INTR_EN_INGRESS_NON_STICKY_PKT 5:5 /* RWIVF */
#define NV_NXBAR_TILEOUT_ERR_FATAL_INTR_EN_INGRESS_NON_STICKY_PKT_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TILEOUT_ERR_FATAL_INTR_EN_INGRESS_NON_STICKY_PKT_ENABLED 0x00000001 /* RW--V */
#define NV_NXBAR_TILEOUT_ERR_FATAL_INTR_EN_INGRESS_NON_STICKY_PKT__PROD 0x00000001 /* RW--V */
#define NV_NXBAR_TILEOUT_ERR_FATAL_INTR_EN_INGRESS_BURST_GT_9_DATA_VC 6:6 /* RWIVF */
#define NV_NXBAR_TILEOUT_ERR_FATAL_INTR_EN_INGRESS_BURST_GT_9_DATA_VC_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TILEOUT_ERR_FATAL_INTR_EN_INGRESS_BURST_GT_9_DATA_VC_ENABLED 0x00000001 /* RW--V */
#define NV_NXBAR_TILEOUT_ERR_FATAL_INTR_EN_INGRESS_BURST_GT_9_DATA_VC__PROD 0x00000001 /* RW--V */
#define NV_NXBAR_TILEOUT_ERR_FATAL_INTR_EN_EGRESS_CDT_PARITY_ERROR 7:7 /* RWIVF */
#define NV_NXBAR_TILEOUT_ERR_FATAL_INTR_EN_EGRESS_CDT_PARITY_ERROR_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TILEOUT_ERR_FATAL_INTR_EN_EGRESS_CDT_PARITY_ERROR_ENABLED 0x00000001 /* RW--V */
#define NV_NXBAR_TILEOUT_ERR_FATAL_INTR_EN_EGRESS_CDT_PARITY_ERROR__PROD 0x00000001 /* RW--V */
#define NV_NXBAR_TILEOUT_ERR_FIRST 0x00000070 /* RW-4R */
#define NV_NXBAR_TILEOUT_ERR_FIRST_INGRESS_BUFFER_OVERFLOW 0:0 /* RWIVF */
#define NV_NXBAR_TILEOUT_ERR_FIRST_INGRESS_BUFFER_OVERFLOW_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TILEOUT_ERR_FIRST_INGRESS_BUFFER_UNDERFLOW 1:1 /* RWIVF */
#define NV_NXBAR_TILEOUT_ERR_FIRST_INGRESS_BUFFER_UNDERFLOW_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TILEOUT_ERR_FIRST_EGRESS_CREDIT_OVERFLOW 2:2 /* RWIVF */
#define NV_NXBAR_TILEOUT_ERR_FIRST_EGRESS_CREDIT_OVERFLOW_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TILEOUT_ERR_FIRST_EGRESS_CREDIT_UNDERFLOW 3:3 /* RWIVF */
#define NV_NXBAR_TILEOUT_ERR_FIRST_EGRESS_CREDIT_UNDERFLOW_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TILEOUT_ERR_FIRST_INGRESS_NON_BURSTY_PKT 4:4 /* RWIVF */
#define NV_NXBAR_TILEOUT_ERR_FIRST_INGRESS_NON_BURSTY_PKT_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TILEOUT_ERR_FIRST_INGRESS_NON_STICKY_PKT 5:5 /* RWIVF */
#define NV_NXBAR_TILEOUT_ERR_FIRST_INGRESS_NON_STICKY_PKT_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TILEOUT_ERR_FIRST_INGRESS_BURST_GT_9_DATA_VC 6:6 /* RWIVF */
#define NV_NXBAR_TILEOUT_ERR_FIRST_INGRESS_BURST_GT_9_DATA_VC_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TILEOUT_ERR_FIRST_EGRESS_CDT_PARITY_ERROR 7:7 /* RWIVF */
#define NV_NXBAR_TILEOUT_ERR_FIRST_EGRESS_CDT_PARITY_ERROR_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TILEOUT_ERR_FIRST_LOG_VC 15:12 /* RWIVF */
#define NV_NXBAR_TILEOUT_ERR_FIRST_LOG_VC_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TILEOUT_ERR_FIRST_LOG_SRC 19:16 /* RWIVF */
#define NV_NXBAR_TILEOUT_ERR_FIRST_LOG_SRC_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TILEOUT_ERR_FIRST_LOG_DST 25:24 /* RWIVF */
#define NV_NXBAR_TILEOUT_ERR_FIRST_LOG_DST_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TILEOUT_PRI_NXBAR_TILEOUT_CG 0x00000048 /* RWE4R */
#define NV_NXBAR_TILEOUT_PRI_NXBAR_TILEOUT_CG_IDLE_CG_DLY_CNT 5:0 /* RWEVF */
#define NV_NXBAR_TILEOUT_PRI_NXBAR_TILEOUT_CG_IDLE_CG_DLY_CNT_HWINIT 0x00000000 /* RWE-V */
#define NV_NXBAR_TILEOUT_PRI_NXBAR_TILEOUT_CG_IDLE_CG_DLY_CNT__PROD 0x00000008 /* RW--V */
#define NV_NXBAR_TILEOUT_PRI_NXBAR_TILEOUT_CG_IDLE_CG_EN 6:6 /* RWEVF */
#define NV_NXBAR_TILEOUT_PRI_NXBAR_TILEOUT_CG_IDLE_CG_EN_ENABLED 0x00000001 /* RW--V */
#define NV_NXBAR_TILEOUT_PRI_NXBAR_TILEOUT_CG_IDLE_CG_EN_DISABLED 0x00000000 /* RWE-V */
#define NV_NXBAR_TILEOUT_PRI_NXBAR_TILEOUT_CG_IDLE_CG_EN__PROD 0x00000001 /* RW--V */
#define NV_NXBAR_TILEOUT_PRI_NXBAR_TILEOUT_CG_STATE_CG_EN 7:7 /* */
#define NV_NXBAR_TILEOUT_PRI_NXBAR_TILEOUT_CG_STATE_CG_EN_ENABLED 0x00000001 /* */
#define NV_NXBAR_TILEOUT_PRI_NXBAR_TILEOUT_CG_STATE_CG_EN_DISABLED 0x00000000 /* */
#define NV_NXBAR_TILEOUT_PRI_NXBAR_TILEOUT_CG_STATE_CG_EN__PROD 0x00000000 /* */
#define NV_NXBAR_TILEOUT_PRI_NXBAR_TILEOUT_CG_STALL_CG_DLY_CNT 13:8 /* */
#define NV_NXBAR_TILEOUT_PRI_NXBAR_TILEOUT_CG_STALL_CG_DLY_CNT_HWINIT 0x00000000 /* */
#define NV_NXBAR_TILEOUT_PRI_NXBAR_TILEOUT_CG_STALL_CG_DLY_CNT__PROD 0x00000000 /* */
#define NV_NXBAR_TILEOUT_PRI_NXBAR_TILEOUT_CG_STALL_CG_EN 14:14 /* RWEVF */
#define NV_NXBAR_TILEOUT_PRI_NXBAR_TILEOUT_CG_STALL_CG_EN_ENABLED 0x00000001 /* RW--V */
#define NV_NXBAR_TILEOUT_PRI_NXBAR_TILEOUT_CG_STALL_CG_EN_DISABLED 0x00000000 /* RWE-V */
#define NV_NXBAR_TILEOUT_PRI_NXBAR_TILEOUT_CG_STALL_CG_EN__PROD 0x00000000 /* RW--V */
#define NV_NXBAR_TILEOUT_PRI_NXBAR_TILEOUT_CG_QUIESCENT_CG_EN 15:15 /* */
#define NV_NXBAR_TILEOUT_PRI_NXBAR_TILEOUT_CG_QUIESCENT_CG_EN_ENABLED 0x00000001 /* */
#define NV_NXBAR_TILEOUT_PRI_NXBAR_TILEOUT_CG_QUIESCENT_CG_EN_DISABLED 0x00000000 /* */
#define NV_NXBAR_TILEOUT_PRI_NXBAR_TILEOUT_CG_QUIESCENT_CG_EN__PROD 0x00000000 /* */
#define NV_NXBAR_TILEOUT_PRI_NXBAR_TILEOUT_CG_WAKEUP_DLY_CNT 19:16 /* RWEVF */
#define NV_NXBAR_TILEOUT_PRI_NXBAR_TILEOUT_CG_WAKEUP_DLY_CNT_HWINIT 0x00000000 /* RWE-V */
#define NV_NXBAR_TILEOUT_PRI_NXBAR_TILEOUT_CG_WAKEUP_DLY_CNT__PROD 0x00000000 /* RW--V */
#define NV_NXBAR_TILEOUT_PRI_NXBAR_TILEOUT_CG_THROT_CLK_CNT 23:20 /* */
#define NV_NXBAR_TILEOUT_PRI_NXBAR_TILEOUT_CG_THROT_CLK_CNT_FULLSPEED 0x0000000f /* */
#define NV_NXBAR_TILEOUT_PRI_NXBAR_TILEOUT_CG_THROT_CLK_CNT__PROD 0x00000000 /* */
#define NV_NXBAR_TILEOUT_PRI_NXBAR_TILEOUT_CG_DI_DT_SKEW_VAL 27:24 /* */
#define NV_NXBAR_TILEOUT_PRI_NXBAR_TILEOUT_CG_DI_DT_SKEW_VAL_HWINIT 0x00000000 /* */
#define NV_NXBAR_TILEOUT_PRI_NXBAR_TILEOUT_CG_DI_DT_SKEW_VAL__PROD 0x00000000 /* */
#define NV_NXBAR_TILEOUT_PRI_NXBAR_TILEOUT_CG_THROT_CLK_EN 28:28 /* */
#define NV_NXBAR_TILEOUT_PRI_NXBAR_TILEOUT_CG_THROT_CLK_EN_ENABLED 0x00000001 /* */
#define NV_NXBAR_TILEOUT_PRI_NXBAR_TILEOUT_CG_THROT_CLK_EN_DISABLED 0x00000000 /* */
#define NV_NXBAR_TILEOUT_PRI_NXBAR_TILEOUT_CG_THROT_CLK_EN__PROD 0x00000000 /* */
#define NV_NXBAR_TILEOUT_PRI_NXBAR_TILEOUT_CG_THROT_CLK_SW_OVER 29:29 /* */
#define NV_NXBAR_TILEOUT_PRI_NXBAR_TILEOUT_CG_THROT_CLK_SW_OVER_EN 0x00000001 /* */
#define NV_NXBAR_TILEOUT_PRI_NXBAR_TILEOUT_CG_THROT_CLK_SW_OVER_DIS 0x00000000 /* */
#define NV_NXBAR_TILEOUT_PRI_NXBAR_TILEOUT_CG_THROT_CLK_SW_OVER__PROD 0x00000000 /* */
#define NV_NXBAR_TILEOUT_PRI_NXBAR_TILEOUT_CG_PAUSE_CG_EN 30:30 /* */
#define NV_NXBAR_TILEOUT_PRI_NXBAR_TILEOUT_CG_PAUSE_CG_EN_ENABLED 0x00000001 /* */
#define NV_NXBAR_TILEOUT_PRI_NXBAR_TILEOUT_CG_PAUSE_CG_EN_DISABLED 0x00000000 /* */
#define NV_NXBAR_TILEOUT_PRI_NXBAR_TILEOUT_CG_PAUSE_CG_EN__PROD 0x00000000 /* */
#define NV_NXBAR_TILEOUT_PRI_NXBAR_TILEOUT_CG_HALT_CG_EN 31:31 /* */
#define NV_NXBAR_TILEOUT_PRI_NXBAR_TILEOUT_CG_HALT_CG_EN_ENABLED 0x00000001 /* */
#define NV_NXBAR_TILEOUT_PRI_NXBAR_TILEOUT_CG_HALT_CG_EN_DISABLED 0x00000000 /* */
#define NV_NXBAR_TILEOUT_PRI_NXBAR_TILEOUT_CG_HALT_CG_EN__PROD 0x00000000 /* */
#define NV_NXBAR_TILEOUT_PRI_NXBAR_TILEOUT_CG1 0x0000004C /* RWE4R */
#define NV_NXBAR_TILEOUT_PRI_NXBAR_TILEOUT_CG1_MONITOR_CG_EN 0:0 /* RWEVF */
#define NV_NXBAR_TILEOUT_PRI_NXBAR_TILEOUT_CG1_MONITOR_CG_EN_ENABLED 0x00000001 /* RW--V */
#define NV_NXBAR_TILEOUT_PRI_NXBAR_TILEOUT_CG1_MONITOR_CG_EN_DISABLED 0x00000000 /* RWE-V */
#define NV_NXBAR_TILEOUT_PRI_NXBAR_TILEOUT_CG1_MONITOR_CG_EN__PROD 0x00000000 /* RW--V */
#endif // __ls10_dev_nxbar_tileout_ip_h__

44
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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the Software),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __ls10_dev_perf_h__
#define __ls10_dev_perf_h__
/* This file is autogenerated. Do not edit */
#define NV_PERF_PMM_PERDOMAIN_OFFSET 0x00000200 /* */
#define NV_PERF_PMM 0x000003FF:0x00000000 /* RW--D */
#define NV_PERF_PMMROUTER 0x000001FF:0x00000000 /* RW--D */
#define NV_PERF_PMMROUTER_CG2 0x00000040 /* RW-4R */
#define NV_PERF_PMMROUTER_CG2_SLCG 31:31 /* RWEVF */
#define NV_PERF_PMMROUTER_CG2_SLCG_ENABLED 0x00000000 /* RWE-V */
#define NV_PERF_PMMROUTER_CG2_SLCG_DISABLED 0x00000001 /* RW--V */
#define NV_PERF_PMMROUTER_CG1_SECURE 0x00000054 /* RW-4R */
#define NV_PERF_PMMROUTER_CG1_SECURE_FLCG_PERFMON 31:31 /* RWEUF */
#define NV_PERF_PMMROUTER_CG1_SECURE_FLCG_PERFMON_DISABLED 0x00000000 /* RWE-V */
#define NV_PERF_PMMROUTER_CG1_SECURE_FLCG_PERFMON__PROD 0x00000001 /* RW--V */
#define NV_PERF_PMMROUTER_CG1_SECURE_FLCG_PERFMON_ENABLED 0x00000001 /* RW--V */
#define NV_PERF_PMMROUTER_PERFMON_CG2_SECURE 0x00000058 /* RW-4R */
#define NV_PERF_PMMROUTER_PERFMON_CG2_SECURE_SLCG 31:31 /* RWEUF */
#define NV_PERF_PMMROUTER_PERFMON_CG2_SECURE_SLCG_ENABLED 0x00000000 /* RWE-V */
#define NV_PERF_PMMROUTER_PERFMON_CG2_SECURE_SLCG__PROD 0x00000000 /* RW--V */
#define NV_PERF_PMMROUTER_PERFMON_CG2_SECURE_SLCG_DISABLED 0x00000001 /* RW--V */
#endif // __ls10_dev_perf_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the Software),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __ls10_dev_pmgr_h__
#define __ls10_dev_pmgr_h__
/* This file is autogenerated. Do not edit */
#define NV_PMGR_ALL 0x003FFFFF:0x0000D000 /* RW--D */
#define NV_PMGR_I2C_PRIV_LEVEL_MASK(i) (0x0000D7A0 + (i)*0x4) /* RW-4A */
#define NV_PMGR_I2C_PRIV_LEVEL_MASK__SIZE_1 10 /* */
#define NV_PMGR_I2C_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
#define NV_PMGR_I2C_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWI-V */
#define NV_PMGR_I2C_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
#define NV_PMGR_I2C_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "opt_secure_pmgr_i2cx_wr_secure" /* */
#define NV_PMGR_I2C_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWI-V */
#define NV_PMGR_I2C_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLED_FUSE1 0x0000000E /* RW--V */
#define NV_PMGR_I2C_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE2 0x0000000C /* RW--V */
#define NV_PMGR_I2C_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLED_FUSE3 0x00000008 /* RW--V */
#define NV_PMGR_I2C_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
#define NV_PMGR_I2C_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
#define NV_PMGR_I2C_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
#define NV_PMGR_I2C_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
#define NV_PMGR_I2C_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
#define NV_PMGR_I2C_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
#define NV_PMGR_I2C_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
#define NV_PMGR_I2C_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
#define NV_PMGR_I2C_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
#define NV_PMGR_I2C_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
#define NV_PMGR_I2C_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
#define NV_PMGR_I2C_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
#define NV_PMGR_I2C_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
#define NV_PMGR_I2C_PRIV_LEVEL_MASK_SOURCE_ENABLE__FUSE_SIGNAL "opt_secure_pmgr_i2cx_wr_secure"/* */
#define NV_PMGR_I2C_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED_FUSE0 0x000FFFFF /* RWI-V */
#define NV_PMGR_I2C_PRIV_LEVEL_MASK_SOURCE_ENABLE_INIT_FUSE1 0x0008094F /* RW--V */
#define NV_PMGR_I2C_PRIV_LEVEL_MASK_SOURCE_ENABLE_INIT_FUSE2 0x0008094F /* RW--V */
#define NV_PMGR_I2C_PRIV_LEVEL_MASK_SOURCE_ENABLE_INIT_FUSE3 0x0008094F /* RW--V */
#define NV_PMGR_I2C_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4
#define NV_PMGR_I2C_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001
#define NV_PMGR_I2C_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000
#define NV_PMGR_GPIO_INPUT_CNTL_1 0x0000D740 /* RW-4R */
#define NV_PMGR_GPIO_INPUT_CNTL_1_PINNUM 7:0 /* RWIVF */
#define NV_PMGR_GPIO_INPUT_CNTL_1_PINNUM_INIT 0x00000001 /* RWI-V */
#define NV_PMGR_GPIO_INPUT_CNTL_1_INV 8:8 /* RWIVF */
#define NV_PMGR_GPIO_INPUT_CNTL_1_INV_NO 0x00000000 /* RWI-V */
#define NV_PMGR_GPIO_INPUT_CNTL_1_INV_YES 0x00000001 /* RW--V */
#define NV_PMGR_GPIO_INPUT_CNTL_1_READ 9:9 /* R--VF */
#define NV_PMGR_GPIO_INPUT_CNTL_1_READ_0 0x00000000 /* R---V */
#define NV_PMGR_GPIO_INPUT_CNTL_1_READ_1 0x00000001 /* R---V */
#define NV_PMGR_GPIO_INPUT_CNTL_1_BYPASS_FILTER 10:10 /* RWIVF */
#define NV_PMGR_GPIO_INPUT_CNTL_1_BYPASS_FILTER_INIT 0x00000000 /* RWI-V */
#define NV_PMGR_GPIO_INPUT_CNTL_1_BYPASS_FILTER_NO 0x00000000 /* RW--V */
#define NV_PMGR_GPIO_INPUT_CNTL_1_BYPASS_FILTER_YES 0x00000001 /* RW--V */
#define NV_PMGR_GPIO_INPUT_CNTL(i) 0x0000D740 + ((i)-1) * (0x0000D744 - 0x0000D740) /* */
#define NV_PMGR_GPIO_INPUT_CNTL__SIZE_1 25 /* */
#define NV_PMGR_GPIO_INPUT_CNTL_PINNUM 7:0 /* */
#define NV_PMGR_GPIO_INPUT_CNTL_PINNUM_UNUSED 0x000000FF /* */
#define NV_PMGR_GPIO_INPUT_CNTL_INV 8:8 /* */
#define NV_PMGR_GPIO_INPUT_CNTL_INV_NO 0x00000000 /* */
#define NV_PMGR_GPIO_INPUT_CNTL_INV_YES 0x00000001 /* */
#define NV_PMGR_GPIO_INPUT_CNTL_READ 9:9 /* */
#define NV_PMGR_GPIO_INPUT_CNTL_READ_0 0x00000000 /* */
#define NV_PMGR_GPIO_INPUT_CNTL_READ_1 0x00000001 /* */
#define NV_PMGR_GPIO_INPUT_CNTL_BYPASS_FILTER 10:10 /* */
#define NV_PMGR_GPIO_INPUT_CNTL_BYPASS_FILTER_NO 0x00000000 /* */
#define NV_PMGR_GPIO_INPUT_CNTL_BYPASS_FILTER_YES 0x00000001 /* */
#endif // __ls10_dev_pmgr_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the Software),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __ls10_dev_pri_hub_prt_ip_h__
#define __ls10_dev_pri_hub_prt_ip_h__
/* This file is autogenerated. Do not edit */
#define NV_PPRIV_PRT 0x000007ff:0x00000000 /* RW--D */
#define NV_PPRIV_PRT_PRIV_ERROR_ADR 0x00000020 /* R--4R */
#define NV_PPRIV_PRT_PRIV_ERROR_WRDAT 0x00000024 /* R--4R */
#define NV_PPRIV_PRT_PRIV_ERROR_INFO 0x00000028 /* R--4R */
#define NV_PPRIV_PRT_PRIV_ERROR_CODE 0x0000002c /* R--4R */
#define NV_PPRIV_PRT_CG1 0x00000150 /* RW-4R */
#define NV_PPRIV_PRT_CG1_SLCG 10:0 /* */
#define NV_PPRIV_PRT_CG1_SLCG_ENABLED 0x000 /* */
#define NV_PPRIV_PRT_CG1_SLCG_DISABLED 0x7ff /* */
#define NV_PPRIV_PRT_CG1_SLCG__PROD 0x000 /* */
#define NV_PPRIV_PRT_CG1_SLCG_SLOWCLK 0:0 /* RWBVF */
#define NV_PPRIV_PRT_CG1_SLCG_SLOWCLK_ENABLED 0x0 /* RW--V */
#define NV_PPRIV_PRT_CG1_SLCG_SLOWCLK_DISABLED 0x1 /* RWB-V */
#define NV_PPRIV_PRT_CG1_SLCG_SLOWCLK__PROD 0x0 /* RW--V */
#define NV_PPRIV_PRT_CG1_SLCG_PRIV_CONFIG_REGS 1:1 /* RWBVF */
#define NV_PPRIV_PRT_CG1_SLCG_PRIV_CONFIG_REGS_ENABLED 0x0 /* RW--V */
#define NV_PPRIV_PRT_CG1_SLCG_PRIV_CONFIG_REGS_DISABLED 0x1 /* RWB-V */
#define NV_PPRIV_PRT_CG1_SLCG_PRIV_CONFIG_REGS__PROD 0x0 /* RW--V */
#define NV_PPRIV_PRT_CG1_SLCG_PRIV_FUNNEL_DECODER 2:2 /* RWBVF */
#define NV_PPRIV_PRT_CG1_SLCG_PRIV_FUNNEL_DECODER_ENABLED 0x0 /* RW--V */
#define NV_PPRIV_PRT_CG1_SLCG_PRIV_FUNNEL_DECODER_DISABLED 0x1 /* RWB-V */
#define NV_PPRIV_PRT_CG1_SLCG_PRIV_FUNNEL_DECODER__PROD 0x0 /* RW--V */
#define NV_PPRIV_PRT_CG1_SLCG_PRIV_FUNNEL_ARB 3:3 /* RWBVF */
#define NV_PPRIV_PRT_CG1_SLCG_PRIV_FUNNEL_ARB_ENABLED 0x0 /* RW--V */
#define NV_PPRIV_PRT_CG1_SLCG_PRIV_FUNNEL_ARB_DISABLED 0x1 /* RWB-V */
#define NV_PPRIV_PRT_CG1_SLCG_PRIV_FUNNEL_ARB__PROD 0x0 /* RW--V */
#define NV_PPRIV_PRT_CG1_SLCG_PRIV_HISTORY_BUFFER 4:4 /* RWBVF */
#define NV_PPRIV_PRT_CG1_SLCG_PRIV_HISTORY_BUFFER_ENABLED 0x0 /* RW--V */
#define NV_PPRIV_PRT_CG1_SLCG_PRIV_HISTORY_BUFFER_DISABLED 0x1 /* RWB-V */
#define NV_PPRIV_PRT_CG1_SLCG_PRIV_HISTORY_BUFFER__PROD 0x0 /* RW--V */
#define NV_PPRIV_PRT_CG1_SLCG_PRIV_MASTER 5:5 /* RWBVF */
#define NV_PPRIV_PRT_CG1_SLCG_PRIV_MASTER_ENABLED 0x0 /* RW--V */
#define NV_PPRIV_PRT_CG1_SLCG_PRIV_MASTER_DISABLED 0x1 /* RWB-V */
#define NV_PPRIV_PRT_CG1_SLCG_PRIV_MASTER__PROD 0x0 /* RW--V */
#define NV_PPRIV_PRT_CG1_SLCG_PRIV_SLAVE 6:6 /* RWBVF */
#define NV_PPRIV_PRT_CG1_SLCG_PRIV_SLAVE_ENABLED 0x0 /* RW--V */
#define NV_PPRIV_PRT_CG1_SLCG_PRIV_SLAVE_DISABLED 0x1 /* RWB-V */
#define NV_PPRIV_PRT_CG1_SLCG_PRIV_SLAVE__PROD 0x0 /* RW--V */
#define NV_PPRIV_PRT_CG1_SLCG_LOC_PRIV 9:9 /* RWBVF */
#define NV_PPRIV_PRT_CG1_SLCG_LOC_PRIV_ENABLED 0x0 /* RW--V */
#define NV_PPRIV_PRT_CG1_SLCG_LOC_PRIV_DISABLED 0x1 /* RWB-V */
#define NV_PPRIV_PRT_CG1_SLCG_LOC_PRIV__PROD 0x0 /* RW--V */
#define NV_PPRIV_PRT_CG1_SLCG_PM 10:10 /* RWBVF */
#define NV_PPRIV_PRT_CG1_SLCG_PM_ENABLED 0x0 /* RW--V */
#define NV_PPRIV_PRT_CG1_SLCG_PM_DISABLED 0x1 /* RWB-V */
#define NV_PPRIV_PRT_CG1_SLCG_PM__PROD 0x0 /* RW--V */
#endif // __ls10_dev_pri_hub_prt_ip_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the Software),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __ls10_dev_pri_hub_sys_ip_h__
#define __ls10_dev_pri_hub_sys_ip_h__
/* This file is autogenerated. Do not edit */
#define NV_PPRIV_SYS 0x000007ff:0x00000000 /* RW--D */
#define NV_PPRIV_SYS_PRIV_ERROR_ADR 0x00000020 /* R--4R */
#define NV_PPRIV_SYS_PRIV_ERROR_WRDAT 0x00000024 /* R--4R */
#define NV_PPRIV_SYS_PRIV_ERROR_INFO 0x00000028 /* R--4R */
#define NV_PPRIV_SYS_PRIV_ERROR_CODE 0x0000002c /* R--4R */
#define NV_PPRIV_SYS_PRI_RING_INIT 0x00000174 /* RW-4R */
#define NV_PPRIV_SYS_PRI_RING_INIT_STATUS 2:0 /* R--VF */
#define NV_PPRIV_SYS_PRI_RING_INIT_STATUS_DEAD 0x0 /* R---V */
#define NV_PPRIV_SYS_PRI_RING_INIT_STATUS_CMD_RDY 0x1 /* R---V */
#define NV_PPRIV_SYS_PRI_RING_INIT_STATUS_ALIVE_IN_SAFE_MODE 0x2 /* R---V */
#define NV_PPRIV_SYS_PRI_RING_INIT_STATUS_ERROR 0x3 /* R---V */
#define NV_PPRIV_SYS_PRI_RING_INIT_STATUS_ALIVE 0x4 /* R---V */
#define NV_PPRIV_SYS_PRI_RING_INIT_CMD 9:8 /* RWBVF */
#define NV_PPRIV_SYS_PRI_RING_INIT_CMD_NONE 0x0 /* RWB-V */
#define NV_PPRIV_SYS_PRI_RING_INIT_CMD_ENUMERATE_AND_START 0x1 /* RW--T */
#define NV_PPRIV_SYS_PRI_RING_INIT_CMD_SAFE_START 0x2 /* RW--T */
#define NV_PPRIV_SYS_PRI_RING_INIT_CMD_TOGGLE_RESET 0x3 /* RW--T */
#define NV_PPRIV_SYS_CG1 0x00000150 /* RW-4R */
#define NV_PPRIV_SYS_CG1_SLCG 10:0 /* */
#define NV_PPRIV_SYS_CG1_SLCG_ENABLED 0x000 /* */
#define NV_PPRIV_SYS_CG1_SLCG_DISABLED 0x7ff /* */
#define NV_PPRIV_SYS_CG1_SLCG__PROD 0x000 /* */
#define NV_PPRIV_SYS_CG1_SLCG_SLOWCLK 0:0 /* RWBVF */
#define NV_PPRIV_SYS_CG1_SLCG_SLOWCLK_ENABLED 0x0 /* RW--V */
#define NV_PPRIV_SYS_CG1_SLCG_SLOWCLK_DISABLED 0x1 /* RWB-V */
#define NV_PPRIV_SYS_CG1_SLCG_SLOWCLK__PROD 0x0 /* RW--V */
#define NV_PPRIV_SYS_CG1_SLCG_PRIV_CONFIG_REGS 1:1 /* RWBVF */
#define NV_PPRIV_SYS_CG1_SLCG_PRIV_CONFIG_REGS_ENABLED 0x0 /* RW--V */
#define NV_PPRIV_SYS_CG1_SLCG_PRIV_CONFIG_REGS_DISABLED 0x1 /* RWB-V */
#define NV_PPRIV_SYS_CG1_SLCG_PRIV_CONFIG_REGS__PROD 0x0 /* RW--V */
#define NV_PPRIV_SYS_CG1_SLCG_PRIV_FUNNEL_DECODER 2:2 /* RWBVF */
#define NV_PPRIV_SYS_CG1_SLCG_PRIV_FUNNEL_DECODER_ENABLED 0x0 /* RW--V */
#define NV_PPRIV_SYS_CG1_SLCG_PRIV_FUNNEL_DECODER_DISABLED 0x1 /* RWB-V */
#define NV_PPRIV_SYS_CG1_SLCG_PRIV_FUNNEL_DECODER__PROD 0x0 /* RW--V */
#define NV_PPRIV_SYS_CG1_SLCG_PRIV_FUNNEL_ARB 3:3 /* RWBVF */
#define NV_PPRIV_SYS_CG1_SLCG_PRIV_FUNNEL_ARB_ENABLED 0x0 /* RW--V */
#define NV_PPRIV_SYS_CG1_SLCG_PRIV_FUNNEL_ARB_DISABLED 0x1 /* RWB-V */
#define NV_PPRIV_SYS_CG1_SLCG_PRIV_FUNNEL_ARB__PROD 0x0 /* RW--V */
#define NV_PPRIV_SYS_CG1_SLCG_PRIV_HISTORY_BUFFER 4:4 /* RWBVF */
#define NV_PPRIV_SYS_CG1_SLCG_PRIV_HISTORY_BUFFER_ENABLED 0x0 /* RW--V */
#define NV_PPRIV_SYS_CG1_SLCG_PRIV_HISTORY_BUFFER_DISABLED 0x1 /* RWB-V */
#define NV_PPRIV_SYS_CG1_SLCG_PRIV_HISTORY_BUFFER__PROD 0x0 /* RW--V */
#define NV_PPRIV_SYS_CG1_SLCG_PRIV_MASTER 5:5 /* RWBVF */
#define NV_PPRIV_SYS_CG1_SLCG_PRIV_MASTER_ENABLED 0x0 /* RW--V */
#define NV_PPRIV_SYS_CG1_SLCG_PRIV_MASTER_DISABLED 0x1 /* RWB-V */
#define NV_PPRIV_SYS_CG1_SLCG_PRIV_MASTER__PROD 0x0 /* RW--V */
#define NV_PPRIV_SYS_CG1_SLCG_PRIV_SLAVE 6:6 /* RWBVF */
#define NV_PPRIV_SYS_CG1_SLCG_PRIV_SLAVE_ENABLED 0x0 /* RW--V */
#define NV_PPRIV_SYS_CG1_SLCG_PRIV_SLAVE_DISABLED 0x1 /* RWB-V */
#define NV_PPRIV_SYS_CG1_SLCG_PRIV_SLAVE__PROD 0x0 /* RW--V */
#define NV_PPRIV_SYS_CG1_SLCG_LOC_PRIV 9:9 /* RWBVF */
#define NV_PPRIV_SYS_CG1_SLCG_LOC_PRIV_ENABLED 0x0 /* RW--V */
#define NV_PPRIV_SYS_CG1_SLCG_LOC_PRIV_DISABLED 0x1 /* RWB-V */
#define NV_PPRIV_SYS_CG1_SLCG_LOC_PRIV__PROD 0x0 /* RW--V */
#define NV_PPRIV_SYS_CG1_SLCG_PM 10:10 /* RWBVF */
#define NV_PPRIV_SYS_CG1_SLCG_PM_ENABLED 0x0 /* RW--V */
#define NV_PPRIV_SYS_CG1_SLCG_PM_DISABLED 0x1 /* RWB-V */
#define NV_PPRIV_SYS_CG1_SLCG_PM__PROD 0x0 /* RW--V */
#endif // __ls10_dev_pri_hub_sys_ip_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the Software),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __ls10_dev_pri_hub_sysb_ip_h__
#define __ls10_dev_pri_hub_sysb_ip_h__
/* This file is autogenerated. Do not edit */
#define NV_PPRIV_SYSB 0x000007ff:0x00000000 /* RW--D */
#define NV_PPRIV_SYSB_PRIV_ERROR_ADR 0x00000020 /* R--4R */
#define NV_PPRIV_SYSB_PRIV_ERROR_WRDAT 0x00000024 /* R--4R */
#define NV_PPRIV_SYSB_PRIV_ERROR_INFO 0x00000028 /* R--4R */
#define NV_PPRIV_SYSB_PRIV_ERROR_CODE 0x0000002c /* R--4R */
#define NV_PPRIV_SYSB_CG1 0x00000150 /* RW-4R */
#define NV_PPRIV_SYSB_CG1_SLCG 10:0 /* */
#define NV_PPRIV_SYSB_CG1_SLCG_ENABLED 0x000 /* */
#define NV_PPRIV_SYSB_CG1_SLCG_DISABLED 0x7ff /* */
#define NV_PPRIV_SYSB_CG1_SLCG__PROD 0x000 /* */
#define NV_PPRIV_SYSB_CG1_SLCG_SLOWCLK 0:0 /* RWBVF */
#define NV_PPRIV_SYSB_CG1_SLCG_SLOWCLK_ENABLED 0x0 /* RW--V */
#define NV_PPRIV_SYSB_CG1_SLCG_SLOWCLK_DISABLED 0x1 /* RWB-V */
#define NV_PPRIV_SYSB_CG1_SLCG_SLOWCLK__PROD 0x0 /* RW--V */
#define NV_PPRIV_SYSB_CG1_SLCG_PRIV_CONFIG_REGS 1:1 /* RWBVF */
#define NV_PPRIV_SYSB_CG1_SLCG_PRIV_CONFIG_REGS_ENABLED 0x0 /* RW--V */
#define NV_PPRIV_SYSB_CG1_SLCG_PRIV_CONFIG_REGS_DISABLED 0x1 /* RWB-V */
#define NV_PPRIV_SYSB_CG1_SLCG_PRIV_CONFIG_REGS__PROD 0x0 /* RW--V */
#define NV_PPRIV_SYSB_CG1_SLCG_PRIV_FUNNEL_DECODER 2:2 /* RWBVF */
#define NV_PPRIV_SYSB_CG1_SLCG_PRIV_FUNNEL_DECODER_ENABLED 0x0 /* RW--V */
#define NV_PPRIV_SYSB_CG1_SLCG_PRIV_FUNNEL_DECODER_DISABLED 0x1 /* RWB-V */
#define NV_PPRIV_SYSB_CG1_SLCG_PRIV_FUNNEL_DECODER__PROD 0x0 /* RW--V */
#define NV_PPRIV_SYSB_CG1_SLCG_PRIV_FUNNEL_ARB 3:3 /* RWBVF */
#define NV_PPRIV_SYSB_CG1_SLCG_PRIV_FUNNEL_ARB_ENABLED 0x0 /* RW--V */
#define NV_PPRIV_SYSB_CG1_SLCG_PRIV_FUNNEL_ARB_DISABLED 0x1 /* RWB-V */
#define NV_PPRIV_SYSB_CG1_SLCG_PRIV_FUNNEL_ARB__PROD 0x0 /* RW--V */
#define NV_PPRIV_SYSB_CG1_SLCG_PRIV_HISTORY_BUFFER 4:4 /* RWBVF */
#define NV_PPRIV_SYSB_CG1_SLCG_PRIV_HISTORY_BUFFER_ENABLED 0x0 /* RW--V */
#define NV_PPRIV_SYSB_CG1_SLCG_PRIV_HISTORY_BUFFER_DISABLED 0x1 /* RWB-V */
#define NV_PPRIV_SYSB_CG1_SLCG_PRIV_HISTORY_BUFFER__PROD 0x0 /* RW--V */
#define NV_PPRIV_SYSB_CG1_SLCG_PRIV_MASTER 5:5 /* RWBVF */
#define NV_PPRIV_SYSB_CG1_SLCG_PRIV_MASTER_ENABLED 0x0 /* RW--V */
#define NV_PPRIV_SYSB_CG1_SLCG_PRIV_MASTER_DISABLED 0x1 /* RWB-V */
#define NV_PPRIV_SYSB_CG1_SLCG_PRIV_MASTER__PROD 0x0 /* RW--V */
#define NV_PPRIV_SYSB_CG1_SLCG_PRIV_SLAVE 6:6 /* RWBVF */
#define NV_PPRIV_SYSB_CG1_SLCG_PRIV_SLAVE_ENABLED 0x0 /* RW--V */
#define NV_PPRIV_SYSB_CG1_SLCG_PRIV_SLAVE_DISABLED 0x1 /* RWB-V */
#define NV_PPRIV_SYSB_CG1_SLCG_PRIV_SLAVE__PROD 0x0 /* RW--V */
#define NV_PPRIV_SYSB_CG1_SLCG_LOC_PRIV 9:9 /* RWBVF */
#define NV_PPRIV_SYSB_CG1_SLCG_LOC_PRIV_ENABLED 0x0 /* RW--V */
#define NV_PPRIV_SYSB_CG1_SLCG_LOC_PRIV_DISABLED 0x1 /* RWB-V */
#define NV_PPRIV_SYSB_CG1_SLCG_LOC_PRIV__PROD 0x0 /* RW--V */
#define NV_PPRIV_SYSB_CG1_SLCG_PM 10:10 /* RWBVF */
#define NV_PPRIV_SYSB_CG1_SLCG_PM_ENABLED 0x0 /* RW--V */
#define NV_PPRIV_SYSB_CG1_SLCG_PM_DISABLED 0x1 /* RWB-V */
#define NV_PPRIV_SYSB_CG1_SLCG_PM__PROD 0x0 /* RW--V */
#endif // __ls10_dev_pri_hub_sysb_ip_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the Software),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __ls10_dev_pri_masterstation_ip_h__
#define __ls10_dev_pri_masterstation_ip_h__
/* This file is autogenerated. Do not edit */
#define NV_PPRIV_MASTER_RING_COMMAND 0x0000004c /* RW-4R */
#define NV_PPRIV_MASTER_RING_COMMAND_CMD 5:0 /* RWBVF */
#define NV_PPRIV_MASTER_RING_COMMAND_CMD_START_RING_RESET_VAL_0 0x01 /* RW--T */
#define NV_PPRIV_MASTER_RING_COMMAND_CMD_NO_CMD_RESET_VAL_1 0x00 /* RWB-V */
#define NV_PPRIV_MASTER_RING_COMMAND_CMD_NO_CMD 0x00 /* RW--V */
#define NV_PPRIV_MASTER_RING_COMMAND_CMD_START_RING 0x01 /* RW--T */
#define NV_PPRIV_MASTER_RING_COMMAND_CMD_ACK_INTERRUPT 0x02 /* RW--T */
#define NV_PPRIV_MASTER_RING_COMMAND_CMD_ENUMERATE_STATIONS 0x03 /* RW--T */
#define NV_PPRIV_MASTER_RING_COMMAND_CMD_ENUMERATE_AND_START_RING 0x04 /* RW--T */
#define NV_PPRIV_MASTER_RING_COMMAND_CMD_NO_TAG_ENUMERATE_AND_START_RING 0x05 /* RW--T */
#define NV_PPRIV_MASTER_RING_COMMAND_CMD_ENUMERATE_STATIONS_BC_GRP 9:6 /* RWBVF */
#define NV_PPRIV_MASTER_RING_COMMAND_CMD_ENUMERATE_STATIONS_BC_GRP_ALL 0x0 /* RWB-V */
#define NV_PPRIV_MASTER_RING_COMMAND_CMD_ENUMERATE_STATIONS_BC_GRP_GPC 0x1 /* RW--V */
#define NV_PPRIV_MASTER_RING_COMMAND_CMD_ENUMERATE_STATIONS_BC_GRP_FBP 0x2 /* RW--V */
#define NV_PPRIV_MASTER_RING_COMMAND_CMD_ENUMERATE_STATIONS_BC_GRP_SYS 0x3 /* RW--V */
#define NV_PPRIV_MASTER_RING_COMMAND_CMD_ENUMERATE_STATIONS_BC_GRP_L2 0x4 /* RW--V */
#define NV_PPRIV_MASTER_RING_COMMAND_CMD_ENUMERATE_STATIONS_BC_GRP_SYSB 0x5 /* RW--V */
#define NV_PPRIV_MASTER_RING_COMMAND_CMD_ENUMERATE_STATIONS_BC_GRP_NO_TAG_ALL 0x8 /* RW--V */
#define NV_PPRIV_MASTER_RING_COMMAND_CMD_ENUMERATE_STATIONS_BC_GRP_NO_TAG_GPC 0x9 /* RW--V */
#define NV_PPRIV_MASTER_RING_COMMAND_CMD_ENUMERATE_STATIONS_BC_GRP_NO_TAG_FBP 0xa /* RW--V */
#define NV_PPRIV_MASTER_RING_COMMAND_CMD_ENUMERATE_STATIONS_BC_GRP_NO_TAG_SYS 0xb /* RW--V */
#define NV_PPRIV_MASTER_RING_COMMAND_CMD_ENUMERATE_STATIONS_BC_GRP_NO_TAG_L2 0xc /* RW--V */
#define NV_PPRIV_MASTER_RING_COMMAND_CMD_ENUMERATE_STATIONS_BC_GRP_NO_TAG_SYSB 0xd /* RW--V */
#define NV_PPRIV_MASTER_RING_START_RESULTS 0x00000050 /* R--4R */
#define NV_PPRIV_MASTER_RING_START_RESULTS_CONNECTIVITY 0:0 /* R-BVF */
#define NV_PPRIV_MASTER_RING_START_RESULTS_CONNECTIVITY_PASS 0x1 /* R---V */
#define NV_PPRIV_MASTER_RING_START_RESULTS_CONNECTIVITY_FAIL 0x0 /* R-B-V */
#define NV_PPRIV_MASTER_RING_INTERRUPT_STATUS0 0x00000058 /* R--4R */
#define NV_PPRIV_MASTER_RING_INTERRUPT_STATUS0_GBL_WRITE_ERROR_FBP 31:16 /* R-BVF */
#define NV_PPRIV_MASTER_RING_INTERRUPT_STATUS0_GBL_WRITE_ERROR_FBP_V 0x0000 /* R-B-V */
#define NV_PPRIV_MASTER_RING_INTERRUPT_STATUS0_GBL_WRITE_ERROR_SYS 8:8 /* R-BVF */
#define NV_PPRIV_MASTER_RING_INTERRUPT_STATUS0_GBL_WRITE_ERROR_SYS_V 0x0 /* R-B-V */
#define NV_PPRIV_MASTER_RING_INTERRUPT_STATUS0_GBL_WRITE_ERROR_SYSB 9:9 /* R-BVF */
#define NV_PPRIV_MASTER_RING_INTERRUPT_STATUS0_GBL_WRITE_ERROR_SYSB_V 0x0 /* R-B-V */
#define NV_PPRIV_MASTER_RING_INTERRUPT_STATUS0_RING_START_CONN_FAULT 0:0 /* R-BVF */
#define NV_PPRIV_MASTER_RING_INTERRUPT_STATUS0_RING_START_CONN_FAULT_V 0x0 /* R-B-V */
#define NV_PPRIV_MASTER_RING_INTERRUPT_STATUS0_DISCONNECT_FAULT 1:1 /* R-BVF */
#define NV_PPRIV_MASTER_RING_INTERRUPT_STATUS0_DISCONNECT_FAULT_V 0x0 /* R-B-V */
#define NV_PPRIV_MASTER_RING_INTERRUPT_STATUS0_OVERFLOW_FAULT 2:2 /* R-BVF */
#define NV_PPRIV_MASTER_RING_INTERRUPT_STATUS0_OVERFLOW_FAULT_V 0x0 /* R-B-V */
#define NV_PPRIV_MASTER_RING_INTERRUPT_STATUS0_RING_ENUMERATION_FAULT 3:3 /* R-BVF */
#define NV_PPRIV_MASTER_RING_INTERRUPT_STATUS0_RING_ENUMERATION_FAULT_V 0x0 /* R-B-V */
#define NV_PPRIV_MASTER_RING_INTERRUPT_STATUS0_GPC_RS_MAP_CONFIG_FAULT 4:4 /* R-BVF */
#define NV_PPRIV_MASTER_RING_INTERRUPT_STATUS0_GPC_RS_MAP_CONFIG_FAULT_V 0x0 /* R-B-V */
#define NV_PPRIV_MASTER_RING_INTERRUPT_STATUS0_DEBUG_INTR_FAULT 5:5 /* R-BVF */
#define NV_PPRIV_MASTER_RING_INTERRUPT_STATUS0_DEBUG_INTR_FAULT_V 0x0 /* R-B-V */
#define NV_PPRIV_MASTER_RING_INTERRUPT_STATUS1 0x0000005c /* R--4R */
#define NV_PPRIV_MASTER_RING_INTERRUPT_STATUS1_GBL_WRITE_ERROR_GPC 31:0 /* R-BVF */
#define NV_PPRIV_MASTER_RING_INTERRUPT_STATUS1_GBL_WRITE_ERROR_GPC_V 0x00000000 /* R-B-V */
#define NV_PPRIV_MASTER 0x000003ff:0x00000000 /* RW--D */
#define NV_PPRIV_MASTER_CG1 0x000000a8 /* RW-4R */
#define NV_PPRIV_MASTER_CG1_SLCG 0:0 /* RWBVF */
#define NV_PPRIV_MASTER_CG1_SLCG__PROD 0x0 /* RW--V */
#define NV_PPRIV_MASTER_CG1_SLCG_ENABLED 0x0 /* RW--V */
#define NV_PPRIV_MASTER_CG1_SLCG_DISABLED 0x1 /* RWB-V */
#endif // __ls10_dev_pri_masterstation_ip_h__

33
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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the Software),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __ls10_dev_pri_ringstation_prt_ip_h__
#define __ls10_dev_pri_ringstation_prt_ip_h__
/* This file is autogenerated. Do not edit */
#define NV_PPRIV_RS_CTRL_PRT 0x000000ff:0x00000000 /* RW--D */
#define NV_PPRIV_RS_CTRL_PRT_CG1 0x00000048 /* RW-4R */
#define NV_PPRIV_RS_CTRL_PRT_CG1_SLCG 1:0 /* RWBVF */
#define NV_PPRIV_RS_CTRL_PRT_CG1_SLCG_ENABLED 0x0 /* RW--V */
#define NV_PPRIV_RS_CTRL_PRT_CG1_SLCG_DISABLED 0x3 /* RWB-V */
#define NV_PPRIV_RS_CTRL_PRT_CG1_SLCG__PROD 0x0 /* RW--V */
#endif // __ls10_dev_pri_ringstation_prt_ip_h__

33
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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the Software),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __ls10_dev_pri_ringstation_sys_ip_h__
#define __ls10_dev_pri_ringstation_sys_ip_h__
/* This file is autogenerated. Do not edit */
#define NV_PPRIV_RS_CTRL_SYS 0x000000ff:0x00000000 /* RW--D */
#define NV_PPRIV_RS_CTRL_SYS_CG1 0x00000048 /* RW-4R */
#define NV_PPRIV_RS_CTRL_SYS_CG1_SLCG 1:0 /* RWBVF */
#define NV_PPRIV_RS_CTRL_SYS_CG1_SLCG_ENABLED 0x0 /* RW--V */
#define NV_PPRIV_RS_CTRL_SYS_CG1_SLCG_DISABLED 0x3 /* RWB-V */
#define NV_PPRIV_RS_CTRL_SYS_CG1_SLCG__PROD 0x0 /* RW--V */
#endif // __ls10_dev_pri_ringstation_sys_ip_h__

33
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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the Software),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __ls10_dev_pri_ringstation_sysb_ip_h__
#define __ls10_dev_pri_ringstation_sysb_ip_h__
/* This file is autogenerated. Do not edit */
#define NV_PPRIV_RS_CTRL_SYSB 0x000000ff:0x00000000 /* RW--D */
#define NV_PPRIV_RS_CTRL_SYSB_CG1 0x00000048 /* RW-4R */
#define NV_PPRIV_RS_CTRL_SYSB_CG1_SLCG 1:0 /* RWBVF */
#define NV_PPRIV_RS_CTRL_SYSB_CG1_SLCG_ENABLED 0x0 /* RW--V */
#define NV_PPRIV_RS_CTRL_SYSB_CG1_SLCG_DISABLED 0x3 /* RWB-V */
#define NV_PPRIV_RS_CTRL_SYSB_CG1_SLCG__PROD 0x0 /* RW--V */
#endif // __ls10_dev_pri_ringstation_sysb_ip_h__

283
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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the Software),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __ls10_dev_reductiontstate_ip_h__
#define __ls10_dev_reductiontstate_ip_h__
/* This file is autogenerated. Do not edit */
#define NV_REDUCTIONTSTATE 0x00002fff:0x00002800 /* RW--D */
#define NV_REDUCTIONTSTATE_ERR_STATUS_0 0x00002c00 /* RW-4R */
#define NV_REDUCTIONTSTATE_ERR_STATUS_0_TAGPOOL_ECC_LIMIT_ERR 2:2 /* RWDVF */
#define NV_REDUCTIONTSTATE_ERR_STATUS_0_TAGPOOL_ECC_LIMIT_ERR__ONWRITE "oneToClear" /* */
#define NV_REDUCTIONTSTATE_ERR_STATUS_0_TAGPOOL_ECC_LIMIT_ERR_NONE 0x00000000 /* RWD-V */
#define NV_REDUCTIONTSTATE_ERR_STATUS_0_TAGPOOL_ECC_LIMIT_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_REDUCTIONTSTATE_ERR_STATUS_0_TAGPOOL_ECC_DBE_ERR 3:3 /* RWDVF */
#define NV_REDUCTIONTSTATE_ERR_STATUS_0_TAGPOOL_ECC_DBE_ERR__ONWRITE "oneToClear" /* */
#define NV_REDUCTIONTSTATE_ERR_STATUS_0_TAGPOOL_ECC_DBE_ERR_NONE 0x00000000 /* RWD-V */
#define NV_REDUCTIONTSTATE_ERR_STATUS_0_TAGPOOL_ECC_DBE_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_REDUCTIONTSTATE_ERR_STATUS_0_CRUMBSTORE_BUF_OVERWRITE_ERR 16:16 /* RWDVF */
#define NV_REDUCTIONTSTATE_ERR_STATUS_0_CRUMBSTORE_BUF_OVERWRITE_ERR__ONWRITE "oneToClear" /* */
#define NV_REDUCTIONTSTATE_ERR_STATUS_0_CRUMBSTORE_BUF_OVERWRITE_ERR_NONE 0x00000000 /* RWD-V */
#define NV_REDUCTIONTSTATE_ERR_STATUS_0_CRUMBSTORE_BUF_OVERWRITE_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_REDUCTIONTSTATE_ERR_STATUS_0_CRUMBSTORE_ECC_LIMIT_ERR 18:18 /* RWDVF */
#define NV_REDUCTIONTSTATE_ERR_STATUS_0_CRUMBSTORE_ECC_LIMIT_ERR__ONWRITE "oneToClear" /* */
#define NV_REDUCTIONTSTATE_ERR_STATUS_0_CRUMBSTORE_ECC_LIMIT_ERR_NONE 0x00000000 /* RWD-V */
#define NV_REDUCTIONTSTATE_ERR_STATUS_0_CRUMBSTORE_ECC_LIMIT_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_REDUCTIONTSTATE_ERR_STATUS_0_CRUMBSTORE_ECC_DBE_ERR 19:19 /* RWDVF */
#define NV_REDUCTIONTSTATE_ERR_STATUS_0_CRUMBSTORE_ECC_DBE_ERR__ONWRITE "oneToClear" /* */
#define NV_REDUCTIONTSTATE_ERR_STATUS_0_CRUMBSTORE_ECC_DBE_ERR_NONE 0x00000000 /* RWD-V */
#define NV_REDUCTIONTSTATE_ERR_STATUS_0_CRUMBSTORE_ECC_DBE_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_REDUCTIONTSTATE_ERR_STATUS_0_CRUMBSTORE_RTO_ERR 20:20 /* RWDVF */
#define NV_REDUCTIONTSTATE_ERR_STATUS_0_CRUMBSTORE_RTO_ERR__ONWRITE "oneToClear" /* */
#define NV_REDUCTIONTSTATE_ERR_STATUS_0_CRUMBSTORE_RTO_ERR_NONE 0x00000000 /* RWD-V */
#define NV_REDUCTIONTSTATE_ERR_STATUS_0_CRUMBSTORE_RTO_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_REDUCTIONTSTATE_ERR_LOG_EN_0 0x00002c04 /* RW-4R */
#define NV_REDUCTIONTSTATE_ERR_LOG_EN_0_TAGPOOL_ECC_LIMIT_ERR 2:2 /* RWEVF */
#define NV_REDUCTIONTSTATE_ERR_LOG_EN_0_TAGPOOL_ECC_LIMIT_ERR__PROD 0x00000001 /* RW--V */
#define NV_REDUCTIONTSTATE_ERR_LOG_EN_0_TAGPOOL_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_REDUCTIONTSTATE_ERR_LOG_EN_0_TAGPOOL_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_REDUCTIONTSTATE_ERR_LOG_EN_0_TAGPOOL_ECC_DBE_ERR 3:3 /* RWEVF */
#define NV_REDUCTIONTSTATE_ERR_LOG_EN_0_TAGPOOL_ECC_DBE_ERR__PROD 0x00000001 /* RW--V */
#define NV_REDUCTIONTSTATE_ERR_LOG_EN_0_TAGPOOL_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_REDUCTIONTSTATE_ERR_LOG_EN_0_TAGPOOL_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_REDUCTIONTSTATE_ERR_LOG_EN_0_CRUMBSTORE_BUF_OVERWRITE_ERR 16:16 /* RWEVF */
#define NV_REDUCTIONTSTATE_ERR_LOG_EN_0_CRUMBSTORE_BUF_OVERWRITE_ERR__PROD 0x00000001 /* RW--V */
#define NV_REDUCTIONTSTATE_ERR_LOG_EN_0_CRUMBSTORE_BUF_OVERWRITE_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_REDUCTIONTSTATE_ERR_LOG_EN_0_CRUMBSTORE_BUF_OVERWRITE_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_REDUCTIONTSTATE_ERR_LOG_EN_0_CRUMBSTORE_ECC_LIMIT_ERR 18:18 /* RWEVF */
#define NV_REDUCTIONTSTATE_ERR_LOG_EN_0_CRUMBSTORE_ECC_LIMIT_ERR__PROD 0x00000001 /* RW--V */
#define NV_REDUCTIONTSTATE_ERR_LOG_EN_0_CRUMBSTORE_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_REDUCTIONTSTATE_ERR_LOG_EN_0_CRUMBSTORE_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_REDUCTIONTSTATE_ERR_LOG_EN_0_CRUMBSTORE_ECC_DBE_ERR 19:19 /* RWEVF */
#define NV_REDUCTIONTSTATE_ERR_LOG_EN_0_CRUMBSTORE_ECC_DBE_ERR__PROD 0x00000001 /* RW--V */
#define NV_REDUCTIONTSTATE_ERR_LOG_EN_0_CRUMBSTORE_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_REDUCTIONTSTATE_ERR_LOG_EN_0_CRUMBSTORE_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_REDUCTIONTSTATE_ERR_LOG_EN_0_CRUMBSTORE_RTO_ERR 20:20 /* RWEVF */
#define NV_REDUCTIONTSTATE_ERR_LOG_EN_0_CRUMBSTORE_RTO_ERR__PROD 0x00000001 /* RW--V */
#define NV_REDUCTIONTSTATE_ERR_LOG_EN_0_CRUMBSTORE_RTO_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_REDUCTIONTSTATE_ERR_LOG_EN_0_CRUMBSTORE_RTO_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_REDUCTIONTSTATE_ERR_FATAL_REPORT_EN_0 0x00002c08 /* RW-4R */
#define NV_REDUCTIONTSTATE_ERR_FATAL_REPORT_EN_0_TAGPOOL_ECC_LIMIT_ERR 2:2 /* RWEVF */
#define NV_REDUCTIONTSTATE_ERR_FATAL_REPORT_EN_0_TAGPOOL_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_REDUCTIONTSTATE_ERR_FATAL_REPORT_EN_0_TAGPOOL_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_REDUCTIONTSTATE_ERR_FATAL_REPORT_EN_0_TAGPOOL_ECC_DBE_ERR 3:3 /* RWEVF */
#define NV_REDUCTIONTSTATE_ERR_FATAL_REPORT_EN_0_TAGPOOL_ECC_DBE_ERR__PROD 0x00000001 /* RW--V */
#define NV_REDUCTIONTSTATE_ERR_FATAL_REPORT_EN_0_TAGPOOL_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_REDUCTIONTSTATE_ERR_FATAL_REPORT_EN_0_TAGPOOL_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_REDUCTIONTSTATE_ERR_FATAL_REPORT_EN_0_CRUMBSTORE_BUF_OVERWRITE_ERR 16:16 /* RWEVF */
#define NV_REDUCTIONTSTATE_ERR_FATAL_REPORT_EN_0_CRUMBSTORE_BUF_OVERWRITE_ERR__PROD 0x00000001 /* RW--V */
#define NV_REDUCTIONTSTATE_ERR_FATAL_REPORT_EN_0_CRUMBSTORE_BUF_OVERWRITE_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_REDUCTIONTSTATE_ERR_FATAL_REPORT_EN_0_CRUMBSTORE_BUF_OVERWRITE_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_REDUCTIONTSTATE_ERR_FATAL_REPORT_EN_0_CRUMBSTORE_ECC_LIMIT_ERR 18:18 /* RWEVF */
#define NV_REDUCTIONTSTATE_ERR_FATAL_REPORT_EN_0_CRUMBSTORE_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_REDUCTIONTSTATE_ERR_FATAL_REPORT_EN_0_CRUMBSTORE_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_REDUCTIONTSTATE_ERR_FATAL_REPORT_EN_0_CRUMBSTORE_ECC_DBE_ERR 19:19 /* RWEVF */
#define NV_REDUCTIONTSTATE_ERR_FATAL_REPORT_EN_0_CRUMBSTORE_ECC_DBE_ERR__PROD 0x00000001 /* RW--V */
#define NV_REDUCTIONTSTATE_ERR_FATAL_REPORT_EN_0_CRUMBSTORE_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_REDUCTIONTSTATE_ERR_FATAL_REPORT_EN_0_CRUMBSTORE_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_REDUCTIONTSTATE_ERR_FATAL_REPORT_EN_0_CRUMBSTORE_RTO_ERR 20:20 /* RWEVF */
#define NV_REDUCTIONTSTATE_ERR_FATAL_REPORT_EN_0_CRUMBSTORE_RTO_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_REDUCTIONTSTATE_ERR_FATAL_REPORT_EN_0_CRUMBSTORE_RTO_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_REDUCTIONTSTATE_ERR_NON_FATAL_REPORT_EN_0 0x00002c0c /* RW-4R */
#define NV_REDUCTIONTSTATE_ERR_NON_FATAL_REPORT_EN_0_TAGPOOL_ECC_LIMIT_ERR 2:2 /* RWEVF */
#define NV_REDUCTIONTSTATE_ERR_NON_FATAL_REPORT_EN_0_TAGPOOL_ECC_LIMIT_ERR__PROD 0x00000001 /* RW--V */
#define NV_REDUCTIONTSTATE_ERR_NON_FATAL_REPORT_EN_0_TAGPOOL_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_REDUCTIONTSTATE_ERR_NON_FATAL_REPORT_EN_0_TAGPOOL_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_REDUCTIONTSTATE_ERR_NON_FATAL_REPORT_EN_0_TAGPOOL_ECC_DBE_ERR 3:3 /* RWEVF */
#define NV_REDUCTIONTSTATE_ERR_NON_FATAL_REPORT_EN_0_TAGPOOL_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_REDUCTIONTSTATE_ERR_NON_FATAL_REPORT_EN_0_TAGPOOL_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_REDUCTIONTSTATE_ERR_NON_FATAL_REPORT_EN_0_CRUMBSTORE_BUF_OVERWRITE_ERR 16:16 /* RWEVF */
#define NV_REDUCTIONTSTATE_ERR_NON_FATAL_REPORT_EN_0_CRUMBSTORE_BUF_OVERWRITE_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_REDUCTIONTSTATE_ERR_NON_FATAL_REPORT_EN_0_CRUMBSTORE_BUF_OVERWRITE_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_REDUCTIONTSTATE_ERR_NON_FATAL_REPORT_EN_0_CRUMBSTORE_ECC_LIMIT_ERR 18:18 /* RWEVF */
#define NV_REDUCTIONTSTATE_ERR_NON_FATAL_REPORT_EN_0_CRUMBSTORE_ECC_LIMIT_ERR__PROD 0x00000001 /* RW--V */
#define NV_REDUCTIONTSTATE_ERR_NON_FATAL_REPORT_EN_0_CRUMBSTORE_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_REDUCTIONTSTATE_ERR_NON_FATAL_REPORT_EN_0_CRUMBSTORE_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_REDUCTIONTSTATE_ERR_NON_FATAL_REPORT_EN_0_CRUMBSTORE_ECC_DBE_ERR 19:19 /* RWEVF */
#define NV_REDUCTIONTSTATE_ERR_NON_FATAL_REPORT_EN_0_CRUMBSTORE_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_REDUCTIONTSTATE_ERR_NON_FATAL_REPORT_EN_0_CRUMBSTORE_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_REDUCTIONTSTATE_ERR_NON_FATAL_REPORT_EN_0_CRUMBSTORE_RTO_ERR 20:20 /* RWEVF */
#define NV_REDUCTIONTSTATE_ERR_NON_FATAL_REPORT_EN_0_CRUMBSTORE_RTO_ERR__PROD 0x00000001 /* RW--V */
#define NV_REDUCTIONTSTATE_ERR_NON_FATAL_REPORT_EN_0_CRUMBSTORE_RTO_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_REDUCTIONTSTATE_ERR_NON_FATAL_REPORT_EN_0_CRUMBSTORE_RTO_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_REDUCTIONTSTATE_ERR_CORRECTABLE_REPORT_EN_0 0x00002c10 /* RW-4R */
#define NV_REDUCTIONTSTATE_ERR_CONTAIN_EN_0 0x00002c14 /* RW-4R */
#define NV_REDUCTIONTSTATE_ERR_CONTAIN_EN_0_TAGPOOL_ECC_LIMIT_ERR 2:2 /* RWEVF */
#define NV_REDUCTIONTSTATE_ERR_CONTAIN_EN_0_TAGPOOL_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_REDUCTIONTSTATE_ERR_CONTAIN_EN_0_TAGPOOL_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_REDUCTIONTSTATE_ERR_CONTAIN_EN_0_TAGPOOL_ECC_DBE_ERR 3:3 /* RWEVF */
#define NV_REDUCTIONTSTATE_ERR_CONTAIN_EN_0_TAGPOOL_ECC_DBE_ERR__PROD 0x00000001 /* RW--V */
#define NV_REDUCTIONTSTATE_ERR_CONTAIN_EN_0_TAGPOOL_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_REDUCTIONTSTATE_ERR_CONTAIN_EN_0_TAGPOOL_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_REDUCTIONTSTATE_ERR_CONTAIN_EN_0_CRUMBSTORE_BUF_OVERWRITE_ERR 16:16 /* RWEVF */
#define NV_REDUCTIONTSTATE_ERR_CONTAIN_EN_0_CRUMBSTORE_BUF_OVERWRITE_ERR__PROD 0x00000001 /* RW--V */
#define NV_REDUCTIONTSTATE_ERR_CONTAIN_EN_0_CRUMBSTORE_BUF_OVERWRITE_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_REDUCTIONTSTATE_ERR_CONTAIN_EN_0_CRUMBSTORE_BUF_OVERWRITE_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_REDUCTIONTSTATE_ERR_CONTAIN_EN_0_CRUMBSTORE_ECC_LIMIT_ERR 18:18 /* RWEVF */
#define NV_REDUCTIONTSTATE_ERR_CONTAIN_EN_0_CRUMBSTORE_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_REDUCTIONTSTATE_ERR_CONTAIN_EN_0_CRUMBSTORE_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_REDUCTIONTSTATE_ERR_CONTAIN_EN_0_CRUMBSTORE_ECC_DBE_ERR 19:19 /* RWEVF */
#define NV_REDUCTIONTSTATE_ERR_CONTAIN_EN_0_CRUMBSTORE_ECC_DBE_ERR__PROD 0x00000001 /* RW--V */
#define NV_REDUCTIONTSTATE_ERR_CONTAIN_EN_0_CRUMBSTORE_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_REDUCTIONTSTATE_ERR_CONTAIN_EN_0_CRUMBSTORE_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_REDUCTIONTSTATE_ERR_CONTAIN_EN_0_CRUMBSTORE_RTO_ERR 20:20 /* RWEVF */
#define NV_REDUCTIONTSTATE_ERR_CONTAIN_EN_0_CRUMBSTORE_RTO_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_REDUCTIONTSTATE_ERR_CONTAIN_EN_0_CRUMBSTORE_RTO_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_REDUCTIONTSTATE_ERR_FIRST_0 0x00002c1c /* RW-4R */
#define NV_REDUCTIONTSTATE_ERR_FIRST_0_TAGPOOL_ECC_LIMIT_ERR 2:2 /* RWDVF */
#define NV_REDUCTIONTSTATE_ERR_FIRST_0_TAGPOOL_ECC_LIMIT_ERR__ONWRITE "oneToClear" /* */
#define NV_REDUCTIONTSTATE_ERR_FIRST_0_TAGPOOL_ECC_LIMIT_ERR_NONE 0x00000000 /* RWD-V */
#define NV_REDUCTIONTSTATE_ERR_FIRST_0_TAGPOOL_ECC_LIMIT_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_REDUCTIONTSTATE_ERR_FIRST_0_TAGPOOL_ECC_DBE_ERR 3:3 /* RWDVF */
#define NV_REDUCTIONTSTATE_ERR_FIRST_0_TAGPOOL_ECC_DBE_ERR__ONWRITE "oneToClear" /* */
#define NV_REDUCTIONTSTATE_ERR_FIRST_0_TAGPOOL_ECC_DBE_ERR_NONE 0x00000000 /* RWD-V */
#define NV_REDUCTIONTSTATE_ERR_FIRST_0_TAGPOOL_ECC_DBE_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_REDUCTIONTSTATE_ERR_FIRST_0_CRUMBSTORE_BUF_OVERWRITE_ERR 16:16 /* RWDVF */
#define NV_REDUCTIONTSTATE_ERR_FIRST_0_CRUMBSTORE_BUF_OVERWRITE_ERR__ONWRITE "oneToClear" /* */
#define NV_REDUCTIONTSTATE_ERR_FIRST_0_CRUMBSTORE_BUF_OVERWRITE_ERR_NONE 0x00000000 /* RWD-V */
#define NV_REDUCTIONTSTATE_ERR_FIRST_0_CRUMBSTORE_BUF_OVERWRITE_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_REDUCTIONTSTATE_ERR_FIRST_0_CRUMBSTORE_ECC_LIMIT_ERR 18:18 /* RWDVF */
#define NV_REDUCTIONTSTATE_ERR_FIRST_0_CRUMBSTORE_ECC_LIMIT_ERR__ONWRITE "oneToClear" /* */
#define NV_REDUCTIONTSTATE_ERR_FIRST_0_CRUMBSTORE_ECC_LIMIT_ERR_NONE 0x00000000 /* RWD-V */
#define NV_REDUCTIONTSTATE_ERR_FIRST_0_CRUMBSTORE_ECC_LIMIT_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_REDUCTIONTSTATE_ERR_FIRST_0_CRUMBSTORE_ECC_DBE_ERR 19:19 /* RWDVF */
#define NV_REDUCTIONTSTATE_ERR_FIRST_0_CRUMBSTORE_ECC_DBE_ERR__ONWRITE "oneToClear" /* */
#define NV_REDUCTIONTSTATE_ERR_FIRST_0_CRUMBSTORE_ECC_DBE_ERR_NONE 0x00000000 /* RWD-V */
#define NV_REDUCTIONTSTATE_ERR_FIRST_0_CRUMBSTORE_ECC_DBE_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_REDUCTIONTSTATE_ERR_FIRST_0_CRUMBSTORE_RTO_ERR 20:20 /* RWDVF */
#define NV_REDUCTIONTSTATE_ERR_FIRST_0_CRUMBSTORE_RTO_ERR__ONWRITE "oneToClear" /* */
#define NV_REDUCTIONTSTATE_ERR_FIRST_0_CRUMBSTORE_RTO_ERR_NONE 0x00000000 /* RWD-V */
#define NV_REDUCTIONTSTATE_ERR_FIRST_0_CRUMBSTORE_RTO_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_REDUCTIONTSTATE_ERR_TIMESTAMP_LOG 0x00002c50 /* R--4R */
#define NV_REDUCTIONTSTATE_ERR_TIMESTAMP_LOG_TIMESTAMP 23:0 /* R-DVF */
#define NV_REDUCTIONTSTATE_ERR_TIMESTAMP_LOG_TIMESTAMP_INIT 0x00000000 /* R-D-V */
#define NV_REDUCTIONTSTATE_ERR_ECC_CTRL 0x00002d00 /* RW-4R */
#define NV_REDUCTIONTSTATE_ERR_ECC_CTRL_TAGPOOL_ECC_ENABLE 0:0 /* RWEVF */
#define NV_REDUCTIONTSTATE_ERR_ECC_CTRL_TAGPOOL_ECC_ENABLE_ENABLE 0x00000001 /* RW--V */
#define NV_REDUCTIONTSTATE_ERR_ECC_CTRL_TAGPOOL_ECC_ENABLE_DISABLE 0x00000000 /* RWE-V */
#define NV_REDUCTIONTSTATE_ERR_ECC_CTRL_TAGPOOL_ECC_ENABLE__PROD 0x00000001 /* RW--V */
#define NV_REDUCTIONTSTATE_ERR_ECC_CTRL_CRUMBSTORE_ECC_ENABLE 1:1 /* RWEVF */
#define NV_REDUCTIONTSTATE_ERR_ECC_CTRL_CRUMBSTORE_ECC_ENABLE_ENABLE 0x00000001 /* RW--V */
#define NV_REDUCTIONTSTATE_ERR_ECC_CTRL_CRUMBSTORE_ECC_ENABLE_DISABLE 0x00000000 /* RWE-V */
#define NV_REDUCTIONTSTATE_ERR_ECC_CTRL_CRUMBSTORE_ECC_ENABLE__PROD 0x00000001 /* RW--V */
#define NV_REDUCTIONTSTATE_ERR_TAGPOOL_ECC_ERROR_COUNTER 0x00002d20 /* RW-4R */
#define NV_REDUCTIONTSTATE_ERR_TAGPOOL_ECC_ERROR_COUNTER_ERROR_COUNT 23:0 /* RWDVF */
#define NV_REDUCTIONTSTATE_ERR_TAGPOOL_ECC_ERROR_COUNTER_ERROR_COUNT_INIT 0x00000000 /* RWD-V */
#define NV_REDUCTIONTSTATE_ERR_TAGPOOL_ECC_ERROR_COUNTER_LIMIT 0x00002d40 /* RW-4R */
#define NV_REDUCTIONTSTATE_ERR_TAGPOOL_ECC_ERROR_COUNTER_LIMIT_ERROR_LIMIT 23:0 /* RWDVF */
#define NV_REDUCTIONTSTATE_ERR_TAGPOOL_ECC_ERROR_COUNTER_LIMIT_ERROR_LIMIT_INIT 0x00ffffff /* RWD-V */
#define NV_REDUCTIONTSTATE_ERR_TAGPOOL_ECC_ERROR_ADDRESS 0x00002d60 /* R--4R */
#define NV_REDUCTIONTSTATE_ERR_TAGPOOL_ECC_ERROR_ADDRESS_ERROR_ADDRESS 7:0 /* R-DVF */
#define NV_REDUCTIONTSTATE_ERR_TAGPOOL_ECC_ERROR_ADDRESS_ERROR_ADDRESS_INIT 0x00000000 /* R-D-V */
#define NV_REDUCTIONTSTATE_ERR_TAGPOOL_ECC_ERROR_ADDRESS_VALID 0x00002d80 /* R--4R */
#define NV_REDUCTIONTSTATE_ERR_TAGPOOL_ECC_ERROR_ADDRESS_VALID_VALID 0:0 /* R-DVF */
#define NV_REDUCTIONTSTATE_ERR_TAGPOOL_ECC_ERROR_ADDRESS_VALID_VALID_INVALID 0x00000000 /* R-D-V */
#define NV_REDUCTIONTSTATE_ERR_TAGPOOL_ECC_ERROR_ADDRESS_VALID_VALID_VALID 0x00000001 /* R---V */
#define NV_REDUCTIONTSTATE_ERR_CRUMBSTORE_ECC_ERROR_COUNTER 0x00002e00 /* RW-4R */
#define NV_REDUCTIONTSTATE_ERR_CRUMBSTORE_ECC_ERROR_COUNTER_ERROR_COUNT 23:0 /* RWDVF */
#define NV_REDUCTIONTSTATE_ERR_CRUMBSTORE_ECC_ERROR_COUNTER_ERROR_COUNT_INIT 0x00000000 /* RWD-V */
#define NV_REDUCTIONTSTATE_ERR_CRUMBSTORE_ECC_ERROR_COUNTER_LIMIT 0x00002e20 /* RW-4R */
#define NV_REDUCTIONTSTATE_ERR_CRUMBSTORE_ECC_ERROR_COUNTER_LIMIT_ERROR_LIMIT 23:0 /* RWDVF */
#define NV_REDUCTIONTSTATE_ERR_CRUMBSTORE_ECC_ERROR_COUNTER_LIMIT_ERROR_LIMIT_INIT 0x00ffffff /* RWD-V */
#define NV_REDUCTIONTSTATE_ERR_CRUMBSTORE_ECC_ERROR_ADDRESS 0x00002e40 /* R--4R */
#define NV_REDUCTIONTSTATE_ERR_CRUMBSTORE_ECC_ERROR_ADDRESS_ERROR_ADDRESS 7:0 /* R-DVF */
#define NV_REDUCTIONTSTATE_ERR_CRUMBSTORE_ECC_ERROR_ADDRESS_ERROR_ADDRESS_INIT 0x00000000 /* R-D-V */
#define NV_REDUCTIONTSTATE_ERR_CRUMBSTORE_ECC_ERROR_ADDRESS_VALID 0x00002e60 /* R--4R */
#define NV_REDUCTIONTSTATE_ERR_CRUMBSTORE_ECC_ERROR_ADDRESS_VALID_VALID 0:0 /* R-DVF */
#define NV_REDUCTIONTSTATE_ERR_CRUMBSTORE_ECC_ERROR_ADDRESS_VALID_VALID_INVALID 0x00000000 /* R-D-V */
#define NV_REDUCTIONTSTATE_ERR_CRUMBSTORE_ECC_ERROR_ADDRESS_VALID_VALID_VALID 0x00000001 /* R---V */
#define NV_REDUCTIONTSTATE_STAT_STALL_BUSY_CONTROL 0x00002f00 /* RW-4R */
#define NV_REDUCTIONTSTATE_STAT_STALL_BUSY_CONTROL_ENABLE_TIMER 0:0 /* RWEVF */
#define NV_REDUCTIONTSTATE_STAT_STALL_BUSY_CONTROL_ENABLE_TIMER_DISABLE 0x00000000 /* RWE-V */
#define NV_REDUCTIONTSTATE_STAT_STALL_BUSY_CONTROL_ENABLE_TIMER_ENABLE 0x00000001 /* RW--V */
#define NV_REDUCTIONTSTATE_STAT_STALL_BUSY_CONTROL_SNAP_ON_DEMAND 1:1 /* RWEVF */
#define NV_REDUCTIONTSTATE_STAT_STALL_BUSY_CONTROL_SNAP_ON_DEMAND__ONWRITE "oneToSet" /* */
#define NV_REDUCTIONTSTATE_STAT_STALL_BUSY_CONTROL_SNAP_ON_DEMAND_DISABLE 0x00000000 /* RWE-V */
#define NV_REDUCTIONTSTATE_STAT_STALL_BUSY_CONTROL_SNAP_ON_DEMAND_ENABLE 0x00000001 /* RW--V */
#define NV_REDUCTIONTSTATE_STAT_WINDOW_0_HIGH 0x00002f04 /* RW-4R */
#define NV_REDUCTIONTSTATE_STAT_WINDOW_0_HIGH_VALUE 15:0 /* RWEVF */
#define NV_REDUCTIONTSTATE_STAT_WINDOW_0_HIGH_VALUE_INIT 0x00000000 /* RWE-V */
#define NV_REDUCTIONTSTATE_STAT_WINDOW_0_LOW 0x00002f08 /* RW-4R */
#define NV_REDUCTIONTSTATE_STAT_WINDOW_0_LOW_VALUE 31:0 /* RWEVF */
#define NV_REDUCTIONTSTATE_STAT_WINDOW_0_LOW_VALUE_INIT 0x00000000 /* RWE-V */
#define NV_REDUCTIONTSTATE_STAT_BUSY_TIMER_0_HIGH 0x00002f0c /* RW-4R */
#define NV_REDUCTIONTSTATE_STAT_BUSY_TIMER_0_HIGH_VALUE 15:0 /* RWEVF */
#define NV_REDUCTIONTSTATE_STAT_BUSY_TIMER_0_HIGH_VALUE_INIT 0x00000000 /* RWE-V */
#define NV_REDUCTIONTSTATE_STAT_BUSY_TIMER_0_LOW 0x00002f10 /* RW-4R */
#define NV_REDUCTIONTSTATE_STAT_BUSY_TIMER_0_LOW_VALUE 31:0 /* RWEVF */
#define NV_REDUCTIONTSTATE_STAT_BUSY_TIMER_0_LOW_VALUE_INIT 0x00000000 /* RWE-V */
#define NV_REDUCTIONTSTATE_STAT_STALL_TIMER_0_HIGH 0x00002f14 /* RW-4R */
#define NV_REDUCTIONTSTATE_STAT_STALL_TIMER_0_HIGH_VALUE 15:0 /* RWEVF */
#define NV_REDUCTIONTSTATE_STAT_STALL_TIMER_0_HIGH_VALUE_INIT 0x00000000 /* RWE-V */
#define NV_REDUCTIONTSTATE_STAT_STALL_TIMER_0_LOW 0x00002f18 /* RW-4R */
#define NV_REDUCTIONTSTATE_STAT_STALL_TIMER_0_LOW_VALUE 31:0 /* RWEVF */
#define NV_REDUCTIONTSTATE_STAT_STALL_TIMER_0_LOW_VALUE_INIT 0x00000000 /* RWE-V */
#define NV_REDUCTIONTSTATE_STAT_WINDOW_1_HIGH 0x00002f1c /* RW-4R */
#define NV_REDUCTIONTSTATE_STAT_WINDOW_1_HIGH_VALUE 15:0 /* RWEVF */
#define NV_REDUCTIONTSTATE_STAT_WINDOW_1_HIGH_VALUE_INIT 0x00000000 /* RWE-V */
#define NV_REDUCTIONTSTATE_STAT_WINDOW_1_LOW 0x00002f20 /* RW-4R */
#define NV_REDUCTIONTSTATE_STAT_WINDOW_1_LOW_VALUE 31:0 /* RWEVF */
#define NV_REDUCTIONTSTATE_STAT_WINDOW_1_LOW_VALUE_INIT 0x00000000 /* RWE-V */
#define NV_REDUCTIONTSTATE_STAT_BUSY_TIMER_1_HIGH 0x00002f24 /* RW-4R */
#define NV_REDUCTIONTSTATE_STAT_BUSY_TIMER_1_HIGH_VALUE 15:0 /* RWEVF */
#define NV_REDUCTIONTSTATE_STAT_BUSY_TIMER_1_HIGH_VALUE_INIT 0x00000000 /* RWE-V */
#define NV_REDUCTIONTSTATE_STAT_BUSY_TIMER_1_LOW 0x00002f28 /* RW-4R */
#define NV_REDUCTIONTSTATE_STAT_BUSY_TIMER_1_LOW_VALUE 31:0 /* RWEVF */
#define NV_REDUCTIONTSTATE_STAT_BUSY_TIMER_1_LOW_VALUE_INIT 0x00000000 /* RWE-V */
#define NV_REDUCTIONTSTATE_STAT_STALL_TIMER_1_HIGH 0x00002f2c /* RW-4R */
#define NV_REDUCTIONTSTATE_STAT_STALL_TIMER_1_HIGH_VALUE 15:0 /* RWEVF */
#define NV_REDUCTIONTSTATE_STAT_STALL_TIMER_1_HIGH_VALUE_INIT 0x00000000 /* RWE-V */
#define NV_REDUCTIONTSTATE_STAT_STALL_TIMER_1_LOW 0x00002f30 /* RW-4R */
#define NV_REDUCTIONTSTATE_STAT_STALL_TIMER_1_LOW_VALUE 31:0 /* RWEVF */
#define NV_REDUCTIONTSTATE_STAT_STALL_TIMER_1_LOW_VALUE_INIT 0x00000000 /* RWE-V */
#define NV_REDUCTIONTSTATE_STAT_RESIDENCY_CONTROL 0x00002f34 /* RW-4R */
#define NV_REDUCTIONTSTATE_STAT_RESIDENCY_CONTROL_ENABLE_TIMER 0:0 /* RWEVF */
#define NV_REDUCTIONTSTATE_STAT_RESIDENCY_CONTROL_ENABLE_TIMER_DISABLE 0x00000000 /* RWE-V */
#define NV_REDUCTIONTSTATE_STAT_RESIDENCY_CONTROL_ENABLE_TIMER_ENABLE 0x00000001 /* RW--V */
#define NV_REDUCTIONTSTATE_STAT_RESIDENCY_CONTROL_SNAP_ON_DEMAND 1:1 /* RWEVF */
#define NV_REDUCTIONTSTATE_STAT_RESIDENCY_CONTROL_SNAP_ON_DEMAND__ONWRITE "oneToSet" /* */
#define NV_REDUCTIONTSTATE_STAT_RESIDENCY_CONTROL_SNAP_ON_DEMAND_DISABLE 0x00000000 /* RWE-V */
#define NV_REDUCTIONTSTATE_STAT_RESIDENCY_CONTROL_SNAP_ON_DEMAND_ENABLE 0x00000001 /* RW--V */
#define NV_REDUCTIONTSTATE_STAT_RESIDENCY_BIN_CTRL_LOW 0x00002f38 /* RW-4R */
#define NV_REDUCTIONTSTATE_STAT_RESIDENCY_BIN_CTRL_LOW_LIMIT 23:0 /* RWEVF */
#define NV_REDUCTIONTSTATE_STAT_RESIDENCY_BIN_CTRL_LOW_LIMIT_INIT 0x0028b0ab /* RWE-V */
#define NV_REDUCTIONTSTATE_STAT_RESIDENCY_BIN_CTRL_HIGH 0x00002f3c /* RW-4R */
#define NV_REDUCTIONTSTATE_STAT_RESIDENCY_BIN_CTRL_HIGH_LIMIT 23:0 /* RWEVF */
#define NV_REDUCTIONTSTATE_STAT_RESIDENCY_BIN_CTRL_HIGH_LIMIT_INIT 0x00cb7355 /* RWE-V */
#define NV_REDUCTIONTSTATE_STAT_RESIDENCY_COUNT_CTRL 0x00002f40 /* RW-4R */
#define NV_REDUCTIONTSTATE_STAT_RESIDENCY_COUNT_CTRL_INDEX 9:0 /* RWEVF */
#define NV_REDUCTIONTSTATE_STAT_RESIDENCY_COUNT_CTRL_INDEX_MIN 0x00000000 /* RWE-V */
#define NV_REDUCTIONTSTATE_STAT_RESIDENCY_COUNT_CTRL_INDEX_MAX 0x000002ff /* RW--V */
#define NV_REDUCTIONTSTATE_STAT_RESIDENCY_COUNT_CTRL_INDEX_MCID_STRIDE 0x00000006 /* */
#define NV_REDUCTIONTSTATE_STAT_RESIDENCY_COUNT_CTRL_INDEX_BIN_LOW_31_0 0x00000000 /* */
#define NV_REDUCTIONTSTATE_STAT_RESIDENCY_COUNT_CTRL_INDEX_BIN_LOW_47_32 0x00000001 /* */
#define NV_REDUCTIONTSTATE_STAT_RESIDENCY_COUNT_CTRL_INDEX_BIN_MED_31_0 0x00000002 /* */
#define NV_REDUCTIONTSTATE_STAT_RESIDENCY_COUNT_CTRL_INDEX_BIN_MED_47_32 0x00000003 /* */
#define NV_REDUCTIONTSTATE_STAT_RESIDENCY_COUNT_CTRL_INDEX_BIN_HIGH_31_0 0x00000004 /* */
#define NV_REDUCTIONTSTATE_STAT_RESIDENCY_COUNT_CTRL_INDEX_BIN_HIGH_47_32 0x00000005 /* */
#define NV_REDUCTIONTSTATE_STAT_RESIDENCY_COUNT_CTRL_AUTOINCR 10:10 /* RWEVF */
#define NV_REDUCTIONTSTATE_STAT_RESIDENCY_COUNT_CTRL_AUTOINCR_OFF 0x00000000 /* RW--V */
#define NV_REDUCTIONTSTATE_STAT_RESIDENCY_COUNT_CTRL_AUTOINCR_ON 0x00000001 /* RWE-V */
#define NV_REDUCTIONTSTATE_STAT_RESIDENCY_COUNT_DATA 0x00002f44 /* R--4R */
#define NV_REDUCTIONTSTATE_STAT_RESIDENCY_COUNT_DATA_COUNT 31:0 /* R-XVF */
#define NV_REDUCTIONTSTATE_STAT_RESIDENCY_COUNT_DATA__APERTURE_INDEX_OFFSET -0x00000004 /* */
#endif // __ls10_dev_reductiontstate_ip_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the Software),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __ls10_dev_riscv_pri_h__
#define __ls10_dev_riscv_pri_h__
/* This file is autogenerated. Do not edit */
#define NV_FALCON2_SOE_BASE 0x00841000
#define NV_PRISCV_RISCV_IRQMASK 0x00000528 /* R--4R */
#define NV_PRISCV_RISCV_IRQDEST 0x0000052c /* RW-4R */
#define NV_PRISCV_RISCV_IRQDELEG 0x00000534 /* RW-4R */
#define NV_PRISCV_RISCV_CPUCTL 0x00000388 /* RW-4R */
#define NV_PRISCV_RISCV_RPC 0x000003ec /* R--4R */
#define NV_PRISCV_RISCV_TRACECTL 0x00000400 /* RW-4R */
#define NV_PRISCV_RISCV_TRACECTL_LOW_THSHD 7:0 /* RWIVF */
#define NV_PRISCV_RISCV_TRACECTL_LOW_THSHD_INIT 0x00000000 /* RWI-V */
#define NV_PRISCV_RISCV_TRACECTL_HIGH_THSHD 15:8 /* RWIVF */
#define NV_PRISCV_RISCV_TRACECTL_HIGH_THSHD_INIT 0x000000ff /* RWI-V */
#define NV_PRISCV_RISCV_TRACECTL_UMODE_ENABLE 20:20 /* RWIVF */
#define NV_PRISCV_RISCV_TRACECTL_UMODE_ENABLE_FALSE 0x00000000 /* RWI-V */
#define NV_PRISCV_RISCV_TRACECTL_UMODE_ENABLE_TRUE 0x00000001 /* RW--V */
#define NV_PRISCV_RISCV_TRACECTL_SMODE_ENABLE 21:21 /* RWIVF */
#define NV_PRISCV_RISCV_TRACECTL_SMODE_ENABLE_FALSE 0x00000000 /* RWI-V */
#define NV_PRISCV_RISCV_TRACECTL_SMODE_ENABLE_TRUE 0x00000001 /* RW--V */
#define NV_PRISCV_RISCV_TRACECTL_MMODE_ENABLE 23:23 /* RWIVF */
#define NV_PRISCV_RISCV_TRACECTL_MMODE_ENABLE_FALSE 0x00000000 /* RWI-V */
#define NV_PRISCV_RISCV_TRACECTL_MMODE_ENABLE_TRUE 0x00000001 /* RW--V */
#define NV_PRISCV_RISCV_TRACECTL_MODE 25:24 /* RWIVF */
#define NV_PRISCV_RISCV_TRACECTL_MODE_FULL 0x00000000 /* RWI-V */
#define NV_PRISCV_RISCV_TRACECTL_MODE_REDUCED 0x00000001 /* RW--V */
#define NV_PRISCV_RISCV_TRACECTL_MODE_STACK 0x00000002 /* RW--V */
#define NV_PRISCV_RISCV_TRACECTL_BELOW_LO 27:27 /* RWIVF */
#define NV_PRISCV_RISCV_TRACECTL_BELOW_LO_INIT 0x00000000 /* RWI-V */
#define NV_PRISCV_RISCV_TRACECTL_ABOVE_HI 28:28 /* RWIVF */
#define NV_PRISCV_RISCV_TRACECTL_ABOVE_HI_INIT 0x00000000 /* RWI-V */
#define NV_PRISCV_RISCV_TRACECTL_INTR_ENABLE 29:29 /* R-IVF */
#define NV_PRISCV_RISCV_TRACECTL_INTR_ENABLE_FALSE 0x00000000 /* R-I-V */
#define NV_PRISCV_RISCV_TRACECTL_INTR_ENABLE_TRUE 0x00000001 /* R---V */
#define NV_PRISCV_RISCV_TRACECTL_FULL 30:30 /* RWIVF */
#define NV_PRISCV_RISCV_TRACECTL_FULL_INIT 0x00000000 /* RWI-V */
#define NV_PRISCV_RISCV_TRACECTL_EMPTY 31:31 /* RWIVF */
#define NV_PRISCV_RISCV_TRACECTL_EMPTY_INIT 0x00000000 /* RWI-V */
#define NV_PRISCV_RISCV_TRACE_RDIDX 0x00000404 /* RW-4R */
#define NV_PRISCV_RISCV_TRACE_RDIDX_RDIDX 7:0 /* RWIVF */
#define NV_PRISCV_RISCV_TRACE_RDIDX_RDIDX_INIT 0x00000000 /* RWI-V */
#define NV_PRISCV_RISCV_TRACE_RDIDX_RSVD0 15:8 /* R-IVF */
#define NV_PRISCV_RISCV_TRACE_RDIDX_RSVD0_INIT 0x00000000 /* R-I-V */
#define NV_PRISCV_RISCV_TRACE_RDIDX_MAXIDX 23:16 /* R-IVF */
#define NV_PRISCV_RISCV_TRACE_RDIDX_MAXIDX_INIT 0x0000003f /* R-I-V */
#define NV_PRISCV_RISCV_TRACE_RDIDX_RSVD1 31:24 /* R-IVF */
#define NV_PRISCV_RISCV_TRACE_RDIDX_RSVD1_INIT 0x00000000 /* R-I-V */
#define NV_PRISCV_RISCV_TRACE_WTIDX 0x00000408 /* RW-4R */
#define NV_PRISCV_RISCV_TRACE_WTIDX_WTIDX 31:24 /* RWIVF */
#define NV_PRISCV_RISCV_TRACE_WTIDX_WTIDX_INIT 0x00000000 /* RWI-V */
#define NV_PRISCV_RISCV_TRACE_WTIDX_RSVD1 23:0 /* R-IVF */
#define NV_PRISCV_RISCV_TRACE_WTIDX_RSVD1_INIT 0x00000000 /* R-I-V */
#define NV_PRISCV_RISCV_TRACEPC_HI 0x00000410 /* RW-4R */
#define NV_PRISCV_RISCV_TRACEPC_LO 0x0000040c /* RW-4R */
#define NV_PRISCV_RISCV_PRIV_ERR_STAT 0x00000500 /* RW-4R */
#define NV_PRISCV_RISCV_PRIV_ERR_INFO 0x00000504 /* R--4R */
#define NV_PRISCV_RISCV_PRIV_ERR_ADDR 0x00000508 /* R--4R */
#define NV_PRISCV_RISCV_PRIV_ERR_ADDR_HI 0x0000050c /* R--4R */
#define NV_PRISCV_RISCV_HUB_ERR_STAT 0x00000510 /* RW-4R */
#define NV_PRISCV_RISCV_BCR_CTRL 0x00000668 /* RW-4R */
#endif // __ls10_dev_riscv_pri_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the Software),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __ls10_dev_route_ip_h__
#define __ls10_dev_route_ip_h__
/* This file is autogenerated. Do not edit */
#define NV_ROUTE 0x00005fff:0x00005000 /* RW--D */
#define NV_ROUTE_REG_TABLE_ADDRESS 0x00005080 /* RW-4R */
#define NV_ROUTE_REG_TABLE_ADDRESS_INDEX 7:0 /* RWEVF */
#define NV_ROUTE_REG_TABLE_ADDRESS_INDEX_MIN 0x00000000 /* RWE-V */
#define NV_ROUTE_REG_TABLE_ADDRESS_INDEX_GLTAB_DEPTH 0x000000ff /* RW--V */
#define NV_ROUTE_REG_TABLE_ADDRESS_AUTO_INCR 31:31 /* RWEVF */
#define NV_ROUTE_REG_TABLE_ADDRESS_AUTO_INCR_DISABLE 0x00000000 /* RW--V */
#define NV_ROUTE_REG_TABLE_ADDRESS_AUTO_INCR_ENABLE 0x00000001 /* RWE-V */
#define NV_ROUTE_REG_TABLE_DATA0 0x00005090 /* RW-4R */
#define NV_ROUTE_REG_TABLE_DATA0_GLX_0 3:0 /* RWEVF */
#define NV_ROUTE_REG_TABLE_DATA0_GLX_0_INIT 0x00000000 /* RWE-V */
#define NV_ROUTE_REG_TABLE_DATA0_GLX_1 7:4 /* RWEVF */
#define NV_ROUTE_REG_TABLE_DATA0_GLX_1_INIT 0x00000000 /* RWE-V */
#define NV_ROUTE_REG_TABLE_DATA0_GLX_2 11:8 /* RWEVF */
#define NV_ROUTE_REG_TABLE_DATA0_GLX_2_INIT 0x00000000 /* RWE-V */
#define NV_ROUTE_REG_TABLE_DATA0_GLX_3 15:12 /* RWEVF */
#define NV_ROUTE_REG_TABLE_DATA0_GLX_3_INIT 0x00000000 /* RWE-V */
#define NV_ROUTE_REG_TABLE_DATA0_GLX_4 19:16 /* RWEVF */
#define NV_ROUTE_REG_TABLE_DATA0_GLX_4_INIT 0x00000000 /* RWE-V */
#define NV_ROUTE_REG_TABLE_DATA0_GLX_5 23:20 /* RWEVF */
#define NV_ROUTE_REG_TABLE_DATA0_GLX_5_INIT 0x00000000 /* RWE-V */
#define NV_ROUTE_REG_TABLE_DATA0_GLX_6 27:24 /* RWEVF */
#define NV_ROUTE_REG_TABLE_DATA0_GLX_6_INIT 0x00000000 /* RWE-V */
#define NV_ROUTE_REG_TABLE_DATA0_GLX_7 31:28 /* RWEVF */
#define NV_ROUTE_REG_TABLE_DATA0_GLX_7_INIT 0x00000000 /* RWE-V */
#define NV_ROUTE_REG_TABLE_DATA1 0x00005094 /* RW-4R */
#define NV_ROUTE_REG_TABLE_DATA1_GLX_8 3:0 /* RWEVF */
#define NV_ROUTE_REG_TABLE_DATA1_GLX_8_INIT 0x00000000 /* RWE-V */
#define NV_ROUTE_REG_TABLE_DATA1_GLX_9 7:4 /* RWEVF */
#define NV_ROUTE_REG_TABLE_DATA1_GLX_9_INIT 0x00000000 /* RWE-V */
#define NV_ROUTE_REG_TABLE_DATA1_GLX_10 11:8 /* RWEVF */
#define NV_ROUTE_REG_TABLE_DATA1_GLX_10_INIT 0x00000000 /* RWE-V */
#define NV_ROUTE_REG_TABLE_DATA1_GLX_11 15:12 /* RWEVF */
#define NV_ROUTE_REG_TABLE_DATA1_GLX_11_INIT 0x00000000 /* RWE-V */
#define NV_ROUTE_REG_TABLE_DATA1_GLX_12 19:16 /* RWEVF */
#define NV_ROUTE_REG_TABLE_DATA1_GLX_12_INIT 0x00000000 /* RWE-V */
#define NV_ROUTE_REG_TABLE_DATA1_GLX_13 23:20 /* RWEVF */
#define NV_ROUTE_REG_TABLE_DATA1_GLX_13_INIT 0x00000000 /* RWE-V */
#define NV_ROUTE_REG_TABLE_DATA1_GLX_14 27:24 /* RWEVF */
#define NV_ROUTE_REG_TABLE_DATA1_GLX_14_INIT 0x00000000 /* RWE-V */
#define NV_ROUTE_REG_TABLE_DATA1_GLX_15 31:28 /* RWEVF */
#define NV_ROUTE_REG_TABLE_DATA1_GLX_15_INIT 0x00000000 /* RWE-V */
#define NV_ROUTE_REG_TABLE_DATA2 0x00005098 /* R--4R */
#define NV_ROUTE_REG_TABLE_DATA2_ECC 7:0 /* R-EVF */
#define NV_ROUTE_REG_TABLE_DATA2_ECC_INIT 0x00000000 /* R-E-V */
#define NV_ROUTE_CMD_ROUTE_TABLE0 0x000050a0 /* RW-4R */
#define NV_ROUTE_CMD_ROUTE_TABLE0_RFUN0 1:0 /* RWEVF */
#define NV_ROUTE_CMD_ROUTE_TABLE0_RFUN0_SPRAY 0x00000000 /* RWE-V */
#define NV_ROUTE_CMD_ROUTE_TABLE0_RFUN0_RESERVED 0x00000001 /* RW--V */
#define NV_ROUTE_CMD_ROUTE_TABLE0_RFUN0_RANDOM 0x00000002 /* RW--V */
#define NV_ROUTE_CMD_ROUTE_TABLE0_RFUN0_ALTERNATE 0x00000003 /* RW--V */
#define NV_ROUTE_CMD_ROUTE_TABLE0_RFUN1 5:4 /* RWEVF */
#define NV_ROUTE_CMD_ROUTE_TABLE0_RFUN1_SPRAY 0x00000000 /* RWE-V */
#define NV_ROUTE_CMD_ROUTE_TABLE0_RFUN1_RESERVED 0x00000001 /* RW--V */
#define NV_ROUTE_CMD_ROUTE_TABLE0_RFUN1_RANDOM 0x00000002 /* RW--V */
#define NV_ROUTE_CMD_ROUTE_TABLE0_RFUN1_ALTERNATE 0x00000003 /* RW--V */
#define NV_ROUTE_CMD_ROUTE_TABLE0_RFUN2 9:8 /* RWEVF */
#define NV_ROUTE_CMD_ROUTE_TABLE0_RFUN2_SPRAY 0x00000000 /* RWE-V */
#define NV_ROUTE_CMD_ROUTE_TABLE0_RFUN2_RESERVED 0x00000001 /* RW--V */
#define NV_ROUTE_CMD_ROUTE_TABLE0_RFUN2_RANDOM 0x00000002 /* RW--V */
#define NV_ROUTE_CMD_ROUTE_TABLE0_RFUN2_ALTERNATE 0x00000003 /* RW--V */
#define NV_ROUTE_CMD_ROUTE_TABLE0_RFUN3 13:12 /* RWEVF */
#define NV_ROUTE_CMD_ROUTE_TABLE0_RFUN3_SPRAY 0x00000000 /* RWE-V */
#define NV_ROUTE_CMD_ROUTE_TABLE0_RFUN3_RESERVED 0x00000001 /* RW--V */
#define NV_ROUTE_CMD_ROUTE_TABLE0_RFUN3_RANDOM 0x00000002 /* RW--V */
#define NV_ROUTE_CMD_ROUTE_TABLE0_RFUN3_ALTERNATE 0x00000003 /* RW--V */
#define NV_ROUTE_CMD_ROUTE_TABLE0_RFUN4 17:16 /* RWEVF */
#define NV_ROUTE_CMD_ROUTE_TABLE0_RFUN4_SPRAY 0x00000000 /* RWE-V */
#define NV_ROUTE_CMD_ROUTE_TABLE0_RFUN4_RESERVED 0x00000001 /* RW--V */
#define NV_ROUTE_CMD_ROUTE_TABLE0_RFUN4_RANDOM 0x00000002 /* RW--V */
#define NV_ROUTE_CMD_ROUTE_TABLE0_RFUN4_ALTERNATE 0x00000003 /* RW--V */
#define NV_ROUTE_CMD_ROUTE_TABLE0_RFUN5 21:20 /* RWEVF */
#define NV_ROUTE_CMD_ROUTE_TABLE0_RFUN5_SPRAY 0x00000000 /* RWE-V */
#define NV_ROUTE_CMD_ROUTE_TABLE0_RFUN5_RESERVED 0x00000001 /* RW--V */
#define NV_ROUTE_CMD_ROUTE_TABLE0_RFUN5_RANDOM 0x00000002 /* RW--V */
#define NV_ROUTE_CMD_ROUTE_TABLE0_RFUN5_ALTERNATE 0x00000003 /* RW--V */
#define NV_ROUTE_CMD_ROUTE_TABLE0_RFUN6 25:24 /* RWEVF */
#define NV_ROUTE_CMD_ROUTE_TABLE0_RFUN6_SPRAY 0x00000000 /* RWE-V */
#define NV_ROUTE_CMD_ROUTE_TABLE0_RFUN6_RESERVED 0x00000001 /* RW--V */
#define NV_ROUTE_CMD_ROUTE_TABLE0_RFUN6_RANDOM 0x00000002 /* RW--V */
#define NV_ROUTE_CMD_ROUTE_TABLE0_RFUN6_ALTERNATE 0x00000003 /* RW--V */
#define NV_ROUTE_CMD_ROUTE_TABLE0_RFUN7 29:28 /* RWEVF */
#define NV_ROUTE_CMD_ROUTE_TABLE0_RFUN7_SPRAY 0x00000000 /* RWE-V */
#define NV_ROUTE_CMD_ROUTE_TABLE0_RFUN7_RESERVED 0x00000001 /* RW--V */
#define NV_ROUTE_CMD_ROUTE_TABLE0_RFUN7_RANDOM 0x00000002 /* RW--V */
#define NV_ROUTE_CMD_ROUTE_TABLE0_RFUN7_ALTERNATE 0x00000003 /* RW--V */
#define NV_ROUTE_CMD_ROUTE_TABLE1 0x000050a4 /* RW-4R */
#define NV_ROUTE_CMD_ROUTE_TABLE1_RFUN8 1:0 /* RWEVF */
#define NV_ROUTE_CMD_ROUTE_TABLE1_RFUN8_SPRAY 0x00000000 /* RWE-V */
#define NV_ROUTE_CMD_ROUTE_TABLE1_RFUN8_RESERVED 0x00000001 /* RW--V */
#define NV_ROUTE_CMD_ROUTE_TABLE1_RFUN8_RANDOM 0x00000002 /* RW--V */
#define NV_ROUTE_CMD_ROUTE_TABLE1_RFUN8_ALTERNATE 0x00000003 /* RW--V */
#define NV_ROUTE_CMD_ROUTE_TABLE1_RFUN9 5:4 /* RWEVF */
#define NV_ROUTE_CMD_ROUTE_TABLE1_RFUN9_SPRAY 0x00000000 /* RWE-V */
#define NV_ROUTE_CMD_ROUTE_TABLE1_RFUN9_RESERVED 0x00000001 /* RW--V */
#define NV_ROUTE_CMD_ROUTE_TABLE1_RFUN9_RANDOM 0x00000002 /* RW--V */
#define NV_ROUTE_CMD_ROUTE_TABLE1_RFUN9_ALTERNATE 0x00000003 /* RW--V */
#define NV_ROUTE_CMD_ROUTE_TABLE1_RFUN10 9:8 /* RWEVF */
#define NV_ROUTE_CMD_ROUTE_TABLE1_RFUN10_SPRAY 0x00000000 /* RWE-V */
#define NV_ROUTE_CMD_ROUTE_TABLE1_RFUN10_RESERVED 0x00000001 /* RW--V */
#define NV_ROUTE_CMD_ROUTE_TABLE1_RFUN10_RANDOM 0x00000002 /* RW--V */
#define NV_ROUTE_CMD_ROUTE_TABLE1_RFUN10_ALTERNATE 0x00000003 /* RW--V */
#define NV_ROUTE_CMD_ROUTE_TABLE1_RFUN11 13:12 /* RWEVF */
#define NV_ROUTE_CMD_ROUTE_TABLE1_RFUN11_SPRAY 0x00000000 /* RWE-V */
#define NV_ROUTE_CMD_ROUTE_TABLE1_RFUN11_RESERVED 0x00000001 /* RW--V */
#define NV_ROUTE_CMD_ROUTE_TABLE1_RFUN11_RANDOM 0x00000002 /* RW--V */
#define NV_ROUTE_CMD_ROUTE_TABLE1_RFUN11_ALTERNATE 0x00000003 /* RW--V */
#define NV_ROUTE_CMD_ROUTE_TABLE1_RFUN12 17:16 /* RWEVF */
#define NV_ROUTE_CMD_ROUTE_TABLE1_RFUN12_SPRAY 0x00000000 /* RWE-V */
#define NV_ROUTE_CMD_ROUTE_TABLE1_RFUN12_RESERVED 0x00000001 /* RW--V */
#define NV_ROUTE_CMD_ROUTE_TABLE1_RFUN12_RANDOM 0x00000002 /* RW--V */
#define NV_ROUTE_CMD_ROUTE_TABLE1_RFUN12_ALTERNATE 0x00000003 /* RW--V */
#define NV_ROUTE_CMD_ROUTE_TABLE1_RFUN13 21:20 /* RWEVF */
#define NV_ROUTE_CMD_ROUTE_TABLE1_RFUN13_SPRAY 0x00000000 /* RWE-V */
#define NV_ROUTE_CMD_ROUTE_TABLE1_RFUN13_RESERVED 0x00000001 /* RW--V */
#define NV_ROUTE_CMD_ROUTE_TABLE1_RFUN13_RANDOM 0x00000002 /* RW--V */
#define NV_ROUTE_CMD_ROUTE_TABLE1_RFUN13_ALTERNATE 0x00000003 /* RW--V */
#define NV_ROUTE_CMD_ROUTE_TABLE1_RFUN14 25:24 /* RWEVF */
#define NV_ROUTE_CMD_ROUTE_TABLE1_RFUN14_SPRAY 0x00000000 /* RWE-V */
#define NV_ROUTE_CMD_ROUTE_TABLE1_RFUN14_RESERVED 0x00000001 /* RW--V */
#define NV_ROUTE_CMD_ROUTE_TABLE1_RFUN14_RANDOM 0x00000002 /* RW--V */
#define NV_ROUTE_CMD_ROUTE_TABLE1_RFUN14_ALTERNATE 0x00000003 /* RW--V */
#define NV_ROUTE_CMD_ROUTE_TABLE1_RFUN15 29:28 /* RWEVF */
#define NV_ROUTE_CMD_ROUTE_TABLE1_RFUN15_SPRAY 0x00000000 /* RWE-V */
#define NV_ROUTE_CMD_ROUTE_TABLE1_RFUN15_RESERVED 0x00000001 /* RW--V */
#define NV_ROUTE_CMD_ROUTE_TABLE1_RFUN15_RANDOM 0x00000002 /* RW--V */
#define NV_ROUTE_CMD_ROUTE_TABLE1_RFUN15_ALTERNATE 0x00000003 /* RW--V */
#define NV_ROUTE_CMD_ROUTE_TABLE2 0x000050a8 /* RW-4R */
#define NV_ROUTE_CMD_ROUTE_TABLE2_RFUN16 1:0 /* RWEVF */
#define NV_ROUTE_CMD_ROUTE_TABLE2_RFUN16_SPRAY 0x00000000 /* RWE-V */
#define NV_ROUTE_CMD_ROUTE_TABLE2_RFUN16_RESERVED 0x00000001 /* RW--V */
#define NV_ROUTE_CMD_ROUTE_TABLE2_RFUN16_RANDOM 0x00000002 /* RW--V */
#define NV_ROUTE_CMD_ROUTE_TABLE2_RFUN16_ALTERNATE 0x00000003 /* RW--V */
#define NV_ROUTE_CMD_ROUTE_TABLE2_RFUN17 5:4 /* RWEVF */
#define NV_ROUTE_CMD_ROUTE_TABLE2_RFUN17_SPRAY 0x00000000 /* RWE-V */
#define NV_ROUTE_CMD_ROUTE_TABLE2_RFUN17_RESERVED 0x00000001 /* RW--V */
#define NV_ROUTE_CMD_ROUTE_TABLE2_RFUN17_RANDOM 0x00000002 /* RW--V */
#define NV_ROUTE_CMD_ROUTE_TABLE2_RFUN17_ALTERNATE 0x00000003 /* RW--V */
#define NV_ROUTE_CMD_ROUTE_TABLE2_RFUN18 9:8 /* RWEVF */
#define NV_ROUTE_CMD_ROUTE_TABLE2_RFUN18_SPRAY 0x00000000 /* RWE-V */
#define NV_ROUTE_CMD_ROUTE_TABLE2_RFUN18_RESERVED 0x00000001 /* RW--V */
#define NV_ROUTE_CMD_ROUTE_TABLE2_RFUN18_RANDOM 0x00000002 /* RW--V */
#define NV_ROUTE_CMD_ROUTE_TABLE2_RFUN18_ALTERNATE 0x00000003 /* RW--V */
#define NV_ROUTE_CMD_ROUTE_TABLE2_RFUN19 13:12 /* RWEVF */
#define NV_ROUTE_CMD_ROUTE_TABLE2_RFUN19_SPRAY 0x00000000 /* RWE-V */
#define NV_ROUTE_CMD_ROUTE_TABLE2_RFUN19_RESERVED 0x00000001 /* RW--V */
#define NV_ROUTE_CMD_ROUTE_TABLE2_RFUN19_RANDOM 0x00000002 /* RW--V */
#define NV_ROUTE_CMD_ROUTE_TABLE2_RFUN19_ALTERNATE 0x00000003 /* RW--V */
#define NV_ROUTE_CMD_ROUTE_TABLE2_RFUN20 17:16 /* RWEVF */
#define NV_ROUTE_CMD_ROUTE_TABLE2_RFUN20_SPRAY 0x00000000 /* RWE-V */
#define NV_ROUTE_CMD_ROUTE_TABLE2_RFUN20_RESERVED 0x00000001 /* RW--V */
#define NV_ROUTE_CMD_ROUTE_TABLE2_RFUN20_RANDOM 0x00000002 /* RW--V */
#define NV_ROUTE_CMD_ROUTE_TABLE2_RFUN20_ALTERNATE 0x00000003 /* RW--V */
#define NV_ROUTE_CMD_ROUTE_TABLE2_RFUN21 21:20 /* RWEVF */
#define NV_ROUTE_CMD_ROUTE_TABLE2_RFUN21_SPRAY 0x00000000 /* RWE-V */
#define NV_ROUTE_CMD_ROUTE_TABLE2_RFUN21_RESERVED 0x00000001 /* RW--V */
#define NV_ROUTE_CMD_ROUTE_TABLE2_RFUN21_RANDOM 0x00000002 /* RW--V */
#define NV_ROUTE_CMD_ROUTE_TABLE2_RFUN21_ALTERNATE 0x00000003 /* RW--V */
#define NV_ROUTE_CMD_ROUTE_TABLE2_RFUN22 25:24 /* RWEVF */
#define NV_ROUTE_CMD_ROUTE_TABLE2_RFUN22_SPRAY 0x00000000 /* RWE-V */
#define NV_ROUTE_CMD_ROUTE_TABLE2_RFUN22_RESERVED 0x00000001 /* RW--V */
#define NV_ROUTE_CMD_ROUTE_TABLE2_RFUN22_RANDOM 0x00000002 /* RW--V */
#define NV_ROUTE_CMD_ROUTE_TABLE2_RFUN22_ALTERNATE 0x00000003 /* RW--V */
#define NV_ROUTE_CMD_ROUTE_TABLE2_RFUN23 29:28 /* RWEVF */
#define NV_ROUTE_CMD_ROUTE_TABLE2_RFUN23_SPRAY 0x00000000 /* RWE-V */
#define NV_ROUTE_CMD_ROUTE_TABLE2_RFUN23_RESERVED 0x00000001 /* RW--V */
#define NV_ROUTE_CMD_ROUTE_TABLE2_RFUN23_RANDOM 0x00000002 /* RW--V */
#define NV_ROUTE_CMD_ROUTE_TABLE2_RFUN23_ALTERNATE 0x00000003 /* RW--V */
#define NV_ROUTE_CMD_ROUTE_TABLE3 0x000050ac /* RW-4R */
#define NV_ROUTE_CMD_ROUTE_TABLE3_RFUN24 1:0 /* RWEVF */
#define NV_ROUTE_CMD_ROUTE_TABLE3_RFUN24_SPRAY 0x00000000 /* RWE-V */
#define NV_ROUTE_CMD_ROUTE_TABLE3_RFUN24_RESERVED 0x00000001 /* RW--V */
#define NV_ROUTE_CMD_ROUTE_TABLE3_RFUN24_RANDOM 0x00000002 /* RW--V */
#define NV_ROUTE_CMD_ROUTE_TABLE3_RFUN24_ALTERNATE 0x00000003 /* RW--V */
#define NV_ROUTE_CMD_ROUTE_TABLE3_RFUN25 5:4 /* RWEVF */
#define NV_ROUTE_CMD_ROUTE_TABLE3_RFUN25_SPRAY 0x00000000 /* RWE-V */
#define NV_ROUTE_CMD_ROUTE_TABLE3_RFUN25_RESERVED 0x00000001 /* RW--V */
#define NV_ROUTE_CMD_ROUTE_TABLE3_RFUN25_RANDOM 0x00000002 /* RW--V */
#define NV_ROUTE_CMD_ROUTE_TABLE3_RFUN25_ALTERNATE 0x00000003 /* RW--V */
#define NV_ROUTE_CMD_ROUTE_TABLE3_RFUN26 9:8 /* RWEVF */
#define NV_ROUTE_CMD_ROUTE_TABLE3_RFUN26_SPRAY 0x00000000 /* RWE-V */
#define NV_ROUTE_CMD_ROUTE_TABLE3_RFUN26_RESERVED 0x00000001 /* RW--V */
#define NV_ROUTE_CMD_ROUTE_TABLE3_RFUN26_RANDOM 0x00000002 /* RW--V */
#define NV_ROUTE_CMD_ROUTE_TABLE3_RFUN26_ALTERNATE 0x00000003 /* RW--V */
#define NV_ROUTE_CMD_ROUTE_TABLE3_RFUN27 13:12 /* RWEVF */
#define NV_ROUTE_CMD_ROUTE_TABLE3_RFUN27_SPRAY 0x00000000 /* RWE-V */
#define NV_ROUTE_CMD_ROUTE_TABLE3_RFUN27_RESERVED 0x00000001 /* RW--V */
#define NV_ROUTE_CMD_ROUTE_TABLE3_RFUN27_RANDOM 0x00000002 /* RW--V */
#define NV_ROUTE_CMD_ROUTE_TABLE3_RFUN27_ALTERNATE 0x00000003 /* RW--V */
#define NV_ROUTE_CMD_ROUTE_TABLE3_RFUN28 17:16 /* RWEVF */
#define NV_ROUTE_CMD_ROUTE_TABLE3_RFUN28_SPRAY 0x00000000 /* RWE-V */
#define NV_ROUTE_CMD_ROUTE_TABLE3_RFUN28_RESERVED 0x00000001 /* RW--V */
#define NV_ROUTE_CMD_ROUTE_TABLE3_RFUN28_RANDOM 0x00000002 /* RW--V */
#define NV_ROUTE_CMD_ROUTE_TABLE3_RFUN28_ALTERNATE 0x00000003 /* RW--V */
#define NV_ROUTE_CMD_ROUTE_TABLE3_RFUN29 21:20 /* RWEVF */
#define NV_ROUTE_CMD_ROUTE_TABLE3_RFUN29_SPRAY 0x00000000 /* RWE-V */
#define NV_ROUTE_CMD_ROUTE_TABLE3_RFUN29_RESERVED 0x00000001 /* RW--V */
#define NV_ROUTE_CMD_ROUTE_TABLE3_RFUN29_RANDOM 0x00000002 /* RW--V */
#define NV_ROUTE_CMD_ROUTE_TABLE3_RFUN29_ALTERNATE 0x00000003 /* RW--V */
#define NV_ROUTE_CMD_ROUTE_TABLE3_RFUN30 25:24 /* RWEVF */
#define NV_ROUTE_CMD_ROUTE_TABLE3_RFUN30_SPRAY 0x00000000 /* RWE-V */
#define NV_ROUTE_CMD_ROUTE_TABLE3_RFUN30_RESERVED 0x00000001 /* RW--V */
#define NV_ROUTE_CMD_ROUTE_TABLE3_RFUN30_RANDOM 0x00000002 /* RW--V */
#define NV_ROUTE_CMD_ROUTE_TABLE3_RFUN30_ALTERNATE 0x00000003 /* RW--V */
#define NV_ROUTE_CMD_ROUTE_TABLE3_RFUN31 29:28 /* RWEVF */
#define NV_ROUTE_CMD_ROUTE_TABLE3_RFUN31_SPRAY 0x00000000 /* RWE-V */
#define NV_ROUTE_CMD_ROUTE_TABLE3_RFUN31_RESERVED 0x00000001 /* RW--V */
#define NV_ROUTE_CMD_ROUTE_TABLE3_RFUN31_RANDOM 0x00000002 /* RW--V */
#define NV_ROUTE_CMD_ROUTE_TABLE3_RFUN31_ALTERNATE 0x00000003 /* RW--V */
#define NV_ROUTE_ERR_STATUS_0 0x00005400 /* RW-4R */
#define NV_ROUTE_ERR_STATUS_0_ROUTEBUFERR 0:0 /* RWDVF */
#define NV_ROUTE_ERR_STATUS_0_ROUTEBUFERR__ONWRITE "oneToClear" /* */
#define NV_ROUTE_ERR_STATUS_0_ROUTEBUFERR_NONE 0x00000000 /* RWD-V */
#define NV_ROUTE_ERR_STATUS_0_ROUTEBUFERR_CLEAR 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_STATUS_0_NOPORTDEFINEDERR 1:1 /* RWDVF */
#define NV_ROUTE_ERR_STATUS_0_NOPORTDEFINEDERR__ONWRITE "oneToClear" /* */
#define NV_ROUTE_ERR_STATUS_0_NOPORTDEFINEDERR_NONE 0x00000000 /* RWD-V */
#define NV_ROUTE_ERR_STATUS_0_NOPORTDEFINEDERR_CLEAR 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_STATUS_0_INVALIDROUTEPOLICYERR 2:2 /* RWDVF */
#define NV_ROUTE_ERR_STATUS_0_INVALIDROUTEPOLICYERR__ONWRITE "oneToClear" /* */
#define NV_ROUTE_ERR_STATUS_0_INVALIDROUTEPOLICYERR_NONE 0x00000000 /* RWD-V */
#define NV_ROUTE_ERR_STATUS_0_INVALIDROUTEPOLICYERR_CLEAR 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_STATUS_0_GLT_ECC_LIMIT_ERR 3:3 /* RWDVF */
#define NV_ROUTE_ERR_STATUS_0_GLT_ECC_LIMIT_ERR__ONWRITE "oneToClear" /* */
#define NV_ROUTE_ERR_STATUS_0_GLT_ECC_LIMIT_ERR_NONE 0x00000000 /* RWD-V */
#define NV_ROUTE_ERR_STATUS_0_GLT_ECC_LIMIT_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_STATUS_0_GLT_ECC_DBE_ERR 4:4 /* RWDVF */
#define NV_ROUTE_ERR_STATUS_0_GLT_ECC_DBE_ERR__ONWRITE "oneToClear" /* */
#define NV_ROUTE_ERR_STATUS_0_GLT_ECC_DBE_ERR_NONE 0x00000000 /* RWD-V */
#define NV_ROUTE_ERR_STATUS_0_GLT_ECC_DBE_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_STATUS_0_PDCTRLPARERR 6:6 /* RWDVF */
#define NV_ROUTE_ERR_STATUS_0_PDCTRLPARERR__ONWRITE "oneToClear" /* */
#define NV_ROUTE_ERR_STATUS_0_PDCTRLPARERR_NONE 0x00000000 /* RWD-V */
#define NV_ROUTE_ERR_STATUS_0_PDCTRLPARERR_CLEAR 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_STATUS_0_NVS_ECC_LIMIT_ERR 7:7 /* RWDVF */
#define NV_ROUTE_ERR_STATUS_0_NVS_ECC_LIMIT_ERR__ONWRITE "oneToClear" /* */
#define NV_ROUTE_ERR_STATUS_0_NVS_ECC_LIMIT_ERR_NONE 0x00000000 /* RWD-V */
#define NV_ROUTE_ERR_STATUS_0_NVS_ECC_LIMIT_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_STATUS_0_NVS_ECC_DBE_ERR 8:8 /* RWDVF */
#define NV_ROUTE_ERR_STATUS_0_NVS_ECC_DBE_ERR__ONWRITE "oneToClear" /* */
#define NV_ROUTE_ERR_STATUS_0_NVS_ECC_DBE_ERR_NONE 0x00000000 /* RWD-V */
#define NV_ROUTE_ERR_STATUS_0_NVS_ECC_DBE_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_STATUS_0_CDTPARERR 9:9 /* RWDVF */
#define NV_ROUTE_ERR_STATUS_0_CDTPARERR__ONWRITE "oneToClear" /* */
#define NV_ROUTE_ERR_STATUS_0_CDTPARERR_NONE 0x00000000 /* RWD-V */
#define NV_ROUTE_ERR_STATUS_0_CDTPARERR_CLEAR 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_STATUS_0_MCRID_ECC_LIMIT_ERR 10:10 /* RWDVF */
#define NV_ROUTE_ERR_STATUS_0_MCRID_ECC_LIMIT_ERR__ONWRITE "oneToClear" /* */
#define NV_ROUTE_ERR_STATUS_0_MCRID_ECC_LIMIT_ERR_NONE 0x00000000 /* RWD-V */
#define NV_ROUTE_ERR_STATUS_0_MCRID_ECC_LIMIT_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_STATUS_0_MCRID_ECC_DBE_ERR 11:11 /* RWDVF */
#define NV_ROUTE_ERR_STATUS_0_MCRID_ECC_DBE_ERR__ONWRITE "oneToClear" /* */
#define NV_ROUTE_ERR_STATUS_0_MCRID_ECC_DBE_ERR_NONE 0x00000000 /* RWD-V */
#define NV_ROUTE_ERR_STATUS_0_MCRID_ECC_DBE_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_STATUS_0_EXTMCRID_ECC_LIMIT_ERR 12:12 /* RWDVF */
#define NV_ROUTE_ERR_STATUS_0_EXTMCRID_ECC_LIMIT_ERR__ONWRITE "oneToClear" /* */
#define NV_ROUTE_ERR_STATUS_0_EXTMCRID_ECC_LIMIT_ERR_NONE 0x00000000 /* RWD-V */
#define NV_ROUTE_ERR_STATUS_0_EXTMCRID_ECC_LIMIT_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_STATUS_0_EXTMCRID_ECC_DBE_ERR 13:13 /* RWDVF */
#define NV_ROUTE_ERR_STATUS_0_EXTMCRID_ECC_DBE_ERR__ONWRITE "oneToClear" /* */
#define NV_ROUTE_ERR_STATUS_0_EXTMCRID_ECC_DBE_ERR_NONE 0x00000000 /* RWD-V */
#define NV_ROUTE_ERR_STATUS_0_EXTMCRID_ECC_DBE_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_STATUS_0_RAM_ECC_LIMIT_ERR 14:14 /* RWDVF */
#define NV_ROUTE_ERR_STATUS_0_RAM_ECC_LIMIT_ERR__ONWRITE "oneToClear" /* */
#define NV_ROUTE_ERR_STATUS_0_RAM_ECC_LIMIT_ERR_NONE 0x00000000 /* RWD-V */
#define NV_ROUTE_ERR_STATUS_0_RAM_ECC_LIMIT_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_STATUS_0_RAM_ECC_DBE_ERR 15:15 /* RWDVF */
#define NV_ROUTE_ERR_STATUS_0_RAM_ECC_DBE_ERR__ONWRITE "oneToClear" /* */
#define NV_ROUTE_ERR_STATUS_0_RAM_ECC_DBE_ERR_NONE 0x00000000 /* RWD-V */
#define NV_ROUTE_ERR_STATUS_0_RAM_ECC_DBE_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_STATUS_0_INVALID_MCRID_ERR 16:16 /* RWDVF */
#define NV_ROUTE_ERR_STATUS_0_INVALID_MCRID_ERR__ONWRITE "oneToClear" /* */
#define NV_ROUTE_ERR_STATUS_0_INVALID_MCRID_ERR_NONE 0x00000000 /* RWD-V */
#define NV_ROUTE_ERR_STATUS_0_INVALID_MCRID_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_STATUS_0_MC_TRIGGER_ERR 17:17 /* RWDVF */
#define NV_ROUTE_ERR_STATUS_0_MC_TRIGGER_ERR__ONWRITE "oneToClear" /* */
#define NV_ROUTE_ERR_STATUS_0_MC_TRIGGER_ERR_NONE 0x00000000 /* RWD-V */
#define NV_ROUTE_ERR_STATUS_0_MC_TRIGGER_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_LOG_EN_0 0x00005404 /* RW-4R */
#define NV_ROUTE_ERR_LOG_EN_0_ROUTEBUFERR 0:0 /* RWEVF */
#define NV_ROUTE_ERR_LOG_EN_0_ROUTEBUFERR__PROD 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_LOG_EN_0_ROUTEBUFERR_DISABLE 0x00000000 /* RWE-V */
#define NV_ROUTE_ERR_LOG_EN_0_ROUTEBUFERR_ENABLE 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_LOG_EN_0_NOPORTDEFINEDERR 1:1 /* RWEVF */
#define NV_ROUTE_ERR_LOG_EN_0_NOPORTDEFINEDERR__PROD 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_LOG_EN_0_NOPORTDEFINEDERR_DISABLE 0x00000000 /* RWE-V */
#define NV_ROUTE_ERR_LOG_EN_0_NOPORTDEFINEDERR_ENABLE 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_LOG_EN_0_INVALIDROUTEPOLICYERR 2:2 /* RWEVF */
#define NV_ROUTE_ERR_LOG_EN_0_INVALIDROUTEPOLICYERR__PROD 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_LOG_EN_0_INVALIDROUTEPOLICYERR_DISABLE 0x00000000 /* RWE-V */
#define NV_ROUTE_ERR_LOG_EN_0_INVALIDROUTEPOLICYERR_ENABLE 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_LOG_EN_0_GLT_ECC_LIMIT_ERR 3:3 /* RWEVF */
#define NV_ROUTE_ERR_LOG_EN_0_GLT_ECC_LIMIT_ERR__PROD 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_LOG_EN_0_GLT_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_ROUTE_ERR_LOG_EN_0_GLT_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_LOG_EN_0_GLT_ECC_DBE_ERR 4:4 /* RWEVF */
#define NV_ROUTE_ERR_LOG_EN_0_GLT_ECC_DBE_ERR__PROD 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_LOG_EN_0_GLT_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_ROUTE_ERR_LOG_EN_0_GLT_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_LOG_EN_0_PDCTRLPARERR 6:6 /* RWEVF */
#define NV_ROUTE_ERR_LOG_EN_0_PDCTRLPARERR__PROD 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_LOG_EN_0_PDCTRLPARERR_DISABLE 0x00000000 /* RWE-V */
#define NV_ROUTE_ERR_LOG_EN_0_PDCTRLPARERR_ENABLE 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_LOG_EN_0_NVS_ECC_LIMIT_ERR 7:7 /* RWEVF */
#define NV_ROUTE_ERR_LOG_EN_0_NVS_ECC_LIMIT_ERR__PROD 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_LOG_EN_0_NVS_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_ROUTE_ERR_LOG_EN_0_NVS_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_LOG_EN_0_NVS_ECC_DBE_ERR 8:8 /* RWEVF */
#define NV_ROUTE_ERR_LOG_EN_0_NVS_ECC_DBE_ERR__PROD 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_LOG_EN_0_NVS_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_ROUTE_ERR_LOG_EN_0_NVS_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_LOG_EN_0_CDTPARERR 9:9 /* RWEVF */
#define NV_ROUTE_ERR_LOG_EN_0_CDTPARERR__PROD 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_LOG_EN_0_CDTPARERR_DISABLE 0x00000000 /* RWE-V */
#define NV_ROUTE_ERR_LOG_EN_0_CDTPARERR_ENABLE 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_LOG_EN_0_MCRID_ECC_LIMIT_ERR 10:10 /* RWEVF */
#define NV_ROUTE_ERR_LOG_EN_0_MCRID_ECC_LIMIT_ERR__PROD 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_LOG_EN_0_MCRID_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_ROUTE_ERR_LOG_EN_0_MCRID_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_LOG_EN_0_MCRID_ECC_DBE_ERR 11:11 /* RWEVF */
#define NV_ROUTE_ERR_LOG_EN_0_MCRID_ECC_DBE_ERR__PROD 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_LOG_EN_0_MCRID_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_ROUTE_ERR_LOG_EN_0_MCRID_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_LOG_EN_0_EXTMCRID_ECC_LIMIT_ERR 12:12 /* RWEVF */
#define NV_ROUTE_ERR_LOG_EN_0_EXTMCRID_ECC_LIMIT_ERR__PROD 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_LOG_EN_0_EXTMCRID_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_ROUTE_ERR_LOG_EN_0_EXTMCRID_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_LOG_EN_0_EXTMCRID_ECC_DBE_ERR 13:13 /* RWEVF */
#define NV_ROUTE_ERR_LOG_EN_0_EXTMCRID_ECC_DBE_ERR__PROD 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_LOG_EN_0_EXTMCRID_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_ROUTE_ERR_LOG_EN_0_EXTMCRID_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_LOG_EN_0_RAM_ECC_LIMIT_ERR 14:14 /* RWEVF */
#define NV_ROUTE_ERR_LOG_EN_0_RAM_ECC_LIMIT_ERR__PROD 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_LOG_EN_0_RAM_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_ROUTE_ERR_LOG_EN_0_RAM_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_LOG_EN_0_RAM_ECC_DBE_ERR 15:15 /* RWEVF */
#define NV_ROUTE_ERR_LOG_EN_0_RAM_ECC_DBE_ERR__PROD 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_LOG_EN_0_RAM_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_ROUTE_ERR_LOG_EN_0_RAM_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_LOG_EN_0_INVALID_MCRID_ERR 16:16 /* RWEVF */
#define NV_ROUTE_ERR_LOG_EN_0_INVALID_MCRID_ERR__PROD 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_LOG_EN_0_INVALID_MCRID_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_ROUTE_ERR_LOG_EN_0_INVALID_MCRID_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_LOG_EN_0_MC_TRIGGER_ERR 17:17 /* RWEVF */
#define NV_ROUTE_ERR_LOG_EN_0_MC_TRIGGER_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_ROUTE_ERR_LOG_EN_0_MC_TRIGGER_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_FATAL_REPORT_EN_0 0x00005408 /* RW-4R */
#define NV_ROUTE_ERR_FATAL_REPORT_EN_0_ROUTEBUFERR 0:0 /* RWEVF */
#define NV_ROUTE_ERR_FATAL_REPORT_EN_0_ROUTEBUFERR__PROD 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_FATAL_REPORT_EN_0_ROUTEBUFERR_DISABLE 0x00000000 /* RWE-V */
#define NV_ROUTE_ERR_FATAL_REPORT_EN_0_ROUTEBUFERR_ENABLE 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_FATAL_REPORT_EN_0_NOPORTDEFINEDERR 1:1 /* RWEVF */
#define NV_ROUTE_ERR_FATAL_REPORT_EN_0_NOPORTDEFINEDERR_DISABLE 0x00000000 /* RWE-V */
#define NV_ROUTE_ERR_FATAL_REPORT_EN_0_NOPORTDEFINEDERR_ENABLE 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_FATAL_REPORT_EN_0_INVALIDROUTEPOLICYERR 2:2 /* RWEVF */
#define NV_ROUTE_ERR_FATAL_REPORT_EN_0_INVALIDROUTEPOLICYERR_DISABLE 0x00000000 /* RWE-V */
#define NV_ROUTE_ERR_FATAL_REPORT_EN_0_INVALIDROUTEPOLICYERR_ENABLE 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_FATAL_REPORT_EN_0_GLT_ECC_LIMIT_ERR 3:3 /* RWEVF */
#define NV_ROUTE_ERR_FATAL_REPORT_EN_0_GLT_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_ROUTE_ERR_FATAL_REPORT_EN_0_GLT_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_FATAL_REPORT_EN_0_GLT_ECC_DBE_ERR 4:4 /* RWEVF */
#define NV_ROUTE_ERR_FATAL_REPORT_EN_0_GLT_ECC_DBE_ERR__PROD 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_FATAL_REPORT_EN_0_GLT_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_ROUTE_ERR_FATAL_REPORT_EN_0_GLT_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_FATAL_REPORT_EN_0_PDCTRLPARERR 6:6 /* RWEVF */
#define NV_ROUTE_ERR_FATAL_REPORT_EN_0_PDCTRLPARERR__PROD 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_FATAL_REPORT_EN_0_PDCTRLPARERR_DISABLE 0x00000000 /* RWE-V */
#define NV_ROUTE_ERR_FATAL_REPORT_EN_0_PDCTRLPARERR_ENABLE 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_FATAL_REPORT_EN_0_NVS_ECC_LIMIT_ERR 7:7 /* RWEVF */
#define NV_ROUTE_ERR_FATAL_REPORT_EN_0_NVS_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_ROUTE_ERR_FATAL_REPORT_EN_0_NVS_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_FATAL_REPORT_EN_0_NVS_ECC_DBE_ERR 8:8 /* RWEVF */
#define NV_ROUTE_ERR_FATAL_REPORT_EN_0_NVS_ECC_DBE_ERR__PROD 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_FATAL_REPORT_EN_0_NVS_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_ROUTE_ERR_FATAL_REPORT_EN_0_NVS_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_FATAL_REPORT_EN_0_CDTPARERR 9:9 /* RWEVF */
#define NV_ROUTE_ERR_FATAL_REPORT_EN_0_CDTPARERR__PROD 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_FATAL_REPORT_EN_0_CDTPARERR_DISABLE 0x00000000 /* RWE-V */
#define NV_ROUTE_ERR_FATAL_REPORT_EN_0_CDTPARERR_ENABLE 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_FATAL_REPORT_EN_0_MCRID_ECC_LIMIT_ERR 10:10 /* RWEVF */
#define NV_ROUTE_ERR_FATAL_REPORT_EN_0_MCRID_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_ROUTE_ERR_FATAL_REPORT_EN_0_MCRID_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_FATAL_REPORT_EN_0_MCRID_ECC_DBE_ERR 11:11 /* RWEVF */
#define NV_ROUTE_ERR_FATAL_REPORT_EN_0_MCRID_ECC_DBE_ERR__PROD 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_FATAL_REPORT_EN_0_MCRID_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_ROUTE_ERR_FATAL_REPORT_EN_0_MCRID_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_FATAL_REPORT_EN_0_EXTMCRID_ECC_LIMIT_ERR 12:12 /* RWEVF */
#define NV_ROUTE_ERR_FATAL_REPORT_EN_0_EXTMCRID_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_ROUTE_ERR_FATAL_REPORT_EN_0_EXTMCRID_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_FATAL_REPORT_EN_0_EXTMCRID_ECC_DBE_ERR 13:13 /* RWEVF */
#define NV_ROUTE_ERR_FATAL_REPORT_EN_0_EXTMCRID_ECC_DBE_ERR__PROD 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_FATAL_REPORT_EN_0_EXTMCRID_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_ROUTE_ERR_FATAL_REPORT_EN_0_EXTMCRID_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_FATAL_REPORT_EN_0_RAM_ECC_LIMIT_ERR 14:14 /* RWEVF */
#define NV_ROUTE_ERR_FATAL_REPORT_EN_0_RAM_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_ROUTE_ERR_FATAL_REPORT_EN_0_RAM_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_FATAL_REPORT_EN_0_RAM_ECC_DBE_ERR 15:15 /* RWEVF */
#define NV_ROUTE_ERR_FATAL_REPORT_EN_0_RAM_ECC_DBE_ERR__PROD 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_FATAL_REPORT_EN_0_RAM_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_ROUTE_ERR_FATAL_REPORT_EN_0_RAM_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_FATAL_REPORT_EN_0_INVALID_MCRID_ERR 16:16 /* RWEVF */
#define NV_ROUTE_ERR_FATAL_REPORT_EN_0_INVALID_MCRID_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_ROUTE_ERR_FATAL_REPORT_EN_0_INVALID_MCRID_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_FATAL_REPORT_EN_0_MC_TRIGGER_ERR 17:17 /* RWEVF */
#define NV_ROUTE_ERR_FATAL_REPORT_EN_0_MC_TRIGGER_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_ROUTE_ERR_FATAL_REPORT_EN_0_MC_TRIGGER_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_NON_FATAL_REPORT_EN_0 0x0000540c /* RW-4R */
#define NV_ROUTE_ERR_NON_FATAL_REPORT_EN_0_ROUTEBUFERR 0:0 /* RWEVF */
#define NV_ROUTE_ERR_NON_FATAL_REPORT_EN_0_ROUTEBUFERR_DISABLE 0x00000000 /* RWE-V */
#define NV_ROUTE_ERR_NON_FATAL_REPORT_EN_0_ROUTEBUFERR_ENABLE 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_NON_FATAL_REPORT_EN_0_NOPORTDEFINEDERR 1:1 /* RWEVF */
#define NV_ROUTE_ERR_NON_FATAL_REPORT_EN_0_NOPORTDEFINEDERR__PROD 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_NON_FATAL_REPORT_EN_0_NOPORTDEFINEDERR_DISABLE 0x00000000 /* RWE-V */
#define NV_ROUTE_ERR_NON_FATAL_REPORT_EN_0_NOPORTDEFINEDERR_ENABLE 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_NON_FATAL_REPORT_EN_0_INVALIDROUTEPOLICYERR 2:2 /* RWEVF */
#define NV_ROUTE_ERR_NON_FATAL_REPORT_EN_0_INVALIDROUTEPOLICYERR__PROD 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_NON_FATAL_REPORT_EN_0_INVALIDROUTEPOLICYERR_DISABLE 0x00000000 /* RWE-V */
#define NV_ROUTE_ERR_NON_FATAL_REPORT_EN_0_INVALIDROUTEPOLICYERR_ENABLE 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_NON_FATAL_REPORT_EN_0_GLT_ECC_LIMIT_ERR 3:3 /* RWEVF */
#define NV_ROUTE_ERR_NON_FATAL_REPORT_EN_0_GLT_ECC_LIMIT_ERR__PROD 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_NON_FATAL_REPORT_EN_0_GLT_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_ROUTE_ERR_NON_FATAL_REPORT_EN_0_GLT_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_NON_FATAL_REPORT_EN_0_GLT_ECC_DBE_ERR 4:4 /* RWEVF */
#define NV_ROUTE_ERR_NON_FATAL_REPORT_EN_0_GLT_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_ROUTE_ERR_NON_FATAL_REPORT_EN_0_GLT_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_NON_FATAL_REPORT_EN_0_PDCTRLPARERR 6:6 /* RWEVF */
#define NV_ROUTE_ERR_NON_FATAL_REPORT_EN_0_PDCTRLPARERR_DISABLE 0x00000000 /* RWE-V */
#define NV_ROUTE_ERR_NON_FATAL_REPORT_EN_0_PDCTRLPARERR_ENABLE 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_NON_FATAL_REPORT_EN_0_NVS_ECC_LIMIT_ERR 7:7 /* RWEVF */
#define NV_ROUTE_ERR_NON_FATAL_REPORT_EN_0_NVS_ECC_LIMIT_ERR__PROD 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_NON_FATAL_REPORT_EN_0_NVS_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_ROUTE_ERR_NON_FATAL_REPORT_EN_0_NVS_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_NON_FATAL_REPORT_EN_0_NVS_ECC_DBE_ERR 8:8 /* RWEVF */
#define NV_ROUTE_ERR_NON_FATAL_REPORT_EN_0_NVS_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_ROUTE_ERR_NON_FATAL_REPORT_EN_0_NVS_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_NON_FATAL_REPORT_EN_0_CDTPARERR 9:9 /* RWEVF */
#define NV_ROUTE_ERR_NON_FATAL_REPORT_EN_0_CDTPARERR_DISABLE 0x00000000 /* RWE-V */
#define NV_ROUTE_ERR_NON_FATAL_REPORT_EN_0_CDTPARERR_ENABLE 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_NON_FATAL_REPORT_EN_0_MCRID_ECC_LIMIT_ERR 10:10 /* RWEVF */
#define NV_ROUTE_ERR_NON_FATAL_REPORT_EN_0_MCRID_ECC_LIMIT_ERR__PROD 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_NON_FATAL_REPORT_EN_0_MCRID_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_ROUTE_ERR_NON_FATAL_REPORT_EN_0_MCRID_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_NON_FATAL_REPORT_EN_0_MCRID_ECC_DBE_ERR 11:11 /* RWEVF */
#define NV_ROUTE_ERR_NON_FATAL_REPORT_EN_0_MCRID_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_ROUTE_ERR_NON_FATAL_REPORT_EN_0_MCRID_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_NON_FATAL_REPORT_EN_0_EXTMCRID_ECC_LIMIT_ERR 12:12 /* RWEVF */
#define NV_ROUTE_ERR_NON_FATAL_REPORT_EN_0_EXTMCRID_ECC_LIMIT_ERR__PROD 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_NON_FATAL_REPORT_EN_0_EXTMCRID_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_ROUTE_ERR_NON_FATAL_REPORT_EN_0_EXTMCRID_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_NON_FATAL_REPORT_EN_0_EXTMCRID_ECC_DBE_ERR 13:13 /* RWEVF */
#define NV_ROUTE_ERR_NON_FATAL_REPORT_EN_0_EXTMCRID_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_ROUTE_ERR_NON_FATAL_REPORT_EN_0_EXTMCRID_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_NON_FATAL_REPORT_EN_0_RAM_ECC_LIMIT_ERR 14:14 /* RWEVF */
#define NV_ROUTE_ERR_NON_FATAL_REPORT_EN_0_RAM_ECC_LIMIT_ERR__PROD 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_NON_FATAL_REPORT_EN_0_RAM_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_ROUTE_ERR_NON_FATAL_REPORT_EN_0_RAM_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_NON_FATAL_REPORT_EN_0_RAM_ECC_DBE_ERR 15:15 /* RWEVF */
#define NV_ROUTE_ERR_NON_FATAL_REPORT_EN_0_RAM_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_ROUTE_ERR_NON_FATAL_REPORT_EN_0_RAM_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_NON_FATAL_REPORT_EN_0_INVALID_MCRID_ERR 16:16 /* RWEVF */
#define NV_ROUTE_ERR_NON_FATAL_REPORT_EN_0_INVALID_MCRID_ERR__PROD 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_NON_FATAL_REPORT_EN_0_INVALID_MCRID_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_ROUTE_ERR_NON_FATAL_REPORT_EN_0_INVALID_MCRID_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_NON_FATAL_REPORT_EN_0_MC_TRIGGER_ERR 17:17 /* RWEVF */
#define NV_ROUTE_ERR_NON_FATAL_REPORT_EN_0_MC_TRIGGER_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_ROUTE_ERR_NON_FATAL_REPORT_EN_0_MC_TRIGGER_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_CORRECTABLE_REPORT_EN_0 0x00005410 /* RW-4R */
#define NV_ROUTE_ERR_CONTAIN_EN_0 0x00005414 /* RW-4R */
#define NV_ROUTE_ERR_CONTAIN_EN_0_ROUTEBUFERR 0:0 /* RWEVF */
#define NV_ROUTE_ERR_CONTAIN_EN_0_ROUTEBUFERR__PROD 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_CONTAIN_EN_0_ROUTEBUFERR_DISABLE 0x00000000 /* RWE-V */
#define NV_ROUTE_ERR_CONTAIN_EN_0_ROUTEBUFERR_ENABLE 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_CONTAIN_EN_0_NOPORTDEFINEDERR 1:1 /* RWEVF */
#define NV_ROUTE_ERR_CONTAIN_EN_0_NOPORTDEFINEDERR_DISABLE 0x00000000 /* RWE-V */
#define NV_ROUTE_ERR_CONTAIN_EN_0_NOPORTDEFINEDERR_ENABLE 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_CONTAIN_EN_0_INVALIDROUTEPOLICYERR 2:2 /* RWEVF */
#define NV_ROUTE_ERR_CONTAIN_EN_0_INVALIDROUTEPOLICYERR_DISABLE 0x00000000 /* RWE-V */
#define NV_ROUTE_ERR_CONTAIN_EN_0_INVALIDROUTEPOLICYERR_ENABLE 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_CONTAIN_EN_0_GLT_ECC_LIMIT_ERR 3:3 /* RWEVF */
#define NV_ROUTE_ERR_CONTAIN_EN_0_GLT_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_ROUTE_ERR_CONTAIN_EN_0_GLT_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_CONTAIN_EN_0_GLT_ECC_DBE_ERR 4:4 /* RWEVF */
#define NV_ROUTE_ERR_CONTAIN_EN_0_GLT_ECC_DBE_ERR__PROD 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_CONTAIN_EN_0_GLT_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_ROUTE_ERR_CONTAIN_EN_0_GLT_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_CONTAIN_EN_0_PDCTRLPARERR 6:6 /* RWEVF */
#define NV_ROUTE_ERR_CONTAIN_EN_0_PDCTRLPARERR__PROD 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_CONTAIN_EN_0_PDCTRLPARERR_DISABLE 0x00000000 /* RWE-V */
#define NV_ROUTE_ERR_CONTAIN_EN_0_PDCTRLPARERR_ENABLE 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_CONTAIN_EN_0_NVS_ECC_LIMIT_ERR 7:7 /* RWEVF */
#define NV_ROUTE_ERR_CONTAIN_EN_0_NVS_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_ROUTE_ERR_CONTAIN_EN_0_NVS_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_CONTAIN_EN_0_NVS_ECC_DBE_ERR 8:8 /* RWEVF */
#define NV_ROUTE_ERR_CONTAIN_EN_0_NVS_ECC_DBE_ERR__PROD 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_CONTAIN_EN_0_NVS_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_ROUTE_ERR_CONTAIN_EN_0_NVS_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_CONTAIN_EN_0_CDTPARERR 9:9 /* RWEVF */
#define NV_ROUTE_ERR_CONTAIN_EN_0_CDTPARERR__PROD 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_CONTAIN_EN_0_CDTPARERR_DISABLE 0x00000000 /* RWE-V */
#define NV_ROUTE_ERR_CONTAIN_EN_0_CDTPARERR_ENABLE 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_CONTAIN_EN_0_MCRID_ECC_LIMIT_ERR 10:10 /* RWEVF */
#define NV_ROUTE_ERR_CONTAIN_EN_0_MCRID_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_ROUTE_ERR_CONTAIN_EN_0_MCRID_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_CONTAIN_EN_0_MCRID_ECC_DBE_ERR 11:11 /* RWEVF */
#define NV_ROUTE_ERR_CONTAIN_EN_0_MCRID_ECC_DBE_ERR__PROD 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_CONTAIN_EN_0_MCRID_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_ROUTE_ERR_CONTAIN_EN_0_MCRID_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_CONTAIN_EN_0_EXTMCRID_ECC_LIMIT_ERR 12:12 /* RWEVF */
#define NV_ROUTE_ERR_CONTAIN_EN_0_EXTMCRID_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_ROUTE_ERR_CONTAIN_EN_0_EXTMCRID_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_CONTAIN_EN_0_EXTMCRID_ECC_DBE_ERR 13:13 /* RWEVF */
#define NV_ROUTE_ERR_CONTAIN_EN_0_EXTMCRID_ECC_DBE_ERR__PROD 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_CONTAIN_EN_0_EXTMCRID_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_ROUTE_ERR_CONTAIN_EN_0_EXTMCRID_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_CONTAIN_EN_0_RAM_ECC_LIMIT_ERR 14:14 /* RWEVF */
#define NV_ROUTE_ERR_CONTAIN_EN_0_RAM_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_ROUTE_ERR_CONTAIN_EN_0_RAM_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_CONTAIN_EN_0_RAM_ECC_DBE_ERR 15:15 /* RWEVF */
#define NV_ROUTE_ERR_CONTAIN_EN_0_RAM_ECC_DBE_ERR__PROD 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_CONTAIN_EN_0_RAM_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_ROUTE_ERR_CONTAIN_EN_0_RAM_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_CONTAIN_EN_0_INVALID_MCRID_ERR 16:16 /* RWEVF */
#define NV_ROUTE_ERR_CONTAIN_EN_0_INVALID_MCRID_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_ROUTE_ERR_CONTAIN_EN_0_INVALID_MCRID_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_CONTAIN_EN_0_MC_TRIGGER_ERR 17:17 /* RWEVF */
#define NV_ROUTE_ERR_CONTAIN_EN_0_MC_TRIGGER_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_ROUTE_ERR_CONTAIN_EN_0_MC_TRIGGER_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_FIRST_0 0x0000541c /* RW-4R */
#define NV_ROUTE_ERR_FIRST_0_ROUTEBUFERR 0:0 /* RWDVF */
#define NV_ROUTE_ERR_FIRST_0_ROUTEBUFERR__ONWRITE "oneToClear" /* */
#define NV_ROUTE_ERR_FIRST_0_ROUTEBUFERR_NONE 0x00000000 /* RWD-V */
#define NV_ROUTE_ERR_FIRST_0_ROUTEBUFERR_CLEAR 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_FIRST_0_NOPORTDEFINEDERR 1:1 /* RWDVF */
#define NV_ROUTE_ERR_FIRST_0_NOPORTDEFINEDERR__ONWRITE "oneToClear" /* */
#define NV_ROUTE_ERR_FIRST_0_NOPORTDEFINEDERR_NONE 0x00000000 /* RWD-V */
#define NV_ROUTE_ERR_FIRST_0_NOPORTDEFINEDERR_CLEAR 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_FIRST_0_INVALIDROUTEPOLICYERR 2:2 /* RWDVF */
#define NV_ROUTE_ERR_FIRST_0_INVALIDROUTEPOLICYERR__ONWRITE "oneToClear" /* */
#define NV_ROUTE_ERR_FIRST_0_INVALIDROUTEPOLICYERR_NONE 0x00000000 /* RWD-V */
#define NV_ROUTE_ERR_FIRST_0_INVALIDROUTEPOLICYERR_CLEAR 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_FIRST_0_GLT_ECC_LIMIT_ERR 3:3 /* RWDVF */
#define NV_ROUTE_ERR_FIRST_0_GLT_ECC_LIMIT_ERR__ONWRITE "oneToClear" /* */
#define NV_ROUTE_ERR_FIRST_0_GLT_ECC_LIMIT_ERR_NONE 0x00000000 /* RWD-V */
#define NV_ROUTE_ERR_FIRST_0_GLT_ECC_LIMIT_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_FIRST_0_GLT_ECC_DBE_ERR 4:4 /* RWDVF */
#define NV_ROUTE_ERR_FIRST_0_GLT_ECC_DBE_ERR__ONWRITE "oneToClear" /* */
#define NV_ROUTE_ERR_FIRST_0_GLT_ECC_DBE_ERR_NONE 0x00000000 /* RWD-V */
#define NV_ROUTE_ERR_FIRST_0_GLT_ECC_DBE_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_FIRST_0_PDCTRLPARERR 6:6 /* RWDVF */
#define NV_ROUTE_ERR_FIRST_0_PDCTRLPARERR__ONWRITE "oneToClear" /* */
#define NV_ROUTE_ERR_FIRST_0_PDCTRLPARERR_NONE 0x00000000 /* RWD-V */
#define NV_ROUTE_ERR_FIRST_0_PDCTRLPARERR_CLEAR 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_FIRST_0_NVS_ECC_LIMIT_ERR 7:7 /* RWDVF */
#define NV_ROUTE_ERR_FIRST_0_NVS_ECC_LIMIT_ERR__ONWRITE "oneToClear" /* */
#define NV_ROUTE_ERR_FIRST_0_NVS_ECC_LIMIT_ERR_NONE 0x00000000 /* RWD-V */
#define NV_ROUTE_ERR_FIRST_0_NVS_ECC_LIMIT_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_FIRST_0_NVS_ECC_DBE_ERR 8:8 /* RWDVF */
#define NV_ROUTE_ERR_FIRST_0_NVS_ECC_DBE_ERR__ONWRITE "oneToClear" /* */
#define NV_ROUTE_ERR_FIRST_0_NVS_ECC_DBE_ERR_NONE 0x00000000 /* RWD-V */
#define NV_ROUTE_ERR_FIRST_0_NVS_ECC_DBE_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_FIRST_0_CDTPARERR 9:9 /* RWDVF */
#define NV_ROUTE_ERR_FIRST_0_CDTPARERR__ONWRITE "oneToClear" /* */
#define NV_ROUTE_ERR_FIRST_0_CDTPARERR_NONE 0x00000000 /* RWD-V */
#define NV_ROUTE_ERR_FIRST_0_CDTPARERR_CLEAR 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_FIRST_0_MCRID_ECC_LIMIT_ERR 10:10 /* RWDVF */
#define NV_ROUTE_ERR_FIRST_0_MCRID_ECC_LIMIT_ERR__ONWRITE "oneToClear" /* */
#define NV_ROUTE_ERR_FIRST_0_MCRID_ECC_LIMIT_ERR_NONE 0x00000000 /* RWD-V */
#define NV_ROUTE_ERR_FIRST_0_MCRID_ECC_LIMIT_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_FIRST_0_MCRID_ECC_DBE_ERR 11:11 /* RWDVF */
#define NV_ROUTE_ERR_FIRST_0_MCRID_ECC_DBE_ERR__ONWRITE "oneToClear" /* */
#define NV_ROUTE_ERR_FIRST_0_MCRID_ECC_DBE_ERR_NONE 0x00000000 /* RWD-V */
#define NV_ROUTE_ERR_FIRST_0_MCRID_ECC_DBE_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_FIRST_0_EXTMCRID_ECC_LIMIT_ERR 12:12 /* RWDVF */
#define NV_ROUTE_ERR_FIRST_0_EXTMCRID_ECC_LIMIT_ERR__ONWRITE "oneToClear" /* */
#define NV_ROUTE_ERR_FIRST_0_EXTMCRID_ECC_LIMIT_ERR_NONE 0x00000000 /* RWD-V */
#define NV_ROUTE_ERR_FIRST_0_EXTMCRID_ECC_LIMIT_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_FIRST_0_EXTMCRID_ECC_DBE_ERR 13:13 /* RWDVF */
#define NV_ROUTE_ERR_FIRST_0_EXTMCRID_ECC_DBE_ERR__ONWRITE "oneToClear" /* */
#define NV_ROUTE_ERR_FIRST_0_EXTMCRID_ECC_DBE_ERR_NONE 0x00000000 /* RWD-V */
#define NV_ROUTE_ERR_FIRST_0_EXTMCRID_ECC_DBE_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_FIRST_0_RAM_ECC_LIMIT_ERR 14:14 /* RWDVF */
#define NV_ROUTE_ERR_FIRST_0_RAM_ECC_LIMIT_ERR__ONWRITE "oneToClear" /* */
#define NV_ROUTE_ERR_FIRST_0_RAM_ECC_LIMIT_ERR_NONE 0x00000000 /* RWD-V */
#define NV_ROUTE_ERR_FIRST_0_RAM_ECC_LIMIT_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_FIRST_0_RAM_ECC_DBE_ERR 15:15 /* RWDVF */
#define NV_ROUTE_ERR_FIRST_0_RAM_ECC_DBE_ERR__ONWRITE "oneToClear" /* */
#define NV_ROUTE_ERR_FIRST_0_RAM_ECC_DBE_ERR_NONE 0x00000000 /* RWD-V */
#define NV_ROUTE_ERR_FIRST_0_RAM_ECC_DBE_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_FIRST_0_INVALID_MCRID_ERR 16:16 /* RWDVF */
#define NV_ROUTE_ERR_FIRST_0_INVALID_MCRID_ERR__ONWRITE "oneToClear" /* */
#define NV_ROUTE_ERR_FIRST_0_INVALID_MCRID_ERR_NONE 0x00000000 /* RWD-V */
#define NV_ROUTE_ERR_FIRST_0_INVALID_MCRID_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_FIRST_0_MC_TRIGGER_ERR 17:17 /* RWDVF */
#define NV_ROUTE_ERR_FIRST_0_MC_TRIGGER_ERR__ONWRITE "oneToClear" /* */
#define NV_ROUTE_ERR_FIRST_0_MC_TRIGGER_ERR_NONE 0x00000000 /* RWD-V */
#define NV_ROUTE_ERR_FIRST_0_MC_TRIGGER_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_HEADER_LOG_4 0x00005430 /* R--4R */
#define NV_ROUTE_ERR_HEADER_LOG_4_DW 31:0 /* R-DVF */
#define NV_ROUTE_ERR_HEADER_LOG_4_DW_INIT 0x00000000 /* R-D-V */
#define NV_ROUTE_ERR_HEADER_LOG_5 0x00005434 /* R--4R */
#define NV_ROUTE_ERR_HEADER_LOG_5_DW 31:0 /* R-DVF */
#define NV_ROUTE_ERR_HEADER_LOG_5_DW_INIT 0x00000000 /* R-D-V */
#define NV_ROUTE_ERR_HEADER_LOG_6 0x00005438 /* R--4R */
#define NV_ROUTE_ERR_HEADER_LOG_6_DW 31:0 /* R-DVF */
#define NV_ROUTE_ERR_HEADER_LOG_6_DW_INIT 0x00000000 /* R-D-V */
#define NV_ROUTE_ERR_HEADER_LOG_7 0x0000543c /* R--4R */
#define NV_ROUTE_ERR_HEADER_LOG_7_DW 31:0 /* R-DVF */
#define NV_ROUTE_ERR_HEADER_LOG_7_DW_INIT 0x00000000 /* R-D-V */
#define NV_ROUTE_ERR_HEADER_LOG_8 0x00005440 /* R--4R */
#define NV_ROUTE_ERR_HEADER_LOG_8_DW 31:0 /* R-DVF */
#define NV_ROUTE_ERR_HEADER_LOG_8_DW_INIT 0x00000000 /* R-D-V */
#define NV_ROUTE_ERR_HEADER_LOG_9 0x00005444 /* R--4R */
#define NV_ROUTE_ERR_HEADER_LOG_9_DW 31:0 /* R-DVF */
#define NV_ROUTE_ERR_HEADER_LOG_9_DW_INIT 0x00000000 /* R-D-V */
#define NV_ROUTE_ERR_HEADER_LOG_10 0x00005448 /* R--4R */
#define NV_ROUTE_ERR_HEADER_LOG_10_DW 31:0 /* R-DVF */
#define NV_ROUTE_ERR_HEADER_LOG_10_DW_INIT 0x00000000 /* R-D-V */
#define NV_ROUTE_ERR_HEADER_LOG_VALID 0x0000544c /* R--4R */
#define NV_ROUTE_ERR_HEADER_LOG_VALID_HEADERVALID0 0:0 /* R-DVF */
#define NV_ROUTE_ERR_HEADER_LOG_VALID_HEADERVALID0_INVALID 0x00000000 /* R-D-V */
#define NV_ROUTE_ERR_HEADER_LOG_VALID_HEADERVALID0_VALID 0x00000001 /* R---V */
#define NV_ROUTE_ERR_TIMESTAMP_LOG 0x00005450 /* R--4R */
#define NV_ROUTE_ERR_TIMESTAMP_LOG_TIMESTAMP 23:0 /* R-DVF */
#define NV_ROUTE_ERR_TIMESTAMP_LOG_TIMESTAMP_INIT 0x00000000 /* R-D-V */
#define NV_ROUTE_ERR_MISC_LOG_0 0x00005454 /* R--4R */
#define NV_ROUTE_ERR_MISC_LOG_0_SPORT 5:0 /* R-DVF */
#define NV_ROUTE_ERR_MISC_LOG_0_SPORT_INIT 0x00000000 /* R-D-V */
#define NV_ROUTE_ERR_MISC_LOG_0_ENCODEDVC 10:8 /* R-DVF */
#define NV_ROUTE_ERR_MISC_LOG_0_ENCODEDVC_INIT 0x00000000 /* R-D-V */
#define NV_ROUTE_ERR_ECC_CTRL 0x00005470 /* RW-4R */
#define NV_ROUTE_ERR_ECC_CTRL_GLT_ECC_ENABLE 0:0 /* RWEVF */
#define NV_ROUTE_ERR_ECC_CTRL_GLT_ECC_ENABLE_ENABLE 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_ECC_CTRL_GLT_ECC_ENABLE_DISABLE 0x00000000 /* RWE-V */
#define NV_ROUTE_ERR_ECC_CTRL_GLT_ECC_ENABLE__PROD 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_ECC_CTRL_NVS_ECC_ENABLE 2:2 /* RWEVF */
#define NV_ROUTE_ERR_ECC_CTRL_NVS_ECC_ENABLE_ENABLE 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_ECC_CTRL_NVS_ECC_ENABLE_DISABLE 0x00000000 /* RWE-V */
#define NV_ROUTE_ERR_ECC_CTRL_NVS_ECC_ENABLE__PROD 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_ECC_CTRL_MCRID_ECC_ENABLE 3:3 /* RWEVF */
#define NV_ROUTE_ERR_ECC_CTRL_MCRID_ECC_ENABLE_ENABLE 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_ECC_CTRL_MCRID_ECC_ENABLE_DISABLE 0x00000000 /* RWE-V */
#define NV_ROUTE_ERR_ECC_CTRL_MCRID_ECC_ENABLE__PROD 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_ECC_CTRL_EXTMCRID_ECC_ENABLE 4:4 /* RWEVF */
#define NV_ROUTE_ERR_ECC_CTRL_EXTMCRID_ECC_ENABLE_ENABLE 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_ECC_CTRL_EXTMCRID_ECC_ENABLE_DISABLE 0x00000000 /* RWE-V */
#define NV_ROUTE_ERR_ECC_CTRL_EXTMCRID_ECC_ENABLE__PROD 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_ECC_CTRL_ECCWRITEBACKENBGLT 5:5 /* RWEVF */
#define NV_ROUTE_ERR_ECC_CTRL_ECCWRITEBACKENBGLT_DISABLE 0x00000000 /* RW--V */
#define NV_ROUTE_ERR_ECC_CTRL_ECCWRITEBACKENBGLT_ENABLE 0x00000001 /* RWE-V */
#define NV_ROUTE_ERR_ECC_CTRL_ECCWRITEBACKMCRIDENB 6:6 /* RWEVF */
#define NV_ROUTE_ERR_ECC_CTRL_ECCWRITEBACKMCRIDENB_DISABLE 0x00000000 /* RW--V */
#define NV_ROUTE_ERR_ECC_CTRL_ECCWRITEBACKMCRIDENB_ENABLE 0x00000001 /* RWE-V */
#define NV_ROUTE_ERR_ECC_CTRL_ECCWRITEBACKEXTMCRIDENB 7:7 /* RWEVF */
#define NV_ROUTE_ERR_ECC_CTRL_ECCWRITEBACKEXTMCRIDENB_DISABLE 0x00000000 /* RW--V */
#define NV_ROUTE_ERR_ECC_CTRL_ECCWRITEBACKEXTMCRIDENB_ENABLE 0x00000001 /* RWE-V */
#define NV_ROUTE_ERR_ECC_CTRL_RAM_ECC_ENABLE 8:8 /* RWEVF */
#define NV_ROUTE_ERR_ECC_CTRL_RAM_ECC_ENABLE_ENABLE 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_ECC_CTRL_RAM_ECC_ENABLE_DISABLE 0x00000000 /* RWE-V */
#define NV_ROUTE_ERR_ECC_CTRL_RAM_ECC_ENABLE__PROD 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_GLT_ECC_ERROR_COUNTER 0x00005480 /* RW-4R */
#define NV_ROUTE_ERR_GLT_ECC_ERROR_COUNTER_ERROR_COUNT 23:0 /* RWDVF */
#define NV_ROUTE_ERR_GLT_ECC_ERROR_COUNTER_ERROR_COUNT_INIT 0x00000000 /* RWD-V */
#define NV_ROUTE_ERR_GLT_ECC_ERROR_COUNTER_LIMIT 0x00005484 /* RW-4R */
#define NV_ROUTE_ERR_GLT_ECC_ERROR_COUNTER_LIMIT_ERROR_LIMIT 23:0 /* RWDVF */
#define NV_ROUTE_ERR_GLT_ECC_ERROR_COUNTER_LIMIT_ERROR_LIMIT_INIT 0x00ffffff /* RWD-V */
#define NV_ROUTE_ERR_GLT_ECC_ERROR_ADDRESS 0x00005488 /* R--4R */
#define NV_ROUTE_ERR_GLT_ECC_ERROR_ADDRESS_ERROR_ADDRESS 7:0 /* R-DVF */
#define NV_ROUTE_ERR_GLT_ECC_ERROR_ADDRESS_ERROR_ADDRESS_INIT 0x00000000 /* R-D-V */
#define NV_ROUTE_ERR_GLT_ECC_ERROR_ADDRESS_VALID 0x0000548c /* R--4R */
#define NV_ROUTE_ERR_GLT_ECC_ERROR_ADDRESS_VALID_VALID 0:0 /* R-DVF */
#define NV_ROUTE_ERR_GLT_ECC_ERROR_ADDRESS_VALID_VALID_INVALID 0x00000000 /* R-D-V */
#define NV_ROUTE_ERR_GLT_ECC_ERROR_ADDRESS_VALID_VALID_VALID 0x00000001 /* R---V */
#define NV_ROUTE_ERR_NVS_ECC_ERROR_COUNTER 0x00005490 /* RW-4R */
#define NV_ROUTE_ERR_NVS_ECC_ERROR_COUNTER_ERROR_COUNT 23:0 /* RWDVF */
#define NV_ROUTE_ERR_NVS_ECC_ERROR_COUNTER_ERROR_COUNT_INIT 0x00000000 /* RWD-V */
#define NV_ROUTE_ERR_NVS_ECC_ERROR_COUNTER_LIMIT 0x00005494 /* RW-4R */
#define NV_ROUTE_ERR_NVS_ECC_ERROR_COUNTER_LIMIT_ERROR_LIMIT 23:0 /* RWDVF */
#define NV_ROUTE_ERR_NVS_ECC_ERROR_COUNTER_LIMIT_ERROR_LIMIT_INIT 0x00ffffff /* RWD-V */
#define NV_ROUTE_ERR_MCRID_ECC_ERROR_COUNTER 0x00005498 /* RW-4R */
#define NV_ROUTE_ERR_MCRID_ECC_ERROR_COUNTER_ERROR_COUNT 23:0 /* RWDVF */
#define NV_ROUTE_ERR_MCRID_ECC_ERROR_COUNTER_ERROR_COUNT_INIT 0x00000000 /* RWD-V */
#define NV_ROUTE_ERR_MCRID_ECC_ERROR_COUNTER_LIMIT 0x0000549c /* RW-4R */
#define NV_ROUTE_ERR_MCRID_ECC_ERROR_COUNTER_LIMIT_ERROR_LIMIT 23:0 /* RWDVF */
#define NV_ROUTE_ERR_MCRID_ECC_ERROR_COUNTER_LIMIT_ERROR_LIMIT_INIT 0x00ffffff /* RWD-V */
#define NV_ROUTE_ERR_MCRID_ECC_ERROR_ADDRESS 0x000054a0 /* R--4R */
#define NV_ROUTE_ERR_MCRID_ECC_ERROR_ADDRESS_ERROR_ADDRESS 6:0 /* R-DVF */
#define NV_ROUTE_ERR_MCRID_ECC_ERROR_ADDRESS_ERROR_ADDRESS_INIT 0x00000000 /* R-D-V */
#define NV_ROUTE_ERR_MCRID_ECC_ERROR_ADDRESS_VALID 0x000054a4 /* R--4R */
#define NV_ROUTE_ERR_MCRID_ECC_ERROR_ADDRESS_VALID_VALID 0:0 /* R-DVF */
#define NV_ROUTE_ERR_MCRID_ECC_ERROR_ADDRESS_VALID_VALID_INVALID 0x00000000 /* R-D-V */
#define NV_ROUTE_ERR_MCRID_ECC_ERROR_ADDRESS_VALID_VALID_VALID 0x00000001 /* R---V */
#define NV_ROUTE_ERR_EXTMCRID_ECC_ERROR_COUNTER 0x000054a8 /* RW-4R */
#define NV_ROUTE_ERR_EXTMCRID_ECC_ERROR_COUNTER_ERROR_COUNT 23:0 /* RWDVF */
#define NV_ROUTE_ERR_EXTMCRID_ECC_ERROR_COUNTER_ERROR_COUNT_INIT 0x00000000 /* RWD-V */
#define NV_ROUTE_ERR_EXTMCRID_ECC_ERROR_COUNTER_LIMIT 0x000054ac /* RW-4R */
#define NV_ROUTE_ERR_EXTMCRID_ECC_ERROR_COUNTER_LIMIT_ERROR_LIMIT 23:0 /* RWDVF */
#define NV_ROUTE_ERR_EXTMCRID_ECC_ERROR_COUNTER_LIMIT_ERROR_LIMIT_INIT 0x00ffffff /* RWD-V */
#define NV_ROUTE_ERR_EXTMCRID_ECC_ERROR_ADDRESS 0x000054b0 /* R--4R */
#define NV_ROUTE_ERR_EXTMCRID_ECC_ERROR_ADDRESS_ERROR_ADDRESS 3:0 /* R-DVF */
#define NV_ROUTE_ERR_EXTMCRID_ECC_ERROR_ADDRESS_ERROR_ADDRESS_INIT 0x00000000 /* R-D-V */
#define NV_ROUTE_ERR_EXTMCRID_ECC_ERROR_ADDRESS_VALID 0x000054b4 /* R--4R */
#define NV_ROUTE_ERR_EXTMCRID_ECC_ERROR_ADDRESS_VALID_VALID 0:0 /* R-DVF */
#define NV_ROUTE_ERR_EXTMCRID_ECC_ERROR_ADDRESS_VALID_VALID_INVALID 0x00000000 /* R-D-V */
#define NV_ROUTE_ERR_EXTMCRID_ECC_ERROR_ADDRESS_VALID_VALID_VALID 0x00000001 /* R---V */
#define NV_ROUTE_MCRID_ECC 0x000054b8 /* R--4R */
#define NV_ROUTE_MCRID_ECC_MCRID_ECC 10:0 /* R-EVF */
#define NV_ROUTE_MCRID_ECC_MCRID_ECC_INIT 0x00000000 /* R-E-V */
#define NV_ROUTE_MCRID_ECC_EXTMCRID_ECC 26:16 /* R-EVF */
#define NV_ROUTE_MCRID_ECC_EXTMCRID_ECC_INIT 0x00000000 /* R-E-V */
#define NV_ROUTE_ERR_RAM_ECC_ERROR_COUNTER 0x000054bc /* RW-4R */
#define NV_ROUTE_ERR_RAM_ECC_ERROR_COUNTER_ERROR_COUNT 23:0 /* RWDVF */
#define NV_ROUTE_ERR_RAM_ECC_ERROR_COUNTER_ERROR_COUNT_INIT 0x00000000 /* RWD-V */
#define NV_ROUTE_ERR_RAM_ECC_ERROR_COUNTER_LIMIT 0x000054c0 /* RW-4R */
#define NV_ROUTE_ERR_RAM_ECC_ERROR_COUNTER_LIMIT_ERROR_LIMIT 23:0 /* RWDVF */
#define NV_ROUTE_ERR_RAM_ECC_ERROR_COUNTER_LIMIT_ERROR_LIMIT_INIT 0x00ffffff /* RWD-V */
#define NV_ROUTE_RIDTABADDR 0x00005600 /* RW-4R */
#define NV_ROUTE_RIDTABADDR_INDEX 6:0 /* RWEVF */
#define NV_ROUTE_RIDTABADDR_INDEX_INIT 0x00000000 /* RWE-V */
#define NV_ROUTE_RIDTABADDR_INDEX_MCRIDTAB_DEPTH 0x0000007f /* RW--V */
#define NV_ROUTE_RIDTABADDR_INDEX_MCRIDEXTTAB_DEPTH 0x0000000f /* RW--V */
#define NV_ROUTE_RIDTABADDR_RAM_SEL 16:16 /* RWEVF */
#define NV_ROUTE_RIDTABADDR_RAM_SEL_SELECTSMCRIDROUTERAM 0x00000000 /* RWE-V */
#define NV_ROUTE_RIDTABADDR_RAM_SEL_SELECTSEXTMCRIDROUTERAM 0x00000001 /* RW--V */
#define NV_ROUTE_RIDTABADDR_AUTO_INCR 31:31 /* RWEVF */
#define NV_ROUTE_RIDTABADDR_AUTO_INCR_ENABLE 0x00000001 /* RWE-V */
#define NV_ROUTE_RIDTABADDR_AUTO_INCR_DISABLE 0x00000000 /* RW--V */
#define NV_ROUTE_RIDTABDATA0 0x00005610 /* RW-4R */
#define NV_ROUTE_RIDTABDATA0_MCPL_SIZE 5:0 /* RWEVF */
#define NV_ROUTE_RIDTABDATA0_MCPL_SIZE_INIT 0x00000000 /* RWE-V */
#define NV_ROUTE_RIDTABDATA0_MCPL_SPRAY_SIZE 11:8 /* RWEVF */
#define NV_ROUTE_RIDTABDATA0_MCPL_SPRAY_SIZE_INIT 0x00000000 /* RWE-V */
#define NV_ROUTE_RIDTABDATA0_MCPL_RID_EXT_PTR 19:16 /* RWEVF */
#define NV_ROUTE_RIDTABDATA0_MCPL_RID_EXT_PTR_INIT 0x00000000 /* RWE-V */
#define NV_ROUTE_RIDTABDATA0_MCPL_NO_DYN_RSP 29:29 /* RWEVF */
#define NV_ROUTE_RIDTABDATA0_MCPL_NO_DYN_RSP_INIT 0x00000000 /* RWE-V */
#define NV_ROUTE_RIDTABDATA0_MCPL_RID_EXT_PTR_VAL 30:30 /* RWEVF */
#define NV_ROUTE_RIDTABDATA0_MCPL_RID_EXT_PTR_VAL_INIT 0x00000000 /* RWE-V */
#define NV_ROUTE_RIDTABDATA0_VALID 31:31 /* RWEVF */
#define NV_ROUTE_RIDTABDATA0_VALID_INIT 0x00000000 /* RWE-V */
#define NV_ROUTE_RIDTABDATA0_VALID_VALID 0x00000001 /* RW--V */
#define NV_ROUTE_RIDTABDATA1 0x00005614 /* RW-4R */
#define NV_ROUTE_RIDTABDATA1_MCPL_E_PORT 3:0 /* RWEVF */
#define NV_ROUTE_RIDTABDATA1_MCPL_E_PORT_INIT 0x00000000 /* RWE-V */
#define NV_ROUTE_RIDTABDATA1_MCPL_E_ALTPATH 4:4 /* RWEVF */
#define NV_ROUTE_RIDTABDATA1_MCPL_E_ALTPATH_INIT 0x00000000 /* RWE-V */
#define NV_ROUTE_RIDTABDATA1_MCPL_E_REQ_VCHOP 6:5 /* RWEVF */
#define NV_ROUTE_RIDTABDATA1_MCPL_E_REQ_VCHOP_INIT 0x00000000 /* RWE-V */
#define NV_ROUTE_RIDTABDATA1_MCPL_O_PORT 10:7 /* RWEVF */
#define NV_ROUTE_RIDTABDATA1_MCPL_O_PORT_INIT 0x00000000 /* RWE-V */
#define NV_ROUTE_RIDTABDATA1_MCPL_O_ALTPATH 11:11 /* RWEVF */
#define NV_ROUTE_RIDTABDATA1_MCPL_O_ALTPATH_INIT 0x00000000 /* RWE-V */
#define NV_ROUTE_RIDTABDATA1_MCPL_O_REQ_VCHOP 13:12 /* RWEVF */
#define NV_ROUTE_RIDTABDATA1_MCPL_O_REQ_VCHOP_INIT 0x00000000 /* RWE-V */
#define NV_ROUTE_RIDTABDATA1_MCPL_TCP 15:14 /* RWEVF */
#define NV_ROUTE_RIDTABDATA1_MCPL_TCP_INIT 0x00000000 /* RWE-V */
#define NV_ROUTE_RIDTABDATA1_MCPL_PORT_FLAG 16:16 /* RWEVF */
#define NV_ROUTE_RIDTABDATA1_MCPL_PORT_FLAG_INIT 0x00000000 /* RWE-V */
#define NV_ROUTE_RIDTABDATA1_MCPL_RND_CONTINUE 17:17 /* RWEVF */
#define NV_ROUTE_RIDTABDATA1_MCPL_RND_CONTINUE_INIT 0x00000000 /* RWE-V */
#define NV_ROUTE_RIDTABDATA1_MCPL_LAST_RND 18:18 /* RWEVF */
#define NV_ROUTE_RIDTABDATA1_MCPL_LAST_RND_INIT 0x00000000 /* RWE-V */
#define NV_ROUTE_RIDTABDATA2 0x00005618 /* RW-4R */
#define NV_ROUTE_RIDTABDATA2_MCPL_STR_PTR0 4:0 /* RWEVF */
#define NV_ROUTE_RIDTABDATA2_MCPL_STR_PTR0_INIT 0x00000000 /* RWE-V */
#define NV_ROUTE_RIDTABDATA2_MCPL_STR_PTR1 12:8 /* RWEVF */
#define NV_ROUTE_RIDTABDATA2_MCPL_STR_PTR1_INIT 0x00000000 /* RWE-V */
#define NV_ROUTE_RIDTABDATA2_MCPL_STR_PTR2 20:16 /* RWEVF */
#define NV_ROUTE_RIDTABDATA2_MCPL_STR_PTR2_INIT 0x00000000 /* RWE-V */
#define NV_ROUTE_RIDTABDATA2_MCPL_STR_PTR3 28:24 /* RWEVF */
#define NV_ROUTE_RIDTABDATA2_MCPL_STR_PTR3_INIT 0x00000000 /* RWE-V */
#define NV_ROUTE_ERR_RAM_ECC_ERROR_ADDRESS 0x0000561c /* R--4R */
#define NV_ROUTE_ERR_RAM_ECC_ERROR_ADDRESS_ERROR_ADDRESS 8:0 /* R-DVF */
#define NV_ROUTE_ERR_RAM_ECC_ERROR_ADDRESS_ERROR_ADDRESS_INIT 0x00000000 /* R-D-V */
#define NV_ROUTE_ERR_RAM_ECC_ERROR_ADDRESS_VALID 0x00005620 /* R--4R */
#define NV_ROUTE_ERR_RAM_ECC_ERROR_ADDRESS_VALID_VALID 0:0 /* R-DVF */
#define NV_ROUTE_ERR_RAM_ECC_ERROR_ADDRESS_VALID_VALID_INVALID 0x00000000 /* R-D-V */
#define NV_ROUTE_ERR_RAM_ECC_ERROR_ADDRESS_VALID_VALID_VALID 0x00000001 /* R---V */
#endif // __ls10_dev_route_ip_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the Software),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __ls10_dev_route_ip_addendum_h__
#define __ls10_dev_route_ip_addendum_h__
// NV_ROUTE_REG_TABLE_DATA0 definition in the manuals have no indexing.
#define NV_ROUTE_REG_TABLE_DATA0_GLX(i) 4*(i)+3:4*(i)+0
#endif // __ls10_dev_route_ip_addendum_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the Software),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __ls10_dev_se_pri_h__
#define __ls10_dev_se_pri_h__
/* This file is autogenerated. Do not edit */
#define NV_PSE 0x001dffff:0x001d8000 /* RW--D */
#define NV_PSE_CG1 0x001df130 /* RW-4R */
#define NV_PSE_CG1_SLCG 8:1 /* RWIVF */
#define NV_PSE_CG1_SLCG_ENABLED 0x00000000 /* RW--V */
#define NV_PSE_CG1_SLCG_DISABLED 0x000000ff /* RWI-V */
#define NV_PSE_CG1_SLCG__PROD 0x000000ff /* RW--V */
#endif // __ls10_dev_se_pri_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the Software),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __ls10_dev_soe_ip_h__
#define __ls10_dev_soe_ip_h__
/* This file is autogenerated. Do not edit */
#define NV_SOE 0x3fff:0x0000 /* RW--D */
#define NV_SOE_FALCON_IRQSTAT 0x0008 /* R--4R */
#define NV_SOE_FALCON_IRQSTAT__DEVICE_MAP 0x00000002 /* */
#define NV_SOE_FALCON_IRQSTAT_GPTMR 0:0 /* R-IVF */
#define NV_SOE_FALCON_IRQSTAT_GPTMR_FALSE 0x00000000 /* R-I-V */
#define NV_SOE_FALCON_IRQSTAT_GPTMR_TRUE 0x00000001 /* R---V */
#define NV_SOE_FALCON_IRQSTAT_WDTMR 1:1 /* R-IVF */
#define NV_SOE_FALCON_IRQSTAT_WDTMR_FALSE 0x00000000 /* R-I-V */
#define NV_SOE_FALCON_IRQSTAT_WDTMR_TRUE 0x00000001 /* R---V */
#define NV_SOE_FALCON_IRQSTAT_MTHD 2:2 /* R-IVF */
#define NV_SOE_FALCON_IRQSTAT_MTHD_FALSE 0x00000000 /* R-I-V */
#define NV_SOE_FALCON_IRQSTAT_MTHD_TRUE 0x00000001 /* R---V */
#define NV_SOE_FALCON_IRQSTAT_CTXSW 3:3 /* R-IVF */
#define NV_SOE_FALCON_IRQSTAT_CTXSW_FALSE 0x00000000 /* R-I-V */
#define NV_SOE_FALCON_IRQSTAT_CTXSW_TRUE 0x00000001 /* R---V */
#define NV_SOE_FALCON_IRQSTAT_HALT 4:4 /* R-IVF */
#define NV_SOE_FALCON_IRQSTAT_HALT_FALSE 0x00000000 /* R-I-V */
#define NV_SOE_FALCON_IRQSTAT_HALT_TRUE 0x00000001 /* R---V */
#define NV_SOE_FALCON_IRQSTAT_EXTERR 5:5 /* R-IVF */
#define NV_SOE_FALCON_IRQSTAT_EXTERR_FALSE 0x00000000 /* R-I-V */
#define NV_SOE_FALCON_IRQSTAT_EXTERR_TRUE 0x00000001 /* R---V */
#define NV_SOE_FALCON_IRQSTAT_SWGEN0 6:6 /* R-IVF */
#define NV_SOE_FALCON_IRQSTAT_SWGEN0_FALSE 0x00000000 /* R-I-V */
#define NV_SOE_FALCON_IRQSTAT_SWGEN0_TRUE 0x00000001 /* R---V */
#define NV_SOE_FALCON_IRQSTAT_SWGEN1 7:7 /* R-IVF */
#define NV_SOE_FALCON_IRQSTAT_SWGEN1_FALSE 0x00000000 /* R-I-V */
#define NV_SOE_FALCON_IRQSTAT_SWGEN1_TRUE 0x00000001 /* R---V */
#define NV_SOE_FALCON_IRQSTAT_EXT 15:8 /* */
#define NV_SOE_FALCON_IRQSTAT_EXT_EXTIRQ1 8:8 /* R-IVF */
#define NV_SOE_FALCON_IRQSTAT_EXT_EXTIRQ1_TRUE 0x00000001 /* R---V */
#define NV_SOE_FALCON_IRQSTAT_EXT_EXTIRQ1_FALSE 0x00000000 /* R-I-V */
#define NV_SOE_FALCON_IRQSTAT_EXT_EXTIRQ2 9:9 /* R-IVF */
#define NV_SOE_FALCON_IRQSTAT_EXT_EXTIRQ2_TRUE 0x00000001 /* R---V */
#define NV_SOE_FALCON_IRQSTAT_EXT_EXTIRQ2_FALSE 0x00000000 /* R-I-V */
#define NV_SOE_FALCON_IRQSTAT_EXT_EXTIRQ3 10:10 /* R-IVF */
#define NV_SOE_FALCON_IRQSTAT_EXT_EXTIRQ3_TRUE 0x00000001 /* R---V */
#define NV_SOE_FALCON_IRQSTAT_EXT_EXTIRQ3_FALSE 0x00000000 /* R-I-V */
#define NV_SOE_FALCON_IRQSTAT_EXT_EXTIRQ4 11:11 /* R-IVF */
#define NV_SOE_FALCON_IRQSTAT_EXT_EXTIRQ4_TRUE 0x00000001 /* R---V */
#define NV_SOE_FALCON_IRQSTAT_EXT_EXTIRQ4_FALSE 0x00000000 /* R-I-V */
#define NV_SOE_FALCON_IRQSTAT_EXT_EXTIRQ5 12:12 /* R-IVF */
#define NV_SOE_FALCON_IRQSTAT_EXT_EXTIRQ5_TRUE 0x00000001 /* R---V */
#define NV_SOE_FALCON_IRQSTAT_EXT_EXTIRQ5_FALSE 0x00000000 /* R-I-V */
#define NV_SOE_FALCON_IRQSTAT_EXT_EXTIRQ6 13:13 /* R-IVF */
#define NV_SOE_FALCON_IRQSTAT_EXT_EXTIRQ6_TRUE 0x00000001 /* R---V */
#define NV_SOE_FALCON_IRQSTAT_EXT_EXTIRQ6_FALSE 0x00000000 /* R-I-V */
#define NV_SOE_FALCON_IRQSTAT_EXT_EXTIRQ7 14:14 /* R-IVF */
#define NV_SOE_FALCON_IRQSTAT_EXT_EXTIRQ7_TRUE 0x00000001 /* R---V */
#define NV_SOE_FALCON_IRQSTAT_EXT_EXTIRQ7_FALSE 0x00000000 /* R-I-V */
#define NV_SOE_FALCON_IRQSTAT_EXT_EXTIRQ8 15:15 /* R-IVF */
#define NV_SOE_FALCON_IRQSTAT_EXT_EXTIRQ8_TRUE 0x00000001 /* R---V */
#define NV_SOE_FALCON_IRQSTAT_EXT_EXTIRQ8_FALSE 0x00000000 /* R-I-V */
#define NV_SOE_FALCON_IRQSTAT_DMA 16:16 /* R-IVF */
#define NV_SOE_FALCON_IRQSTAT_DMA_TRUE 0x00000001 /* R---V */
#define NV_SOE_FALCON_IRQSTAT_DMA_FALSE 0x00000000 /* R-I-V */
#define NV_SOE_FALCON_IRQSTAT_SHA 17:17 /* R-IVF */
#define NV_SOE_FALCON_IRQSTAT_SHA_TRUE 0x00000001 /* R---V */
#define NV_SOE_FALCON_IRQSTAT_SHA_FALSE 0x00000000 /* R-I-V */
#define NV_SOE_FALCON_IRQSTAT_MEMERR 18:18 /* R-IVF */
#define NV_SOE_FALCON_IRQSTAT_MEMERR_TRUE 0x00000001 /* R---V */
#define NV_SOE_FALCON_IRQSTAT_MEMERR_FALSE 0x00000000 /* R-I-V */
#define NV_SOE_FALCON_IRQSTAT_CTXSW_ERROR 19:19 /* R-XVF */
#define NV_SOE_FALCON_IRQSTAT_CTXSW_ERROR_TRUE 0x00000001 /* R---V */
#define NV_SOE_FALCON_IRQSTAT_CTXSW_ERROR_FALSE 0x00000000 /* R---V */
#define NV_SOE_FALCON_IRQSTAT_GDMA 20:20 /* R-XVF */
#define NV_SOE_FALCON_IRQSTAT_GDMA_TRUE 0x00000001 /* R---V */
#define NV_SOE_FALCON_IRQSTAT_GDMA_FALSE 0x00000000 /* R---V */
#define NV_SOE_FALCON_IRQSTAT_ICD 22:22 /* R-XVF */
#define NV_SOE_FALCON_IRQSTAT_ICD_TRUE 0x00000001 /* R---V */
#define NV_SOE_FALCON_IRQSTAT_ICD_FALSE 0x00000000 /* R---V */
#define NV_SOE_FALCON_IRQSTAT_IOPMP 23:23 /* R-XVF */
#define NV_SOE_FALCON_IRQSTAT_IOPMP_TRUE 0x00000001 /* R---V */
#define NV_SOE_FALCON_IRQSTAT_IOPMP_FALSE 0x00000000 /* R---V */
#define NV_SOE_FALCON_IRQSTAT_CORE_MISMATCH 24:24 /* R-XVF */
#define NV_SOE_FALCON_IRQSTAT_CORE_MISMATCH_TRUE 0x00000001 /* R---V */
#define NV_SOE_FALCON_IRQSTAT_CORE_MISMATCH_FALSE 0x00000000 /* R---V */
#define NV_SOE_FALCON_IRQSTAT_SE_SAP 25:25 /* R-XVF */
#define NV_SOE_FALCON_IRQSTAT_SE_SAP_SET 0x00000001 /* R---V */
#define NV_SOE_FALCON_IRQSTAT_SE_PKA 26:26 /* R-XVF */
#define NV_SOE_FALCON_IRQSTAT_SE_PKA_SET 0x00000001 /* R---V */
#define NV_SOE_FALCON_IRQSTAT_SE_RNG 27:27 /* R-XVF */
#define NV_SOE_FALCON_IRQSTAT_SE_RNG_SET 0x00000001 /* R---V */
#define NV_SOE_FALCON_IRQSTAT_SE_KEYMOVER 28:28 /* R-XVF */
#define NV_SOE_FALCON_IRQSTAT_SE_KEYMOVER_SET 0x00000001 /* R---V */
#define NV_SOE_FALCON_CGCTL 0x00a0 /* RW-4R */
#define NV_SOE_FALCON_CGCTL__DEVICE_MAP 0x00000000 /* */
#define NV_SOE_FALCON_CGCTL_CG_OVERRIDE 0:0 /* RWIVF */
#define NV_SOE_FALCON_CGCTL_CG_OVERRIDE_INIT 0x00000000 /* RWI-V */
#define NV_SOE_FALCON_CG2 0x0134 /* RW-4R */
#define NV_SOE_FALCON_CG2__DEVICE_MAP 0x00000000 /* */
#define NV_SOE_FALCON_CG2_SLCG 17:1 /* */
#define NV_SOE_FALCON_CG2_SLCG_ENABLED 0 /* */
#define NV_SOE_FALCON_CG2_SLCG_DISABLED 0x1FFFF /* */
#define NV_SOE_FALCON_CG2_SLCG__PROD 0x000A0 /* */
#define NV_SOE_FALCON_CG2_SLCG_FALCON_DMA 1:1 /* RWIVF */
#define NV_SOE_FALCON_CG2_SLCG_FALCON_DMA_ENABLED 0x00000000 /* RW--V */
#define NV_SOE_FALCON_CG2_SLCG_FALCON_DMA_DISABLED 0x00000001 /* RWI-V */
#define NV_SOE_FALCON_CG2_SLCG_FALCON_GC6_SR_FSM 2:2 /* RWIVF */
#define NV_SOE_FALCON_CG2_SLCG_FALCON_GC6_SR_FSM_ENABLED 0x00000000 /* RW--V */
#define NV_SOE_FALCON_CG2_SLCG_FALCON_GC6_SR_FSM_DISABLED 0x00000001 /* RWI-V */
#define NV_SOE_FALCON_CG2_SLCG_FALCON_PIPE 3:3 /* RWIVF */
#define NV_SOE_FALCON_CG2_SLCG_FALCON_PIPE_ENABLED 0x00000000 /* RW--V */
#define NV_SOE_FALCON_CG2_SLCG_FALCON_PIPE_DISABLED 0x00000001 /* RWI-V */
#define NV_SOE_FALCON_CG2_SLCG_FALCON_DIV 4:4 /* RWIVF */
#define NV_SOE_FALCON_CG2_SLCG_FALCON_DIV_ENABLED 0x00000000 /* RW--V */
#define NV_SOE_FALCON_CG2_SLCG_FALCON_DIV_DISABLED 0x00000001 /* RWI-V */
#define NV_SOE_FALCON_CG2_SLCG_FALCON_ICD 5:5 /* RWIVF */
#define NV_SOE_FALCON_CG2_SLCG_FALCON_ICD_ENABLED 0x00000000 /* RW--V */
#define NV_SOE_FALCON_CG2_SLCG_FALCON_ICD_DISABLED 0x00000001 /* RWI-V */
#define NV_SOE_FALCON_CG2_SLCG_FALCON_CFG 6:6 /* RWIVF */
#define NV_SOE_FALCON_CG2_SLCG_FALCON_CFG_ENABLED 0x00000000 /* RW--V */
#define NV_SOE_FALCON_CG2_SLCG_FALCON_CFG_DISABLED 0x00000001 /* RWI-V */
#define NV_SOE_FALCON_CG2_SLCG_FALCON_CTXSW 7:7 /* RWIVF */
#define NV_SOE_FALCON_CG2_SLCG_FALCON_CTXSW_ENABLED 0x00000000 /* RW--V */
#define NV_SOE_FALCON_CG2_SLCG_FALCON_CTXSW_DISABLED 0x00000001 /* RWI-V */
#define NV_SOE_FALCON_CG2_SLCG_FALCON_PMB 8:8 /* RWIVF */
#define NV_SOE_FALCON_CG2_SLCG_FALCON_PMB_ENABLED 0x00000000 /* RW--V */
#define NV_SOE_FALCON_CG2_SLCG_FALCON_PMB_DISABLED 0x00000001 /* RWI-V */
#define NV_SOE_FALCON_CG2_SLCG_FALCON_RF 9:9 /* RWIVF */
#define NV_SOE_FALCON_CG2_SLCG_FALCON_RF_ENABLED 0x00000000 /* RW--V */
#define NV_SOE_FALCON_CG2_SLCG_FALCON_RF_DISABLED 0x00000001 /* RWI-V */
#define NV_SOE_FALCON_CG2_SLCG_FALCON_MUL 10:10 /* RWIVF */
#define NV_SOE_FALCON_CG2_SLCG_FALCON_MUL_ENABLED 0x00000000 /* RW--V */
#define NV_SOE_FALCON_CG2_SLCG_FALCON_MUL_DISABLED 0x00000001 /* RWI-V */
#define NV_SOE_FALCON_CG2_SLCG_FALCON_LDST 11:11 /* RWIVF */
#define NV_SOE_FALCON_CG2_SLCG_FALCON_LDST_ENABLED 0x00000000 /* RW--V */
#define NV_SOE_FALCON_CG2_SLCG_FALCON_LDST_DISABLED 0x00000001 /* RWI-V */
#define NV_SOE_FALCON_CG2_SLCG_FALCON_TSYNC 12:12 /* RWIVF */
#define NV_SOE_FALCON_CG2_SLCG_FALCON_TSYNC_ENABLED 0x00000000 /* RW--V */
#define NV_SOE_FALCON_CG2_SLCG_FALCON_TSYNC_DISABLED 0x00000001 /* RWI-V */
#define NV_SOE_FALCON_CG2_SLCG_FALCON_GPTMR 13:13 /* RWIVF */
#define NV_SOE_FALCON_CG2_SLCG_FALCON_GPTMR_ENABLED 0x00000000 /* RW--V */
#define NV_SOE_FALCON_CG2_SLCG_FALCON_GPTMR_DISABLED 0x00000001 /* RWI-V */
#define NV_SOE_FALCON_CG2_SLCG_FALCON_WDTMR 14:14 /* RWIVF */
#define NV_SOE_FALCON_CG2_SLCG_FALCON_WDTMR_ENABLED 0x00000000 /* RW--V */
#define NV_SOE_FALCON_CG2_SLCG_FALCON_WDTMR_DISABLED 0x00000001 /* RWI-V */
#define NV_SOE_FALCON_CG2_SLCG_FALCON_IRQSTAT 15:15 /* RWIVF */
#define NV_SOE_FALCON_CG2_SLCG_FALCON_IRQSTAT_ENABLED 0x00000000 /* RW--V */
#define NV_SOE_FALCON_CG2_SLCG_FALCON_IRQSTAT_DISABLED 0x00000001 /* RWI-V */
#define NV_SOE_FALCON_CG2_SLCG_FALCON_TOP 16:16 /* RWIVF */
#define NV_SOE_FALCON_CG2_SLCG_FALCON_TOP_ENABLED 0x00000000 /* RW--V */
#define NV_SOE_FALCON_CG2_SLCG_FALCON_TOP_DISABLED 0x00000001 /* RWI-V */
#define NV_SOE_FALCON_CG2_SLCG_FBIF 17:17 /* RWIVF */
#define NV_SOE_FALCON_CG2_SLCG_FBIF_ENABLED 0x00000000 /* RW--V */
#define NV_SOE_FALCON_CG2_SLCG_FBIF_DISABLED 0x00000001 /* RWI-V */
#define NV_SOE_FALCON_CG2_SLCG_FALCON_SHA 18:18 /* RWIVF */
#define NV_SOE_FALCON_CG2_SLCG_FALCON_SHA__PROD 0x00000001 /* RW--V */
#define NV_SOE_FALCON_CG2_SLCG_FALCON_SHA_ENABLED 0x00000000 /* RW--V */
#define NV_SOE_FALCON_CG2_SLCG_FALCON_SHA_DISABLED 0x00000001 /* RWI-V */
#define NV_SOE_FALCON_CG2_SLCG_FALCON_GDMA 19:19 /* RWIVF */
#define NV_SOE_FALCON_CG2_SLCG_FALCON_GDMA__PROD 0x00000001 /* RW--V */
#define NV_SOE_FALCON_CG2_SLCG_FALCON_GDMA_ENABLED 0x00000000 /* RW--V */
#define NV_SOE_FALCON_CG2_SLCG_FALCON_GDMA_DISABLED 0x00000001 /* RWI-V */
#define NV_SOE_FALCON_CG2_SLCG_FALCON_TSE 20:20 /* RWIVF */
#define NV_SOE_FALCON_CG2_SLCG_FALCON_TSE__PROD 0x00000001 /* RW--V */
#define NV_SOE_FALCON_CG2_SLCG_FALCON_TSE_ENABLED 0x00000000 /* RW--V */
#define NV_SOE_FALCON_CG2_SLCG_FALCON_TSE_DISABLED 0x00000001 /* RWI-V */
#define NV_SOE_RISCV_IRQMASK 0x1528 /* R--4R */
#define NV_SOE_RISCV_IRQMASK__DEVICE_MAP 0x00000002 /* */
#define NV_SOE_RISCV_IRQMASK_GPTMR 0:0 /* R-IVF */
#define NV_SOE_RISCV_IRQMASK_GPTMR_UNSET 0x00000000 /* R-I-V */
#define NV_SOE_RISCV_IRQMASK_GPTMR_SET 0x00000001 /* R---V */
#define NV_SOE_RISCV_IRQMASK_WDTMR 1:1 /* R-IVF */
#define NV_SOE_RISCV_IRQMASK_WDTMR_UNSET 0x00000000 /* R-I-V */
#define NV_SOE_RISCV_IRQMASK_WDTMR_SET 0x00000001 /* R---V */
#define NV_SOE_RISCV_IRQMASK_MTHD 2:2 /* R-IVF */
#define NV_SOE_RISCV_IRQMASK_MTHD_UNSET 0x00000000 /* R-I-V */
#define NV_SOE_RISCV_IRQMASK_MTHD_SET 0x00000001 /* R---V */
#define NV_SOE_RISCV_IRQMASK_CTXSW 3:3 /* R-IVF */
#define NV_SOE_RISCV_IRQMASK_CTXSW_UNSET 0x00000000 /* R-I-V */
#define NV_SOE_RISCV_IRQMASK_CTXSW_SET 0x00000001 /* R---V */
#define NV_SOE_RISCV_IRQMASK_HALT 4:4 /* R-IVF */
#define NV_SOE_RISCV_IRQMASK_HALT_UNSET 0x00000000 /* R-I-V */
#define NV_SOE_RISCV_IRQMASK_HALT_SET 0x00000001 /* R---V */
#define NV_SOE_RISCV_IRQMASK_EXTERR 5:5 /* R-IVF */
#define NV_SOE_RISCV_IRQMASK_EXTERR_UNSET 0x00000000 /* R-I-V */
#define NV_SOE_RISCV_IRQMASK_EXTERR_SET 0x00000001 /* R---V */
#define NV_SOE_RISCV_IRQMASK_SWGEN0 6:6 /* R-IVF */
#define NV_SOE_RISCV_IRQMASK_SWGEN0_UNSET 0x00000000 /* R-I-V */
#define NV_SOE_RISCV_IRQMASK_SWGEN0_SET 0x00000001 /* R---V */
#define NV_SOE_RISCV_IRQMASK_SWGEN1 7:7 /* R-IVF */
#define NV_SOE_RISCV_IRQMASK_SWGEN1_UNSET 0x00000000 /* R-I-V */
#define NV_SOE_RISCV_IRQMASK_SWGEN1_SET 0x00000001 /* R---V */
#define NV_SOE_RISCV_IRQDEST 0x152c /* RW-4R */
#define NV_SOE_RISCV_IRQDEST__DEVICE_MAP 0x00000002 /* */
#define NV_SOE_RISCV_IRQDEST_GPTMR 0:0 /* RWIVF */
#define NV_SOE_RISCV_IRQDEST_GPTMR_RISCV 0x00000000 /* RWI-V */
#define NV_SOE_RISCV_IRQDEST_GPTMR_HOST 0x00000001 /* RW--V */
#define NV_SOE_RISCV_IRQDEST_WDTMR 1:1 /* RWIVF */
#define NV_SOE_RISCV_IRQDEST_WDTMR_RISCV 0x00000000 /* RWI-V */
#define NV_SOE_RISCV_IRQDEST_WDTMR_HOST 0x00000001 /* RW--V */
#define NV_SOE_RISCV_IRQDEST_MTHD 2:2 /* RWIVF */
#define NV_SOE_RISCV_IRQDEST_MTHD_RISCV 0x00000000 /* RWI-V */
#define NV_SOE_RISCV_IRQDEST_MTHD_HOST 0x00000001 /* RW--V */
#define NV_SOE_RISCV_IRQDEST_CTXSW 3:3 /* RWIVF */
#define NV_SOE_RISCV_IRQDEST_CTXSW_RISCV 0x00000000 /* RWI-V */
#define NV_SOE_RISCV_IRQDEST_CTXSW_HOST 0x00000001 /* RW--V */
#define NV_SOE_RISCV_IRQDEST_HALT 4:4 /* RWIVF */
#define NV_SOE_RISCV_IRQDEST_HALT_RISCV 0x00000000 /* RWI-V */
#define NV_SOE_RISCV_IRQDEST_HALT_HOST 0x00000001 /* RW--V */
#define NV_SOE_RISCV_IRQDEST_EXTERR 5:5 /* RWIVF */
#define NV_SOE_RISCV_IRQDEST_EXTERR_RISCV 0x00000000 /* RWI-V */
#define NV_SOE_RISCV_IRQDEST_EXTERR_HOST 0x00000001 /* RW--V */
#define NV_SOE_RISCV_IRQDEST_SWGEN0 6:6 /* RWIVF */
#define NV_SOE_RISCV_IRQDEST_SWGEN0_RISCV 0x00000000 /* RWI-V */
#define NV_SOE_RISCV_IRQDEST_SWGEN0_HOST 0x00000001 /* RW--V */
#define NV_SOE_RISCV_IRQDEST_SWGEN1 7:7 /* RWIVF */
#define NV_SOE_RISCV_IRQDEST_SWGEN1_RISCV 0x00000000 /* RWI-V */
#define NV_SOE_RISCV_IRQDEST_SWGEN1_HOST 0x00000001 /* RW--V */
#define NV_SOE_RISCV_IRQDEST_EXT 15:8 /* */
#define NV_SOE_RISCV_IRQDEST_EXT_EXTIRQ1 8:8 /* RWIVF */
#define NV_SOE_RISCV_IRQDEST_EXT_EXTIRQ1_RISCV 0x00000000 /* RWI-V */
#define NV_SOE_RISCV_IRQDEST_EXT_EXTIRQ1_HOST 0x00000001 /* RW--V */
#define NV_SOE_RISCV_IRQDEST_EXT_EXTIRQ2 9:9 /* RWIVF */
#define NV_SOE_RISCV_IRQDEST_EXT_EXTIRQ2_RISCV 0x00000000 /* RWI-V */
#define NV_SOE_RISCV_IRQDEST_EXT_EXTIRQ2_HOST 0x00000001 /* RW--V */
#define NV_SOE_RISCV_IRQDEST_EXT_EXTIRQ3 10:10 /* RWIVF */
#define NV_SOE_RISCV_IRQDEST_EXT_EXTIRQ3_RISCV 0x00000000 /* RWI-V */
#define NV_SOE_RISCV_IRQDEST_EXT_EXTIRQ3_HOST 0x00000001 /* RW--V */
#define NV_SOE_RISCV_IRQDEST_EXT_EXTIRQ4 11:11 /* RWIVF */
#define NV_SOE_RISCV_IRQDEST_EXT_EXTIRQ4_RISCV 0x00000000 /* RWI-V */
#define NV_SOE_RISCV_IRQDEST_EXT_EXTIRQ4_HOST 0x00000001 /* RW--V */
#define NV_SOE_RISCV_IRQDEST_EXT_EXTIRQ5 12:12 /* RWIVF */
#define NV_SOE_RISCV_IRQDEST_EXT_EXTIRQ5_RISCV 0x00000000 /* RWI-V */
#define NV_SOE_RISCV_IRQDEST_EXT_EXTIRQ5_HOST 0x00000001 /* RW--V */
#define NV_SOE_RISCV_IRQDEST_EXT_EXTIRQ6 13:13 /* RWIVF */
#define NV_SOE_RISCV_IRQDEST_EXT_EXTIRQ6_RISCV 0x00000000 /* RWI-V */
#define NV_SOE_RISCV_IRQDEST_EXT_EXTIRQ6_HOST 0x00000001 /* RW--V */
#define NV_SOE_RISCV_IRQDEST_EXT_EXTIRQ7 14:14 /* RWIVF */
#define NV_SOE_RISCV_IRQDEST_EXT_EXTIRQ7_RISCV 0x00000000 /* RWI-V */
#define NV_SOE_RISCV_IRQDEST_EXT_EXTIRQ7_HOST 0x00000001 /* RW--V */
#define NV_SOE_RISCV_IRQDEST_EXT_EXTIRQ8 15:15 /* RWIVF */
#define NV_SOE_RISCV_IRQDEST_EXT_EXTIRQ8_RISCV 0x00000000 /* RWI-V */
#define NV_SOE_RISCV_IRQDEST_EXT_EXTIRQ8_HOST 0x00000001 /* RW--V */
#define NV_SOE_RISCV_IRQDEST_DMA 16:16 /* RWIVF */
#define NV_SOE_RISCV_IRQDEST_DMA_RISCV 0x00000000 /* RWI-V */
#define NV_SOE_RISCV_IRQDEST_DMA_HOST 0x00000001 /* RW--V */
#define NV_SOE_RISCV_IRQDEST_SHA 17:17 /* RWIVF */
#define NV_SOE_RISCV_IRQDEST_SHA_RISCV 0x00000000 /* RWI-V */
#define NV_SOE_RISCV_IRQDEST_SHA_HOST 0x00000001 /* RW--V */
#define NV_SOE_RISCV_IRQDEST_MEMERR 18:18 /* RWIVF */
#define NV_SOE_RISCV_IRQDEST_MEMERR_RISCV 0x00000000 /* RWI-V */
#define NV_SOE_RISCV_IRQDEST_MEMERR_HOST 0x00000001 /* RW--V */
#define NV_SOE_RISCV_IRQDEST_CTXSW_ERROR 19:19 /* R-IVF */
#define NV_SOE_RISCV_IRQDEST_CTXSW_ERROR_RISCV 0x00000000 /* R---V */
#define NV_SOE_RISCV_IRQDEST_CTXSW_ERROR_HOST 0x00000001 /* R-I-V */
#define NV_SOE_RISCV_IRQDEST_GDMA 20:20 /* RWIVF */
#define NV_SOE_RISCV_IRQDEST_GDMA_RISCV 0x00000000 /* RWI-V */
#define NV_SOE_RISCV_IRQDEST_GDMA_HOST 0x00000001 /* RW--V */
#define NV_SOE_RISCV_IRQDEST_ICD 22:22 /* RWIVF */
#define NV_SOE_RISCV_IRQDEST_ICD_RISCV 0x00000000 /* RWI-V */
#define NV_SOE_RISCV_IRQDEST_ICD_HOST 0x00000001 /* RW--V */
#define NV_SOE_RISCV_IRQDEST_IOPMP 23:23 /* RWIVF */
#define NV_SOE_RISCV_IRQDEST_IOPMP_RISCV 0x00000000 /* RWI-V */
#define NV_SOE_RISCV_IRQDEST_IOPMP_HOST 0x00000001 /* RW--V */
#define NV_SOE_RISCV_IRQDEST_CORE_MISMATCH 24:24 /* R-IVF */
#define NV_SOE_RISCV_IRQDEST_CORE_MISMATCH_RISCV 0x00000000 /* R---V */
#define NV_SOE_RISCV_IRQDEST_CORE_MISMATCH_HOST 0x00000001 /* R-I-V */
#define NV_SOE_RISCV_IRQDEST_SE_SAP 25:25 /* RWIVF */
#define NV_SOE_RISCV_IRQDEST_SE_SAP_RISCV 0x00000000 /* RWI-V */
#define NV_SOE_RISCV_IRQDEST_SE_SAP_HOST 0x00000001 /* RW--V */
#define NV_SOE_RISCV_IRQDEST_SE_PKA 26:26 /* RWIVF */
#define NV_SOE_RISCV_IRQDEST_SE_PKA_RISCV 0x00000000 /* RWI-V */
#define NV_SOE_RISCV_IRQDEST_SE_PKA_HOST 0x00000001 /* RW--V */
#define NV_SOE_RISCV_IRQDEST_SE_RNG 27:27 /* RWIVF */
#define NV_SOE_RISCV_IRQDEST_SE_RNG_RISCV 0x00000000 /* RWI-V */
#define NV_SOE_RISCV_IRQDEST_SE_RNG_HOST 0x00000001 /* RW--V */
#define NV_SOE_RISCV_IRQDEST_SE_KEYMOVER 28:28 /* RWIVF */
#define NV_SOE_RISCV_IRQDEST_SE_KEYMOVER_RISCV 0x00000000 /* RWI-V */
#define NV_SOE_RISCV_IRQDEST_SE_KEYMOVER_HOST 0x00000001 /* RW--V */
#define NV_SOE_RISCV_CPUCTL 0x1388 /* RW-4R */
#define NV_SOE_RISCV_CPUCTL_STARTCPU 0:0 /* -WIVF */
#define NV_SOE_RISCV_CPUCTL_STARTCPU_FALSE 0x00000000 /* -WI-V */
#define NV_SOE_RISCV_CPUCTL_STARTCPU_TRUE 0x00000001 /* -W--V */
#define NV_SOE_RISCV_CPUCTL_HALTED 4:4 /* R-IVF */
#define NV_SOE_RISCV_CPUCTL_HALTED_INIT 0x00000001 /* R-I-V */
#define NV_SOE_RISCV_CPUCTL_HALTED_TRUE 0x00000001 /* R---V */
#define NV_SOE_RISCV_CPUCTL_HALTED_FALSE 0x00000000 /* R---V */
#define NV_SOE_RISCV_CPUCTL_STOPPED 5:5 /* R-IVF */
#define NV_SOE_RISCV_CPUCTL_STOPPED_INIT 0x00000000 /* R-I-V */
#define NV_SOE_RISCV_CPUCTL_ACTIVE_STAT 7:7 /* R-IVF */
#define NV_SOE_RISCV_CPUCTL_ACTIVE_STAT_INACTIVE 0x00000000 /* R-I-V */
#define NV_SOE_RISCV_CPUCTL_ACTIVE_STAT_ACTIVE 0x00000001 /* R---V */
#define NV_SOE_RISCV_CG 0x1398 /* RW-4R */
#define NV_SOE_RISCV_CG__DEVICE_MAP 0x00000000 /* */
#define NV_SOE_RISCV_CG_SLCG 1:0 /* */
#define NV_SOE_RISCV_CG_SLCG_DISABLED 0 /* */
#define NV_SOE_RISCV_CG_SLCG_ENABLED 3 /* */
#define NV_SOE_RISCV_CG_SLCG__PROD 3 /* */
#define NV_SOE_RISCV_CG_SLCG_EXT 0:0 /* RWIVF */
#define NV_SOE_RISCV_CG_SLCG_EXT_DISABLED 0x00000000 /* RWI-V */
#define NV_SOE_RISCV_CG_SLCG_EXT_ENABLED 0x00000001 /* RW--V */
#define NV_SOE_RISCV_CG_SLCG_CORE 1:1 /* RWIVF */
#define NV_SOE_RISCV_CG_SLCG_CORE_DISABLED 0x00000000 /* RWI-V */
#define NV_SOE_RISCV_CG_SLCG_CORE_ENABLED 0x00000001 /* RW--V */
#define NV_SOE_RISCV_CG_RSVD 31:2 /* R-IVF */
#define NV_SOE_RISCV_CG_RSVD_INIT 0x00000000 /* R-I-V */
#define NV_SOE_RISCV_CG_CORE_SLCG 1:1 /* */
#define NV_SOE_RISCV_CG_SLCG_DISABLE 0 /* */
#define NV_SOE_RISCV_CG_SLCG_ENABLE 1 /* */
#define NV_SOE_RISCV_CG_CORE_SLCG_DISABLE 0 /* */
#define NV_SOE_RISCV_CG_CORE_SLCG_ENABLE 1 /* */
#define NV_SOE_PRIV_BLOCKER_CTRL_CG1 0x0e28 /* RW-4R */
#define NV_SOE_PRIV_BLOCKER_CTRL_CG1_SLCG 0:0 /* RWIVF */
#define NV_SOE_PRIV_BLOCKER_CTRL_CG1_SLCG_DISABLED 0x00000001 /* RWI-V */
#define NV_SOE_PRIV_BLOCKER_CTRL_CG1_SLCG_ENABLED 0x00000000 /* RW--V */
#define NV_SOE_PRIV_BLOCKER_CTRL_CG1_SLCG__PROD 0x00000000 /* RW--V */
#define NV_SOE_BAR0_TMOUT 0x070c /* RW-4R */
#define NV_SOE_BAR0_TMOUT_CYCLES 31:0 /* RWIVF */
#define NV_SOE_BAR0_TMOUT_CYCLES_INIT 0x01f2a737 /* RWI-V */
#define NV_SOE_BAR0_TMOUT_CYCLES__PROD 0x01f2a737 /* RW--V */
#define NV_SOE_MISC_CG1 0x083c /* RW-4R */
#define NV_SOE_MISC_CG1_SLCG 31:0 /* RWIVF */
#define NV_SOE_MISC_CG1_SLCG_ENABLED 0x00000000 /* RW--V */
#define NV_SOE_MISC_CG1_SLCG_DISABLED 0x8000003d /* RWI-V */
#define NV_SOE_MISC_CG1_SLCG__PROD 0x0000003c /* RW--V */
#define NV_SOE_MISC_CG1_SLCG_FALCON 0:0 /* */
#define NV_SOE_MISC_CG1_SLCG_FALCON_ENABLED 0 /* */
#define NV_SOE_MISC_CG1_SLCG_FALCON_DISABLED 1 /* */
#define NV_SOE_MISC_CG1_SLCG_SCP 2:2 /* */
#define NV_SOE_MISC_CG1_SLCG_SCP_ENABLED 0 /* */
#define NV_SOE_MISC_CG1_SLCG_SCP_DISABLED 1 /* */
#define NV_SOE_MISC_CG1_SLCG_CSBMASTER 3:3 /* */
#define NV_SOE_MISC_CG1_SLCG_CSBMASTER_ENABLED 0 /* */
#define NV_SOE_MISC_CG1_SLCG_CSBMASTER_DISABLED 1 /* */
#define NV_SOE_MISC_CG1_SLCG_BAR0 4:4 /* */
#define NV_SOE_MISC_CG1_SLCG_BAR0_ENABLED 0 /* */
#define NV_SOE_MISC_CG1_SLCG_BAR0_DISABLED 1 /* */
#define NV_SOE_MISC_CG1_SLCG_MISC 5:5 /* */
#define NV_SOE_MISC_CG1_SLCG_MISC_ENABLED 0 /* */
#define NV_SOE_MISC_CG1_SLCG_MISC_DISABLED 1 /* */
#define NV_SOE_MISC_CG1_SLCG_TOP 31:31 /* */
#define NV_SOE_MISC_CG1_SLCG_TOP_ENABLED 0x00000000 /* */
#define NV_SOE_MISC_CG1_SLCG_TOP_DISABLED 0x00000001 /* */
#define NV_SOE_MISC_TOP_CG 0x0840 /* RW-4R */
#define NV_SOE_MISC_TOP_CG_IDLE_CG_DLY_CNT 5:0 /* RWIVF */
#define NV_SOE_MISC_TOP_CG_IDLE_CG_DLY_CNT_INIT 0x0000001f /* RWI-V */
#endif // __ls10_dev_soe_ip_h__

60
src/common/inc/swref/published/nvswitch/ls10/dev_soe_ip_addendum.h Normal file
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@@ -0,0 +1,60 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the Software),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __ls10_dev_soe_ip_addendum_h__
#define __ls10_dev_soe_ip_addendum_h__
#define NV_SOE_MUTEX_DEFINES \
NV_MUTEX_ID_SOE_EMEM_ACCESS, \
#define NV_SOE_EMEM_ACCESS_PORT_NVSWITCH (0)
#define NV_SOE_EMEM_ACCESS_PORT_NVWATCH (1)
#define UNUSED_EMEM_ACCESS_PORT_2 (2)
#define UNUSED_EMEM_ACCESS_PORT_3 (3)
#define NUM_SAW_ENGINE 1
#define NUM_NVLINK_ENGINE 9
#define NUM_TLC_ENGINE 64
#define NUM_NVLIPT_LNK_ENGINE 64
#define NUM_NPG_ENGINE 16
#define NUM_NPG_BCAST_ENGINE 1
#define NUM_NPORT_ENGINE 64
#define NUM_NPORT_MULTICAST_BCAST_ENGINE 1
#define NUM_NXBAR_ENGINE 3
#define NUM_NXBAR_BCAST_ENGINE 1
#define NUM_TILE_ENGINE 36
#define NUM_TILE_MULTICAST_BCAST_ENGINE 1
#define NUM_NVLW_ENGINE 16
#define NUM_BUS_ENGINE 1
#define NUM_GIN_ENGINE 1
#define NUM_MINION_ENGINE NUM_NVLW_ENGINE
#define NUM_MINION_BCAST_ENGINE 1
#define NUM_NVLIPT_ENGINE NUM_NVLW_ENGINE
#define NUM_NVLIPT_BCAST_ENGINE 1
#define NUM_SYS_PRI_HUB 1
#define NUM_PRI_MASTER_RS 1
#define NUM_LINKS_PER_MINION (NUM_NPORT_ENGINE / NUM_MINION_ENGINE)
#endif // __ls10_dev_soe_ip_addendum_h__

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src/common/inc/swref/published/nvswitch/ls10/dev_sourcetrack_ip.h Normal file
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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the Software),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __ls10_dev_sourcetrack_ip_h__
#define __ls10_dev_sourcetrack_ip_h__
/* This file is autogenerated. Do not edit */
#define NV_SOURCETRACK 0x00006fff:0x00006000 /* RW--D */
#define NV_SOURCETRACK_CTRL 0x00006040 /* RW-4R */
#define NV_SOURCETRACK_CTRL_COL_RSP_DIS 0:0 /* RWEVF */
#define NV_SOURCETRACK_CTRL_COL_RSP_DIS_DISABLED 0x00000000 /* RWE-V */
#define NV_SOURCETRACK_CTRL_COL_RSP_DIS_ENABLED 0x00000001 /* RW--V */
#define NV_SOURCETRACK_CTRL_STO_ENB 9:9 /* RWEVF */
#define NV_SOURCETRACK_CTRL_STO_ENB_ENABLED 0x00000001 /* RWE-V */
#define NV_SOURCETRACK_CTRL_STO_ENB_DISABLED 0x00000000 /* RW--V */
#define NV_SOURCETRACK_MULTISEC_TIMER0 0x00006044 /* RW-4R */
#define NV_SOURCETRACK_MULTISEC_TIMER0_TIMERVAL0 19:0 /* RWEVF */
#define NV_SOURCETRACK_MULTISEC_TIMER0_TIMERVAL0_INIT 0x00003e80 /* RWE-V */
#define NV_SOURCETRACK_ERR_STATUS_0 0x00006400 /* RW-4R */
#define NV_SOURCETRACK_ERR_STATUS_0_CREQ_TCEN0_CRUMBSTORE_ECC_LIMIT_ERR 0:0 /* RWDVF */
#define NV_SOURCETRACK_ERR_STATUS_0_CREQ_TCEN0_CRUMBSTORE_ECC_LIMIT_ERR__ONWRITE "oneToClear" /* */
#define NV_SOURCETRACK_ERR_STATUS_0_CREQ_TCEN0_CRUMBSTORE_ECC_LIMIT_ERR_NONE 0x00000000 /* RWD-V */
#define NV_SOURCETRACK_ERR_STATUS_0_CREQ_TCEN0_CRUMBSTORE_ECC_LIMIT_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_SOURCETRACK_ERR_STATUS_0_CREQ_TCEN0_CRUMBSTORE_ECC_DBE_ERR 1:1 /* RWDVF */
#define NV_SOURCETRACK_ERR_STATUS_0_CREQ_TCEN0_CRUMBSTORE_ECC_DBE_ERR__ONWRITE "oneToClear" /* */
#define NV_SOURCETRACK_ERR_STATUS_0_CREQ_TCEN0_CRUMBSTORE_ECC_DBE_ERR_NONE 0x00000000 /* RWD-V */
#define NV_SOURCETRACK_ERR_STATUS_0_CREQ_TCEN0_CRUMBSTORE_ECC_DBE_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_SOURCETRACK_ERR_STATUS_0_DUP_CREQ_TCEN0_TAG_ERR 2:2 /* RWDVF */
#define NV_SOURCETRACK_ERR_STATUS_0_DUP_CREQ_TCEN0_TAG_ERR__ONWRITE "oneToClear" /* */
#define NV_SOURCETRACK_ERR_STATUS_0_DUP_CREQ_TCEN0_TAG_ERR_NONE 0x00000000 /* RWD-V */
#define NV_SOURCETRACK_ERR_STATUS_0_DUP_CREQ_TCEN0_TAG_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_SOURCETRACK_ERR_STATUS_0_INVALID_TCEN0_RSP_ERR 3:3 /* RWDVF */
#define NV_SOURCETRACK_ERR_STATUS_0_INVALID_TCEN0_RSP_ERR__ONWRITE "oneToClear" /* */
#define NV_SOURCETRACK_ERR_STATUS_0_INVALID_TCEN0_RSP_ERR_NONE 0x00000000 /* RWD-V */
#define NV_SOURCETRACK_ERR_STATUS_0_INVALID_TCEN0_RSP_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_SOURCETRACK_ERR_STATUS_0_INVALID_TCEN1_RSP_ERR 4:4 /* RWDVF */
#define NV_SOURCETRACK_ERR_STATUS_0_INVALID_TCEN1_RSP_ERR__ONWRITE "oneToClear" /* */
#define NV_SOURCETRACK_ERR_STATUS_0_INVALID_TCEN1_RSP_ERR_NONE 0x00000000 /* RWD-V */
#define NV_SOURCETRACK_ERR_STATUS_0_INVALID_TCEN1_RSP_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_SOURCETRACK_ERR_STATUS_0_SOURCETRACK_TIME_OUT_ERR 5:5 /* RWDVF */
#define NV_SOURCETRACK_ERR_STATUS_0_SOURCETRACK_TIME_OUT_ERR__ONWRITE "oneToClear" /* */
#define NV_SOURCETRACK_ERR_STATUS_0_SOURCETRACK_TIME_OUT_ERR_NONE 0x00000000 /* RWD-V */
#define NV_SOURCETRACK_ERR_STATUS_0_SOURCETRACK_TIME_OUT_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_SOURCETRACK_ERR_LOG_EN_0 0x00006404 /* RW-4R */
#define NV_SOURCETRACK_ERR_LOG_EN_0_CREQ_TCEN0_CRUMBSTORE_ECC_LIMIT_ERR 0:0 /* RWEVF */
#define NV_SOURCETRACK_ERR_LOG_EN_0_CREQ_TCEN0_CRUMBSTORE_ECC_LIMIT_ERR__PROD 0x00000001 /* RW--V */
#define NV_SOURCETRACK_ERR_LOG_EN_0_CREQ_TCEN0_CRUMBSTORE_ECC_LIMIT_ERR__TPROD 0x00000000 /* RW--V */
#define NV_SOURCETRACK_ERR_LOG_EN_0_CREQ_TCEN0_CRUMBSTORE_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_SOURCETRACK_ERR_LOG_EN_0_CREQ_TCEN0_CRUMBSTORE_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_SOURCETRACK_ERR_LOG_EN_0_CREQ_TCEN0_CRUMBSTORE_ECC_DBE_ERR 1:1 /* RWEVF */
#define NV_SOURCETRACK_ERR_LOG_EN_0_CREQ_TCEN0_CRUMBSTORE_ECC_DBE_ERR__PROD 0x00000001 /* RW--V */
#define NV_SOURCETRACK_ERR_LOG_EN_0_CREQ_TCEN0_CRUMBSTORE_ECC_DBE_ERR__TPROD 0x00000000 /* RW--V */
#define NV_SOURCETRACK_ERR_LOG_EN_0_CREQ_TCEN0_CRUMBSTORE_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_SOURCETRACK_ERR_LOG_EN_0_CREQ_TCEN0_CRUMBSTORE_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_SOURCETRACK_ERR_LOG_EN_0_DUP_CREQ_TCEN0_TAG_ERR 2:2 /* RWEVF */
#define NV_SOURCETRACK_ERR_LOG_EN_0_DUP_CREQ_TCEN0_TAG_ERR__PROD 0x00000001 /* RW--V */
#define NV_SOURCETRACK_ERR_LOG_EN_0_DUP_CREQ_TCEN0_TAG_ERR__TPROD 0x00000000 /* RW--V */
#define NV_SOURCETRACK_ERR_LOG_EN_0_DUP_CREQ_TCEN0_TAG_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_SOURCETRACK_ERR_LOG_EN_0_DUP_CREQ_TCEN0_TAG_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_SOURCETRACK_ERR_LOG_EN_0_INVALID_TCEN0_RSP_ERR 3:3 /* RWEVF */
#define NV_SOURCETRACK_ERR_LOG_EN_0_INVALID_TCEN0_RSP_ERR__PROD 0x00000001 /* RW--V */
#define NV_SOURCETRACK_ERR_LOG_EN_0_INVALID_TCEN0_RSP_ERR__TPROD 0x00000000 /* RW--V */
#define NV_SOURCETRACK_ERR_LOG_EN_0_INVALID_TCEN0_RSP_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_SOURCETRACK_ERR_LOG_EN_0_INVALID_TCEN0_RSP_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_SOURCETRACK_ERR_LOG_EN_0_INVALID_TCEN1_RSP_ERR 4:4 /* RWEVF */
#define NV_SOURCETRACK_ERR_LOG_EN_0_INVALID_TCEN1_RSP_ERR__PROD 0x00000001 /* RW--V */
#define NV_SOURCETRACK_ERR_LOG_EN_0_INVALID_TCEN1_RSP_ERR__TPROD 0x00000000 /* RW--V */
#define NV_SOURCETRACK_ERR_LOG_EN_0_INVALID_TCEN1_RSP_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_SOURCETRACK_ERR_LOG_EN_0_INVALID_TCEN1_RSP_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_SOURCETRACK_ERR_LOG_EN_0_SOURCETRACK_TIME_OUT_ERR 5:5 /* RWEVF */
#define NV_SOURCETRACK_ERR_LOG_EN_0_SOURCETRACK_TIME_OUT_ERR__PROD 0x00000001 /* RW--V */
#define NV_SOURCETRACK_ERR_LOG_EN_0_SOURCETRACK_TIME_OUT_ERR__TPROD 0x00000000 /* RW--V */
#define NV_SOURCETRACK_ERR_LOG_EN_0_SOURCETRACK_TIME_OUT_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_SOURCETRACK_ERR_LOG_EN_0_SOURCETRACK_TIME_OUT_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_SOURCETRACK_ERR_FATAL_REPORT_EN_0 0x00006408 /* RW-4R */
#define NV_SOURCETRACK_ERR_FATAL_REPORT_EN_0_CREQ_TCEN0_CRUMBSTORE_ECC_LIMIT_ERR 0:0 /* RWEVF */
#define NV_SOURCETRACK_ERR_FATAL_REPORT_EN_0_CREQ_TCEN0_CRUMBSTORE_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_SOURCETRACK_ERR_FATAL_REPORT_EN_0_CREQ_TCEN0_CRUMBSTORE_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_SOURCETRACK_ERR_FATAL_REPORT_EN_0_CREQ_TCEN0_CRUMBSTORE_ECC_DBE_ERR 1:1 /* RWEVF */
#define NV_SOURCETRACK_ERR_FATAL_REPORT_EN_0_CREQ_TCEN0_CRUMBSTORE_ECC_DBE_ERR__PROD 0x00000001 /* RW--V */
#define NV_SOURCETRACK_ERR_FATAL_REPORT_EN_0_CREQ_TCEN0_CRUMBSTORE_ECC_DBE_ERR__TPROD 0x00000000 /* RW--V */
#define NV_SOURCETRACK_ERR_FATAL_REPORT_EN_0_CREQ_TCEN0_CRUMBSTORE_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_SOURCETRACK_ERR_FATAL_REPORT_EN_0_CREQ_TCEN0_CRUMBSTORE_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_SOURCETRACK_ERR_FATAL_REPORT_EN_0_DUP_CREQ_TCEN0_TAG_ERR 2:2 /* RWEVF */
#define NV_SOURCETRACK_ERR_FATAL_REPORT_EN_0_DUP_CREQ_TCEN0_TAG_ERR__PROD 0x00000001 /* RW--V */
#define NV_SOURCETRACK_ERR_FATAL_REPORT_EN_0_DUP_CREQ_TCEN0_TAG_ERR__TPROD 0x00000000 /* RW--V */
#define NV_SOURCETRACK_ERR_FATAL_REPORT_EN_0_DUP_CREQ_TCEN0_TAG_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_SOURCETRACK_ERR_FATAL_REPORT_EN_0_DUP_CREQ_TCEN0_TAG_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_SOURCETRACK_ERR_FATAL_REPORT_EN_0_INVALID_TCEN0_RSP_ERR 3:3 /* RWEVF */
#define NV_SOURCETRACK_ERR_FATAL_REPORT_EN_0_INVALID_TCEN0_RSP_ERR__PROD 0x00000001 /* RW--V */
#define NV_SOURCETRACK_ERR_FATAL_REPORT_EN_0_INVALID_TCEN0_RSP_ERR__TPROD 0x00000000 /* RW--V */
#define NV_SOURCETRACK_ERR_FATAL_REPORT_EN_0_INVALID_TCEN0_RSP_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_SOURCETRACK_ERR_FATAL_REPORT_EN_0_INVALID_TCEN0_RSP_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_SOURCETRACK_ERR_FATAL_REPORT_EN_0_INVALID_TCEN1_RSP_ERR 4:4 /* RWEVF */
#define NV_SOURCETRACK_ERR_FATAL_REPORT_EN_0_INVALID_TCEN1_RSP_ERR__PROD 0x00000001 /* RW--V */
#define NV_SOURCETRACK_ERR_FATAL_REPORT_EN_0_INVALID_TCEN1_RSP_ERR__TPROD 0x00000000 /* RW--V */
#define NV_SOURCETRACK_ERR_FATAL_REPORT_EN_0_INVALID_TCEN1_RSP_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_SOURCETRACK_ERR_FATAL_REPORT_EN_0_INVALID_TCEN1_RSP_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_SOURCETRACK_ERR_FATAL_REPORT_EN_0_SOURCETRACK_TIME_OUT_ERR 5:5 /* RWEVF */
#define NV_SOURCETRACK_ERR_FATAL_REPORT_EN_0_SOURCETRACK_TIME_OUT_ERR__PROD 0x00000001 /* RW--V */
#define NV_SOURCETRACK_ERR_FATAL_REPORT_EN_0_SOURCETRACK_TIME_OUT_ERR__TPROD 0x00000000 /* RW--V */
#define NV_SOURCETRACK_ERR_FATAL_REPORT_EN_0_SOURCETRACK_TIME_OUT_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_SOURCETRACK_ERR_FATAL_REPORT_EN_0_SOURCETRACK_TIME_OUT_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_SOURCETRACK_ERR_NON_FATAL_REPORT_EN_0 0x0000640c /* RW-4R */
#define NV_SOURCETRACK_ERR_NON_FATAL_REPORT_EN_0_CREQ_TCEN0_CRUMBSTORE_ECC_LIMIT_ERR 0:0 /* RWEVF */
#define NV_SOURCETRACK_ERR_NON_FATAL_REPORT_EN_0_CREQ_TCEN0_CRUMBSTORE_ECC_LIMIT_ERR__PROD 0x00000001 /* RW--V */
#define NV_SOURCETRACK_ERR_NON_FATAL_REPORT_EN_0_CREQ_TCEN0_CRUMBSTORE_ECC_LIMIT_ERR__TPROD 0x00000000 /* RW--V */
#define NV_SOURCETRACK_ERR_NON_FATAL_REPORT_EN_0_CREQ_TCEN0_CRUMBSTORE_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_SOURCETRACK_ERR_NON_FATAL_REPORT_EN_0_CREQ_TCEN0_CRUMBSTORE_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_SOURCETRACK_ERR_NON_FATAL_REPORT_EN_0_CREQ_TCEN0_CRUMBSTORE_ECC_DBE_ERR 1:1 /* RWEVF */
#define NV_SOURCETRACK_ERR_NON_FATAL_REPORT_EN_0_CREQ_TCEN0_CRUMBSTORE_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_SOURCETRACK_ERR_NON_FATAL_REPORT_EN_0_CREQ_TCEN0_CRUMBSTORE_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_SOURCETRACK_ERR_NON_FATAL_REPORT_EN_0_DUP_CREQ_TCEN0_TAG_ERR 2:2 /* RWEVF */
#define NV_SOURCETRACK_ERR_NON_FATAL_REPORT_EN_0_DUP_CREQ_TCEN0_TAG_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_SOURCETRACK_ERR_NON_FATAL_REPORT_EN_0_DUP_CREQ_TCEN0_TAG_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_SOURCETRACK_ERR_NON_FATAL_REPORT_EN_0_INVALID_TCEN0_RSP_ERR 3:3 /* RWEVF */
#define NV_SOURCETRACK_ERR_NON_FATAL_REPORT_EN_0_INVALID_TCEN0_RSP_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_SOURCETRACK_ERR_NON_FATAL_REPORT_EN_0_INVALID_TCEN0_RSP_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_SOURCETRACK_ERR_NON_FATAL_REPORT_EN_0_INVALID_TCEN1_RSP_ERR 4:4 /* RWEVF */
#define NV_SOURCETRACK_ERR_NON_FATAL_REPORT_EN_0_INVALID_TCEN1_RSP_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_SOURCETRACK_ERR_NON_FATAL_REPORT_EN_0_INVALID_TCEN1_RSP_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_SOURCETRACK_ERR_NON_FATAL_REPORT_EN_0_SOURCETRACK_TIME_OUT_ERR 5:5 /* RWEVF */
#define NV_SOURCETRACK_ERR_NON_FATAL_REPORT_EN_0_SOURCETRACK_TIME_OUT_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_SOURCETRACK_ERR_NON_FATAL_REPORT_EN_0_SOURCETRACK_TIME_OUT_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_SOURCETRACK_ERR_CORRECTABLE_REPORT_EN_0 0x00006410 /* RW-4R */
#define NV_SOURCETRACK_ERR_CONTAIN_EN_0 0x00006414 /* RW-4R */
#define NV_SOURCETRACK_ERR_CONTAIN_EN_0_CREQ_TCEN0_CRUMBSTORE_ECC_LIMIT_ERR 0:0 /* RWEVF */
#define NV_SOURCETRACK_ERR_CONTAIN_EN_0_CREQ_TCEN0_CRUMBSTORE_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_SOURCETRACK_ERR_CONTAIN_EN_0_CREQ_TCEN0_CRUMBSTORE_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_SOURCETRACK_ERR_CONTAIN_EN_0_CREQ_TCEN0_CRUMBSTORE_ECC_DBE_ERR 1:1 /* RWEVF */
#define NV_SOURCETRACK_ERR_CONTAIN_EN_0_CREQ_TCEN0_CRUMBSTORE_ECC_DBE_ERR__PROD 0x00000001 /* RW--V */
#define NV_SOURCETRACK_ERR_CONTAIN_EN_0_CREQ_TCEN0_CRUMBSTORE_ECC_DBE_ERR__TPROD 0x00000000 /* RW--V */
#define NV_SOURCETRACK_ERR_CONTAIN_EN_0_CREQ_TCEN0_CRUMBSTORE_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_SOURCETRACK_ERR_CONTAIN_EN_0_CREQ_TCEN0_CRUMBSTORE_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_SOURCETRACK_ERR_CONTAIN_EN_0_DUP_CREQ_TCEN0_TAG_ERR 2:2 /* RWEVF */
#define NV_SOURCETRACK_ERR_CONTAIN_EN_0_DUP_CREQ_TCEN0_TAG_ERR__PROD 0x00000001 /* RW--V */
#define NV_SOURCETRACK_ERR_CONTAIN_EN_0_DUP_CREQ_TCEN0_TAG_ERR__TPROD 0x00000000 /* RW--V */
#define NV_SOURCETRACK_ERR_CONTAIN_EN_0_DUP_CREQ_TCEN0_TAG_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_SOURCETRACK_ERR_CONTAIN_EN_0_DUP_CREQ_TCEN0_TAG_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_SOURCETRACK_ERR_CONTAIN_EN_0_INVALID_TCEN0_RSP_ERR 3:3 /* RWEVF */
#define NV_SOURCETRACK_ERR_CONTAIN_EN_0_INVALID_TCEN0_RSP_ERR__PROD 0x00000001 /* RW--V */
#define NV_SOURCETRACK_ERR_CONTAIN_EN_0_INVALID_TCEN0_RSP_ERR__TPROD 0x00000000 /* RW--V */
#define NV_SOURCETRACK_ERR_CONTAIN_EN_0_INVALID_TCEN0_RSP_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_SOURCETRACK_ERR_CONTAIN_EN_0_INVALID_TCEN0_RSP_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_SOURCETRACK_ERR_CONTAIN_EN_0_INVALID_TCEN1_RSP_ERR 4:4 /* RWEVF */
#define NV_SOURCETRACK_ERR_CONTAIN_EN_0_INVALID_TCEN1_RSP_ERR__PROD 0x00000001 /* RW--V */
#define NV_SOURCETRACK_ERR_CONTAIN_EN_0_INVALID_TCEN1_RSP_ERR__TPROD 0x00000000 /* RW--V */
#define NV_SOURCETRACK_ERR_CONTAIN_EN_0_INVALID_TCEN1_RSP_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_SOURCETRACK_ERR_CONTAIN_EN_0_INVALID_TCEN1_RSP_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_SOURCETRACK_ERR_CONTAIN_EN_0_SOURCETRACK_TIME_OUT_ERR 5:5 /* RWEVF */
#define NV_SOURCETRACK_ERR_CONTAIN_EN_0_SOURCETRACK_TIME_OUT_ERR__PROD 0x00000001 /* RW--V */
#define NV_SOURCETRACK_ERR_CONTAIN_EN_0_SOURCETRACK_TIME_OUT_ERR__TPROD 0x00000000 /* RW--V */
#define NV_SOURCETRACK_ERR_CONTAIN_EN_0_SOURCETRACK_TIME_OUT_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_SOURCETRACK_ERR_CONTAIN_EN_0_SOURCETRACK_TIME_OUT_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_SOURCETRACK_ERR_FIRST_0 0x0000641c /* RW-4R */
#define NV_SOURCETRACK_ERR_FIRST_0_CREQ_TCEN0_CRUMBSTORE_ECC_LIMIT_ERR 0:0 /* RWDVF */
#define NV_SOURCETRACK_ERR_FIRST_0_CREQ_TCEN0_CRUMBSTORE_ECC_LIMIT_ERR__ONWRITE "oneToClear" /* */
#define NV_SOURCETRACK_ERR_FIRST_0_CREQ_TCEN0_CRUMBSTORE_ECC_LIMIT_ERR_NONE 0x00000000 /* RWD-V */
#define NV_SOURCETRACK_ERR_FIRST_0_CREQ_TCEN0_CRUMBSTORE_ECC_LIMIT_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_SOURCETRACK_ERR_FIRST_0_CREQ_TCEN0_CRUMBSTORE_ECC_DBE_ERR 1:1 /* RWDVF */
#define NV_SOURCETRACK_ERR_FIRST_0_CREQ_TCEN0_CRUMBSTORE_ECC_DBE_ERR__ONWRITE "oneToClear" /* */
#define NV_SOURCETRACK_ERR_FIRST_0_CREQ_TCEN0_CRUMBSTORE_ECC_DBE_ERR_NONE 0x00000000 /* RWD-V */
#define NV_SOURCETRACK_ERR_FIRST_0_CREQ_TCEN0_CRUMBSTORE_ECC_DBE_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_SOURCETRACK_ERR_FIRST_0_DUP_CREQ_TCEN0_TAG_ERR 2:2 /* RWDVF */
#define NV_SOURCETRACK_ERR_FIRST_0_DUP_CREQ_TCEN0_TAG_ERR__ONWRITE "oneToClear" /* */
#define NV_SOURCETRACK_ERR_FIRST_0_DUP_CREQ_TCEN0_TAG_ERR_NONE 0x00000000 /* RWD-V */
#define NV_SOURCETRACK_ERR_FIRST_0_DUP_CREQ_TCEN0_TAG_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_SOURCETRACK_ERR_FIRST_0_INVALID_TCEN0_RSP_ERR 3:3 /* RWDVF */
#define NV_SOURCETRACK_ERR_FIRST_0_INVALID_TCEN0_RSP_ERR__ONWRITE "oneToClear" /* */
#define NV_SOURCETRACK_ERR_FIRST_0_INVALID_TCEN0_RSP_ERR_NONE 0x00000000 /* RWD-V */
#define NV_SOURCETRACK_ERR_FIRST_0_INVALID_TCEN0_RSP_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_SOURCETRACK_ERR_FIRST_0_INVALID_TCEN1_RSP_ERR 4:4 /* RWDVF */
#define NV_SOURCETRACK_ERR_FIRST_0_INVALID_TCEN1_RSP_ERR__ONWRITE "oneToClear" /* */
#define NV_SOURCETRACK_ERR_FIRST_0_INVALID_TCEN1_RSP_ERR_NONE 0x00000000 /* RWD-V */
#define NV_SOURCETRACK_ERR_FIRST_0_INVALID_TCEN1_RSP_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_SOURCETRACK_ERR_FIRST_0_SOURCETRACK_TIME_OUT_ERR 5:5 /* RWDVF */
#define NV_SOURCETRACK_ERR_FIRST_0_SOURCETRACK_TIME_OUT_ERR__ONWRITE "oneToClear" /* */
#define NV_SOURCETRACK_ERR_FIRST_0_SOURCETRACK_TIME_OUT_ERR_NONE 0x00000000 /* RWD-V */
#define NV_SOURCETRACK_ERR_FIRST_0_SOURCETRACK_TIME_OUT_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_SOURCETRACK_ERR_ECC_CTRL 0x00006470 /* RW-4R */
#define NV_SOURCETRACK_ERR_ECC_CTRL_CREQ_TCEN0_CRUMBSTORE_ECC_ENABLE 0:0 /* RWEVF */
#define NV_SOURCETRACK_ERR_ECC_CTRL_CREQ_TCEN0_CRUMBSTORE_ECC_ENABLE_ENABLE 0x00000001 /* RW--V */
#define NV_SOURCETRACK_ERR_ECC_CTRL_CREQ_TCEN0_CRUMBSTORE_ECC_ENABLE_DISABLE 0x00000000 /* RWE-V */
#define NV_SOURCETRACK_ERR_ECC_CTRL_CREQ_TCEN0_CRUMBSTORE_ECC_ENABLE__PROD 0x00000001 /* RW--V */
#define NV_SOURCETRACK_ERR_CREQ_TCEN0_CRUMBSTORE_ECC_ERROR_COUNTER 0x00006480 /* RW-4R */
#define NV_SOURCETRACK_ERR_CREQ_TCEN0_CRUMBSTORE_ECC_ERROR_COUNTER_ERROR_COUNT 23:0 /* RWDVF */
#define NV_SOURCETRACK_ERR_CREQ_TCEN0_CRUMBSTORE_ECC_ERROR_COUNTER_ERROR_COUNT_INIT 0x00000000 /* RWD-V */
#define NV_SOURCETRACK_ERR_CREQ_TCEN0_CRUMBSTORE_ECC_ERROR_COUNTER_LIMIT 0x00006484 /* RW-4R */
#define NV_SOURCETRACK_ERR_CREQ_TCEN0_CRUMBSTORE_ECC_ERROR_COUNTER_LIMIT_ERROR_LIMIT 23:0 /* RWDVF */
#define NV_SOURCETRACK_ERR_CREQ_TCEN0_CRUMBSTORE_ECC_ERROR_COUNTER_LIMIT_ERROR_LIMIT_INIT 0x00ffffff /* RWD-V */
#define NV_SOURCETRACK_ERR_CREQ_TCEN0_CRUMBSTORE_ECC_ERROR_ADDRESS 0x00006488 /* R--4R */
#define NV_SOURCETRACK_ERR_CREQ_TCEN0_CRUMBSTORE_ECC_ERROR_ADDRESS_ERROR_ADDRESS 9:0 /* R-DVF */
#define NV_SOURCETRACK_ERR_CREQ_TCEN0_CRUMBSTORE_ECC_ERROR_ADDRESS_ERROR_ADDRESS_INIT 0x00000000 /* R-D-V */
#define NV_SOURCETRACK_ERR_CREQ_TCEN0_CRUMBSTORE_ECC_ERROR_ADDRESS_VALID 0x0000648c /* R--4R */
#define NV_SOURCETRACK_ERR_CREQ_TCEN0_CRUMBSTORE_ECC_ERROR_ADDRESS_VALID_VALID 0:0 /* R-DVF */
#define NV_SOURCETRACK_ERR_CREQ_TCEN0_CRUMBSTORE_ECC_ERROR_ADDRESS_VALID_VALID_INVALID 0x00000000 /* R-D-V */
#define NV_SOURCETRACK_ERR_CREQ_TCEN0_CRUMBSTORE_ECC_ERROR_ADDRESS_VALID_VALID_VALID 0x00000001 /* R---V */
#endif // __ls10_dev_sourcetrack_ip_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the Software),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __ls10_dev_therm_h__
#define __ls10_dev_therm_h__
/* This file is autogenerated. Do not edit */
#define NV_THERM 0x067fff:0x066000 /* RW--D */
#define NV_THERM_I2CS_SCRATCH 0x000660bc /* RW-4R */
#define NV_THERM_I2CS_SCRATCH_DATA 31:0 /* RWIVF */
#define NV_THERM_I2CS_SCRATCH_DATA_INIT 0x00000000 /* RWI-V */
#define NV_THERM_TSENSE_U2_A_0_BJT_0 0x00066f10 /* RW-4R */
#define NV_THERM_TSENSE_U2_A_0_BJT_0_TEMPERATURE 13:0 /* R-IVF */
#define NV_THERM_TSENSE_U2_A_0_BJT_0_TEMPERATURE_INIT 0x00000000 /* RWI-V */
#define NV_THERM_TSENSE_U2_A_0_BJT_0_SOURCE 16:16 /* R-IVF */
#define NV_THERM_TSENSE_U2_A_0_BJT_0_SOURCE_INIT 0x00000000 /* RWI-V */
#define NV_THERM_TSENSE_U2_A_0_BJT_0_TEMPERATURE_VALID 30:30 /* R-IVF */
#define NV_THERM_TSENSE_U2_A_0_BJT_0_TEMPERATURE_VALID_INIT 0x00000000 /* RWI-V */
#define NV_THERM_TSENSE_U2_A_0_BJT_0_TEMPERATURE_EN 31:31 /* RWIVF */
#define NV_THERM_TSENSE_U2_A_0_BJT_0_TEMPERATURE_EN_INIT 0x00000001 /* RWI-V */
#define NV_THERM_TSENSE_U2_A_0_BJT_1 0x00066f14 /* RW-4R */
#define NV_THERM_TSENSE_U2_A_0_BJT_1_TEMPERATURE 13:0 /* R-IVF */
#define NV_THERM_TSENSE_U2_A_0_BJT_1_TEMPERATURE_INIT 0x00000000 /* RWI-V */
#define NV_THERM_TSENSE_U2_A_0_BJT_1_SOURCE 16:16 /* R-IVF */
#define NV_THERM_TSENSE_U2_A_0_BJT_1_SOURCE_INIT 0x00000000 /* RWI-V */
#define NV_THERM_TSENSE_U2_A_0_BJT_1_TEMPERATURE_VALID 30:30 /* R-IVF */
#define NV_THERM_TSENSE_U2_A_0_BJT_1_TEMPERATURE_VALID_INIT 0x00000000 /* RWI-V */
#define NV_THERM_TSENSE_U2_A_0_BJT_1_TEMPERATURE_EN 31:31 /* RWIVF */
#define NV_THERM_TSENSE_U2_A_0_BJT_1_TEMPERATURE_EN_INIT 0x00000001 /* RWI-V */
#define NV_THERM_TSENSE_U2_A_0_BJT_2 0x00066f18 /* RW-4R */
#define NV_THERM_TSENSE_U2_A_0_BJT_2_TEMPERATURE 13:0 /* R-IVF */
#define NV_THERM_TSENSE_U2_A_0_BJT_2_TEMPERATURE_INIT 0x00000000 /* RWI-V */
#define NV_THERM_TSENSE_U2_A_0_BJT_2_SOURCE 16:16 /* R-IVF */
#define NV_THERM_TSENSE_U2_A_0_BJT_2_SOURCE_INIT 0x00000000 /* RWI-V */
#define NV_THERM_TSENSE_U2_A_0_BJT_2_TEMPERATURE_VALID 30:30 /* R-IVF */
#define NV_THERM_TSENSE_U2_A_0_BJT_2_TEMPERATURE_VALID_INIT 0x00000000 /* RWI-V */
#define NV_THERM_TSENSE_U2_A_0_BJT_2_TEMPERATURE_EN 31:31 /* RWIVF */
#define NV_THERM_TSENSE_U2_A_0_BJT_2_TEMPERATURE_EN_INIT 0x00000001 /* RWI-V */
#define NV_THERM_TSENSE_U2_A_0_BJT_3 0x00066f1c /* RW-4R */
#define NV_THERM_TSENSE_U2_A_0_BJT_3_TEMPERATURE 13:0 /* R-IVF */
#define NV_THERM_TSENSE_U2_A_0_BJT_3_TEMPERATURE_INIT 0x00000000 /* RWI-V */
#define NV_THERM_TSENSE_U2_A_0_BJT_3_SOURCE 16:16 /* R-IVF */
#define NV_THERM_TSENSE_U2_A_0_BJT_3_SOURCE_INIT 0x00000000 /* RWI-V */
#define NV_THERM_TSENSE_U2_A_0_BJT_3_TEMPERATURE_VALID 30:30 /* R-IVF */
#define NV_THERM_TSENSE_U2_A_0_BJT_3_TEMPERATURE_VALID_INIT 0x00000000 /* RWI-V */
#define NV_THERM_TSENSE_U2_A_0_BJT_3_TEMPERATURE_EN 31:31 /* RWIVF */
#define NV_THERM_TSENSE_U2_A_0_BJT_3_TEMPERATURE_EN_INIT 0x00000001 /* RWI-V */
#define NV_THERM_TSENSE_U2_A_0_BJT_4 0x00066f20 /* RW-4R */
#define NV_THERM_TSENSE_U2_A_0_BJT_4_TEMPERATURE 13:0 /* R-IVF */
#define NV_THERM_TSENSE_U2_A_0_BJT_4_TEMPERATURE_INIT 0x00000000 /* RWI-V */
#define NV_THERM_TSENSE_U2_A_0_BJT_4_SOURCE 16:16 /* R-IVF */
#define NV_THERM_TSENSE_U2_A_0_BJT_4_SOURCE_INIT 0x00000000 /* RWI-V */
#define NV_THERM_TSENSE_U2_A_0_BJT_4_TEMPERATURE_VALID 30:30 /* R-IVF */
#define NV_THERM_TSENSE_U2_A_0_BJT_4_TEMPERATURE_VALID_INIT 0x00000000 /* RWI-V */
#define NV_THERM_TSENSE_U2_A_0_BJT_4_TEMPERATURE_EN 31:31 /* RWIVF */
#define NV_THERM_TSENSE_U2_A_0_BJT_4_TEMPERATURE_EN_INIT 0x00000001 /* RWI-V */
#define NV_THERM_TSENSE_U2_A_0_BJT_5 0x00066f24 /* RW-4R */
#define NV_THERM_TSENSE_U2_A_0_BJT_5_TEMPERATURE 13:0 /* R-IVF */
#define NV_THERM_TSENSE_U2_A_0_BJT_5_TEMPERATURE_INIT 0x00000000 /* RWI-V */
#define NV_THERM_TSENSE_U2_A_0_BJT_5_SOURCE 16:16 /* R-IVF */
#define NV_THERM_TSENSE_U2_A_0_BJT_5_SOURCE_INIT 0x00000000 /* RWI-V */
#define NV_THERM_TSENSE_U2_A_0_BJT_5_TEMPERATURE_VALID 30:30 /* R-IVF */
#define NV_THERM_TSENSE_U2_A_0_BJT_5_TEMPERATURE_VALID_INIT 0x00000000 /* RWI-V */
#define NV_THERM_TSENSE_U2_A_0_BJT_5_TEMPERATURE_EN 31:31 /* RWIVF */
#define NV_THERM_TSENSE_U2_A_0_BJT_5_TEMPERATURE_EN_INIT 0x00000001 /* RWI-V */
#define NV_THERM_TSENSE_U2_A_0_BJT_0_TEMPERATURE_MODIFICATIONS 0x00066f28 /* RW-4R */
#define NV_THERM_TSENSE_U2_A_0_BJT_0_TEMPERATURE_MODIFICATIONS_TEMPERATURE_OFFSET 13:0 /* RWIVF */
#define NV_THERM_TSENSE_U2_A_0_BJT_0_TEMPERATURE_MODIFICATIONS_TEMPERATURE_OFFSET_INIT 0x00000000 /* RWI-V */
#define NV_THERM_TSENSE_U2_A_0_BJT_0_TEMPERATURE_MODIFICATIONS_TEMPERATURE_OVERRIDE 29:16 /* RWIVF */
#define NV_THERM_TSENSE_U2_A_0_BJT_0_TEMPERATURE_MODIFICATIONS_TEMPERATURE_OVERRIDE_INIT 0x00000000 /* RWI-V */
#define NV_THERM_TSENSE_U2_A_0_BJT_0_TEMPERATURE_MODIFICATIONS_TEMPERATURE_OVERRIDE_EN 31:31 /* RWIVF */
#define NV_THERM_TSENSE_U2_A_0_BJT_0_TEMPERATURE_MODIFICATIONS_TEMPERATURE_OVERRIDE_EN_INIT 0x00000000 /* RWI-V */
#define NV_THERM_TSENSE_U2_A_0_BJT_1_TEMPERATURE_MODIFICATIONS 0x00066f2c /* RW-4R */
#define NV_THERM_TSENSE_U2_A_0_BJT_1_TEMPERATURE_MODIFICATIONS_TEMPERATURE_OFFSET 13:0 /* RWIVF */
#define NV_THERM_TSENSE_U2_A_0_BJT_1_TEMPERATURE_MODIFICATIONS_TEMPERATURE_OFFSET_INIT 0x00000000 /* RWI-V */
#define NV_THERM_TSENSE_U2_A_0_BJT_1_TEMPERATURE_MODIFICATIONS_TEMPERATURE_OVERRIDE 29:16 /* RWIVF */
#define NV_THERM_TSENSE_U2_A_0_BJT_1_TEMPERATURE_MODIFICATIONS_TEMPERATURE_OVERRIDE_INIT 0x00000000 /* RWI-V */
#define NV_THERM_TSENSE_U2_A_0_BJT_1_TEMPERATURE_MODIFICATIONS_TEMPERATURE_OVERRIDE_EN 31:31 /* RWIVF */
#define NV_THERM_TSENSE_U2_A_0_BJT_1_TEMPERATURE_MODIFICATIONS_TEMPERATURE_OVERRIDE_EN_INIT 0x00000000 /* RWI-V */
#define NV_THERM_TSENSE_U2_A_0_BJT_2_TEMPERATURE_MODIFICATIONS 0x00066f30 /* RW-4R */
#define NV_THERM_TSENSE_U2_A_0_BJT_2_TEMPERATURE_MODIFICATIONS_TEMPERATURE_OFFSET 13:0 /* RWIVF */
#define NV_THERM_TSENSE_U2_A_0_BJT_2_TEMPERATURE_MODIFICATIONS_TEMPERATURE_OFFSET_INIT 0x00000000 /* RWI-V */
#define NV_THERM_TSENSE_U2_A_0_BJT_2_TEMPERATURE_MODIFICATIONS_TEMPERATURE_OVERRIDE 29:16 /* RWIVF */
#define NV_THERM_TSENSE_U2_A_0_BJT_2_TEMPERATURE_MODIFICATIONS_TEMPERATURE_OVERRIDE_INIT 0x00000000 /* RWI-V */
#define NV_THERM_TSENSE_U2_A_0_BJT_2_TEMPERATURE_MODIFICATIONS_TEMPERATURE_OVERRIDE_EN 31:31 /* RWIVF */
#define NV_THERM_TSENSE_U2_A_0_BJT_2_TEMPERATURE_MODIFICATIONS_TEMPERATURE_OVERRIDE_EN_INIT 0x00000000 /* RWI-V */
#define NV_THERM_TSENSE_U2_A_0_BJT_3_TEMPERATURE_MODIFICATIONS 0x00066f34 /* RW-4R */
#define NV_THERM_TSENSE_U2_A_0_BJT_3_TEMPERATURE_MODIFICATIONS_TEMPERATURE_OFFSET 13:0 /* RWIVF */
#define NV_THERM_TSENSE_U2_A_0_BJT_3_TEMPERATURE_MODIFICATIONS_TEMPERATURE_OFFSET_INIT 0x00000000 /* RWI-V */
#define NV_THERM_TSENSE_U2_A_0_BJT_3_TEMPERATURE_MODIFICATIONS_TEMPERATURE_OVERRIDE 29:16 /* RWIVF */
#define NV_THERM_TSENSE_U2_A_0_BJT_3_TEMPERATURE_MODIFICATIONS_TEMPERATURE_OVERRIDE_INIT 0x00000000 /* RWI-V */
#define NV_THERM_TSENSE_U2_A_0_BJT_3_TEMPERATURE_MODIFICATIONS_TEMPERATURE_OVERRIDE_EN 31:31 /* RWIVF */
#define NV_THERM_TSENSE_U2_A_0_BJT_3_TEMPERATURE_MODIFICATIONS_TEMPERATURE_OVERRIDE_EN_INIT 0x00000000 /* RWI-V */
#define NV_THERM_TSENSE_U2_A_0_BJT_4_TEMPERATURE_MODIFICATIONS 0x00066f38 /* RW-4R */
#define NV_THERM_TSENSE_U2_A_0_BJT_4_TEMPERATURE_MODIFICATIONS_TEMPERATURE_OFFSET 13:0 /* RWIVF */
#define NV_THERM_TSENSE_U2_A_0_BJT_4_TEMPERATURE_MODIFICATIONS_TEMPERATURE_OFFSET_INIT 0x00000000 /* RWI-V */
#define NV_THERM_TSENSE_U2_A_0_BJT_4_TEMPERATURE_MODIFICATIONS_TEMPERATURE_OVERRIDE 29:16 /* RWIVF */
#define NV_THERM_TSENSE_U2_A_0_BJT_4_TEMPERATURE_MODIFICATIONS_TEMPERATURE_OVERRIDE_INIT 0x00000000 /* RWI-V */
#define NV_THERM_TSENSE_U2_A_0_BJT_4_TEMPERATURE_MODIFICATIONS_TEMPERATURE_OVERRIDE_EN 31:31 /* RWIVF */
#define NV_THERM_TSENSE_U2_A_0_BJT_4_TEMPERATURE_MODIFICATIONS_TEMPERATURE_OVERRIDE_EN_INIT 0x00000000 /* RWI-V */
#define NV_THERM_TSENSE_U2_A_0_BJT_5_TEMPERATURE_MODIFICATIONS 0x00066f3c /* RW-4R */
#define NV_THERM_TSENSE_U2_A_0_BJT_5_TEMPERATURE_MODIFICATIONS_TEMPERATURE_OFFSET 13:0 /* RWIVF */
#define NV_THERM_TSENSE_U2_A_0_BJT_5_TEMPERATURE_MODIFICATIONS_TEMPERATURE_OFFSET_INIT 0x00000000 /* RWI-V */
#define NV_THERM_TSENSE_U2_A_0_BJT_5_TEMPERATURE_MODIFICATIONS_TEMPERATURE_OVERRIDE 29:16 /* RWIVF */
#define NV_THERM_TSENSE_U2_A_0_BJT_5_TEMPERATURE_MODIFICATIONS_TEMPERATURE_OVERRIDE_INIT 0x00000000 /* RWI-V */
#define NV_THERM_TSENSE_U2_A_0_BJT_5_TEMPERATURE_MODIFICATIONS_TEMPERATURE_OVERRIDE_EN 31:31 /* RWIVF */
#define NV_THERM_TSENSE_U2_A_0_BJT_5_TEMPERATURE_MODIFICATIONS_TEMPERATURE_OVERRIDE_EN_INIT 0x00000000 /* RWI-V */
#define NV_THERM_TSENSE_MAXIMUM_TEMPERATURE 0x00066f40 /* R--4R */
#define NV_THERM_TSENSE_MAXIMUM_TEMPERATURE_MAXIMUM_TEMPERATURE 13:0 /* R--VF */
#define NV_THERM_TSENSE_MAXIMUM_TEMPERATURE_MAX_TEMP_SENSE_NUMBER 24:16 /* R--VF */
#define NV_THERM_TSENSE_THRESHOLD_TEMPERATURES 0x00066f44 /* RW-4R */
#define NV_THERM_TSENSE_THRESHOLD_TEMPERATURES_WARNING_TEMPERATURE 13:0 /* RWIVF */
#define NV_THERM_TSENSE_THRESHOLD_TEMPERATURES_WARNING_TEMPERATURE_INIT 0x00000c80 /* RWI-V */
#define NV_THERM_TSENSE_THRESHOLD_TEMPERATURES_OVERTEMP_TEMPERATURE 29:16 /* RWIVF */
#define NV_THERM_TSENSE_THRESHOLD_TEMPERATURES_OVERTEMP_TEMPERATURE_INIT 0x00000dc0 /* RWI-V */
#define NV_THERM_TSENSE_U2_A_0_BJT_6 0x00066fa0 /* RW-4R */
#define NV_THERM_TSENSE_U2_A_0_BJT_6_TEMPERATURE 13:0 /* R-IVF */
#define NV_THERM_TSENSE_U2_A_0_BJT_6_TEMPERATURE_INIT 0x00000000 /* RWI-V */
#define NV_THERM_TSENSE_U2_A_0_BJT_6_SOURCE 16:16 /* R-IVF */
#define NV_THERM_TSENSE_U2_A_0_BJT_6_SOURCE_INIT 0x00000000 /* RWI-V */
#define NV_THERM_TSENSE_U2_A_0_BJT_6_TEMPERATURE_VALID 30:30 /* R-IVF */
#define NV_THERM_TSENSE_U2_A_0_BJT_6_TEMPERATURE_VALID_INIT 0x00000000 /* RWI-V */
#define NV_THERM_TSENSE_U2_A_0_BJT_6_TEMPERATURE_EN 31:31 /* RWIVF */
#define NV_THERM_TSENSE_U2_A_0_BJT_6_TEMPERATURE_EN_INIT 0x00000001 /* RWI-V */
#define NV_THERM_TSENSE_U2_A_0_BJT_7 0x00066fa4 /* RW-4R */
#define NV_THERM_TSENSE_U2_A_0_BJT_7_TEMPERATURE 13:0 /* R-IVF */
#define NV_THERM_TSENSE_U2_A_0_BJT_7_TEMPERATURE_INIT 0x00000000 /* RWI-V */
#define NV_THERM_TSENSE_U2_A_0_BJT_7_SOURCE 16:16 /* R-IVF */
#define NV_THERM_TSENSE_U2_A_0_BJT_7_SOURCE_INIT 0x00000000 /* RWI-V */
#define NV_THERM_TSENSE_U2_A_0_BJT_7_TEMPERATURE_VALID 30:30 /* R-IVF */
#define NV_THERM_TSENSE_U2_A_0_BJT_7_TEMPERATURE_VALID_INIT 0x00000000 /* RWI-V */
#define NV_THERM_TSENSE_U2_A_0_BJT_7_TEMPERATURE_EN 31:31 /* RWIVF */
#define NV_THERM_TSENSE_U2_A_0_BJT_7_TEMPERATURE_EN_INIT 0x00000001 /* RWI-V */
#define NV_THERM_TSENSE_U2_A_0_BJT_8 0x00066fa8 /* RW-4R */
#define NV_THERM_TSENSE_U2_A_0_BJT_8_TEMPERATURE 13:0 /* R-IVF */
#define NV_THERM_TSENSE_U2_A_0_BJT_8_TEMPERATURE_INIT 0x00000000 /* RWI-V */
#define NV_THERM_TSENSE_U2_A_0_BJT_8_SOURCE 16:16 /* R-IVF */
#define NV_THERM_TSENSE_U2_A_0_BJT_8_SOURCE_INIT 0x00000000 /* RWI-V */
#define NV_THERM_TSENSE_U2_A_0_BJT_8_TEMPERATURE_VALID 30:30 /* R-IVF */
#define NV_THERM_TSENSE_U2_A_0_BJT_8_TEMPERATURE_VALID_INIT 0x00000000 /* RWI-V */
#define NV_THERM_TSENSE_U2_A_0_BJT_8_TEMPERATURE_EN 31:31 /* RWIVF */
#define NV_THERM_TSENSE_U2_A_0_BJT_8_TEMPERATURE_EN_INIT 0x00000001 /* RWI-V */
#define NV_THERM_TSENSE_U2_A_0_BJT_6_TEMPERATURE_MODIFICATIONS 0x00066fb0 /* RW-4R */
#define NV_THERM_TSENSE_U2_A_0_BJT_6_TEMPERATURE_MODIFICATIONS_TEMPERATURE_OFFSET 13:0 /* RWIVF */
#define NV_THERM_TSENSE_U2_A_0_BJT_6_TEMPERATURE_MODIFICATIONS_TEMPERATURE_OFFSET_INIT 0x00000000 /* RWI-V */
#define NV_THERM_TSENSE_U2_A_0_BJT_6_TEMPERATURE_MODIFICATIONS_TEMPERATURE_OVERRIDE 29:16 /* RWIVF */
#define NV_THERM_TSENSE_U2_A_0_BJT_6_TEMPERATURE_MODIFICATIONS_TEMPERATURE_OVERRIDE_INIT 0x00000000 /* RWI-V */
#define NV_THERM_TSENSE_U2_A_0_BJT_6_TEMPERATURE_MODIFICATIONS_TEMPERATURE_OVERRIDE_EN 31:31 /* RWIVF */
#define NV_THERM_TSENSE_U2_A_0_BJT_6_TEMPERATURE_MODIFICATIONS_TEMPERATURE_OVERRIDE_EN_INIT 0x00000000 /* RWI-V */
#define NV_THERM_TSENSE_U2_A_0_BJT_7_TEMPERATURE_MODIFICATIONS 0x00066fb4 /* RW-4R */
#define NV_THERM_TSENSE_U2_A_0_BJT_7_TEMPERATURE_MODIFICATIONS_TEMPERATURE_OFFSET 13:0 /* RWIVF */
#define NV_THERM_TSENSE_U2_A_0_BJT_7_TEMPERATURE_MODIFICATIONS_TEMPERATURE_OFFSET_INIT 0x00000000 /* RWI-V */
#define NV_THERM_TSENSE_U2_A_0_BJT_7_TEMPERATURE_MODIFICATIONS_TEMPERATURE_OVERRIDE 29:16 /* RWIVF */
#define NV_THERM_TSENSE_U2_A_0_BJT_7_TEMPERATURE_MODIFICATIONS_TEMPERATURE_OVERRIDE_INIT 0x00000000 /* RWI-V */
#define NV_THERM_TSENSE_U2_A_0_BJT_7_TEMPERATURE_MODIFICATIONS_TEMPERATURE_OVERRIDE_EN 31:31 /* RWIVF */
#define NV_THERM_TSENSE_U2_A_0_BJT_7_TEMPERATURE_MODIFICATIONS_TEMPERATURE_OVERRIDE_EN_INIT 0x00000000 /* RWI-V */
#define NV_THERM_TSENSE_U2_A_0_BJT_8_TEMPERATURE_MODIFICATIONS 0x00066fb8 /* RW-4R */
#define NV_THERM_TSENSE_U2_A_0_BJT_8_TEMPERATURE_MODIFICATIONS_TEMPERATURE_OFFSET 13:0 /* RWIVF */
#define NV_THERM_TSENSE_U2_A_0_BJT_8_TEMPERATURE_MODIFICATIONS_TEMPERATURE_OFFSET_INIT 0x00000000 /* RWI-V */
#define NV_THERM_TSENSE_U2_A_0_BJT_8_TEMPERATURE_MODIFICATIONS_TEMPERATURE_OVERRIDE 29:16 /* RWIVF */
#define NV_THERM_TSENSE_U2_A_0_BJT_8_TEMPERATURE_MODIFICATIONS_TEMPERATURE_OVERRIDE_INIT 0x00000000 /* RWI-V */
#define NV_THERM_TSENSE_U2_A_0_BJT_8_TEMPERATURE_MODIFICATIONS_TEMPERATURE_OVERRIDE_EN 31:31 /* RWIVF */
#define NV_THERM_TSENSE_U2_A_0_BJT_8_TEMPERATURE_MODIFICATIONS_TEMPERATURE_OVERRIDE_EN_INIT 0x00000000 /* RWI-V */
#endif // __ls10_dev_therm_h__

37
src/common/inc/swref/published/nvswitch/ls10/dev_timer_ip.h Normal file
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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the Software),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __ls10_dev_timer_ip_h__
#define __ls10_dev_timer_ip_h__
/* This file is autogenerated. Do not edit */
#define NV_PTIMER 0x00000FFF:0x00000000 /* RW--D */
#define NV_PTIMER_PRI_TMR_CG1 0x00000600 /* RW-4R */
#define NV_PTIMER_PRI_TMR_CG1_MONITOR_CG_EN 0:0 /* RWIVF */
#define NV_PTIMER_PRI_TMR_CG1_MONITOR_CG_EN_ENABLED 0x00000001 /* RW--V */
#define NV_PTIMER_PRI_TMR_CG1_MONITOR_CG_EN_DISABLED 0x00000000 /* RWI-V */
#define NV_PTIMER_PRI_TMR_CG1_MONITOR_CG_EN__PROD 0x00000000 /* RW--V */
#define NV_PTIMER_PRI_TMR_CG1_SLCG 1:1 /* RWIVF */
#define NV_PTIMER_PRI_TMR_CG1_SLCG_ENABLED 0x00000000 /* RW--V */
#define NV_PTIMER_PRI_TMR_CG1_SLCG_DISABLED 0x00000001 /* RWI-V */
#define NV_PTIMER_PRI_TMR_CG1_SLCG__PROD 0x00000000 /* RW--V */
#endif // __ls10_dev_timer_ip_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the Software),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __ls10_dev_trim_h__
#define __ls10_dev_trim_h__
/* This file is autogenerated. Do not edit */
#define NV_CLOCK_NVSW_SYS 0x00001FFF:0x00000000 /* RW--D */
#define NV_CLOCK_NVSW_SYS_SWITCHCLK_SWITCH_DIVIDER 0x00000080 /* RW-4R */
#define NV_CLOCK_NVSW_SYS_SWITCHCLK_SWITCH_DIVIDER_DIVIDER_SEL 5:0 /* RWEUF */
#define NV_CLOCK_NVSW_SYS_SWITCHCLK_SWITCH_DIVIDER_DIVIDER_SEL_BY1 0x00000000 /* RW--V */
#define NV_CLOCK_NVSW_SYS_SWITCHCLK_SWITCH_DIVIDER_DIVIDER_SEL_BY2 0x00000002 /* RW--V */
#define NV_CLOCK_NVSW_SYS_SWITCHCLK_SWITCH_DIVIDER_DIVIDER_SEL_BY3 0x00000004 /* RW--V */
#define NV_CLOCK_NVSW_SYS_SWITCHCLK_SWITCH_DIVIDER_DIVIDER_SEL_BY4 0x00000006 /* RW--V */
#define NV_CLOCK_NVSW_SYS_SWITCHCLK_SWITCH_DIVIDER_DIVIDER_SEL_BY5 0x00000008 /* RW--V */
#define NV_CLOCK_NVSW_SYS_SWITCHCLK_SWITCH_DIVIDER_DIVIDER_SEL_BY6 0x0000000A /* RW--V */
#define NV_CLOCK_NVSW_SYS_SWITCHCLK_SWITCH_DIVIDER_DIVIDER_SEL_BY7 0x0000000C /* RW--V */
#define NV_CLOCK_NVSW_SYS_SWITCHCLK_SWITCH_DIVIDER_DIVIDER_SEL_BY8 0x0000000E /* RW--V */
#define NV_CLOCK_NVSW_SYS_SWITCHCLK_SWITCH_DIVIDER_DIVIDER_SEL_BY9 0x00000010 /* RW--V */
#define NV_CLOCK_NVSW_SYS_SWITCHCLK_SWITCH_DIVIDER_DIVIDER_SEL_BY10 0x00000012 /* RW--V */
#define NV_CLOCK_NVSW_SYS_SWITCHCLK_SWITCH_DIVIDER_DIVIDER_SEL_BY11 0x00000014 /* RW--V */
#define NV_CLOCK_NVSW_SYS_SWITCHCLK_SWITCH_DIVIDER_DIVIDER_SEL_BY12 0x00000016 /* RW--V */
#define NV_CLOCK_NVSW_SYS_SWITCHCLK_SWITCH_DIVIDER_DIVIDER_SEL_BY13 0x00000018 /* RW--V */
#define NV_CLOCK_NVSW_SYS_SWITCHCLK_SWITCH_DIVIDER_DIVIDER_SEL_BY14 0x0000001A /* RW--V */
#define NV_CLOCK_NVSW_SYS_SWITCHCLK_SWITCH_DIVIDER_DIVIDER_SEL_BY15 0x0000001C /* RW--V */
#define NV_CLOCK_NVSW_SYS_SWITCHCLK_SWITCH_DIVIDER_DIVIDER_SEL_BY16 0x0000001E /* RW--V */
#define NV_CLOCK_NVSW_SYS_SWITCHCLK_SWITCH_DIVIDER_DIVIDER_SEL_BY17 0x00000020 /* RW--V */
#define NV_CLOCK_NVSW_SYS_SWITCHCLK_SWITCH_DIVIDER_DIVIDER_SEL_BY18 0x00000022 /* RW--V */
#define NV_CLOCK_NVSW_SYS_SWITCHCLK_SWITCH_DIVIDER_DIVIDER_SEL_BY19 0x00000024 /* RW--V */
#define NV_CLOCK_NVSW_SYS_SWITCHCLK_SWITCH_DIVIDER_DIVIDER_SEL_BY20 0x00000026 /* RW--V */
#define NV_CLOCK_NVSW_SYS_SWITCHCLK_SWITCH_DIVIDER_DIVIDER_SEL_BY21 0x00000028 /* RW--V */
#define NV_CLOCK_NVSW_SYS_SWITCHCLK_SWITCH_DIVIDER_DIVIDER_SEL_BY22 0x0000002A /* RW--V */
#define NV_CLOCK_NVSW_SYS_SWITCHCLK_SWITCH_DIVIDER_DIVIDER_SEL_BY23 0x0000002C /* RW--V */
#define NV_CLOCK_NVSW_SYS_SWITCHCLK_SWITCH_DIVIDER_DIVIDER_SEL_BY24 0x0000002E /* RW--V */
#define NV_CLOCK_NVSW_SYS_SWITCHCLK_SWITCH_DIVIDER_DIVIDER_SEL_BY25 0x00000030 /* RW--V */
#define NV_CLOCK_NVSW_SYS_SWITCHCLK_SWITCH_DIVIDER_DIVIDER_SEL_BY26 0x00000032 /* RW--V */
#define NV_CLOCK_NVSW_SYS_SWITCHCLK_SWITCH_DIVIDER_DIVIDER_SEL_BY27 0x00000034 /* RW--V */
#define NV_CLOCK_NVSW_SYS_SWITCHCLK_SWITCH_DIVIDER_DIVIDER_SEL_BY28 0x00000036 /* RW--V */
#define NV_CLOCK_NVSW_SYS_SWITCHCLK_SWITCH_DIVIDER_DIVIDER_SEL_BY29 0x00000038 /* RW--V */
#define NV_CLOCK_NVSW_SYS_SWITCHCLK_SWITCH_DIVIDER_DIVIDER_SEL_BY30 0x0000003A /* RW--V */
#define NV_CLOCK_NVSW_SYS_SWITCHCLK_SWITCH_DIVIDER_DIVIDER_SEL_BY31 0x0000003C /* RW--V */
#define NV_CLOCK_NVSW_SYS_SWITCHCLK_SWITCH_DIVIDER_DIVIDER_SEL_INIT 0x00000002 /* RWE-V */
#define NV_CLOCK_NVSW_SYS_SWITCHCLK_SWITCH_DIVIDER_ASYNC_MODE 11:8 /* RWEUF */
#define NV_CLOCK_NVSW_SYS_SWITCHCLK_SWITCH_DIVIDER_ASYNC_MODE_INIT 0x00000000 /* RWE-V */
#define NV_CLOCK_NVSW_SYS_SWITCHCLK_SWITCH_DIVIDER_CLOCK_SOURCE_SEL 15:12 /* RWEUF */
#define NV_CLOCK_NVSW_SYS_SWITCHCLK_SWITCH_DIVIDER_CLOCK_SOURCE_SEL_PEX_REFCLK 0x00000001 /* RW--V */
#define NV_CLOCK_NVSW_SYS_SWITCHCLK_SWITCH_DIVIDER_CLOCK_SOURCE_SEL_PEX_REFCLK_1 0x00000002 /* RW--V */
#define NV_CLOCK_NVSW_SYS_SWITCHCLK_SWITCH_DIVIDER_CLOCK_SOURCE_SEL_PEX_REFCLK_2 0x00000004 /* RW--V */
#define NV_CLOCK_NVSW_SYS_SWITCHCLK_SWITCH_DIVIDER_CLOCK_SOURCE_SEL_SWITCHPLL 0x00000008 /* RW--V */
#define NV_CLOCK_NVSW_SYS_SWITCHCLK_SWITCH_DIVIDER_CLOCK_SOURCE_SEL_INIT 0x00000001 /* RWE-V */
#define NV_CLOCK_NVSW_SYS_SWITCHCLK_SWITCH_DIVIDER_GATE_CLOCK 16:16 /* RWEUF */
#define NV_CLOCK_NVSW_SYS_SWITCHCLK_SWITCH_DIVIDER_GATE_CLOCK_INIT 0x00000000 /* RWE-V */
#define NV_CLOCK_NVSW_SYS_SWITCHCLK_SWITCH_DIVIDER_GATE_CLOCK_GATED 0x00000001 /* RW--V */
#define NV_CLOCK_NVSW_SYS_SWITCHCLK_SWITCH_DIVIDER_BYPASS_FSM 17:17 /* RWEUF */
#define NV_CLOCK_NVSW_SYS_SWITCHCLK_SWITCH_DIVIDER_BYPASS_FSM_INIT 0x00000000 /* RWE-V */
#define NV_CLOCK_NVSW_SYS_SWITCHCLK_SWITCH_DIVIDER_BYPASS_FSM_BYPASSED 0x00000001 /* RW--V */
#define NV_CLOCK_NVSW_SYS_SWITCHCLK_SWITCH_DIVIDER_SWITCH_STATUS 21:18 /* R--UF */
#define NV_CLOCK_NVSW_SYS_SWITCHCLK_SWITCH_DIVIDER_SWITCH_DIVIDER_DONE 22:22 /* R--UF */
#define NV_CLOCK_NVSW_SYS_SWITCHCLK_SWITCH_DIVIDER_STATUS_DONE_2 23:23 /* R--UF */
#define NV_CLOCK_NVSW_SYS_SWITCHCLK_SWITCH_DIVIDER_STATUS_DONE_3 24:24 /* R--UF */
#define NV_CLOCK_NVSW_SYS_SWITCHCLK_SWITCH_DIVIDER_DEBUG_OUT_STATE 27:25 /* R--UF */
#define NV_CLOCK_NVSW_SYS_SWITCHCLK_SWITCH_DIVIDER_SPARE 30:28 /* RWEUF */
#define NV_CLOCK_NVSW_SYS_SWITCHCLK_SWITCH_DIVIDER_SPARE_INIT 0x00000000 /* RWE-V */
#define NV_CLOCK_NVSW_SYS_SWITCHCLK_SWITCH_DIVIDER_SW_FSM_EN 31:31 /* RWEUF */
#define NV_CLOCK_NVSW_SYS_SWITCHCLK_SWITCH_DIVIDER_SW_FSM_EN_INIT 0x00000000 /* RWE-V */
#define NV_CLOCK_NVSW_SYS_SWITCHCLK_SWITCH_DIVIDER_SW_FSM_EN_ASSERT 0x00000001 /* RW--V */
#define NV_CLOCK_NVSW_SYS_SWITCHCLK_SWITCH_DIVIDER_SW_FSM_EN_DEASSERT 0x00000000 /* RW--V */
#define NV_CLOCK_NVSW_SYS_SYSTEM_CLK_SWITCH_DIVIDER 0x00000088 /* RW-4R */
#define NV_CLOCK_NVSW_SYS_SYSTEM_CLK_SWITCH_DIVIDER_DIVIDER_SEL 5:0 /* RWEUF */
#define NV_CLOCK_NVSW_SYS_SYSTEM_CLK_SWITCH_DIVIDER_DIVIDER_SEL_BY1 0x00000000 /* RW--V */
#define NV_CLOCK_NVSW_SYS_SYSTEM_CLK_SWITCH_DIVIDER_DIVIDER_SEL_BY2 0x00000002 /* RW--V */
#define NV_CLOCK_NVSW_SYS_SYSTEM_CLK_SWITCH_DIVIDER_DIVIDER_SEL_BY3 0x00000004 /* RW--V */
#define NV_CLOCK_NVSW_SYS_SYSTEM_CLK_SWITCH_DIVIDER_DIVIDER_SEL_BY4 0x00000006 /* RW--V */
#define NV_CLOCK_NVSW_SYS_SYSTEM_CLK_SWITCH_DIVIDER_DIVIDER_SEL_BY5 0x00000008 /* RW--V */
#define NV_CLOCK_NVSW_SYS_SYSTEM_CLK_SWITCH_DIVIDER_DIVIDER_SEL_BY6 0x0000000A /* RW--V */
#define NV_CLOCK_NVSW_SYS_SYSTEM_CLK_SWITCH_DIVIDER_DIVIDER_SEL_BY7 0x0000000C /* RW--V */
#define NV_CLOCK_NVSW_SYS_SYSTEM_CLK_SWITCH_DIVIDER_DIVIDER_SEL_BY8 0x0000000E /* RW--V */
#define NV_CLOCK_NVSW_SYS_SYSTEM_CLK_SWITCH_DIVIDER_DIVIDER_SEL_BY9 0x00000010 /* RW--V */
#define NV_CLOCK_NVSW_SYS_SYSTEM_CLK_SWITCH_DIVIDER_DIVIDER_SEL_BY10 0x00000012 /* RW--V */
#define NV_CLOCK_NVSW_SYS_SYSTEM_CLK_SWITCH_DIVIDER_DIVIDER_SEL_BY11 0x00000014 /* RW--V */
#define NV_CLOCK_NVSW_SYS_SYSTEM_CLK_SWITCH_DIVIDER_DIVIDER_SEL_BY12 0x00000016 /* RW--V */
#define NV_CLOCK_NVSW_SYS_SYSTEM_CLK_SWITCH_DIVIDER_DIVIDER_SEL_BY13 0x00000018 /* RW--V */
#define NV_CLOCK_NVSW_SYS_SYSTEM_CLK_SWITCH_DIVIDER_DIVIDER_SEL_BY14 0x0000001A /* RW--V */
#define NV_CLOCK_NVSW_SYS_SYSTEM_CLK_SWITCH_DIVIDER_DIVIDER_SEL_BY15 0x0000001C /* RW--V */
#define NV_CLOCK_NVSW_SYS_SYSTEM_CLK_SWITCH_DIVIDER_DIVIDER_SEL_BY16 0x0000001E /* RW--V */
#define NV_CLOCK_NVSW_SYS_SYSTEM_CLK_SWITCH_DIVIDER_DIVIDER_SEL_BY17 0x00000020 /* RW--V */
#define NV_CLOCK_NVSW_SYS_SYSTEM_CLK_SWITCH_DIVIDER_DIVIDER_SEL_BY18 0x00000022 /* RW--V */
#define NV_CLOCK_NVSW_SYS_SYSTEM_CLK_SWITCH_DIVIDER_DIVIDER_SEL_BY19 0x00000024 /* RW--V */
#define NV_CLOCK_NVSW_SYS_SYSTEM_CLK_SWITCH_DIVIDER_DIVIDER_SEL_BY20 0x00000026 /* RW--V */
#define NV_CLOCK_NVSW_SYS_SYSTEM_CLK_SWITCH_DIVIDER_DIVIDER_SEL_BY21 0x00000028 /* RW--V */
#define NV_CLOCK_NVSW_SYS_SYSTEM_CLK_SWITCH_DIVIDER_DIVIDER_SEL_BY22 0x0000002A /* RW--V */
#define NV_CLOCK_NVSW_SYS_SYSTEM_CLK_SWITCH_DIVIDER_DIVIDER_SEL_BY23 0x0000002C /* RW--V */
#define NV_CLOCK_NVSW_SYS_SYSTEM_CLK_SWITCH_DIVIDER_DIVIDER_SEL_BY24 0x0000002E /* RW--V */
#define NV_CLOCK_NVSW_SYS_SYSTEM_CLK_SWITCH_DIVIDER_DIVIDER_SEL_BY25 0x00000030 /* RW--V */
#define NV_CLOCK_NVSW_SYS_SYSTEM_CLK_SWITCH_DIVIDER_DIVIDER_SEL_BY26 0x00000032 /* RW--V */
#define NV_CLOCK_NVSW_SYS_SYSTEM_CLK_SWITCH_DIVIDER_DIVIDER_SEL_BY27 0x00000034 /* RW--V */
#define NV_CLOCK_NVSW_SYS_SYSTEM_CLK_SWITCH_DIVIDER_DIVIDER_SEL_BY28 0x00000036 /* RW--V */
#define NV_CLOCK_NVSW_SYS_SYSTEM_CLK_SWITCH_DIVIDER_DIVIDER_SEL_BY29 0x00000038 /* RW--V */
#define NV_CLOCK_NVSW_SYS_SYSTEM_CLK_SWITCH_DIVIDER_DIVIDER_SEL_BY30 0x0000003A /* RW--V */
#define NV_CLOCK_NVSW_SYS_SYSTEM_CLK_SWITCH_DIVIDER_DIVIDER_SEL_BY31 0x0000003C /* RW--V */
#define NV_CLOCK_NVSW_SYS_SYSTEM_CLK_SWITCH_DIVIDER_DIVIDER_SEL_INIT 0x00000004 /* RWE-V */
#define NV_CLOCK_NVSW_SYS_SYSTEM_CLK_SWITCH_DIVIDER_ASYNC_MODE 11:8 /* RWEUF */
#define NV_CLOCK_NVSW_SYS_SYSTEM_CLK_SWITCH_DIVIDER_ASYNC_MODE_INIT 0x00000000 /* RWE-V */
#define NV_CLOCK_NVSW_SYS_SYSTEM_CLK_SWITCH_DIVIDER_CLOCK_SOURCE_SEL 15:12 /* RWEUF */
#define NV_CLOCK_NVSW_SYS_SYSTEM_CLK_SWITCH_DIVIDER_CLOCK_SOURCE_SEL_PEX_REFCLK 0x00000001 /* RW--V */
#define NV_CLOCK_NVSW_SYS_SYSTEM_CLK_SWITCH_DIVIDER_CLOCK_SOURCE_SEL_PEX_REFCLK_1 0x00000002 /* RW--V */
#define NV_CLOCK_NVSW_SYS_SYSTEM_CLK_SWITCH_DIVIDER_CLOCK_SOURCE_SEL_PEX_REFCLK_2 0x00000004 /* RW--V */
#define NV_CLOCK_NVSW_SYS_SYSTEM_CLK_SWITCH_DIVIDER_CLOCK_SOURCE_SEL_SWITCHPLL 0x00000008 /* RW--V */
#define NV_CLOCK_NVSW_SYS_SYSTEM_CLK_SWITCH_DIVIDER_CLOCK_SOURCE_SEL_INIT 0x00000001 /* RWE-V */
#define NV_CLOCK_NVSW_SYS_SYSTEM_CLK_SWITCH_DIVIDER_GATE_CLOCK 16:16 /* RWEUF */
#define NV_CLOCK_NVSW_SYS_SYSTEM_CLK_SWITCH_DIVIDER_GATE_CLOCK_INIT 0x00000000 /* RWE-V */
#define NV_CLOCK_NVSW_SYS_SYSTEM_CLK_SWITCH_DIVIDER_GATE_CLOCK_GATED 0x00000001 /* RW--V */
#define NV_CLOCK_NVSW_SYS_SYSTEM_CLK_SWITCH_DIVIDER_BYPASS_FSM 17:17 /* RWEUF */
#define NV_CLOCK_NVSW_SYS_SYSTEM_CLK_SWITCH_DIVIDER_BYPASS_FSM_INIT 0x00000000 /* RWE-V */
#define NV_CLOCK_NVSW_SYS_SYSTEM_CLK_SWITCH_DIVIDER_BYPASS_FSM_BYPASSED 0x00000001 /* RW--V */
#define NV_CLOCK_NVSW_SYS_SYSTEM_CLK_SWITCH_DIVIDER_SWITCH_STATUS 21:18 /* R--UF */
#define NV_CLOCK_NVSW_SYS_SYSTEM_CLK_SWITCH_DIVIDER_SWITCH_DIVIDER_DONE 22:22 /* R--UF */
#define NV_CLOCK_NVSW_SYS_SYSTEM_CLK_SWITCH_DIVIDER_STATUS_DONE_2 23:23 /* R--UF */
#define NV_CLOCK_NVSW_SYS_SYSTEM_CLK_SWITCH_DIVIDER_STATUS_DONE_3 24:24 /* R--UF */
#define NV_CLOCK_NVSW_SYS_SYSTEM_CLK_SWITCH_DIVIDER_DEBUG_OUT_STATE 27:25 /* R--UF */
#define NV_CLOCK_NVSW_SYS_SYSTEM_CLK_SWITCH_DIVIDER_SPARE 30:28 /* RWEUF */
#define NV_CLOCK_NVSW_SYS_SYSTEM_CLK_SWITCH_DIVIDER_SPARE_INIT 0x00000000 /* RWE-V */
#define NV_CLOCK_NVSW_SYS_SYSTEM_CLK_SWITCH_DIVIDER_SW_FSM_EN 31:31 /* RWEUF */
#define NV_CLOCK_NVSW_SYS_SYSTEM_CLK_SWITCH_DIVIDER_SW_FSM_EN_INIT 0x00000000 /* RWE-V */
#define NV_CLOCK_NVSW_SYS_SYSTEM_CLK_SWITCH_DIVIDER_SW_FSM_EN_ASSERT 0x00000001 /* RW--V */
#define NV_CLOCK_NVSW_SYS_SYSTEM_CLK_SWITCH_DIVIDER_SW_FSM_EN_DEASSERT 0x00000000 /* RW--V */
#define NV_CLOCK_NVSW_SYS_RX_BYPASS_REFCLK 0x000000C4 /* RW-4R */
#define NV_CLOCK_NVSW_SYS_RX_BYPASS_REFCLK_DISABLE 0:0 /* RWEUF */
#define NV_CLOCK_NVSW_SYS_RX_BYPASS_REFCLK_DISABLE_INIT 0x00000001 /* RWE-V */
#define NV_CLOCK_NVSW_SYS_RX_BYPASS_REFCLK_DIV 13:4 /* RWEUF */
#define NV_CLOCK_NVSW_SYS_RX_BYPASS_REFCLK_DIV_INIT 0x0000000C /* RWE-V */
#define NV_CLOCK_NVSW_SYS_RX_BYPASS_REFCLK_REFCLK_BUF_EN_CYA 14:14 /* RWEUF */
#define NV_CLOCK_NVSW_SYS_RX_BYPASS_REFCLK_REFCLK_BUF_EN_CYA_INIT 0x00000000 /* RWE-V */
#define NV_CLOCK_NVSW_SYS_RX_BYPASS_REFCLK_REFCLK_BUF_EN_OVERRIDE 15:15 /* RWEUF */
#define NV_CLOCK_NVSW_SYS_RX_BYPASS_REFCLK_REFCLK_BUF_EN_OVERRIDE_INIT 0x00000000 /* RWE-V */
#define NV_CLOCK_NVSW_SYS_SWITCHPLL_CFG 0x00000100 /* RW-4R */
#define NV_CLOCK_NVSW_SYS_SWITCHPLL_CFG_ENABLE 0:0 /* RWEUF */
#define NV_CLOCK_NVSW_SYS_SWITCHPLL_CFG_ENABLE_INIT 0x00000000 /* RWE-V */
#define NV_CLOCK_NVSW_SYS_SWITCHPLL_CFG_ENABLE_NO 0x00000000 /* RW--V */
#define NV_CLOCK_NVSW_SYS_SWITCHPLL_CFG_ENABLE_YES 0x00000001 /* RW--V */
#define NV_CLOCK_NVSW_SYS_SWITCHPLL_CFG_IDDQ 1:1 /* RWEUF */
#define NV_CLOCK_NVSW_SYS_SWITCHPLL_CFG_IDDQ_INIT 0x00000001 /* RWE-V */
#define NV_CLOCK_NVSW_SYS_SWITCHPLL_CFG_IDDQ_POWER_ON 0x00000000 /* RW--V */
#define NV_CLOCK_NVSW_SYS_SWITCHPLL_CFG_IDDQ_POWER_OFF 0x00000001 /* RW--V */
#define NV_CLOCK_NVSW_SYS_SWITCHPLL_CFG_EN_LCKDET 4:4 /* RWEUF */
#define NV_CLOCK_NVSW_SYS_SWITCHPLL_CFG_EN_LCKDET_INIT 0x00000001 /* RWE-V */
#define NV_CLOCK_NVSW_SYS_SWITCHPLL_CFG_EN_LCKDET_POWER_ON 0x00000001 /* RW--V */
#define NV_CLOCK_NVSW_SYS_SWITCHPLL_CFG_EN_LCKDET_POWER_OFF 0x00000000 /* RW--V */
#define NV_CLOCK_NVSW_SYS_SWITCHPLL_CFG_LOCK_OVERRIDE 5:5 /* RWEUF */
#define NV_CLOCK_NVSW_SYS_SWITCHPLL_CFG_LOCK_OVERRIDE_INIT 0x00000000 /* RWE-V */
#define NV_CLOCK_NVSW_SYS_SWITCHPLL_CFG_LOCK_OVERRIDE_DISABLE 0x00000000 /* RW--V */
#define NV_CLOCK_NVSW_SYS_SWITCHPLL_CFG_LOCK_OVERRIDE_ENABLE 0x00000001 /* RW--V */
#define NV_CLOCK_NVSW_SYS_SWITCHPLL_CFG_PLL_LOCK 17:17 /* R--UF */
#define NV_CLOCK_NVSW_SYS_SWITCHPLL_CFG_PLL_LOCK_FALSE 0x00000000 /* R---V */
#define NV_CLOCK_NVSW_SYS_SWITCHPLL_CFG_PLL_LOCK_TRUE 0x00000001 /* R---V */
#define NV_CLOCK_NVSW_SYS_SWITCHPLL_CFG_BYPASSPLL_CYA 21:21 /* RWEUF */
#define NV_CLOCK_NVSW_SYS_SWITCHPLL_CFG_BYPASSPLL_CYA_INIT 0x00000000 /* RWE-V */
#define NV_CLOCK_NVSW_SYS_SWITCHPLL_CFG_SEL_TESTOUT 28:26 /* RWEUF */
#define NV_CLOCK_NVSW_SYS_SWITCHPLL_CFG_SEL_TESTOUT_INIT 0x00000000 /* RWE-V */
#define NV_CLOCK_NVSW_SYS_SWITCHPLL_COEFF 0x00000104 /* RW-4R */
#define NV_CLOCK_NVSW_SYS_SWITCHPLL_COEFF_MDIV 7:0 /* RWEUF */
#define NV_CLOCK_NVSW_SYS_SWITCHPLL_COEFF_MDIV_MIN 0x00000001 /* RW--V */
#define NV_CLOCK_NVSW_SYS_SWITCHPLL_COEFF_MDIV_MAX 0x000000FF /* RW--V */
#define NV_CLOCK_NVSW_SYS_SWITCHPLL_COEFF_MDIV_INIT 0x00000005 /* RWE-V */
#define NV_CLOCK_NVSW_SYS_SWITCHPLL_COEFF_NDIV 15:8 /* RWEUF */
#define NV_CLOCK_NVSW_SYS_SWITCHPLL_COEFF_NDIV_MIN 0x00000008 /* RW--V */
#define NV_CLOCK_NVSW_SYS_SWITCHPLL_COEFF_NDIV_MAX 0x000000FF /* RW--V */
#define NV_CLOCK_NVSW_SYS_SWITCHPLL_COEFF_NDIV_INIT 0x00000085 /* RWE-V */
#define NV_CLOCK_NVSW_SYS_SWITCHPLL_COEFF_PLDIV 21:16 /* RWEUF */
#define NV_CLOCK_NVSW_SYS_SWITCHPLL_COEFF_PLDIV_INIT 0x00000001 /* RWE-V */
#define NV_CLOCK_NVSW_SYS_SWITCHPLL_COEFF_PLDIV_MIN 0x00000001 /* RW--V */
#define NV_CLOCK_NVSW_SYS_SWITCHPLL_COEFF_PLDIV_MAX 0x0000001F /* RW--V */
#define NV_CLOCK_NVSW_SYS_SWITCHPLL_CTRL 0x00000108 /* RW-4R */
#define NV_CLOCK_NVSW_SYS_SWITCHPLL_CTRL_KCP 19:18 /* RWEUF */
#define NV_CLOCK_NVSW_SYS_SWITCHPLL_CTRL_KCP_INIT 0x00000000 /* RWE-V */
#define NV_CLOCK_NVSW_SYS_SWITCHPLL_CTRL_KVCO 22:20 /* RWEUF */
#define NV_CLOCK_NVSW_SYS_SWITCHPLL_CTRL_KVCO_INIT 0x00000000 /* RWE-V */
#define NV_CLOCK_NVSW_SYS_SWITCHPLL_CTRL_PLL_FREQLOCK 28:28 /* R--UF */
#define NV_CLOCK_NVSW_SYS_SWITCHPLL_SECURE_0 0x00000118 /* RW-4R */
#define NV_CLOCK_NVSW_SYS_SWITCHPLL_SECURE_0_VREG_CTRL 1:0 /* RWEUF */
#define NV_CLOCK_NVSW_SYS_SWITCHPLL_SECURE_0_VREG_CTRL_INIT 0x00000000 /* RWE-V */
#define NV_CLOCK_NVSW_SYS_SWITCHPLL_SECURE_0_VREG_CTRL_1V0 0x00000000 /* R---V */
#define NV_CLOCK_NVSW_SYS_SWITCHPLL_SECURE_0_VREG_CTRL_1V05 0x00000001 /* R---V */
#define NV_CLOCK_NVSW_SYS_SWITCHPLL_SECURE_0_VREG_CTRL_1V1 0x00000002 /* R---V */
#define NV_CLOCK_NVSW_SYS_SWITCHPLL_SECURE_0_VREG_CTRL_0V95 0x00000003 /* R---V */
#define NV_CLOCK_NVSW_SYS_SWITCHPLL_SECURE 0x0000011c /* RW-4R */
#define NV_CLOCK_NVSW_SYS_SWITCHPLL_SECURE_SETUP 31:0 /* RWEUF */
#define NV_CLOCK_NVSW_SYS_SWITCHPLL_SECURE_SETUP_INIT 0x00000000 /* RWE-V */
#define NV_CLOCK_NVSW_PRT_NVLINK_UPHY0_PLL0_SLCG 0x00000330 /* RW-4R */
#define NV_CLOCK_NVSW_PRT_NVLINK_UPHY0_PLL0_SLCG_CFGSM 1:1 /* RWEVF */
#define NV_CLOCK_NVSW_PRT_NVLINK_UPHY0_PLL0_SLCG_CFGSM_ENABLED 0x00000000 /* RW--V */
#define NV_CLOCK_NVSW_PRT_NVLINK_UPHY0_PLL0_SLCG_CFGSM_DISABLED 0x00000001 /* RWE-V */
#define NV_CLOCK_NVSW_PRT_NVLINK_UPHY0_PLL0_SLCG_CFGSM__PROD 0x00000000 /* RW--V */
#endif // __ls10_dev_trim_h__

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src/common/inc/swref/published/nvswitch/ls10/dev_tstate_ip.h Normal file
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@@ -0,0 +1,274 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the Software),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __ls10_dev_tstate_ip_h__
#define __ls10_dev_tstate_ip_h__
/* This file is autogenerated. Do not edit */
#define NV_TSTATE 0x00003fff:0x00003000 /* RW--D */
#define NV_TSTATE_TAGSTATECONTROL 0x00003040 /* RW-4R */
#define NV_TSTATE_TAGSTATECONTROL_ATO_ENB 9:9 /* RWEVF */
#define NV_TSTATE_TAGSTATECONTROL_ATO_ENB_ON 0x00000001 /* RWE-V */
#define NV_TSTATE_TAGSTATECONTROL_ATO_ENB_OFF 0x00000000 /* RW--V */
#define NV_TSTATE_ATO_TIMER_LIMIT 0x00003048 /* RW-4R */
#define NV_TSTATE_ATO_TIMER_LIMIT_LIMIT 19:0 /* RWEVF */
#define NV_TSTATE_ATO_TIMER_LIMIT_LIMIT_INIT 0x00000355 /* RWE-V */
#define NV_TSTATE_ERR_STATUS_0 0x00003400 /* RW-4R */
#define NV_TSTATE_ERR_STATUS_0_TAGPOOLBUFERR 0:0 /* RWDVF */
#define NV_TSTATE_ERR_STATUS_0_TAGPOOLBUFERR__ONWRITE "oneToClear" /* */
#define NV_TSTATE_ERR_STATUS_0_TAGPOOLBUFERR_NONE 0x00000000 /* RWD-V */
#define NV_TSTATE_ERR_STATUS_0_TAGPOOLBUFERR_CLEAR 0x00000001 /* RW--V */
#define NV_TSTATE_ERR_STATUS_0_TAGPOOL_ECC_LIMIT_ERR 1:1 /* RWDVF */
#define NV_TSTATE_ERR_STATUS_0_TAGPOOL_ECC_LIMIT_ERR__ONWRITE "oneToClear" /* */
#define NV_TSTATE_ERR_STATUS_0_TAGPOOL_ECC_LIMIT_ERR_NONE 0x00000000 /* RWD-V */
#define NV_TSTATE_ERR_STATUS_0_TAGPOOL_ECC_LIMIT_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_TSTATE_ERR_STATUS_0_TAGPOOL_ECC_DBE_ERR 2:2 /* RWDVF */
#define NV_TSTATE_ERR_STATUS_0_TAGPOOL_ECC_DBE_ERR__ONWRITE "oneToClear" /* */
#define NV_TSTATE_ERR_STATUS_0_TAGPOOL_ECC_DBE_ERR_NONE 0x00000000 /* RWD-V */
#define NV_TSTATE_ERR_STATUS_0_TAGPOOL_ECC_DBE_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_TSTATE_ERR_STATUS_0_CRUMBSTOREBUFERR 3:3 /* RWDVF */
#define NV_TSTATE_ERR_STATUS_0_CRUMBSTOREBUFERR__ONWRITE "oneToClear" /* */
#define NV_TSTATE_ERR_STATUS_0_CRUMBSTOREBUFERR_NONE 0x00000000 /* RWD-V */
#define NV_TSTATE_ERR_STATUS_0_CRUMBSTOREBUFERR_CLEAR 0x00000001 /* RW--V */
#define NV_TSTATE_ERR_STATUS_0_CRUMBSTORE_ECC_LIMIT_ERR 4:4 /* RWDVF */
#define NV_TSTATE_ERR_STATUS_0_CRUMBSTORE_ECC_LIMIT_ERR__ONWRITE "oneToClear" /* */
#define NV_TSTATE_ERR_STATUS_0_CRUMBSTORE_ECC_LIMIT_ERR_NONE 0x00000000 /* RWD-V */
#define NV_TSTATE_ERR_STATUS_0_CRUMBSTORE_ECC_LIMIT_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_TSTATE_ERR_STATUS_0_CRUMBSTORE_ECC_DBE_ERR 5:5 /* RWDVF */
#define NV_TSTATE_ERR_STATUS_0_CRUMBSTORE_ECC_DBE_ERR__ONWRITE "oneToClear" /* */
#define NV_TSTATE_ERR_STATUS_0_CRUMBSTORE_ECC_DBE_ERR_NONE 0x00000000 /* RWD-V */
#define NV_TSTATE_ERR_STATUS_0_CRUMBSTORE_ECC_DBE_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_TSTATE_ERR_STATUS_0_ATO_ERR 6:6 /* RWDVF */
#define NV_TSTATE_ERR_STATUS_0_ATO_ERR__ONWRITE "oneToClear" /* */
#define NV_TSTATE_ERR_STATUS_0_ATO_ERR_NONE 0x00000000 /* RWD-V */
#define NV_TSTATE_ERR_STATUS_0_ATO_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_TSTATE_ERR_STATUS_0_CAMRSP_ERR 7:7 /* RWDVF */
#define NV_TSTATE_ERR_STATUS_0_CAMRSP_ERR__ONWRITE "oneToClear" /* */
#define NV_TSTATE_ERR_STATUS_0_CAMRSP_ERR_NONE 0x00000000 /* RWD-V */
#define NV_TSTATE_ERR_STATUS_0_CAMRSP_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_TSTATE_ERR_LOG_EN_0 0x00003404 /* RW-4R */
#define NV_TSTATE_ERR_LOG_EN_0_TAGPOOLBUFERR 0:0 /* RWEVF */
#define NV_TSTATE_ERR_LOG_EN_0_TAGPOOLBUFERR__PROD 0x00000001 /* RW--V */
#define NV_TSTATE_ERR_LOG_EN_0_TAGPOOLBUFERR_DISABLE 0x00000000 /* RWE-V */
#define NV_TSTATE_ERR_LOG_EN_0_TAGPOOLBUFERR_ENABLE 0x00000001 /* RW--V */
#define NV_TSTATE_ERR_LOG_EN_0_TAGPOOL_ECC_LIMIT_ERR 1:1 /* RWEVF */
#define NV_TSTATE_ERR_LOG_EN_0_TAGPOOL_ECC_LIMIT_ERR__PROD 0x00000001 /* RW--V */
#define NV_TSTATE_ERR_LOG_EN_0_TAGPOOL_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_TSTATE_ERR_LOG_EN_0_TAGPOOL_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_TSTATE_ERR_LOG_EN_0_TAGPOOL_ECC_DBE_ERR 2:2 /* RWEVF */
#define NV_TSTATE_ERR_LOG_EN_0_TAGPOOL_ECC_DBE_ERR__PROD 0x00000001 /* RW--V */
#define NV_TSTATE_ERR_LOG_EN_0_TAGPOOL_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_TSTATE_ERR_LOG_EN_0_TAGPOOL_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_TSTATE_ERR_LOG_EN_0_CRUMBSTOREBUFERR 3:3 /* RWEVF */
#define NV_TSTATE_ERR_LOG_EN_0_CRUMBSTOREBUFERR__PROD 0x00000001 /* RW--V */
#define NV_TSTATE_ERR_LOG_EN_0_CRUMBSTOREBUFERR_DISABLE 0x00000000 /* RWE-V */
#define NV_TSTATE_ERR_LOG_EN_0_CRUMBSTOREBUFERR_ENABLE 0x00000001 /* RW--V */
#define NV_TSTATE_ERR_LOG_EN_0_CRUMBSTORE_ECC_LIMIT_ERR 4:4 /* RWEVF */
#define NV_TSTATE_ERR_LOG_EN_0_CRUMBSTORE_ECC_LIMIT_ERR__PROD 0x00000001 /* RW--V */
#define NV_TSTATE_ERR_LOG_EN_0_CRUMBSTORE_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_TSTATE_ERR_LOG_EN_0_CRUMBSTORE_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_TSTATE_ERR_LOG_EN_0_CRUMBSTORE_ECC_DBE_ERR 5:5 /* RWEVF */
#define NV_TSTATE_ERR_LOG_EN_0_CRUMBSTORE_ECC_DBE_ERR__PROD 0x00000001 /* RW--V */
#define NV_TSTATE_ERR_LOG_EN_0_CRUMBSTORE_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_TSTATE_ERR_LOG_EN_0_CRUMBSTORE_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_TSTATE_ERR_LOG_EN_0_ATO_ERR 6:6 /* RWEVF */
#define NV_TSTATE_ERR_LOG_EN_0_ATO_ERR__PROD 0x00000001 /* RW--V */
#define NV_TSTATE_ERR_LOG_EN_0_ATO_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_TSTATE_ERR_LOG_EN_0_ATO_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_TSTATE_ERR_LOG_EN_0_CAMRSP_ERR 7:7 /* RWEVF */
#define NV_TSTATE_ERR_LOG_EN_0_CAMRSP_ERR__PROD 0x00000001 /* RW--V */
#define NV_TSTATE_ERR_LOG_EN_0_CAMRSP_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_TSTATE_ERR_LOG_EN_0_CAMRSP_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_TSTATE_ERR_FATAL_REPORT_EN_0 0x00003408 /* RW-4R */
#define NV_TSTATE_ERR_FATAL_REPORT_EN_0_TAGPOOLBUFERR 0:0 /* RWEVF */
#define NV_TSTATE_ERR_FATAL_REPORT_EN_0_TAGPOOLBUFERR__PROD 0x00000001 /* RW--V */
#define NV_TSTATE_ERR_FATAL_REPORT_EN_0_TAGPOOLBUFERR_DISABLE 0x00000000 /* RWE-V */
#define NV_TSTATE_ERR_FATAL_REPORT_EN_0_TAGPOOLBUFERR_ENABLE 0x00000001 /* RW--V */
#define NV_TSTATE_ERR_FATAL_REPORT_EN_0_TAGPOOL_ECC_LIMIT_ERR 1:1 /* RWEVF */
#define NV_TSTATE_ERR_FATAL_REPORT_EN_0_TAGPOOL_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_TSTATE_ERR_FATAL_REPORT_EN_0_TAGPOOL_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_TSTATE_ERR_FATAL_REPORT_EN_0_TAGPOOL_ECC_DBE_ERR 2:2 /* RWEVF */
#define NV_TSTATE_ERR_FATAL_REPORT_EN_0_TAGPOOL_ECC_DBE_ERR__PROD 0x00000001 /* RW--V */
#define NV_TSTATE_ERR_FATAL_REPORT_EN_0_TAGPOOL_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_TSTATE_ERR_FATAL_REPORT_EN_0_TAGPOOL_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_TSTATE_ERR_FATAL_REPORT_EN_0_CRUMBSTOREBUFERR 3:3 /* RWEVF */
#define NV_TSTATE_ERR_FATAL_REPORT_EN_0_CRUMBSTOREBUFERR__PROD 0x00000001 /* RW--V */
#define NV_TSTATE_ERR_FATAL_REPORT_EN_0_CRUMBSTOREBUFERR_DISABLE 0x00000000 /* RWE-V */
#define NV_TSTATE_ERR_FATAL_REPORT_EN_0_CRUMBSTOREBUFERR_ENABLE 0x00000001 /* RW--V */
#define NV_TSTATE_ERR_FATAL_REPORT_EN_0_CRUMBSTORE_ECC_LIMIT_ERR 4:4 /* RWEVF */
#define NV_TSTATE_ERR_FATAL_REPORT_EN_0_CRUMBSTORE_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_TSTATE_ERR_FATAL_REPORT_EN_0_CRUMBSTORE_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_TSTATE_ERR_FATAL_REPORT_EN_0_CRUMBSTORE_ECC_DBE_ERR 5:5 /* RWEVF */
#define NV_TSTATE_ERR_FATAL_REPORT_EN_0_CRUMBSTORE_ECC_DBE_ERR__PROD 0x00000001 /* RW--V */
#define NV_TSTATE_ERR_FATAL_REPORT_EN_0_CRUMBSTORE_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_TSTATE_ERR_FATAL_REPORT_EN_0_CRUMBSTORE_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_TSTATE_ERR_FATAL_REPORT_EN_0_ATO_ERR 6:6 /* RWEVF */
#define NV_TSTATE_ERR_FATAL_REPORT_EN_0_ATO_ERR__PROD 0x00000001 /* RW--V */
#define NV_TSTATE_ERR_FATAL_REPORT_EN_0_ATO_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_TSTATE_ERR_FATAL_REPORT_EN_0_ATO_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_TSTATE_ERR_FATAL_REPORT_EN_0_CAMRSP_ERR 7:7 /* RWEVF */
#define NV_TSTATE_ERR_FATAL_REPORT_EN_0_CAMRSP_ERR__PROD 0x00000001 /* RW--V */
#define NV_TSTATE_ERR_FATAL_REPORT_EN_0_CAMRSP_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_TSTATE_ERR_FATAL_REPORT_EN_0_CAMRSP_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_TSTATE_ERR_NON_FATAL_REPORT_EN_0 0x0000340c /* RW-4R */
#define NV_TSTATE_ERR_NON_FATAL_REPORT_EN_0_TAGPOOLBUFERR 0:0 /* RWEVF */
#define NV_TSTATE_ERR_NON_FATAL_REPORT_EN_0_TAGPOOLBUFERR_DISABLE 0x00000000 /* RWE-V */
#define NV_TSTATE_ERR_NON_FATAL_REPORT_EN_0_TAGPOOLBUFERR_ENABLE 0x00000001 /* RW--V */
#define NV_TSTATE_ERR_NON_FATAL_REPORT_EN_0_TAGPOOL_ECC_LIMIT_ERR 1:1 /* RWEVF */
#define NV_TSTATE_ERR_NON_FATAL_REPORT_EN_0_TAGPOOL_ECC_LIMIT_ERR__PROD 0x00000001 /* RW--V */
#define NV_TSTATE_ERR_NON_FATAL_REPORT_EN_0_TAGPOOL_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_TSTATE_ERR_NON_FATAL_REPORT_EN_0_TAGPOOL_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_TSTATE_ERR_NON_FATAL_REPORT_EN_0_TAGPOOL_ECC_DBE_ERR 2:2 /* RWEVF */
#define NV_TSTATE_ERR_NON_FATAL_REPORT_EN_0_TAGPOOL_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_TSTATE_ERR_NON_FATAL_REPORT_EN_0_TAGPOOL_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_TSTATE_ERR_NON_FATAL_REPORT_EN_0_CRUMBSTOREBUFERR 3:3 /* RWEVF */
#define NV_TSTATE_ERR_NON_FATAL_REPORT_EN_0_CRUMBSTOREBUFERR_DISABLE 0x00000000 /* RWE-V */
#define NV_TSTATE_ERR_NON_FATAL_REPORT_EN_0_CRUMBSTOREBUFERR_ENABLE 0x00000001 /* RW--V */
#define NV_TSTATE_ERR_NON_FATAL_REPORT_EN_0_CRUMBSTORE_ECC_LIMIT_ERR 4:4 /* RWEVF */
#define NV_TSTATE_ERR_NON_FATAL_REPORT_EN_0_CRUMBSTORE_ECC_LIMIT_ERR__PROD 0x00000001 /* RW--V */
#define NV_TSTATE_ERR_NON_FATAL_REPORT_EN_0_CRUMBSTORE_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_TSTATE_ERR_NON_FATAL_REPORT_EN_0_CRUMBSTORE_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_TSTATE_ERR_NON_FATAL_REPORT_EN_0_CRUMBSTORE_ECC_DBE_ERR 5:5 /* RWEVF */
#define NV_TSTATE_ERR_NON_FATAL_REPORT_EN_0_CRUMBSTORE_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_TSTATE_ERR_NON_FATAL_REPORT_EN_0_CRUMBSTORE_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_TSTATE_ERR_NON_FATAL_REPORT_EN_0_ATO_ERR 6:6 /* RWEVF */
#define NV_TSTATE_ERR_NON_FATAL_REPORT_EN_0_ATO_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_TSTATE_ERR_NON_FATAL_REPORT_EN_0_ATO_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_TSTATE_ERR_NON_FATAL_REPORT_EN_0_CAMRSP_ERR 7:7 /* RWEVF */
#define NV_TSTATE_ERR_NON_FATAL_REPORT_EN_0_CAMRSP_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_TSTATE_ERR_NON_FATAL_REPORT_EN_0_CAMRSP_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_TSTATE_ERR_CORRECTABLE_REPORT_EN_0 0x00003410 /* RW-4R */
#define NV_TSTATE_ERR_CONTAIN_EN_0 0x00003414 /* RW-4R */
#define NV_TSTATE_ERR_CONTAIN_EN_0_TAGPOOLBUFERR 0:0 /* RWEVF */
#define NV_TSTATE_ERR_CONTAIN_EN_0_TAGPOOLBUFERR__PROD 0x00000001 /* RW--V */
#define NV_TSTATE_ERR_CONTAIN_EN_0_TAGPOOLBUFERR_DISABLE 0x00000000 /* RWE-V */
#define NV_TSTATE_ERR_CONTAIN_EN_0_TAGPOOLBUFERR_ENABLE 0x00000001 /* RW--V */
#define NV_TSTATE_ERR_CONTAIN_EN_0_TAGPOOL_ECC_LIMIT_ERR 1:1 /* RWEVF */
#define NV_TSTATE_ERR_CONTAIN_EN_0_TAGPOOL_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_TSTATE_ERR_CONTAIN_EN_0_TAGPOOL_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_TSTATE_ERR_CONTAIN_EN_0_TAGPOOL_ECC_DBE_ERR 2:2 /* RWEVF */
#define NV_TSTATE_ERR_CONTAIN_EN_0_TAGPOOL_ECC_DBE_ERR__PROD 0x00000001 /* RW--V */
#define NV_TSTATE_ERR_CONTAIN_EN_0_TAGPOOL_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_TSTATE_ERR_CONTAIN_EN_0_TAGPOOL_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_TSTATE_ERR_CONTAIN_EN_0_CRUMBSTOREBUFERR 3:3 /* RWEVF */
#define NV_TSTATE_ERR_CONTAIN_EN_0_CRUMBSTOREBUFERR__PROD 0x00000001 /* RW--V */
#define NV_TSTATE_ERR_CONTAIN_EN_0_CRUMBSTOREBUFERR_DISABLE 0x00000000 /* RWE-V */
#define NV_TSTATE_ERR_CONTAIN_EN_0_CRUMBSTOREBUFERR_ENABLE 0x00000001 /* RW--V */
#define NV_TSTATE_ERR_CONTAIN_EN_0_CRUMBSTORE_ECC_LIMIT_ERR 4:4 /* RWEVF */
#define NV_TSTATE_ERR_CONTAIN_EN_0_CRUMBSTORE_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_TSTATE_ERR_CONTAIN_EN_0_CRUMBSTORE_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_TSTATE_ERR_CONTAIN_EN_0_CRUMBSTORE_ECC_DBE_ERR 5:5 /* RWEVF */
#define NV_TSTATE_ERR_CONTAIN_EN_0_CRUMBSTORE_ECC_DBE_ERR__PROD 0x00000001 /* RW--V */
#define NV_TSTATE_ERR_CONTAIN_EN_0_CRUMBSTORE_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_TSTATE_ERR_CONTAIN_EN_0_CRUMBSTORE_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_TSTATE_ERR_CONTAIN_EN_0_ATO_ERR 6:6 /* RWEVF */
#define NV_TSTATE_ERR_CONTAIN_EN_0_ATO_ERR__PROD 0x00000001 /* RW--V */
#define NV_TSTATE_ERR_CONTAIN_EN_0_ATO_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_TSTATE_ERR_CONTAIN_EN_0_ATO_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_TSTATE_ERR_CONTAIN_EN_0_CAMRSP_ERR 7:7 /* RWEVF */
#define NV_TSTATE_ERR_CONTAIN_EN_0_CAMRSP_ERR__PROD 0x00000001 /* RW--V */
#define NV_TSTATE_ERR_CONTAIN_EN_0_CAMRSP_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_TSTATE_ERR_CONTAIN_EN_0_CAMRSP_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_TSTATE_ERR_FIRST_0 0x0000341c /* RW-4R */
#define NV_TSTATE_ERR_FIRST_0_TAGPOOLBUFERR 0:0 /* RWDVF */
#define NV_TSTATE_ERR_FIRST_0_TAGPOOLBUFERR__ONWRITE "oneToClear" /* */
#define NV_TSTATE_ERR_FIRST_0_TAGPOOLBUFERR_NONE 0x00000000 /* RWD-V */
#define NV_TSTATE_ERR_FIRST_0_TAGPOOLBUFERR_CLEAR 0x00000001 /* RW--V */
#define NV_TSTATE_ERR_FIRST_0_TAGPOOL_ECC_LIMIT_ERR 1:1 /* RWDVF */
#define NV_TSTATE_ERR_FIRST_0_TAGPOOL_ECC_LIMIT_ERR__ONWRITE "oneToClear" /* */
#define NV_TSTATE_ERR_FIRST_0_TAGPOOL_ECC_LIMIT_ERR_NONE 0x00000000 /* RWD-V */
#define NV_TSTATE_ERR_FIRST_0_TAGPOOL_ECC_LIMIT_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_TSTATE_ERR_FIRST_0_TAGPOOL_ECC_DBE_ERR 2:2 /* RWDVF */
#define NV_TSTATE_ERR_FIRST_0_TAGPOOL_ECC_DBE_ERR__ONWRITE "oneToClear" /* */
#define NV_TSTATE_ERR_FIRST_0_TAGPOOL_ECC_DBE_ERR_NONE 0x00000000 /* RWD-V */
#define NV_TSTATE_ERR_FIRST_0_TAGPOOL_ECC_DBE_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_TSTATE_ERR_FIRST_0_CRUMBSTOREBUFERR 3:3 /* RWDVF */
#define NV_TSTATE_ERR_FIRST_0_CRUMBSTOREBUFERR__ONWRITE "oneToClear" /* */
#define NV_TSTATE_ERR_FIRST_0_CRUMBSTOREBUFERR_NONE 0x00000000 /* RWD-V */
#define NV_TSTATE_ERR_FIRST_0_CRUMBSTOREBUFERR_CLEAR 0x00000001 /* RW--V */
#define NV_TSTATE_ERR_FIRST_0_CRUMBSTORE_ECC_LIMIT_ERR 4:4 /* RWDVF */
#define NV_TSTATE_ERR_FIRST_0_CRUMBSTORE_ECC_LIMIT_ERR__ONWRITE "oneToClear" /* */
#define NV_TSTATE_ERR_FIRST_0_CRUMBSTORE_ECC_LIMIT_ERR_NONE 0x00000000 /* RWD-V */
#define NV_TSTATE_ERR_FIRST_0_CRUMBSTORE_ECC_LIMIT_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_TSTATE_ERR_FIRST_0_CRUMBSTORE_ECC_DBE_ERR 5:5 /* RWDVF */
#define NV_TSTATE_ERR_FIRST_0_CRUMBSTORE_ECC_DBE_ERR__ONWRITE "oneToClear" /* */
#define NV_TSTATE_ERR_FIRST_0_CRUMBSTORE_ECC_DBE_ERR_NONE 0x00000000 /* RWD-V */
#define NV_TSTATE_ERR_FIRST_0_CRUMBSTORE_ECC_DBE_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_TSTATE_ERR_FIRST_0_ATO_ERR 6:6 /* RWDVF */
#define NV_TSTATE_ERR_FIRST_0_ATO_ERR__ONWRITE "oneToClear" /* */
#define NV_TSTATE_ERR_FIRST_0_ATO_ERR_NONE 0x00000000 /* RWD-V */
#define NV_TSTATE_ERR_FIRST_0_ATO_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_TSTATE_ERR_FIRST_0_CAMRSP_ERR 7:7 /* RWDVF */
#define NV_TSTATE_ERR_FIRST_0_CAMRSP_ERR__ONWRITE "oneToClear" /* */
#define NV_TSTATE_ERR_FIRST_0_CAMRSP_ERR_NONE 0x00000000 /* RWD-V */
#define NV_TSTATE_ERR_FIRST_0_CAMRSP_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_TSTATE_ERR_DEBUG 0x00003420 /* R--4R */
#define NV_TSTATE_ERR_DEBUG_ATO_SOURCE 7:0 /* R-DVF */
#define NV_TSTATE_ERR_DEBUG_ATO_SOURCE_INIT 0x00000000 /* R-D-V */
#define NV_TSTATE_ERR_TIMESTAMP_LOG 0x00003450 /* R--4R */
#define NV_TSTATE_ERR_TIMESTAMP_LOG_TIMESTAMP 23:0 /* R-DVF */
#define NV_TSTATE_ERR_TIMESTAMP_LOG_TIMESTAMP_INIT 0x00000000 /* R-D-V */
#define NV_TSTATE_ERR_MISC_LOG_0 0x00003454 /* R--4R */
#define NV_TSTATE_ERR_MISC_LOG_0_ENCODEDVC 10:8 /* R-DVF */
#define NV_TSTATE_ERR_MISC_LOG_0_ENCODEDVC_CREQ 0x00000000 /* R-D-V */
#define NV_TSTATE_ERR_MISC_LOG_0_ENCODEDVC_DGD 0x00000001 /* R---V */
#define NV_TSTATE_ERR_MISC_LOG_0_ENCODEDVC_ATR 0x00000002 /* R---V */
#define NV_TSTATE_ERR_MISC_LOG_0_ENCODEDVC_ATSD 0x00000003 /* R---V */
#define NV_TSTATE_ERR_MISC_LOG_0_ENCODEDVC_PROBE 0x00000004 /* R---V */
#define NV_TSTATE_ERR_MISC_LOG_0_ENCODEDVC_CREQ_TD 0x00000005 /* R---V */
#define NV_TSTATE_ERR_MISC_LOG_0_ENCODEDVC_DGD_TD 0x00000006 /* R---V */
#define NV_TSTATE_ERR_ECC_CTRL 0x00003470 /* RW-4R */
#define NV_TSTATE_ERR_ECC_CTRL_CRUMBSTORE_ECC_ENABLE 0:0 /* RWEVF */
#define NV_TSTATE_ERR_ECC_CTRL_CRUMBSTORE_ECC_ENABLE_ENABLE 0x00000001 /* RW--V */
#define NV_TSTATE_ERR_ECC_CTRL_CRUMBSTORE_ECC_ENABLE_DISABLE 0x00000000 /* RWE-V */
#define NV_TSTATE_ERR_ECC_CTRL_CRUMBSTORE_ECC_ENABLE__PROD 0x00000001 /* RW--V */
#define NV_TSTATE_ERR_ECC_CTRL_TAGPOOL_ECC_ENABLE 1:1 /* RWEVF */
#define NV_TSTATE_ERR_ECC_CTRL_TAGPOOL_ECC_ENABLE_ENABLE 0x00000001 /* RW--V */
#define NV_TSTATE_ERR_ECC_CTRL_TAGPOOL_ECC_ENABLE_DISABLE 0x00000000 /* RWE-V */
#define NV_TSTATE_ERR_ECC_CTRL_TAGPOOL_ECC_ENABLE__PROD 0x00000001 /* RW--V */
#define NV_TSTATE_ERR_CRUMBSTORE_ECC_ERROR_COUNTER 0x00003480 /* RW-4R */
#define NV_TSTATE_ERR_CRUMBSTORE_ECC_ERROR_COUNTER_ERROR_COUNT 23:0 /* RWDVF */
#define NV_TSTATE_ERR_CRUMBSTORE_ECC_ERROR_COUNTER_ERROR_COUNT_INIT 0x00000000 /* RWD-V */
#define NV_TSTATE_ERR_CRUMBSTORE_ECC_ERROR_COUNTER_LIMIT 0x00003484 /* RW-4R */
#define NV_TSTATE_ERR_CRUMBSTORE_ECC_ERROR_COUNTER_LIMIT_ERROR_LIMIT 23:0 /* RWDVF */
#define NV_TSTATE_ERR_CRUMBSTORE_ECC_ERROR_COUNTER_LIMIT_ERROR_LIMIT_INIT 0x00ffffff /* RWD-V */
#define NV_TSTATE_ERR_CRUMBSTORE_ECC_ERROR_ADDRESS 0x00003488 /* R--4R */
#define NV_TSTATE_ERR_CRUMBSTORE_ECC_ERROR_ADDRESS_ERROR_ADDRESS 9:0 /* R-DVF */
#define NV_TSTATE_ERR_CRUMBSTORE_ECC_ERROR_ADDRESS_ERROR_ADDRESS_INIT 0x00000000 /* R-D-V */
#define NV_TSTATE_ERR_CRUMBSTORE_ECC_ERROR_ADDRESS_VALID 0x0000348c /* R--4R */
#define NV_TSTATE_ERR_CRUMBSTORE_ECC_ERROR_ADDRESS_VALID_VALID 0:0 /* R-DVF */
#define NV_TSTATE_ERR_CRUMBSTORE_ECC_ERROR_ADDRESS_VALID_VALID_INVALID 0x00000000 /* R-D-V */
#define NV_TSTATE_ERR_CRUMBSTORE_ECC_ERROR_ADDRESS_VALID_VALID_VALID 0x00000001 /* R---V */
#define NV_TSTATE_ERR_TAGPOOL_ECC_ERROR_COUNTER 0x00003490 /* RW-4R */
#define NV_TSTATE_ERR_TAGPOOL_ECC_ERROR_COUNTER_ERROR_COUNT 23:0 /* RWDVF */
#define NV_TSTATE_ERR_TAGPOOL_ECC_ERROR_COUNTER_ERROR_COUNT_INIT 0x00000000 /* RWD-V */
#define NV_TSTATE_ERR_TAGPOOL_ECC_ERROR_COUNTER_LIMIT 0x00003494 /* RW-4R */
#define NV_TSTATE_ERR_TAGPOOL_ECC_ERROR_COUNTER_LIMIT_ERROR_LIMIT 23:0 /* RWDVF */
#define NV_TSTATE_ERR_TAGPOOL_ECC_ERROR_COUNTER_LIMIT_ERROR_LIMIT_INIT 0x00ffffff /* RWD-V */
#define NV_TSTATE_ERR_TAGPOOL_ECC_ERROR_ADDRESS 0x00003498 /* R--4R */
#define NV_TSTATE_ERR_TAGPOOL_ECC_ERROR_ADDRESS_ERROR_ADDRESS 9:0 /* R-DVF */
#define NV_TSTATE_ERR_TAGPOOL_ECC_ERROR_ADDRESS_ERROR_ADDRESS_INIT 0x00000000 /* R-D-V */
#define NV_TSTATE_ERR_TAGPOOL_ECC_ERROR_ADDRESS_VALID 0x0000349c /* R--4R */
#define NV_TSTATE_ERR_TAGPOOL_ECC_ERROR_ADDRESS_VALID_VALID 0:0 /* R-DVF */
#define NV_TSTATE_ERR_TAGPOOL_ECC_ERROR_ADDRESS_VALID_VALID_INVALID 0x00000000 /* R-D-V */
#define NV_TSTATE_ERR_TAGPOOL_ECC_ERROR_ADDRESS_VALID_VALID_VALID 0x00000001 /* R---V */
#endif // __ls10_dev_tstate_ip_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the Software),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __ls10_dev_xtl_ep_pri_h__
#define __ls10_dev_xtl_ep_pri_h__
/* This file is autogenerated. Do not edit */
#define NV_XTL 0x91FFF:0x91000 /* RW--D */
#define NV_XTL_EP_PRI 0x00FFF:0x00000 /* RW--D */
#define NV_XTL_EP_PRI_XTL_EP_CG 0x00000F00 /* RWI4R */
#define NV_XTL_EP_PRI_XTL_EP_CG_IDLE_CG_DLY_CNT 5:0 /* RWIVF */
#define NV_XTL_EP_PRI_XTL_EP_CG_IDLE_CG_DLY_CNT_HWINIT 0x0000000B /* RWI-V */
#define NV_XTL_EP_PRI_XTL_EP_CG_IDLE_CG_DLY_CNT__PROD 0x0000000B /* RW--V */
#define NV_XTL_EP_PRI_XTL_EP_CG_IDLE_CG_EN 6:6 /* RWIVF */
#define NV_XTL_EP_PRI_XTL_EP_CG_IDLE_CG_EN_ENABLED 0x00000001 /* RW--V */
#define NV_XTL_EP_PRI_XTL_EP_CG_IDLE_CG_EN_DISABLED 0x00000000 /* RWI-V */
#define NV_XTL_EP_PRI_XTL_EP_CG_IDLE_CG_EN__PROD 0x00000001 /* RW--V */
#define NV_XTL_EP_PRI_XTL_EP_CG_STATE_CG_EN 7:7 /* */
#define NV_XTL_EP_PRI_XTL_EP_CG_STATE_CG_EN_ENABLED 0x00000001 /* */
#define NV_XTL_EP_PRI_XTL_EP_CG_STATE_CG_EN_DISABLED 0x00000000 /* */
#define NV_XTL_EP_PRI_XTL_EP_CG_STATE_CG_EN__PROD 0x00000000 /* */
#define NV_XTL_EP_PRI_XTL_EP_CG_STALL_CG_DLY_CNT 13:8 /* */
#define NV_XTL_EP_PRI_XTL_EP_CG_STALL_CG_DLY_CNT_HWINIT 0x00000000 /* */
#define NV_XTL_EP_PRI_XTL_EP_CG_STALL_CG_DLY_CNT__PROD 0x00000000 /* */
#define NV_XTL_EP_PRI_XTL_EP_CG_STALL_CG_EN 14:14 /* RWIVF */
#define NV_XTL_EP_PRI_XTL_EP_CG_STALL_CG_EN_ENABLED 0x00000001 /* RW--V */
#define NV_XTL_EP_PRI_XTL_EP_CG_STALL_CG_EN_DISABLED 0x00000000 /* RWI-V */
#define NV_XTL_EP_PRI_XTL_EP_CG_STALL_CG_EN__PROD 0x00000000 /* RW--V */
#define NV_XTL_EP_PRI_XTL_EP_CG_QUIESCENT_CG_EN 15:15 /* */
#define NV_XTL_EP_PRI_XTL_EP_CG_QUIESCENT_CG_EN_ENABLED 0x00000001 /* */
#define NV_XTL_EP_PRI_XTL_EP_CG_QUIESCENT_CG_EN_DISABLED 0x00000000 /* */
#define NV_XTL_EP_PRI_XTL_EP_CG_QUIESCENT_CG_EN__PROD 0x00000000 /* */
#define NV_XTL_EP_PRI_XTL_EP_CG_WAKEUP_DLY_CNT 19:16 /* RWIVF */
#define NV_XTL_EP_PRI_XTL_EP_CG_WAKEUP_DLY_CNT_HWINIT 0x0000000B /* RWI-V */
#define NV_XTL_EP_PRI_XTL_EP_CG_WAKEUP_DLY_CNT__PROD 0x0000000B /* RW--V */
#define NV_XTL_EP_PRI_XTL_EP_CG_THROT_CLK_CNT 23:20 /* */
#define NV_XTL_EP_PRI_XTL_EP_CG_THROT_CLK_CNT_FULLSPEED 0x0000000f /* */
#define NV_XTL_EP_PRI_XTL_EP_CG_THROT_CLK_CNT__PROD 0x00000000 /* */
#define NV_XTL_EP_PRI_XTL_EP_CG_DI_DT_SKEW_VAL 27:24 /* */
#define NV_XTL_EP_PRI_XTL_EP_CG_DI_DT_SKEW_VAL_HWINIT 0x00000000 /* */
#define NV_XTL_EP_PRI_XTL_EP_CG_DI_DT_SKEW_VAL__PROD 0x00000000 /* */
#define NV_XTL_EP_PRI_XTL_EP_CG_THROT_CLK_EN 28:28 /* */
#define NV_XTL_EP_PRI_XTL_EP_CG_THROT_CLK_EN_ENABLED 0x00000001 /* */
#define NV_XTL_EP_PRI_XTL_EP_CG_THROT_CLK_EN_DISABLED 0x00000000 /* */
#define NV_XTL_EP_PRI_XTL_EP_CG_THROT_CLK_EN__PROD 0x00000000 /* */
#define NV_XTL_EP_PRI_XTL_EP_CG_THROT_CLK_SW_OVER 29:29 /* */
#define NV_XTL_EP_PRI_XTL_EP_CG_THROT_CLK_SW_OVER_EN 0x00000001 /* */
#define NV_XTL_EP_PRI_XTL_EP_CG_THROT_CLK_SW_OVER_DIS 0x00000000 /* */
#define NV_XTL_EP_PRI_XTL_EP_CG_THROT_CLK_SW_OVER__PROD 0x00000000 /* */
#define NV_XTL_EP_PRI_XTL_EP_CG_PAUSE_CG_EN 30:30 /* */
#define NV_XTL_EP_PRI_XTL_EP_CG_PAUSE_CG_EN_ENABLED 0x00000001 /* */
#define NV_XTL_EP_PRI_XTL_EP_CG_PAUSE_CG_EN_DISABLED 0x00000000 /* */
#define NV_XTL_EP_PRI_XTL_EP_CG_PAUSE_CG_EN__PROD 0x00000000 /* */
#define NV_XTL_EP_PRI_XTL_EP_CG_HALT_CG_EN 31:31 /* */
#define NV_XTL_EP_PRI_XTL_EP_CG_HALT_CG_EN_ENABLED 0x00000001 /* */
#define NV_XTL_EP_PRI_XTL_EP_CG_HALT_CG_EN_DISABLED 0x00000000 /* */
#define NV_XTL_EP_PRI_XTL_EP_CG_HALT_CG_EN__PROD 0x00000000 /* */
#define NV_XTL_EP_PRI_XTL_EP_CG1 0x00000F04 /* RWI4R */
#define NV_XTL_EP_PRI_XTL_EP_CG1_MONITOR_CG_EN 0:0 /* RWIVF */
#define NV_XTL_EP_PRI_XTL_EP_CG1_MONITOR_CG_EN_ENABLED 0x00000001 /* RW--V */
#define NV_XTL_EP_PRI_XTL_EP_CG1_MONITOR_CG_EN_DISABLED 0x00000000 /* RWI-V */
#define NV_XTL_EP_PRI_XTL_EP_CG1_MONITOR_CG_EN__PROD 0x00000000 /* RW--V */
#define NV_XTL_EP_PRI_XTL_EP_CG1_SLCG 15:1 /* RWIVF */
#define NV_XTL_EP_PRI_XTL_EP_CG1_SLCG_ENABLED 0x00000000 /* RW--V */
#define NV_XTL_EP_PRI_XTL_EP_CG1_SLCG_DISABLED 0x00007FFF /* RWI-V */
#define NV_XTL_EP_PRI_XTL_EP_CG1_SLCG__PROD 0x00000000 /* RW--V */
#endif // __ls10_dev_xtl_ep_pri_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the Software),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __ls10_npgip_discovery_h__
#define __ls10_npgip_discovery_h__
/* This file is autogenerated. Do not edit */
#define NV_NPG_DISCOVERY /* R--4P */
#define NV_NPG_DISCOVERY_ENTRY 1:0 /* R-EVF */
#define NV_NPG_DISCOVERY_ENTRY_INVALID 0x00000000 /* R-E-V */
#define NV_NPG_DISCOVERY_ENTRY_ENUM 0x00000001 /* R---V */
#define NV_NPG_DISCOVERY_ENTRY_DATA1 0x00000002 /* R---V */
#define NV_NPG_DISCOVERY_ENTRY_DATA2 0x00000003 /* R---V */
#define NV_NPG_DISCOVERY_CONTENTS 30:2 /* R-EVF */
#define NV_NPG_DISCOVERY_CONTENTS_INIT 0x00000000 /* R-E-V */
#define NV_NPG_DISCOVERY_CHAIN 31:31 /* R-EVF */
#define NV_NPG_DISCOVERY_CHAIN_DISABLE 0x00000000 /* R-E-V */
#define NV_NPG_DISCOVERY_CHAIN_ENABLE 0x00000001 /* R---V */
#define NV_NPG_DISCOVERY_ENUM_DEVICE 7:2 /* R--UF */
#define NV_NPG_DISCOVERY_ENUM_DEVICE_INVALID 0x0 /* R---V */
#define NV_NPG_DISCOVERY_ENUM_DEVICE_NPG 0x1 /* R---V */
#define NV_NPG_DISCOVERY_ENUM_DEVICE_NPORT 0x2 /* R---V */
#define NV_NPG_DISCOVERY_ENUM_DEVICE_NPORT_MULTICAST 0x3 /* R---V */
#define NV_NPG_DISCOVERY_ENUM_DEVICE_NPG_PERFMON 0x4 /* R---V */
#define NV_NPG_DISCOVERY_ENUM_DEVICE_NPORT_PERFMON 0x5 /* R---V */
#define NV_NPG_DISCOVERY_ENUM_DEVICE_NPORT_PERFMON_MULTICAST 0x6 /* R---V */
#define NV_NPG_DISCOVERY_ENUM_ID 15:8 /* R--UF */
#define NV_NPG_DISCOVERY_ENUM_RESERVED 19:16 /* R--UF */
#define NV_NPG_DISCOVERY_ENUM_VERSION 30:20 /* R--UF */
#define NV_NPG_DISCOVERY_ENUM_VERSION_1 0x1 /* R---V */
#define NV_NPG_DISCOVERY_ENUM_VERSION_2 0x2 /* R---V */
#define NV_NPG_DISCOVERY_ENUM_VERSION_3 0x3 /* R---V */
#define NV_NPG_DISCOVERY_DATA1_RESET 6:2 /* R--UF */
#define NV_NPG_DISCOVERY_DATA1_INTR 11:7 /* R--UF */
#define NV_NPG_DISCOVERY_DATA1_RESERVED2 11:2 /* R--UF */
#define NV_NPG_DISCOVERY_DATA1_NPG_LENGTH 30:12 /* R--UF */
#define NV_NPG_DISCOVERY_DATA1_RESERVED 30:12 /* R--UF */
#define NV_NPG_DISCOVERY_DATA2_TYPE 30:26 /* R--UF */
#define NV_NPG_DISCOVERY_DATA2_TYPE_INVALID 0x0 /* R---V */
#define NV_NPG_DISCOVERY_DATA2_TYPE_RESERVED 0x1 /* R---V */
#define NV_NPG_DISCOVERY_DATA2_TYPE_RESETREG 0x2 /* R---V */
#define NV_NPG_DISCOVERY_DATA2_TYPE_INTRREG 0x3 /* R---V */
#define NV_NPG_DISCOVERY_DATA2_TYPE_DISCOVERY 0x4 /* R---V */
#define NV_NPG_DISCOVERY_DATA2_TYPE_UNICAST 0x5 /* R---V */
#define NV_NPG_DISCOVERY_DATA2_TYPE_BROADCAST 0x6 /* R---V */
#define NV_NPG_DISCOVERY_DATA2_TYPE_MULTICAST0 0x7 /* R---V */
#define NV_NPG_DISCOVERY_DATA2_TYPE_MULTICAST1 0x8 /* R---V */
#define NV_NPG_DISCOVERY_DATA2_TYPE_MULTICAST2 0x9 /* R---V */
#define NV_NPG_DISCOVERY_DATA2_ADDR 25:2 /* R--UF */
#define NV_NPG_DISCOVERY_PRI_BASE_ALIGN 12 /* */
#endif // __ls10_npgip_discovery_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the Software),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __ls10_nvlinkip_discovery_h__
#define __ls10_nvlinkip_discovery_h__
/* This file is autogenerated. Do not edit */
#define NV_NVLINKIP_DISCOVERY_COMMON /* R--4P */
#define NV_NVLINKIP_DISCOVERY_COMMON_ENTRY 1:0 /* R-EVF */
#define NV_NVLINKIP_DISCOVERY_COMMON_ENTRY_INVALID 0x00000000 /* R-E-V */
#define NV_NVLINKIP_DISCOVERY_COMMON_ENTRY_ENUM 0x00000001 /* R---V */
#define NV_NVLINKIP_DISCOVERY_COMMON_ENTRY_DATA1 0x00000002 /* R---V */
#define NV_NVLINKIP_DISCOVERY_COMMON_ENTRY_DATA2 0x00000003 /* R---V */
#define NV_NVLINKIP_DISCOVERY_COMMON_CONTENTS 30:2 /* R-EVF */
#define NV_NVLINKIP_DISCOVERY_COMMON_CONTENTS_INIT 0x00000000 /* R-E-V */
#define NV_NVLINKIP_DISCOVERY_COMMON_CHAIN 31:31 /* R-EVF */
#define NV_NVLINKIP_DISCOVERY_COMMON_CHAIN_DISABLE 0x00000000 /* R-E-V */
#define NV_NVLINKIP_DISCOVERY_COMMON_CHAIN_ENABLE 0x00000001 /* R---V */
#define NV_NVLINKIP_DISCOVERY_COMMON_DEVICE 7:2 /* R--UF */
#define NV_NVLINKIP_DISCOVERY_COMMON_DEVICE_INVALID 0x0 /* R---V */
#define NV_NVLINKIP_DISCOVERY_COMMON_DEVICE_IOCTRL 0x1 /* R---V */
#define NV_NVLINKIP_DISCOVERY_COMMON_DEVICE_NVLTL 0x2 /* R---V */
#define NV_NVLINKIP_DISCOVERY_COMMON_DEVICE_NVLINK 0x3 /* R---V */
#define NV_NVLINKIP_DISCOVERY_COMMON_DEVICE_MINION 0x4 /* R---V */
#define NV_NVLINKIP_DISCOVERY_COMMON_DEVICE_NVLIPT 0x5 /* R---V */
#define NV_NVLINKIP_DISCOVERY_COMMON_DEVICE_NVLTLC 0x6 /* R---V */
#define NV_NVLINKIP_DISCOVERY_COMMON_DEVICE_IOCTRLMIF 0x7 /* R---V */
#define NV_NVLINKIP_DISCOVERY_COMMON_DEVICE_DLPL_MULTICAST 0x8 /* R---V */
#define NV_NVLINKIP_DISCOVERY_COMMON_DEVICE_NVLTLC_MULTICAST 0x9 /* R---V */
#define NV_NVLINKIP_DISCOVERY_COMMON_DEVICE_IOCTRLMIF_MULTICAST 0xA /* R---V */
#define NV_NVLINKIP_DISCOVERY_COMMON_DEVICE_DLPL 0xB /* R---V */
#define NV_NVLINKIP_DISCOVERY_COMMON_DEVICE_SIOCTRL 0xC /* R---V */
#define NV_NVLINKIP_DISCOVERY_COMMON_DEVICE_TIOCTRL 0xD /* R---V */
#define NV_NVLINKIP_DISCOVERY_COMMON_DEVICE_SIOCTRL_PERFMON 0xE /* R---V */
#define NV_NVLINKIP_DISCOVERY_COMMON_DEVICE_NVLIPT_SYS_PERFMON 0xF /* R---V */
#define NV_NVLINKIP_DISCOVERY_COMMON_DEVICE_TX_PERFMON_MULTICAST 0x10 /* R---V */
#define NV_NVLINKIP_DISCOVERY_COMMON_DEVICE_RX_PERFMON_MULTICAST 0x11 /* R---V */
#define NV_NVLINKIP_DISCOVERY_COMMON_DEVICE_TX_PERFMON 0x12 /* R---V */
#define NV_NVLINKIP_DISCOVERY_COMMON_DEVICE_RX_PERFMON 0x13 /* R---V */
#define NV_NVLINKIP_DISCOVERY_COMMON_DEVICE_NVLW 0x14 /* R---V */
#define NV_NVLINKIP_DISCOVERY_COMMON_DEVICE_NVLW_PERFMON 0x15 /* R---V */
#define NV_NVLINKIP_DISCOVERY_COMMON_DEVICE_NVLDL 0x16 /* R---V */
#define NV_NVLINKIP_DISCOVERY_COMMON_DEVICE_NVLDL_MULTICAST 0x17 /* R---V */
#define NV_NVLINKIP_DISCOVERY_COMMON_DEVICE_SYS_PERFMON 0x18 /* R---V */
#define NV_NVLINKIP_DISCOVERY_COMMON_DEVICE_SYS_PERFMON_MULTICAST 0x19 /* R---V */
#define NV_NVLINKIP_DISCOVERY_COMMON_DEVICE_NVLIPT_LNK 0x1A /* R---V */
#define NV_NVLINKIP_DISCOVERY_COMMON_DEVICE_NVLIPT_LNK_MULTICAST 0x1B /* R---V */
#define NV_NVLINKIP_DISCOVERY_COMMON_DEVICE_PLL 0x1C /* R---V */
#define NV_NVLINKIP_DISCOVERY_COMMON_DEVICE_CPR 0x1D /* R---V */
#define NV_NVLINKIP_DISCOVERY_COMMON_ID 15:8 /* R--UF */
#define NV_NVLINKIP_DISCOVERY_COMMON_RESERVED 19:16 /* R--UF */
#define NV_NVLINKIP_DISCOVERY_COMMON_VERSION 30:20 /* R--UF */
#define NV_NVLINKIP_DISCOVERY_COMMON_VERSION_NVLINK10 0x1 /* R---V */
#define NV_NVLINKIP_DISCOVERY_COMMON_VERSION_NVLINK20 0x2 /* R---V */
#define NV_NVLINKIP_DISCOVERY_COMMON_VERSION_3 0x3 /* R---V */
#define NV_NVLINKIP_DISCOVERY_COMMON_VERSION_NVLINK22 0x4 /* R---V */
#define NV_NVLINKIP_DISCOVERY_COMMON_VERSION_NVLINK30 0x5 /* R---V */
#define NV_NVLINKIP_DISCOVERY_COMMON_VERSION_NVLINK31 0x6 /* R---V */
#define NV_NVLINKIP_DISCOVERY_COMMON_VERSION_NVLINK40 0x7 /* R---V */
#define NV_NVLINKIP_DISCOVERY_COMMON_DATA1_RESERVED 30:12 /* R--UF */
#define NV_NVLINKIP_DISCOVERY_COMMON_DATA1_IOCTRL_LENGTH 30:12 /* R--UF */
#define NV_NVLINKIP_DISCOVERY_COMMON_DATA1_RESERVED2 11:2 /* R--UF */
#define NV_NVLINKIP_DISCOVERY_COMMON_DATA2_TYPE 30:26 /* R--UF */
#define NV_NVLINKIP_DISCOVERY_COMMON_DATA2_TYPE_INVALID 0x0 /* R---V */
#define NV_NVLINKIP_DISCOVERY_COMMON_DATA2_TYPE_PLLCONTROL 0x1 /* R---V */
#define NV_NVLINKIP_DISCOVERY_COMMON_DATA2_TYPE_RESETREG 0x2 /* R---V */
#define NV_NVLINKIP_DISCOVERY_COMMON_DATA2_TYPE_INTRREG 0x3 /* R---V */
#define NV_NVLINKIP_DISCOVERY_COMMON_DATA2_TYPE_DISCOVERY 0x4 /* R---V */
#define NV_NVLINKIP_DISCOVERY_COMMON_DATA2_TYPE_UNICAST 0x5 /* R---V */
#define NV_NVLINKIP_DISCOVERY_COMMON_DATA2_TYPE_BROADCAST 0x6 /* R---V */
#define NV_NVLINKIP_DISCOVERY_COMMON_DATA2_TYPE_MULTICAST0 0x7 /* R---V */
#define NV_NVLINKIP_DISCOVERY_COMMON_DATA2_TYPE_MULTICAST1 0x8 /* R---V */
#define NV_NVLINKIP_DISCOVERY_COMMON_DATA2_TYPE_MULTICAST2 0x9 /* R---V */
#define NV_NVLINKIP_DISCOVERY_COMMON_DATA2_ADDR 25:2 /* R--UF */
#define NV_NVLINKIP_DISCOVERY_COMMON_DATA2_ADDR_ALIGN 2 /* */
#endif // __ls10_nvlinkip_discovery_h__

74
src/common/inc/swref/published/nvswitch/ls10/nxbar_discovery.h Normal file
View File

@@ -0,0 +1,74 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the Software),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __ls10_nxbar_discovery_h__
#define __ls10_nxbar_discovery_h__
/* This file is autogenerated. Do not edit */
#define NV_NXBAR_DISCOVERY /* R--4P */
#define NV_NXBAR_DISCOVERY_ENTRY 1:0 /* R-EVF */
#define NV_NXBAR_DISCOVERY_ENTRY_INVALID 0x00000000 /* R-E-V */
#define NV_NXBAR_DISCOVERY_ENTRY_ENUM 0x00000001 /* R---V */
#define NV_NXBAR_DISCOVERY_ENTRY_DATA1 0x00000002 /* R---V */
#define NV_NXBAR_DISCOVERY_ENTRY_DATA2 0x00000003 /* R---V */
#define NV_NXBAR_DISCOVERY_CONTENTS 30:2 /* R-EVF */
#define NV_NXBAR_DISCOVERY_CONTENTS_INIT 0x00000000 /* R-E-V */
#define NV_NXBAR_DISCOVERY_CHAIN 31:31 /* R-EVF */
#define NV_NXBAR_DISCOVERY_CHAIN_DISABLE 0x00000000 /* R-E-V */
#define NV_NXBAR_DISCOVERY_CHAIN_ENABLE 0x00000001 /* R---V */
#define NV_NXBAR_DISCOVERY_ENUM_DEVICE 7:2 /* R--UF */
#define NV_NXBAR_DISCOVERY_ENUM_DEVICE_INVALID 0x0 /* R---V */
#define NV_NXBAR_DISCOVERY_ENUM_DEVICE_NXBAR 0x1 /* R---V */
#define NV_NXBAR_DISCOVERY_ENUM_DEVICE_TILE 0x2 /* R---V */
#define NV_NXBAR_DISCOVERY_ENUM_DEVICE_TILE_MULTICAST 0x3 /* R---V */
#define NV_NXBAR_DISCOVERY_ENUM_DEVICE_NXBAR_PERFMON 0x4 /* R---V */
#define NV_NXBAR_DISCOVERY_ENUM_DEVICE_TILE_PERFMON 0x5 /* R---V */
#define NV_NXBAR_DISCOVERY_ENUM_DEVICE_TILE_PERFMON_MULTICAST 0x6 /* R---V */
#define NV_NXBAR_DISCOVERY_ENUM_DEVICE_TILEOUT 0x7 /* R---V */
#define NV_NXBAR_DISCOVERY_ENUM_DEVICE_TILEOUT_MULTICAST 0x8 /* R---V */
#define NV_NXBAR_DISCOVERY_ENUM_DEVICE_TILEOUT_PERFMON 0x9 /* R---V */
#define NV_NXBAR_DISCOVERY_ENUM_DEVICE_TILEOUT_PERFMON_MULTICAST 0xA /* R---V */
#define NV_NXBAR_DISCOVERY_ENUM_ID 15:8 /* R--UF */
#define NV_NXBAR_DISCOVERY_ENUM_RESERVED 19:16 /* R--UF */
#define NV_NXBAR_DISCOVERY_ENUM_VERSION 30:20 /* R--UF */
#define NV_NXBAR_DISCOVERY_ENUM_VERSION_1 0x1 /* R---V */
#define NV_NXBAR_DISCOVERY_ENUM_VERSION_2 0x2 /* R---V */
#define NV_NXBAR_DISCOVERY_ENUM_VERSION_3 0x3 /* R---V */
#define NV_NXBAR_DISCOVERY_DATA1_RESET 6:2 /* R--UF */
#define NV_NXBAR_DISCOVERY_DATA1_INTR 11:7 /* R--UF */
#define NV_NXBAR_DISCOVERY_DATA1_RESERVED2 11:2 /* R--UF */
#define NV_NXBAR_DISCOVERY_DATA1_NXBAR_LENGTH 30:12 /* R--UF */
#define NV_NXBAR_DISCOVERY_DATA1_RESERVED 30:12 /* R--UF */
#define NV_NXBAR_DISCOVERY_DATA2_TYPE 30:26 /* R--UF */
#define NV_NXBAR_DISCOVERY_DATA2_TYPE_INVALID 0x0 /* R---V */
#define NV_NXBAR_DISCOVERY_DATA2_TYPE_RESERVED 0x1 /* R---V */
#define NV_NXBAR_DISCOVERY_DATA2_TYPE_RESETREG 0x2 /* R---V */
#define NV_NXBAR_DISCOVERY_DATA2_TYPE_INTRREG 0x3 /* R---V */
#define NV_NXBAR_DISCOVERY_DATA2_TYPE_DISCOVERY 0x4 /* R---V */
#define NV_NXBAR_DISCOVERY_DATA2_TYPE_UNICAST 0x5 /* R---V */
#define NV_NXBAR_DISCOVERY_DATA2_TYPE_BROADCAST 0x6 /* R---V */
#define NV_NXBAR_DISCOVERY_DATA2_TYPE_MULTICAST0 0x7 /* R---V */
#define NV_NXBAR_DISCOVERY_DATA2_TYPE_MULTICAST1 0x8 /* R---V */
#define NV_NXBAR_DISCOVERY_DATA2_TYPE_MULTICAST2 0x9 /* R---V */
#define NV_NXBAR_DISCOVERY_DATA2_ADDR 25:2 /* R--UF */
#define NV_NXBAR_DISCOVERY_PRI_BASE_ALIGN 12 /* */
#endif // __ls10_nxbar_discovery_h__

1
src/common/inc/swref/published/pcie_switch/pcie_switch_ref.h
View File

@@ -26,6 +26,7 @@
#include "published/br03/dev_br03_xvd.h"
#include "published/br03/dev_br03_xvu.h"
#include "published/br04/br04_ref.h"
#include "nvdevid.h"
//
// This file has the vendor and device IDs of all supported PCIe switches

2
src/common/modeset/hdmipacket/nvhdmipkt.h
View File

@@ -254,6 +254,7 @@ typedef struct _tagNVHDMIPKT_CALLBACK
NvBool expression);
} NVHDMIPKT_CALLBACK;
/*********************** HDMI Library interface to write hdmi ctrl/packet ***********************/
typedef void* NvHdmiPkt_Handle;
#define NVHDMIPKT_INVALID_HANDLE ((NvHdmiPkt_Handle)0)
@@ -300,6 +301,7 @@ NvHdmiPkt_PacketWrite(NvHdmiPkt_Handle libHandle,
NvU32 packetLen,
NvU8 const *const pPacket);
/***************************** Interface to initialize HDMI Library *****************************/
/************************************************************************************************

1
src/common/modeset/hdmipacket/nvhdmipkt_0073.c
View File

@@ -388,4 +388,5 @@ initializeHdmiPktInterface0073(NVHDMIPKT_CLASS* pClass)
pClass->hdmiQueryFRLConfig = hdmiQueryFRLConfigDummy;
pClass->hdmiSetFRLConfig = hdmiSetFRLConfigDummy;
pClass->hdmiClearFRLConfig = hdmiClearFRLConfigDummy;
}

1
src/common/modeset/hdmipacket/nvhdmipkt_9171.c
View File

@@ -846,4 +846,5 @@ initializeHdmiPktInterface9171(NVHDMIPKT_CLASS* pClass)
pClass->hdmiQueryFRLConfig = hdmiQueryFRLConfigDummy;
pClass->hdmiSetFRLConfig = hdmiSetFRLConfigDummy;
pClass->hdmiClearFRLConfig = hdmiClearFRLConfigDummy;
}

1
src/common/modeset/hdmipacket/nvhdmipkt_common.h
View File

@@ -110,5 +110,4 @@ extern NVHDMIPKT_RESULT hdmiClearFRLConfigDummy(NVHDMIPKT_CLASS *pThis,
NvU32 subDevice,
NvU32 displayId);
#endif //_NVHDMIPKT_COMMON_H_

93
src/common/modeset/timing/displayid20.h
View File

@@ -1,6 +1,6 @@
//*****************************************************************************
//
// SPDX-FileCopyrightText: Copyright (c) 2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
// SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
// SPDX-License-Identifier: MIT
//
// Permission is hereby granted, free of charge, to any person obtaining a
@@ -100,14 +100,20 @@ typedef struct _tagDISPLAYID_2_0_DATA_BLOCK_HEADER
#define DISPLAYID_2_0_BLOCK_TYPE_TIMING_7 0x22
#define DISPLAYID_2_0_BLOCK_TYPE_TIMING_8 0x23
#define DISPLAYID_2_0_BLOCK_TYPE_TIMING_9 0x24
#define DISPLAYID_2_0_BLOCK_TYPE_TIMING_10 0x2A
#define DISPLAYID_2_0_BLOCK_TYPE_RANGE_LIMITS 0x25
#define DISPLAYID_2_0_BLOCK_TYPE_INTERFACE_FEATURES 0x26
#define DISPLAYID_2_0_BLOCK_TYPE_STEREO 0x27
#define DISPLAYID_2_0_BLOCK_TYPE_TILED_DISPLAY 0x28
#define DISPLAYID_2_0_BLOCK_TYPE_CONTAINER_ID 0x29
#define DISPLAYID_2_0_BLOCK_TYPE_TIMING_10 0x2A
#define DISPLAYID_2_0_BLOCK_TYPE_ADAPTIVE_SYNC 0x2B
#define DISPLAYID_2_0_BLOCK_TYPE_ARVR_HMD 0x2C
#define DISPLAYID_2_0_BLOCK_TYPE_ARVR_LAYER 0x2D
// 0x7D - 0x2E RESERVED for Additional VESA-defined Data Blocks
#define DISPLAYID_2_0_BLOCK_TYPE_VENDOR_SPEC 0x7E
// 0x80 - 0x7F RESERVED
#define DISPLAYID_2_0_BLOCK_TYPE_CTA_DATA 0x81
// 0xFF - 0x82 RESERVED for additional data blocks related to external standards organization(s).
#define DISPLAYID_2_0_PRODUCT_NAME_STRING_MAX_LEN ((0xFB - 0xF) + 1)
@@ -236,7 +242,7 @@ typedef struct _tag_DISPLAYID_2_0_TIMING_7_DESCRIPTOR
NvU8 interface_frame_scanning_type : 1;
NvU8 stereo_support : 2;
NvU8 is_preferred_or_ycc420 : 1;
}options;
} options;
struct
{
@@ -246,7 +252,7 @@ typedef struct _tag_DISPLAYID_2_0_TIMING_7_DESCRIPTOR
NvU8 front_porch_pixels_high : 7;
NvU8 sync_polarity : 1;
NvU8 sync_width_pixels[2];
}horizontal;
} horizontal;
struct
{
@@ -256,8 +262,7 @@ typedef struct _tag_DISPLAYID_2_0_TIMING_7_DESCRIPTOR
NvU8 front_porch_lines_high : 7;
NvU8 sync_polarity : 1;
NvU8 sync_width_lines[2];
}vertical;
} vertical;
} DISPLAYID_2_0_TIMING_7_DESCRIPTOR;
#define DISPLAYID_2_0_TIMING_7_MAX_DESCRIPTORS 12
@@ -336,11 +341,11 @@ typedef struct _tagDISPLAYID_2_0_TIMING_8_BLOCK
typedef struct _TAG_DISPLAYID_2_0_TIMING_9_DESCRIPTOR
{
struct {
NvU8 timing_formula:3;
NvU8 reserved0:1;
NvU8 fractional_refresh_rate_support:1;
NvU8 stereo_support:2;
NvU8 reserved1:1;
NvU8 timing_formula :3;
NvU8 reserved0 :1;
NvU8 rr_1000div1001_support :1;
NvU8 stereo_support :2;
NvU8 reserved1 :1;
} options;
NvU8 horizontal_active_pixels[2];
@@ -350,10 +355,10 @@ typedef struct _TAG_DISPLAYID_2_0_TIMING_9_DESCRIPTOR
#define DISPLAYID_2_0_TIMING_FORMULA_CVT_1_2_STANDARD 0
#define DISPLAYID_2_0_TIMING_FORMULA_CVT_1_2_REDUCED_BLANKING_1 1
#define DISPLAYID_2_0_TIMING_FORMULA_CVT_1_2_REDUCED_BLANKING_2 2
#define DISPLAYID_2_0_TIMING_FORMULA_CVT_1_2_REDUCED_BLANKING_3 3
#define DISPLAYID_2_0_TIMING_FORMULA_CVT_2_0_REDUCED_BLANKING_2 2
#define DISPLAYID_2_0_TIMING_FORMULA_CVT_2_0_REDUCED_BLANKING_3 3
#define DISPLAYID_2_0_TIMING_9_MAX_DESCRIPTORS 41
#define DISPLAYID_2_0_TIMING_9_MAX_DESCRIPTORS 18
typedef struct _tagDISPLAYID_2_0_TIMING_9_BLOCK
{
@@ -379,8 +384,8 @@ typedef struct _DISPLAYID_2_0_TIMING_10_6BYTES_DESCRIPTOR
{
struct {
NvU8 timing_formula :3;
NvU8 reserved0 :1;
NvU8 vrr_or_hblank :1;
NvU8 early_vsync :1;
NvU8 rr1000div1001_or_hblank :1;
NvU8 stereo_support :2;
NvU8 ycc420_support :1;
} options;
@@ -398,8 +403,8 @@ typedef struct _DISPLAYID_2_0_TIMING_10_7BYTES_DESCRIPTOR
NvU8 additional_vblank_timing :3;
} DISPLAYID_2_0_TIMING_10_7BYTES_DESCRIPTOR;
#define DISPLAYID_2_0_TIMING_10_MAX_6BYTES_DESCRIPTORS 41
#define DISPLAYID_2_0_TIMING_10_MAX_7BYTES_DESCRIPTORS 35
#define DISPLAYID_2_0_TIMING_10_MAX_6BYTES_DESCRIPTORS 18
#define DISPLAYID_2_0_TIMING_10_MAX_7BYTES_DESCRIPTORS 16
typedef struct _DISPLAYID_2_0_TIMING_10_BLOCK
{
@@ -416,10 +421,11 @@ typedef struct _tagDISPLAYID_2_0_RANGE_LIMITS_BLOCK
NvU8 pixel_clock_max[3];
NvU8 vertical_frequency_min;
NvU8 vertical_frequency_max_7_0;
struct {
NvU8 vertical_frequency_max_9_8:2;
NvU8 reserved:5;
NvU8 seamless_dynamic_video_timing_change:1;
NvU8 vertical_frequency_max_9_8 :2;
NvU8 reserved :5;
NvU8 seamless_dynamic_video_timing_change :1;
} dynamic_video_timing_range_support;
} DISPLAYID_2_0_RANGE_LIMITS_BLOCK;
@@ -677,6 +683,51 @@ typedef struct _tagDISPLAYID_2_0_CONTAINERID_BLOCK
NvU8 container_id[DISPLAYID_2_0_CONTAINERID_BLOCK_PAYLOAD_LENGTH];
} DISPLAYID_2_0_CONTAINERID_BLOCK;
#define DISPLAYID_2_0_ADAPTIVE_SYNC_DETAILED_TIMING_COUNT 4
typedef struct _tagDISPLAYID_2_0_ADAPTIVE_SYNC_BLOCK_HEADER
{
NvU8 type; // Adaptive-Sync (0x2B)
NvU8 revision :3;
NvU8 reserved0 :1;
NvU8 payload_bytes_adaptive_sync_len :3;
NvU8 reserved1 :1;
NvU8 payload_bytes;
} DISPLAYID_2_0_ADAPTIVE_SYNC_BLOCK_HEADER;
typedef struct _tagDISPLAYID_2_0_ADAPTIVE_SYNC_DESCRIPTOR
{
struct
{
NvU8 range : 1;
NvU8 successive_frame_inc_tolerance : 1;
NvU8 modes : 2;
NvU8 seamless_transition_not_support: 1;
NvU8 successive_frame_dec_tolerance : 1;
NvU8 reserved : 2;
} operation_range_info;
// 6.2 format (six integer bits and two fractional bits)
// six integer bits == 0 - 63ms
// two fractional bits == 0.00(00), 0.25(01b),0.50(10), 0.75(11b)
NvU8 max_single_frame_inc;
NvU8 min_refresh_rate;
struct
{
NvU8 max_rr_7_0;
NvU8 max_rr_9_8 : 2;
NvU8 reserved : 6;
} max_refresh_rate;
// same as max_single_frame_inc expression
NvU8 max_single_frame_dec;
} DISPLAYID_2_0_ADAPTIVE_SYNC_DESCRIPTOR;
typedef struct _tagDISPLAYID_2_0_ADAPTIVE_SYNC_BLOCK
{
DISPLAYID_2_0_ADAPTIVE_SYNC_BLOCK_HEADER header;
DISPLAYID_2_0_ADAPTIVE_SYNC_DESCRIPTOR descriptors[DISPLAYID_2_0_ADAPTIVE_SYNC_DETAILED_TIMING_COUNT];
} DISPLAYID_2_0_ADAPTIVE_SYNC_BLOCK;
typedef struct _tagDISPLAYID_2_0_VENDOR_SPECIFIC_BLOCK
{
DISPLAYID_2_0_DATA_BLOCK_HEADER header;

34
src/common/modeset/timing/dpsdp.h
View File

@@ -49,8 +49,8 @@ typedef enum tagSDP_VSC_REVNUM
{
SDP_VSC_REVNUM_STEREO = 1,
SDP_VSC_REVNUM_STEREO_PSR,
SDP_VSC_REVNUM_STEREO_PSR2,
SDP_VSC_REVNUM_PSR2_EXTN,
SDP_VSC_REVNUM_STEREO_PSR2,
SDP_VSC_REVNUM_PSR2_EXTN,
SDP_VSC_REVNUM_STEREO_PSR2_COLOR,
SDP_VSC_REVNUM_STEREO_PR,
SDP_VSC_REVNUM_STEREO_PR_COLOR,
@@ -60,7 +60,7 @@ typedef enum tagSDP_VSC_VALID_DATA_BYTES
{
SDP_VSC_VALID_DATA_BYTES_STEREO = 1,
SDP_VSC_VALID_DATA_BYTES_STEREO_PSR = 8,
SDP_VSC_VALID_DATA_BYTES_PSR2 = 12,
SDP_VSC_VALID_DATA_BYTES_PSR2 = 12,
SDP_VSC_VALID_DATA_BYTES_PSR2_COLOR = 19,
SDP_VSC_VALID_DATA_BYTES_PR = 16,
SDP_VSC_VALID_DATA_BYTES_PR_COLOR = 19,
@@ -161,7 +161,7 @@ typedef enum tagSDP_VSC_COLOR_FMT_Y_COLORIMETRY
typedef struct tagDPSDP_DP_VSC_SDP_DESCRIPTOR
{
NvU8 dataSize; // the db data size
// header
struct
{
@@ -174,11 +174,11 @@ typedef struct tagDPSDP_DP_VSC_SDP_DESCRIPTOR
} hb;
// data content
struct
struct
{
// Stereo field. Note: Needs to be expanded when needed. Refer to DP1.3 spec.
// Stereo field. Note: Needs to be expanded when needed. Refer to DP1.3 spec.
NvU8 stereoInterface; // DB0
// PSR Field. Note: Needs to be expanded when needed. Refer to DP1.3 spec.
// PSR Field. Note: Needs to be expanded when needed. Refer to DP1.3 spec.
NvU8 psrState : 1; //DB1
NvU8 psrUpdateRfb : 1;
NvU8 psrCrcValid : 1;
@@ -203,7 +203,7 @@ typedef struct tagDPSDP_DP_VSC_SDP_DESCRIPTOR
NvU8 db14;
NvU8 db15;
// Colorimetry Infoframe Secondary Data Package following DP1.3 spec
// Colorimetry Infoframe Secondary Data Package following DP1.3 spec
NvU8 colorimetryFormat : 4; // DB16 infoframe per DP1.3 spec
NvU8 pixEncoding : 4; // DB16 infoframe per DP1.3 spec
@@ -229,7 +229,7 @@ typedef struct tagDPSDP_DP_VSC_SDP_DESCRIPTOR
typedef struct tagDPSDP_DP_PR_VSC_SDP_DESCRIPTOR
{
NvU8 dataSize; // the db data size
// header
struct
{
@@ -242,11 +242,11 @@ typedef struct tagDPSDP_DP_PR_VSC_SDP_DESCRIPTOR
} hb;
// data content
struct
struct
{
// Stereo field. Note: Needs to be expanded when needed. Refer to DP1.3 spec.
// Stereo field. Note: Needs to be expanded when needed. Refer to DP1.3 spec.
NvU8 stereoInterface; // DB0
// PSR Field. Note: Needs to be expanded when needed. Refer to DP1.3 spec.
// PSR Field. Note: Needs to be expanded when needed. Refer to DP1.3 spec.
NvU8 prState : 1; // DB1
NvU8 prReserved : 1; // Always ZERO
NvU8 prCrcValid : 1;
@@ -268,7 +268,7 @@ typedef struct tagDPSDP_DP_PR_VSC_SDP_DESCRIPTOR
NvU8 db14;
NvU8 db15;
// Colorimetry Infoframe Secondary Data Package following DP1.3 spec
// Colorimetry Infoframe Secondary Data Package following DP1.3 spec
NvU8 colorimetryFormat : 4; // DB16 infoframe per DP1.3 spec
NvU8 pixEncoding : 4; // DB16 infoframe per DP1.3 spec
@@ -294,12 +294,12 @@ typedef struct tagDPSDP_DP_PR_VSC_SDP_DESCRIPTOR
typedef struct tagDPSDP_DESCRIPTOR
{
NvU8 dataSize;
// header byte
struct
struct
{
NvU8 hb0;
NvU8 hb1;
NvU8 hb1;
NvU8 hb2;
NvU8 hb3;
} hb;
@@ -308,7 +308,7 @@ typedef struct tagDPSDP_DESCRIPTOR
struct
{
NvU8 db0;
NvU8 db1;
NvU8 db1;
NvU8 db2;
NvU8 db3;
NvU8 db4;

17
src/common/modeset/timing/edid.h
View File

@@ -30,12 +30,12 @@
#ifndef __EDID_H_
#define __EDID_H_
#include "nvtiming.h"
#include "nvtiming_pvt.h"
#include "displayid.h"
#include "displayid20.h"
// EDID 1.x detailed timing template
#define NVT_PVT_EDID_LDD_PAYLOAD_SIZE 13
typedef struct _tagEDID_LONG_DISPLAY_DESCRIPTOR
@@ -286,7 +286,6 @@ typedef struct _tagEIA861EXTENSION
NvU8 checksum; // 0x7F
}EIA861EXTENSION;
typedef struct _tagVTBEXTENSION
{
NvU8 tag; // 0x00
@@ -298,6 +297,18 @@ typedef struct _tagVTBEXTENSION
NvU8 checksum;
}VTBEXTENSION;
// EDID DisplayID extension block template
typedef struct _tagDIDEXTENSION
{
NvU8 tag; // 0x00
NvU8 struct_version; // 0x01
NvU8 length; // 0x02
NvU8 use_case; // 0x03
NvU8 ext_count; // 0x04
NvU8 data[NVT_DID_MAX_EXT_PAYLOAD]; // 0x05 - 0x7E
NvU8 checksum; // 0x7F
}DIDEXTENSION;
// video signal interface mask
#define NVT_PVT_EDID_INPUT_ISDIGITAL_MASK 0x80 // 0==analog
#define NVT_PVT_EDID_INPUT_ISDIGITAL_SHIFT 7

1045
src/common/modeset/timing/nvt_displayid20.c
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