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https://github.com/NVIDIA/open-gpu-kernel-modules.git
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525.53
This commit is contained in:
Andy Ritger
376
src/common/nvswitch/kernel/ls10/flcn_ls10.c
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376
src/common/nvswitch/kernel/ls10/flcn_ls10.c
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/*
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* SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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* SPDX-License-Identifier: MIT
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include "common_nvswitch.h"
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#include "ls10/ls10.h"
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#include "flcn/flcn_nvswitch.h"
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#include "nvswitch/ls10/dev_falcon_v4.h"
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#include "nvswitch/ls10/dev_riscv_pri.h"
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//
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// Functions shared with LR10
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//
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void flcnSetupHal_LR10(PFLCN pFlcn);
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static NvU32
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_flcnRiscvRegRead_LS10
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(
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nvswitch_device *device,
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PFLCN pFlcn,
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NvU32 offset
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)
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{
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// Probably should perform some checks on the offset, the device, and the engine descriptor
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return nvswitch_reg_read_32(device, NV_FALCON2_SOE_BASE + offset);
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}
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static void
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_flcnRiscvRegWrite_LS10
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(
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nvswitch_device *device,
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PFLCN pFlcn,
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NvU32 offset,
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NvU32 data
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)
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{
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// Probably should perform some checks on the offset, the device, and the engine descriptor
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nvswitch_reg_write_32(device, NV_FALCON2_SOE_BASE + offset, data);
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}
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/*!
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* @brief Retrieve the size of the falcon data memory.
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*
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* @param[in] pGpu OBJGPU pointer
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* @param[in] pFlcn Falcon object pointer
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* @param[in] bFalconReachable If set, returns size that can be reached by Falcon
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*
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* @return IMEM size in bytes
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*/
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static NvU32
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_flcnDmemSize_LS10
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(
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nvswitch_device *device,
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PFLCN pFlcn
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)
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{
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NvU32 data = flcnRegRead_HAL(device, pFlcn, NV_PFALCON_FALCON_HWCFG3);
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return (DRF_VAL(_PFALCON, _FALCON_HWCFG3, _DMEM_TOTAL_SIZE, data) <<
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FALCON_DMEM_BLKSIZE2);
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}
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/*
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* @brief Get the destination after masking
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* off all but the OFFSET and BLOCK in IMEM
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*
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* @param[in] dst Destination in IMEM
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*
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* @returns dst with only OFFSET and BLOCK bits set
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*/
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static NvU32
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_flcnSetImemAddr_LS10
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(
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nvswitch_device *device,
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PFLCN pFlcn,
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NvU32 dst
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)
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{
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NVSWITCH_ASSERT(0);
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return 0;
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}
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/*!
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*
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* @brief Copy contents of pSrc to IMEM
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*
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* @param[in] pGpu OBJGPU pointer
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* @param[in] pFlcn Falcon object pointer
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* @param[in] dst Destination in IMEM
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* @param[in] pSrc IMEM contents
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* @param[in] sizeInBytes Total IMEM size in bytes
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* @param[in] bSecure NV_TRUE if IMEM is signed
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* @param[in] tag IMEM tag
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* @param[in] port PMB port to copy IMEM
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*
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* @returns void
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*/
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static void
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_flcnImemCopyTo_LS10
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(
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nvswitch_device *device,
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PFLCN pFlcn,
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NvU32 dst,
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NvU8 *pSrc,
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NvU32 sizeBytes,
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NvBool bSecure,
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NvU32 tag,
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NvU8 port
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)
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{
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}
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/*!
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*
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* @brief Mask the DMEM destination to have only the BLK and OFFSET bits set
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*
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* @param[in] dst Destination in DMEM
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*
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* @returns masked destination value in DMEM
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*/
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static NvU32
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_flcnSetDmemAddr_LS10
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(
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nvswitch_device *device,
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PFLCN pFlcn,
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NvU32 dst
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)
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{
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return (dst & (DRF_SHIFTMASK(NV_PFALCON_FALCON_DMEMC_OFFS) |
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DRF_SHIFTMASK(NV_PFALCON_FALCON_DMEMC_BLK)));
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}
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/*!
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* Depending on the direction of the copy, copies 'sizeBytes' to/from 'pBuf'
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* from/to DMEM offset 'dmemAddr' using DMEM access port 'port'.
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*
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* @param[in] pGpu GPU object pointer
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* @param[in] pFlcn Falcon object pointer
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* @param[in] dmemAddr The DMEM offset for the copy
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* @param[in] pBuf The pointer to the buffer containing the data to copy
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* @param[in] sizeBytes The number of bytes to copy
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* @param[in] port The DMEM port index to use when accessing DMEM
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* @param[in] bCopyFrom Boolean representing the copy direction (to/from DMEM)
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*
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* @return NV_OK if the data was successfully copied
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* NV_ERR_INVALID_ARGUMENT if the input argument(s) is/are invalid
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*/
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static NV_STATUS
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_flcnDmemTransfer_LS10
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(
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nvswitch_device *device,
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PFLCN pFlcn,
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NvU32 dmemAddr,
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NvU8 *pBuf,
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NvU32 sizeBytes,
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NvU8 port,
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NvBool bCopyFrom
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)
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{
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NvU32 numWords;
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NvU32 numBytes;
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NvU32 *pData = (NvU32 *)pBuf;
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NvU32 reg32;
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NvU32 i;
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// simply return if the copy-size is zero
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if (sizeBytes == 0)
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{
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NVSWITCH_PRINT(device, ERROR, "Zero-byte copy requested\n");
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NVSWITCH_ASSERT(0);
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return -NVL_BAD_ARGS;
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}
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// the DMEM address must be 4-byte aligned
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if (!NV_IS_ALIGNED(dmemAddr, FLCN_DMEM_ACCESS_ALIGNMENT))
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{
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NVSWITCH_PRINT(device, ERROR, "Source not 4-byte aligned. dmemAddr=0x%08x\n", dmemAddr);
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NVSWITCH_ASSERT(0);
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return -NVL_BAD_ARGS;
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}
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// calculate the number of words and bytes
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numWords = sizeBytes >> 2;
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numBytes = sizeBytes & NVSWITCH_MASK_BITS(2);
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// mask off all but the OFFSET and BLOCK in DMEM offset
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reg32 = flcnSetDmemAddr_HAL(device, pFlcn, dmemAddr);
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if (bCopyFrom)
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{
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// mark auto-increment on read
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reg32 = FLD_SET_DRF_NUM(_PFALCON, _FALCON_DMEMC, _AINCR, 0x1, reg32);
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}
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else
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{
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// mark auto-increment on write
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reg32 = FLD_SET_DRF_NUM(_PFALCON, _FALCON_DMEMC, _AINCW, 0x1, reg32);
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}
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flcnRegWrite_HAL(device, pFlcn, NV_PFALCON_FALCON_DMEMC(port), reg32);
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// directly copy as many words as possible
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for (i = 0; i < numWords; i++)
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{
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if (bCopyFrom)
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{
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pData[i] = flcnRegRead_HAL(device, pFlcn, NV_PFALCON_FALCON_DMEMD(port));
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}
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else
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{
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flcnRegWrite_HAL(device, pFlcn, NV_PFALCON_FALCON_DMEMD(port), pData[i]);
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}
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}
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// Check if there are left over bytes to copy
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if (numBytes > 0)
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{
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NvU32 bytesCopied = numWords << 2;
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//
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// Read the contents first. If we're copying to the DMEM, we've set
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// autoincrement on write, so reading does not modify the pointer. We
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// can, thus, do a read/modify/write without needing to worry about the
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// pointer having moved forward. There is no special explanation needed
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// if we're copying from the DMEM since this is the last access to HW
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// in that case.
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//
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reg32 = flcnRegRead_HAL(device, pFlcn, NV_PFALCON_FALCON_DMEMD(port));
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if (bCopyFrom)
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{
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// Copy byte-by-byte into the buffer as required
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for (i = 0; i < numBytes; i++)
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{
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pBuf[bytesCopied + i] = ((NvU8 *)®32)[i];
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}
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}
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else
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{
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// Modify what we read byte-by-byte before writing to dmem
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for (i = 0; i < numBytes; i++)
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{
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((NvU8 *)®32)[i] = pBuf[bytesCopied + i];
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}
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flcnRegWrite_HAL(device, pFlcn, NV_PFALCON_FALCON_DMEMD(port), reg32);
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}
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}
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return NVL_SUCCESS;
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}
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static void
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_flcnDbgInfoCaptureRiscvPcTrace_LS10
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(
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nvswitch_device *device,
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PFLCN pFlcn
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)
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{
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NvU32 ctl, ridx, widx, count, bufferSize;
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NvBool full;
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flcnRiscvRegWrite_HAL(device, pFlcn, NV_PRISCV_RISCV_TRACECTL,
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DRF_DEF(_PRISCV_RISCV, _TRACECTL, _MODE, _FULL) |
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DRF_DEF(_PRISCV_RISCV, _TRACECTL, _UMODE_ENABLE, _TRUE) |
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DRF_DEF(_PRISCV_RISCV, _TRACECTL, _MMODE_ENABLE, _TRUE) |
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DRF_DEF(_PRISCV_RISCV, _TRACECTL, _INTR_ENABLE, _FALSE) |
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DRF_DEF(_PRISCV_RISCV, _TRACECTL, _HIGH_THSHD, _INIT));
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ctl = flcnRiscvRegRead_HAL(device, pFlcn, NV_PRISCV_RISCV_TRACECTL);
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full = FLD_TEST_DRF_NUM(_PRISCV_RISCV, _TRACECTL,_FULL, 1, ctl);
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if (full)
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{
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NVSWITCH_PRINT(device, INFO, "%s: Trace buffer full. Entries may have been lost.\n", __FUNCTION__);
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}
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// Reset and disable buffer, we don't need it during dump
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flcnRiscvRegWrite_HAL(device, pFlcn, NV_PRISCV_RISCV_TRACECTL, 0);
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widx = flcnRiscvRegRead_HAL(device, pFlcn, NV_PRISCV_RISCV_TRACE_WTIDX);
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widx = DRF_VAL(_PRISCV_RISCV, _TRACE_WTIDX, _WTIDX, widx);
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ridx = flcnRiscvRegRead_HAL(device, pFlcn, NV_PRISCV_RISCV_TRACE_RDIDX);
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bufferSize = DRF_VAL(_PRISCV_RISCV, _TRACE_RDIDX, _MAXIDX, ridx);
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ridx = DRF_VAL(_PRISCV_RISCV, _TRACE_RDIDX, _RDIDX, ridx);
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count = widx > ridx ? widx - ridx : bufferSize + widx - ridx;
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//
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// Trace buffer is full when write idx == read idx and full is set,
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// otherwise it is empty.
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//
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if (widx == ridx && !full)
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count = 0;
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if (count)
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{
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NvU32 entry;
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NVSWITCH_PRINT(device, INFO, "%s: Tracebuffer has %d entries. Starting with latest.\n", __FUNCTION__, count);
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ridx = widx;
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for (entry = 0; entry < count; ++entry)
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{
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NvU64 pc;
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ridx = ridx > 0 ? ridx - 1 : bufferSize - 1;
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flcnRiscvRegWrite_HAL(device, pFlcn, NV_PRISCV_RISCV_TRACE_RDIDX, DRF_NUM(_PRISCV_RISCV, _TRACE_RDIDX, _RDIDX, ridx));
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pc = flcnRiscvRegRead_HAL(device, pFlcn, NV_PRISCV_RISCV_TRACEPC_HI);
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pc = (pc << 32) | flcnRiscvRegRead_HAL(device, pFlcn, NV_PRISCV_RISCV_TRACEPC_LO);
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NVSWITCH_PRINT(device, INFO, "%s: TRACE[%d] = 0x%16llx\n", __FUNCTION__, entry, pc);
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}
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}
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else
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{
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NVSWITCH_PRINT(device, INFO, "%s: Trace buffer is empty.\n", __FUNCTION__);
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}
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// reset trace buffer
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flcnRiscvRegWrite_HAL(device, pFlcn, NV_PRISCV_RISCV_TRACE_RDIDX, 0);
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flcnRiscvRegWrite_HAL(device, pFlcn, NV_PRISCV_RISCV_TRACE_WTIDX, 0);
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// Clear full and empty bits
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ctl = FLD_SET_DRF_NUM(_PRISCV_RISCV, _TRACECTL, _FULL, 0, ctl);
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ctl = FLD_SET_DRF_NUM(_PRISCV_RISCV, _TRACECTL, _EMPTY, 0, ctl);
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flcnRiscvRegWrite_HAL(device, pFlcn, NV_PRISCV_RISCV_TRACECTL, ctl);
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}
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/**
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* @brief set hal function pointers for functions defined in
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* LS10 (i.e. this file)
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*
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* this function has to be at the end of the file so that all the
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* other functions are already defined.
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*
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* @param[in] pFlcn The flcn for which to set hals
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*/
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void
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flcnSetupHal_LS10
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(
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PFLCN pFlcn
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)
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{
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flcn_hal *pHal = pFlcn->pHal;
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flcnSetupHal_LR10(pFlcn);
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pHal->riscvRegRead = _flcnRiscvRegRead_LS10;
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pHal->riscvRegWrite = _flcnRiscvRegWrite_LS10;
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pHal->dmemTransfer = _flcnDmemTransfer_LS10;
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pHal->setDmemAddr = _flcnSetDmemAddr_LS10;
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pHal->imemCopyTo = _flcnImemCopyTo_LS10;
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pHal->setImemAddr = _flcnSetImemAddr_LS10;
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pHal->dmemSize = _flcnDmemSize_LS10;
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pHal->dbgInfoCaptureRiscvPcTrace = _flcnDbgInfoCaptureRiscvPcTrace_LS10;
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}
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