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This commit is contained in:
Andy Ritger
2022-11-10 08:39:33 -08:00
parent 7c345b838b
commit 758b4ee818
1323 changed files with 262135 additions and 60754 deletions
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2
src/common/sdk/nvidia/inc/Nvcm.h
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@@ -45,14 +45,12 @@
extern "C" {
#endif
#if !defined(XAPIGEN) /* avoid duplicate generated xapi fns */
#include "nvgputypes.h"
#ifndef _H2INC
#include "rmcd.h"
#endif
#include "nverror.h"
#endif /* !XAPIGEN */
#define NV_ROBUST_CHANNEL_ALLOCFAIL_CLIENT 0x00000001
#define NV_ROBUST_CHANNEL_ALLOCFAIL_DEVICE 0x00000002

319
src/common/sdk/nvidia/inc/alloc/alloc_channel.h Normal file
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@@ -0,0 +1,319 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: alloc/alloc_channel.finn
//
#include "nvlimits.h"
#include "nvcfg_sdk.h"
typedef struct NV_MEMORY_DESC_PARAMS {
NV_DECLARE_ALIGNED(NvU64 base, 8);
NV_DECLARE_ALIGNED(NvU64 size, 8);
NvU32 addressSpace;
NvU32 cacheAttrib;
} NV_MEMORY_DESC_PARAMS;
/*
* NV_CHANNEL_ALLOC_PARAMS.flags values.
*
* These flags may apply to all channel types: PIO, DMA, and GPFIFO.
* They are also designed so that zero is always the correct default.
*
* NVOS04_FLAGS_CHANNEL_TYPE:
* This flag specifies the type of channel to allocate. Legal values
* for this flag include:
*
* NVOS04_FLAGS_CHANNEL_TYPE_PHYSICAL:
* This flag specifies that a physical channel is to be allocated.
*
* NVOS04_FLAGS_CHANNEL_TYPE_VIRTUAL:
* OBSOLETE - NOT SUPPORTED
*
* NVOS04_FLAGS_CHANNEL_TYPE_PHYSICAL_FOR_VIRTUAL:
* OBSOLETE - NOT SUPPORTED
*/
/* valid NVOS04_FLAGS_CHANNEL_TYPE values */
#define NVOS04_FLAGS_CHANNEL_TYPE 1:0
#define NVOS04_FLAGS_CHANNEL_TYPE_PHYSICAL 0x00000000
#define NVOS04_FLAGS_CHANNEL_TYPE_VIRTUAL 0x00000001 // OBSOLETE
#define NVOS04_FLAGS_CHANNEL_TYPE_PHYSICAL_FOR_VIRTUAL 0x00000002 // OBSOLETE
/*
* NVOS04_FLAGS_VPR:
* This flag specifies if channel is intended for work with
* Video Protected Regions (VPR)
*
* NVOS04_FLAGS_VPR_TRUE:
* The channel will only write to protected memory regions.
*
* NVOS04_FLAGS_VPR_FALSE:
* The channel will never read from protected memory regions.
*/
#define NVOS04_FLAGS_VPR 2:2
#define NVOS04_FLAGS_VPR_FALSE 0x00000000
#define NVOS04_FLAGS_VPR_TRUE 0x00000001
/*
* NVOS04_FLAGS_CHANNEL_SKIP_MAP_REFCOUNTING:
* This flag specifies if the channel can skip refcounting of potentially
* accessed mappings on job kickoff. This flag is only meaningful for
* kernel drivers which perform refcounting of memory mappings.
*
* NVOS04_FLAGS_CHANNEL_SKIP_MAP_REFCOUNTING_FALSE:
* The channel cannot not skip refcounting of memory mappings
*
* NVOS04_FLAGS_CHANNEL_SKIP_MAP_REFCOUNTING_TRUE:
* The channel can skip refcounting of memory mappings
*/
#define NVOS04_FLAGS_CHANNEL_SKIP_MAP_REFCOUNTING 3:3
#define NVOS04_FLAGS_CHANNEL_SKIP_MAP_REFCOUNTING_FALSE 0x00000000
#define NVOS04_FLAGS_CHANNEL_SKIP_MAP_REFCOUNTING_TRUE 0x00000001
/*
* NVOS04_FLAGS_GROUP_CHANNEL_RUNQUEUE:
* This flag specifies which "runqueue" the allocated channel will be
* executed on in a TSG. Channels on different runqueues within a TSG
* may be able to feed methods into the engine simultaneously.
* Non-default values are only supported on GP10x and later and only for
* channels within a TSG.
*/
#define NVOS04_FLAGS_GROUP_CHANNEL_RUNQUEUE 4:4
#define NVOS04_FLAGS_GROUP_CHANNEL_RUNQUEUE_DEFAULT 0x00000000
#define NVOS04_FLAGS_GROUP_CHANNEL_RUNQUEUE_ONE 0x00000001
/*
* NVOS04_FLAGS_PRIVILEGED_CHANNEL:
* This flag tells RM whether to give the channel admin privilege. This
* flag will only take effect if the client is GSP-vGPU plugin. It is
* needed so that guest can update page tables in physical mode and do
* scrubbing.
*/
#define NVOS04_FLAGS_PRIVILEGED_CHANNEL 5:5
#define NVOS04_FLAGS_PRIVILEGED_CHANNEL_FALSE 0x00000000
#define NVOS04_FLAGS_PRIVILEGED_CHANNEL_TRUE 0x00000001
/*
* NVOS04_FLAGS_DELAY_CHANNEL_SCHEDULING:
* This flags tells RM not to schedule a newly created channel within a
* channel group immediately even if channel group is currently scheduled.
* Channel will not be scheduled until NVA06F_CTRL_GPFIFO_SCHEDULE is
* invoked. This is used eg. for CUDA which needs to do additional
* initialization before starting up a channel.
* Default is FALSE.
*/
#define NVOS04_FLAGS_DELAY_CHANNEL_SCHEDULING 6:6
#define NVOS04_FLAGS_DELAY_CHANNEL_SCHEDULING_FALSE 0x00000000
#define NVOS04_FLAGS_DELAY_CHANNEL_SCHEDULING_TRUE 0x00000001
/*
* NVOS04_FLAGS_DENY_PHYSICAL_MODE_CE:
* This flag specifies whether or not to deny access to the physical
* mode of CopyEngine regardless of whether or not the client handle
* is admin. If set to true, this channel allocation will always result
* in an unprivileged channel. If set to false, the privilege of the channel
* will depend on the privilege level of the client handle.
* This is primarily meant for vGPU since all client handles
* granted to guests are admin.
*/
#define NVOS04_FLAGS_CHANNEL_DENY_PHYSICAL_MODE_CE 7:7
#define NVOS04_FLAGS_CHANNEL_DENY_PHYSICAL_MODE_CE_FALSE 0x00000000
#define NVOS04_FLAGS_CHANNEL_DENY_PHYSICAL_MODE_CE_TRUE 0x00000001
/*
* NVOS04_FLAGS_CHANNEL_USERD_INDEX_VALUE
*
* This flag specifies the channel offset in terms of within a page of
* USERD. For example, value 3 means the 4th channel within a USERD page.
* Given the USERD size is 512B, we will have 8 channels total, so 3 bits
* are reserved.
*
* When _USERD_INDEX_FIXED_TRUE is set but INDEX_PAGE_FIXED_FALSE is set,
* it will ask for a new USERD page.
*
*/
#define NVOS04_FLAGS_CHANNEL_USERD_INDEX_VALUE 10:8
#define NVOS04_FLAGS_CHANNEL_USERD_INDEX_FIXED 11:11
#define NVOS04_FLAGS_CHANNEL_USERD_INDEX_FIXED_FALSE 0x00000000
#define NVOS04_FLAGS_CHANNEL_USERD_INDEX_FIXED_TRUE 0x00000001
/*
* NVOS04_FLAGS_CHANNEL_USERD_INDEX_PAGE_VALUE
*
* This flag specifies the channel offset in terms of USERD page. When
* this PAGE_FIXED_TRUE is set, the INDEX_FIXED_FALSE bit should also
* be set, otherwise INVALID_STATE will be returned.
*
* And the field _USERD_INDEX_VALUE will be used to request the specific
* offset within a USERD page.
*/
#define NVOS04_FLAGS_CHANNEL_USERD_INDEX_PAGE_VALUE 20:12
#define NVOS04_FLAGS_CHANNEL_USERD_INDEX_PAGE_FIXED 21:21
#define NVOS04_FLAGS_CHANNEL_USERD_INDEX_PAGE_FIXED_FALSE 0x00000000
#define NVOS04_FLAGS_CHANNEL_USERD_INDEX_PAGE_FIXED_TRUE 0x00000001
/*
* NVOS04_FLAGS_DENY_AUTH_LEVEL_PRIV
* This flag specifies whether or not to deny access to the privileged
* host methods TLB_INVALIDATE and ACCESS_COUNTER_CLR
*/
#define NVOS04_FLAGS_CHANNEL_DENY_AUTH_LEVEL_PRIV 22:22
#define NVOS04_FLAGS_CHANNEL_DENY_AUTH_LEVEL_PRIV_FALSE 0x00000000
#define NVOS04_FLAGS_CHANNEL_DENY_AUTH_LEVEL_PRIV_TRUE 0x00000001
/*
* NVOS04_FLAGS_CHANNEL_SKIP_SCRUBBER
*
* This flag specifies scrubbing should be skipped for any internal
* allocations made for this channel from PMA using ctx buf pools.
* Only kernel clients are allowed to use this setting.
*/
#define NVOS04_FLAGS_CHANNEL_SKIP_SCRUBBER 23:23
#define NVOS04_FLAGS_CHANNEL_SKIP_SCRUBBER_FALSE 0x00000000
#define NVOS04_FLAGS_CHANNEL_SKIP_SCRUBBER_TRUE 0x00000001
/*
* NVOS04_FLAGS_CHANNEL_CLIENT_MAP_FIFO
*
* This flag specifies that the client is expected to map USERD themselves
* and RM need not do so.
*/
#define NVOS04_FLAGS_CHANNEL_CLIENT_MAP_FIFO 24:24
#define NVOS04_FLAGS_CHANNEL_CLIENT_MAP_FIFO_FALSE 0x00000000
#define NVOS04_FLAGS_CHANNEL_CLIENT_MAP_FIFO_TRUE 0x00000001
/*
* NVOS04_FLAGS_SET_EVICT_LAST_CE_PREFETCH_CHANNEL
*/
#define NVOS04_FLAGS_SET_EVICT_LAST_CE_PREFETCH_CHANNEL 25:25
#define NVOS04_FLAGS_SET_EVICT_LAST_CE_PREFETCH_CHANNEL_FALSE 0x00000000
#define NVOS04_FLAGS_SET_EVICT_LAST_CE_PREFETCH_CHANNEL_TRUE 0x00000001
/*
* NVOS04_FLAGS_CHANNEL_VGPU_PLUGIN_CONTEXT
*
* This flag specifies whether the channel calling context is from CPU
* VGPU plugin.
*/
#define NVOS04_FLAGS_CHANNEL_VGPU_PLUGIN_CONTEXT 26:26
#define NVOS04_FLAGS_CHANNEL_VGPU_PLUGIN_CONTEXT_FALSE 0x00000000
#define NVOS04_FLAGS_CHANNEL_VGPU_PLUGIN_CONTEXT_TRUE 0x00000001
/*
* NVOS04_FLAGS_CHANNEL_PBDMA_ACQUIRE_TIMEOUT
*
* This flag specifies the channel PBDMA ACQUIRE timeout option.
* _FALSE to disable it, _TRUE to enable it.
* When this flag is enabled, if a host semaphore acquire does not
* complete in about 2 sec, it will time out and trigger a RC error.
*/
#define NVOS04_FLAGS_CHANNEL_PBDMA_ACQUIRE_TIMEOUT 27:27
#define NVOS04_FLAGS_CHANNEL_PBDMA_ACQUIRE_TIMEOUT_FALSE 0x00000000
#define NVOS04_FLAGS_CHANNEL_PBDMA_ACQUIRE_TIMEOUT_TRUE 0x00000001
/*
* NVOS04_FLAGS_GROUP_CHANNEL_THREAD:
* This flags specifies the thread id in which an allocated channel
* will be executed in a TSG. The relationship between the thread id
* in A TSG and respective definitions are implementation specific.
* Also, not all classes will be supported at thread > 0.
* This field cannot be used on non-TSG channels and must be set to
* the default value (0) in that case. If thread > 0 on a non-TSG
* channel, the allocation will fail
*/
#define NVOS04_FLAGS_GROUP_CHANNEL_THREAD 29:28
#define NVOS04_FLAGS_GROUP_CHANNEL_THREAD_DEFAULT 0x00000000
#define NVOS04_FLAGS_GROUP_CHANNEL_THREAD_ONE 0x00000001
#define NVOS04_FLAGS_GROUP_CHANNEL_THREAD_TWO 0x00000002
#define NVOS04_FLAGS_MAP_CHANNEL 30:30
#define NVOS04_FLAGS_MAP_CHANNEL_FALSE 0x00000000
#define NVOS04_FLAGS_MAP_CHANNEL_TRUE 0x00000001
#define NVOS04_FLAGS_SKIP_CTXBUFFER_ALLOC 31:31
#define NVOS04_FLAGS_SKIP_CTXBUFFER_ALLOC_FALSE 0x00000000
#define NVOS04_FLAGS_SKIP_CTXBUFFER_ALLOC_TRUE 0x00000001
#define NV_CHANNEL_ALLOC_PARAMS_MESSAGE_ID (0x906fU)
typedef struct NV_CHANNEL_ALLOC_PARAMS {
NvHandle hObjectError; // error context DMA
NvHandle hObjectBuffer; // no longer used
NV_DECLARE_ALIGNED(NvU64 gpFifoOffset, 8); // offset to beginning of GP FIFO
NvU32 gpFifoEntries; // number of GP FIFO entries
NvU32 flags;
NvHandle hContextShare; // context share handle
NvHandle hVASpace; // VASpace for the channel
// handle to UserD memory object for channel, ignored if hUserdMemory[0]=0
NvHandle hUserdMemory[NV_MAX_SUBDEVICES];
// offset to beginning of UserD within hUserdMemory[x]
NV_DECLARE_ALIGNED(NvU64 userdOffset[NV_MAX_SUBDEVICES], 8);
// engine type(NV2080_ENGINE_TYPE_*) with which this channel is associated
NvU32 engineType;
// Channel identifier that is unique for the duration of a RM session
NvU32 cid;
// One-hot encoded bitmask to match SET_SUBDEVICE_MASK methods
NvU32 subDeviceId;
NvHandle hObjectEccError; // ECC error context DMA
NV_DECLARE_ALIGNED(NV_MEMORY_DESC_PARAMS instanceMem, 8);
NV_DECLARE_ALIGNED(NV_MEMORY_DESC_PARAMS userdMem, 8);
NV_DECLARE_ALIGNED(NV_MEMORY_DESC_PARAMS ramfcMem, 8);
NV_DECLARE_ALIGNED(NV_MEMORY_DESC_PARAMS mthdbufMem, 8);
NvHandle hPhysChannelGroup; // reserved
NvU32 internalFlags; // reserved
NV_DECLARE_ALIGNED(NV_MEMORY_DESC_PARAMS errorNotifierMem, 8); // reserved
NV_DECLARE_ALIGNED(NV_MEMORY_DESC_PARAMS eccErrorNotifierMem, 8); // reserved
NvU32 ProcessID; // reserved
NvU32 SubProcessID; // reserved
} NV_CHANNEL_ALLOC_PARAMS;
typedef NV_CHANNEL_ALLOC_PARAMS NV_CHANNELGPFIFO_ALLOCATION_PARAMETERS;

4
src/common/sdk/nvidia/inc/class/cl0000.h
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@@ -34,12 +34,12 @@
#include "cl0000_notification.h"
/* object NV01_NULL_OBJECT */
#define NV01_NULL_OBJECT (0x00000000)
#define NV01_NULL_OBJECT (0x0) /* finn: Evaluated from "NV0000_ALLOC_PARAMETERS_MESSAGE_ID" */
/* obsolete alises */
#define NV1_NULL_OBJECT NV01_NULL_OBJECT
#define NV01_ROOT (0x00000000)
#define NV01_ROOT (0x0U) /* finn: Evaluated from "NV0000_ALLOC_PARAMETERS_MESSAGE_ID" */
/* NvAlloc parameteters */
#define NV0000_ALLOC_PARAMETERS_MESSAGE_ID (0x0000U)

2
src/common/sdk/nvidia/inc/class/cl0005.h
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@@ -32,7 +32,7 @@
#include "cl0005_notification.h"
#define NV01_EVENT (0x00000005)
#define NV01_EVENT (0x5U) /* finn: Evaluated from "NV0005_ALLOC_PARAMETERS_MESSAGE_ID" */
/* NvRmAlloc() parameters */
#define NV0005_ALLOC_PARAMETERS_MESSAGE_ID (0x0005U)

2
src/common/sdk/nvidia/inc/class/cl000f.h
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@@ -30,7 +30,7 @@
// Source file: class/cl000f.finn
//
#define FABRIC_MANAGER_SESSION (0x0000000F)
#define FABRIC_MANAGER_SESSION (0xfU) /* finn: Evaluated from "NV000F_ALLOCATION_PARAMETERS_MESSAGE_ID" */
#define NV000F_NOTIFIERS_FABRIC_EVENT (0)

4
src/common/sdk/nvidia/inc/class/cl0060.h
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@@ -30,10 +30,8 @@
// Source file: class/cl0060.finn
//
#define NV0060_SYNC_GPU_BOOST (0x00000060)
#define NV0060_SYNC_GPU_BOOST (0x60U) /* finn: Evaluated from "NV0060_ALLOC_PARAMETERS_MESSAGE_ID" */
/*!
*/
#define NV0060_ALLOC_PARAMETERS_MESSAGE_ID (0x0060U)
typedef struct NV0060_ALLOC_PARAMETERS {

4
src/common/sdk/nvidia/inc/class/cl0070.h
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@@ -29,8 +29,8 @@
// Source file: class/cl0070.finn
//
#define NV01_MEMORY_VIRTUAL (0x00000070)
#define NV01_MEMORY_SYSTEM_DYNAMIC (0x00000070)
#define NV01_MEMORY_VIRTUAL (0x70U) /* finn: Evaluated from "NV_MEMORY_VIRTUAL_ALLOCATION_PARAMS_MESSAGE_ID" */
#define NV01_MEMORY_SYSTEM_DYNAMIC (0x70U) /* finn: Evaluated from "NV_MEMORY_VIRTUAL_ALLOCATION_PARAMS_MESSAGE_ID" */
/*
* NV_MEMORY_VIRTUAL_ALLOCATION_PARAMS

2
src/common/sdk/nvidia/inc/class/cl0080.h
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@@ -33,7 +33,7 @@
#include "nvlimits.h"
#include "cl0080_notification.h"
#define NV01_DEVICE_0 (0x00000080)
#define NV01_DEVICE_0 (0x80U) /* finn: Evaluated from "NV0080_ALLOC_PARAMETERS_MESSAGE_ID" */
/* NvAlloc parameteters */
#define NV0080_MAX_DEVICES NV_MAX_DEVICES

32
src/common/sdk/nvidia/inc/class/cl0092.h
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@@ -1,5 +1,5 @@
/*
* Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2020-2022, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -20,10 +20,16 @@
* DEALINGS IN THE SOFTWARE.
*/
#ifndef SDK_CL0092_H
#define SDK_CL0092_H
#pragma once
#include "nvtypes.h"
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: class/cl0092.finn
//
#include "class/cl0092_callback.h"
/*
* This RgLineCallback class allows RM clients to register/unregister the RG line callback functions.
@@ -50,19 +56,17 @@
* Pointer to the ctrl call param struct.
*/
#define NV0092_RG_LINE_CALLBACK 0x0092
#define NV0092_RG_LINE_CALLBACK (0x92U) /* finn: Evaluated from "NV0092_RG_LINE_CALLBACK_ALLOCATION_PARAMETERS_MESSAGE_ID" */
typedef void (*NV0092_REGISTER_RG_LINE_CALLBACK_FN)(NvU32 rgIntrLine, void *param1, NvBool bIsIrqlIsr);
#define NV0092_RG_LINE_CALLBACK_ALLOCATION_PARAMETERS_MESSAGE_ID (0x0092U)
typedef struct
{
NvU32 subDeviceInstance;
NvU32 head;
NvU32 rgLineNum;
typedef struct NV0092_RG_LINE_CALLBACK_ALLOCATION_PARAMETERS {
NvU32 subDeviceInstance;
NvU32 head;
NvU32 rgLineNum;
NV0092_REGISTER_RG_LINE_CALLBACK_FN pCallbkFn;
NV_DECLARE_ALIGNED(NvP64 pCallbkFn, 8); /* A function pointer of NV0092_REGISTER_RG_LINE_CALLBACK_FN */
void *pCallbkParams;
NV_DECLARE_ALIGNED(NvP64 pCallbkParams, 8); /* The param1 in NV0092_REGISTER_RG_LINE_CALLBACK_FN */
} NV0092_RG_LINE_CALLBACK_ALLOCATION_PARAMETERS;
#endif // SDK_CL0092_H

20
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080common.h → src/common/sdk/nvidia/inc/class/cl0092_callback.h
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@@ -1,6 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2001-2004 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
* Copyright (c) 2022, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -9,26 +8,21 @@
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
#ifndef SDK_CL0092_CALLBACK_H
#define SDK_CL0092_CALLBACK_H
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl2080/ctrl2080common.finn
//
typedef void (*NV0092_REGISTER_RG_LINE_CALLBACK_FN)(NvU32 rgIntrLine, NvP64 param1, NvBool bIsIrqlIsr);
#define NV2080_CTRL_CMD_MAX_HEADS 2
#endif // SDK_CL0092_CALLBACK_H

72
src/common/sdk/nvidia/inc/class/cl00c1.h
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@@ -1,5 +1,5 @@
/*
* Copyright (c) 2018-2018, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2018-2022, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -20,50 +20,46 @@
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _cl00c1_h_
#define _cl00c1_h_
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: class/cl00c1.finn
//
#include "nvtypes.h"
#include "nvlimits.h"
#define NV_FB_SEGMENT (0x000000C1)
#define NV_FB_SEGMENT (0xc1U) /* finn: Evaluated from "NV_FB_SEGMENT_ALLOCATION_PARAMS_MESSAGE_ID" */
/*
* NV_FB_SEGMENT_ALLOCATION_PARAMS - Allocation params to create FB segment through
* NvRmAlloc.
*/
typedef struct
{
NvHandle hCtxDma;
NvU32 subDeviceIDMask NV_ALIGN_BYTES(8);
NvU64 dmaOffset NV_ALIGN_BYTES(8);
NvU64 VidOffset NV_ALIGN_BYTES(8);
NvU64 Offset NV_ALIGN_BYTES(8); // To be deprecated
NvU64 pOffset[NV_MAX_SUBDEVICES] NV_ALIGN_BYTES(8);
NvU64 Length NV_ALIGN_BYTES(8);
NvU64 ValidLength NV_ALIGN_BYTES(8);
NvP64 pPageArray NV_ALIGN_BYTES(8);
NvU32 startPageIndex;
NvHandle AllocHintHandle;
NvU32 Flags;
NvHandle hMemory; // Not used in NvRmAlloc path; only used in CTRL path
NvHandle hClient; // Not used in NvRmAlloc path; only used in CTRL path
NvHandle hDevice; // Not used in NvRmAlloc path; only used in CTRL path
NvP64 pCpuAddress NV_ALIGN_BYTES(8); // To be deprecated
NvP64 ppCpuAddress[NV_MAX_SUBDEVICES] NV_ALIGN_BYTES(8);
NvU64 GpuAddress NV_ALIGN_BYTES(8); // To be deprecated
NvU64 pGpuAddress[NV_MAX_SUBDEVICES] NV_ALIGN_BYTES(8);
NvHandle hAllocHintClient;
NvU32 kind;
NvU32 compTag;
#define NV_FB_SEGMENT_ALLOCATION_PARAMS_MESSAGE_ID (0x00C1U)
typedef struct NV_FB_SEGMENT_ALLOCATION_PARAMS {
NvHandle hCtxDma; // unused
NvU32 subDeviceIDMask;
NV_DECLARE_ALIGNED(NvU64 dmaOffset, 8); // unused
NV_DECLARE_ALIGNED(NvU64 VidOffset, 8);
NV_DECLARE_ALIGNED(NvU64 Offset, 8); // To be deprecated
NV_DECLARE_ALIGNED(NvU64 pOffset[NV_MAX_SUBDEVICES], 8);
NV_DECLARE_ALIGNED(NvU64 Length, 8);
NV_DECLARE_ALIGNED(NvU64 ValidLength, 8);
NV_DECLARE_ALIGNED(NvP64 pPageArray, 8);
NvU32 startPageIndex;
NvHandle AllocHintHandle;
NvU32 Flags;
NvHandle hMemory; // Not used in NvRmAlloc path; only used in CTRL path
NvHandle hClient; // Not used in NvRmAlloc path; only used in CTRL path
NvHandle hDevice; // Not used in NvRmAlloc path; only used in CTRL path
NV_DECLARE_ALIGNED(NvP64 pCpuAddress, 8); // To be deprecated
NV_DECLARE_ALIGNED(NvP64 ppCpuAddress[NV_MAX_SUBDEVICES], 8);
NV_DECLARE_ALIGNED(NvU64 GpuAddress, 8); // To be deprecated
NV_DECLARE_ALIGNED(NvU64 pGpuAddress[NV_MAX_SUBDEVICES], 8);
NvHandle hAllocHintClient;
NvU32 kind;
NvU32 compTag;
} NV_FB_SEGMENT_ALLOCATION_PARAMS;
#ifdef __cplusplus
}; /* extern "C" */
#endif
#endif /* _cl00c1_h_ */

2
src/common/sdk/nvidia/inc/class/cl00c2.h
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@@ -29,7 +29,7 @@
// Source file: class/cl00c2.finn
//
#define NV01_MEMORY_LOCAL_PHYSICAL (0x000000c2)
#define NV01_MEMORY_LOCAL_PHYSICAL (0xc2U) /* finn: Evaluated from "NV_PHYSICAL_MEMORY_ALLOCATION_PARAMS_MESSAGE_ID" */
#define NV_PHYSICAL_MEMORY_ALLOCATION_PARAMS_MESSAGE_ID (0x00c2U)

2
src/common/sdk/nvidia/inc/class/cl00c3.h
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@@ -29,7 +29,7 @@
// Source file: class/cl00c3.finn
//
#define NV01_MEMORY_SYNCPOINT 0x00C3
#define NV01_MEMORY_SYNCPOINT (0xc3U) /* finn: Evaluated from "NV_MEMORY_SYNCPOINT_ALLOCATION_PARAMS_MESSAGE_ID" */
/*
* NV_MEMORY_SYNCPOINT_ALLOCATION_PARAMS - Allocation params to create syncpoint

2
src/common/sdk/nvidia/inc/class/cl00db.h
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@@ -31,7 +31,7 @@
// Source file: class/cl00db.finn
//
#define NV40_DEBUG_BUFFER (0x000000db)
#define NV40_DEBUG_BUFFER (0xdbU) /* finn: Evaluated from "NV00DB_ALLOCATION_PARAMETERS_MESSAGE_ID" */
/* NvRmAlloc() parameters */
#define NV00DB_ALLOCATION_PARAMETERS_MESSAGE_ID (0x00dbU)

50
src/common/sdk/nvidia/inc/class/cl00de.h Normal file
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@@ -0,0 +1,50 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _cl00de_h_
#define _cl00de_h_
#ifdef __cplusplus
extern "C" {
#endif
#define RM_USER_SHARED_DATA (0x000000de)
typedef struct NV00DE_SHARED_DATA {
volatile NvU32 seq;
NvU32 bar1Size;
NvU32 bar1AvailSize;
// New data members always add to bottom
} NV00DE_SHARED_DATA;
typedef struct NV00DE_ALLOC_PARAMETERS {
// initialize to 0
NvU32 reserved;
} NV00DE_ALLOC_PARAMETERS;
#ifdef __cplusplus
}; /* extern "C" */
#endif
#endif /* _cl00de_h_ */

2
src/common/sdk/nvidia/inc/class/cl00f3.h
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@@ -40,7 +40,7 @@
* other parameters are passed as Nv01MemoryFla structure.
*/
#define NV01_MEMORY_FLA (0x000000f3)
#define NV01_MEMORY_FLA (0xf3U) /* finn: Evaluated from "NV_FLA_MEMORY_ALLOCATION_PARAMS_MESSAGE_ID" */
/*
* Structure of NV_FLA_MEMORY_ALLOCATION_PARAMS

14
src/common/sdk/nvidia/inc/class/cl00f8.h
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@@ -36,7 +36,7 @@
* Class definition for allocating a contiguous or discontiguous FLA.
*/
#define NV_MEMORY_FABRIC (0x000000f8)
#define NV_MEMORY_FABRIC (0xf8U) /* finn: Evaluated from "NV00F8_ALLOCATION_PARAMETERS_MESSAGE_ID" */
/*
* alignment [IN]
@@ -77,11 +77,13 @@
* Must be physical memory page size aligned.
*
* map.hVidMem [IN]
* Handle to the physical video memory. Must be passed when the sticky flag is set so that the
* FLA -> PA mapping can happen during object creation.
* Phys memory with 2MB pages is supported.
* Phys memory handle can be NV01_NULL_OBJECT if FLEXIBLE_FLA flag is passed.
* hVidMem should belong the same device and client which is allocating FLA.
* - Handle to the physical memory.
* - Must be passed so that the FLA -> GPA mapping can happen during object creation.
* - For sticky allocations, physical memory being mapped should be large enough
* (accounting map.offset) to cover the whole fabric object allocation size.
* - For flexible allocations, physical memory handle should be zero.
* - Phys memory with 2MB and 512MB pages is supported.
* - hVidMem should belong the same device and client which is allocating FLA.
*
* map.flags [IN]
* Reserved for future use.

73
src/common/sdk/nvidia/inc/class/cl00fd.h Normal file
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@@ -0,0 +1,73 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2010-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
/*
* Class definition for allocating a contiguous or discontiguous Multicast FLA.
*/
#pragma once
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: class/cl00fd.finn
//
#define NV_MEMORY_MULTICAST_FABRIC (0xfdU) /* finn: Evaluated from "NV00FD_ALLOCATION_PARAMETERS_MESSAGE_ID" */
/*
* alignment [IN]
* Alignment for the allocation.
* Should be at least the requested page size.
*
* allocSize [IN]
* Size of the Multicast FLA VA.
*
* pageSize [IN]
* Requested page size. Can be any of the NV_MEMORY_MULTICAST_FABRIC_PAGE_SIZE_*
*
* allocFlags [IN]
* Reserved for future use
* Clients should pass 0 as of now.
*
* numGpus [IN]
* Number of unique GPUs to be attached.
*
* pOsEvent [IN]
* Optional OS event handle created with NvRmAllocOsEvent().
*/
#define NV_MEMORY_MULTICAST_FABRIC_PAGE_SIZE_512M 0x20000000
#define NV00FD_ALLOCATION_PARAMETERS_MESSAGE_ID (0x00fdU)
typedef struct NV00FD_ALLOCATION_PARAMETERS {
NV_DECLARE_ALIGNED(NvU64 alignment, 8);
NV_DECLARE_ALIGNED(NvU64 allocSize, 8);
NvU32 pageSize;
NvU32 allocFlags;
NvU32 numGpus;
NV_DECLARE_ALIGNED(NvP64 pOsEvent, 8);
} NV00FD_ALLOCATION_PARAMETERS;

46
src/common/sdk/nvidia/inc/class/cl00fe.h Normal file
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@@ -0,0 +1,46 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: class/cl00fe.finn
//
#define NV_MEMORY_MAPPER (0xfeU) /* finn: Evaluated from "NV_MEMORY_MAPPER_ALLOCATION_PARAMS_MESSAGE_ID" */
/*
* NV_MEMORY_MAPPER_ALLOCATION_PARAMS
*
* Allocation params for NV_MEMORY_MAPPER.
* This class provides paging operations channel interface to userspace clients.
*/
#define NV_MEMORY_MAPPER_ALLOCATION_PARAMS_MESSAGE_ID (0x00FEU)
typedef struct NV_MEMORY_MAPPER_ALLOCATION_PARAMS {
NvBool unused;
} NV_MEMORY_MAPPER_ALLOCATION_PARAMS;

478
src/common/sdk/nvidia/inc/class/cl2080.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2002-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2002-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -21,472 +21,26 @@
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _cl2080_h_
#define _cl2080_h_
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: class/cl2080.finn
//
#include "nvtypes.h"
#include "nvlimits.h"
#include "cl2080_notification.h"
#define NV20_SUBDEVICE_0 (0x00002080)
/* event values */
#define NV2080_NOTIFIERS_SW (0)
#define NV2080_NOTIFIERS_HOTPLUG (1)
#define NV2080_NOTIFIERS_POWER_CONNECTOR (2)
#define NV2080_NOTIFIERS_THERMAL_SW (3)
#define NV2080_NOTIFIERS_THERMAL_HW (4)
#define NV2080_NOTIFIERS_FULL_SCREEN_CHANGE (5)
#define NV2080_NOTIFIERS_EVENTBUFFER (6)
#define NV2080_NOTIFIERS_DP_IRQ (7)
#define NV2080_NOTIFIERS_GR_DEBUG_INTR (8)
#define NV2080_NOTIFIERS_PMU_EVENT (9)
#define NV2080_NOTIFIERS_PMU_COMMAND (10)
#define NV2080_NOTIFIERS_TIMER (11)
#define NV2080_NOTIFIERS_GRAPHICS (12)
#define NV2080_NOTIFIERS_PPP (13)
#define NV2080_NOTIFIERS_VLD (14) // also known as BSP
#define NV2080_NOTIFIERS_NVDEC0 NV2080_NOTIFIERS_VLD
#define NV2080_NOTIFIERS_NVDEC1 (15)
#define NV2080_NOTIFIERS_NVDEC2 (16)
#define NV2080_NOTIFIERS_NVDEC3 (17)
#define NV2080_NOTIFIERS_NVDEC4 (18)
#define NV2080_NOTIFIERS_NVDEC5 (19)
#define NV2080_NOTIFIERS_NVDEC6 (20)
#define NV2080_NOTIFIERS_NVDEC7 (21)
#define NV2080_NOTIFIERS_PDEC (22) // also known as VP
#define NV2080_NOTIFIERS_CE0 (23)
#define NV2080_NOTIFIERS_CE1 (24)
#define NV2080_NOTIFIERS_CE2 (25)
#define NV2080_NOTIFIERS_CE3 (26)
#define NV2080_NOTIFIERS_CE4 (27)
#define NV2080_NOTIFIERS_CE5 (28)
#define NV2080_NOTIFIERS_CE6 (29)
#define NV2080_NOTIFIERS_CE7 (30)
#define NV2080_NOTIFIERS_CE8 (31)
#define NV2080_NOTIFIERS_CE9 (32)
#define NV2080_NOTIFIERS_PSTATE_CHANGE (33)
#define NV2080_NOTIFIERS_HDCP_STATUS_CHANGE (34)
#define NV2080_NOTIFIERS_FIFO_EVENT_MTHD (35)
#define NV2080_NOTIFIERS_PRIV_RING_HANG (36)
#define NV2080_NOTIFIERS_RC_ERROR (37)
#define NV2080_NOTIFIERS_MSENC (38)
#define NV2080_NOTIFIERS_NVENC0 NV2080_NOTIFIERS_MSENC
#define NV2080_NOTIFIERS_NVENC1 (39)
#define NV2080_NOTIFIERS_NVENC2 (40)
#define NV2080_NOTIFIERS_UNUSED_0 (41) // Unused
#define NV2080_NOTIFIERS_ACPI_NOTIFY (42)
#define NV2080_NOTIFIERS_COOLER_DIAG_ZONE (43)
#define NV2080_NOTIFIERS_THERMAL_DIAG_ZONE (44)
#define NV2080_NOTIFIERS_AUDIO_HDCP_REQUEST (45)
#define NV2080_NOTIFIERS_WORKLOAD_MODULATION_CHANGE (46)
#define NV2080_NOTIFIERS_GPIO_0_RISING_INTERRUPT (47)
#define NV2080_NOTIFIERS_GPIO_1_RISING_INTERRUPT (48)
#define NV2080_NOTIFIERS_GPIO_2_RISING_INTERRUPT (49)
#define NV2080_NOTIFIERS_GPIO_3_RISING_INTERRUPT (50)
#define NV2080_NOTIFIERS_GPIO_4_RISING_INTERRUPT (51)
#define NV2080_NOTIFIERS_GPIO_5_RISING_INTERRUPT (52)
#define NV2080_NOTIFIERS_GPIO_6_RISING_INTERRUPT (53)
#define NV2080_NOTIFIERS_GPIO_7_RISING_INTERRUPT (54)
#define NV2080_NOTIFIERS_GPIO_8_RISING_INTERRUPT (55)
#define NV2080_NOTIFIERS_GPIO_9_RISING_INTERRUPT (56)
#define NV2080_NOTIFIERS_GPIO_10_RISING_INTERRUPT (57)
#define NV2080_NOTIFIERS_GPIO_11_RISING_INTERRUPT (58)
#define NV2080_NOTIFIERS_GPIO_12_RISING_INTERRUPT (59)
#define NV2080_NOTIFIERS_GPIO_13_RISING_INTERRUPT (60)
#define NV2080_NOTIFIERS_GPIO_14_RISING_INTERRUPT (61)
#define NV2080_NOTIFIERS_GPIO_15_RISING_INTERRUPT (62)
#define NV2080_NOTIFIERS_GPIO_16_RISING_INTERRUPT (63)
#define NV2080_NOTIFIERS_GPIO_17_RISING_INTERRUPT (64)
#define NV2080_NOTIFIERS_GPIO_18_RISING_INTERRUPT (65)
#define NV2080_NOTIFIERS_GPIO_19_RISING_INTERRUPT (66)
#define NV2080_NOTIFIERS_GPIO_20_RISING_INTERRUPT (67)
#define NV2080_NOTIFIERS_GPIO_21_RISING_INTERRUPT (68)
#define NV2080_NOTIFIERS_GPIO_22_RISING_INTERRUPT (69)
#define NV2080_NOTIFIERS_GPIO_23_RISING_INTERRUPT (70)
#define NV2080_NOTIFIERS_GPIO_24_RISING_INTERRUPT (71)
#define NV2080_NOTIFIERS_GPIO_25_RISING_INTERRUPT (72)
#define NV2080_NOTIFIERS_GPIO_26_RISING_INTERRUPT (73)
#define NV2080_NOTIFIERS_GPIO_27_RISING_INTERRUPT (74)
#define NV2080_NOTIFIERS_GPIO_28_RISING_INTERRUPT (75)
#define NV2080_NOTIFIERS_GPIO_29_RISING_INTERRUPT (76)
#define NV2080_NOTIFIERS_GPIO_30_RISING_INTERRUPT (77)
#define NV2080_NOTIFIERS_GPIO_31_RISING_INTERRUPT (78)
#define NV2080_NOTIFIERS_GPIO_0_FALLING_INTERRUPT (79)
#define NV2080_NOTIFIERS_GPIO_1_FALLING_INTERRUPT (80)
#define NV2080_NOTIFIERS_GPIO_2_FALLING_INTERRUPT (81)
#define NV2080_NOTIFIERS_GPIO_3_FALLING_INTERRUPT (82)
#define NV2080_NOTIFIERS_GPIO_4_FALLING_INTERRUPT (83)
#define NV2080_NOTIFIERS_GPIO_5_FALLING_INTERRUPT (84)
#define NV2080_NOTIFIERS_GPIO_6_FALLING_INTERRUPT (85)
#define NV2080_NOTIFIERS_GPIO_7_FALLING_INTERRUPT (86)
#define NV2080_NOTIFIERS_GPIO_8_FALLING_INTERRUPT (87)
#define NV2080_NOTIFIERS_GPIO_9_FALLING_INTERRUPT (88)
#define NV2080_NOTIFIERS_GPIO_10_FALLING_INTERRUPT (89)
#define NV2080_NOTIFIERS_GPIO_11_FALLING_INTERRUPT (90)
#define NV2080_NOTIFIERS_GPIO_12_FALLING_INTERRUPT (91)
#define NV2080_NOTIFIERS_GPIO_13_FALLING_INTERRUPT (92)
#define NV2080_NOTIFIERS_GPIO_14_FALLING_INTERRUPT (93)
#define NV2080_NOTIFIERS_GPIO_15_FALLING_INTERRUPT (94)
#define NV2080_NOTIFIERS_GPIO_16_FALLING_INTERRUPT (95)
#define NV2080_NOTIFIERS_GPIO_17_FALLING_INTERRUPT (96)
#define NV2080_NOTIFIERS_GPIO_18_FALLING_INTERRUPT (97)
#define NV2080_NOTIFIERS_GPIO_19_FALLING_INTERRUPT (98)
#define NV2080_NOTIFIERS_GPIO_20_FALLING_INTERRUPT (99)
#define NV2080_NOTIFIERS_GPIO_21_FALLING_INTERRUPT (100)
#define NV2080_NOTIFIERS_GPIO_22_FALLING_INTERRUPT (101)
#define NV2080_NOTIFIERS_GPIO_23_FALLING_INTERRUPT (102)
#define NV2080_NOTIFIERS_GPIO_24_FALLING_INTERRUPT (103)
#define NV2080_NOTIFIERS_GPIO_25_FALLING_INTERRUPT (104)
#define NV2080_NOTIFIERS_GPIO_26_FALLING_INTERRUPT (105)
#define NV2080_NOTIFIERS_GPIO_27_FALLING_INTERRUPT (106)
#define NV2080_NOTIFIERS_GPIO_28_FALLING_INTERRUPT (107)
#define NV2080_NOTIFIERS_GPIO_29_FALLING_INTERRUPT (108)
#define NV2080_NOTIFIERS_GPIO_30_FALLING_INTERRUPT (109)
#define NV2080_NOTIFIERS_GPIO_31_FALLING_INTERRUPT (110)
#define NV2080_NOTIFIERS_ECC_SBE (111)
#define NV2080_NOTIFIERS_ECC_DBE (112)
#define NV2080_NOTIFIERS_STEREO_EMITTER_DETECTION (113)
#define NV2080_NOTIFIERS_GC5_GPU_READY (114)
#define NV2080_NOTIFIERS_SEC2 (115)
#define NV2080_NOTIFIERS_GC6_REFCOUNT_INC (116)
#define NV2080_NOTIFIERS_GC6_REFCOUNT_DEC (117)
#define NV2080_NOTIFIERS_POWER_EVENT (118)
#define NV2080_NOTIFIERS_CLOCKS_CHANGE (119)
#define NV2080_NOTIFIERS_HOTPLUG_PROCESSING_COMPLETE (120)
#define NV2080_NOTIFIERS_PHYSICAL_PAGE_FAULT (121)
#define NV2080_NOTIFIERS_RESERVED122 (122)
#define NV2080_NOTIFIERS_NVLINK_ERROR_FATAL (123)
#define NV2080_NOTIFIERS_PRIV_REG_ACCESS_FAULT (124)
#define NV2080_NOTIFIERS_NVLINK_ERROR_RECOVERY_REQUIRED (125)
#define NV2080_NOTIFIERS_NVJPG (126)
#define NV2080_NOTIFIERS_NVJPEG0 NV2080_NOTIFIERS_NVJPG
#define NV2080_NOTIFIERS_NVJPEG1 (127)
#define NV2080_NOTIFIERS_NVJPEG2 (128)
#define NV2080_NOTIFIERS_NVJPEG3 (129)
#define NV2080_NOTIFIERS_NVJPEG4 (130)
#define NV2080_NOTIFIERS_NVJPEG5 (131)
#define NV2080_NOTIFIERS_NVJPEG6 (132)
#define NV2080_NOTIFIERS_NVJPEG7 (133)
#define NV2080_NOTIFIERS_RUNLIST_AND_ENG_IDLE (134)
#define NV2080_NOTIFIERS_RUNLIST_ACQUIRE (135)
#define NV2080_NOTIFIERS_RUNLIST_ACQUIRE_AND_ENG_IDLE (136)
#define NV2080_NOTIFIERS_RUNLIST_IDLE (137)
#define NV2080_NOTIFIERS_TSG_PREEMPT_COMPLETE (138)
#define NV2080_NOTIFIERS_RUNLIST_PREEMPT_COMPLETE (139)
#define NV2080_NOTIFIERS_CTXSW_TIMEOUT (140)
#define NV2080_NOTIFIERS_INFOROM_ECC_OBJECT_UPDATED (141)
#define NV2080_NOTIFIERS_NVTELEMETRY_REPORT_EVENT (142)
#define NV2080_NOTIFIERS_DSTATE_XUSB_PPC (143)
#define NV2080_NOTIFIERS_FECS_CTX_SWITCH (144)
#define NV2080_NOTIFIERS_XUSB_PPC_CONNECTED (145)
#define NV2080_NOTIFIERS_GR0 NV2080_NOTIFIERS_GRAPHICS
#define NV2080_NOTIFIERS_GR1 (146)
#define NV2080_NOTIFIERS_GR2 (147)
#define NV2080_NOTIFIERS_GR3 (148)
#define NV2080_NOTIFIERS_GR4 (149)
#define NV2080_NOTIFIERS_GR5 (150)
#define NV2080_NOTIFIERS_GR6 (151)
#define NV2080_NOTIFIERS_GR7 (152)
#define NV2080_NOTIFIERS_OFA (153)
#define NV2080_NOTIFIERS_DSTATE_HDA (154)
#define NV2080_NOTIFIERS_POISON_ERROR_NON_FATAL (155)
#define NV2080_NOTIFIERS_POISON_ERROR_FATAL (156)
#define NV2080_NOTIFIERS_UCODE_RESET (157)
#define NV2080_NOTIFIERS_PLATFORM_POWER_MODE_CHANGE (158)
#define NV2080_NOTIFIERS_SMC_CONFIG_UPDATE (159)
#define NV2080_NOTIFIERS_INFOROM_RRL_OBJECT_UPDATED (160)
#define NV2080_NOTIFIERS_INFOROM_PBL_OBJECT_UPDATED (161)
#define NV2080_NOTIFIERS_LPWR_DIFR_PREFETCH_REQUEST (162)
#define NV2080_NOTIFIERS_SEC_FAULT_ERROR (163)
#define NV2080_NOTIFIERS_POSSIBLE_ERROR (164)
#define NV2080_NOTIFIERS_MAXCOUNT (165)
// Indexed GR notifier reference
#define NV2080_NOTIFIERS_GR(x) ((x == 0) ? (NV2080_NOTIFIERS_GR0) : (NV2080_NOTIFIERS_GR1 + (x-1)))
#define NV2080_NOTIFIER_TYPE_IS_GR(x) (((x) == NV2080_NOTIFIERS_GR0) || (((x) >= NV2080_NOTIFIERS_GR1) && ((x) <= NV2080_NOTIFIERS_GR7)))
// Indexed CE notifier reference
#define NV2080_NOTIFIERS_CE(x) (NV2080_NOTIFIERS_CE0 + (x))
#define NV2080_NOTIFIER_TYPE_IS_CE(x) (((x) >= NV2080_NOTIFIERS_CE0) && ((x) <= NV2080_NOTIFIERS_CE9))
// Indexed MSENC notifier reference
#define NV2080_NOTIFIERS_NVENC(x) (NV2080_NOTIFIERS_NVENC0 + (x))
#define NV2080_NOTIFIER_TYPE_IS_NVENC(x) (((x) >= NV2080_NOTIFIERS_NVENC0) && ((x) <= NV2080_NOTIFIERS_NVENC2))
// Indexed NVDEC notifier reference
#define NV2080_NOTIFIERS_NVDEC(x) (NV2080_NOTIFIERS_NVDEC0 + (x))
#define NV2080_NOTIFIER_TYPE_IS_NVDEC(x) (((x) >= NV2080_NOTIFIERS_NVDEC0) && ((x) <= NV2080_NOTIFIERS_NVDEC7))
// Indexed NVJPEG notifier reference
#define NV2080_NOTIFIERS_NVJPEG(x) (NV2080_NOTIFIERS_NVJPEG0 + (x))
#define NV2080_NOTIFIER_TYPE_IS_NVJPEG(x) (((x) >= NV2080_NOTIFIERS_NVJPEG0) && ((x) <= NV2080_NOTIFIERS_NVJPEG7))
#define NV2080_NOTIFIERS_GPIO_RISING_INTERRUPT(pin) (NV2080_NOTIFIERS_GPIO_0_RISING_INTERRUPT+(pin))
#define NV2080_NOTIFIERS_GPIO_FALLING_INTERRUPT(pin) (NV2080_NOTIFIERS_GPIO_0_FALLING_INTERRUPT+(pin))
#define NV2080_SUBDEVICE_NOTIFICATION_STATUS_IN_PROGRESS (0x8000)
#define NV2080_SUBDEVICE_NOTIFICATION_STATUS_BAD_ARGUMENT (0x4000)
#define NV2080_SUBDEVICE_NOTIFICATION_STATUS_ERROR_INVALID_STATE (0x2000)
#define NV2080_SUBDEVICE_NOTIFICATION_STATUS_ERROR_STATE_IN_USE (0x1000)
#define NV2080_SUBDEVICE_NOTIFICATION_STATUS_DONE_SUCCESS (0x0000)
/* exported engine defines */
#define NV2080_ENGINE_TYPE_NULL (0x00000000)
#define NV2080_ENGINE_TYPE_GRAPHICS (0x00000001)
#define NV2080_ENGINE_TYPE_GR0 NV2080_ENGINE_TYPE_GRAPHICS
#define NV2080_ENGINE_TYPE_GR1 (0x00000002)
#define NV2080_ENGINE_TYPE_GR2 (0x00000003)
#define NV2080_ENGINE_TYPE_GR3 (0x00000004)
#define NV2080_ENGINE_TYPE_GR4 (0x00000005)
#define NV2080_ENGINE_TYPE_GR5 (0x00000006)
#define NV2080_ENGINE_TYPE_GR6 (0x00000007)
#define NV2080_ENGINE_TYPE_GR7 (0x00000008)
#define NV2080_ENGINE_TYPE_COPY0 (0x00000009)
#define NV2080_ENGINE_TYPE_COPY1 (0x0000000a)
#define NV2080_ENGINE_TYPE_COPY2 (0x0000000b)
#define NV2080_ENGINE_TYPE_COPY3 (0x0000000c)
#define NV2080_ENGINE_TYPE_COPY4 (0x0000000d)
#define NV2080_ENGINE_TYPE_COPY5 (0x0000000e)
#define NV2080_ENGINE_TYPE_COPY6 (0x0000000f)
#define NV2080_ENGINE_TYPE_COPY7 (0x00000010)
#define NV2080_ENGINE_TYPE_COPY8 (0x00000011)
#define NV2080_ENGINE_TYPE_COPY9 (0x00000012)
#define NV2080_ENGINE_TYPE_BSP (0x00000013)
#define NV2080_ENGINE_TYPE_NVDEC0 NV2080_ENGINE_TYPE_BSP
#define NV2080_ENGINE_TYPE_NVDEC1 (0x00000014)
#define NV2080_ENGINE_TYPE_NVDEC2 (0x00000015)
#define NV2080_ENGINE_TYPE_NVDEC3 (0x00000016)
#define NV2080_ENGINE_TYPE_NVDEC4 (0x00000017)
#define NV2080_ENGINE_TYPE_NVDEC5 (0x00000018)
#define NV2080_ENGINE_TYPE_NVDEC6 (0x00000019)
#define NV2080_ENGINE_TYPE_NVDEC7 (0x0000001a)
#define NV2080_ENGINE_TYPE_MSENC (0x0000001b)
#define NV2080_ENGINE_TYPE_NVENC0 NV2080_ENGINE_TYPE_MSENC /* Mutually exclusive alias */
#define NV2080_ENGINE_TYPE_NVENC1 (0x0000001c)
#define NV2080_ENGINE_TYPE_NVENC2 (0x0000001d)
#define NV2080_ENGINE_TYPE_VP (0x0000001e)
#define NV2080_ENGINE_TYPE_ME (0x0000001f)
#define NV2080_ENGINE_TYPE_PPP (0x00000020)
#define NV2080_ENGINE_TYPE_MPEG (0x00000021)
#define NV2080_ENGINE_TYPE_SW (0x00000022)
#define NV2080_ENGINE_TYPE_CIPHER (0x00000023)
#define NV2080_ENGINE_TYPE_TSEC NV2080_ENGINE_TYPE_CIPHER
#define NV2080_ENGINE_TYPE_VIC (0x00000024)
#define NV2080_ENGINE_TYPE_MP (0x00000025)
#define NV2080_ENGINE_TYPE_SEC2 (0x00000026)
#define NV2080_ENGINE_TYPE_HOST (0x00000027)
#define NV2080_ENGINE_TYPE_DPU (0x00000028)
#define NV2080_ENGINE_TYPE_PMU (0x00000029)
#define NV2080_ENGINE_TYPE_FBFLCN (0x0000002a)
#define NV2080_ENGINE_TYPE_NVJPG (0x0000002b)
#define NV2080_ENGINE_TYPE_NVJPEG0 NV2080_ENGINE_TYPE_NVJPG
#define NV2080_ENGINE_TYPE_NVJPEG1 (0x0000002c)
#define NV2080_ENGINE_TYPE_NVJPEG2 (0x0000002d)
#define NV2080_ENGINE_TYPE_NVJPEG3 (0x0000002e)
#define NV2080_ENGINE_TYPE_NVJPEG4 (0x0000002f)
#define NV2080_ENGINE_TYPE_NVJPEG5 (0x00000030)
#define NV2080_ENGINE_TYPE_NVJPEG6 (0x00000031)
#define NV2080_ENGINE_TYPE_NVJPEG7 (0x00000032)
#define NV2080_ENGINE_TYPE_OFA (0x00000033)
#define NV2080_ENGINE_TYPE_LAST (0x00000034)
#define NV2080_ENGINE_TYPE_ALLENGINES (0xffffffff)
#define NV2080_ENGINE_TYPE_COPY_SIZE 10
#define NV2080_ENGINE_TYPE_NVENC_SIZE 3
#define NV2080_ENGINE_TYPE_NVJPEG_SIZE 8
#define NV2080_ENGINE_TYPE_NVDEC_SIZE 8
#define NV2080_ENGINE_TYPE_GR_SIZE 8
// Indexed engines
#define NV2080_ENGINE_TYPE_COPY(i) (NV2080_ENGINE_TYPE_COPY0+(i))
#define NV2080_ENGINE_TYPE_IS_COPY(i) (((i) >= NV2080_ENGINE_TYPE_COPY0) && ((i) < NV2080_ENGINE_TYPE_COPY(NV2080_ENGINE_TYPE_COPY_SIZE)))
#define NV2080_ENGINE_TYPE_COPY_IDX(i) ((i) - NV2080_ENGINE_TYPE_COPY0)
#define NV2080_ENGINE_TYPE_NVENC(i) (NV2080_ENGINE_TYPE_NVENC0+(i))
#define NV2080_ENGINE_TYPE_IS_NVENC(i) (((i) >= NV2080_ENGINE_TYPE_NVENC0) && ((i) < NV2080_ENGINE_TYPE_NVENC(NV2080_ENGINE_TYPE_NVENC_SIZE)))
#define NV2080_ENGINE_TYPE_NVENC_IDX(i) ((i) - NV2080_ENGINE_TYPE_NVENC0)
#define NV2080_ENGINE_TYPE_NVDEC(i) (NV2080_ENGINE_TYPE_NVDEC0+(i))
#define NV2080_ENGINE_TYPE_IS_NVDEC(i) (((i) >= NV2080_ENGINE_TYPE_NVDEC0) && ((i) < NV2080_ENGINE_TYPE_NVDEC(NV2080_ENGINE_TYPE_NVDEC_SIZE)))
#define NV2080_ENGINE_TYPE_NVDEC_IDX(i) ((i) - NV2080_ENGINE_TYPE_NVDEC0)
#define NV2080_ENGINE_TYPE_NVJPEG(i) (NV2080_ENGINE_TYPE_NVJPEG0+(i))
#define NV2080_ENGINE_TYPE_IS_NVJPEG(i) (((i) >= NV2080_ENGINE_TYPE_NVJPEG0) && ((i) < NV2080_ENGINE_TYPE_NVJPEG(NV2080_ENGINE_TYPE_NVJPEG_SIZE)))
#define NV2080_ENGINE_TYPE_NVJPEG_IDX(i) ((i) - NV2080_ENGINE_TYPE_NVJPEG0)
#define NV2080_ENGINE_TYPE_GR(i) (NV2080_ENGINE_TYPE_GR0 + (i))
#define NV2080_ENGINE_TYPE_IS_GR(i) (((i) >= NV2080_ENGINE_TYPE_GR0) && ((i) < NV2080_ENGINE_TYPE_GR(NV2080_ENGINE_TYPE_GR_SIZE)))
#define NV2080_ENGINE_TYPE_GR_IDX(i) ((i) - NV2080_ENGINE_TYPE_GR0)
#define NV2080_ENGINE_TYPE_IS_VALID(i) (((i) > (NV2080_ENGINE_TYPE_NULL)) && ((i) < (NV2080_ENGINE_TYPE_LAST)))
/* exported client defines */
#define NV2080_CLIENT_TYPE_TEX (0x00000001)
#define NV2080_CLIENT_TYPE_COLOR (0x00000002)
#define NV2080_CLIENT_TYPE_DEPTH (0x00000003)
#define NV2080_CLIENT_TYPE_DA (0x00000004)
#define NV2080_CLIENT_TYPE_FE (0x00000005)
#define NV2080_CLIENT_TYPE_SCC (0x00000006)
#define NV2080_CLIENT_TYPE_WID (0x00000007)
#define NV2080_CLIENT_TYPE_MSVLD (0x00000008)
#define NV2080_CLIENT_TYPE_MSPDEC (0x00000009)
#define NV2080_CLIENT_TYPE_MSPPP (0x0000000a)
#define NV2080_CLIENT_TYPE_VIC (0x0000000b)
#define NV2080_CLIENT_TYPE_ALLCLIENTS (0xffffffff)
/* GC5 Gpu Ready event defines */
#define NV2080_GC5_EXIT_COMPLETE (0x00000001)
#define NV2080_GC5_ENTRY_ABORTED (0x00000002)
/* Platform Power Mode event defines */
#define NV2080_PLATFORM_POWER_MODE_CHANGE_COMPLETION (0x00000000)
#define NV2080_PLATFORM_POWER_MODE_CHANGE_ACPI_NOTIFICATION (0x00000001)
/* NvNotification[] fields and values */
#define NV2080_NOTIFICATION_STATUS_ERROR_PROTECTION_FAULT (0x4000)
/* pio method data structure */
typedef volatile struct _cl2080_tag0 {
NvV32 Reserved00[0x7c0];
} Nv2080Typedef, Nv20Subdevice0;
#define NV2080_TYPEDEF Nv20Subdevice0
#define NV20_SUBDEVICE_0 (0x2080U) /* finn: Evaluated from "NV2080_ALLOC_PARAMETERS_MESSAGE_ID" */
/* NvAlloc parameteters */
#define NV2080_MAX_SUBDEVICES NV_MAX_SUBDEVICES
typedef struct {
NvU32 subDeviceId;
#define NV2080_MAX_SUBDEVICES NV_MAX_SUBDEVICES
#define NV2080_ALLOC_PARAMETERS_MESSAGE_ID (0x2080U)
typedef struct NV2080_ALLOC_PARAMETERS {
NvU32 subDeviceId;
} NV2080_ALLOC_PARAMETERS;
/* HDCP Status change notification information */
typedef struct Nv2080HdcpStatusChangeNotificationRec {
NvU32 displayId;
NvU32 hdcpStatusChangeNotif;
} Nv2080HdcpStatusChangeNotification;
/* Pstate change notification information */
typedef struct Nv2080PStateChangeNotificationRec {
struct {
NvU32 nanoseconds[2]; /* nanoseconds since Jan. 1, 1970 0- 7*/
} timeStamp; /* -0007*/
NvU32 NewPstate;
} Nv2080PStateChangeNotification;
/* Clocks change notification information */
typedef struct Nv2080ClocksChangeNotificationRec {
struct {
NvU32 nanoseconds[2]; /* nanoseconds since Jan. 1, 1970 0- 7*/
} timeStamp; /* -0007*/
} Nv2080ClocksChangeNotification;
/* WorkLoad Modulation state change notification information*/
typedef struct Nv2080WorkloadModulationChangeNotificationRec {
struct {
NvU32 nanoseconds[2]; /* nanoseconds since Jan. 1, 1970 0- 7*/
} timeStamp; /* -0007*/
NvBool WorkloadModulationEnabled;
} Nv2080WorkloadModulationChangeNotification;
/* Hotplug notification information */
typedef struct {
NvU32 plugDisplayMask;
NvU32 unplugDisplayMask;
} Nv2080HotplugNotification;
/* Power state changing notification information */
typedef struct {
NvBool bSwitchToAC;
NvBool bGPUCapabilityChanged;
NvU32 displayMaskAffected;
} Nv2080PowerEventNotification;
/* DP IRQ notification information */
typedef struct Nv2080DpIrqNotificationRec {
NvU32 displayId;
} Nv2080DpIrqNotification;
/* XUSB/PPC D-State change notification information */
typedef struct Nv2080DstateXusbPpcNotificationRec {
NvU32 dstateXusb;
NvU32 dstatePpc;
} Nv2080DstateXusbPpcNotification;
/* XUSB/PPC Connection status notification information */
typedef struct Nv2080XusbPpcConnectStateNotificationRec {
NvBool bConnected;
} Nv2080XusbPpcConnectStateNotification;
/* ACPI event notification information */
typedef struct Nv2080ACPIEvent {
NvU32 event;
} Nv2080ACPIEvent;
/* Cooler Zone notification information */
typedef struct _NV2080_COOLER_DIAG_ZONE_NOTIFICATION_REC {
NvU32 currentZone;
} NV2080_COOLER_DIAG_ZONE_NOTIFICATION_REC;
/* Thermal Zone notification information */
typedef struct _NV2080_THERM_DIAG_ZONE_NOTIFICATION_REC {
NvU32 currentZone;
} NV2080_THERM_DIAG_ZONE_NOTIFICATION_REC;
/* HDCP ref count change notification information */
typedef struct Nv2080AudioHdcpRequestRec {
NvU32 displayId;
NvU32 requestedState;
} Nv2080AudioHdcpRequest;
/* Gpu ready event information */
typedef struct Nv2080GC5GpuReadyParams {
NvU32 event;
NvU32 sciIntr0;
NvU32 sciIntr1;
} Nv2080GC5GpuReadyParams;
/* Priv reg access fault notification information */
typedef struct {
NvU32 errAddr;
} Nv2080PrivRegAccessFaultNotification;
/* HDA D-State change notification information
* See @HDACODEC_DSTATE for definitions
*/
typedef struct Nv2080DstateHdaCodecNotificationRec {
NvU32 dstateHdaCodec;
} Nv2080DstateHdaCodecNotification;
/*
* Platform Power Mode event information
*/
typedef struct _NV2080_PLATFORM_POWER_MODE_CHANGE_STATUS {
NvU8 platformPowerModeIndex;
NvU8 platformPowerModeMask;
NvU8 eventReason;
} NV2080_PLATFORM_POWER_MODE_CHANGE_STATUS;
#define NV2080_PLATFORM_POWER_MODE_CHANGE_INFO_INDEX 7:0
#define NV2080_PLATFORM_POWER_MODE_CHANGE_INFO_MASK 15:8
#define NV2080_PLATFORM_POWER_MODE_CHANGE_INFO_REASON 23:16
/*
* ENGINE_INFO_TYPE_NV2080 of the engine for which the QOS interrupt has been raised
*/
typedef struct {
NvU32 engineType;
} Nv2080QosIntrNotification;
typedef struct {
NvU64 physAddress NV_ALIGN_BYTES(8);
} Nv2080EccDbeNotification;
/*
* LPWR DIFR Prefetch Request - Size of L2 Cache
*/
typedef struct {
NvU32 l2CacheSize;
} Nv2080LpwrDifrPrefetchNotification;
#ifdef __cplusplus
}; /* extern "C" */
#endif
#endif /* _cl2080_h_ */

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src/common/sdk/nvidia/inc/class/cl2080_notification.h Normal file
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/*
* SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _cl2080_notification_h_
#define _cl2080_notification_h_
#ifdef __cplusplus
extern "C" {
#endif
/* event values */
#define NV2080_NOTIFIERS_SW (0)
#define NV2080_NOTIFIERS_HOTPLUG (1)
#define NV2080_NOTIFIERS_POWER_CONNECTOR (2)
#define NV2080_NOTIFIERS_THERMAL_SW (3)
#define NV2080_NOTIFIERS_THERMAL_HW (4)
#define NV2080_NOTIFIERS_FULL_SCREEN_CHANGE (5)
#define NV2080_NOTIFIERS_EVENTBUFFER (6)
#define NV2080_NOTIFIERS_DP_IRQ (7)
#define NV2080_NOTIFIERS_GR_DEBUG_INTR (8)
#define NV2080_NOTIFIERS_PMU_EVENT (9)
#define NV2080_NOTIFIERS_PMU_COMMAND (10)
#define NV2080_NOTIFIERS_TIMER (11)
#define NV2080_NOTIFIERS_GRAPHICS (12)
#define NV2080_NOTIFIERS_PPP (13)
#define NV2080_NOTIFIERS_VLD (14) // also known as BSP
#define NV2080_NOTIFIERS_NVDEC0 NV2080_NOTIFIERS_VLD
#define NV2080_NOTIFIERS_NVDEC1 (15)
#define NV2080_NOTIFIERS_NVDEC2 (16)
#define NV2080_NOTIFIERS_NVDEC3 (17)
#define NV2080_NOTIFIERS_NVDEC4 (18)
#define NV2080_NOTIFIERS_NVDEC5 (19)
#define NV2080_NOTIFIERS_NVDEC6 (20)
#define NV2080_NOTIFIERS_NVDEC7 (21)
#define NV2080_NOTIFIERS_PDEC (22) // also known as VP
#define NV2080_NOTIFIERS_CE0 (23)
#define NV2080_NOTIFIERS_CE1 (24)
#define NV2080_NOTIFIERS_CE2 (25)
#define NV2080_NOTIFIERS_CE3 (26)
#define NV2080_NOTIFIERS_CE4 (27)
#define NV2080_NOTIFIERS_CE5 (28)
#define NV2080_NOTIFIERS_CE6 (29)
#define NV2080_NOTIFIERS_CE7 (30)
#define NV2080_NOTIFIERS_CE8 (31)
#define NV2080_NOTIFIERS_CE9 (32)
#define NV2080_NOTIFIERS_PSTATE_CHANGE (33)
#define NV2080_NOTIFIERS_HDCP_STATUS_CHANGE (34)
#define NV2080_NOTIFIERS_FIFO_EVENT_MTHD (35)
#define NV2080_NOTIFIERS_PRIV_RING_HANG (36)
#define NV2080_NOTIFIERS_RC_ERROR (37)
#define NV2080_NOTIFIERS_MSENC (38)
#define NV2080_NOTIFIERS_NVENC0 NV2080_NOTIFIERS_MSENC
#define NV2080_NOTIFIERS_NVENC1 (39)
#define NV2080_NOTIFIERS_NVENC2 (40)
#define NV2080_NOTIFIERS_UNUSED_0 (41) // Unused
#define NV2080_NOTIFIERS_ACPI_NOTIFY (42)
#define NV2080_NOTIFIERS_COOLER_DIAG_ZONE (43)
#define NV2080_NOTIFIERS_THERMAL_DIAG_ZONE (44)
#define NV2080_NOTIFIERS_AUDIO_HDCP_REQUEST (45)
#define NV2080_NOTIFIERS_WORKLOAD_MODULATION_CHANGE (46)
#define NV2080_NOTIFIERS_GPIO_0_RISING_INTERRUPT (47)
#define NV2080_NOTIFIERS_GPIO_1_RISING_INTERRUPT (48)
#define NV2080_NOTIFIERS_GPIO_2_RISING_INTERRUPT (49)
#define NV2080_NOTIFIERS_GPIO_3_RISING_INTERRUPT (50)
#define NV2080_NOTIFIERS_GPIO_4_RISING_INTERRUPT (51)
#define NV2080_NOTIFIERS_GPIO_5_RISING_INTERRUPT (52)
#define NV2080_NOTIFIERS_GPIO_6_RISING_INTERRUPT (53)
#define NV2080_NOTIFIERS_GPIO_7_RISING_INTERRUPT (54)
#define NV2080_NOTIFIERS_GPIO_8_RISING_INTERRUPT (55)
#define NV2080_NOTIFIERS_GPIO_9_RISING_INTERRUPT (56)
#define NV2080_NOTIFIERS_GPIO_10_RISING_INTERRUPT (57)
#define NV2080_NOTIFIERS_GPIO_11_RISING_INTERRUPT (58)
#define NV2080_NOTIFIERS_GPIO_12_RISING_INTERRUPT (59)
#define NV2080_NOTIFIERS_GPIO_13_RISING_INTERRUPT (60)
#define NV2080_NOTIFIERS_GPIO_14_RISING_INTERRUPT (61)
#define NV2080_NOTIFIERS_GPIO_15_RISING_INTERRUPT (62)
#define NV2080_NOTIFIERS_GPIO_16_RISING_INTERRUPT (63)
#define NV2080_NOTIFIERS_GPIO_17_RISING_INTERRUPT (64)
#define NV2080_NOTIFIERS_GPIO_18_RISING_INTERRUPT (65)
#define NV2080_NOTIFIERS_GPIO_19_RISING_INTERRUPT (66)
#define NV2080_NOTIFIERS_GPIO_20_RISING_INTERRUPT (67)
#define NV2080_NOTIFIERS_GPIO_21_RISING_INTERRUPT (68)
#define NV2080_NOTIFIERS_GPIO_22_RISING_INTERRUPT (69)
#define NV2080_NOTIFIERS_GPIO_23_RISING_INTERRUPT (70)
#define NV2080_NOTIFIERS_GPIO_24_RISING_INTERRUPT (71)
#define NV2080_NOTIFIERS_GPIO_25_RISING_INTERRUPT (72)
#define NV2080_NOTIFIERS_GPIO_26_RISING_INTERRUPT (73)
#define NV2080_NOTIFIERS_GPIO_27_RISING_INTERRUPT (74)
#define NV2080_NOTIFIERS_GPIO_28_RISING_INTERRUPT (75)
#define NV2080_NOTIFIERS_GPIO_29_RISING_INTERRUPT (76)
#define NV2080_NOTIFIERS_GPIO_30_RISING_INTERRUPT (77)
#define NV2080_NOTIFIERS_GPIO_31_RISING_INTERRUPT (78)
#define NV2080_NOTIFIERS_GPIO_0_FALLING_INTERRUPT (79)
#define NV2080_NOTIFIERS_GPIO_1_FALLING_INTERRUPT (80)
#define NV2080_NOTIFIERS_GPIO_2_FALLING_INTERRUPT (81)
#define NV2080_NOTIFIERS_GPIO_3_FALLING_INTERRUPT (82)
#define NV2080_NOTIFIERS_GPIO_4_FALLING_INTERRUPT (83)
#define NV2080_NOTIFIERS_GPIO_5_FALLING_INTERRUPT (84)
#define NV2080_NOTIFIERS_GPIO_6_FALLING_INTERRUPT (85)
#define NV2080_NOTIFIERS_GPIO_7_FALLING_INTERRUPT (86)
#define NV2080_NOTIFIERS_GPIO_8_FALLING_INTERRUPT (87)
#define NV2080_NOTIFIERS_GPIO_9_FALLING_INTERRUPT (88)
#define NV2080_NOTIFIERS_GPIO_10_FALLING_INTERRUPT (89)
#define NV2080_NOTIFIERS_GPIO_11_FALLING_INTERRUPT (90)
#define NV2080_NOTIFIERS_GPIO_12_FALLING_INTERRUPT (91)
#define NV2080_NOTIFIERS_GPIO_13_FALLING_INTERRUPT (92)
#define NV2080_NOTIFIERS_GPIO_14_FALLING_INTERRUPT (93)
#define NV2080_NOTIFIERS_GPIO_15_FALLING_INTERRUPT (94)
#define NV2080_NOTIFIERS_GPIO_16_FALLING_INTERRUPT (95)
#define NV2080_NOTIFIERS_GPIO_17_FALLING_INTERRUPT (96)
#define NV2080_NOTIFIERS_GPIO_18_FALLING_INTERRUPT (97)
#define NV2080_NOTIFIERS_GPIO_19_FALLING_INTERRUPT (98)
#define NV2080_NOTIFIERS_GPIO_20_FALLING_INTERRUPT (99)
#define NV2080_NOTIFIERS_GPIO_21_FALLING_INTERRUPT (100)
#define NV2080_NOTIFIERS_GPIO_22_FALLING_INTERRUPT (101)
#define NV2080_NOTIFIERS_GPIO_23_FALLING_INTERRUPT (102)
#define NV2080_NOTIFIERS_GPIO_24_FALLING_INTERRUPT (103)
#define NV2080_NOTIFIERS_GPIO_25_FALLING_INTERRUPT (104)
#define NV2080_NOTIFIERS_GPIO_26_FALLING_INTERRUPT (105)
#define NV2080_NOTIFIERS_GPIO_27_FALLING_INTERRUPT (106)
#define NV2080_NOTIFIERS_GPIO_28_FALLING_INTERRUPT (107)
#define NV2080_NOTIFIERS_GPIO_29_FALLING_INTERRUPT (108)
#define NV2080_NOTIFIERS_GPIO_30_FALLING_INTERRUPT (109)
#define NV2080_NOTIFIERS_GPIO_31_FALLING_INTERRUPT (110)
#define NV2080_NOTIFIERS_ECC_SBE (111)
#define NV2080_NOTIFIERS_ECC_DBE (112)
#define NV2080_NOTIFIERS_STEREO_EMITTER_DETECTION (113)
#define NV2080_NOTIFIERS_GC5_GPU_READY (114)
#define NV2080_NOTIFIERS_SEC2 (115)
#define NV2080_NOTIFIERS_GC6_REFCOUNT_INC (116)
#define NV2080_NOTIFIERS_GC6_REFCOUNT_DEC (117)
#define NV2080_NOTIFIERS_POWER_EVENT (118)
#define NV2080_NOTIFIERS_CLOCKS_CHANGE (119)
#define NV2080_NOTIFIERS_HOTPLUG_PROCESSING_COMPLETE (120)
#define NV2080_NOTIFIERS_PHYSICAL_PAGE_FAULT (121)
#define NV2080_NOTIFIERS_RESERVED122 (122)
#define NV2080_NOTIFIERS_NVLINK_ERROR_FATAL (123)
#define NV2080_NOTIFIERS_PRIV_REG_ACCESS_FAULT (124)
#define NV2080_NOTIFIERS_NVLINK_ERROR_RECOVERY_REQUIRED (125)
#define NV2080_NOTIFIERS_NVJPG (126)
#define NV2080_NOTIFIERS_NVJPEG0 NV2080_NOTIFIERS_NVJPG
#define NV2080_NOTIFIERS_NVJPEG1 (127)
#define NV2080_NOTIFIERS_NVJPEG2 (128)
#define NV2080_NOTIFIERS_NVJPEG3 (129)
#define NV2080_NOTIFIERS_NVJPEG4 (130)
#define NV2080_NOTIFIERS_NVJPEG5 (131)
#define NV2080_NOTIFIERS_NVJPEG6 (132)
#define NV2080_NOTIFIERS_NVJPEG7 (133)
#define NV2080_NOTIFIERS_RUNLIST_AND_ENG_IDLE (134)
#define NV2080_NOTIFIERS_RUNLIST_ACQUIRE (135)
#define NV2080_NOTIFIERS_RUNLIST_ACQUIRE_AND_ENG_IDLE (136)
#define NV2080_NOTIFIERS_RUNLIST_IDLE (137)
#define NV2080_NOTIFIERS_TSG_PREEMPT_COMPLETE (138)
#define NV2080_NOTIFIERS_RUNLIST_PREEMPT_COMPLETE (139)
#define NV2080_NOTIFIERS_CTXSW_TIMEOUT (140)
#define NV2080_NOTIFIERS_INFOROM_ECC_OBJECT_UPDATED (141)
#define NV2080_NOTIFIERS_NVTELEMETRY_REPORT_EVENT (142)
#define NV2080_NOTIFIERS_DSTATE_XUSB_PPC (143)
#define NV2080_NOTIFIERS_FECS_CTX_SWITCH (144)
#define NV2080_NOTIFIERS_XUSB_PPC_CONNECTED (145)
#define NV2080_NOTIFIERS_GR0 NV2080_NOTIFIERS_GRAPHICS
#define NV2080_NOTIFIERS_GR1 (146)
#define NV2080_NOTIFIERS_GR2 (147)
#define NV2080_NOTIFIERS_GR3 (148)
#define NV2080_NOTIFIERS_GR4 (149)
#define NV2080_NOTIFIERS_GR5 (150)
#define NV2080_NOTIFIERS_GR6 (151)
#define NV2080_NOTIFIERS_GR7 (152)
#define NV2080_NOTIFIERS_OFA (153)
#define NV2080_NOTIFIERS_DSTATE_HDA (154)
#define NV2080_NOTIFIERS_POISON_ERROR_NON_FATAL (155)
#define NV2080_NOTIFIERS_POISON_ERROR_FATAL (156)
#define NV2080_NOTIFIERS_UCODE_RESET (157)
#define NV2080_NOTIFIERS_PLATFORM_POWER_MODE_CHANGE (158)
#define NV2080_NOTIFIERS_SMC_CONFIG_UPDATE (159)
#define NV2080_NOTIFIERS_INFOROM_RRL_OBJECT_UPDATED (160)
#define NV2080_NOTIFIERS_INFOROM_PBL_OBJECT_UPDATED (161)
#define NV2080_NOTIFIERS_LPWR_DIFR_PREFETCH_REQUEST (162)
#define NV2080_NOTIFIERS_SEC_FAULT_ERROR (163)
#define NV2080_NOTIFIERS_POSSIBLE_ERROR (164)
#define NV2080_NOTIFIERS_NVLINK_INFO_LINK_UP (165)
#define NV2080_NOTIFIERS_NVLINK_INFO_LINK_DOWN (176)
#define NV2080_NOTIFIERS_MAXCOUNT (177)
// Indexed GR notifier reference
#define NV2080_NOTIFIERS_GR(x) ((x == 0) ? (NV2080_NOTIFIERS_GR0) : (NV2080_NOTIFIERS_GR1 + (x - 1)))
#define NV2080_NOTIFIERS_GR_IDX(x) ((x) - NV2080_NOTIFIERS_GR0)
#define NV2080_NOTIFIER_TYPE_IS_GR(x) (((x) == NV2080_NOTIFIERS_GR0) || (((x) >= NV2080_NOTIFIERS_GR1) && ((x) <= NV2080_NOTIFIERS_GR7)))
#define NV2080_NOTIFIERS_CE(x) (NV2080_NOTIFIERS_CE0 + (x))
#define NV2080_NOTIFIERS_CE_IDX(x) ((x) - NV2080_NOTIFIERS_CE0)
#define NV2080_NOTIFIER_TYPE_IS_CE(x) (((x) >= NV2080_NOTIFIERS_CE0) && ((x) <= NV2080_NOTIFIERS_CE9))
// Indexed MSENC notifier reference
#define NV2080_NOTIFIERS_NVENC(x) (NV2080_NOTIFIERS_NVENC0 + (x))
#define NV2080_NOTIFIERS_NVENC_IDX(x) ((x) - NV2080_NOTIFIERS_NVENC0)
#define NV2080_NOTIFIER_TYPE_IS_NVENC(x) (((x) >= NV2080_NOTIFIERS_NVENC0) && ((x) <= NV2080_NOTIFIERS_NVENC2))
// Indexed NVDEC notifier reference
#define NV2080_NOTIFIERS_NVDEC(x) (NV2080_NOTIFIERS_NVDEC0 + (x))
#define NV2080_NOTIFIERS_NVDEC_IDX(x) ((x) - NV2080_NOTIFIERS_NVDEC0)
#define NV2080_NOTIFIER_TYPE_IS_NVDEC(x) (((x) >= NV2080_NOTIFIERS_NVDEC0) && ((x) <= NV2080_NOTIFIERS_NVDEC7))
// Indexed NVJPEG notifier reference
#define NV2080_NOTIFIERS_NVJPEG(x) (NV2080_NOTIFIERS_NVJPEG0 + (x))
#define NV2080_NOTIFIERS_NVJPEG_IDX(x) ((x) - NV2080_NOTIFIERS_NVJPEG0)
#define NV2080_NOTIFIER_TYPE_IS_NVJPEG(x) (((x) >= NV2080_NOTIFIERS_NVJPEG0) && ((x) <= NV2080_NOTIFIERS_NVJPEG7))
#define NV2080_NOTIFIERS_GPIO_RISING_INTERRUPT(pin) (NV2080_NOTIFIERS_GPIO_0_RISING_INTERRUPT + (pin))
#define NV2080_NOTIFIERS_GPIO_FALLING_INTERRUPT(pin) (NV2080_NOTIFIERS_GPIO_0_FALLING_INTERRUPT + (pin))
#define NV2080_SUBDEVICE_NOTIFICATION_STATUS_IN_PROGRESS (0x8000)
#define NV2080_SUBDEVICE_NOTIFICATION_STATUS_BAD_ARGUMENT (0x4000)
#define NV2080_SUBDEVICE_NOTIFICATION_STATUS_ERROR_INVALID_STATE (0x2000)
#define NV2080_SUBDEVICE_NOTIFICATION_STATUS_ERROR_STATE_IN_USE (0x1000)
#define NV2080_SUBDEVICE_NOTIFICATION_STATUS_DONE_SUCCESS (0x0000)
/* exported engine defines */
#define NV2080_ENGINE_TYPE_NULL (0x00000000)
#define NV2080_ENGINE_TYPE_GRAPHICS (0x00000001)
#define NV2080_ENGINE_TYPE_GR0 NV2080_ENGINE_TYPE_GRAPHICS
#define NV2080_ENGINE_TYPE_GR1 (0x00000002)
#define NV2080_ENGINE_TYPE_GR2 (0x00000003)
#define NV2080_ENGINE_TYPE_GR3 (0x00000004)
#define NV2080_ENGINE_TYPE_GR4 (0x00000005)
#define NV2080_ENGINE_TYPE_GR5 (0x00000006)
#define NV2080_ENGINE_TYPE_GR6 (0x00000007)
#define NV2080_ENGINE_TYPE_GR7 (0x00000008)
#define NV2080_ENGINE_TYPE_COPY0 (0x00000009)
#define NV2080_ENGINE_TYPE_COPY1 (0x0000000a)
#define NV2080_ENGINE_TYPE_COPY2 (0x0000000b)
#define NV2080_ENGINE_TYPE_COPY3 (0x0000000c)
#define NV2080_ENGINE_TYPE_COPY4 (0x0000000d)
#define NV2080_ENGINE_TYPE_COPY5 (0x0000000e)
#define NV2080_ENGINE_TYPE_COPY6 (0x0000000f)
#define NV2080_ENGINE_TYPE_COPY7 (0x00000010)
#define NV2080_ENGINE_TYPE_COPY8 (0x00000011)
#define NV2080_ENGINE_TYPE_COPY9 (0x00000012)
#define NV2080_ENGINE_TYPE_BSP (0x00000013)
#define NV2080_ENGINE_TYPE_NVDEC0 NV2080_ENGINE_TYPE_BSP
#define NV2080_ENGINE_TYPE_NVDEC1 (0x00000014)
#define NV2080_ENGINE_TYPE_NVDEC2 (0x00000015)
#define NV2080_ENGINE_TYPE_NVDEC3 (0x00000016)
#define NV2080_ENGINE_TYPE_NVDEC4 (0x00000017)
#define NV2080_ENGINE_TYPE_NVDEC5 (0x00000018)
#define NV2080_ENGINE_TYPE_NVDEC6 (0x00000019)
#define NV2080_ENGINE_TYPE_NVDEC7 (0x0000001a)
#define NV2080_ENGINE_TYPE_MSENC (0x0000001b)
#define NV2080_ENGINE_TYPE_NVENC0 NV2080_ENGINE_TYPE_MSENC /* Mutually exclusive alias */
#define NV2080_ENGINE_TYPE_NVENC1 (0x0000001c)
#define NV2080_ENGINE_TYPE_NVENC2 (0x0000001d)
#define NV2080_ENGINE_TYPE_VP (0x0000001e)
#define NV2080_ENGINE_TYPE_ME (0x0000001f)
#define NV2080_ENGINE_TYPE_PPP (0x00000020)
#define NV2080_ENGINE_TYPE_MPEG (0x00000021)
#define NV2080_ENGINE_TYPE_SW (0x00000022)
#define NV2080_ENGINE_TYPE_CIPHER (0x00000023)
#define NV2080_ENGINE_TYPE_TSEC NV2080_ENGINE_TYPE_CIPHER
#define NV2080_ENGINE_TYPE_VIC (0x00000024)
#define NV2080_ENGINE_TYPE_MP (0x00000025)
#define NV2080_ENGINE_TYPE_SEC2 (0x00000026)
#define NV2080_ENGINE_TYPE_HOST (0x00000027)
#define NV2080_ENGINE_TYPE_DPU (0x00000028)
#define NV2080_ENGINE_TYPE_PMU (0x00000029)
#define NV2080_ENGINE_TYPE_FBFLCN (0x0000002a)
#define NV2080_ENGINE_TYPE_NVJPG (0x0000002b)
#define NV2080_ENGINE_TYPE_NVJPEG0 NV2080_ENGINE_TYPE_NVJPG
#define NV2080_ENGINE_TYPE_NVJPEG1 (0x0000002c)
#define NV2080_ENGINE_TYPE_NVJPEG2 (0x0000002d)
#define NV2080_ENGINE_TYPE_NVJPEG3 (0x0000002e)
#define NV2080_ENGINE_TYPE_NVJPEG4 (0x0000002f)
#define NV2080_ENGINE_TYPE_NVJPEG5 (0x00000030)
#define NV2080_ENGINE_TYPE_NVJPEG6 (0x00000031)
#define NV2080_ENGINE_TYPE_NVJPEG7 (0x00000032)
#define NV2080_ENGINE_TYPE_OFA (0x00000033)
#define NV2080_ENGINE_TYPE_LAST (0x0000003e)
#define NV2080_ENGINE_TYPE_ALLENGINES (0xffffffff)
#define NV2080_ENGINE_TYPE_COPY_SIZE 10
#define NV2080_ENGINE_TYPE_NVENC_SIZE 3
#define NV2080_ENGINE_TYPE_NVJPEG_SIZE 8
#define NV2080_ENGINE_TYPE_NVDEC_SIZE 8
#define NV2080_ENGINE_TYPE_GR_SIZE 8
// Indexed engines
#define NV2080_ENGINE_TYPE_COPY(i) (NV2080_ENGINE_TYPE_COPY0+(i))
#define NV2080_ENGINE_TYPE_IS_COPY(i) (((i) >= NV2080_ENGINE_TYPE_COPY0) && ((i) <= NV2080_ENGINE_TYPE_COPY9))
#define NV2080_ENGINE_TYPE_COPY_IDX(i) ((i) - NV2080_ENGINE_TYPE_COPY0)
#define NV2080_ENGINE_TYPE_NVENC(i) (NV2080_ENGINE_TYPE_NVENC0+(i))
#define NV2080_ENGINE_TYPE_IS_NVENC(i) (((i) >= NV2080_ENGINE_TYPE_NVENC0) && ((i) < NV2080_ENGINE_TYPE_NVENC(NV2080_ENGINE_TYPE_NVENC_SIZE)))
#define NV2080_ENGINE_TYPE_NVENC_IDX(i) ((i) - NV2080_ENGINE_TYPE_NVENC0)
#define NV2080_ENGINE_TYPE_NVDEC(i) (NV2080_ENGINE_TYPE_NVDEC0+(i))
#define NV2080_ENGINE_TYPE_IS_NVDEC(i) (((i) >= NV2080_ENGINE_TYPE_NVDEC0) && ((i) < NV2080_ENGINE_TYPE_NVDEC(NV2080_ENGINE_TYPE_NVDEC_SIZE)))
#define NV2080_ENGINE_TYPE_NVDEC_IDX(i) ((i) - NV2080_ENGINE_TYPE_NVDEC0)
#define NV2080_ENGINE_TYPE_NVJPEG(i) (NV2080_ENGINE_TYPE_NVJPEG0+(i))
#define NV2080_ENGINE_TYPE_IS_NVJPEG(i) (((i) >= NV2080_ENGINE_TYPE_NVJPEG0) && ((i) < NV2080_ENGINE_TYPE_NVJPEG(NV2080_ENGINE_TYPE_NVJPEG_SIZE)))
#define NV2080_ENGINE_TYPE_NVJPEG_IDX(i) ((i) - NV2080_ENGINE_TYPE_NVJPEG0)
#define NV2080_ENGINE_TYPE_GR(i) (NV2080_ENGINE_TYPE_GR0 + (i))
#define NV2080_ENGINE_TYPE_IS_GR(i) (((i) >= NV2080_ENGINE_TYPE_GR0) && ((i) < NV2080_ENGINE_TYPE_GR(NV2080_ENGINE_TYPE_GR_SIZE)))
#define NV2080_ENGINE_TYPE_GR_IDX(i) ((i) - NV2080_ENGINE_TYPE_GR0)
#define NV2080_ENGINE_TYPE_IS_VALID(i) (((i) > (NV2080_ENGINE_TYPE_NULL)) && ((i) < (NV2080_ENGINE_TYPE_LAST)))
/* exported client defines */
#define NV2080_CLIENT_TYPE_TEX (0x00000001)
#define NV2080_CLIENT_TYPE_COLOR (0x00000002)
#define NV2080_CLIENT_TYPE_DEPTH (0x00000003)
#define NV2080_CLIENT_TYPE_DA (0x00000004)
#define NV2080_CLIENT_TYPE_FE (0x00000005)
#define NV2080_CLIENT_TYPE_SCC (0x00000006)
#define NV2080_CLIENT_TYPE_WID (0x00000007)
#define NV2080_CLIENT_TYPE_MSVLD (0x00000008)
#define NV2080_CLIENT_TYPE_MSPDEC (0x00000009)
#define NV2080_CLIENT_TYPE_MSPPP (0x0000000a)
#define NV2080_CLIENT_TYPE_VIC (0x0000000b)
#define NV2080_CLIENT_TYPE_ALLCLIENTS (0xffffffff)
/* GC5 Gpu Ready event defines */
#define NV2080_GC5_EXIT_COMPLETE (0x00000001)
#define NV2080_GC5_ENTRY_ABORTED (0x00000002)
/* Platform Power Mode event defines */
#define NV2080_PLATFORM_POWER_MODE_CHANGE_COMPLETION (0x00000000)
#define NV2080_PLATFORM_POWER_MODE_CHANGE_ACPI_NOTIFICATION (0x00000001)
/* NvNotification[] fields and values */
#define NV2080_NOTIFICATION_STATUS_ERROR_PROTECTION_FAULT (0x4000)
/* pio method data structure */
typedef volatile struct _cl2080_tag0 {
NvV32 Reserved00[0x7c0];
} Nv2080Typedef, Nv20Subdevice0;
#define NV2080_TYPEDEF Nv20Subdevice0
/* HDCP Status change notification information */
typedef struct Nv2080HdcpStatusChangeNotificationRec {
NvU32 displayId;
NvU32 hdcpStatusChangeNotif;
} Nv2080HdcpStatusChangeNotification;
/* Pstate change notification information */
typedef struct Nv2080PStateChangeNotificationRec {
struct {
NvU32 nanoseconds[2]; /* nanoseconds since Jan. 1, 1970 0- 7*/
} timeStamp; /* -0007*/
NvU32 NewPstate;
} Nv2080PStateChangeNotification;
/* Clocks change notification information */
typedef struct Nv2080ClocksChangeNotificationRec {
struct {
NvU32 nanoseconds[2]; /* nanoseconds since Jan. 1, 1970 0- 7*/
} timeStamp; /* -0007*/
} Nv2080ClocksChangeNotification;
/* WorkLoad Modulation state change notification information*/
typedef struct Nv2080WorkloadModulationChangeNotificationRec {
struct {
NvU32 nanoseconds[2]; /* nanoseconds since Jan. 1, 1970 0- 7*/
} timeStamp; /* -0007*/
NvBool WorkloadModulationEnabled;
} Nv2080WorkloadModulationChangeNotification;
/* Hotplug notification information */
typedef struct {
NvU32 plugDisplayMask;
NvU32 unplugDisplayMask;
} Nv2080HotplugNotification;
/* Power state changing notification information */
typedef struct {
NvBool bSwitchToAC;
NvBool bGPUCapabilityChanged;
NvU32 displayMaskAffected;
} Nv2080PowerEventNotification;
/* DP IRQ notification information */
typedef struct Nv2080DpIrqNotificationRec {
NvU32 displayId;
} Nv2080DpIrqNotification;
/* XUSB/PPC D-State change notification information */
typedef struct Nv2080DstateXusbPpcNotificationRec {
NvU32 dstateXusb;
NvU32 dstatePpc;
} Nv2080DstateXusbPpcNotification;
/* XUSB/PPC Connection status notification information */
typedef struct Nv2080XusbPpcConnectStateNotificationRec {
NvBool bConnected;
} Nv2080XusbPpcConnectStateNotification;
/* ACPI event notification information */
typedef struct Nv2080ACPIEvent {
NvU32 event;
} Nv2080ACPIEvent;
/* Cooler Zone notification information */
typedef struct _NV2080_COOLER_DIAG_ZONE_NOTIFICATION_REC {
NvU32 currentZone;
} NV2080_COOLER_DIAG_ZONE_NOTIFICATION_REC;
/* Thermal Zone notification information */
typedef struct _NV2080_THERM_DIAG_ZONE_NOTIFICATION_REC {
NvU32 currentZone;
} NV2080_THERM_DIAG_ZONE_NOTIFICATION_REC;
/* HDCP ref count change notification information */
typedef struct Nv2080AudioHdcpRequestRec {
NvU32 displayId;
NvU32 requestedState;
} Nv2080AudioHdcpRequest;
/* Gpu ready event information */
typedef struct Nv2080GC5GpuReadyParams {
NvU32 event;
NvU32 sciIntr0;
NvU32 sciIntr1;
} Nv2080GC5GpuReadyParams;
/* Priv reg access fault notification information */
typedef struct {
NvU32 errAddr;
} Nv2080PrivRegAccessFaultNotification;
/* HDA D-State change notification information
* See @HDACODEC_DSTATE for definitions
*/
typedef struct Nv2080DstateHdaCodecNotificationRec {
NvU32 dstateHdaCodec;
} Nv2080DstateHdaCodecNotification;
/*
* Platform Power Mode event information
*/
typedef struct _NV2080_PLATFORM_POWER_MODE_CHANGE_STATUS {
NvU8 platformPowerModeIndex;
NvU8 platformPowerModeMask;
NvU8 eventReason;
} NV2080_PLATFORM_POWER_MODE_CHANGE_STATUS;
#define NV2080_PLATFORM_POWER_MODE_CHANGE_INFO_INDEX 7:0
#define NV2080_PLATFORM_POWER_MODE_CHANGE_INFO_MASK 15:8
#define NV2080_PLATFORM_POWER_MODE_CHANGE_INFO_REASON 23:16
/*
* ENGINE_INFO_TYPE_NV2080 of the engine for which the QOS interrupt has been raised
*/
typedef struct {
NvU32 engineType;
} Nv2080QosIntrNotification;
typedef struct {
NvU64 physAddress NV_ALIGN_BYTES(8);
} Nv2080EccDbeNotification;
/*
* LPWR DIFR Prefetch Request - Size of L2 Cache
*/
typedef struct {
NvU32 l2CacheSize;
} Nv2080LpwrDifrPrefetchNotification;
/*
* Nvlink Link status change Notification
*/
typedef struct {
NvU32 GpuId;
NvU32 linkId;
} Nv2080NvlinkLnkChangeNotification;
#ifdef __cplusplus
}; /* extern "C" */
#endif
#endif /* _cl2080_notification_h_ */

29
src/common/sdk/nvidia/inc/class/cl2081.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2021-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -20,24 +20,21 @@
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _cl2081_h_
#define _cl2081_h_
#ifdef __cplusplus
extern "C" {
#endif
#pragma once
#include "nvtypes.h"
#include <nvtypes.h>
#define NV2081_BINAPI (0x00002081)
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: class/cl2081.finn
//
typedef struct{
NvU32 reserved;
}NV2081_ALLOC_PARAMETERS;
#define NV2081_BINAPI (0x2081U) /* finn: Evaluated from "NV2081_ALLOC_PARAMETERS_MESSAGE_ID" */
#ifdef __cplusplus
}; /* extern "C" */
#endif
#define NV2081_ALLOC_PARAMETERS_MESSAGE_ID (0x2081U)
typedef struct NV2081_ALLOC_PARAMETERS {
NvU32 reserved;
} NV2081_ALLOC_PARAMETERS;
#endif

27
src/common/sdk/nvidia/inc/class/cl2082.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2021-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -21,23 +21,20 @@
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _cl2082_h_
#define _cl2082_h_
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#include <nvtypes.h>
#include "nvtypes.h"
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: class/cl2082.finn
//
#define NV2082_BINAPI_PRIVILEGED (0x00002082)
#define NV2082_BINAPI_PRIVILEGED (0x2082U) /* finn: Evaluated from "NV2082_ALLOC_PARAMETERS_MESSAGE_ID" */
typedef struct{
NvU32 reserved;
}NV2082_ALLOC_PARAMETERS;
#define NV2082_ALLOC_PARAMETERS_MESSAGE_ID (0x2082U)
#ifdef __cplusplus
}; /* extern "C" */
#endif
typedef struct NV2082_ALLOC_PARAMETERS {
NvU32 reserved;
} NV2082_ALLOC_PARAMETERS;
#endif

2
src/common/sdk/nvidia/inc/class/cl30f1.h
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@@ -33,7 +33,7 @@
#include "cl30f1_notification.h"
/* class NV30_GSYNC */
#define NV30_GSYNC (0x000030F1)
#define NV30_GSYNC (0x30f1U) /* finn: Evaluated from "NV30F1_ALLOC_PARAMETERS_MESSAGE_ID" */
#define NV30F1_GSYNC_CONNECTOR_ONE (0)
#define NV30F1_GSYNC_CONNECTOR_TWO (1)

2
src/common/sdk/nvidia/inc/class/cl503b.h
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@@ -31,7 +31,7 @@
// Source file: class/cl503b.finn
//
#define NV50_P2P (0x0000503b)
#define NV50_P2P (0x503bU) /* finn: Evaluated from "NV503B_ALLOC_PARAMETERS_MESSAGE_ID" */
#define NV503B_FLAGS_P2P_TYPE 0:0
#define NV503B_FLAGS_P2P_TYPE_GPA 0

2
src/common/sdk/nvidia/inc/class/cl503c.h
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@@ -31,7 +31,7 @@
// Source file: class/cl503c.finn
//
#define NV50_THIRD_PARTY_P2P (0x0000503c)
#define NV50_THIRD_PARTY_P2P (0x503cU) /* finn: Evaluated from "NV503C_ALLOC_PARAMETERS_MESSAGE_ID" */
/* NvRmAlloc parameters */
#define NV503C_ALLOC_PARAMETERS_MESSAGE_ID (0x503cU)

5
src/common/sdk/nvidia/inc/class/cl5070.h
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@@ -1,5 +1,6 @@
/*
* Copyright (c) 1993-2022, NVIDIA CORPORATION. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -31,7 +32,7 @@
#include "cl5070_notification.h"
#define NV50_DISPLAY (0x00005070)
#define NV50_DISPLAY (0x5070U) /* finn: Evaluated from "NV5070_ALLOCATION_PARAMETERS_MESSAGE_ID" */
#define NV5070_ALLOCATION_PARAMETERS_MESSAGE_ID (0x5070U)

3
src/common/sdk/nvidia/inc/class/cl5070_notification.h
View File

@@ -1,5 +1,6 @@
/*
* Copyright (c) 2022, NVIDIA CORPORATION. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),

2
src/common/sdk/nvidia/inc/class/cl5080.h
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@@ -32,7 +32,7 @@
#include "cl5080_notification.h"
#define NV50_DEFERRED_API_CLASS (0x00005080)
#define NV50_DEFERRED_API_CLASS (0x5080U) /* finn: Evaluated from "NV5080_ALLOC_PARAMS_MESSAGE_ID" */
/* NvRmAlloc parameters */
#define NV5080_ALLOC_PARAMS_MESSAGE_ID (0x5080U)

3
src/common/sdk/nvidia/inc/class/cl83de.h
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@@ -30,7 +30,7 @@
// Source file: class/cl83de.finn
//
#define GT200_DEBUGGER (0x000083de)
#define GT200_DEBUGGER (0x83deU) /* finn: Evaluated from "NV83DE_ALLOC_PARAMETERS_MESSAGE_ID" */
/*
* Creating the GT200_DEBUGGER object:
@@ -53,3 +53,4 @@ typedef struct NV83DE_ALLOC_PARAMETERS {
NvHandle hAppClient;
NvHandle hClass3dObject;
} NV83DE_ALLOC_PARAMETERS;

162
src/common/sdk/nvidia/inc/class/cl84a0.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2001-2014 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2001-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -21,14 +21,16 @@
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _cl84A0_h_
#define _cl84A0_h_
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#include <nvtypes.h>
#include "nvtypes.h"
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: class/cl84a0.finn
//
#include "cl84a0_deprecated.h"
/*
* Class definitions for creating a memory descriptor from a list of page numbers
@@ -40,14 +42,14 @@ extern "C" {
*/
/* List of system memory physical page numbers */
#define NV01_MEMORY_LIST_SYSTEM (0x00000081)
#define NV01_MEMORY_LIST_SYSTEM (0x00000081)
/* List of frame buffer physical page numbers */
#define NV01_MEMORY_LIST_FBMEM (0x00000082)
#define NV01_MEMORY_LIST_FBMEM (0x00000082)
/* List of page numbers relative to the start of the specified object */
#define NV01_MEMORY_LIST_OBJECT (0x00000083)
#define NV01_MEMORY_LIST_OBJECT (0x00000083)
/*
* List structure of NV01_MEMORY_LIST_* classes
* List structure of NV01_MEMORY_LIST_* classes
*
* The pageNumber array is variable in length, with pageCount elements,
* so the allocated size of the structure must reflect that.
@@ -56,103 +58,53 @@ extern "C" {
* NV01_MEMORY_LIST_OBJECT when the underlying object is
* FBMEM (must be zero for other cases)
*
* Nv01MemoryList is deprecated. NV_MEMORY_LIST_ALLOCATION_PARAMS should be used
* instead.
*/
typedef struct Nv01MemoryListRec {
NvHandle hClient; /* client to which object belongs
* (may differ from client creating the mapping).
* May be NV01_NULL_OBJECT, in which case client
* handle is used */
NvHandle hParent; /* device with which object is associated.
* Must be NV01_NULL_OBJECT if hClient is NV01_NULL_OBJECT.
* Must not be NV01_NULL_OBJECT if hClient is
* not NV01_NULL_OBJECT. */
NvHandle hObject; /* object to which pages are relative
* (NV01_NULL_OBJECT for NV01_MEMORY_LIST_SYSTEM
* and NV01_MEMORY_LIST_FBMEM) */
NvHandle hHwResClient;/* client associated with the backdoor vnc surface*/
NvHandle hHwResDevice;/* device associated to the bacdoor vnc surface*/
NvHandle hHwResHandle;/* handle to hardware resources allocated to
* backdoor vnc surface*/
NvU32 pteAdjust; /* offset of data in first page */
NvU32 type; /* FBMEM: NVOS32_TYPE_* */
NvU32 flags; /* FBMEM: NVOS32_ALLOC_FLAGS_* */
NvU32 attr; /* FBMEM: NVOS32_ATTR_* */
NvU32 attr2; /* FBMEM: NVOS32_ATTR2_* */
NvU32 height; /* FBMEM: height in pixels */
NvU32 width; /* FBMEM: width in pixels */
NvU32 format; /* FBMEM: memory kind */
NvU32 comprcovg; /* FBMEM: compression coverage */
NvU32 zcullcovg; /* FBMEM: Z-cull coverage */
NvU32 pageCount; /* count of elements in pageNumber array */
NvU32 heapOwner; /* heap owner information from client */
NvU32 reserved_1; /* reserved: must be 0 */
NvU64 NV_DECLARE_ALIGNED(guestId,8);
/* ID of the guest VM. e.g., domain ID in case of Xen */
NvU64 NV_DECLARE_ALIGNED(rangeBegin,8);
/* preferred VA range start address */
NvU64 NV_DECLARE_ALIGNED(rangeEnd,8);
/* preferred VA range end address */
NvU32 pitch;
NvU32 ctagOffset;
NvU64 size;
NvU64 align;
NvU64 pageNumber[1]; /* variable length array of page numbers */
} Nv01MemoryList;
/*
* NV_MEMORY_LIST_ALLOCATION_PARAMS - Allocation params to create memory list
* through NvRmAlloc.
*/
typedef struct
{
NvHandle hClient; /* client to which object belongs
* (may differ from client creating the mapping).
* May be NV01_NULL_OBJECT, in which case client
* handle is used */
NvHandle hParent; /* device with which object is associated.
* Must be NV01_NULL_OBJECT if hClient is NV01_NULL_OBJECT.
* Must not be NV01_NULL_OBJECT if hClient is
* not NV01_NULL_OBJECT. */
NvHandle hObject; /* object to which pages are relative
* (NV01_NULL_OBJECT for NV01_MEMORY_LIST_SYSTEM
* and NV01_MEMORY_LIST_FBMEM) */
NvHandle hHwResClient;/* client associated with the backdoor vnc surface*/
NvHandle hHwResDevice;/* device associated to the bacdoor vnc surface*/
NvHandle hHwResHandle;/* handle to hardware resources allocated to
* backdoor vnc surface*/
NvU32 pteAdjust; /* offset of data in first page */
NvU32 reserved_0; /* reserved: must be 0 */
NvU32 type; /* FBMEM: NVOS32_TYPE_* */
NvU32 flags; /* FBMEM: NVOS32_ALLOC_FLAGS_* */
NvU32 attr; /* FBMEM: NVOS32_ATTR_* */
NvU32 attr2; /* FBMEM: NVOS32_ATTR2_* */
NvU32 height; /* FBMEM: height in pixels */
NvU32 width; /* FBMEM: width in pixels */
NvU32 format; /* FBMEM: memory kind */
NvU32 comprcovg; /* FBMEM: compression coverage */
NvU32 zcullcovg; /* FBMEM: Z-cull coverage */
NvU32 pageCount; /* count of elements in pageNumber array */
NvU32 heapOwner; /* heap owner information from client */
#define NV_MEMORY_LIST_ALLOCATION_PARAMS_MESSAGE_ID (0x84a0U)
NvU64 NV_DECLARE_ALIGNED(guestId,8);
/* ID of the guest VM. e.g., domain ID in case of Xen */
NvU64 NV_DECLARE_ALIGNED(rangeBegin,8);
/* preferred VA range start address */
NvU64 NV_DECLARE_ALIGNED(rangeEnd,8);
/* preferred VA range end address */
NvU32 pitch;
NvU32 ctagOffset;
NvU64 size;
NvU64 align;
NvP64 pageNumberList NV_ALIGN_BYTES(8);
NvU64 limit NV_ALIGN_BYTES(8);
NvU32 flagsOs02;
typedef struct NV_MEMORY_LIST_ALLOCATION_PARAMS {
NvHandle hClient; /* client to which object belongs
* (may differ from client creating the mapping).
* May be NV01_NULL_OBJECT, in which case client
* handle is used */
NvHandle hParent; /* device with which object is associated.
* Must be NV01_NULL_OBJECT if hClient is NV01_NULL_OBJECT.
* Must not be NV01_NULL_OBJECT if hClient is
* not NV01_NULL_OBJECT. */
NvHandle hObject; /* object to which pages are relative
* (NV01_NULL_OBJECT for NV01_MEMORY_LIST_SYSTEM
* and NV01_MEMORY_LIST_FBMEM) */
NvHandle hHwResClient; /* client associated with the backdoor vnc surface*/
NvHandle hHwResDevice; /* device associated to the bacdoor vnc surface*/
NvHandle hHwResHandle; /* handle to hardware resources allocated to
* backdoor vnc surface*/
NvU32 pteAdjust; /* offset of data in first page */
NvU32 reserved_0; /* reserved: must be 0 */
NvU32 type; /* FBMEM: NVOS32_TYPE_* */
NvU32 flags; /* FBMEM: NVOS32_ALLOC_FLAGS_* */
NvU32 attr; /* FBMEM: NVOS32_ATTR_* */
NvU32 attr2; /* FBMEM: NVOS32_ATTR2_* */
NvU32 height; /* FBMEM: height in pixels */
NvU32 width; /* FBMEM: width in pixels */
NvU32 format; /* FBMEM: memory kind */
NvU32 comprcovg; /* FBMEM: compression coverage */
NvU32 zcullcovg; /* FBMEM: Z-cull coverage */
NvU32 pageCount; /* count of elements in pageNumber array */
NvU32 heapOwner; /* heap owner information from client */
NV_DECLARE_ALIGNED(NvU64 guestId, 8);
/* ID of the guest VM. e.g., domain ID in case of Xen */
NV_DECLARE_ALIGNED(NvU64 rangeBegin, 8);
/* preferred VA range start address */
NV_DECLARE_ALIGNED(NvU64 rangeEnd, 8);
/* preferred VA range end address */
NvU32 pitch;
NvU32 ctagOffset;
NV_DECLARE_ALIGNED(NvU64 size, 8);
NV_DECLARE_ALIGNED(NvU64 align, 8);
NV_DECLARE_ALIGNED(NvP64 pageNumberList, 8);
NV_DECLARE_ALIGNED(NvU64 limit, 8);
NvU32 flagsOs02;
} NV_MEMORY_LIST_ALLOCATION_PARAMS;
#ifdef __cplusplus
}; /* extern "C" */
#endif
#endif /* _cl84A0_h_ */

90
src/common/sdk/nvidia/inc/class/cl84a0_deprecated.h Normal file
View File

@@ -0,0 +1,90 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _cl84a0_deprecated_h_
#define _cl84a0_deprecated_h_
#ifdef __cplusplus
extern "C" {
#endif
/*
* List structure of NV01_MEMORY_LIST_* classes
*
* The pageNumber array is variable in length, with pageCount elements,
* so the allocated size of the structure must reflect that.
*
* FBMEM items apply only to NV01_MEMORY_LIST_FBMEM and to
* NV01_MEMORY_LIST_OBJECT when the underlying object is
* FBMEM (must be zero for other cases)
*
* Nv01MemoryList is deprecated. NV_MEMORY_LIST_ALLOCATION_PARAMS should be used
* instead.
*/
typedef struct Nv01MemoryListRec {
NvHandle hClient; /* client to which object belongs
* (may differ from client creating the mapping).
* May be NV01_NULL_OBJECT, in which case client
* handle is used */
NvHandle hParent; /* device with which object is associated.
* Must be NV01_NULL_OBJECT if hClient is NV01_NULL_OBJECT.
* Must not be NV01_NULL_OBJECT if hClient is
* not NV01_NULL_OBJECT. */
NvHandle hObject; /* object to which pages are relative
* (NV01_NULL_OBJECT for NV01_MEMORY_LIST_SYSTEM
* and NV01_MEMORY_LIST_FBMEM) */
NvHandle hHwResClient;/* client associated with the backdoor vnc surface*/
NvHandle hHwResDevice;/* device associated to the bacdoor vnc surface*/
NvHandle hHwResHandle;/* handle to hardware resources allocated to
* backdoor vnc surface*/
NvU32 pteAdjust; /* offset of data in first page */
NvU32 type; /* FBMEM: NVOS32_TYPE_* */
NvU32 flags; /* FBMEM: NVOS32_ALLOC_FLAGS_* */
NvU32 attr; /* FBMEM: NVOS32_ATTR_* */
NvU32 attr2; /* FBMEM: NVOS32_ATTR2_* */
NvU32 height; /* FBMEM: height in pixels */
NvU32 width; /* FBMEM: width in pixels */
NvU32 format; /* FBMEM: memory kind */
NvU32 comprcovg; /* FBMEM: compression coverage */
NvU32 zcullcovg; /* FBMEM: Z-cull coverage */
NvU32 pageCount; /* count of elements in pageNumber array */
NvU32 heapOwner; /* heap owner information from client */
NvU32 reserved_1; /* reserved: must be 0 */
NvU64 NV_DECLARE_ALIGNED(guestId,8);
/* ID of the guest VM. e.g., domain ID in case of Xen */
NvU64 NV_DECLARE_ALIGNED(rangeBegin,8);
/* preferred VA range start address */
NvU64 NV_DECLARE_ALIGNED(rangeEnd,8);
/* preferred VA range end address */
NvU32 pitch;
NvU32 ctagOffset;
NvU64 size;
NvU64 align;
NvU64 pageNumber[1]; /* variable length array of page numbers */
} Nv01MemoryList;
#ifdef __cplusplus
}; /* extern "C" */
#endif
#endif /* _cl84a0_deprecated_h_ */

32
src/common/sdk/nvidia/inc/class/cl9010.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2016-2019, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2016-2022, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -19,21 +19,27 @@
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef SDK_CL9010_H
#define SDK_CL9010_H
#include "nvtypes.h"
#pragma once
#define NV9010_VBLANK_CALLBACK 0x9010
#include <nvtypes.h>
typedef void (*OSVBLANKCALLBACKPROC)(void * pParm1, void * pParm2);
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: class/cl9010.finn
//
typedef struct
{
OSVBLANKCALLBACKPROC pProc; // Routine to call at vblank time
NvV32 LogicalHead; // Logical Head
void *pParm1; // pParm1
void *pParm2; // pParm2
#include "class/cl9010_callback.h"
#define NV9010_VBLANK_CALLBACK (0x9010U) /* finn: Evaluated from "NV_VBLANK_CALLBACK_ALLOCATION_PARAMETERS_MESSAGE_ID" */
#define NV_VBLANK_CALLBACK_ALLOCATION_PARAMETERS_MESSAGE_ID (0x9010U)
typedef struct NV_VBLANK_CALLBACK_ALLOCATION_PARAMETERS {
NV_DECLARE_ALIGNED(NvP64 pProc, 8); // Routine to call at vblank time
// A function pointer of OSVBLANKCALLBACKPROC
NvV32 LogicalHead; // Logical Head
NV_DECLARE_ALIGNED(NvP64 pParm1, 8); // pParm1
NV_DECLARE_ALIGNED(NvP64 pParm2, 8); // pParm2
} NV_VBLANK_CALLBACK_ALLOCATION_PARAMETERS;
#endif // SDK_CL9010_H

21
src/common/sdk/nvidia/inc/class/cla297.h → src/common/sdk/nvidia/inc/class/cl9010_callback.h
View File

@@ -1,6 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
* Copyright (c) 2022, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -9,26 +8,20 @@
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef SDK_CL9010_CALLBACK_H
#define SDK_CL9010_CALLBACK_H
#ifndef _cl_kepler_c_h_
#define _cl_kepler_c_h_
typedef void (*OSVBLANKCALLBACKPROC)(NvP64 pParm1, NvP64 pParm2);
/* AUTO GENERATED FILE -- DO NOT EDIT */
/* Command: ../../class/bin/sw_header.pl kepler_c */
#include "nvtypes.h"
#define KEPLER_C 0xA297
#endif /* _cl_kepler_c_h_ */
#endif // SDK_CL9010_CALLBACK_H

2
src/common/sdk/nvidia/inc/class/cl9072.h
View File

@@ -32,7 +32,7 @@
#include "cl9072_notification.h"
#define GF100_DISP_SW 0x00009072
#define GF100_DISP_SW (0x9072U) /* finn: Evaluated from "NV9072_ALLOCATION_PARAMETERS_MESSAGE_ID" */
#define NV9072_ALLOCATION_PARAMETERS_MESSAGE_ID (0x9072U)

3815
src/common/sdk/nvidia/inc/class/cl9097.h Normal file
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File diff suppressed because it is too large Load Diff

377
src/common/sdk/nvidia/inc/class/cl90cd.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2017-2017 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2017-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -21,158 +21,158 @@
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _cl90cd_h_
#define _cl90cd_h_
/*
* NV_EVENT_BUFFER
* An event buffer is shared between user (RO) and kernel(RW).
* It holds debug/profile event data provided by the kernel.
*
*/
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: class/cl90cd.finn
//
#define NV_EVENT_BUFFER (0x90cdU) /* finn: Evaluated from "NV_EVENT_BUFFER_ALLOC_PARAMETERS_MESSAGE_ID" */
/*
* NV_EVENT_BUFFER
* An event buffer is shared between user (RO) and kernel(RW).
* It holds debug/profile event data provided by the kernel.
*
*/
#define NV_EVENT_BUFFER (0x000090CD)
/*
* NV_EVENT_BUFFER_HEADER
* This structure holds the get and put values used to index/consume event buffer.
* Along with other RO data shared with the user.
*
* recordGet/Put: These "pointers" work in the traditional sense:
* - when GET==PUT, the fifo is empty
* - when GET==PUT+1, the fifo is full
* This implies a full fifo always has one "wasted" element.
*
* recordCount: This is the total number of records added to the buffer by the kernel
* This information is filled out when the buffer is setup to keep newest records.
* recordCount = number of records currently in the buffer + overflow count.
*
* recordDropcount: This is the number of event records that are dropped because the
* buffer is full.
* This information is filled out when event buffer is setup to keep oldest records.
*
* vardataDropcount: Event buffer provides a dual stream of data, where the record can contain
* an optional offset to a variable length data buffer.
* This is the number of variable data records that are dropped because the
* buffer is full.
* This information is filled out when event buffer is setup to keep oldest records.
*/
typedef struct
{
NvU32 recordGet;
NvU32 recordPut;
NvU64 recordCount;
NvU64 recordDropcount;
NvU64 vardataDropcount;
* NV_EVENT_BUFFER_HEADER
* This structure holds the get and put values used to index/consume event buffer.
* Along with other RO data shared with the user.
*
* recordGet/Put: These "pointers" work in the traditional sense:
* - when GET==PUT, the fifo is empty
* - when GET==PUT+1, the fifo is full
* This implies a full fifo always has one "wasted" element.
*
* recordCount: This is the total number of records added to the buffer by the kernel
* This information is filled out when the buffer is setup to keep newest records.
* recordCount = number of records currently in the buffer + overflow count.
*
* recordDropcount: This is the number of event records that are dropped because the
* buffer is full.
* This information is filled out when event buffer is setup to keep oldest records.
*
* vardataDropcount: Event buffer provides a dual stream of data, where the record can contain
* an optional offset to a variable length data buffer.
* This is the number of variable data records that are dropped because the
* buffer is full.
* This information is filled out when event buffer is setup to keep oldest records.
*/
typedef struct NV_EVENT_BUFFER_HEADER {
NvU32 recordGet;
NvU32 recordPut;
NV_DECLARE_ALIGNED(NvU64 recordCount, 8);
NV_DECLARE_ALIGNED(NvU64 recordDropcount, 8);
NV_DECLARE_ALIGNED(NvU64 vardataDropcount, 8);
} NV_EVENT_BUFFER_HEADER;
/*
* NV_EVENT_BUFFER_RECORD_HEADER
* This is the header added to each event record.
* This helps identify the event type and variable length data is associated with it.
*/
typedef struct
{
NvU16 type;
NvU16 subtype;
NvU32 varData; // [31: 5] = (varDataOffset >> 5); 0 < vardataOffset <= vardataBufferSize
// [ 4: 1] = reserved for future use
// [ 0: 0] = isVardataStartOffsetZero
* NV_EVENT_BUFFER_RECORD_HEADER
* This is the header added to each event record.
* This helps identify the event type and variable length data is associated with it.
*/
typedef struct NV_EVENT_BUFFER_RECORD_HEADER {
NvU16 type;
NvU16 subtype;
NvU32 varData; // [31: 5] = (varDataOffset >> 5); 0 < vardataOffset <= vardataBufferSize
// [ 4: 1] = reserved for future use
// [ 0: 0] = isVardataStartOffsetZero
} NV_EVENT_BUFFER_RECORD_HEADER;
/*
* NV_EVENT_BUFFER_RECORD
* This structure defines a generic event record.
* The size of this record is fixed for a given event buffer.
* It is configured by the user during allocation.
*/
typedef struct
{
* NV_EVENT_BUFFER_RECORD
* This structure defines a generic event record.
* The size of this record is fixed for a given event buffer.
* It is configured by the user during allocation.
*/
typedef struct NV_EVENT_BUFFER_RECORD {
NV_EVENT_BUFFER_RECORD_HEADER recordHeader;
NvU64 inlinePayload[1] NV_ALIGN_BYTES(8); // 1st element of the payload/data
NV_DECLARE_ALIGNED(NvU64 inlinePayload[1], 8); // 1st element of the payload/data
// Do not add more elements here, inlinePayload can contain more than one elements
} NV_EVENT_BUFFER_RECORD;
#define NV_EVENT_VARDATA_GRANULARITY 32
#define NV_EVENT_VARDATA_OFFSET_MASK (~(NV_EVENT_VARDATA_GRANULARITY - 1))
#define NV_EVENT_VARDATA_START_OFFSET_ZERO 0x01
#define NV_EVENT_VARDATA_GRANULARITY 32
#define NV_EVENT_VARDATA_OFFSET_MASK (~(NV_EVENT_VARDATA_GRANULARITY - 1))
#define NV_EVENT_VARDATA_START_OFFSET_ZERO 0x01
/*
* NV_EVENT_BUFFER_ALLOC_PARAMETERS
*
* bufferHeader [OUT]
* This is the user VA offset pointing to the base of NV_EVENT_BUFFER_HEADER.
*
* recordBuffer [OUT]
* This is the user VA offset pointing to the base of the event record buffer.
* This buffer will contain NV_EVENT_BUFFER_RECORDs added by the kernel.
*
* recordSize [IN]
* This is the size of NV_EVENT_BUFFER_RECORD used by this buffer
*
* recordCount [IN]
* This is the number of records that recordBuffer can hold.
*
* vardataBuffer [OUT]
* This is the user VA offset pointing to the base of the variable data buffer.
*
* vardataBufferSize [IN]
* Size of the variable data buffer in bytes.
*
* recordsFreeThreshold [IN]
* This is the notification threshold for the event record buffer.
* This felid specifies the number of records that the buffer can
* still hold before it gets full.
*
* vardataFreeThreshold [IN]
* This is the notification threshold for the vardata buffer.
* This felid specifies the number of bytes that the buffer can
* still hold before it gets full.
*
* notificationHandle [IN]
* When recordsFreeThreshold or vardataFreeThreshold is met, kernel will notify
* user on this handle. If notificationHandle = NULL, event notification
* is disabled. This is an OS specific notification handle.
* It is a Windows event handle or a fd pointer on Linux.
*
* hSubDevice [IN]
* An event buffer can either hold sub-device related events or system events.
* This handle specifies the sub-device to associate this buffer with.
* If this parameter is NULL, then the buffer is tied to the client instead.
*
* flags [IN]
* Set to 0 by default.
* This field can hold any future flags to configure the buffer if needed.
*
* hBufferHeader [IN]
* The backing memory object for the buffer header. Must be a NV01_MEMORY_DEVICELESS object.
* On Windows platforms, a buffer will be internally generated if hBufferHeader is 0.
*
* hRecordBuffer [IN]
* The backing memory object for the record buffer. Must be a NV01_MEMORY_DEVICELESS object.
* On Windows platforms, a buffer will be internally generated if hRecordBuffer is 0.
*
* hVardataBuffer [IN]
* The backing memory object for the vardata buffer. Must be a NV01_MEMORY_DEVICELESS object.
* On Windows platforms, a buffer will be internally generated if hVardataBuffer is 0.
*
*/
typedef struct
{
NvP64 bufferHeader NV_ALIGN_BYTES(8);
NvP64 recordBuffer NV_ALIGN_BYTES(8);
NvU32 recordSize;
NvU32 recordCount;
NvP64 vardataBuffer NV_ALIGN_BYTES(8);
NvU32 vardataBufferSize;
NvU32 recordsFreeThreshold;
NvU64 notificationHandle NV_ALIGN_BYTES(8);
NvU32 vardataFreeThreshold;
* NV_EVENT_BUFFER_ALLOC_PARAMETERS
*
* bufferHeader [OUT]
* This is the user VA offset pointing to the base of NV_EVENT_BUFFER_HEADER.
*
* recordBuffer [OUT]
* This is the user VA offset pointing to the base of the event record buffer.
* This buffer will contain NV_EVENT_BUFFER_RECORDs added by the kernel.
*
* recordSize [IN]
* This is the size of NV_EVENT_BUFFER_RECORD used by this buffer
*
* recordCount [IN]
* This is the number of records that recordBuffer can hold.
*
* vardataBuffer [OUT]
* This is the user VA offset pointing to the base of the variable data buffer.
*
* vardataBufferSize [IN]
* Size of the variable data buffer in bytes.
*
* recordsFreeThreshold [IN]
* This is the notification threshold for the event record buffer.
* This felid specifies the number of records that the buffer can
* still hold before it gets full.
*
* vardataFreeThreshold [IN]
* This is the notification threshold for the vardata buffer.
* This felid specifies the number of bytes that the buffer can
* still hold before it gets full.
*
* notificationHandle [IN]
* When recordsFreeThreshold or vardataFreeThreshold is met, kernel will notify
* user on this handle. If notificationHandle = NULL, event notification
* is disabled. This is an OS specific notification handle.
* It is a Windows event handle or a fd pointer on Linux.
*
* hSubDevice [IN]
* An event buffer can either hold sub-device related events or system events.
* This handle specifies the sub-device to associate this buffer with.
* If this parameter is NULL, then the buffer is tied to the client instead.
*
* flags [IN]
* Set to 0 by default.
* This field can hold any future flags to configure the buffer if needed.
*
* hBufferHeader [IN]
* The backing memory object for the buffer header. Must be a NV01_MEMORY_DEVICELESS object.
* On Windows platforms, a buffer will be internally generated if hBufferHeader is 0.
*
* hRecordBuffer [IN]
* The backing memory object for the record buffer. Must be a NV01_MEMORY_DEVICELESS object.
* On Windows platforms, a buffer will be internally generated if hRecordBuffer is 0.
*
* hVardataBuffer [IN]
* The backing memory object for the vardata buffer. Must be a NV01_MEMORY_DEVICELESS object.
* On Windows platforms, a buffer will be internally generated if hVardataBuffer is 0.
*
*/
#define NV_EVENT_BUFFER_ALLOC_PARAMETERS_MESSAGE_ID (0x90cdU)
typedef struct NV_EVENT_BUFFER_ALLOC_PARAMETERS {
NV_DECLARE_ALIGNED(NvP64 bufferHeader, 8);
NV_DECLARE_ALIGNED(NvP64 recordBuffer, 8);
NvU32 recordSize;
NvU32 recordCount;
NV_DECLARE_ALIGNED(NvP64 vardataBuffer, 8);
NvU32 vardataBufferSize;
NvU32 recordsFreeThreshold;
NV_DECLARE_ALIGNED(NvU64 notificationHandle, 8);
NvU32 vardataFreeThreshold;
NvHandle hSubDevice;
NvU32 flags;
NvU32 flags;
NvHandle hBufferHeader;
NvHandle hRecordBuffer;
@@ -180,65 +180,58 @@ typedef struct
} NV_EVENT_BUFFER_ALLOC_PARAMETERS;
/*
* NV_EVENT_BUFFER_BIND
* This class is used to allocate an Event Type object bound to a given event buffer.
* This allocation call associates an event type with an event buffer.
* Multiple event types can be associated with the same buffer as long as they belong to
* the same category i.e. either sub-device or system.
* When event buffer is enabled, if an event bound to this buffer occurs,
* some relevant data gets added to it.
* cl2080.h has a list of sub-device events that can be associated with a buffer
* cl0000.h has a list of system events that can be associated with a buffer
* These defines are also used in class NV01_EVENT_OS_EVENT (0x79) to get event notification
* and class NV01_EVENT_KERNEL_CALLBACK_EX (0x7E) to get kernel callbacks.
* This class extends that support to additionally get relevant data in an event buffer
*
*/
#define NV_EVENT_BUFFER_BIND (0x0000007F)
* NV_EVENT_BUFFER_BIND
* This class is used to allocate an Event Type object bound to a given event buffer.
* This allocation call associates an event type with an event buffer.
* Multiple event types can be associated with the same buffer as long as they belong to
* the same category i.e. either sub-device or system.
* When event buffer is enabled, if an event bound to this buffer occurs,
* some relevant data gets added to it.
* cl2080.h has a list of sub-device events that can be associated with a buffer
* cl0000.h has a list of system events that can be associated with a buffer
* These defines are also used in class NV01_EVENT_OS_EVENT (0x79) to get event notification
* and class NV01_EVENT_KERNEL_CALLBACK_EX (0x7E) to get kernel callbacks.
* This class extends that support to additionally get relevant data in an event buffer
*
*/
#define NV_EVENT_BUFFER_BIND (0x0000007F)
/*
* NV_EVENT_BUFFER_BIND_PARAMETERS
*
* bufferHandle [IN]
* Event buffer handle used to bind the given event type
*
* eventType [IN]
* This is one of the eventTypeIDs from cl2080.h/cl000.h
* e.g. NV2080_NOTIFIERS_PSTATE_CHANGE
*
* eventSubtype [IN]
* Event subtype for a given type of event.
* This field is optional depending on if an eventtype has a subtype.
*
* hClientTarget [IN]
* Handle of the target client whose events are to be bound to the given buffer
* e.g. context switch events can be tracked for a given client.
* This field is optional depending on the event type.
* e.g. pstate change events are per gpu but do not depend on a client.
*
* hSrcResource [IN]
* source resource handle for the event type
* e.g. channel handle: RC/context switch can be tracked for a given channel
* This field is optional depending on the event type.
* e.g. pstate change events are per gpu and cannot be sub-categorized
*
* KernelCallbackdata [IN]
* This field is reserved for KERNEL ONLY clients.
*
*/
typedef struct
{
* NV_EVENT_BUFFER_BIND_PARAMETERS
*
* bufferHandle [IN]
* Event buffer handle used to bind the given event type
*
* eventType [IN]
* This is one of the eventTypeIDs from cl2080.h/cl000.h
* e.g. NV2080_NOTIFIERS_PSTATE_CHANGE
*
* eventSubtype [IN]
* Event subtype for a given type of event.
* This field is optional depending on if an eventtype has a subtype.
*
* hClientTarget [IN]
* Handle of the target client whose events are to be bound to the given buffer
* e.g. context switch events can be tracked for a given client.
* This field is optional depending on the event type.
* e.g. pstate change events are per gpu but do not depend on a client.
*
* hSrcResource [IN]
* source resource handle for the event type
* e.g. channel handle: RC/context switch can be tracked for a given channel
* This field is optional depending on the event type.
* e.g. pstate change events are per gpu and cannot be sub-categorized
*
* KernelCallbackdata [IN]
* This field is reserved for KERNEL ONLY clients.
*
*/
typedef struct NV_EVENT_BUFFER_BIND_PARAMETERS {
NvHandle bufferHandle;
NvU16 eventType;
NvU16 eventSubtype;
NvU16 eventType;
NvU16 eventSubtype;
NvHandle hClientTarget;
NvHandle hSrcResource;
NvP64 KernelCallbackdata NV_ALIGN_BYTES(8);
NV_DECLARE_ALIGNED(NvP64 KernelCallbackdata, 8);
} NV_EVENT_BUFFER_BIND_PARAMETERS;
#ifdef __cplusplus
}; /* extern "C" */
#endif
#endif // _cl90cd_h_

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src/common/sdk/nvidia/inc/class/cl9170.h
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@@ -29,7 +29,7 @@
// Source file: class/cl9170.finn
//
#define NV9170_DISPLAY (0x00009170)
#define NV9170_DISPLAY (0x9170U) /* finn: Evaluated from "NV9170_ALLOCATION_PARAMETERS_MESSAGE_ID" */
#define NV9170_ALLOCATION_PARAMETERS_MESSAGE_ID (0x9170U)

2
src/common/sdk/nvidia/inc/class/cl9270.h
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@@ -29,7 +29,7 @@
// Source file: class/cl9270.finn
//
#define NV9270_DISPLAY (0x00009270)
#define NV9270_DISPLAY (0x9270U) /* finn: Evaluated from "NV9270_ALLOCATION_PARAMETERS_MESSAGE_ID" */
#define NV9270_ALLOCATION_PARAMETERS_MESSAGE_ID (0x9270U)

2
src/common/sdk/nvidia/inc/class/cl9470.h
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@@ -29,7 +29,7 @@
// Source file: class/cl9470.finn
//
#define NV9470_DISPLAY (0x00009470)
#define NV9470_DISPLAY (0x9470U) /* finn: Evaluated from "NV9470_ALLOCATION_PARAMETERS_MESSAGE_ID" */
#define NV9470_ALLOCATION_PARAMETERS_MESSAGE_ID (0x9470U)

2
src/common/sdk/nvidia/inc/class/cl9570.h
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@@ -29,7 +29,7 @@
// Source file: class/cl9570.finn
//
#define NV9570_DISPLAY (0x00009570)
#define NV9570_DISPLAY (0x9570U) /* finn: Evaluated from "NV9570_ALLOCATION_PARAMETERS_MESSAGE_ID" */
#define NV9570_ALLOCATION_PARAMETERS_MESSAGE_ID (0x9570U)

2
src/common/sdk/nvidia/inc/class/cl9770.h
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@@ -29,7 +29,7 @@
// Source file: class/cl9770.finn
//
#define NV9770_DISPLAY (0x00009770)
#define NV9770_DISPLAY (0x9770U) /* finn: Evaluated from "NV9770_ALLOCATION_PARAMETERS_MESSAGE_ID" */
#define NV9770_ALLOCATION_PARAMETERS_MESSAGE_ID (0x9770U)

2
src/common/sdk/nvidia/inc/class/cl9870.h
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@@ -29,7 +29,7 @@
// Source file: class/cl9870.finn
//
#define NV9870_DISPLAY (0x00009870)
#define NV9870_DISPLAY (0x9870U) /* finn: Evaluated from "NV9870_ALLOCATION_PARAMETERS_MESSAGE_ID" */
#define NV9870_ALLOCATION_PARAMETERS_MESSAGE_ID (0x9870U)

3
src/common/sdk/nvidia/inc/class/cla06fsubch.h
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@@ -25,6 +25,9 @@
#define _cla06fsubch_h_
#define NVA06F_SUBCHANNEL_2D 3
#define NVA06F_SUBCHANNEL_3D 0
#define NVA06F_SUBCHANNEL_COMPUTE 1
#define NVA06F_SUBCHANNEL_COPY_ENGINE 4
#define NVA06F_SUBCHANNEL_I2M 2
#endif // _cla06fsubch_h_

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src/common/sdk/nvidia/inc/class/cla081.h Normal file
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@@ -0,0 +1,44 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2012 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _cla081_h_
#define _cla081_h_
#ifdef __cplusplus
extern "C" {
#endif
#define NVA081_VGPU_CONFIG (0x0000a081)
/*event values*/
#define NVA081_NOTIFIERS_EVENT_VGPU_GUEST_CREATED (0)
#define NVA081_NOTIFIERS_EVENT_VGPU_GUEST_INITIALISING (1)
#define NVA081_NOTIFIERS_EVENT_VGPU_GUEST_DESTROYED (2)
#define NVA081_NOTIFIERS_MAXCOUNT (5)
#ifdef __cplusplus
}; /* extern "C" */
#endif
#endif // _cla081_h

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src/common/sdk/nvidia/inc/class/cla084.h Normal file
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/*
* SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: class/cla084.finn
//
#include "nv_vgpu_types.h"
#include "cla084_notification.h"
#define NVA084_KERNEL_HOST_VGPU_DEVICE (0xa084U) /* finn: Evaluated from "NVA084_ALLOC_PARAMETERS_MESSAGE_ID" */
#define NVA084_MAX_VMMU_SEGMENTS 384
/*
* NVA084_ALLOC_PARAMETERS
*
* This structure represents vGPU host device KERNEL object allocation parameters.
* dbdf -> domain (31:16), bus (15:8), device (7:3), function (2:0)
* gfid -> Used only when SRIOV is enabled otherwise set to 0.
* swizzId [IN/OUT] -> Used only when MIG mode is enabled otherwise set
* to NV2080_CTRL_GPU_PARTITION_ID_INVALID.
* numChannels -> Used only when SRIOV is enabled. Must be a power of 2.
* bDisableDefaultSmcExecPartRestore - If set to true, SMC default execution partition
* save/restore will not be done in host-RM
* vgpuDeviceInstanceId -> Specifies the vGPU device instance per VM to be used
* for supporting multiple vGPUs per VM.
* numGuestFbHandles -> number of guest memory handles
* guestFbHandleList -> handle list to guest memory
* hPluginHeapMemory -> plugin heap memory handle
* bDeviceProfilingEnabled -> If set to true, profiling is allowed
*/
#define NVA084_ALLOC_PARAMETERS_MESSAGE_ID (0xa084U)
typedef struct NVA084_ALLOC_PARAMETERS {
NvU32 dbdf;
NvU32 gfid;
NvU32 swizzId;
NvU32 vgpuType;
NvU32 vmPid;
NvU32 numChannels;
NvU32 numPluginChannels;
VM_ID_TYPE vmIdType;
NV_DECLARE_ALIGNED(VM_ID guestVmId, 8);
NvBool bDisableDefaultSmcExecPartRestore;
NvU32 vgpuDeviceInstanceId;
NvU32 numGuestFbHandles;
NvHandle guestFbHandleList[NVA084_MAX_VMMU_SEGMENTS];
NvHandle hPluginHeapMemory;
NV_DECLARE_ALIGNED(NvU64 ctrlBuffOffset, 8);
NvBool bDeviceProfilingEnabled;
} NVA084_ALLOC_PARAMETERS;

53
src/common/sdk/nvidia/inc/class/cla084_notification.h Normal file
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/*
* SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _cla084_notification_h_
#define _cla084_notification_h_
#ifdef __cplusplus
extern "C" {
#endif
//
// @todo: We will define the actual event values later based on the use case.
// These event values are only for Test purpose.
//
/* event values */
#define NVA084_NOTIFIERS_EVENT_VGPU_PLUGIN_TASK_BOOTLOADED (0)
#define NVA084_NOTIFIERS_EVENT_VGPU_PLUGIN_TASK_UNLOADED (1)
#define NVA084_NOTIFIERS_EVENT_VGPU_PLUGIN_TASK_CRASHED (2)
#define NVA084_NOTIFIERS_EVENT_GUEST_DRIVER_LOADED (3)
#define NVA084_NOTIFIERS_EVENT_GUEST_DRIVER_UNLOADED (4)
#define NVA084_NOTIFIERS_MAXCOUNT (5)
#define NVA084_NOTIFICATION_STATUS_IN_PROGRESS (0x8000)
#define NVA084_NOTIFICATION_STATUS_BAD_ARGUMENT (0x4000)
#define NVA084_NOTIFICATION_STATUS_ERROR_INVALID_STATE (0x2000)
#define NVA084_NOTIFICATION_STATUS_ERROR_STATE_IN_USE (0x1000)
#define NVA084_NOTIFICATION_STATUS_DONE_SUCCESS (0x0000)
#ifdef __cplusplus
}; /* extern "C" */
#endif
#endif // _cla084_notification_h_

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src/common/sdk/nvidia/inc/class/cla26f.h Normal file
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/*
* SPDX-FileCopyrightText: Copyright (c) 2001-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _cla26f_h_
#define _cla26f_h_
#ifdef __cplusplus
extern "C" {
#endif
#include "nvtypes.h"
/* class KEPLER_CHANNEL_GPFIFO */
/*
* Documentation for KEPLER_CHANNEL_GPFIFO can be found in dev_pbdma.ref,
* chapter "User Control Registers". It is documented as device NV_UDMA.
* The GPFIFO format itself is also documented in dev_pbdma.ref,
* NV_PPBDMA_GP_ENTRY_*. The pushbuffer format is documented in dev_ram.ref,
* chapter "FIFO DMA RAM", NV_FIFO_DMA_*.
*
*/
#define KEPLER_CHANNEL_GPFIFO_C (0x0000A26F)
/* pio method data structure */
typedef volatile struct _cla26f_tag0 {
NvV32 Reserved00[0x7c0];
} NvA26FTypedef, KEPLER_ChannelGPFifoC;
#define NVA26F_TYPEDEF KEPLER_CHANNELChannelGPFifo
/* dma flow control data structure */
typedef volatile struct _cla26f_tag1 {
NvU32 Ignored00[0x010]; /* 0000-003f*/
NvU32 Put; /* put offset, read/write 0040-0043*/
NvU32 Get; /* get offset, read only 0044-0047*/
NvU32 Reference; /* reference value, read only 0048-004b*/
NvU32 PutHi; /* high order put offset bits 004c-004f*/
NvU32 Ignored01[0x002]; /* 0050-0057*/
NvU32 TopLevelGet; /* top level get offset, read only 0058-005b*/
NvU32 TopLevelGetHi; /* high order top level get bits 005c-005f*/
NvU32 GetHi; /* high order get offset bits 0060-0063*/
NvU32 Ignored02[0x007]; /* 0064-007f*/
NvU32 Ignored03; /* used to be engine yield 0080-0083*/
NvU32 Ignored04[0x001]; /* 0084-0087*/
NvU32 GPGet; /* GP FIFO get offset, read only 0088-008b*/
NvU32 GPPut; /* GP FIFO put offset 008c-008f*/
NvU32 Ignored05[0x5c];
} NvA26FControl, KeplerCControlGPFifo;
/* fields and values */
#define NVA26F_NUMBER_OF_SUBCHANNELS (8)
#define NVA26F_SET_OBJECT (0x00000000)
#define NVA26F_SET_OBJECT_NVCLASS 15:0
#define NVA26F_SET_OBJECT_ENGINE 20:16
#define NVA26F_SET_OBJECT_ENGINE_SW 0x0000001f
#define NVA26F_ILLEGAL (0x00000004)
#define NVA26F_ILLEGAL_HANDLE 31:0
#define NVA26F_NOP (0x00000008)
#define NVA26F_NOP_HANDLE 31:0
#define NVA26F_SEMAPHOREA (0x00000010)
#define NVA26F_SEMAPHOREA_OFFSET_UPPER 7:0
#define NVA26F_SEMAPHOREB (0x00000014)
#define NVA26F_SEMAPHOREB_OFFSET_LOWER 31:2
#define NVA26F_SEMAPHOREC (0x00000018)
#define NVA26F_SEMAPHOREC_PAYLOAD 31:0
#define NVA26F_SEMAPHORED (0x0000001C)
#define NVA26F_SEMAPHORED_OPERATION 3:0
#define NVA26F_SEMAPHORED_OPERATION_ACQUIRE 0x00000001
#define NVA26F_SEMAPHORED_OPERATION_RELEASE 0x00000002
#define NVA26F_SEMAPHORED_OPERATION_ACQ_GEQ 0x00000004
#define NVA26F_SEMAPHORED_OPERATION_ACQ_AND 0x00000008
#define NVA26F_SEMAPHORED_ACQUIRE_SWITCH 12:12
#define NVA26F_SEMAPHORED_ACQUIRE_SWITCH_DISABLED 0x00000000
#define NVA26F_SEMAPHORED_ACQUIRE_SWITCH_ENABLED 0x00000001
#define NVA26F_SEMAPHORED_RELEASE_WFI 20:20
#define NVA26F_SEMAPHORED_RELEASE_WFI_EN 0x00000000
#define NVA26F_SEMAPHORED_RELEASE_WFI_DIS 0x00000001
#define NVA26F_SEMAPHORED_RELEASE_SIZE 24:24
#define NVA26F_SEMAPHORED_RELEASE_SIZE_16BYTE 0x00000000
#define NVA26F_SEMAPHORED_RELEASE_SIZE_4BYTE 0x00000001
#define NVA26F_NON_STALL_INTERRUPT (0x00000020)
#define NVA26F_NON_STALL_INTERRUPT_HANDLE 31:0
#define NVA26F_FB_FLUSH (0x00000024)
#define NVA26F_FB_FLUSH_HANDLE 31:0
#define NVA26F_MEM_OP_A (0x00000028)
#define NVA26F_MEM_OP_A_OPERAND_LOW 31:2
#define NVA26F_MEM_OP_A_TLB_INVALIDATE_ADDR 29:2
#define NVA26F_MEM_OP_A_TLB_INVALIDATE_TARGET 31:30
#define NVA26F_MEM_OP_A_TLB_INVALIDATE_TARGET_VID_MEM 0x00000000
#define NVA26F_MEM_OP_A_TLB_INVALIDATE_TARGET_SYS_MEM_COHERENT 0x00000002
#define NVA26F_MEM_OP_A_TLB_INVALIDATE_TARGET_SYS_MEM_NONCOHERENT 0x00000003
#define NVA26F_MEM_OP_B (0x0000002c)
#define NVA26F_MEM_OP_B_OPERAND_HIGH 7:0
#define NVA26F_MEM_OP_B_OPERATION 31:27
#define NVA26F_MEM_OP_B_OPERATION_SYSMEMBAR_FLUSH 0x00000005
#define NVA26F_MEM_OP_B_OPERATION_MMU_TLB_INVALIDATE 0x00000009
#define NVA26F_MEM_OP_B_OPERATION_L2_INVALIDATE_CLEAN_LINES 0x0000000e
#define NVA26F_MEM_OP_B_OPERATION_L2_CLEAN_COMPTAGS 0x0000000f
#define NVA26F_MEM_OP_B_OPERATION_L2_FLUSH_DIRTY 0x00000010
#define NVA26F_MEM_OP_B_MMU_TLB_INVALIDATE_PDB 0:0
#define NVA26F_MEM_OP_B_MMU_TLB_INVALIDATE_PDB_ONE 0x00000000
#define NVA26F_MEM_OP_B_MMU_TLB_INVALIDATE_PDB_ALL 0x00000001
#define NVA26F_MEM_OP_B_MMU_TLB_INVALIDATE_GPC 1:1
#define NVA26F_MEM_OP_B_MMU_TLB_INVALIDATE_GPC_ENABLE 0x00000000
#define NVA26F_MEM_OP_B_MMU_TLB_INVALIDATE_GPC_DISABLE 0x00000001
#define NVA26F_SET_REFERENCE (0x00000050)
#define NVA26F_SET_REFERENCE_COUNT 31:0
#define NVA26F_SYNCPOINTA (0x00000070)
#define NVA26F_SYNCPOINTA_PAYLOAD 31:0
#define NVA26F_SYNCPOINTB (0x00000074)
#define NVA26F_SYNCPOINTB_OPERATION 1:0
#define NVA26F_SYNCPOINTB_OPERATION_WAIT 0x00000000
#define NVA26F_SYNCPOINTB_OPERATION_INCR 0x00000001
#define NVA26F_SYNCPOINTB_OPERATION_BASE_ADD 0x00000002
#define NVA26F_SYNCPOINTB_OPERATION_BASE_WRITE 0x00000003
#define NVA26F_SYNCPOINTB_WAIT_SWITCH 4:4
#define NVA26F_SYNCPOINTB_WAIT_SWITCH_DIS 0x00000000
#define NVA26F_SYNCPOINTB_WAIT_SWITCH_EN 0x00000001
#define NVA26F_SYNCPOINTB_BASE 5:5
#define NVA26F_SYNCPOINTB_BASE_DIS 0x00000000
#define NVA26F_SYNCPOINTB_BASE_EN 0x00000001
#define NVA26F_SYNCPOINTB_SYNCPT_INDEX 15:8
#define NVA26F_SYNCPOINTB_BASE_INDEX 25:20
#define NVA26F_WFI (0x00000078)
#define NVA26F_WFI_HANDLE 31:0
#define NVA26F_CRC_CHECK (0x0000007c)
#define NVA26F_CRC_CHECK_VALUE 31:0
#define NVA26F_YIELD (0x00000080)
#define NVA26F_YIELD_OP 1:0
#define NVA26F_YIELD_OP_NOP 0x00000000
/* GPFIFO entry format */
#define NVA26F_GP_ENTRY__SIZE 8
#define NVA26F_GP_ENTRY0_FETCH 0:0
#define NVA26F_GP_ENTRY0_FETCH_UNCONDITIONAL 0x00000000
#define NVA26F_GP_ENTRY0_FETCH_CONDITIONAL 0x00000001
#define NVA26F_GP_ENTRY0_GET 31:2
#define NVA26F_GP_ENTRY0_OPERAND 31:0
#define NVA26F_GP_ENTRY1_GET_HI 7:0
#define NVA26F_GP_ENTRY1_PRIV 8:8
#define NVA26F_GP_ENTRY1_PRIV_USER 0x00000000
#define NVA26F_GP_ENTRY1_PRIV_KERNEL 0x00000001
#define NVA26F_GP_ENTRY1_LEVEL 9:9
#define NVA26F_GP_ENTRY1_LEVEL_MAIN 0x00000000
#define NVA26F_GP_ENTRY1_LEVEL_SUBROUTINE 0x00000001
#define NVA26F_GP_ENTRY1_LENGTH 30:10
#define NVA26F_GP_ENTRY1_SYNC 31:31
#define NVA26F_GP_ENTRY1_SYNC_PROCEED 0x00000000
#define NVA26F_GP_ENTRY1_SYNC_WAIT 0x00000001
#define NVA26F_GP_ENTRY1_OPCODE 7:0
#define NVA26F_GP_ENTRY1_OPCODE_NOP 0x00000000
#define NVA26F_GP_ENTRY1_OPCODE_ILLEGAL 0x00000001
#define NVA26F_GP_ENTRY1_OPCODE_GP_CRC 0x00000002
#define NVA26F_GP_ENTRY1_OPCODE_PB_CRC 0x00000003
/* dma method formats */
#define NVA26F_DMA_METHOD_ADDRESS_OLD 12:2
#define NVA26F_DMA_METHOD_ADDRESS 11:0
#define NVA26F_DMA_SUBDEVICE_MASK 15:4
#define NVA26F_DMA_METHOD_SUBCHANNEL 15:13
#define NVA26F_DMA_TERT_OP 17:16
#define NVA26F_DMA_TERT_OP_GRP0_INC_METHOD (0x00000000)
#define NVA26F_DMA_TERT_OP_GRP0_SET_SUB_DEV_MASK (0x00000001)
#define NVA26F_DMA_TERT_OP_GRP0_STORE_SUB_DEV_MASK (0x00000002)
#define NVA26F_DMA_TERT_OP_GRP0_USE_SUB_DEV_MASK (0x00000003)
#define NVA26F_DMA_TERT_OP_GRP2_NON_INC_METHOD (0x00000000)
#define NVA26F_DMA_METHOD_COUNT_OLD 28:18
#define NVA26F_DMA_METHOD_COUNT 28:16
#define NVA26F_DMA_IMMD_DATA 28:16
#define NVA26F_DMA_SEC_OP 31:29
#define NVA26F_DMA_SEC_OP_GRP0_USE_TERT (0x00000000)
#define NVA26F_DMA_SEC_OP_INC_METHOD (0x00000001)
#define NVA26F_DMA_SEC_OP_GRP2_USE_TERT (0x00000002)
#define NVA26F_DMA_SEC_OP_NON_INC_METHOD (0x00000003)
#define NVA26F_DMA_SEC_OP_IMMD_DATA_METHOD (0x00000004)
#define NVA26F_DMA_SEC_OP_ONE_INC (0x00000005)
#define NVA26F_DMA_SEC_OP_RESERVED6 (0x00000006)
#define NVA26F_DMA_SEC_OP_END_PB_SEGMENT (0x00000007)
/* dma incrementing method format */
#define NVA26F_DMA_INCR_ADDRESS 11:0
#define NVA26F_DMA_INCR_SUBCHANNEL 15:13
#define NVA26F_DMA_INCR_COUNT 28:16
#define NVA26F_DMA_INCR_OPCODE 31:29
#define NVA26F_DMA_INCR_OPCODE_VALUE (0x00000001)
#define NVA26F_DMA_INCR_DATA 31:0
/* dma non-incrementing method format */
#define NVA26F_DMA_NONINCR_ADDRESS 11:0
#define NVA26F_DMA_NONINCR_SUBCHANNEL 15:13
#define NVA26F_DMA_NONINCR_COUNT 28:16
#define NVA26F_DMA_NONINCR_OPCODE 31:29
#define NVA26F_DMA_NONINCR_OPCODE_VALUE (0x00000003)
#define NVA26F_DMA_NONINCR_DATA 31:0
/* dma increment-once method format */
#define NVA26F_DMA_ONEINCR_ADDRESS 11:0
#define NVA26F_DMA_ONEINCR_SUBCHANNEL 15:13
#define NVA26F_DMA_ONEINCR_COUNT 28:16
#define NVA26F_DMA_ONEINCR_OPCODE 31:29
#define NVA26F_DMA_ONEINCR_OPCODE_VALUE (0x00000005)
#define NVA26F_DMA_ONEINCR_DATA 31:0
/* dma no-operation format */
#define NVA26F_DMA_NOP (0x00000000)
/* dma immediate-data format */
#define NVA26F_DMA_IMMD_ADDRESS 11:0
#define NVA26F_DMA_IMMD_SUBCHANNEL 15:13
#define NVA26F_DMA_IMMD_DATA 28:16
#define NVA26F_DMA_IMMD_OPCODE 31:29
#define NVA26F_DMA_IMMD_OPCODE_VALUE (0x00000004)
/* dma set sub-device mask format */
#define NVA26F_DMA_SET_SUBDEVICE_MASK_VALUE 15:4
#define NVA26F_DMA_SET_SUBDEVICE_MASK_OPCODE 31:16
#define NVA26F_DMA_SET_SUBDEVICE_MASK_OPCODE_VALUE (0x00000001)
/* dma store sub-device mask format */
#define NVA26F_DMA_STORE_SUBDEVICE_MASK_VALUE 15:4
#define NVA26F_DMA_STORE_SUBDEVICE_MASK_OPCODE 31:16
#define NVA26F_DMA_STORE_SUBDEVICE_MASK_OPCODE_VALUE (0x00000002)
/* dma use sub-device mask format */
#define NVA26F_DMA_USE_SUBDEVICE_MASK_OPCODE 31:16
#define NVA26F_DMA_USE_SUBDEVICE_MASK_OPCODE_VALUE (0x00000003)
/* dma end-segment format */
#define NVA26F_DMA_ENDSEG_OPCODE 31:29
#define NVA26F_DMA_ENDSEG_OPCODE_VALUE (0x00000007)
/* dma legacy incrementing/non-incrementing formats */
#define NVA26F_DMA_ADDRESS 12:2
#define NVA26F_DMA_SUBCH 15:13
#define NVA26F_DMA_OPCODE3 17:16
#define NVA26F_DMA_OPCODE3_NONE (0x00000000)
#define NVA26F_DMA_COUNT 28:18
#define NVA26F_DMA_OPCODE 31:29
#define NVA26F_DMA_OPCODE_METHOD (0x00000000)
#define NVA26F_DMA_OPCODE_NONINC_METHOD (0x00000002)
#define NVA26F_DMA_DATA 31:0
#ifdef __cplusplus
}; /* extern "C" */
#endif
#endif /* _cla26f_h_ */

28
src/common/sdk/nvidia/inc/class/clb069sw.h
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@@ -1,5 +1,5 @@
/*******************************************************************************
Copyright (c) 2008-2013 NVIDIA Corporation
Copyright (c) 2008-2022 NVIDIA Corporation
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to
@@ -21,26 +21,18 @@
*******************************************************************************/
#include "nvtypes.h"
#pragma once
#ifndef _clb069_sw_h_
#define _clb069_sw_h_
#include <nvtypes.h>
#ifdef __cplusplus
extern "C" {
#endif
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: class/clb069sw.finn
//
/* This file is *not* auto-generated. */
typedef struct
{
NvU32 flags; // set to 0
#define NVB069_ALLOCATION_PARAMETERS_MESSAGE_ID (0xb069U)
typedef struct NVB069_ALLOCATION_PARAMETERS {
NvU32 flags; // set to 0
} NVB069_ALLOCATION_PARAMETERS;
#ifdef __cplusplus
}; /* extern "C" */
#endif
#endif // _clb096_sw_h

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src/common/sdk/nvidia/inc/class/clb097.h
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src/common/sdk/nvidia/inc/class/clb097tex.h Normal file
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32
src/common/sdk/nvidia/inc/class/clb0b5sw.h
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@@ -21,38 +21,34 @@
* DEALINGS IN THE SOFTWARE.
*/
#include "nvtypes.h"
#pragma once
#ifndef _clb0b5sw_h_
#define _clb0b5sw_h_
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: class/clb0b5sw.finn
//
#ifdef __cplusplus
extern "C" {
#endif
/* This file is *not* auto-generated. */
//
// Using VERSION_0 will cause the API to interpret
// engineType as a CE engine instance. This allows
// for backward compatibility with 85B5sw and 90B5sw.
//
#define NVB0B5_ALLOCATION_PARAMETERS_VERSION_0 0
#define NVB0B5_ALLOCATION_PARAMETERS_VERSION_0 0
//
// Using VERSION_1 will cause the API to interpret
// engineType as an NV2080_ENGINE_TYPE ordinal.
//
#define NVB0B5_ALLOCATION_PARAMETERS_VERSION_1 1
#define NVB0B5_ALLOCATION_PARAMETERS_VERSION_1 1
typedef struct
{
NvU32 version;
NvU32 engineType;
#define NVB0B5_ALLOCATION_PARAMETERS_MESSAGE_ID (0xb0b5U)
typedef struct NVB0B5_ALLOCATION_PARAMETERS {
NvU32 version;
NvU32 engineType;
} NVB0B5_ALLOCATION_PARAMETERS;
#ifdef __cplusplus
}; /* extern "C" */
#endif
#endif // _clb0b5sw_h_

4181
src/common/sdk/nvidia/inc/class/clb197.h
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23
src/common/sdk/nvidia/inc/class/clb2cc.h
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@@ -21,22 +21,26 @@
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _clb2cc_h_
#define _clb2cc_h_
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: class/clb2cc.finn
//
#include "clb0cc.h"
#define MAXWELL_PROFILER_DEVICE (0x0000B2CC)
#define MAXWELL_PROFILER_DEVICE (0xb2ccU) /* finn: Evaluated from "NVB2CC_ALLOC_PARAMETERS_MESSAGE_ID" */
/*
* Creating the MAXWELL_PROFILER_DEVICE object:
* - The profiler object is instantiated as a child of subdevice.
*/
typedef struct {
#define NVB2CC_ALLOC_PARAMETERS_MESSAGE_ID (0xb2ccU)
typedef struct NVB2CC_ALLOC_PARAMETERS {
/*
* This parameter specifies the handle of the client that owns the context
* specified by hContextTarget. This can set it to 0 where a context
@@ -54,8 +58,3 @@ typedef struct {
NvHandle hContextTarget;
} NVB2CC_ALLOC_PARAMETERS;
#ifdef __cplusplus
}; /* extern "C" */
#endif
#endif /* _clb2cc_h_ */

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src/common/sdk/nvidia/inc/class/clc097.h
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src/common/sdk/nvidia/inc/class/clc097tex.h Normal file
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34
src/common/sdk/nvidia/inc/class/clc0b5sw.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2014-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2014-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -21,38 +21,34 @@
* DEALINGS IN THE SOFTWARE.
*/
#include "nvtypes.h"
#pragma once
#ifndef _clc0b5sw_h_
#define _clc0b5sw_h_
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: class/clc0b5sw.finn
//
#ifdef __cplusplus
extern "C" {
#endif
/* This file is *not* auto-generated. */
//
// Using VERSION_0 will cause the API to interpret
// engineType as a CE engine instance. This allows
// for backward compatibility with 85B5sw and 90B5sw.
//
#define NVC0B5_ALLOCATION_PARAMETERS_VERSION_0 0
#define NVC0B5_ALLOCATION_PARAMETERS_VERSION_0 0
//
// Using VERSION_1 will cause the API to interpret
// engineType as an NV2080_ENGINE_TYPE ordinal.
//
#define NVC0B5_ALLOCATION_PARAMETERS_VERSION_1 1
#define NVC0B5_ALLOCATION_PARAMETERS_VERSION_1 1
typedef struct
{
NvU32 version;
NvU32 engineType;
#define NVC0B5_ALLOCATION_PARAMETERS_MESSAGE_ID (0xc0b5U)
typedef struct NVC0B5_ALLOCATION_PARAMETERS {
NvU32 version;
NvU32 engineType;
} NVC0B5_ALLOCATION_PARAMETERS;
#ifdef __cplusplus
}; /* extern "C" */
#endif
#endif // _clc0b5sw_h_

4263
src/common/sdk/nvidia/inc/class/clc197.h
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34
src/common/sdk/nvidia/inc/class/clc1b5sw.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2016-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2016-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -21,38 +21,34 @@
* DEALINGS IN THE SOFTWARE.
*/
#include "nvtypes.h"
#pragma once
#ifndef _clc1b5sw_h_
#define _clc1b5sw_h_
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: class/clc1b5sw.finn
//
#ifdef __cplusplus
extern "C" {
#endif
/* This file is *not* auto-generated. */
//
// Using VERSION_0 will cause the API to interpret
// engineType as a CE engine instance. This allows
// for backward compatibility with 85B5sw and 90B5sw.
//
#define NVC1B5_ALLOCATION_PARAMETERS_VERSION_0 0
#define NVC1B5_ALLOCATION_PARAMETERS_VERSION_0 0
//
// Using VERSION_1 will cause the API to interpret
// engineType as an NV2080_ENGINE_TYPE ordinal.
//
#define NVC1B5_ALLOCATION_PARAMETERS_VERSION_1 1
#define NVC1B5_ALLOCATION_PARAMETERS_VERSION_1 1
typedef struct
{
NvU32 version;
NvU32 engineType;
#define NVC1B5_ALLOCATION_PARAMETERS_MESSAGE_ID (0xc1b5U)
typedef struct NVC1B5_ALLOCATION_PARAMETERS {
NvU32 version;
NvU32 engineType;
} NVC1B5_ALLOCATION_PARAMETERS;
#ifdef __cplusplus
}; /* extern "C" */
#endif
#endif // _clc1b5sw_h_

40
src/common/sdk/nvidia/inc/class/clc370.h
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@@ -1,5 +1,5 @@
/*
* Copyright (c) 2015-2020, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2015-2022, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -20,36 +20,24 @@
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _clc370_h_
#define _clc370_h_
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#include <nvtypes.h>
#include "nvtypes.h"
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: class/clc370.finn
//
#include "class/cl5070.h"
#include "clc370_notification.h"
#define NVC370_DISPLAY (0x0000C370)
#define NVC370_DISPLAY (0xc370U) /* finn: Evaluated from "NVC370_ALLOCATION_PARAMETERS_MESSAGE_ID" */
/* event values */
#define NVC370_NOTIFIERS_SW NV5070_NOTIFIERS_SW
#define NVC370_NOTIFIERS_BEGIN NV5070_NOTIFIERS_MAXCOUNT
#define NVC370_NOTIFIERS_VPR NVC370_NOTIFIERS_BEGIN + (0)
#define NVC370_NOTIFIERS_RG_SEM_NOTIFICATION NVC370_NOTIFIERS_VPR + (1)
#define NVC370_NOTIFIERS_WIN_SEM_NOTIFICATION NVC370_NOTIFIERS_RG_SEM_NOTIFICATION + (1)
#define NVC370_NOTIFIERS_MAXCOUNT NVC370_NOTIFIERS_WIN_SEM_NOTIFICATION + (1)
#define NVC370_ALLOCATION_PARAMETERS_MESSAGE_ID (0xc370U)
typedef struct
{
NvU32 numHeads; // Number of HEADs in this chip/display
NvU32 numSors; // Number of SORs in this chip/display
NvU32 numPiors; // Number of PIORs in this chip/display
typedef struct NVC370_ALLOCATION_PARAMETERS {
NvU32 numHeads; // Number of HEADs in this chip/display
NvU32 numSors; // Number of SORs in this chip/display
NvU32 numPiors; // Number of PIORs in this chip/display
} NVC370_ALLOCATION_PARAMETERS;
#ifdef __cplusplus
}; /* extern "C" */
#endif
#endif /* _clc370_h_ */

45
src/common/sdk/nvidia/inc/class/clc370_notification.h Normal file
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@@ -0,0 +1,45 @@
/*
* Copyright (c) 2022, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _clc370_notification_h_
#define _clc370_notification_h_
#ifdef __cplusplus
extern "C" {
#endif
#include "class/cl5070.h"
/* event values */
#define NVC370_NOTIFIERS_SW NV5070_NOTIFIERS_SW
#define NVC370_NOTIFIERS_BEGIN NV5070_NOTIFIERS_MAXCOUNT
#define NVC370_NOTIFIERS_VPR NVC370_NOTIFIERS_BEGIN + (0)
#define NVC370_NOTIFIERS_RG_SEM_NOTIFICATION NVC370_NOTIFIERS_VPR + (1)
#define NVC370_NOTIFIERS_WIN_SEM_NOTIFICATION NVC370_NOTIFIERS_RG_SEM_NOTIFICATION + (1)
#define NVC370_NOTIFIERS_MAXCOUNT NVC370_NOTIFIERS_WIN_SEM_NOTIFICATION + (1)
#ifdef __cplusplus
}; /* extern "C" */
#endif
#endif /* _clc370_notification_h_ */

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src/common/sdk/nvidia/inc/class/clc397.h
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src/common/sdk/nvidia/inc/class/clc3b5sw.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2016-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2016-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -21,38 +21,34 @@
* DEALINGS IN THE SOFTWARE.
*/
#include "nvtypes.h"
#pragma once
#ifndef _clc3b5sw_h_
#define _clc3b5sw_h_
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: class/clc3b5sw.finn
//
#ifdef __cplusplus
extern "C" {
#endif
/* This file is *not* auto-generated. */
//
// Using VERSION_0 will cause the API to interpret
// engineType as a CE engine instance. This allows
// for backward compatibility with 85B5sw and 90B5sw.
//
#define NVC3B5_ALLOCATION_PARAMETERS_VERSION_0 0
#define NVC3B5_ALLOCATION_PARAMETERS_VERSION_0 0
//
// Using VERSION_1 will cause the API to interpret
// engineType as an NV2080_ENGINE_TYPE ordinal.
//
#define NVC3B5_ALLOCATION_PARAMETERS_VERSION_1 1
#define NVC3B5_ALLOCATION_PARAMETERS_VERSION_1 1
typedef struct
{
NvU32 version;
NvU32 engineType;
#define NVC3B5_ALLOCATION_PARAMETERS_MESSAGE_ID (0xc3b5U)
typedef struct NVC3B5_ALLOCATION_PARAMETERS {
NvU32 version;
NvU32 engineType;
} NVC3B5_ALLOCATION_PARAMETERS;
#ifdef __cplusplus
}; /* extern "C" */
#endif
#endif // _clc3b5sw_h_

32
src/common/sdk/nvidia/inc/class/clc570.h
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@@ -1,5 +1,5 @@
/*
* Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2017-2022, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -20,28 +20,22 @@
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _clc570_h_
#define _clc570_h_
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#include <nvtypes.h>
#include "nvtypes.h"
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: class/clc570.finn
//
#include "class/cl5070.h"
#define NVC570_DISPLAY (0xc570U) /* finn: Evaluated from "NVC570_ALLOCATION_PARAMETERS_MESSAGE_ID" */
#define NVC570_DISPLAY (0x0000C570)
#define NVC570_ALLOCATION_PARAMETERS_MESSAGE_ID (0xc570U)
typedef struct
{
NvU32 numHeads; // Number of HEADs in this chip/display
NvU32 numSors; // Number of SORs in this chip/display
NvU32 numPiors; // Number of PIORs in this chip/display
typedef struct NVC570_ALLOCATION_PARAMETERS {
NvU32 numHeads; // Number of HEADs in this chip/display
NvU32 numSors; // Number of SORs in this chip/display
NvU32 numPiors; // Number of PIORs in this chip/display
} NVC570_ALLOCATION_PARAMETERS;
#ifdef __cplusplus
}; /* extern "C" */
#endif
#endif /* _clc570_h_ */

28
src/common/sdk/nvidia/inc/class/clc574.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -21,25 +21,21 @@
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _clc574_h_
#define _clc574_h_
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#include <nvtypes.h>
#include "nvtypes.h"
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: class/clc574.finn
//
#define UVM_CHANNEL_RETAINER (0x0000C574)
#define UVM_CHANNEL_RETAINER (0xc574U) /* finn: Evaluated from "NV_UVM_CHANNEL_RETAINER_ALLOC_PARAMS_MESSAGE_ID" */
typedef struct
{
#define NV_UVM_CHANNEL_RETAINER_ALLOC_PARAMS_MESSAGE_ID (0xc574U)
typedef struct NV_UVM_CHANNEL_RETAINER_ALLOC_PARAMS {
NvHandle hClient;
NvHandle hChannel;
}NV_UVM_CHANNEL_RETAINER_ALLOC_PARAMS;
} NV_UVM_CHANNEL_RETAINER_ALLOC_PARAMS;
#ifdef __cplusplus
}; /* extern "C" */
#endif
#endif /* _clc574_h_ */

32
src/common/sdk/nvidia/inc/class/clc58b.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2017-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2017-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -21,16 +21,18 @@
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _clc58b_h_
#define _clc58b_h_
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#include <nvtypes.h>
#define TURING_VMMU_A (0x0000c58b)
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: class/clc58b.finn
//
/**
#define TURING_VMMU_A (0xc58bU) /* finn: Evaluated from "TURING_VMMU_A_ALLOCATION_PARAMETERS_MESSAGE_ID" */
/*
* @brief NvAlloc parameters for TuringVmmuA class
*
* This class represents mapping between guest physical and system physical.
@@ -38,17 +40,11 @@ extern "C" {
*
* gfid [in]
* GFID of VF
**/
*/
typedef struct
{
#define TURING_VMMU_A_ALLOCATION_PARAMETERS_MESSAGE_ID (0xc58bU)
typedef struct TURING_VMMU_A_ALLOCATION_PARAMETERS {
NvHandle hHostVgpuDevice;
} TURING_VMMU_A_ALLOCATION_PARAMETERS;
#ifdef __cplusplus
}; /* extern "C" */
#endif
#endif // _clc58b_h

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src/common/sdk/nvidia/inc/class/clc597.h
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src/common/sdk/nvidia/inc/class/clc5b5sw.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2017-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2017-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -21,38 +21,34 @@
* DEALINGS IN THE SOFTWARE.
*/
#include "nvtypes.h"
#pragma once
#ifndef _clc5b5sw_h_
#define _clc5b5sw_h_
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: class/clc5b5sw.finn
//
#ifdef __cplusplus
extern "C" {
#endif
/* This file is *not* auto-generated. */
//
// Using VERSION_0 will cause the API to interpret
// engineType as a CE engine instance. This allows
// for backward compatibility with 85B5sw and 90B5sw.
//
#define NVC5B5_ALLOCATION_PARAMETERS_VERSION_0 0
#define NVC5B5_ALLOCATION_PARAMETERS_VERSION_0 0
//
// Using VERSION_1 will cause the API to interpret
// engineType as an NV2080_ENGINE_TYPE ordinal.
//
#define NVC5B5_ALLOCATION_PARAMETERS_VERSION_1 1
#define NVC5B5_ALLOCATION_PARAMETERS_VERSION_1 1
typedef struct
{
NvU32 version;
NvU32 engineType;
#define NVC5B5_ALLOCATION_PARAMETERS_MESSAGE_ID (0xc5b5U)
typedef struct NVC5B5_ALLOCATION_PARAMETERS {
NvU32 version;
NvU32 engineType;
} NVC5B5_ALLOCATION_PARAMETERS;
#ifdef __cplusplus
}; /* extern "C" */
#endif
#endif // _clc5b5sw_h_

28
src/common/sdk/nvidia/inc/class/clc637.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2018 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2018-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -21,16 +21,16 @@
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _clc637_h_
#define _clc637_h_
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#include <nvtypes.h>
#include "nvtypes.h"
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: class/clc637.finn
//
#define AMPERE_SMC_PARTITION_REF (0x0000c637)
#define AMPERE_SMC_PARTITION_REF (0xc637U) /* finn: Evaluated from "NVC637_ALLOCATION_PARAMETERS_MESSAGE_ID" */
//
// This swizzId can be used by root clients like tools for device level
@@ -42,10 +42,12 @@ extern "C" {
// TODO: Deprecate NVC637_DEVICE_LEVEL_SWIZZID once all the clients are moved to
// NVC637_DEVICE_PROFILING_SWIZZID
//
#define NVC637_DEVICE_LEVEL_SWIZZID NVC637_DEVICE_PROFILING_SWIZZID
#define NVC637_DEVICE_LEVEL_SWIZZID NVC637_DEVICE_PROFILING_SWIZZID
/* NvRmAlloc parameters */
typedef struct {
#define NVC637_ALLOCATION_PARAMETERS_MESSAGE_ID (0xc637U)
typedef struct NVC637_ALLOCATION_PARAMETERS {
//
// capDescriptor is a file descriptor for unix RM clients, but a void
// pointer for windows RM clients.
@@ -58,9 +60,3 @@ typedef struct {
NvU32 swizzId;
} NVC637_ALLOCATION_PARAMETERS;
#ifdef __cplusplus
}; /* extern "C" */
#endif
#endif /* _clc637_h_ */

27
src/common/sdk/nvidia/inc/class/clc638.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2019 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2019-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -21,20 +21,21 @@
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
#ifndef _clc638_h_
#define _clc638_h_
#include <nvtypes.h>
#ifdef __cplusplus
extern "C" {
#endif
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: class/clc638.finn
//
#include "nvtypes.h"
#define AMPERE_SMC_EXEC_PARTITION_REF (0x0000c638)
#define AMPERE_SMC_EXEC_PARTITION_REF (0xc638U) /* finn: Evaluated from "NVC638_ALLOCATION_PARAMETERS_MESSAGE_ID" */
/* NvRmAlloc parameters */
typedef struct {
#define NVC638_ALLOCATION_PARAMETERS_MESSAGE_ID (0xc638U)
typedef struct NVC638_ALLOCATION_PARAMETERS {
//
// capDescriptor is a file descriptor for unix RM clients, but a void
// pointer for windows RM clients.
@@ -47,9 +48,3 @@ typedef struct {
NvU32 execPartitionId;
} NVC638_ALLOCATION_PARAMETERS;
#ifdef __cplusplus
}; /* extern "C" */
#endif
#endif /* _clc638_h_ */

26
src/common/sdk/nvidia/inc/class/clc639.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2019 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2019-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -21,20 +21,21 @@
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
#ifndef _clc639_h_
#define _clc639_h_
#include <nvtypes.h>
#ifdef __cplusplus
extern "C" {
#endif
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: class/clc639.finn
//
#include "nvtypes.h"
#define AMPERE_SMC_CONFIG_SESSION (0x0000c639)
#define AMPERE_SMC_CONFIG_SESSION (0xc639U) /* finn: Evaluated from "NVC639_ALLOCATION_PARAMETERS_MESSAGE_ID" */
/* NvRmAlloc parameters */
typedef struct {
#define NVC639_ALLOCATION_PARAMETERS_MESSAGE_ID (0xc639U)
typedef struct NVC639_ALLOCATION_PARAMETERS {
//
// capDescriptor is a file descriptor for unix RM clients, but a void
// pointer for windows RM clients.
@@ -45,8 +46,3 @@ typedef struct {
NV_DECLARE_ALIGNED(NvU64 capDescriptor, 8);
} NVC639_ALLOCATION_PARAMETERS;
#ifdef __cplusplus
}; /* extern "C" */
#endif
#endif /* _clc639_h_ */

26
src/common/sdk/nvidia/inc/class/clc640.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -21,20 +21,21 @@
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
#ifndef _clc640_h_
#define _clc640_h_
#include <nvtypes.h>
#ifdef __cplusplus
extern "C" {
#endif
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: class/clc640.finn
//
#include "nvtypes.h"
#define AMPERE_SMC_MONITOR_SESSION (0x0000c640)
#define AMPERE_SMC_MONITOR_SESSION (0xc640U) /* finn: Evaluated from "NVC640_ALLOCATION_PARAMETERS_MESSAGE_ID" */
/* NvRmAlloc parameters */
typedef struct {
#define NVC640_ALLOCATION_PARAMETERS_MESSAGE_ID (0xc640U)
typedef struct NVC640_ALLOCATION_PARAMETERS {
//
// capDescriptor is a file descriptor for unix RM clients, but a void
// pointer for windows RM clients.
@@ -45,8 +46,3 @@ typedef struct {
NV_DECLARE_ALIGNED(NvU64 capDescriptor, 8);
} NVC640_ALLOCATION_PARAMETERS;
#ifdef __cplusplus
}; /* extern "C" */
#endif
#endif /* _clc640_h_ */

32
src/common/sdk/nvidia/inc/class/clc670.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2018-2022, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -20,26 +20,22 @@
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _clc670_h_
#define _clc670_h_
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#include <nvtypes.h>
#include "nvtypes.h"
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: class/clc670.finn
//
#define NVC670_DISPLAY (0x0000C670)
#define NVC670_DISPLAY (0xc670U) /* finn: Evaluated from "NVC670_ALLOCATION_PARAMETERS_MESSAGE_ID" */
typedef struct
{
NvU32 numHeads; // Number of HEADs in this chip/display
NvU32 numSors; // Number of SORs in this chip/display
NvU32 numDsis; // Number of DSIs in this chip/display
#define NVC670_ALLOCATION_PARAMETERS_MESSAGE_ID (0xc670U)
typedef struct NVC670_ALLOCATION_PARAMETERS {
NvU32 numHeads; // Number of HEADs in this chip/display
NvU32 numSors; // Number of SORs in this chip/display
NvU32 numDsis; // Number of DSIs in this chip/display
} NVC670_ALLOCATION_PARAMETERS;
#ifdef __cplusplus
}; /* extern "C" */
#endif
#endif /* _clc670_h_ */

4373
src/common/sdk/nvidia/inc/class/clc697.h
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File diff suppressed because it is too large Load Diff

34
src/common/sdk/nvidia/inc/class/clc6b5sw.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2018-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2018-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -21,38 +21,34 @@
* DEALINGS IN THE SOFTWARE.
*/
#include "nvtypes.h"
#pragma once
#ifndef _clc6b5sw_h_
#define _clc6b5sw_h_
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: class/clc6b5sw.finn
//
#ifdef __cplusplus
extern "C" {
#endif
/* This file is *not* auto-generated. */
//
// Using VERSION_0 will cause the API to interpret
// engineType as a CE engine instance. This allows
// for backward compatibility with 85B5sw and 90B5sw.
//
#define NVC6B5_ALLOCATION_PARAMETERS_VERSION_0 0
#define NVC6B5_ALLOCATION_PARAMETERS_VERSION_0 0
//
// Using VERSION_1 will cause the API to interpret
// engineType as an NV2080_ENGINE_TYPE ordinal.
//
#define NVC6B5_ALLOCATION_PARAMETERS_VERSION_1 1
#define NVC6B5_ALLOCATION_PARAMETERS_VERSION_1 1
typedef struct
{
NvU32 version;
NvU32 engineType;
#define NVC6B5_ALLOCATION_PARAMETERS_MESSAGE_ID (0xc6b5U)
typedef struct NVC6B5_ALLOCATION_PARAMETERS {
NvU32 version;
NvU32 engineType;
} NVC6B5_ALLOCATION_PARAMETERS;
#ifdef __cplusplus
}; /* extern "C" */
#endif
#endif // _clc5b5sw_h_

19
src/common/sdk/nvidia/inc/class/clc770.h
View File

@@ -20,19 +20,16 @@
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _clc770_h_
#define _clc770_h_
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#include <nvtypes.h>
#include "nvtypes.h"
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: class/clc770.finn
//
#define NVC770_DISPLAY (0xc770U) /* finn: Evaluated from "NVC770_ALLOCATION_PARAMETERS_MESSAGE_ID" */
#define NVC770_DISPLAY (0x0000C770)
#ifdef __cplusplus
}; /* extern "C" */
#endif
#endif /* _clc770_h_ */

16
src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000gspc.h → src/common/sdk/nvidia/inc/class/clc77f.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2005-2016 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -21,12 +21,14 @@
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
#include <nvtypes.h>
#ifndef _clC77F_h_
#define _clC77F_h_
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl0000/ctrl0000gspc.finn
//
// This class provides functional support of Display ANYChannel, Display Contextdmas bound to
// ANYChannel can be used on any other display window channels.
//
#define NVC77F_ANY_CHANNEL_DMA (0x0000C77F)
#endif // _clC77F_h_

4502
src/common/sdk/nvidia/inc/class/clc797.h
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File diff suppressed because it is too large Load Diff

24
src/common/sdk/nvidia/inc/class/clc86f.h
View File

@@ -57,4 +57,28 @@ typedef volatile struct Nvc86fControl_struct {
#define NVC86F_SEM_EXECUTE_RELEASE_WFI_DIS 0x00000000
#define NVC86F_SEM_EXECUTE_PAYLOAD_SIZE 24:24
#define NVC86F_SEM_EXECUTE_PAYLOAD_SIZE_32BIT 0x00000000
/* GPFIFO entry format */
#define NVC86F_GP_ENTRY__SIZE 8
#define NVC86F_GP_ENTRY0_FETCH 0:0
#define NVC86F_GP_ENTRY0_FETCH_UNCONDITIONAL 0x00000000
#define NVC86F_GP_ENTRY0_FETCH_CONDITIONAL 0x00000001
#define NVC86F_GP_ENTRY0_GET 31:2
#define NVC86F_GP_ENTRY0_OPERAND 31:0
#define NVC86F_GP_ENTRY0_PB_EXTENDED_BASE_OPERAND 24:8
#define NVC86F_GP_ENTRY1_GET_HI 7:0
#define NVC86F_GP_ENTRY1_LEVEL 9:9
#define NVC86F_GP_ENTRY1_LEVEL_MAIN 0x00000000
#define NVC86F_GP_ENTRY1_LEVEL_SUBROUTINE 0x00000001
#define NVC86F_GP_ENTRY1_LENGTH 30:10
#define NVC86F_GP_ENTRY1_SYNC 31:31
#define NVC86F_GP_ENTRY1_SYNC_PROCEED 0x00000000
#define NVC86F_GP_ENTRY1_SYNC_WAIT 0x00000001
#define NVC86F_GP_ENTRY1_OPCODE 7:0
#define NVC86F_GP_ENTRY1_OPCODE_NOP 0x00000000
#define NVC86F_GP_ENTRY1_OPCODE_ILLEGAL 0x00000001
#define NVC86F_GP_ENTRY1_OPCODE_GP_CRC 0x00000002
#define NVC86F_GP_ENTRY1_OPCODE_PB_CRC 0x00000003
#define NVC86F_GP_ENTRY1_OPCODE_SET_PB_SEGMENT_EXTENDED_BASE 0x00000004
#endif // __gh100_clc86f_h__

4460
src/common/sdk/nvidia/inc/class/clc997.h
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File diff suppressed because it is too large Load Diff

4461
src/common/sdk/nvidia/inc/class/clcb97.h
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File diff suppressed because it is too large Load Diff

2437
src/common/sdk/nvidia/inc/class/clcb97tex.h Normal file
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File diff suppressed because it is too large Load Diff

8
src/common/sdk/nvidia/inc/cpuopsys.h
View File

@@ -239,7 +239,7 @@
#endif
/* For verification-only features not intended to be included in normal drivers */
#if (defined(NV_MODS) || defined(NV_GSP_MODS)) && defined(DEBUG) && !defined(DISABLE_VERIF_FEATURES)
#if defined(ENABLE_VERIF_FEATURES)
#define NV_VERIF_FEATURES
#endif
@@ -269,12 +269,6 @@
#define NV_IS_MODS 0
#if defined(NV_GSP_MODS)
#define NV_IS_GSP_MODS 1
#else
#define NV_IS_GSP_MODS 0
#endif
#define NVOS_IS_WINDOWS 0
#if defined(NV_WINDOWS_CE)
#define NVOS_IS_WINDOWS_CE 1

1
src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000base.h
View File

@@ -42,7 +42,6 @@
#define NV0000_CTRL_EVENT (0x05)
#define NV0000_CTRL_NVD (0x06)
#define NV0000_CTRL_SWINSTR (0x07)
#define NV0000_CTRL_GSPC (0x08)
#define NV0000_CTRL_PROC (0x09)
#define NV0000_CTRL_SYNC_GPU_BOOST (0x0A)
#define NV0000_CTRL_GPUACCT (0x0B)

31
src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000client.h
View File

@@ -63,18 +63,20 @@ typedef struct NV0000_CTRL_CLIENT_GET_ADDR_SPACE_TYPE_PARAMS {
NvU32 addrSpaceType; /* [out] - Memory Address Space Type */
} NV0000_CTRL_CLIENT_GET_ADDR_SPACE_TYPE_PARAMS;
#define NV0000_CTRL_CMD_CLIENT_GET_ADDR_SPACE_TYPE_INVALID 0x00000000
#define NV0000_CTRL_CMD_CLIENT_GET_ADDR_SPACE_TYPE_SYSMEM 0x00000001
#define NV0000_CTRL_CMD_CLIENT_GET_ADDR_SPACE_TYPE_VIDMEM 0x00000002
#define NV0000_CTRL_CMD_CLIENT_GET_ADDR_SPACE_TYPE_REGMEM 0x00000003
#define NV0000_CTRL_CMD_CLIENT_GET_ADDR_SPACE_TYPE_FABRIC 0x00000004
#define NV0000_CTRL_CMD_CLIENT_GET_ADDR_SPACE_TYPE_INVALID 0x00000000
#define NV0000_CTRL_CMD_CLIENT_GET_ADDR_SPACE_TYPE_SYSMEM 0x00000001
#define NV0000_CTRL_CMD_CLIENT_GET_ADDR_SPACE_TYPE_VIDMEM 0x00000002
#define NV0000_CTRL_CMD_CLIENT_GET_ADDR_SPACE_TYPE_REGMEM 0x00000003
#define NV0000_CTRL_CMD_CLIENT_GET_ADDR_SPACE_TYPE_FABRIC 0x00000004
/*
* NV0000_CTRL_CMD_CLIENT_GET_HANDLE_INFO
*
* This command may be used to query information on a handle
*/
#define NV0000_CTRL_CMD_CLIENT_GET_HANDLE_INFO (0xd02) /* finn: Evaluated from "(FINN_NV01_ROOT_CLIENT_INTERFACE_ID << 8) | NV0000_CTRL_CLIENT_GET_HANDLE_INFO_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_CMD_CLIENT_GET_HANDLE_INFO (0xd02) /* finn: Evaluated from "(FINN_NV01_ROOT_CLIENT_INTERFACE_ID << 8) | NV0000_CTRL_CLIENT_GET_HANDLE_INFO_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_CLIENT_GET_HANDLE_INFO_PARAMS_MESSAGE_ID (0x2U)
@@ -160,5 +162,22 @@ typedef struct NV0000_CTRL_CLIENT_SHARE_OBJECT_PARAMS {
RS_SHARE_POLICY sharePolicy; /* [in] - Share Policy to apply */
} NV0000_CTRL_CLIENT_SHARE_OBJECT_PARAMS;
/*
* NV0000_CTRL_CMD_CLIENT_OBJECTS_ARE_DUPLICATES
*
* This command returns true if the objects are duplicates.
*
* Currently supported only for memory objects.
*/
#define NV0000_CTRL_CMD_CLIENT_OBJECTS_ARE_DUPLICATES (0xd07) /* finn: Evaluated from "(FINN_NV01_ROOT_CLIENT_INTERFACE_ID << 8) | NV0000_CTRL_CLIENT_OBJECTS_ARE_DUPLICATES_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_CLIENT_OBJECTS_ARE_DUPLICATES_PARAMS_MESSAGE_ID (0x7U)
typedef struct NV0000_CTRL_CLIENT_OBJECTS_ARE_DUPLICATES_PARAMS {
NvHandle hObject1; /* [in] - Handle of object to be checked */
NvHandle hObject2; /* [in] - Handle of object to be checked */
NvBool bDuplicates; /* [out] - Returns true if duplicates */
} NV0000_CTRL_CLIENT_OBJECTS_ARE_DUPLICATES_PARAMS;
/* _ctrl0000client_h_ */

144
src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000gpu.h
View File

@@ -56,10 +56,10 @@
* NV_ERR_INVALID_PARAM_STRUCT
* NV_ERR_OPERATING_SYSTEM
*/
#define NV0000_CTRL_CMD_GPU_GET_ATTACHED_IDS (0x201) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_GET_ATTACHED_IDS_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_CMD_GPU_GET_ATTACHED_IDS (0x201U) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_GET_ATTACHED_IDS_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_GPU_MAX_ATTACHED_GPUS 32
#define NV0000_CTRL_GPU_INVALID_ID (0xffffffff)
#define NV0000_CTRL_GPU_MAX_ATTACHED_GPUS 32U
#define NV0000_CTRL_GPU_INVALID_ID (0xffffffffU)
#define NV0000_CTRL_GPU_GET_ATTACHED_IDS_PARAMS_MESSAGE_ID (0x1U)
@@ -70,9 +70,9 @@ typedef struct NV0000_CTRL_GPU_GET_ATTACHED_IDS_PARAMS {
/*
* Deprecated. Please use NV0000_CTRL_CMD_GPU_GET_ID_INFO_V2 instead.
*/
#define NV0000_CTRL_CMD_GPU_GET_ID_INFO (0x202) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_GET_ID_INFO_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_CMD_GPU_GET_ID_INFO (0x202U) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_GET_ID_INFO_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_GPU_MAX_SZNAME 128
#define NV0000_CTRL_GPU_MAX_SZNAME 128U
#define NV0000_CTRL_NO_NUMA_NODE (-1)
@@ -149,7 +149,7 @@ typedef struct NV0000_CTRL_GPU_GET_ID_INFO_PARAMS {
#define NV0000_CTRL_CMD_GPU_GET_ID_INFO_V2 (0x205) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_GET_ID_INFO_V2_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_CMD_GPU_GET_ID_INFO_V2 (0x205U) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_GET_ID_INFO_V2_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_GPU_GET_ID_INFO_V2_PARAMS_MESSAGE_ID (0x5U)
@@ -167,25 +167,25 @@ typedef struct NV0000_CTRL_GPU_GET_ID_INFO_V2_PARAMS {
/* valid flags values */
#define NV0000_CTRL_GPU_ID_INFO_IN_USE 0:0
#define NV0000_CTRL_GPU_ID_INFO_IN_USE_FALSE (0x00000000)
#define NV0000_CTRL_GPU_ID_INFO_IN_USE_TRUE (0x00000001)
#define NV0000_CTRL_GPU_ID_INFO_IN_USE_FALSE (0x00000000U)
#define NV0000_CTRL_GPU_ID_INFO_IN_USE_TRUE (0x00000001U)
#define NV0000_CTRL_GPU_ID_INFO_LINKED_INTO_SLI_DEVICE 1:1
#define NV0000_CTRL_GPU_ID_INFO_LINKED_INTO_SLI_DEVICE_FALSE (0x00000000)
#define NV0000_CTRL_GPU_ID_INFO_LINKED_INTO_SLI_DEVICE_TRUE (0x00000001)
#define NV0000_CTRL_GPU_ID_INFO_LINKED_INTO_SLI_DEVICE_FALSE (0x00000000U)
#define NV0000_CTRL_GPU_ID_INFO_LINKED_INTO_SLI_DEVICE_TRUE (0x00000001U)
#define NV0000_CTRL_GPU_ID_INFO_MOBILE 2:2
#define NV0000_CTRL_GPU_ID_INFO_MOBILE_FALSE (0x00000000)
#define NV0000_CTRL_GPU_ID_INFO_MOBILE_TRUE (0x00000001)
#define NV0000_CTRL_GPU_ID_INFO_MOBILE_FALSE (0x00000000U)
#define NV0000_CTRL_GPU_ID_INFO_MOBILE_TRUE (0x00000001U)
#define NV0000_CTRL_GPU_ID_INFO_BOOT_MASTER 3:3
#define NV0000_CTRL_GPU_ID_INFO_BOOT_MASTER_FALSE (0x00000000)
#define NV0000_CTRL_GPU_ID_INFO_BOOT_MASTER_TRUE (0x00000001)
#define NV0000_CTRL_GPU_ID_INFO_BOOT_MASTER_FALSE (0x00000000U)
#define NV0000_CTRL_GPU_ID_INFO_BOOT_MASTER_TRUE (0x00000001U)
#define NV0000_CTRL_GPU_ID_INFO_SOC 5:5
#define NV0000_CTRL_GPU_ID_INFO_SOC_FALSE (0x00000000)
#define NV0000_CTRL_GPU_ID_INFO_SOC_TRUE (0x00000001)
#define NV0000_CTRL_GPU_ID_INFO_SOC_FALSE (0x00000000U)
#define NV0000_CTRL_GPU_ID_INFO_SOC_TRUE (0x00000001U)
#define NV0000_CTRL_GPU_ID_INFO_ATS_ENABLED 6:6
#define NV0000_CTRL_GPU_ID_INFO_ATS_ENABLED_FALSE (0x00000000)
#define NV0000_CTRL_GPU_ID_INFO_ATS_ENABLED_TRUE (0x00000001)
#define NV0000_CTRL_GPU_ID_INFO_ATS_ENABLED_FALSE (0x00000000U)
#define NV0000_CTRL_GPU_ID_INFO_ATS_ENABLED_TRUE (0x00000001U)
/*
* NV0000_CTRL_CMD_GPU_GET_INIT_STATUS
@@ -213,7 +213,7 @@ typedef struct NV0000_CTRL_GPU_GET_ID_INFO_V2_PARAMS {
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_INVALID_STATE
*/
#define NV0000_CTRL_CMD_GPU_GET_INIT_STATUS (0x203) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_GET_INIT_STATUS_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_CMD_GPU_GET_INIT_STATUS (0x203U) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_GET_INIT_STATUS_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_GPU_GET_INIT_STATUS_PARAMS_MESSAGE_ID (0x3U)
@@ -240,7 +240,7 @@ typedef struct NV0000_CTRL_GPU_GET_INIT_STATUS_PARAMS {
* NV_OK
* NV_ERR_INVALID_PARAM_STRUCT
*/
#define NV0000_CTRL_CMD_GPU_GET_DEVICE_IDS (0x204) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_GET_DEVICE_IDS_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_CMD_GPU_GET_DEVICE_IDS (0x204U) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_GET_DEVICE_IDS_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_GPU_GET_DEVICE_IDS_PARAMS_MESSAGE_ID (0x4U)
@@ -275,7 +275,7 @@ typedef struct NV0000_CTRL_GPU_GET_DEVICE_IDS_PARAMS {
* Possible status values returned are:
* NV_OK
*/
#define NV0000_CTRL_CMD_GPU_GET_PROBED_IDS (0x214) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_GET_PROBED_IDS_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_CMD_GPU_GET_PROBED_IDS (0x214U) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_GET_PROBED_IDS_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_GPU_MAX_PROBED_GPUS NV_MAX_DEVICES
@@ -312,7 +312,7 @@ typedef struct NV0000_CTRL_GPU_GET_PROBED_IDS_PARAMS {
* NV_ERR_NOT_SUPPORTED
* NV_ERR_INVALID_ARGUMENT
*/
#define NV0000_CTRL_CMD_GPU_GET_PCI_INFO (0x21b) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_GET_PCI_INFO_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_CMD_GPU_GET_PCI_INFO (0x21bU) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_GET_PCI_INFO_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_GPU_GET_PCI_INFO_PARAMS_MESSAGE_ID (0x1BU)
@@ -371,9 +371,9 @@ typedef struct NV0000_CTRL_GPU_GET_PCI_INFO_PARAMS {
* NV_ERR_IRQ_EDGE_TRIGGERED
* NV_ERR_IRQ_NOT_FIRING
*/
#define NV0000_CTRL_CMD_GPU_ATTACH_IDS (0x215) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_ATTACH_IDS_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_CMD_GPU_ATTACH_IDS (0x215U) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_ATTACH_IDS_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_GPU_ATTACH_ALL_PROBED_IDS (0x0000ffff)
#define NV0000_CTRL_GPU_ATTACH_ALL_PROBED_IDS (0x0000ffffU)
#define NV0000_CTRL_GPU_ATTACH_IDS_PARAMS_MESSAGE_ID (0x15U)
@@ -424,9 +424,9 @@ typedef struct NV0000_CTRL_GPU_ATTACH_IDS_PARAMS {
* NV_ERR_INVALID_PARAM_STRUCT
* NV_ERR_INVALID_ARGUMENT
*/
#define NV0000_CTRL_CMD_GPU_DETACH_IDS (0x216) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_DETACH_IDS_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_CMD_GPU_DETACH_IDS (0x216U) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_DETACH_IDS_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_GPU_DETACH_ALL_ATTACHED_IDS (0x0000ffff)
#define NV0000_CTRL_GPU_DETACH_ALL_ATTACHED_IDS (0x0000ffffU)
#define NV0000_CTRL_GPU_DETACH_IDS_PARAMS_MESSAGE_ID (0x16U)
@@ -455,7 +455,7 @@ typedef struct NV0000_CTRL_GPU_DETACH_IDS_PARAMS {
* NV_ERR_INVALID_STATE
*
*/
#define NV0000_CTRL_CMD_GPU_GET_SVM_SIZE (0x240) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_GET_SVM_SIZE_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_CMD_GPU_GET_SVM_SIZE (0x240U) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_GET_SVM_SIZE_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_GPU_GET_SVM_SIZE_PARAMS_MESSAGE_ID (0x40U)
@@ -504,10 +504,10 @@ typedef struct NV0000_CTRL_GPU_GET_SVM_SIZE_PARAMS {
* NV_ERR_OBJECT_NOT_FOUND
*
*/
#define NV0000_CTRL_CMD_GPU_GET_UUID_INFO (0x274) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_GET_UUID_INFO_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_CMD_GPU_GET_UUID_INFO (0x274U) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_GET_UUID_INFO_PARAMS_MESSAGE_ID" */
/* maximum possible number of bytes of GID information */
#define NV0000_GPU_MAX_GID_LENGTH (0x00000100)
#define NV0000_GPU_MAX_GID_LENGTH (0x00000100U)
#define NV0000_CTRL_GPU_GET_UUID_INFO_PARAMS_MESSAGE_ID (0x74U)
@@ -520,12 +520,12 @@ typedef struct NV0000_CTRL_GPU_GET_UUID_INFO_PARAMS {
} NV0000_CTRL_GPU_GET_UUID_INFO_PARAMS;
#define NV0000_CTRL_CMD_GPU_GET_UUID_INFO_FLAGS_FORMAT 1:0
#define NV0000_CTRL_CMD_GPU_GET_UUID_INFO_FLAGS_FORMAT_ASCII (0x00000000)
#define NV0000_CTRL_CMD_GPU_GET_UUID_INFO_FLAGS_FORMAT_BINARY (0x00000002)
#define NV0000_CTRL_CMD_GPU_GET_UUID_INFO_FLAGS_FORMAT_ASCII (0x00000000U)
#define NV0000_CTRL_CMD_GPU_GET_UUID_INFO_FLAGS_FORMAT_BINARY (0x00000002U)
#define NV0000_CTRL_CMD_GPU_GET_UUID_INFO_FLAGS_TYPE 2:2
#define NV0000_CTRL_CMD_GPU_GET_UUID_INFO_FLAGS_TYPE_SHA1 (0x00000000)
#define NV0000_CTRL_CMD_GPU_GET_UUID_INFO_FLAGS_TYPE_SHA256 (0x00000001)
#define NV0000_CTRL_CMD_GPU_GET_UUID_INFO_FLAGS_TYPE_SHA1 (0x00000000U)
#define NV0000_CTRL_CMD_GPU_GET_UUID_INFO_FLAGS_TYPE_SHA256 (0x00000001U)
/*
* NV0000_CTRL_CMD_GPU_GET_UUID_FROM_GPU_ID
@@ -566,7 +566,7 @@ typedef struct NV0000_CTRL_GPU_GET_UUID_INFO_PARAMS {
* NV_ERR_OBJECT_NOT_FOUND
* NV_ERR_OPERATING_SYSTEM
*/
#define NV0000_CTRL_CMD_GPU_GET_UUID_FROM_GPU_ID (0x275) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_GET_UUID_FROM_GPU_ID_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_CMD_GPU_GET_UUID_FROM_GPU_ID (0x275U) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_GET_UUID_FROM_GPU_ID_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_GPU_GET_UUID_FROM_GPU_ID_PARAMS_MESSAGE_ID (0x75U)
@@ -579,13 +579,13 @@ typedef struct NV0000_CTRL_GPU_GET_UUID_FROM_GPU_ID_PARAMS {
/* valid format values */
#define NV0000_CTRL_CMD_GPU_GET_UUID_FROM_GPU_ID_FLAGS_FORMAT 1:0
#define NV0000_CTRL_CMD_GPU_GET_UUID_FROM_GPU_ID_FLAGS_FORMAT_ASCII (0x00000000)
#define NV0000_CTRL_CMD_GPU_GET_UUID_FROM_GPU_ID_FLAGS_FORMAT_BINARY (0x00000002)
#define NV0000_CTRL_CMD_GPU_GET_UUID_FROM_GPU_ID_FLAGS_FORMAT_ASCII (0x00000000U)
#define NV0000_CTRL_CMD_GPU_GET_UUID_FROM_GPU_ID_FLAGS_FORMAT_BINARY (0x00000002U)
/*valid type values*/
#define NV0000_CTRL_CMD_GPU_GET_UUID_FROM_GPU_ID_FLAGS_TYPE 2:2
#define NV0000_CTRL_CMD_GPU_GET_UUID_FROM_GPU_ID_FLAGS_TYPE_SHA1 (0x00000000)
#define NV0000_CTRL_CMD_GPU_GET_UUID_FROM_GPU_ID_FLAGS_TYPE_SHA256 (0x00000001)
#define NV0000_CTRL_CMD_GPU_GET_UUID_FROM_GPU_ID_FLAGS_TYPE_SHA1 (0x00000000U)
#define NV0000_CTRL_CMD_GPU_GET_UUID_FROM_GPU_ID_FLAGS_TYPE_SHA256 (0x00000001U)
@@ -630,15 +630,15 @@ typedef struct NV0000_CTRL_GPU_GET_UUID_FROM_GPU_ID_PARAMS {
* NV_ERR_IN_USE
*/
#define NV0000_CTRL_CMD_GPU_MODIFY_DRAIN_STATE (0x278) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_MODIFY_DRAIN_STATE_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_CMD_GPU_MODIFY_DRAIN_STATE (0x278U) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_MODIFY_DRAIN_STATE_PARAMS_MESSAGE_ID" */
/* Possible values of newState */
#define NV0000_CTRL_GPU_DRAIN_STATE_DISABLED (0x00000000)
#define NV0000_CTRL_GPU_DRAIN_STATE_ENABLED (0x00000001)
#define NV0000_CTRL_GPU_DRAIN_STATE_DISABLED (0x00000000U)
#define NV0000_CTRL_GPU_DRAIN_STATE_ENABLED (0x00000001U)
/* Defined bits for the "flags" argument */
#define NV0000_CTRL_GPU_DRAIN_STATE_FLAG_REMOVE_DEVICE (0x00000001)
#define NV0000_CTRL_GPU_DRAIN_STATE_FLAG_LINK_DISABLE (0x00000002)
#define NV0000_CTRL_GPU_DRAIN_STATE_FLAG_REMOVE_DEVICE (0x00000001U)
#define NV0000_CTRL_GPU_DRAIN_STATE_FLAG_LINK_DISABLE (0x00000002U)
#define NV0000_CTRL_GPU_MODIFY_DRAIN_STATE_PARAMS_MESSAGE_ID (0x78U)
@@ -678,7 +678,7 @@ typedef struct NV0000_CTRL_GPU_MODIFY_DRAIN_STATE_PARAMS {
* NV_ERR_INVALID_ARGUMENT
*/
#define NV0000_CTRL_CMD_GPU_QUERY_DRAIN_STATE (0x279) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_QUERY_DRAIN_STATE_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_CMD_GPU_QUERY_DRAIN_STATE (0x279U) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_QUERY_DRAIN_STATE_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_GPU_QUERY_DRAIN_STATE_PARAMS_MESSAGE_ID (0x79U)
@@ -716,7 +716,7 @@ typedef struct NV0000_CTRL_GPU_QUERY_DRAIN_STATE_PARAMS {
* NV_ERR_NOT_SUPPORTED
*/
#define NV0000_CTRL_CMD_GPU_DISCOVER (0x27a) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | 0x7A" */
#define NV0000_CTRL_CMD_GPU_DISCOVER (0x27aU) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | 0x7A" */
typedef struct NV0000_CTRL_GPU_DISCOVER_PARAMS {
NvU32 domain;
@@ -740,7 +740,7 @@ typedef struct NV0000_CTRL_GPU_DISCOVER_PARAMS {
* NV_OK
*
*/
#define NV0000_CTRL_CMD_GPU_GET_MEMOP_ENABLE (0x27b) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_GET_MEMOP_ENABLE_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_CMD_GPU_GET_MEMOP_ENABLE (0x27bU) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_GET_MEMOP_ENABLE_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_GPU_GET_MEMOP_ENABLE_PARAMS_MESSAGE_ID (0x7BU)
@@ -748,7 +748,7 @@ typedef struct NV0000_CTRL_GPU_GET_MEMOP_ENABLE_PARAMS {
NvU32 enableMask;
} NV0000_CTRL_GPU_GET_MEMOP_ENABLE_PARAMS;
#define NV0000_CTRL_GPU_FLAGS_MEMOP_ENABLE (0x00000001)
#define NV0000_CTRL_GPU_FLAGS_MEMOP_ENABLE (0x00000001U)
@@ -770,7 +770,7 @@ typedef struct NV0000_CTRL_GPU_GET_MEMOP_ENABLE_PARAMS {
* NV_ERR_IN_USE
*
*/
#define NV0000_CTRL_CMD_GPU_DISABLE_NVLINK_INIT (0x281) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_DISABLE_NVLINK_INIT_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_CMD_GPU_DISABLE_NVLINK_INIT (0x281U) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_DISABLE_NVLINK_INIT_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_GPU_DISABLE_NVLINK_INIT_PARAMS_MESSAGE_ID (0x81U)
@@ -781,16 +781,16 @@ typedef struct NV0000_CTRL_GPU_DISABLE_NVLINK_INIT_PARAMS {
} NV0000_CTRL_GPU_DISABLE_NVLINK_INIT_PARAMS;
#define NV0000_CTRL_GPU_LEGACY_CONFIG_MAX_PARAM_DATA 0x00000175
#define NV0000_CTRL_GPU_LEGACY_CONFIG_MAX_PROPERTIES_IN 6
#define NV0000_CTRL_GPU_LEGACY_CONFIG_MAX_PROPERTIES_OUT 5
#define NV0000_CTRL_GPU_LEGACY_CONFIG_MAX_PARAM_DATA 0x00000175U
#define NV0000_CTRL_GPU_LEGACY_CONFIG_MAX_PROPERTIES_IN 6U
#define NV0000_CTRL_GPU_LEGACY_CONFIG_MAX_PROPERTIES_OUT 5U
/*
* NV0000_CTRL_CMD_GPU_LEGACY_CONFIG
*
* Path to use legacy RM GetConfig/Set API. This API is being phased out.
*/
#define NV0000_CTRL_CMD_GPU_LEGACY_CONFIG (0x282) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_LEGACY_CONFIG_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_CMD_GPU_LEGACY_CONFIG (0x282U) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_LEGACY_CONFIG_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_GPU_LEGACY_CONFIG_PARAMS_MESSAGE_ID (0x82U)
@@ -801,9 +801,6 @@ typedef struct NV0000_CTRL_GPU_LEGACY_CONFIG_PARAMS {
NvU32 dataType; /* [out] - data union type */
union {
struct {
NvV32 value;
} configGet;
struct {
NvU32 newValue;
NvU32 oldValue;
@@ -820,16 +817,15 @@ typedef struct NV0000_CTRL_GPU_LEGACY_CONFIG_PARAMS {
} data;
} NV0000_CTRL_GPU_LEGACY_CONFIG_PARAMS;
#define NV0000_CTRL_GPU_LEGACY_CONFIG_OP_TYPE_GET (0x00000000)
#define NV0000_CTRL_GPU_LEGACY_CONFIG_OP_TYPE_SET (0x00000001)
#define NV0000_CTRL_GPU_LEGACY_CONFIG_OP_TYPE_GET_EX (0x00000002)
#define NV0000_CTRL_GPU_LEGACY_CONFIG_OP_TYPE_SET_EX (0x00000003)
#define NV0000_CTRL_GPU_LEGACY_CONFIG_OP_TYPE_RESERVED (0x00000004)
#define NV0000_CTRL_GPU_LEGACY_CONFIG_OP_TYPE_SET (0x00000001U)
#define NV0000_CTRL_GPU_LEGACY_CONFIG_OP_TYPE_GET_EX (0x00000002U)
#define NV0000_CTRL_GPU_LEGACY_CONFIG_OP_TYPE_SET_EX (0x00000003U)
#define NV0000_CTRL_GPU_LEGACY_CONFIG_OP_TYPE_RESERVED (0x00000004U)
/*
* NV0000_CTRL_CMD_IDLE_CHANNELS
*/
#define NV0000_CTRL_CMD_IDLE_CHANNELS (0x283) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_IDLE_CHANNELS_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_CMD_IDLE_CHANNELS (0x283U) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_IDLE_CHANNELS_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_GPU_IDLE_CHANNELS_PARAMS_MESSAGE_ID (0x83U)
@@ -847,5 +843,31 @@ typedef struct NV0000_CTRL_GPU_IDLE_CHANNELS_PARAMS {
NvV32 timeout;
} NV0000_CTRL_GPU_IDLE_CHANNELS_PARAMS;
#define NV0000_CTRL_GPU_IMAGE_TYPE_GSP (0x00000001U)
#define NV0000_CTRL_GPU_IMAGE_TYPE_GSP_LOG (0x00000002U)
/*
* NV0000_CTRL_CMD_PUSH_GSP_UCODE
*
* This command is used to push the GSP ucode into RM.
* This function is used only on VMware
*
* Possible status values returned are:
* NV_OK The sent data is stored successfully
* NV_ERR_INVALID_ARGUMENT if the arguments are not proper
* NV_ERR_NO_MEMORY if memory allocation failed
* NV_ERR_NOT_SUPPORTED if function is invoked on non-GSP setup or any
* setup other than VMware host
*
*/
#define NV0000_CTRL_CMD_PUSH_GSP_UCODE (0x285) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_PUSH_GSP_UCODE_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_GPU_PUSH_GSP_UCODE_PARAMS_MESSAGE_ID (0x85U)
typedef struct NV0000_CTRL_GPU_PUSH_GSP_UCODE_PARAMS {
NvU8 image;
NV_DECLARE_ALIGNED(NvU64 totalSize, 8);
NV_DECLARE_ALIGNED(NvP64 pData, 8);
} NV0000_CTRL_GPU_PUSH_GSP_UCODE_PARAMS;
/* _ctrl0000gpu_h_ */

2017
src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000system.h
View File

File diff suppressed because it is too large Load Diff

5
src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000unix.h
View File

@@ -222,6 +222,9 @@ typedef struct NV0000_CTRL_OS_GET_GPU_INFO_PARAMS {
* deviceInstatnce
* This parameter returns a deviceInstance on which the object is located.
*
* NV_MAX_DEVICES is returned if the object is parented by a client instead
* of a device.
*
* maxObjects
* This parameter returns the maximum number of object handles that may be
* contained in the file descriptor.
@@ -416,6 +419,8 @@ typedef struct NV0000_CTRL_OS_UNIX_EXPORT_OBJECTS_TO_FD_PARAMS {
#define NV0000_CTRL_CMD_OS_UNIX_IMPORT_OBJECT_TYPE_SYSMEM 2
#define NV0000_CTRL_CMD_OS_UNIX_IMPORT_OBJECT_TYPE_FABRIC 3
#define NV0000_CTRL_OS_UNIX_IMPORT_OBJECTS_FROM_FD_PARAMS_MESSAGE_ID (0xCU)
typedef struct NV0000_CTRL_OS_UNIX_IMPORT_OBJECTS_FROM_FD_PARAMS {

48
src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000vgpu.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2016-2018 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2016-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -30,3 +30,49 @@
// Source file: ctrl/ctrl0000/ctrl0000vgpu.finn
//
#include "ctrl/ctrl0000/ctrl0000base.h"
#include "ctrl/ctrlxxxx.h"
#include "ctrl/ctrla081.h"
#include "class/cl0000.h"
#include "nv_vgpu_types.h"
/*
* NV0000_CTRL_CMD_VGPU_GET_START_DATA
*
* This command gets data associated with NV0000_NOTIFIERS_VGPU_MGR_START to
* start VGPU process.
*
* mdevUuid
* This parameter gives mdev device UUID for which nvidia-vgpu-mgr should
* init process.
*
* qemuPid
* This parameter specifies the QEMU process ID of the VM.
*
* gpuPciId
* This parameter provides gpuId of GPU on which vgpu device is created.
*
* configParams
* This parameter specifies the configuration parameters for vGPU
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_EVENT
* NV_ERR_OBJECT_NOT_FOUND
* NV_ERR_INVALID_CLIENT
*
*/
#define NV0000_CTRL_CMD_VGPU_GET_START_DATA (0xc01) /* finn: Evaluated from "(FINN_NV01_ROOT_VGPU_INTERFACE_ID << 8) | NV0000_CTRL_VGPU_GET_START_DATA_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_VGPU_GET_START_DATA_PARAMS_MESSAGE_ID (0x1U)
typedef struct NV0000_CTRL_VGPU_GET_START_DATA_PARAMS {
NvU8 mdevUuid[VM_UUID_SIZE];
NvU8 configParams[1024];
NvU32 qemuPid;
NvU32 gpuPciId;
NvU16 vgpuId;
NvU32 gpuPciBdf;
} NV0000_CTRL_VGPU_GET_START_DATA_PARAMS;
/* _ctrl0000vgpu_h_ */

22
src/common/sdk/nvidia/inc/ctrl/ctrl0041.h
View File

@@ -156,28 +156,6 @@ typedef struct NV0041_CTRL_GET_SURFACE_ZCULL_ID_PARAMS {
NvU32 zcullId;
} NV0041_CTRL_GET_SURFACE_ZCULL_ID_PARAMS;
/*
* NV0041_CTRL_CMD_GET_SURFACE_PARTITION_STRIDE
*
* This command returns the partition stride (in bytes) for real memory
* associated with the memory object.
*
* Possible status values returned are:
* NV_OK
* NVOS_STATUS_BAD_OBJECT_HANDLE
* NVOS_STATUS_BAD_OBJECT_PARENT
* NVOS_STATUS_NOT_SUPPORTED
*
*/
#define NV0041_CTRL_CMD_GET_SURFACE_PARTITION_STRIDE (0x410105) /* finn: Evaluated from "(FINN_NV01_ROOT_USER_MEMORY_INTERFACE_ID << 8) | NV0041_CTRL_GET_SURFACE_PARTITION_STRIDE_PARAMS_MESSAGE_ID" */
#define NV0041_CTRL_GET_SURFACE_PARTITION_STRIDE_PARAMS_MESSAGE_ID (0x5U)
typedef struct NV0041_CTRL_GET_SURFACE_PARTITION_STRIDE_PARAMS {
NvU32 partitionStride;
} NV0041_CTRL_GET_SURFACE_PARTITION_STRIDE_PARAMS;
// return values for 'tilingFormat'
// XXX - the names for these are misleading

52
src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073dfp.h
View File

@@ -1137,6 +1137,10 @@ typedef struct NV0073_CTRL_CMD_DFP_GET_DISP_MUX_STATUS_PARAMS {
* Major version number of DSC decoder on Panel.
* dscDecoderVersionMinor
* Minor version number of DSC decoder on Panel.
* dscUseCustomPPS
* Flag to indicate if Panel uses custom PPS values which deviate from standard values.
* dscCustomPPSData
* 32 bytes of custom PPS data required by Panel.
* dscEncoderCaps
* Capabilities of DSC encoder in SoC.
*
@@ -1148,31 +1152,35 @@ typedef struct NV0073_CTRL_CMD_DFP_GET_DISP_MUX_STATUS_PARAMS {
#define NV0073_CTRL_CMD_DFP_GET_DSI_MODE_TIMING (0x731166U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DFP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_DFP_GET_DSI_MODE_TIMING_PARAMS_MESSAGE_ID" */
#define NV0073_CTRL_CMD_DFP_DSI_CUSTOM_PPS_DATA_COUNT 32U
#define NV0073_CTRL_CMD_DFP_GET_DSI_MODE_TIMING_PARAMS_MESSAGE_ID (0x66U)
typedef struct NV0073_CTRL_CMD_DFP_GET_DSI_MODE_TIMING_PARAMS {
NvU32 subDeviceInstance;
NvU32 displayId;
NvU32 hActive;
NvU32 vActive;
NvU32 hFrontPorch;
NvU32 vFrontPorch;
NvU32 hBackPorch;
NvU32 vBackPorch;
NvU32 hSyncWidth;
NvU32 vSyncWidth;
NvU32 bpp;
NvU32 refresh;
NvU32 pclkHz;
NvU32 numLanes;
NvU32 dscEnable;
NvU32 dscBpp;
NvU32 dscNumSlices;
NvU32 dscDualDsc;
NvU32 dscSliceHeight;
NvU32 dscBlockPrediction;
NvU32 dscDecoderVersionMajor;
NvU32 dscDecoderVersionMinor;
NvU32 subDeviceInstance;
NvU32 displayId;
NvU32 hActive;
NvU32 vActive;
NvU32 hFrontPorch;
NvU32 vFrontPorch;
NvU32 hBackPorch;
NvU32 vBackPorch;
NvU32 hSyncWidth;
NvU32 vSyncWidth;
NvU32 bpp;
NvU32 refresh;
NvU32 pclkHz;
NvU32 numLanes;
NvU32 dscEnable;
NvU32 dscBpp;
NvU32 dscNumSlices;
NvU32 dscDualDsc;
NvU32 dscSliceHeight;
NvU32 dscBlockPrediction;
NvU32 dscDecoderVersionMajor;
NvU32 dscDecoderVersionMinor;
NvBool dscUseCustomPPS;
NvU32 dscCustomPPSData[NV0073_CTRL_CMD_DFP_DSI_CUSTOM_PPS_DATA_COUNT];
struct {
NvBool bDscSupported;

22
src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073dp.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2005-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2005-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -1738,8 +1738,8 @@ typedef struct NV0073_CTRL_CMD_DP_SEND_ACT_PARAMS {
* should be set to zero for default behavior.
* sorIndex
* Specifies the SOR index.
* bIsDp12Supported
* Returns NV_TRUE if DP1.2 is supported by the GPU else NV_FALSE
* dpVersionsSupported
* Specified the DP versions supported by the GPU
* bIsMultistreamSupported
* Returns NV_TRUE if MST is supported by the GPU else NV_FALSE
* bIsSCEnabled
@@ -1788,6 +1788,7 @@ typedef struct NV0073_CTRL_CMD_DP_SEND_ACT_PARAMS {
* NV_ERR_NOT_SUPPORTED
*
*/
#define NV0073_CTRL_CMD_DP_GET_CAPS (0x731369U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_DP_GET_CAPS_PARAMS_MESSAGE_ID" */
#define NV0073_CTRL_CMD_DP_GET_CAPS_PARAMS_MESSAGE_ID (0x69U)
@@ -1796,8 +1797,7 @@ typedef struct NV0073_CTRL_CMD_DP_GET_CAPS_PARAMS {
NvU32 subDeviceInstance;
NvU32 sorIndex;
NvU32 maxLinkRate;
NvBool bIsDp12Supported;
NvBool bIsDp14Supported;
NvU32 dpVersionsSupported;
NvBool bIsMultistreamSupported;
NvBool bIsSCEnabled;
NvBool bHasIncreasedWatermarkLimits;
@@ -1818,6 +1818,15 @@ typedef struct NV0073_CTRL_CMD_DP_GET_CAPS_PARAMS {
} DSC;
} NV0073_CTRL_CMD_DP_GET_CAPS_PARAMS;
#define NV0073_CTRL_CMD_DP_GET_CAPS_DP_VERSIONS_SUPPORTED_DP1_2 0:0
#define NV0073_CTRL_CMD_DP_GET_CAPS_DP_VERSIONS_SUPPORTED_DP1_2_NO (0x00000000U)
#define NV0073_CTRL_CMD_DP_GET_CAPS_DP_VERSIONS_SUPPORTED_DP1_2_YES (0x00000001U)
#define NV0073_CTRL_CMD_DP_GET_CAPS_DP_VERSIONS_SUPPORTED_DP1_4 1:1
#define NV0073_CTRL_CMD_DP_GET_CAPS_DP_VERSIONS_SUPPORTED_DP1_4_NO (0x00000000U)
#define NV0073_CTRL_CMD_DP_GET_CAPS_DP_VERSIONS_SUPPORTED_DP1_4_YES (0x00000001U)
#define NV0073_CTRL_CMD_DP_GET_CAPS_MAX_LINK_RATE 2:0
#define NV0073_CTRL_CMD_DP_GET_CAPS_MAX_LINK_RATE_NONE (0x00000000U)
#define NV0073_CTRL_CMD_DP_GET_CAPS_MAX_LINK_RATE_1_62 (0x00000001U)
@@ -2705,7 +2714,7 @@ typedef struct NV0073_CTRL_CMD_DP_AUXCH_OD_CTRL_PARAMS {
#define NV0073_CTRL_CMD_DP_AUXCH_OD_CTL_SET_ENABLE_OD 0x00000003
/*
* NV0073_CTRL_CMD_DP_SET_MSA_PROPERTIES_V2
* NV0073_CTRL_CMD_DP_SET_MSA_PROPERTIES
*
* This command returns the following info
*
@@ -2755,5 +2764,4 @@ typedef struct NV0073_CTRL_CMD_DP_SET_MSA_PROPERTIES_V2_PARAMS {
NvBool bDebugValues;
NV0073_CTRL_DP_MSA_PROPERTIES_VALUES featureDebugValues;
} NV0073_CTRL_CMD_DP_SET_MSA_PROPERTIES_V2_PARAMS;
/* _ctrl0073dp_h_ */

74
src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073specific.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 1993-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -574,7 +574,48 @@ typedef struct NV0073_CTRL_SPECIFIC_ACPI_ID_MAPPING {
NvU32 dodIndex;
} NV0073_CTRL_SPECIFIC_ACPI_ID_MAPPING;
/*
* NV0073_CTRL_CMD_GET_ACPI_DOD_DISPLAY_PORT_ATTACHMENT
*
* This call will return the Display Port Attachment value
* per displayID as defined by Nvidia that is directly
* associated with the ACPI 3.0 _DOD entry's Display Port
* Attachment field. This should help clients map the
* _DOD ACPI ID to each displayID. Note, that some systems
* do not have a standard in place for this field. On those
* systems, the RM will return NV_ERR_NOT_SUPPORTED.
*
* Note that this "Display Port" attachment field has nothing
* to do with DisplayPort/DP. It's an unfortunate name inside
* the ACPI 3.0 spec that coincides with the name of DisplayPort.
*
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_PARAM_STRUCT
* NV_ERR_NOT_SUPPORTED
*
*/
#define NV0073_CTRL_GET_ACPI_DOD_DISPLAY_PORT_ATTACHMENT_PARAMS_MESSAGE_ID (0x85U)
typedef struct NV0073_CTRL_GET_ACPI_DOD_DISPLAY_PORT_ATTACHMENT_PARAMS {
NvU32 subDeviceInstance;
NvU32 displayId;
NvU32 dispPortAttachment;
} NV0073_CTRL_GET_ACPI_DOD_DISPLAY_PORT_ATTACHMENT_PARAMS;
#define NV0073_CTRL_CMD_SPECIFIC_GET_ACPI_DOD_DISPLAY_PORT_ATTACHMENT (0x730285U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_GET_ACPI_DOD_DISPLAY_PORT_ATTACHMENT_PARAMS_MESSAGE_ID" */
// defines for dispPortAttachment
#define NV0073_DISPLAY_PORT_ATTACHMENT_ANALOG (0x00000000U)
#define NV0073_DISPLAY_PORT_ATTACHMENT_LVDS (0x00000001U)
#define NV0073_DISPLAY_PORT_ATTACHMENT_DP_A (0x00000002U)
#define NV0073_DISPLAY_PORT_ATTACHMENT_DP_B (0x00000003U)
#define NV0073_DISPLAY_PORT_ATTACHMENT_DP_C (0x00000004U)
#define NV0073_DISPLAY_PORT_ATTACHMENT_DP_D (0x00000005U)
#define NV0073_DISPLAY_PORT_ATTACHMENT_UNKNOWN (0xFFFFFFFFU)
/*
* NV0073_CTRL_CMD_SPECIFIC_SET_ACPI_ID_MAPPING
@@ -1835,7 +1876,34 @@ typedef struct NV0073_CTRL_SPECIFIC_DISP_I2C_READ_WRITE_PARAMS {
NvU8 writeBuffer[NV0073_CTRL_SPECIFIC_DISP_I2C_READ_WRITE_BUF_LEN];
} NV0073_CTRL_SPECIFIC_DISP_I2C_READ_WRITE_PARAMS;
#define NV0073_CTRL_SPECIFIC_DISP_I2C_READ_MODE (0x00000001)
#define NV0073_CTRL_SPECIFIC_DISP_I2C_WRITE_MODE (0x00000000)
#define NV0073_CTRL_SPECIFIC_DISP_I2C_READ_MODE (0x00000001)
#define NV0073_CTRL_SPECIFIC_DISP_I2C_WRITE_MODE (0x00000000)
/*
* NV0073_CTRL_CMD_GET_VALID_HEAD_WINDOW_ASSIGNMENT
*
* This command returns the valid window head assignment mask
*
* windowHeadMask [out]
* This out parameter is an array which holds the head mask for
* each window. The Nth element in the array would be a bitmask
* of which heads can possibly drive window N.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_GENERIC
*/
#define NV0073_CTRL_CMD_SPECIFIC_GET_VALID_HEAD_WINDOW_ASSIGNMENT (0x7302ad) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_SPECIFIC_GET_VALID_HEAD_WINDOW_ASSIGNMENT_PARAMS_MESSAGE_ID" */
#define NV0073_CTRL_SPECIFIC_MAX_WINDOWS 32U
#define NV0073_CTRL_SPECIFIC_FLEXIBLE_HEAD_WINDOW_ASSIGNMENT (0xFFU)
#define NV0073_CTRL_SPECIFIC_GET_VALID_HEAD_WINDOW_ASSIGNMENT_PARAMS_MESSAGE_ID (0xADU)
typedef struct NV0073_CTRL_SPECIFIC_GET_VALID_HEAD_WINDOW_ASSIGNMENT_PARAMS {
NvU32 subDeviceInstance;
NvU8 windowHeadMask[NV0073_CTRL_SPECIFIC_MAX_WINDOWS];
} NV0073_CTRL_SPECIFIC_GET_VALID_HEAD_WINDOW_ASSIGNMENT_PARAMS;
/* _ctrl0073specific_h_ */

408
src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073system.h
View File

@@ -603,6 +603,122 @@ typedef struct NV0073_CTRL_SYSTEM_GET_ACTIVE_PARAMS {
/*
* NV0073_CTRL_SYSTEM_ACPI_ID_MAP
*
* This structure defines the mapping between the RM's displayId and the
* defined ACPI IDs for each display.
* displayId
* This parameter is a handle to a single display output path from the
* GPU pins to the display connector. Each display ID is defined by one bit.
* A zero in this parameter indicates a skip entry.
* acpiId
* This parameter defines the corresponding ACPI ID of the displayId.
* flags
* This parameter specifies optional flags that describe the association
* between the display ID and the ACPI ID.
* NV0073_CTRL_SYSTEM_ACPI_ID_MAP_ORIGIN
* This field describes where the ACPI was found.
* NV0073_CTRL_SYSTEM_ACPI_ID_MAP_ORIGIN_RM
* The ACPI ID was generated by RM code.
* NV0073_CTRL_SYSTEM_ACPI_ID_MAP_ORIGIN_DOD
* The ACPI ID was found via the ACPI _DOD call.
* NV0073_CTRL_SYSTEM_ACPI_ID_MAP_ORIGIN_CLIENT
* The ACPI ID was generated by RM Client and sent to RM. Note this
* must be set on a NV0073_CTRL_CMD_SYSTEM_SET_ACPI_ID_MAP call.
* NV0073_CTRL_SYSTEM_ACPI_ID_MAP_SNAG_UNDOCKED
* This flag explains that the ACPI ID is only valid when the system
* is undocked. If this flag is not set, the ACPI ID is valid always.
* NV0073_CTRL_SYSTEM_ACPI_ID_MAP_SNAG_DOCKED
* This flag explains that the ACPI ID is only valid when the system
* is docked. If this flag is not set, the ACPI ID is valid always.
* NV0073_CTRL_SYSTEM_ACPI_ID_MAP_DOD_BIOS_DETECT
* This flag is set only if the _DOD returns that the device can be
* detected by the system BIOS. This flag is copied directly from
* the ACPI spec.
* NV0073_CTRL_SYSTEM_ACPI_ID_MAP_DOD_NON_VGA_OUTPUT
* This flag is set only if the _DOD returns that the device is
* a non-VGA device whose power is related to the VGA device.
* i.e. TV tuner, DVD decoder, Video capture. This flag is copied
* directly from the ACPI spec.
* NV0073_CTRL_SYSTEM_ACPI_ID_MAP_DOD_MULTIHEAD_ID
* This value is set only if the _DOD returns it. The number
* indicates the head output of a multi-head device. This has no
* relation to the term, Head, currently used in the RM today.
* This is strictly a copy of the value directly from the ACPI spec.
* NV0073_CTRL_SYSTEM_ACPI_ID_MAP_DOD_SCHEME
* This flag is set only if the _DOD returns that the acpiID follows
* the ACPI 3.0 spec. This flag is copied directly from
* the ACPI spec.
*
*/
typedef struct NV0073_CTRL_SYSTEM_ACPI_ID_MAP_PARAMS {
NvU32 displayId;
NvU32 acpiId;
NvU32 flags;
} NV0073_CTRL_SYSTEM_ACPI_ID_MAP_PARAMS;
#define NV0073_CTRL_SYSTEM_ACPI_ID_MAP_ORIGIN 1:0
#define NV0073_CTRL_SYSTEM_ACPI_ID_MAP_ORIGIN_RM 0x00000000U
#define NV0073_CTRL_SYSTEM_ACPI_ID_MAP_ORIGIN_DOD 0x00000001U
#define NV0073_CTRL_SYSTEM_ACPI_ID_MAP_ORIGIN_CLIENT 0x00000002U
#define NV0073_CTRL_SYSTEM_ACPI_ID_MAP_SNAG_UNDOCKED 2:2
#define NV0073_CTRL_SYSTEM_ACPI_ID_MAP_SNAG_UNDOCKED_FALSE 0x00000000U
#define NV0073_CTRL_SYSTEM_ACPI_ID_MAP_SNAG_UNDOCKED_TRUE 0x00000001U
#define NV0073_CTRL_SYSTEM_ACPI_ID_MAP_SNAG_DOCKED 3:3
#define NV0073_CTRL_SYSTEM_ACPI_ID_MAP_SNAG_DOCKED_FALSE 0x00000000U
#define NV0073_CTRL_SYSTEM_ACPI_ID_MAP_SNAG_DOCKED_TRUE 0x00000001U
#define NV0073_CTRL_SYSTEM_ACPI_ID_MAP_DOD_BIOS_DETECT 16:16
#define NV0073_CTRL_SYSTEM_ACPI_ID_MAP_DOD_BIOS_DETECT_FALSE 0x00000000U
#define NV0073_CTRL_SYSTEM_ACPI_ID_MAP_DOD_BIOS_DETECT_TRUE 0x00000001U
#define NV0073_CTRL_SYSTEM_ACPI_ID_MAP_DOD_NON_VGA_OUTPUT 17:17
#define NV0073_CTRL_SYSTEM_ACPI_ID_MAP_DOD_NON_VGA_OUTPUT_FALSE 0x00000000U
#define NV0073_CTRL_SYSTEM_ACPI_ID_MAP_DOD_NON_VGA_OUTPUT_TRUE 0x00000001U
#define NV0073_CTRL_SYSTEM_ACPI_ID_MAP_DOD_MULTIHEAD_ID 20:18
#define NV0073_CTRL_SYSTEM_ACPI_ID_MAP_DOD_SCHEME 31:31
#define NV0073_CTRL_SYSTEM_ACPI_ID_MAP_DOD_SCHEME_VENDOR 0x00000000U
#define NV0073_CTRL_SYSTEM_ACPI_ID_MAP_DOD_SCHEME_30 0x00000001U
#define NV0073_CTRL_SYSTEM_ACPI_ID_MAP_MAX_DISPLAYS (16U)
/*
* NV0073_CTRL_CMD_SYSTEM_GET_ACPI_ID_MAP
*
* This command retrieves the mapping between the RM's displayId and the
* defined ACPI IDs for each display.
*
* subDeviceInstance
* This parameter specifies the subdevice instance within the
* NV04_DISPLAY_COMMON parent device to which the operation should be
* directed. This parameter must specify a value between zero and
* the total number of subdevices within the parent device. It should
* be set to zero for default behavior.
* NV0073_CTRL_SYSTEM_ACPI_ID_MAP_PARAMS
* An array of display ID to ACPI ids with flags for each description.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
* Only returned if subdeviceInstance was not valid.
*/
#define NV0073_CTRL_CMD_SYSTEM_GET_ACPI_ID_MAP (0x73015aU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_SYSTEM_GET_ACPI_ID_MAP_PARAMS_MESSAGE_ID" */
#define NV0073_CTRL_SYSTEM_GET_ACPI_ID_MAP_PARAMS_MESSAGE_ID (0x5AU)
typedef struct NV0073_CTRL_SYSTEM_GET_ACPI_ID_MAP_PARAMS {
NvU32 subDeviceInstance;
NV0073_CTRL_SYSTEM_ACPI_ID_MAP_PARAMS acpiIdMap[NV0073_CTRL_SYSTEM_ACPI_ID_MAP_MAX_DISPLAYS];
} NV0073_CTRL_SYSTEM_GET_ACPI_ID_MAP_PARAMS;
/*
* NV0073_CTRL_CMD_SYSTEM_GET_INTERNAL_DISPLAYS
*
@@ -670,6 +786,265 @@ typedef struct NV0073_CTRL_SYSTEM_GET_BOOT_DISPLAYS_PARAMS {
/*
* NV0073_CTRL_CMD_SYSTEM_EXECUTE_ACPI_METHOD
*
* This command is used to execute general MXM ACPI methods.
*
* method
* This parameter identifies the MXM ACPI API to be invoked.
* Valid values for this parameter are:
* NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_MXMI
* This value specifies that the MXMI API is to invoked.
* NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_MXMS
* This value specifies that the MXMS API is to invoked.
* NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_MXMX
* This value specifies that the MXMX API is to invoked.
* NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_GPUON
* This value specifies that the Hybrid GPU ON API is to be invoked.
* NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_GPUOFF
* This value specifies that the Hybrid GPU OFF API is to be invoked.
* NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_GPUSTA
* This value specifies that the Hybrid GPU STA API is to be invoked.
* NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_MXDS
* This value specifies that the Hybrid GPU MXDS API is to be invoked.
* NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_NVHG_MXMX
* This value specifies that the Hybrid GPU MXMX API is to be invoked.
* NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DOS
* This value specifies that the Hybrid GPU DOS API is to be invoked.
* NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_ROM
* This value specifies that the Hybrid GPU ROM API is to be invoked.
* NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DOD
* This value specifies that the Hybrid GPU DOD API is to be invoked.
* NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_SUPPORT
* This value specifies that the Hybrid GPU DSM subfunction SUPPORT
* API is to be invoked.
* NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_HYBRIDCAPS
* This value specifies that the Hybrid GPU DSM subfunction SUPPORT
* API is to be invoked.
* NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_POLICYSELECT
* This value specifies that the Hybrid GPU DSM subfunction POLICYSELECT
* API is to be invoked.
* NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_POWERCONTROL
* This value specifies that the Hybrid GPU DSM subfunction POWERCONTROL
* API is to be invoked.
* NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_PLATPOLICY
* This value specifies that the Hybrid GPU DSM subfunction PLATPOLICY
* API is to be invoked.
* NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_DISPLAYSTATUS
* This value specifies that the Hybrid GPU DSM subfunction DISPLAYSTATUS
* API is to be invoked.
* NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_MDTL
* This value specifies that the Hybrid GPU DSM subfunction MDTL
* API is to be invoked.
* NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_HCSMBLIST
* This value specifies that the Hybrid GPU DSM subfunction HCSMBLIST
* API is to be invoked.
* NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_HCSMBADDR
* This value specifies that the Hybrid GPU DSM subfunction HCSMBADDR
* API is to be invoked.
* NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_HCREADBYTE
* This value specifies that the Hybrid GPU DSM subfunction HCREADBYTE
* API is to be invoked.
* NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_HCSENDBYTE
* This value specifies that the Hybrid GPU DSM subfunction HCSENDBYTES
* API is to be invoked.
* NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_HCGETSTATUS
* This value specifies that the Hybrid GPU DSM subfunction HCGETSTATUS
* API is to be invoked.
* NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_HCTRIGDDC
* This value specifies that the Hybrid GPU DSM subfunction HCTRIGDDC
* API is to be invoked.
* NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_HCGETDDC
* This value specifies that the Hybrid GPU DSM subfunction HCGETDDC
* API is to be invoked.
* NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DCS
* This value specifies that the Hybrid GPU DCS API is to be invoked.
* NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_MXM_MXSS
* This value specifies that the DSM MXM subfunction MXSS
* API is to be invoked.
* NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_MXM_MXMI
* This value specifies that the DSM MXM subfunction MXMI
* API is to be invoked.
* NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_MXM_MXMS
* This value specifies that the DSM MXM subfunction MXMS
* API is to be invoked.
* NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_MXM_MXPP
* This value specifies that the DSM MXM subfunction MXPP
* API is to be invoked.
* NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_MXM_MXDP
* This value specifies that the DSM MXM subfunction MXDP
* API is to be invoked.
* NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_MXM_MDTL
* This value specifies that the DSM MXM subfunction MDTL
* API is to be invoked.
* NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_MXM_MXCB
* This value specifies that the DSM MXM subfunction MXCB
* API is to be invoked.
* NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GENERIC_CTL_REMAPFUNC
* This value specifies the DSM generic remapping should return function
* and subfunction when this API is to be invoked.
* NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GENERIC_HYBRIDCAPS
* This value specifies that the generic DSM subfunction HYBRIDCAPS
* API is to be invoked.
* NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GENERIC_POLICYSELECT
* This value specifies that the generic DSM subfunction POLICYSELECT
* API is to be invoked.
* NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GENERIC_PLATPOLICY
* This value specifies that the generic DSM subfunction PLATPOLICY
* API is to be invoked.
* NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GENERIC_DISPLAYSTATUS
* This value specifies that the generic DSM subfunction DISPLAYSTATUS
* API is to be invoked.
* NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GENERIC_MDTL
* This value specifies that the generic DSM subfunction MDTL
* API is to be invoked.
* NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GENERIC_GETOBJBYTYPE
* This value specifies that the generic DSM subfunction GETOBJBYTYPE
* API is to be invoked.
* NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GENERIC_GETALLOBJS
* This value specifies that the generic DSM subfunction GETALLOBJS
* API is to be invoked.
* NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GENERIC_GETEVENTLIST
* This value specifies that the generic DSM subfunction GETEVENTLIST
* API is to be invoked.
* NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GENERIC_GETBACKLIGHT
* This value specifies that the generic DSM subfunction GETBACKLIGHT
* API is to be invoked.
* NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GENERIC_CTL_TESTSUBFUNCENABLED
* This value specifies the testIfDsmSubFunctionEnabled test should
* be done for the func/subfunction when this API is to be invoked.
* NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GENERIC_CTL_GETSUPPORTEDFUNC
* This value specifies the list of supported generic dsm functions
* should be returned.
* NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_NVOP_OPTIMUSCAPS
* This value specifies that the DSM NVOP subfunction OPTIMUSCAPS
* API is to be invoked.
* NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_NVOP_OPTIMUSFLAG
* This value specifies that the DSM NVOP subfunction OPTIMUSFLAG
* API is to be invoked. This API will set a Flag in sbios to Indicate
* that HD Audio Controller is disable/Enabled from GPU Config space.
* This flag will be used by sbios to restore Audio state after resuming
* from s3/s4.
* NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_WMMX_NVOP_GPUON
* This value specifies that the WMMX (WMI-ACPI) GPON methods has to be invoked
* this call should happen below DPC level from any client.
* inData
* This parameter specifies the method-specific input buffer. Data is
* passed to the specified API using this buffer. For display related
* APIs the associated display mask can be found at a byte offset within
* the inData buffer using the following method-specific values:
* NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_MXMX_DISP_MASK_OFFSET
* NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_MXDS_DISP_MASK_OFFSET
* NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_NVHG_MXMX_DISP_MASK_OFFSET
* NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DOS_DISP_MASK_OFFSET
* inDataSize
* This parameter specifies the size of the inData buffer in bytes.
* outStatus
* This parameter returns the status code from the associated ACPI call.
* outData
* This parameter specifies the method-specific output buffer. Data
* is returned by the specified API using this buffer.
* outDataSize
* This parameter specifies the size of the outData buffer in bytes.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_PARAM_STRUCT
* NV_ERR_INVALID_ARGUMENT
*/
#define NV0073_CTRL_CMD_SYSTEM_EXECUTE_ACPI_METHOD (0x730168U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_PARAMS_MESSAGE_ID" */
#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_PARAMS_MESSAGE_ID (0x68U)
typedef struct NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_PARAMS {
NvU32 method;
NV_DECLARE_ALIGNED(NvP64 inData, 8);
NvU16 inDataSize;
NvU32 outStatus;
NV_DECLARE_ALIGNED(NvP64 outData, 8);
NvU16 outDataSize;
} NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_PARAMS;
/* valid method parameter values */
#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_MXMX (0x00000002U)
#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_MXMX_DISP_MASK_OFFSET (0x00000001U)
#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_GPUON (0x00000003U)
#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_GPUOFF (0x00000004U)
#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_GPUSTA (0x00000005U)
#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_MXDS (0x00000006U)
#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_NVHG_MXMX (0x00000007U)
#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DOS (0x00000008U)
#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_ROM (0x00000009U)
#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DOD (0x0000000aU)
#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_SUPPORT (0x0000000bU)
#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_HYBRIDCAPS (0x0000000cU)
#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_POLICYSELECT (0x0000000dU)
#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_POWERCONTROL (0x0000000eU)
#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_PLATPOLICY (0x0000000fU)
#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_DISPLAYSTATUS (0x00000010U)
#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_MDTL (0x00000011U)
#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_HCSMBLIST (0x00000012U)
#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_HCSMBADDR (0x00000013U)
#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_HCREADBYTE (0x00000014U)
#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_HCSENDBYTE (0x00000015U)
#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_HCGETSTATUS (0x00000016U)
#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_HCTRIGDDC (0x00000017U)
#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_HCGETDDC (0x00000018U)
#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DCS (0x00000019U)
#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_MXM_MXSS (0x0000001aU)
#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_MXM_MXMI (0x0000001bU)
#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_MXM_MXMS (0x0000001cU)
#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_MXM_MXPP (0x0000001dU)
#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_MXM_MXDP (0x0000001eU)
#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_MXM_MDTL (0x0000001fU)
#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_MXM_MXCB (0x00000020U)
#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_MXM_GETEVENTLIST (0x00000021U)
#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GETMEMTABLE (0x00000022U)
#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GETMEMCFG (0x00000023U)
#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GETOBJBYTYPE (0x00000024U)
#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GETALLOBJS (0x00000025U)
#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GENERIC_CTL_REMAPFUNC (0x00000026U)
#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GENERIC_DISPLAYSTATUS (0x0000002aU)
#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GENERIC_MDTL (0x0000002bU)
#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GENERIC_GETOBJBYTYPE (0x0000002cU)
#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GENERIC_GETALLOBJS (0x0000002dU)
#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GENERIC_GETEVENTLIST (0x0000002eU)
#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GENERIC_GETBACKLIGHT (0x0000002fU)
#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GENERIC_CTL_TESTSUBFUNCENABLED (0x00000030U)
#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GENERIC_CTL_GETSUPPORTEDFUNC (0x00000031U)
#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_NVOP_OPTIMUSCAPS (0x00000032U)
#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_WMMX_NVOP_GPUON (0x00000033U)
#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_NVOP_OPTIMUSFLAG (0x00000034U)
#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GENERIC_GETCALLBACKS (0x00000036U)
#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_NBCI_SUPPORTFUNCS (0x00000037U)
#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_NBCI_PLATCAPS (0x00000038U)
#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_NBCI_PLATPOLICY (0x00000039U)
#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GENERIC_MSTL (0x0000003aU)
#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_NVGPS_FUNC_SUPPORT (0x0000003bU)
#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_NBCI_MXDS (0x0000003cU)
#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_NBCI_MXDM (0x0000003dU)
#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_NBCI_MXID (0x0000003eU)
#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_NBCI_LRST (0x0000003fU)
#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DDC_EDID (0x00000040U)
/* valid input buffer offset values */
#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_MXDS_DISP_MASK_OFFSET (0x00000004U)
#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_NVHG_MXMX_DISP_MASK_OFFSET (0x00000004U)
#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DOS_DISP_MASK_OFFSET (0x00000004U)
#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_NBCI_MXDS_DISP_MASK_OFFSET (0x00000004U)
#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_NBCI_MXDM_DISP_MASK_OFFSET (0x00000004U)
#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_NBCI_MXID_DISP_MASK_OFFSET (0x00000004U)
#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_NBCI_LRST_DISP_MASK_OFFSET (0x00000004U)
#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DDC_EDID_DISP_MASK_OFFSET (0x00000004U)
/*
* NV0073_CTRL_CMD_SYSTEM_GET_HOTPLUG_UNPLUG_STATE
*
@@ -1068,5 +1443,38 @@ typedef struct NV0073_CTRL_CMD_SYSTEM_CHECK_SIDEBAND_I2C_SUPPORT_PARAMS {
NvBool bIsSidebandI2cSupported;
} NV0073_CTRL_CMD_SYSTEM_CHECK_SIDEBAND_I2C_SUPPORT_PARAMS;
/*
* NV0073_CTRL_CMD_SYSTEM_CHECK_SIDEBAND_SR_SUPPORT
*
* This command is used to query if SIDEBAND SR can be used with the
* given display device. If PSR API is supported on the system,
* then sideband SR support is set to false.
*
* subDeviceInstance (in)
* This parameter specifies the subdevice instance within the
* NV04_DISPLAY_COMMON parent device to which the operation
* should be directed.
* displayId (in)
* This parameter inputs the displayId of the active display. A value
* of zero indicates no display is active.
* bIsSidebandSrSupported
* If it is true, it means that sideband is supported and not PSR API.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_PARAM_STRUCT
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_NOT_SUPPORTED
*/
#define NV0073_CTRL_CMD_SYSTEM_CHECK_SIDEBAND_SR_SUPPORT (0x73019dU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_CMD_SYSTEM_CHECK_SIDEBAND_SR_SUPPORT_PARAMS_MESSAGE_ID" */
#define NV0073_CTRL_CMD_SYSTEM_CHECK_SIDEBAND_SR_SUPPORT_PARAMS_MESSAGE_ID (0x9DU)
typedef struct NV0073_CTRL_CMD_SYSTEM_CHECK_SIDEBAND_SR_SUPPORT_PARAMS {
NvU32 subDeviceInstance;
NvU32 displayId;
NvBool bIsSidebandSrSupported;
} NV0073_CTRL_CMD_SYSTEM_CHECK_SIDEBAND_SR_SUPPORT_PARAMS;
/* _ctrl0073system_h_ */

2
src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080dma.h
View File

@@ -696,7 +696,7 @@ typedef struct NV0080_CTRL_DMA_UPDATE_PDE_2_PARAMS {
NvU32 flags;
NV_DECLARE_ALIGNED(NV0080_CTRL_DMA_UPDATE_PDE_2_PAGE_TABLE_PARAMS ptParams[NV0080_CTRL_DMA_UPDATE_PDE_2_PT_IDX__SIZE], 8);
NvHandle hVASpace;
NV_DECLARE_ALIGNED(NvP64 pPdeBuffer, 8); // NV_MMU_VER2_PDE__SIZE
NV_DECLARE_ALIGNED(NvP64 pPdeBuffer, 8); // NV_MMU_VER2_DUAL_PDE__SIZE
NvU32 subDeviceId; // ID+1, 0 for BC
} NV0080_CTRL_DMA_UPDATE_PDE_2_PARAMS;

2
src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080fifo.h
View File

@@ -192,7 +192,7 @@ typedef struct NV0080_CTRL_FIFO_CHANNEL {
#define NV0080_CTRL_FIFO_START_SELECTED_CHANNELS_PARAMS_MESSAGE_ID (0x5U)
typedef struct NV0080_CTRL_FIFO_START_SELECTED_CHANNELS_PARAMS {
NvU32 fifoStartChannelListSize;
NvU32 fifoStartChannelListCount;
NvHandle channelHandle[8];
NV_DECLARE_ALIGNED(NvP64 fifoStartChannelList, 8);
} NV0080_CTRL_FIFO_START_SELECTED_CHANNELS_PARAMS;

2
src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080gpu.h
View File

@@ -494,7 +494,7 @@ typedef struct NV0080_CTRL_GPU_GET_SRIOV_CAPS_PARAMS {
// Update this macro if new HW exceeds GPU Classlist MAX_SIZE
#define NV0080_CTRL_GPU_CLASSLIST_MAX_SIZE 116
#define NV0080_CTRL_GPU_CLASSLIST_MAX_SIZE 160
#define NV0080_CTRL_CMD_GPU_GET_CLASSLIST_V2 (0x800292) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GPU_INTERFACE_ID << 8) | NV0080_CTRL_GPU_GET_CLASSLIST_V2_PARAMS_MESSAGE_ID" */

5
src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080gr.h
View File

@@ -150,13 +150,14 @@ typedef struct NV0080_CTRL_GR_INFO {
#define NV0080_CTRL_GR_INFO_INDEX_MAX_PER_ENGINE_SUBCONTEXT_COUNT (0x0000002E)
#define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_SLICES_PER_LTC (0x00000032)
/* When adding a new INDEX, please update MAX_SIZE accordingly
* NOTE: 0080 functionality is merged with 2080 functionality, so this max size
* reflects that.
*/
#define NV0080_CTRL_GR_INFO_INDEX_MAX (0x00000031)
#define NV0080_CTRL_GR_INFO_MAX_SIZE (0x32) /* finn: Evaluated from "(NV0080_CTRL_GR_INFO_INDEX_MAX + 1)" */
#define NV0080_CTRL_GR_INFO_INDEX_MAX (0x00000032)
#define NV0080_CTRL_GR_INFO_MAX_SIZE (0x33) /* finn: Evaluated from "(NV0080_CTRL_GR_INFO_INDEX_MAX + 1)" */
/*
* NV0080_CTRL_CMD_GR_GET_INFO

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