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This commit is contained in:
Andy Ritger
2022-11-10 08:39:33 -08:00
parent 7c345b838b
commit 758b4ee818
1323 changed files with 262135 additions and 60754 deletions
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1
src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000base.h
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@@ -42,7 +42,6 @@
#define NV0000_CTRL_EVENT (0x05)
#define NV0000_CTRL_NVD (0x06)
#define NV0000_CTRL_SWINSTR (0x07)
#define NV0000_CTRL_GSPC (0x08)
#define NV0000_CTRL_PROC (0x09)
#define NV0000_CTRL_SYNC_GPU_BOOST (0x0A)
#define NV0000_CTRL_GPUACCT (0x0B)

31
src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000client.h
View File

@@ -63,18 +63,20 @@ typedef struct NV0000_CTRL_CLIENT_GET_ADDR_SPACE_TYPE_PARAMS {
NvU32 addrSpaceType; /* [out] - Memory Address Space Type */
} NV0000_CTRL_CLIENT_GET_ADDR_SPACE_TYPE_PARAMS;
#define NV0000_CTRL_CMD_CLIENT_GET_ADDR_SPACE_TYPE_INVALID 0x00000000
#define NV0000_CTRL_CMD_CLIENT_GET_ADDR_SPACE_TYPE_SYSMEM 0x00000001
#define NV0000_CTRL_CMD_CLIENT_GET_ADDR_SPACE_TYPE_VIDMEM 0x00000002
#define NV0000_CTRL_CMD_CLIENT_GET_ADDR_SPACE_TYPE_REGMEM 0x00000003
#define NV0000_CTRL_CMD_CLIENT_GET_ADDR_SPACE_TYPE_FABRIC 0x00000004
#define NV0000_CTRL_CMD_CLIENT_GET_ADDR_SPACE_TYPE_INVALID 0x00000000
#define NV0000_CTRL_CMD_CLIENT_GET_ADDR_SPACE_TYPE_SYSMEM 0x00000001
#define NV0000_CTRL_CMD_CLIENT_GET_ADDR_SPACE_TYPE_VIDMEM 0x00000002
#define NV0000_CTRL_CMD_CLIENT_GET_ADDR_SPACE_TYPE_REGMEM 0x00000003
#define NV0000_CTRL_CMD_CLIENT_GET_ADDR_SPACE_TYPE_FABRIC 0x00000004
/*
* NV0000_CTRL_CMD_CLIENT_GET_HANDLE_INFO
*
* This command may be used to query information on a handle
*/
#define NV0000_CTRL_CMD_CLIENT_GET_HANDLE_INFO (0xd02) /* finn: Evaluated from "(FINN_NV01_ROOT_CLIENT_INTERFACE_ID << 8) | NV0000_CTRL_CLIENT_GET_HANDLE_INFO_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_CMD_CLIENT_GET_HANDLE_INFO (0xd02) /* finn: Evaluated from "(FINN_NV01_ROOT_CLIENT_INTERFACE_ID << 8) | NV0000_CTRL_CLIENT_GET_HANDLE_INFO_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_CLIENT_GET_HANDLE_INFO_PARAMS_MESSAGE_ID (0x2U)
@@ -160,5 +162,22 @@ typedef struct NV0000_CTRL_CLIENT_SHARE_OBJECT_PARAMS {
RS_SHARE_POLICY sharePolicy; /* [in] - Share Policy to apply */
} NV0000_CTRL_CLIENT_SHARE_OBJECT_PARAMS;
/*
* NV0000_CTRL_CMD_CLIENT_OBJECTS_ARE_DUPLICATES
*
* This command returns true if the objects are duplicates.
*
* Currently supported only for memory objects.
*/
#define NV0000_CTRL_CMD_CLIENT_OBJECTS_ARE_DUPLICATES (0xd07) /* finn: Evaluated from "(FINN_NV01_ROOT_CLIENT_INTERFACE_ID << 8) | NV0000_CTRL_CLIENT_OBJECTS_ARE_DUPLICATES_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_CLIENT_OBJECTS_ARE_DUPLICATES_PARAMS_MESSAGE_ID (0x7U)
typedef struct NV0000_CTRL_CLIENT_OBJECTS_ARE_DUPLICATES_PARAMS {
NvHandle hObject1; /* [in] - Handle of object to be checked */
NvHandle hObject2; /* [in] - Handle of object to be checked */
NvBool bDuplicates; /* [out] - Returns true if duplicates */
} NV0000_CTRL_CLIENT_OBJECTS_ARE_DUPLICATES_PARAMS;
/* _ctrl0000client_h_ */

144
src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000gpu.h
View File

@@ -56,10 +56,10 @@
* NV_ERR_INVALID_PARAM_STRUCT
* NV_ERR_OPERATING_SYSTEM
*/
#define NV0000_CTRL_CMD_GPU_GET_ATTACHED_IDS (0x201) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_GET_ATTACHED_IDS_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_CMD_GPU_GET_ATTACHED_IDS (0x201U) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_GET_ATTACHED_IDS_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_GPU_MAX_ATTACHED_GPUS 32
#define NV0000_CTRL_GPU_INVALID_ID (0xffffffff)
#define NV0000_CTRL_GPU_MAX_ATTACHED_GPUS 32U
#define NV0000_CTRL_GPU_INVALID_ID (0xffffffffU)
#define NV0000_CTRL_GPU_GET_ATTACHED_IDS_PARAMS_MESSAGE_ID (0x1U)
@@ -70,9 +70,9 @@ typedef struct NV0000_CTRL_GPU_GET_ATTACHED_IDS_PARAMS {
/*
* Deprecated. Please use NV0000_CTRL_CMD_GPU_GET_ID_INFO_V2 instead.
*/
#define NV0000_CTRL_CMD_GPU_GET_ID_INFO (0x202) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_GET_ID_INFO_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_CMD_GPU_GET_ID_INFO (0x202U) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_GET_ID_INFO_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_GPU_MAX_SZNAME 128
#define NV0000_CTRL_GPU_MAX_SZNAME 128U
#define NV0000_CTRL_NO_NUMA_NODE (-1)
@@ -149,7 +149,7 @@ typedef struct NV0000_CTRL_GPU_GET_ID_INFO_PARAMS {
#define NV0000_CTRL_CMD_GPU_GET_ID_INFO_V2 (0x205) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_GET_ID_INFO_V2_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_CMD_GPU_GET_ID_INFO_V2 (0x205U) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_GET_ID_INFO_V2_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_GPU_GET_ID_INFO_V2_PARAMS_MESSAGE_ID (0x5U)
@@ -167,25 +167,25 @@ typedef struct NV0000_CTRL_GPU_GET_ID_INFO_V2_PARAMS {
/* valid flags values */
#define NV0000_CTRL_GPU_ID_INFO_IN_USE 0:0
#define NV0000_CTRL_GPU_ID_INFO_IN_USE_FALSE (0x00000000)
#define NV0000_CTRL_GPU_ID_INFO_IN_USE_TRUE (0x00000001)
#define NV0000_CTRL_GPU_ID_INFO_IN_USE_FALSE (0x00000000U)
#define NV0000_CTRL_GPU_ID_INFO_IN_USE_TRUE (0x00000001U)
#define NV0000_CTRL_GPU_ID_INFO_LINKED_INTO_SLI_DEVICE 1:1
#define NV0000_CTRL_GPU_ID_INFO_LINKED_INTO_SLI_DEVICE_FALSE (0x00000000)
#define NV0000_CTRL_GPU_ID_INFO_LINKED_INTO_SLI_DEVICE_TRUE (0x00000001)
#define NV0000_CTRL_GPU_ID_INFO_LINKED_INTO_SLI_DEVICE_FALSE (0x00000000U)
#define NV0000_CTRL_GPU_ID_INFO_LINKED_INTO_SLI_DEVICE_TRUE (0x00000001U)
#define NV0000_CTRL_GPU_ID_INFO_MOBILE 2:2
#define NV0000_CTRL_GPU_ID_INFO_MOBILE_FALSE (0x00000000)
#define NV0000_CTRL_GPU_ID_INFO_MOBILE_TRUE (0x00000001)
#define NV0000_CTRL_GPU_ID_INFO_MOBILE_FALSE (0x00000000U)
#define NV0000_CTRL_GPU_ID_INFO_MOBILE_TRUE (0x00000001U)
#define NV0000_CTRL_GPU_ID_INFO_BOOT_MASTER 3:3
#define NV0000_CTRL_GPU_ID_INFO_BOOT_MASTER_FALSE (0x00000000)
#define NV0000_CTRL_GPU_ID_INFO_BOOT_MASTER_TRUE (0x00000001)
#define NV0000_CTRL_GPU_ID_INFO_BOOT_MASTER_FALSE (0x00000000U)
#define NV0000_CTRL_GPU_ID_INFO_BOOT_MASTER_TRUE (0x00000001U)
#define NV0000_CTRL_GPU_ID_INFO_SOC 5:5
#define NV0000_CTRL_GPU_ID_INFO_SOC_FALSE (0x00000000)
#define NV0000_CTRL_GPU_ID_INFO_SOC_TRUE (0x00000001)
#define NV0000_CTRL_GPU_ID_INFO_SOC_FALSE (0x00000000U)
#define NV0000_CTRL_GPU_ID_INFO_SOC_TRUE (0x00000001U)
#define NV0000_CTRL_GPU_ID_INFO_ATS_ENABLED 6:6
#define NV0000_CTRL_GPU_ID_INFO_ATS_ENABLED_FALSE (0x00000000)
#define NV0000_CTRL_GPU_ID_INFO_ATS_ENABLED_TRUE (0x00000001)
#define NV0000_CTRL_GPU_ID_INFO_ATS_ENABLED_FALSE (0x00000000U)
#define NV0000_CTRL_GPU_ID_INFO_ATS_ENABLED_TRUE (0x00000001U)
/*
* NV0000_CTRL_CMD_GPU_GET_INIT_STATUS
@@ -213,7 +213,7 @@ typedef struct NV0000_CTRL_GPU_GET_ID_INFO_V2_PARAMS {
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_INVALID_STATE
*/
#define NV0000_CTRL_CMD_GPU_GET_INIT_STATUS (0x203) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_GET_INIT_STATUS_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_CMD_GPU_GET_INIT_STATUS (0x203U) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_GET_INIT_STATUS_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_GPU_GET_INIT_STATUS_PARAMS_MESSAGE_ID (0x3U)
@@ -240,7 +240,7 @@ typedef struct NV0000_CTRL_GPU_GET_INIT_STATUS_PARAMS {
* NV_OK
* NV_ERR_INVALID_PARAM_STRUCT
*/
#define NV0000_CTRL_CMD_GPU_GET_DEVICE_IDS (0x204) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_GET_DEVICE_IDS_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_CMD_GPU_GET_DEVICE_IDS (0x204U) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_GET_DEVICE_IDS_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_GPU_GET_DEVICE_IDS_PARAMS_MESSAGE_ID (0x4U)
@@ -275,7 +275,7 @@ typedef struct NV0000_CTRL_GPU_GET_DEVICE_IDS_PARAMS {
* Possible status values returned are:
* NV_OK
*/
#define NV0000_CTRL_CMD_GPU_GET_PROBED_IDS (0x214) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_GET_PROBED_IDS_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_CMD_GPU_GET_PROBED_IDS (0x214U) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_GET_PROBED_IDS_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_GPU_MAX_PROBED_GPUS NV_MAX_DEVICES
@@ -312,7 +312,7 @@ typedef struct NV0000_CTRL_GPU_GET_PROBED_IDS_PARAMS {
* NV_ERR_NOT_SUPPORTED
* NV_ERR_INVALID_ARGUMENT
*/
#define NV0000_CTRL_CMD_GPU_GET_PCI_INFO (0x21b) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_GET_PCI_INFO_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_CMD_GPU_GET_PCI_INFO (0x21bU) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_GET_PCI_INFO_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_GPU_GET_PCI_INFO_PARAMS_MESSAGE_ID (0x1BU)
@@ -371,9 +371,9 @@ typedef struct NV0000_CTRL_GPU_GET_PCI_INFO_PARAMS {
* NV_ERR_IRQ_EDGE_TRIGGERED
* NV_ERR_IRQ_NOT_FIRING
*/
#define NV0000_CTRL_CMD_GPU_ATTACH_IDS (0x215) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_ATTACH_IDS_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_CMD_GPU_ATTACH_IDS (0x215U) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_ATTACH_IDS_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_GPU_ATTACH_ALL_PROBED_IDS (0x0000ffff)
#define NV0000_CTRL_GPU_ATTACH_ALL_PROBED_IDS (0x0000ffffU)
#define NV0000_CTRL_GPU_ATTACH_IDS_PARAMS_MESSAGE_ID (0x15U)
@@ -424,9 +424,9 @@ typedef struct NV0000_CTRL_GPU_ATTACH_IDS_PARAMS {
* NV_ERR_INVALID_PARAM_STRUCT
* NV_ERR_INVALID_ARGUMENT
*/
#define NV0000_CTRL_CMD_GPU_DETACH_IDS (0x216) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_DETACH_IDS_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_CMD_GPU_DETACH_IDS (0x216U) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_DETACH_IDS_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_GPU_DETACH_ALL_ATTACHED_IDS (0x0000ffff)
#define NV0000_CTRL_GPU_DETACH_ALL_ATTACHED_IDS (0x0000ffffU)
#define NV0000_CTRL_GPU_DETACH_IDS_PARAMS_MESSAGE_ID (0x16U)
@@ -455,7 +455,7 @@ typedef struct NV0000_CTRL_GPU_DETACH_IDS_PARAMS {
* NV_ERR_INVALID_STATE
*
*/
#define NV0000_CTRL_CMD_GPU_GET_SVM_SIZE (0x240) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_GET_SVM_SIZE_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_CMD_GPU_GET_SVM_SIZE (0x240U) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_GET_SVM_SIZE_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_GPU_GET_SVM_SIZE_PARAMS_MESSAGE_ID (0x40U)
@@ -504,10 +504,10 @@ typedef struct NV0000_CTRL_GPU_GET_SVM_SIZE_PARAMS {
* NV_ERR_OBJECT_NOT_FOUND
*
*/
#define NV0000_CTRL_CMD_GPU_GET_UUID_INFO (0x274) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_GET_UUID_INFO_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_CMD_GPU_GET_UUID_INFO (0x274U) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_GET_UUID_INFO_PARAMS_MESSAGE_ID" */
/* maximum possible number of bytes of GID information */
#define NV0000_GPU_MAX_GID_LENGTH (0x00000100)
#define NV0000_GPU_MAX_GID_LENGTH (0x00000100U)
#define NV0000_CTRL_GPU_GET_UUID_INFO_PARAMS_MESSAGE_ID (0x74U)
@@ -520,12 +520,12 @@ typedef struct NV0000_CTRL_GPU_GET_UUID_INFO_PARAMS {
} NV0000_CTRL_GPU_GET_UUID_INFO_PARAMS;
#define NV0000_CTRL_CMD_GPU_GET_UUID_INFO_FLAGS_FORMAT 1:0
#define NV0000_CTRL_CMD_GPU_GET_UUID_INFO_FLAGS_FORMAT_ASCII (0x00000000)
#define NV0000_CTRL_CMD_GPU_GET_UUID_INFO_FLAGS_FORMAT_BINARY (0x00000002)
#define NV0000_CTRL_CMD_GPU_GET_UUID_INFO_FLAGS_FORMAT_ASCII (0x00000000U)
#define NV0000_CTRL_CMD_GPU_GET_UUID_INFO_FLAGS_FORMAT_BINARY (0x00000002U)
#define NV0000_CTRL_CMD_GPU_GET_UUID_INFO_FLAGS_TYPE 2:2
#define NV0000_CTRL_CMD_GPU_GET_UUID_INFO_FLAGS_TYPE_SHA1 (0x00000000)
#define NV0000_CTRL_CMD_GPU_GET_UUID_INFO_FLAGS_TYPE_SHA256 (0x00000001)
#define NV0000_CTRL_CMD_GPU_GET_UUID_INFO_FLAGS_TYPE_SHA1 (0x00000000U)
#define NV0000_CTRL_CMD_GPU_GET_UUID_INFO_FLAGS_TYPE_SHA256 (0x00000001U)
/*
* NV0000_CTRL_CMD_GPU_GET_UUID_FROM_GPU_ID
@@ -566,7 +566,7 @@ typedef struct NV0000_CTRL_GPU_GET_UUID_INFO_PARAMS {
* NV_ERR_OBJECT_NOT_FOUND
* NV_ERR_OPERATING_SYSTEM
*/
#define NV0000_CTRL_CMD_GPU_GET_UUID_FROM_GPU_ID (0x275) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_GET_UUID_FROM_GPU_ID_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_CMD_GPU_GET_UUID_FROM_GPU_ID (0x275U) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_GET_UUID_FROM_GPU_ID_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_GPU_GET_UUID_FROM_GPU_ID_PARAMS_MESSAGE_ID (0x75U)
@@ -579,13 +579,13 @@ typedef struct NV0000_CTRL_GPU_GET_UUID_FROM_GPU_ID_PARAMS {
/* valid format values */
#define NV0000_CTRL_CMD_GPU_GET_UUID_FROM_GPU_ID_FLAGS_FORMAT 1:0
#define NV0000_CTRL_CMD_GPU_GET_UUID_FROM_GPU_ID_FLAGS_FORMAT_ASCII (0x00000000)
#define NV0000_CTRL_CMD_GPU_GET_UUID_FROM_GPU_ID_FLAGS_FORMAT_BINARY (0x00000002)
#define NV0000_CTRL_CMD_GPU_GET_UUID_FROM_GPU_ID_FLAGS_FORMAT_ASCII (0x00000000U)
#define NV0000_CTRL_CMD_GPU_GET_UUID_FROM_GPU_ID_FLAGS_FORMAT_BINARY (0x00000002U)
/*valid type values*/
#define NV0000_CTRL_CMD_GPU_GET_UUID_FROM_GPU_ID_FLAGS_TYPE 2:2
#define NV0000_CTRL_CMD_GPU_GET_UUID_FROM_GPU_ID_FLAGS_TYPE_SHA1 (0x00000000)
#define NV0000_CTRL_CMD_GPU_GET_UUID_FROM_GPU_ID_FLAGS_TYPE_SHA256 (0x00000001)
#define NV0000_CTRL_CMD_GPU_GET_UUID_FROM_GPU_ID_FLAGS_TYPE_SHA1 (0x00000000U)
#define NV0000_CTRL_CMD_GPU_GET_UUID_FROM_GPU_ID_FLAGS_TYPE_SHA256 (0x00000001U)
@@ -630,15 +630,15 @@ typedef struct NV0000_CTRL_GPU_GET_UUID_FROM_GPU_ID_PARAMS {
* NV_ERR_IN_USE
*/
#define NV0000_CTRL_CMD_GPU_MODIFY_DRAIN_STATE (0x278) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_MODIFY_DRAIN_STATE_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_CMD_GPU_MODIFY_DRAIN_STATE (0x278U) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_MODIFY_DRAIN_STATE_PARAMS_MESSAGE_ID" */
/* Possible values of newState */
#define NV0000_CTRL_GPU_DRAIN_STATE_DISABLED (0x00000000)
#define NV0000_CTRL_GPU_DRAIN_STATE_ENABLED (0x00000001)
#define NV0000_CTRL_GPU_DRAIN_STATE_DISABLED (0x00000000U)
#define NV0000_CTRL_GPU_DRAIN_STATE_ENABLED (0x00000001U)
/* Defined bits for the "flags" argument */
#define NV0000_CTRL_GPU_DRAIN_STATE_FLAG_REMOVE_DEVICE (0x00000001)
#define NV0000_CTRL_GPU_DRAIN_STATE_FLAG_LINK_DISABLE (0x00000002)
#define NV0000_CTRL_GPU_DRAIN_STATE_FLAG_REMOVE_DEVICE (0x00000001U)
#define NV0000_CTRL_GPU_DRAIN_STATE_FLAG_LINK_DISABLE (0x00000002U)
#define NV0000_CTRL_GPU_MODIFY_DRAIN_STATE_PARAMS_MESSAGE_ID (0x78U)
@@ -678,7 +678,7 @@ typedef struct NV0000_CTRL_GPU_MODIFY_DRAIN_STATE_PARAMS {
* NV_ERR_INVALID_ARGUMENT
*/
#define NV0000_CTRL_CMD_GPU_QUERY_DRAIN_STATE (0x279) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_QUERY_DRAIN_STATE_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_CMD_GPU_QUERY_DRAIN_STATE (0x279U) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_QUERY_DRAIN_STATE_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_GPU_QUERY_DRAIN_STATE_PARAMS_MESSAGE_ID (0x79U)
@@ -716,7 +716,7 @@ typedef struct NV0000_CTRL_GPU_QUERY_DRAIN_STATE_PARAMS {
* NV_ERR_NOT_SUPPORTED
*/
#define NV0000_CTRL_CMD_GPU_DISCOVER (0x27a) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | 0x7A" */
#define NV0000_CTRL_CMD_GPU_DISCOVER (0x27aU) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | 0x7A" */
typedef struct NV0000_CTRL_GPU_DISCOVER_PARAMS {
NvU32 domain;
@@ -740,7 +740,7 @@ typedef struct NV0000_CTRL_GPU_DISCOVER_PARAMS {
* NV_OK
*
*/
#define NV0000_CTRL_CMD_GPU_GET_MEMOP_ENABLE (0x27b) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_GET_MEMOP_ENABLE_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_CMD_GPU_GET_MEMOP_ENABLE (0x27bU) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_GET_MEMOP_ENABLE_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_GPU_GET_MEMOP_ENABLE_PARAMS_MESSAGE_ID (0x7BU)
@@ -748,7 +748,7 @@ typedef struct NV0000_CTRL_GPU_GET_MEMOP_ENABLE_PARAMS {
NvU32 enableMask;
} NV0000_CTRL_GPU_GET_MEMOP_ENABLE_PARAMS;
#define NV0000_CTRL_GPU_FLAGS_MEMOP_ENABLE (0x00000001)
#define NV0000_CTRL_GPU_FLAGS_MEMOP_ENABLE (0x00000001U)
@@ -770,7 +770,7 @@ typedef struct NV0000_CTRL_GPU_GET_MEMOP_ENABLE_PARAMS {
* NV_ERR_IN_USE
*
*/
#define NV0000_CTRL_CMD_GPU_DISABLE_NVLINK_INIT (0x281) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_DISABLE_NVLINK_INIT_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_CMD_GPU_DISABLE_NVLINK_INIT (0x281U) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_DISABLE_NVLINK_INIT_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_GPU_DISABLE_NVLINK_INIT_PARAMS_MESSAGE_ID (0x81U)
@@ -781,16 +781,16 @@ typedef struct NV0000_CTRL_GPU_DISABLE_NVLINK_INIT_PARAMS {
} NV0000_CTRL_GPU_DISABLE_NVLINK_INIT_PARAMS;
#define NV0000_CTRL_GPU_LEGACY_CONFIG_MAX_PARAM_DATA 0x00000175
#define NV0000_CTRL_GPU_LEGACY_CONFIG_MAX_PROPERTIES_IN 6
#define NV0000_CTRL_GPU_LEGACY_CONFIG_MAX_PROPERTIES_OUT 5
#define NV0000_CTRL_GPU_LEGACY_CONFIG_MAX_PARAM_DATA 0x00000175U
#define NV0000_CTRL_GPU_LEGACY_CONFIG_MAX_PROPERTIES_IN 6U
#define NV0000_CTRL_GPU_LEGACY_CONFIG_MAX_PROPERTIES_OUT 5U
/*
* NV0000_CTRL_CMD_GPU_LEGACY_CONFIG
*
* Path to use legacy RM GetConfig/Set API. This API is being phased out.
*/
#define NV0000_CTRL_CMD_GPU_LEGACY_CONFIG (0x282) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_LEGACY_CONFIG_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_CMD_GPU_LEGACY_CONFIG (0x282U) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_LEGACY_CONFIG_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_GPU_LEGACY_CONFIG_PARAMS_MESSAGE_ID (0x82U)
@@ -801,9 +801,6 @@ typedef struct NV0000_CTRL_GPU_LEGACY_CONFIG_PARAMS {
NvU32 dataType; /* [out] - data union type */
union {
struct {
NvV32 value;
} configGet;
struct {
NvU32 newValue;
NvU32 oldValue;
@@ -820,16 +817,15 @@ typedef struct NV0000_CTRL_GPU_LEGACY_CONFIG_PARAMS {
} data;
} NV0000_CTRL_GPU_LEGACY_CONFIG_PARAMS;
#define NV0000_CTRL_GPU_LEGACY_CONFIG_OP_TYPE_GET (0x00000000)
#define NV0000_CTRL_GPU_LEGACY_CONFIG_OP_TYPE_SET (0x00000001)
#define NV0000_CTRL_GPU_LEGACY_CONFIG_OP_TYPE_GET_EX (0x00000002)
#define NV0000_CTRL_GPU_LEGACY_CONFIG_OP_TYPE_SET_EX (0x00000003)
#define NV0000_CTRL_GPU_LEGACY_CONFIG_OP_TYPE_RESERVED (0x00000004)
#define NV0000_CTRL_GPU_LEGACY_CONFIG_OP_TYPE_SET (0x00000001U)
#define NV0000_CTRL_GPU_LEGACY_CONFIG_OP_TYPE_GET_EX (0x00000002U)
#define NV0000_CTRL_GPU_LEGACY_CONFIG_OP_TYPE_SET_EX (0x00000003U)
#define NV0000_CTRL_GPU_LEGACY_CONFIG_OP_TYPE_RESERVED (0x00000004U)
/*
* NV0000_CTRL_CMD_IDLE_CHANNELS
*/
#define NV0000_CTRL_CMD_IDLE_CHANNELS (0x283) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_IDLE_CHANNELS_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_CMD_IDLE_CHANNELS (0x283U) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_IDLE_CHANNELS_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_GPU_IDLE_CHANNELS_PARAMS_MESSAGE_ID (0x83U)
@@ -847,5 +843,31 @@ typedef struct NV0000_CTRL_GPU_IDLE_CHANNELS_PARAMS {
NvV32 timeout;
} NV0000_CTRL_GPU_IDLE_CHANNELS_PARAMS;
#define NV0000_CTRL_GPU_IMAGE_TYPE_GSP (0x00000001U)
#define NV0000_CTRL_GPU_IMAGE_TYPE_GSP_LOG (0x00000002U)
/*
* NV0000_CTRL_CMD_PUSH_GSP_UCODE
*
* This command is used to push the GSP ucode into RM.
* This function is used only on VMware
*
* Possible status values returned are:
* NV_OK The sent data is stored successfully
* NV_ERR_INVALID_ARGUMENT if the arguments are not proper
* NV_ERR_NO_MEMORY if memory allocation failed
* NV_ERR_NOT_SUPPORTED if function is invoked on non-GSP setup or any
* setup other than VMware host
*
*/
#define NV0000_CTRL_CMD_PUSH_GSP_UCODE (0x285) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_PUSH_GSP_UCODE_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_GPU_PUSH_GSP_UCODE_PARAMS_MESSAGE_ID (0x85U)
typedef struct NV0000_CTRL_GPU_PUSH_GSP_UCODE_PARAMS {
NvU8 image;
NV_DECLARE_ALIGNED(NvU64 totalSize, 8);
NV_DECLARE_ALIGNED(NvP64 pData, 8);
} NV0000_CTRL_GPU_PUSH_GSP_UCODE_PARAMS;
/* _ctrl0000gpu_h_ */

32
src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000gspc.h
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@@ -1,32 +0,0 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2005-2016 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl0000/ctrl0000gspc.finn
//

2017
src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000system.h
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File diff suppressed because it is too large Load Diff

5
src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000unix.h
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@@ -222,6 +222,9 @@ typedef struct NV0000_CTRL_OS_GET_GPU_INFO_PARAMS {
* deviceInstatnce
* This parameter returns a deviceInstance on which the object is located.
*
* NV_MAX_DEVICES is returned if the object is parented by a client instead
* of a device.
*
* maxObjects
* This parameter returns the maximum number of object handles that may be
* contained in the file descriptor.
@@ -416,6 +419,8 @@ typedef struct NV0000_CTRL_OS_UNIX_EXPORT_OBJECTS_TO_FD_PARAMS {
#define NV0000_CTRL_CMD_OS_UNIX_IMPORT_OBJECT_TYPE_SYSMEM 2
#define NV0000_CTRL_CMD_OS_UNIX_IMPORT_OBJECT_TYPE_FABRIC 3
#define NV0000_CTRL_OS_UNIX_IMPORT_OBJECTS_FROM_FD_PARAMS_MESSAGE_ID (0xCU)
typedef struct NV0000_CTRL_OS_UNIX_IMPORT_OBJECTS_FROM_FD_PARAMS {

48
src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000vgpu.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2016-2018 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2016-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -30,3 +30,49 @@
// Source file: ctrl/ctrl0000/ctrl0000vgpu.finn
//
#include "ctrl/ctrl0000/ctrl0000base.h"
#include "ctrl/ctrlxxxx.h"
#include "ctrl/ctrla081.h"
#include "class/cl0000.h"
#include "nv_vgpu_types.h"
/*
* NV0000_CTRL_CMD_VGPU_GET_START_DATA
*
* This command gets data associated with NV0000_NOTIFIERS_VGPU_MGR_START to
* start VGPU process.
*
* mdevUuid
* This parameter gives mdev device UUID for which nvidia-vgpu-mgr should
* init process.
*
* qemuPid
* This parameter specifies the QEMU process ID of the VM.
*
* gpuPciId
* This parameter provides gpuId of GPU on which vgpu device is created.
*
* configParams
* This parameter specifies the configuration parameters for vGPU
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_EVENT
* NV_ERR_OBJECT_NOT_FOUND
* NV_ERR_INVALID_CLIENT
*
*/
#define NV0000_CTRL_CMD_VGPU_GET_START_DATA (0xc01) /* finn: Evaluated from "(FINN_NV01_ROOT_VGPU_INTERFACE_ID << 8) | NV0000_CTRL_VGPU_GET_START_DATA_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_VGPU_GET_START_DATA_PARAMS_MESSAGE_ID (0x1U)
typedef struct NV0000_CTRL_VGPU_GET_START_DATA_PARAMS {
NvU8 mdevUuid[VM_UUID_SIZE];
NvU8 configParams[1024];
NvU32 qemuPid;
NvU32 gpuPciId;
NvU16 vgpuId;
NvU32 gpuPciBdf;
} NV0000_CTRL_VGPU_GET_START_DATA_PARAMS;
/* _ctrl0000vgpu_h_ */