mirror of
https://github.com/NVIDIA/open-gpu-kernel-modules.git
synced 2026-03-05 21:29:54 +00:00
525.53
This commit is contained in:
Andy Ritger
@@ -56,10 +56,10 @@
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* NV_ERR_INVALID_PARAM_STRUCT
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* NV_ERR_OPERATING_SYSTEM
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*/
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#define NV0000_CTRL_CMD_GPU_GET_ATTACHED_IDS (0x201) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_GET_ATTACHED_IDS_PARAMS_MESSAGE_ID" */
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#define NV0000_CTRL_CMD_GPU_GET_ATTACHED_IDS (0x201U) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_GET_ATTACHED_IDS_PARAMS_MESSAGE_ID" */
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#define NV0000_CTRL_GPU_MAX_ATTACHED_GPUS 32
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#define NV0000_CTRL_GPU_INVALID_ID (0xffffffff)
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#define NV0000_CTRL_GPU_MAX_ATTACHED_GPUS 32U
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#define NV0000_CTRL_GPU_INVALID_ID (0xffffffffU)
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#define NV0000_CTRL_GPU_GET_ATTACHED_IDS_PARAMS_MESSAGE_ID (0x1U)
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@@ -70,9 +70,9 @@ typedef struct NV0000_CTRL_GPU_GET_ATTACHED_IDS_PARAMS {
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/*
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* Deprecated. Please use NV0000_CTRL_CMD_GPU_GET_ID_INFO_V2 instead.
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*/
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#define NV0000_CTRL_CMD_GPU_GET_ID_INFO (0x202) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_GET_ID_INFO_PARAMS_MESSAGE_ID" */
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#define NV0000_CTRL_CMD_GPU_GET_ID_INFO (0x202U) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_GET_ID_INFO_PARAMS_MESSAGE_ID" */
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#define NV0000_CTRL_GPU_MAX_SZNAME 128
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#define NV0000_CTRL_GPU_MAX_SZNAME 128U
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#define NV0000_CTRL_NO_NUMA_NODE (-1)
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@@ -149,7 +149,7 @@ typedef struct NV0000_CTRL_GPU_GET_ID_INFO_PARAMS {
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#define NV0000_CTRL_CMD_GPU_GET_ID_INFO_V2 (0x205) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_GET_ID_INFO_V2_PARAMS_MESSAGE_ID" */
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#define NV0000_CTRL_CMD_GPU_GET_ID_INFO_V2 (0x205U) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_GET_ID_INFO_V2_PARAMS_MESSAGE_ID" */
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#define NV0000_CTRL_GPU_GET_ID_INFO_V2_PARAMS_MESSAGE_ID (0x5U)
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@@ -167,25 +167,25 @@ typedef struct NV0000_CTRL_GPU_GET_ID_INFO_V2_PARAMS {
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/* valid flags values */
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#define NV0000_CTRL_GPU_ID_INFO_IN_USE 0:0
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#define NV0000_CTRL_GPU_ID_INFO_IN_USE_FALSE (0x00000000)
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#define NV0000_CTRL_GPU_ID_INFO_IN_USE_TRUE (0x00000001)
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#define NV0000_CTRL_GPU_ID_INFO_IN_USE_FALSE (0x00000000U)
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#define NV0000_CTRL_GPU_ID_INFO_IN_USE_TRUE (0x00000001U)
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#define NV0000_CTRL_GPU_ID_INFO_LINKED_INTO_SLI_DEVICE 1:1
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#define NV0000_CTRL_GPU_ID_INFO_LINKED_INTO_SLI_DEVICE_FALSE (0x00000000)
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#define NV0000_CTRL_GPU_ID_INFO_LINKED_INTO_SLI_DEVICE_TRUE (0x00000001)
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#define NV0000_CTRL_GPU_ID_INFO_LINKED_INTO_SLI_DEVICE_FALSE (0x00000000U)
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#define NV0000_CTRL_GPU_ID_INFO_LINKED_INTO_SLI_DEVICE_TRUE (0x00000001U)
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#define NV0000_CTRL_GPU_ID_INFO_MOBILE 2:2
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#define NV0000_CTRL_GPU_ID_INFO_MOBILE_FALSE (0x00000000)
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#define NV0000_CTRL_GPU_ID_INFO_MOBILE_TRUE (0x00000001)
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#define NV0000_CTRL_GPU_ID_INFO_MOBILE_FALSE (0x00000000U)
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#define NV0000_CTRL_GPU_ID_INFO_MOBILE_TRUE (0x00000001U)
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#define NV0000_CTRL_GPU_ID_INFO_BOOT_MASTER 3:3
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#define NV0000_CTRL_GPU_ID_INFO_BOOT_MASTER_FALSE (0x00000000)
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#define NV0000_CTRL_GPU_ID_INFO_BOOT_MASTER_TRUE (0x00000001)
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#define NV0000_CTRL_GPU_ID_INFO_BOOT_MASTER_FALSE (0x00000000U)
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#define NV0000_CTRL_GPU_ID_INFO_BOOT_MASTER_TRUE (0x00000001U)
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#define NV0000_CTRL_GPU_ID_INFO_SOC 5:5
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#define NV0000_CTRL_GPU_ID_INFO_SOC_FALSE (0x00000000)
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#define NV0000_CTRL_GPU_ID_INFO_SOC_TRUE (0x00000001)
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#define NV0000_CTRL_GPU_ID_INFO_SOC_FALSE (0x00000000U)
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#define NV0000_CTRL_GPU_ID_INFO_SOC_TRUE (0x00000001U)
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#define NV0000_CTRL_GPU_ID_INFO_ATS_ENABLED 6:6
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#define NV0000_CTRL_GPU_ID_INFO_ATS_ENABLED_FALSE (0x00000000)
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#define NV0000_CTRL_GPU_ID_INFO_ATS_ENABLED_TRUE (0x00000001)
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#define NV0000_CTRL_GPU_ID_INFO_ATS_ENABLED_FALSE (0x00000000U)
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#define NV0000_CTRL_GPU_ID_INFO_ATS_ENABLED_TRUE (0x00000001U)
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/*
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* NV0000_CTRL_CMD_GPU_GET_INIT_STATUS
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@@ -213,7 +213,7 @@ typedef struct NV0000_CTRL_GPU_GET_ID_INFO_V2_PARAMS {
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* NV_ERR_INVALID_ARGUMENT
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* NV_ERR_INVALID_STATE
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*/
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#define NV0000_CTRL_CMD_GPU_GET_INIT_STATUS (0x203) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_GET_INIT_STATUS_PARAMS_MESSAGE_ID" */
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#define NV0000_CTRL_CMD_GPU_GET_INIT_STATUS (0x203U) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_GET_INIT_STATUS_PARAMS_MESSAGE_ID" */
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#define NV0000_CTRL_GPU_GET_INIT_STATUS_PARAMS_MESSAGE_ID (0x3U)
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@@ -240,7 +240,7 @@ typedef struct NV0000_CTRL_GPU_GET_INIT_STATUS_PARAMS {
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* NV_OK
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* NV_ERR_INVALID_PARAM_STRUCT
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*/
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#define NV0000_CTRL_CMD_GPU_GET_DEVICE_IDS (0x204) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_GET_DEVICE_IDS_PARAMS_MESSAGE_ID" */
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#define NV0000_CTRL_CMD_GPU_GET_DEVICE_IDS (0x204U) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_GET_DEVICE_IDS_PARAMS_MESSAGE_ID" */
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#define NV0000_CTRL_GPU_GET_DEVICE_IDS_PARAMS_MESSAGE_ID (0x4U)
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@@ -275,7 +275,7 @@ typedef struct NV0000_CTRL_GPU_GET_DEVICE_IDS_PARAMS {
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* Possible status values returned are:
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* NV_OK
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*/
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#define NV0000_CTRL_CMD_GPU_GET_PROBED_IDS (0x214) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_GET_PROBED_IDS_PARAMS_MESSAGE_ID" */
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#define NV0000_CTRL_CMD_GPU_GET_PROBED_IDS (0x214U) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_GET_PROBED_IDS_PARAMS_MESSAGE_ID" */
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#define NV0000_CTRL_GPU_MAX_PROBED_GPUS NV_MAX_DEVICES
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@@ -312,7 +312,7 @@ typedef struct NV0000_CTRL_GPU_GET_PROBED_IDS_PARAMS {
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* NV_ERR_NOT_SUPPORTED
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* NV_ERR_INVALID_ARGUMENT
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*/
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#define NV0000_CTRL_CMD_GPU_GET_PCI_INFO (0x21b) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_GET_PCI_INFO_PARAMS_MESSAGE_ID" */
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#define NV0000_CTRL_CMD_GPU_GET_PCI_INFO (0x21bU) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_GET_PCI_INFO_PARAMS_MESSAGE_ID" */
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#define NV0000_CTRL_GPU_GET_PCI_INFO_PARAMS_MESSAGE_ID (0x1BU)
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@@ -371,9 +371,9 @@ typedef struct NV0000_CTRL_GPU_GET_PCI_INFO_PARAMS {
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* NV_ERR_IRQ_EDGE_TRIGGERED
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* NV_ERR_IRQ_NOT_FIRING
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*/
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#define NV0000_CTRL_CMD_GPU_ATTACH_IDS (0x215) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_ATTACH_IDS_PARAMS_MESSAGE_ID" */
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#define NV0000_CTRL_CMD_GPU_ATTACH_IDS (0x215U) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_ATTACH_IDS_PARAMS_MESSAGE_ID" */
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#define NV0000_CTRL_GPU_ATTACH_ALL_PROBED_IDS (0x0000ffff)
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#define NV0000_CTRL_GPU_ATTACH_ALL_PROBED_IDS (0x0000ffffU)
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#define NV0000_CTRL_GPU_ATTACH_IDS_PARAMS_MESSAGE_ID (0x15U)
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@@ -424,9 +424,9 @@ typedef struct NV0000_CTRL_GPU_ATTACH_IDS_PARAMS {
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* NV_ERR_INVALID_PARAM_STRUCT
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* NV_ERR_INVALID_ARGUMENT
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*/
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#define NV0000_CTRL_CMD_GPU_DETACH_IDS (0x216) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_DETACH_IDS_PARAMS_MESSAGE_ID" */
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#define NV0000_CTRL_CMD_GPU_DETACH_IDS (0x216U) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_DETACH_IDS_PARAMS_MESSAGE_ID" */
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#define NV0000_CTRL_GPU_DETACH_ALL_ATTACHED_IDS (0x0000ffff)
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#define NV0000_CTRL_GPU_DETACH_ALL_ATTACHED_IDS (0x0000ffffU)
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#define NV0000_CTRL_GPU_DETACH_IDS_PARAMS_MESSAGE_ID (0x16U)
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@@ -455,7 +455,7 @@ typedef struct NV0000_CTRL_GPU_DETACH_IDS_PARAMS {
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* NV_ERR_INVALID_STATE
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*
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*/
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#define NV0000_CTRL_CMD_GPU_GET_SVM_SIZE (0x240) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_GET_SVM_SIZE_PARAMS_MESSAGE_ID" */
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#define NV0000_CTRL_CMD_GPU_GET_SVM_SIZE (0x240U) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_GET_SVM_SIZE_PARAMS_MESSAGE_ID" */
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#define NV0000_CTRL_GPU_GET_SVM_SIZE_PARAMS_MESSAGE_ID (0x40U)
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@@ -504,10 +504,10 @@ typedef struct NV0000_CTRL_GPU_GET_SVM_SIZE_PARAMS {
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* NV_ERR_OBJECT_NOT_FOUND
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*
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*/
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#define NV0000_CTRL_CMD_GPU_GET_UUID_INFO (0x274) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_GET_UUID_INFO_PARAMS_MESSAGE_ID" */
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#define NV0000_CTRL_CMD_GPU_GET_UUID_INFO (0x274U) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_GET_UUID_INFO_PARAMS_MESSAGE_ID" */
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/* maximum possible number of bytes of GID information */
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#define NV0000_GPU_MAX_GID_LENGTH (0x00000100)
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#define NV0000_GPU_MAX_GID_LENGTH (0x00000100U)
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#define NV0000_CTRL_GPU_GET_UUID_INFO_PARAMS_MESSAGE_ID (0x74U)
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@@ -520,12 +520,12 @@ typedef struct NV0000_CTRL_GPU_GET_UUID_INFO_PARAMS {
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} NV0000_CTRL_GPU_GET_UUID_INFO_PARAMS;
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#define NV0000_CTRL_CMD_GPU_GET_UUID_INFO_FLAGS_FORMAT 1:0
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#define NV0000_CTRL_CMD_GPU_GET_UUID_INFO_FLAGS_FORMAT_ASCII (0x00000000)
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#define NV0000_CTRL_CMD_GPU_GET_UUID_INFO_FLAGS_FORMAT_BINARY (0x00000002)
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#define NV0000_CTRL_CMD_GPU_GET_UUID_INFO_FLAGS_FORMAT_ASCII (0x00000000U)
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#define NV0000_CTRL_CMD_GPU_GET_UUID_INFO_FLAGS_FORMAT_BINARY (0x00000002U)
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#define NV0000_CTRL_CMD_GPU_GET_UUID_INFO_FLAGS_TYPE 2:2
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#define NV0000_CTRL_CMD_GPU_GET_UUID_INFO_FLAGS_TYPE_SHA1 (0x00000000)
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#define NV0000_CTRL_CMD_GPU_GET_UUID_INFO_FLAGS_TYPE_SHA256 (0x00000001)
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#define NV0000_CTRL_CMD_GPU_GET_UUID_INFO_FLAGS_TYPE_SHA1 (0x00000000U)
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#define NV0000_CTRL_CMD_GPU_GET_UUID_INFO_FLAGS_TYPE_SHA256 (0x00000001U)
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/*
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* NV0000_CTRL_CMD_GPU_GET_UUID_FROM_GPU_ID
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@@ -566,7 +566,7 @@ typedef struct NV0000_CTRL_GPU_GET_UUID_INFO_PARAMS {
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* NV_ERR_OBJECT_NOT_FOUND
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* NV_ERR_OPERATING_SYSTEM
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*/
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#define NV0000_CTRL_CMD_GPU_GET_UUID_FROM_GPU_ID (0x275) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_GET_UUID_FROM_GPU_ID_PARAMS_MESSAGE_ID" */
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#define NV0000_CTRL_CMD_GPU_GET_UUID_FROM_GPU_ID (0x275U) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_GET_UUID_FROM_GPU_ID_PARAMS_MESSAGE_ID" */
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#define NV0000_CTRL_GPU_GET_UUID_FROM_GPU_ID_PARAMS_MESSAGE_ID (0x75U)
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@@ -579,13 +579,13 @@ typedef struct NV0000_CTRL_GPU_GET_UUID_FROM_GPU_ID_PARAMS {
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/* valid format values */
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#define NV0000_CTRL_CMD_GPU_GET_UUID_FROM_GPU_ID_FLAGS_FORMAT 1:0
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#define NV0000_CTRL_CMD_GPU_GET_UUID_FROM_GPU_ID_FLAGS_FORMAT_ASCII (0x00000000)
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#define NV0000_CTRL_CMD_GPU_GET_UUID_FROM_GPU_ID_FLAGS_FORMAT_BINARY (0x00000002)
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#define NV0000_CTRL_CMD_GPU_GET_UUID_FROM_GPU_ID_FLAGS_FORMAT_ASCII (0x00000000U)
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#define NV0000_CTRL_CMD_GPU_GET_UUID_FROM_GPU_ID_FLAGS_FORMAT_BINARY (0x00000002U)
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/*valid type values*/
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#define NV0000_CTRL_CMD_GPU_GET_UUID_FROM_GPU_ID_FLAGS_TYPE 2:2
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#define NV0000_CTRL_CMD_GPU_GET_UUID_FROM_GPU_ID_FLAGS_TYPE_SHA1 (0x00000000)
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#define NV0000_CTRL_CMD_GPU_GET_UUID_FROM_GPU_ID_FLAGS_TYPE_SHA256 (0x00000001)
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#define NV0000_CTRL_CMD_GPU_GET_UUID_FROM_GPU_ID_FLAGS_TYPE_SHA1 (0x00000000U)
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#define NV0000_CTRL_CMD_GPU_GET_UUID_FROM_GPU_ID_FLAGS_TYPE_SHA256 (0x00000001U)
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@@ -630,15 +630,15 @@ typedef struct NV0000_CTRL_GPU_GET_UUID_FROM_GPU_ID_PARAMS {
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* NV_ERR_IN_USE
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*/
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#define NV0000_CTRL_CMD_GPU_MODIFY_DRAIN_STATE (0x278) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_MODIFY_DRAIN_STATE_PARAMS_MESSAGE_ID" */
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#define NV0000_CTRL_CMD_GPU_MODIFY_DRAIN_STATE (0x278U) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_MODIFY_DRAIN_STATE_PARAMS_MESSAGE_ID" */
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/* Possible values of newState */
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#define NV0000_CTRL_GPU_DRAIN_STATE_DISABLED (0x00000000)
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#define NV0000_CTRL_GPU_DRAIN_STATE_ENABLED (0x00000001)
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#define NV0000_CTRL_GPU_DRAIN_STATE_DISABLED (0x00000000U)
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#define NV0000_CTRL_GPU_DRAIN_STATE_ENABLED (0x00000001U)
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/* Defined bits for the "flags" argument */
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#define NV0000_CTRL_GPU_DRAIN_STATE_FLAG_REMOVE_DEVICE (0x00000001)
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#define NV0000_CTRL_GPU_DRAIN_STATE_FLAG_LINK_DISABLE (0x00000002)
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#define NV0000_CTRL_GPU_DRAIN_STATE_FLAG_REMOVE_DEVICE (0x00000001U)
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#define NV0000_CTRL_GPU_DRAIN_STATE_FLAG_LINK_DISABLE (0x00000002U)
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#define NV0000_CTRL_GPU_MODIFY_DRAIN_STATE_PARAMS_MESSAGE_ID (0x78U)
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@@ -678,7 +678,7 @@ typedef struct NV0000_CTRL_GPU_MODIFY_DRAIN_STATE_PARAMS {
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* NV_ERR_INVALID_ARGUMENT
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*/
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#define NV0000_CTRL_CMD_GPU_QUERY_DRAIN_STATE (0x279) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_QUERY_DRAIN_STATE_PARAMS_MESSAGE_ID" */
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#define NV0000_CTRL_CMD_GPU_QUERY_DRAIN_STATE (0x279U) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_QUERY_DRAIN_STATE_PARAMS_MESSAGE_ID" */
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#define NV0000_CTRL_GPU_QUERY_DRAIN_STATE_PARAMS_MESSAGE_ID (0x79U)
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@@ -716,7 +716,7 @@ typedef struct NV0000_CTRL_GPU_QUERY_DRAIN_STATE_PARAMS {
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* NV_ERR_NOT_SUPPORTED
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*/
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#define NV0000_CTRL_CMD_GPU_DISCOVER (0x27a) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | 0x7A" */
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#define NV0000_CTRL_CMD_GPU_DISCOVER (0x27aU) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | 0x7A" */
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typedef struct NV0000_CTRL_GPU_DISCOVER_PARAMS {
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NvU32 domain;
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@@ -740,7 +740,7 @@ typedef struct NV0000_CTRL_GPU_DISCOVER_PARAMS {
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* NV_OK
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*
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||||
*/
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#define NV0000_CTRL_CMD_GPU_GET_MEMOP_ENABLE (0x27b) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_GET_MEMOP_ENABLE_PARAMS_MESSAGE_ID" */
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||||
#define NV0000_CTRL_CMD_GPU_GET_MEMOP_ENABLE (0x27bU) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_GET_MEMOP_ENABLE_PARAMS_MESSAGE_ID" */
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#define NV0000_CTRL_GPU_GET_MEMOP_ENABLE_PARAMS_MESSAGE_ID (0x7BU)
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@@ -748,7 +748,7 @@ typedef struct NV0000_CTRL_GPU_GET_MEMOP_ENABLE_PARAMS {
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NvU32 enableMask;
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} NV0000_CTRL_GPU_GET_MEMOP_ENABLE_PARAMS;
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#define NV0000_CTRL_GPU_FLAGS_MEMOP_ENABLE (0x00000001)
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#define NV0000_CTRL_GPU_FLAGS_MEMOP_ENABLE (0x00000001U)
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@@ -770,7 +770,7 @@ typedef struct NV0000_CTRL_GPU_GET_MEMOP_ENABLE_PARAMS {
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* NV_ERR_IN_USE
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||||
*
|
||||
*/
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#define NV0000_CTRL_CMD_GPU_DISABLE_NVLINK_INIT (0x281) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_DISABLE_NVLINK_INIT_PARAMS_MESSAGE_ID" */
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||||
#define NV0000_CTRL_CMD_GPU_DISABLE_NVLINK_INIT (0x281U) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_DISABLE_NVLINK_INIT_PARAMS_MESSAGE_ID" */
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#define NV0000_CTRL_GPU_DISABLE_NVLINK_INIT_PARAMS_MESSAGE_ID (0x81U)
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@@ -781,16 +781,16 @@ typedef struct NV0000_CTRL_GPU_DISABLE_NVLINK_INIT_PARAMS {
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} NV0000_CTRL_GPU_DISABLE_NVLINK_INIT_PARAMS;
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||||
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#define NV0000_CTRL_GPU_LEGACY_CONFIG_MAX_PARAM_DATA 0x00000175
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||||
#define NV0000_CTRL_GPU_LEGACY_CONFIG_MAX_PROPERTIES_IN 6
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||||
#define NV0000_CTRL_GPU_LEGACY_CONFIG_MAX_PROPERTIES_OUT 5
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||||
#define NV0000_CTRL_GPU_LEGACY_CONFIG_MAX_PARAM_DATA 0x00000175U
|
||||
#define NV0000_CTRL_GPU_LEGACY_CONFIG_MAX_PROPERTIES_IN 6U
|
||||
#define NV0000_CTRL_GPU_LEGACY_CONFIG_MAX_PROPERTIES_OUT 5U
|
||||
|
||||
/*
|
||||
* NV0000_CTRL_CMD_GPU_LEGACY_CONFIG
|
||||
*
|
||||
* Path to use legacy RM GetConfig/Set API. This API is being phased out.
|
||||
*/
|
||||
#define NV0000_CTRL_CMD_GPU_LEGACY_CONFIG (0x282) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_LEGACY_CONFIG_PARAMS_MESSAGE_ID" */
|
||||
#define NV0000_CTRL_CMD_GPU_LEGACY_CONFIG (0x282U) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_LEGACY_CONFIG_PARAMS_MESSAGE_ID" */
|
||||
|
||||
#define NV0000_CTRL_GPU_LEGACY_CONFIG_PARAMS_MESSAGE_ID (0x82U)
|
||||
|
||||
@@ -801,9 +801,6 @@ typedef struct NV0000_CTRL_GPU_LEGACY_CONFIG_PARAMS {
|
||||
NvU32 dataType; /* [out] - data union type */
|
||||
|
||||
union {
|
||||
struct {
|
||||
NvV32 value;
|
||||
} configGet;
|
||||
struct {
|
||||
NvU32 newValue;
|
||||
NvU32 oldValue;
|
||||
@@ -820,16 +817,15 @@ typedef struct NV0000_CTRL_GPU_LEGACY_CONFIG_PARAMS {
|
||||
} data;
|
||||
} NV0000_CTRL_GPU_LEGACY_CONFIG_PARAMS;
|
||||
|
||||
#define NV0000_CTRL_GPU_LEGACY_CONFIG_OP_TYPE_GET (0x00000000)
|
||||
#define NV0000_CTRL_GPU_LEGACY_CONFIG_OP_TYPE_SET (0x00000001)
|
||||
#define NV0000_CTRL_GPU_LEGACY_CONFIG_OP_TYPE_GET_EX (0x00000002)
|
||||
#define NV0000_CTRL_GPU_LEGACY_CONFIG_OP_TYPE_SET_EX (0x00000003)
|
||||
#define NV0000_CTRL_GPU_LEGACY_CONFIG_OP_TYPE_RESERVED (0x00000004)
|
||||
#define NV0000_CTRL_GPU_LEGACY_CONFIG_OP_TYPE_SET (0x00000001U)
|
||||
#define NV0000_CTRL_GPU_LEGACY_CONFIG_OP_TYPE_GET_EX (0x00000002U)
|
||||
#define NV0000_CTRL_GPU_LEGACY_CONFIG_OP_TYPE_SET_EX (0x00000003U)
|
||||
#define NV0000_CTRL_GPU_LEGACY_CONFIG_OP_TYPE_RESERVED (0x00000004U)
|
||||
|
||||
/*
|
||||
* NV0000_CTRL_CMD_IDLE_CHANNELS
|
||||
*/
|
||||
#define NV0000_CTRL_CMD_IDLE_CHANNELS (0x283) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_IDLE_CHANNELS_PARAMS_MESSAGE_ID" */
|
||||
#define NV0000_CTRL_CMD_IDLE_CHANNELS (0x283U) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_IDLE_CHANNELS_PARAMS_MESSAGE_ID" */
|
||||
|
||||
#define NV0000_CTRL_GPU_IDLE_CHANNELS_PARAMS_MESSAGE_ID (0x83U)
|
||||
|
||||
@@ -847,5 +843,31 @@ typedef struct NV0000_CTRL_GPU_IDLE_CHANNELS_PARAMS {
|
||||
NvV32 timeout;
|
||||
} NV0000_CTRL_GPU_IDLE_CHANNELS_PARAMS;
|
||||
|
||||
#define NV0000_CTRL_GPU_IMAGE_TYPE_GSP (0x00000001U)
|
||||
#define NV0000_CTRL_GPU_IMAGE_TYPE_GSP_LOG (0x00000002U)
|
||||
|
||||
/*
|
||||
* NV0000_CTRL_CMD_PUSH_GSP_UCODE
|
||||
*
|
||||
* This command is used to push the GSP ucode into RM.
|
||||
* This function is used only on VMware
|
||||
*
|
||||
* Possible status values returned are:
|
||||
* NV_OK The sent data is stored successfully
|
||||
* NV_ERR_INVALID_ARGUMENT if the arguments are not proper
|
||||
* NV_ERR_NO_MEMORY if memory allocation failed
|
||||
* NV_ERR_NOT_SUPPORTED if function is invoked on non-GSP setup or any
|
||||
* setup other than VMware host
|
||||
*
|
||||
*/
|
||||
#define NV0000_CTRL_CMD_PUSH_GSP_UCODE (0x285) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_PUSH_GSP_UCODE_PARAMS_MESSAGE_ID" */
|
||||
|
||||
#define NV0000_CTRL_GPU_PUSH_GSP_UCODE_PARAMS_MESSAGE_ID (0x85U)
|
||||
|
||||
typedef struct NV0000_CTRL_GPU_PUSH_GSP_UCODE_PARAMS {
|
||||
NvU8 image;
|
||||
NV_DECLARE_ALIGNED(NvU64 totalSize, 8);
|
||||
NV_DECLARE_ALIGNED(NvP64 pData, 8);
|
||||
} NV0000_CTRL_GPU_PUSH_GSP_UCODE_PARAMS;
|
||||
/* _ctrl0000gpu_h_ */
|
||||
|
||||
|
||||
Reference in New Issue
Block a user