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This commit is contained in:
Andy Ritger
2022-11-10 08:39:33 -08:00
parent 7c345b838b
commit 758b4ee818
1323 changed files with 262135 additions and 60754 deletions
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2
src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080dma.h
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@@ -696,7 +696,7 @@ typedef struct NV0080_CTRL_DMA_UPDATE_PDE_2_PARAMS {
NvU32 flags;
NV_DECLARE_ALIGNED(NV0080_CTRL_DMA_UPDATE_PDE_2_PAGE_TABLE_PARAMS ptParams[NV0080_CTRL_DMA_UPDATE_PDE_2_PT_IDX__SIZE], 8);
NvHandle hVASpace;
NV_DECLARE_ALIGNED(NvP64 pPdeBuffer, 8); // NV_MMU_VER2_PDE__SIZE
NV_DECLARE_ALIGNED(NvP64 pPdeBuffer, 8); // NV_MMU_VER2_DUAL_PDE__SIZE
NvU32 subDeviceId; // ID+1, 0 for BC
} NV0080_CTRL_DMA_UPDATE_PDE_2_PARAMS;

2
src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080fifo.h
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@@ -192,7 +192,7 @@ typedef struct NV0080_CTRL_FIFO_CHANNEL {
#define NV0080_CTRL_FIFO_START_SELECTED_CHANNELS_PARAMS_MESSAGE_ID (0x5U)
typedef struct NV0080_CTRL_FIFO_START_SELECTED_CHANNELS_PARAMS {
NvU32 fifoStartChannelListSize;
NvU32 fifoStartChannelListCount;
NvHandle channelHandle[8];
NV_DECLARE_ALIGNED(NvP64 fifoStartChannelList, 8);
} NV0080_CTRL_FIFO_START_SELECTED_CHANNELS_PARAMS;

2
src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080gpu.h
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@@ -494,7 +494,7 @@ typedef struct NV0080_CTRL_GPU_GET_SRIOV_CAPS_PARAMS {
// Update this macro if new HW exceeds GPU Classlist MAX_SIZE
#define NV0080_CTRL_GPU_CLASSLIST_MAX_SIZE 116
#define NV0080_CTRL_GPU_CLASSLIST_MAX_SIZE 160
#define NV0080_CTRL_CMD_GPU_GET_CLASSLIST_V2 (0x800292) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GPU_INTERFACE_ID << 8) | NV0080_CTRL_GPU_GET_CLASSLIST_V2_PARAMS_MESSAGE_ID" */

5
src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080gr.h
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@@ -150,13 +150,14 @@ typedef struct NV0080_CTRL_GR_INFO {
#define NV0080_CTRL_GR_INFO_INDEX_MAX_PER_ENGINE_SUBCONTEXT_COUNT (0x0000002E)
#define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_SLICES_PER_LTC (0x00000032)
/* When adding a new INDEX, please update MAX_SIZE accordingly
* NOTE: 0080 functionality is merged with 2080 functionality, so this max size
* reflects that.
*/
#define NV0080_CTRL_GR_INFO_INDEX_MAX (0x00000031)
#define NV0080_CTRL_GR_INFO_MAX_SIZE (0x32) /* finn: Evaluated from "(NV0080_CTRL_GR_INFO_INDEX_MAX + 1)" */
#define NV0080_CTRL_GR_INFO_INDEX_MAX (0x00000032)
#define NV0080_CTRL_GR_INFO_MAX_SIZE (0x33) /* finn: Evaluated from "(NV0080_CTRL_GR_INFO_INDEX_MAX + 1)" */
/*
* NV0080_CTRL_CMD_GR_GET_INFO

15
src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080unix.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2015-2015 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2015-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -59,21 +59,10 @@
*/
#define NV0080_CTRL_CMD_OS_UNIX_VT_SWITCH (0x801e01) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_OS_UNIX_INTERFACE_ID << 8) | NV0080_CTRL_OS_UNIX_VT_SWITCH_PARAMS_MESSAGE_ID" */
typedef struct NV0080_CTRL_OS_UNIX_VT_SWITCH_FB_INFO {
NvU32 subDeviceInstance;
NvU16 width;
NvU16 height;
NvU16 depth;
NvU16 pitch;
} NV0080_CTRL_OS_UNIX_VT_SWITCH_FB_INFO;
#define NV0080_CTRL_OS_UNIX_VT_SWITCH_PARAMS_MESSAGE_ID (0x1U)
typedef struct NV0080_CTRL_OS_UNIX_VT_SWITCH_PARAMS {
NvU32 cmd; /* in */
NV0080_CTRL_OS_UNIX_VT_SWITCH_FB_INFO fbInfo; /* out */
NvU32 cmd; /* in */
} NV0080_CTRL_OS_UNIX_VT_SWITCH_PARAMS;
/* Called when the display driver needs RM to save the console data,