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This commit is contained in:
Andy Ritger
2022-11-10 08:39:33 -08:00
parent 7c345b838b
commit 758b4ee818
1323 changed files with 262135 additions and 60754 deletions
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237
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080bios.h
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@@ -106,6 +106,243 @@ typedef struct NV2080_CTRL_BIOS_GET_INFO_V2_PARAMS {
NV2080_CTRL_BIOS_INFO biosInfoList[NV2080_CTRL_BIOS_INFO_MAX_SIZE];
} NV2080_CTRL_BIOS_GET_INFO_V2_PARAMS;
/*
* NV2080_CTRL_BIOS_NBSI
*
* NV2080_CTRL_BIOS_NBSI_MAX_REG_STRING_LENGTH
* This is the maximum length of a given registry string input (in characters).
*
* NV2080_CTRL_BIOS_NBSI_STRING_TYPE_ASCII
* This is a value indicating the format of a registry string is ascii.
* NV2080_CTRL_BIOS_NBSI_STRING_TYPE_UNICODE
* This is a value indicating the format of a registry string is unicode.
* NV2080_CTRL_BIOS_NBSI_STRING_TYPE_HASH
* This is a value indicating a registry string is actually a pre-hashed value.
*
* NV2080_CTRL_BIOS_NBSI_REG_STRING
* This is a structure used to store a registry string object.
* The members are as follows:
*
* size
* This is the size (in bytes) of the data contained in the string. If this
* is greater than the maximum registry string length, an error will be
* returned.
* type
* This is the type of data contained in the registry string. It can be either
* ascii, unicode or a pre-hashed value.
* value
* This is the value of the string. Depending on the type, a different object
* will be used to access the data.
*/
#define NV2080_CTRL_BIOS_NBSI_MAX_REG_STRING_LENGTH (0x00000100)
#define NV2080_CTRL_BIOS_NBSI_STRING_TYPE_ASCII (0x00000000)
#define NV2080_CTRL_BIOS_NBSI_STRING_TYPE_UNICODE (0x00000001)
#define NV2080_CTRL_BIOS_NBSI_STRING_TYPE_HASH (0x00000002)
#define NV2080_CTRL_BIOS_NBSI_MODULE_ROOT (0x00000000)
#define NV2080_CTRL_BIOS_NBSI_MODULE_RM (0x00000001)
#define NV2080_CTRL_BIOS_NBSI_MODULE_DISPLAYDRIVER (0x00000002)
#define NV2080_CTRL_BIOS_NBSI_MODULE_VIDEO (0x00000003)
#define NV2080_CTRL_BIOS_NBSI_MODULE_CPL (0x00000004)
#define NV2080_CTRL_BIOS_NBSI_MODULE_D3D (0x00000005)
#define NV2080_CTRL_BIOS_NBSI_MODULE_OGL (0x00000006)
#define NV2080_CTRL_BIOS_NBSI_MODULE_PMU (0x00000007)
#define NV2080_CTRL_BIOS_NBSI_MODULE_MODE (0x00000008)
// this should equal the last NBSI_MODULE plus 1.
#define NV2080_CTRL_BIOS_NBSI_NUM_MODULES (0x00000009)
//
// Never use this value! It's needed for DD/Video modules, but does not correspond
// to a valid NBSI hive!
//
#define NV2080_CTRL_BIOS_NBSI_MODULE_UNKNOWN (0x80000000)
typedef struct NV2080_CTRL_BIOS_NBSI_REG_STRING {
NvU32 size;
NvU32 type;
union {
NvU8 ascii[NV2080_CTRL_BIOS_NBSI_MAX_REG_STRING_LENGTH];
NvU16 unicode[NV2080_CTRL_BIOS_NBSI_MAX_REG_STRING_LENGTH];
NvU16 hash;
} value;
} NV2080_CTRL_BIOS_NBSI_REG_STRING;
/*
* NV2080_CTRL_CMD_BIOS_GET_NBSI
*
* module
* This field specifies the given module per the MODULE_TYPES enum.
* path
* This field specifies the full path and registry node name for a
* given NBSI object. This is a maximum of 255 unicode characters,
* but may be provided as ascii or a pre-formed hash per the type
* member. The size (in bytes) of the given string/hash should be
* provided in the size member.
*
* NOTE: In the case of an incomplete path such as HKR, one may pass
* in simply the root node. E.g.:
* 1.) Normal case: HKLM\Path\Subpath
* 2.) Unknown case: HKR
* It is expected that all unknown/incomplete paths will be determined
* prior to NBSI programming! There is otherwise NO WAY to match
* the hash given by an incomplete path to that stored in NBSI!
*
* valueName
* This field specifies the registry name for a given NBSI object.
* This is a maximum of 255 unicode characters, but may be provided
* in ascii or a pre-formed hash per the type member. The size (in bytes)
* of the given string/hash should be provided in the size member.
* retBuf
* This field provides a pointer to a buffer into which the value
* retrieved from NBSI may be returned
* retSize
* This field is an input/output. It specifies the maximum size of the
* return buffer as an input, and the size of the returned data as an
* output.
* errorCode
* This field is a return value. It gives an error code representing
* failure to return a value (as opposed to failure of the call).
* This obeys the following:
*
* NV2080_CTRL_BIOS_GET_NBSI_SUCCESS
* The call has returned complete and valid data.
* NV2080_CTRL_BIOS_GET_NBSI_OVERRIDE
* The call returned complete and valid data which is expected to override
* any stored registry settings.
* NV2080_CTRL_BIOS_GET_NBSI_INCOMPLETE
* The call returned data, but the size of the return buffer was
* insufficient to contain it. The value returned in retSize represents
* the total size necessary (in bytes) to contain the data.
* if the size was non-0, the buffer is filled with the object contents up
* to that size. Can be used with retBufOffset to use multiple calls to get
* tables of very large size.
* NV2080_CTRL_BIOS_GET_NBSI_NOT_FOUND
* The call did not find a valid NBSI object for this key. This indicates
* NBSI has no opinion and, more importantly, any data returned is identical
* to data passed in.
*
* Possible return values are:
* NV_OK
* NV_ERR_INVALID_PARAM_STRUCT
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_NOT_SUPPORTED
*/
#define NV2080_CTRL_BIOS_GET_NBSI_SUCCESS (0x00000000)
#define NV2080_CTRL_BIOS_GET_NBSI_OVERRIDE (0x00000001)
#define NV2080_CTRL_BIOS_GET_NBSI_BAD_HASH (0xFFFFFFFA)
#define NV2080_CTRL_BIOS_GET_NBSI_APITEST_SUCCESS (0xFFFFFFFB)
#define NV2080_CTRL_BIOS_GET_NBSI_BAD_TABLE (0xFFFFFFFC)
#define NV2080_CTRL_BIOS_GET_NBSI_NO_TABLE (0xFFFFFFFD)
#define NV2080_CTRL_BIOS_GET_NBSI_INCOMPLETE (0xFFFFFFFE)
#define NV2080_CTRL_BIOS_GET_NBSI_NOT_FOUND (0xFFFFFFFF)
#define NV2080_CTRL_CMD_BIOS_GET_NBSI (0x20800803) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BIOS_INTERFACE_ID << 8) | NV2080_CTRL_BIOS_GET_NBSI_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_BIOS_GET_NBSI_PARAMS_MESSAGE_ID (0x3U)
typedef struct NV2080_CTRL_BIOS_GET_NBSI_PARAMS {
NvU32 module;
NV2080_CTRL_BIOS_NBSI_REG_STRING path;
NV2080_CTRL_BIOS_NBSI_REG_STRING valueName;
NV_DECLARE_ALIGNED(NvP64 retBuf, 8);
NvU32 retSize;
NvU32 errorCode;
} NV2080_CTRL_BIOS_GET_NBSI_PARAMS;
#define NV2080_CTRL_CMD_BIOS_GET_NBSI_V2 (0x2080080e) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BIOS_INTERFACE_ID << 8) | NV2080_CTRL_BIOS_GET_NBSI_V2_PARAMS_MESSAGE_ID" */
#define NV2080_BIOS_GET_NBSI_MAX_RET_SIZE (0x100)
#define NV2080_CTRL_BIOS_GET_NBSI_V2_PARAMS_MESSAGE_ID (0xEU)
typedef struct NV2080_CTRL_BIOS_GET_NBSI_V2_PARAMS {
NvU32 module;
NV2080_CTRL_BIOS_NBSI_REG_STRING path;
NV2080_CTRL_BIOS_NBSI_REG_STRING valueName;
NvU8 retBuf[NV2080_BIOS_GET_NBSI_MAX_RET_SIZE];
NvU32 retSize;
NvU32 errorCode;
} NV2080_CTRL_BIOS_GET_NBSI_V2_PARAMS;
/*
* NV2080_CTRL_CMD_BIOS_GET_NBSI_OBJ
*
* globType
* This field specifies the glob type wanted
* 0xffff: APItest... returns NV2080_CTRL_BIOS_GET_NBSI_APITEST_SUCCESS
* globIndex
* Index for globType desired
* 0 = best fit
* 1..255 = actual index
* globSource
* Index to nbsi directory sources used when getting entire directory
* 0 = registry
* 1 = VBIOS
* 2 = SBIOS
* 3 = ACPI
* retBufOffset
* When making multiple calls to get the object (if retSize is too small)
* offset into real object (0=start of object)
* retBuf
* This field provides a pointer to a buffer into which the object
* retrieved from NBSI may be returned
* retSize
* This field is an input/output. It specifies the maximum size of the
* return buffer as an input, and the size of the returned data as an
* output.
* totalObjSize
* This field is an output, where the total size of the object being
* retrieved is returned.
* errorCode
* This field is a return value. It gives an error code representing
* failure to return a value (as opposed to failure of the call).
* This obeys the following:
*
* NV2080_CTRL_BIOS_GET_NBSI_SUCCESS
* The call has returned complete and valid data.
* NV2080_CTRL_BIOS_GET_NBSI_OVERRIDE
* The call returned complete and valid data which is expected to override
* any stored registry settings.
* NV2080_CTRL_BIOS_GET_NBSI_INCOMPLETE
* The call returned data, but the size of the return buffer was
* insufficient to contain it. The value returned in retSize represents
* the total size necessary (in bytes) to contain the data.
* NV2080_CTRL_BIOS_GET_NBSI_NOT_FOUND
* The call did not find a valid NBSI object for this key. This indicates
* NBSI has no opinion and, more importantly, any data returned is identical
* to data passed in.
*
* Possible return values are:
* NV2080_CTRL_BIOS_GET_NBSI_SUCCESS
* NV2080_CTRL_BIOS_GET_NBSI_APITEST_NODIRACCESS
* NV2080_CTRL_BIOS_GET_NBSI_APITEST_SUCCESS
* NV2080_CTRL_BIOS_GET_NBSI_INCOMPLETE
* NV2080_CTRL_BIOS_GET_NBSI_BAD_TABLE
* NV2080_CTRL_BIOS_GET_NBSI_NO_TABLE
* NV2080_CTRL_BIOS_GET_NBSI_NOT_FOUND
*/
#define NV2080_CTRL_CMD_BIOS_GET_NBSI_OBJ (0x20800806) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BIOS_INTERFACE_ID << 8) | NV2080_CTRL_BIOS_GET_NBSI_OBJ_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_BIOS_GET_NBSI_OBJ_PARAMS_MESSAGE_ID (0x6U)
typedef struct NV2080_CTRL_BIOS_GET_NBSI_OBJ_PARAMS {
NvU16 globType;
NvU8 globIndex;
NvU16 globSource;
NvU32 retBufOffset;
NV_DECLARE_ALIGNED(NvP64 retBuf, 8);
NvU32 retSize;
NvU32 totalObjSize;
NvU32 errorCode;
} NV2080_CTRL_BIOS_GET_NBSI_OBJ_PARAMS;
#define GLOB_TYPE_GET_NBSI_DIR 0xfffe
#define GLOB_TYPE_APITEST 0xffff
#define GLOB_TYPE_GET_NBSI_ACPI_RAW 0xfffd
/*

94
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080bus.h
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@@ -363,6 +363,7 @@ typedef struct NV2080_CTRL_BUS_INFO {
#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_MAX_SPEED_8000MBPS (0x00000003)
#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_MAX_SPEED_16000MBPS (0x00000004)
#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_MAX_SPEED_32000MBPS (0x00000005)
#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_MAX_SPEED_64000MBPS (0x00000006)
#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_MAX_WIDTH 9:4
#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_ASPM 11:10
#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_ASPM_NONE (0x00000000)
@@ -374,18 +375,21 @@ typedef struct NV2080_CTRL_BUS_INFO {
#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GEN_GEN3 (0x00000002)
#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GEN_GEN4 (0x00000003)
#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GEN_GEN5 (0x00000004)
#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GEN_GEN6 (0x00000005)
#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_CURR_LEVEL 19:16
#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_CURR_LEVEL_GEN1 (0x00000000)
#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_CURR_LEVEL_GEN2 (0x00000001)
#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_CURR_LEVEL_GEN3 (0x00000002)
#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_CURR_LEVEL_GEN4 (0x00000003)
#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_CURR_LEVEL_GEN5 (0x00000004)
#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_CURR_LEVEL_GEN6 (0x00000005)
#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GPU_GEN 23:20
#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GPU_GEN_GEN1 (0x00000000)
#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GPU_GEN_GEN2 (0x00000001)
#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GPU_GEN_GEN3 (0x00000002)
#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GPU_GEN_GEN4 (0x00000003)
#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GPU_GEN_GEN5 (0x00000004)
#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GPU_GEN_GEN6 (0x00000005)
#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_SPEED_CHANGES 24:24
#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_SPEED_CHANGES_ENABLED (0x00000000)
#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_SPEED_CHANGES_DISABLED (0x00000001)
@@ -402,6 +406,7 @@ typedef struct NV2080_CTRL_BUS_INFO {
#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_SPEED_8000MBPS (0x00000003)
#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_SPEED_16000MBPS (0x00000004)
#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_SPEED_32000MBPS (0x00000005)
#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_SPEED_64000MBPS (0x00000006)
#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_WIDTH 25:20
#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_WIDTH_UNDEFINED (0x00000000)
#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_WIDTH_X1 (0x00000001)
@@ -708,6 +713,7 @@ typedef struct NV2080_CTRL_BUS_SET_PCIE_SPEED_PARAMS {
#define NV2080_CTRL_BUS_SET_PCIE_SPEED_8000MBPS (0x00000003)
#define NV2080_CTRL_BUS_SET_PCIE_SPEED_16000MBPS (0x00000004)
#define NV2080_CTRL_BUS_SET_PCIE_SPEED_32000MBPS (0x00000005)
#define NV2080_CTRL_BUS_SET_PCIE_SPEED_64000MBPS (0x00000006)
/*
* NV2080_CTRL_CMD_BUS_SET_HWBC_UPSTREAM_PCIE_SPEED
@@ -1492,3 +1498,91 @@ typedef struct NV2080_CTRL_BUS_GET_C2C_ERR_INFO_PARAMS {
} errCnts[NV2080_CTRL_BUS_GET_C2C_ERR_INFO_MAX_NUM_C2C_INSTANCES * NV2080_CTRL_BUS_GET_C2C_ERR_INFO_MAX_C2C_LINKS_PER_INSTANCE];
} NV2080_CTRL_BUS_GET_C2C_ERR_INFO_PARAMS;
/*
* NV2080_CTRL_CMD_BUS_SET_P2P_MAPPING
*
* This command sets P2P mapping.
*
* connectionType[IN]
* Connection type, one of NV2080_CTRL_CMD_BUS_SET_P2P_MAPPINGS_CONNECTION
* peerId[IN]
* peerId of remote GPU from local GPU on which call is made.
* bSpaAccessOnly[IN]
* SPA access only. SPA addressing mode is supported when we support ATS.
* bUseUuid [in]
* Option only available for Guest RPCs and is not avaliable for external clients.
* Set to NV_TRUE to use remoteGpuUuid in lieu of remoteGpuId to identify target GPU.
* remoteGpuId[IN]
* GPU ID of remote GPU.
* remoteGpuUuid [in]
* Alternative to gpuId; used to identify target GPU for which caps are being queried.
* Option only available for Guest RPCs.
* If bUseUuid == NV_TRUE, gpuUuid is used in lieu of gpuId to identify target GPU.
* If bUseUuid == NV_FALSE, gpuUuid is ignored and gpuId is used by default.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_NOT_SUPPORTED
*/
#define NV2080_CTRL_CMD_BUS_SET_P2P_MAPPING (0x2080182e) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_BUS_SET_P2P_MAPPING_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_CMD_BUS_SET_P2P_MAPPING_CONNECTION_TYPE_INVALID 0
#define NV2080_CTRL_CMD_BUS_SET_P2P_MAPPING_CONNECTION_TYPE_NVLINK 1
#define NV2080_CTRL_CMD_BUS_SET_P2P_MAPPING_CONNECTION_TYPE_PCIE 2
#define NV2080_CTRL_CMD_BUS_SET_P2P_MAPPING_CONNECTION_TYPE_PCIE_BAR1 3
#define NV2080_CTRL_CMD_BUS_SET_P2P_MAPPING_CONNECTION_TYPE_C2C 4
#define NV2080_SET_P2P_MAPPING_UUID_LEN 16U
#define NV2080_CTRL_BUS_SET_P2P_MAPPING_PARAMS_MESSAGE_ID (0x2EU)
typedef struct NV2080_CTRL_BUS_SET_P2P_MAPPING_PARAMS {
NvU32 connectionType;
NvU32 peerId;
NvBool bSpaAccessOnly;
NvBool bUseUuid;
NvU32 remoteGpuId;
NvU8 remoteGpuUuid[NV2080_SET_P2P_MAPPING_UUID_LEN];
} NV2080_CTRL_BUS_SET_P2P_MAPPING_PARAMS;
/*
* NV2080_CTRL_CMD_BUS_UNSET_P2P_MAPPING
*
* This command unsets P2P mapping.
*
* connectionType[IN]
* Connection type, one of NV2080_CTRL_CMD_BUS_SET_P2P_MAPPINGS_CONNECTION
* peerId[IN]
* peerId of remote GPU from local GPU on which call is mad.
* bUseUuid [in]
* Option only available for Guest RPCs and is not avaliable for external clients.
* Set to NV_TRUE to use remoteGpuUuid in lieu of remoteGpuId to identify target GPU.
* remoteGpuId[IN]
* GPU ID of remote GPU.
* remoteGpuUuid [in]
* Alternative to gpuId; used to identify target GPU for which caps are being queried.
* Option only available for Guest RPCs.
* If bUseUuid == NV_TRUE, gpuUuid is used in lieu of gpuId to identify target GPU.
* If bUseUuid == NV_FALSE, gpuUuid is ignored and gpuId is used by default.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_NOT_SUPPORTED
*/
#define NV2080_CTRL_CMD_BUS_UNSET_P2P_MAPPING (0x2080182f) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_BUS_UNSET_P2P_MAPPING_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_BUS_UNSET_P2P_MAPPING_PARAMS_MESSAGE_ID (0x2FU)
typedef struct NV2080_CTRL_BUS_UNSET_P2P_MAPPING_PARAMS {
NvU32 connectionType;
NvU32 peerId;
NvBool bUseUuid;
NvU32 remoteGpuId;
NvU8 remoteGpuUuid[NV2080_SET_P2P_MAPPING_UUID_LEN];
} NV2080_CTRL_BUS_UNSET_P2P_MAPPING_PARAMS;

25
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080ce.h
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@@ -32,9 +32,10 @@
/* NV20_SUBDEVICE_XX ce control commands and parameters */
#include "nvcfg_sdk.h"
#include "ctrl2080common.h"
/* NV20_SUBDEVICE_XX ce control commands and parameters */
/*
* NV2080_CTRL_CMD_CE_GET_CAPS
@@ -139,7 +140,7 @@ typedef struct NV2080_CTRL_CE_GET_CAPS_V2_PARAMS {
/*
* NV2080_CTRL_CMD_CE_GET_CE_PCE_MASK
*
* This command returns the mapping of PCE's for the given LCE
* This command returns the mapping of PCE's for the given LCE.
*
* ceEngineType
* This parameter specifies the copy engine type
@@ -153,6 +154,8 @@ typedef struct NV2080_CTRL_CE_GET_CAPS_V2_PARAMS {
* NV_ERR_INVALID_ARGUMENT
*/
#define NV2080_CTRL_CMD_CE_GET_CE_PCE_MASK (0x20802a02) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_CE_INTERFACE_ID << 8) | NV2080_CTRL_CE_GET_CE_PCE_MASK_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_CE_GET_CE_PCE_MASK_PARAMS_MESSAGE_ID (0x2U)
@@ -198,13 +201,13 @@ typedef struct NV2080_CTRL_CE_SET_PCE_LCE_CONFIG_PARAMS {
*
* This command updates the PCE-LCE mappings
*
* pPceLceMap [IN]
* pceLceMap [IN]
* This parameter contains the array of PCE to LCE mappings.
* The array is indexed by the PCE index, and contains the
* LCE index that the PCE is assigned to. A unused PCE is
* tagged with NV2080_CTRL_CE_UPDATE_PCE_LCE_MAPPINGS_INVALID_LCE.
*
* pGrceConfig [IN]
* grceConfig [IN]
* This parameter contains the array of GRCE configs.
* 0xF -> GRCE does not share with any LCE
* 0-MAX_LCE -> GRCE shares with the given LCE
@@ -238,6 +241,18 @@ typedef struct NV2080_CTRL_CE_UPDATE_PCE_LCE_MAPPINGS_PARAMS {
#define NV2080_CTRL_CE_UPDATE_PCE_LCE_MAPPINGS_INVALID_LCE 0xf
/*
* NV2080_CTRL_CMD_CE_UPDATE_CLASS_DB
*
* This function triggers an update of the exported CE classes. CEs with
* no physical resources will not be exported. A record of these
* will be return in in the stubbedCeMask.
*
* An example if NV2080_ENGINE_TYPE_COPY4 is stubbed (1<<4) will be
* set in stubbedCeMask.
*/
#define NV2080_CTRL_CMD_CE_UPDATE_CLASS_DB (0x20802a06) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_CE_INTERFACE_ID << 8) | NV2080_CTRL_CE_UPDATE_CLASS_DB_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_CE_UPDATE_CLASS_DB_PARAMS_MESSAGE_ID (0x6U)

34
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080common.h
View File

@@ -1,34 +0,0 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2001-2004 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl2080/ctrl2080common.finn
//
#define NV2080_CTRL_CMD_MAX_HEADS 2

2
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080dma.h
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@@ -34,8 +34,6 @@
/* NV20_SUBDEVICE_XX dma control commands and parameters */
#include "ctrl2080common.h"
/*
* NV2080_CTRL_CMD_DMA_INVALIDATE_TLB
*

2
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080ecc.h
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@@ -34,7 +34,7 @@
#define NV2080_CTRL_CMD_ECC_GET_CLIENT_EXPOSED_COUNTERS (0x20803400) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_ECC_INTERFACE_ID << 8) | NV2080_CTRL_ECC_GET_CLIENT_EXPOSED_COUNTERS_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_CMD_ECC_GET_CLIENT_EXPOSED_COUNTERS (0x20803400U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_ECC_INTERFACE_ID << 8) | NV2080_CTRL_ECC_GET_CLIENT_EXPOSED_COUNTERS_PARAMS_MESSAGE_ID" */
/*
* NV2080_CTRL_ECC_GET_CLIENT_EXPOSED_COUNTERS_PARAMS

533
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080fb.h
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File diff suppressed because it is too large Load Diff

44
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080fifo.h
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@@ -474,7 +474,7 @@ typedef struct NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION_PARAMS {
* NV2080_CTRL_CMD_FIFO_GET_DEVICE_INFO_TABLE
*
* This command retrieves entries from the SW encoded GPU device info table
* from Host RM.
* from Host RM.
*
* Parameters:
*
@@ -517,7 +517,7 @@ typedef struct NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION_PARAMS {
* pbdmaFaultIds
* List of pbdma fault ids associated with engine
* numPbdmas
* Number of pbdmas
* Number of pbdmas
* engineName
* Name of the engine
*/
@@ -643,8 +643,8 @@ typedef struct NV2080_CTRL_CMD_FIFO_CLEAR_FAULTED_BIT_PARAMS {
* description for more details.
* - NV2080_CTRL_FIFO_RUNLIST_SCHED_POLICY_CHANNEL_INTERLEAVED_WDDM
* This scheduling policy will make channels to be scheduled according
* to their interleave level per WDDM policy.
* See NVA06C_CTRL_CMD_SET_INTERLEAVE_LEVEL description for more details.
* to their interleave level per WDDM policy.
* See NVA06C_CTRL_CMD_SET_INTERLEAVE_LEVEL description for more details.
*
* Possible status values returned are:
* NV_OK
@@ -734,10 +734,10 @@ typedef struct NV2080_CTRL_FIFO_DISABLE_USERMODE_CHANNELS_PARAMS {
*
* When a VF subcontext is marked as a zombie, host RM points its PDB to a dummy
* page allocated by guest RM in GPA space. This command provides the parameters
* of the guest RMs memory descriptor to be able to create a corresponding
* of the guest RMs memory descriptor to be able to create a corresponding
* memory descriptor on the host RM. Host RM uses this to program the PDB of a
* zombie subcontext.
*
*
* Parameters:
* Input parameters to describe the memory descriptor
* [in] base
@@ -756,4 +756,36 @@ typedef struct NV2080_CTRL_FIFO_SETUP_VF_ZOMBIE_SUBCTX_PDB_PARAMS {
NvU32 cacheAttrib;
} NV2080_CTRL_FIFO_SETUP_VF_ZOMBIE_SUBCTX_PDB_PARAMS;
/*
* NV2080_CTRL_CMD_FIFO_GET_ALLOCATED_CHANNELS
*
* Get's a bitmask of allocated channels. No guarantees are made about
* synchronization. A channel returned as allocated by this ctrl cmd might have
* already been destructed.
*
* Parameters:
* [in] runlistId
* [in,out] bitMask A 1 bit indicates that a channel with this index/id is
* allocated. This field is a multiple of 32 bits and each 32
* bit group must be accessed as a platform 32 bit int to
* correctly map channel IDs.
*
*/
#define NV2080_CTRL_CMD_FIFO_GET_ALLOCATED_CHANNELS (0x20801119) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FIFO_INTERFACE_ID << 8) | NV2080_CTRL_FIFO_GET_ALLOCATED_CHANNELS_PARAMS_MESSAGE_ID" */
/*
* The maximum number than can be returned by
* NV2080_CTRL_CMD_INTERNAL_FIFO_GET_NUM_CHANNELS
*/
#define NV2080_CTRL_FIFO_GET_ALLOCATED_CHANNELS_MAX_CHANNELS 4096
#define NV2080_CTRL_FIFO_GET_ALLOCATED_CHANNELS_PARAMS_MESSAGE_ID (0x19U)
typedef struct NV2080_CTRL_FIFO_GET_ALLOCATED_CHANNELS_PARAMS {
NvU32 runlistId;
NvU32 bitMask[NV2080_CTRL_FIFO_GET_ALLOCATED_CHANNELS_MAX_CHANNELS / 32];
} NV2080_CTRL_FIFO_GET_ALLOCATED_CHANNELS_PARAMS;
/* _ctrl2080fifo_h_ */

2
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080fla.h
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@@ -34,8 +34,6 @@
/* NV20_SUBDEVICE_XX FLA control commands and parameters */
#include "ctrl2080common.h"
/*
* NV2080_CTRL_CMD_FLA_RANGE
*

25
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080flcn.h
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@@ -80,22 +80,44 @@ typedef struct NV2080_CTRL_FLCN_GET_DMEM_USAGE_PARAMS {
* @defgroup NVOS_INST_EVT Instrumentation event types.
* @{
*/
//! Reserved for uStreamer internal use.
#define NV2080_CTRL_FLCN_NVOS_INST_EVT_RSVD_DO_NOT_USE 0x00U
//! RTOS CTXSW includes next taskID and number of ODP for previous task.
#define NV2080_CTRL_FLCN_NVOS_INST_EVT_CTXSW_END 0x01U
//! Begin of a HW IRQ.
#define NV2080_CTRL_FLCN_NVOS_INST_EVT_HW_IRQ_BEGIN 0x02U
//! End of a HW IRQ, before stack pinning etc is performed.
#define NV2080_CTRL_FLCN_NVOS_INST_EVT_HW_IRQ_END 0x03U
//! RTOS Timer tick slip. (Only for # tick processed > 1).
#define NV2080_CTRL_FLCN_NVOS_INST_EVT_TIMER_TICK 0x04U
//! Task start processing an event, includes taskId, eventType and unitId (optional).
#define NV2080_CTRL_FLCN_NVOS_INST_EVT_TASK_EVENT_BEGIN 0x05U
//! Task finished processing an event, incldues taskId.
#define NV2080_CTRL_FLCN_NVOS_INST_EVT_TASK_EVENT_END 0x06U
//! Latency for inserting response into RM queue.
#define NV2080_CTRL_FLCN_NVOS_INST_EVT_RM_QUEUE_LATENCY 0x07U
//! Special / multi-purpose event, see field definition below.
#define NV2080_CTRL_FLCN_NVOS_INST_EVT_TASK_SPECIAL_EVENT 0x08U
#define NV2080_CTRL_FLCN_NVOS_INST_EVT_DMA_BEGIN 0x09U
//! Unused, recycle
#define NV2080_CTRL_FLCN_NVOS_INST_EVT_UNUSED_0 0x09U
#define NV2080_CTRL_FLCN_NVOS_INST_EVT_DMA_END 0x0AU
//! Begin/end for arbitrary block of code. The payload contains a sub-ID for each location profiled.
#define NV2080_CTRL_FLCN_NVOS_INST_EVT_GENERIC_BEGIN 0x0BU
#define NV2080_CTRL_FLCN_NVOS_INST_EVT_GENERIC_END 0x0CU
//! Queueing time for the most recent event.
#define NV2080_CTRL_FLCN_NVOS_INST_EVT_TASK_EVENT_LATENCY 0x0DU
/*!@}*/
@@ -191,6 +213,7 @@ typedef struct NV2080_CTRL_FLCN_GET_ENGINE_ARCH_PARAMS {
#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_TASK_EVENT_BEGIN_EVENT_TYPE 23:16
#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_TASK_EVENT_END_TASK_ID 7:0
#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_TASK_EVENT_END_CALLBACK_ID 15:8
#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_TASK_EVENT_END_RPC_FUNC 15:8
#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_TASK_EVENT_END_RPC_FUNC_BOBJ_CMD_BASE 0xF0
#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_TASK_EVENT_END_CLASS_ID 23:16

922
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080gpu.h
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File diff suppressed because it is too large Load Diff

6
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080gr.h
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@@ -33,6 +33,8 @@
#include "ctrl/ctrl2080/ctrl2080base.h"
#include "ctrl/ctrl0080/ctrl0080gr.h" /* 2080 is partially derivative of 0080 */
#include "nvcfg_sdk.h"
/*
* NV2080_CTRL_GR_ROUTE_INFO
*
@@ -250,6 +252,7 @@ typedef NV0080_CTRL_GR_INFO NV2080_CTRL_GR_INFO;
#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_SINGLETON_GPCS NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_SINGLETON_GPCS
#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_GFXC_GPCS NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_GFXC_GPCS
#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_GFXC_TPCS_PER_GFXC_GPC NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_GFXC_TPCS_PER_GFXC_GPC
#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_SLICES_PER_LTC NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_SLICES_PER_LTC
/* When adding a new INDEX, please update INDEX_MAX and MAX_SIZE accordingly
* NOTE: 0080 functionality is merged with 2080 functionality, so this max size
@@ -297,6 +300,8 @@ typedef NV0080_CTRL_GR_INFO NV2080_CTRL_GR_INFO;
#define NV2080_CTRL_GR_INFO_SM_VERSION_8_09 (0x00000809U)
#define NV2080_CTRL_GR_INFO_SM_VERSION_9_00 (0x00000900U)
/* compatibility SM versions to match the official names in the ISA (e.g., SM5.2) */
#define NV2080_CTRL_GR_INFO_SM_VERSION_5_2 (NV2080_CTRL_GR_INFO_SM_VERSION_5_02)
#define NV2080_CTRL_GR_INFO_SM_VERSION_5_3 (NV2080_CTRL_GR_INFO_SM_VERSION_5_03)
@@ -314,6 +319,7 @@ typedef NV0080_CTRL_GR_INFO NV2080_CTRL_GR_INFO;
#define NV2080_CTRL_GR_INFO_SM_VERSION_9_0 (NV2080_CTRL_GR_INFO_SM_VERSION_9_00)
/**
* NV2080_CTRL_CMD_GR_GET_INFO
*

1
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080illum.h
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@@ -28,3 +28,4 @@
// Source file: ctrl/ctrl2080/ctrl2080illum.finn
//

912
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080internal.h
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File diff suppressed because it is too large Load Diff

66
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080lpwr.h
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@@ -23,6 +23,8 @@
#pragma once
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl2080/ctrl2080lpwr.finn
@@ -30,5 +32,69 @@
/*!
* NV2080_CTRL_CMD_LPWR_DIFR_CTRL
*
* This command is used to control the DIFR
* feature behavior.
*
*/
#define NV2080_CTRL_CMD_LPWR_DIFR_CTRL (0x20802801) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_LPWR_INTERFACE_ID << 8) | NV2080_CTRL_CMD_LPWR_DIFR_CTRL_PARAMS_MESSAGE_ID" */
/*!
* @brief Various Values for control
*/
// Disable the DIFR
#define NV2080_CTRL_LPWR_DIFR_CTRL_DISABLE (0x00000001)
// Enable the DIFR
#define NV2080_CTRL_LPWR_DIFR_CTRL_ENABLE (0x00000002)
// Support status for DIFR
#define NV2080_CTRL_LPWR_DIFR_CTRL_SUPPORT_STATUS (0x00000003)
/*!
* Structure containing DIFR control call Parameters
*/
#define NV2080_CTRL_CMD_LPWR_DIFR_CTRL_PARAMS_MESSAGE_ID (0x1U)
typedef struct NV2080_CTRL_CMD_LPWR_DIFR_CTRL_PARAMS {
NvU32 ctrlParamVal;
} NV2080_CTRL_CMD_LPWR_DIFR_CTRL_PARAMS;
// Values for the SUPPORT Control Status
#define NV2080_CTRL_LPWR_DIFR_SUPPORTED (0x00000001)
#define NV2080_CTRL_LPWR_DIFR_NOT_SUPPORTED (0x00000002)
/*!
* NV2080_CTRL_CMD_LPWR_DIFR_PREFETCH_RESPONSE
*
* This control call is used to send the prefetch response
*
*/
#define NV2080_CTRL_CMD_LPWR_DIFR_PREFETCH_RESPONSE (0x20802802) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_LPWR_INTERFACE_ID << 8) | NV2080_CTRL_CMD_LPWR_DIFR_PREFETCH_RESPONSE_PARAMS_MESSAGE_ID" */
/*!
* @brief Various Values of Reponses for Prefetch Status
*/
// Prefetch is successfull.
#define NV2080_CTRL_LPWR_DIFR_PREFETCH_SUCCESS (0x00000001)
// OS Filps are enabled, so prefetch can not be done.
#define NV2080_CTRL_LPWR_DIFR_PREFETCH_FAIL_OS_FLIPS_ENABLED (0x00000002)
// Current Display surface can not fit in L2
#define NV2080_CTRL_LPWR_DIFR_PREFETCH_FAIL_INSUFFICIENT_L2_SIZE (0x00000003)
// Fatal and un recoverable Error
#define NV2080_CTRL_LPWR_DIFR_PREFETCH_FAIL_CE_HW_ERROR (0x00000004)
/*!
* Structure containing DIFR prefetch response control call Parameters
*/
#define NV2080_CTRL_CMD_LPWR_DIFR_PREFETCH_RESPONSE_PARAMS_MESSAGE_ID (0x2U)
typedef struct NV2080_CTRL_CMD_LPWR_DIFR_PREFETCH_RESPONSE_PARAMS {
NvU32 responseVal;
} NV2080_CTRL_CMD_LPWR_DIFR_PREFETCH_RESPONSE_PARAMS;
// _ctrl2080lpwr_h_

231
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080nvlink.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2014-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2014-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -134,6 +134,7 @@ typedef struct NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS_PARAMS {
#define NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_3_0 (0x00000005U)
#define NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_3_1 (0x00000006U)
#define NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_4_0 (0x00000007U)
#define NV2080_CTRL_NVLINK_CAPS_NCI_VERSION_INVALID (0x00000000U)
#define NV2080_CTRL_NVLINK_CAPS_NCI_VERSION_1_0 (0x00000001U)
#define NV2080_CTRL_NVLINK_CAPS_NCI_VERSION_2_0 (0x00000002U)
@@ -142,6 +143,7 @@ typedef struct NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS_PARAMS {
#define NV2080_CTRL_NVLINK_CAPS_NCI_VERSION_3_1 (0x00000006U)
#define NV2080_CTRL_NVLINK_CAPS_NCI_VERSION_4_0 (0x00000007U)
/*
* NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS
*
@@ -491,12 +493,40 @@ typedef struct NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS_PARAMS {
* Returns the NVLIPT_LNK Log En Mask 0
* Used in Ampere and later
*
* NVLIPTLnkCtrlLinkStateRequest
* Returns the NVLIPT_LNK Control Link State Request value
* Used in Ampere and later
*
* DLSpeedStatusTx
* Returns the NVLINK DL speed status for sublink Tx
*
* DLSpeedStatusRx
* Returns the NVLINK DL speed status for sublink Rx
*
* NVLDLRxSlsmErrCntl
* Returns the NVLDL_RXSLSM_ERR_CNTL value
* Used in Hopper and later
*
* NVLDLTopLinkState
* Returns the NVLDL_TOP_LINK_STATE value
* Used in Hopper and later
*
* NVLDLTopIntr
* Returns the NVLDL_TOP_INTR value
* Used in Hopper and later
*
* DLStatMN00
* Returns the DLSTAT MN00 Code and subcode
* Used in Hopper and later
*
* DLStatUC01
* Returns the DLSTAT UC01 value
* Used in Hopper and later
*
* MinionNvlinkLinkIntr
* Returns the MINION_NVLINK_LINK_INTR code and subcode
* Used in Hopper and later
*
* bExcessErrorDL
* Returns true for excessive error rate interrupt from DL
*/
@@ -519,8 +549,15 @@ typedef struct NV2080_CTRL_NVLINK_ERR_INFO {
NvU32 MIFRxErrStatus0;
NvU32 NVLIPTLnkErrStatus0;
NvU32 NVLIPTLnkErrLogEn0;
NvU32 NVLIPTLnkCtrlLinkStateRequest;
NvU32 DLSpeedStatusTx;
NvU32 DLSpeedStatusRx;
NvU32 NVLDLRxSlsmErrCntl;
NvU32 NVLDLTopLinkState;
NvU32 NVLDLTopIntr;
NvU32 DLStatMN00;
NvU32 DLStatUC01;
NvU32 MinionNvlinkLinkIntr;
NvBool bExcessErrorDL;
} NV2080_CTRL_NVLINK_ERR_INFO;
@@ -601,6 +638,11 @@ typedef struct NV2080_CTRL_NVLINK_COMMON_ERR_INFO {
#define NV2080_CTRL_NVLINK_SL1_SLSM_STATUS_RX_PRIMARY_STATE_SAFE (0x00000006U)
#define NV2080_CTRL_NVLINK_SL1_SLSM_STATUS_RX_PRIMARY_STATE_OFF (0x00000007U)
/* Flags to query different debug registers */
#define NV2080_CTRL_NVLINK_ERR_INFO_FLAGS_DEFAULT (0x0U)
#define NV2080_CTRL_NVLINK_ERR_INFO_FLAGS_INTR_STATUS (0x1U)
#define NV2080_CTRL_NVLINK_ERR_INFO_FLAGS_ALI_STATUS (0x2U)
#define NV2080_CTRL_NVLINK_MAX_IOCTRLS 3U
/*
* NV2080_CTRL_NVLINK_GET_ERR_INFO_PARAMS
@@ -616,6 +658,12 @@ typedef struct NV2080_CTRL_NVLINK_COMMON_ERR_INFO {
*
* commonErrInfo
* Returns the error information common to each IOCTRL
*
* ErrInfoFlags
* Input for determining which values to query. Possible values:
* NV2080_CTRL_NVLINK_ERR_INFO_FLAGS_INTR_STATUS
* NV2080_CTRL_NVLINK_ERR_INFO_FLAGS_ALI_STATUS
*
*/
#define NV2080_CTRL_NVLINK_GET_ERR_INFO_PARAMS_MESSAGE_ID (0x3U)
@@ -624,6 +672,7 @@ typedef struct NV2080_CTRL_NVLINK_GET_ERR_INFO_PARAMS {
NV2080_CTRL_NVLINK_ERR_INFO linkErrInfo[NV2080_CTRL_NVLINK_MAX_LINKS];
NvU32 ioctrlMask;
NV2080_CTRL_NVLINK_COMMON_ERR_INFO commonErrInfo[NV2080_CTRL_NVLINK_MAX_IOCTRLS];
NvU8 ErrInfoFlags;
} NV2080_CTRL_NVLINK_GET_ERR_INFO_PARAMS;
/*
@@ -1340,100 +1389,8 @@ typedef struct NV2080_CTRL_NVLINK_INJECT_TLC_ERROR_PARAMS {
NV2080_CTRL_NVLINK_INJECT_TLC_ERROR_TYPE errorType;
} NV2080_CTRL_NVLINK_INJECT_TLC_ERROR_PARAMS;
/*
* NV2080_CTRL_CMD_NVLINK_CHECK_BRIDGE
*
* This command returns the presence and data fields of an NVLink Bridge EEPROM.
*
* [in] linkId
* The NVLink ID to check for a bridge EEPROM
* [out] bPresent
* NV_TRUE if the EEPROM chip is detected.
* [out] bValid
* NV_TRUE if the the data read passes validity checks. If so, the following
* fields are populated.
* [out] firmwareVersion
* The firmware version formatted as PPPP.SSSS.BB, e.g. 4931.0200.01.01,
* padded with one or more 0x00
* [out] bridgeVendor
* The bridge vendor name, padded with one or more 0x00
* [out] boardPartNumber
* The board part number, formatted as CCC-FPPPP-SSSS-RRR
* (e.g. 699-24931-0200-000), padded with one or more 0x00
* [out] boardRevision
* The board revision, e.g. A00, padded with one or more 0x00
* [out] configuration
* Bridge form factor (2-way/3-way/4-way).
* See NV2080_CTRL_NVLINK_BRIDGE_CONFIGURATION_*
* [out] spacing
* # of slots spacing identifier. See NV2080_CTRL_NVLINK_BRIDGE_SPACING_*
* [out] interconnectType
* Type of interconnect. See NV2080_CTRL_NVLINK_BRIDGE_INTERCONNECT_TYPE_*
* [out] interconnectWidth
* Width of interconnect NVHS lanes.
* See NV2080_CTRL_NVLINK_BRIDGE_INTERCONNECT_WIDTH_*
* [out] maximumLandDataRate
* Maximum data transfer rate in T/s, as an IEEE-754 32-bit float
* [out] featureIllumination
* Illumination feature supported.
* See NV2080_CTRL_NVLINK_BRIDGE_ILLUMINATION_FEATURE_*
* [out] businessUnit
* Business unit identifier.
*/
#define NV2080_CTRL_CMD_NVLINK_CHECK_BRIDGE (0x20803010U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_CHECK_BRIDGE_PARAMS_MESSAGE_ID" */
// ASCII bytes plus space for null terminator
#define NV2080_CTRL_NVLINK_BRIDGE_FIRMWARE_VERSION_LENGTH (0x11U) /* finn: Evaluated from "(16 + 1)" */
#define NV2080_CTRL_NVLINK_BRIDGE_VENDOR_LENGTH (0x15U) /* finn: Evaluated from "(20 + 1)" */
#define NV2080_CTRL_NVLINK_BRIDGE_BOARD_PART_NUMBER_LENGTH (0x15U) /* finn: Evaluated from "(20 + 1)" */
#define NV2080_CTRL_NVLINK_BRIDGE_BOARD_REVISION_LENGTH (0x4U) /* finn: Evaluated from "(3 + 1)" */
#define NV2080_CTRL_NVLINK_BRIDGE_CONFIGURATION_UNDEFINED (0x00U)
#define NV2080_CTRL_NVLINK_BRIDGE_CONFIGURATION_2_WAY (0x02U)
#define NV2080_CTRL_NVLINK_BRIDGE_CONFIGURATION_3_WAY (0x03U)
#define NV2080_CTRL_NVLINK_BRIDGE_CONFIGURATION_4_WAY (0x04U)
#define NV2080_CTRL_NVLINK_BRIDGE_SPACING_UNDEFINED (0x00U)
#define NV2080_CTRL_NVLINK_BRIDGE_SPACING_2_SLOT (0x02U)
#define NV2080_CTRL_NVLINK_BRIDGE_SPACING_3_SLOT (0x03U)
#define NV2080_CTRL_NVLINK_BRIDGE_SPACING_4_SLOT (0x04U)
#define NV2080_CTRL_NVLINK_BRIDGE_INTERCONNECT_TYPE_UNDEFINED (0x00U)
#define NV2080_CTRL_NVLINK_BRIDGE_INTERCONNECT_TYPE_NVLINK_2 (0x02U)
#define NV2080_CTRL_NVLINK_BRIDGE_INTERCONNECT_TYPE_NVLINK_3 (0x03U)
#define NV2080_CTRL_NVLINK_BRIDGE_INTERCONNECT_WIDTH_UNDEFINED (0x00U)
#define NV2080_CTRL_NVLINK_BRIDGE_INTERCONNECT_WIDTH_4_LANES (0x02U)
#define NV2080_CTRL_NVLINK_BRIDGE_INTERCONNECT_WIDTH_8_LANES (0x03U)
#define NV2080_CTRL_NVLINK_BRIDGE_INTERCONNECT_WIDTH_16_LANES (0x04U)
#define NV2080_CTRL_NVLINK_BRIDGE_ILLUMINATION_FEATURE_NONE (0x00U)
#define NV2080_CTRL_NVLINK_BRIDGE_ILLUMINATION_FEATURE_SINGLE_COLOR (0x01U)
#define NV2080_CTRL_NVLINK_BRIDGE_ILLUMINATION_FEATURE_RGB (0x02U)
#define NV2080_CTRL_NVLINK_CHECK_BRIDGE_PARAMS_MESSAGE_ID (0x10U)
typedef struct NV2080_CTRL_NVLINK_CHECK_BRIDGE_PARAMS {
NvU32 linkId;
NvBool bPresent;
NvBool bValid;
char firmwareVersion[NV2080_CTRL_NVLINK_BRIDGE_FIRMWARE_VERSION_LENGTH];
char bridgeVendor[NV2080_CTRL_NVLINK_BRIDGE_VENDOR_LENGTH];
char boardPartNumber[NV2080_CTRL_NVLINK_BRIDGE_BOARD_PART_NUMBER_LENGTH];
char boardRevision[NV2080_CTRL_NVLINK_BRIDGE_BOARD_REVISION_LENGTH];
NvU8 businessUnit;
NvU8 configuration;
NvU8 spacing;
NvU8 interconnectType;
NvU8 interconnectWidth;
NvF32 maximumLaneDataRate;
NvU8 featureIllumination;
} NV2080_CTRL_NVLINK_CHECK_BRIDGE_PARAMS;
/*
* NV2080_CTRL_CMD_NVLINK_GET_LINK_FOM_VALUES
*
@@ -2309,10 +2266,17 @@ typedef struct NV2080_CTRL_NVLINK_UPDATE_PEER_LINK_MASK_PARAMS {
#define NV2080_CTRL_NVLINK_UPDATE_LINK_CONNECTION_PARAMS_MESSAGE_ID (0x25U)
typedef struct NV2080_CTRL_NVLINK_UPDATE_LINK_CONNECTION_PARAMS {
NvU32 linkId;
NvBool bConnected;
NV_DECLARE_ALIGNED(NvU64 remoteDeviceType, 8);
NV_DECLARE_ALIGNED(NvU64 remoteChipSid, 8);
NvU32 linkId;
NvU32 laneRxdetStatusMask;
NvU32 remoteLinkNumber;
NvU32 remotePciDeviceId;
NvU32 remoteDomain;
NvU8 remoteBus;
NvU8 remoteDevice;
NvU8 remoteFunction;
NvBool bConnected;
} NV2080_CTRL_NVLINK_UPDATE_LINK_CONNECTION_PARAMS;
#define NV2080_CTRL_CMD_NVLINK_UPDATE_LINK_CONNECTION (0x20803025U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_UPDATE_LINK_CONNECTION_PARAMS_MESSAGE_ID" */
@@ -2883,6 +2847,81 @@ typedef struct NV2080_CTRL_NVLINK_EOM_CONTROL_PARAMS {
NvU32 params;
} NV2080_CTRL_NVLINK_EOM_CONTROL_PARAMS;
#define NV2080_CTRL_CMD_NVLINK_EOM_CONTROL (0x2080303c) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_EOM_CONTROL_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_CMD_NVLINK_EOM_CONTROL (0x2080303c) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_EOM_CONTROL_PARAMS_MESSAGE_ID" */
/*!
* Inband Recieved Data
*/
#define NV2080_CTRL_NVLINK_INBAND_MAX_MSG_SIZE 4096
#define NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_PARAMS_MESSAGE_ID (0x3dU)
typedef struct NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_PARAMS {
NvU8 data[NV2080_CTRL_NVLINK_INBAND_MAX_MSG_SIZE];
NvU32 dataSize;
} NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_PARAMS;
#define NV2080_CTRL_NVLINK_L1_THRESHOLD_SET (0x00000000U)
#define NV2080_CTRL_NVLINK_L1_THRESHOLD_GET (0x00000001U)
/*
* NV2080_CTRL_CMD_NVLINK_L1_THRESHOLD
*
* This command is used to get/set the L1 threshold value
*
* [in] flag
* Whether to set or get the L1 threshold value
*
* [in/out] l1Threshold
* Used to set or get the L1 threshold value
*
*/
#define NV2080_CTRL_NVLINK_L1_THRESHOLD_PARAMS_MESSAGE_ID (0x3eU)
typedef struct NV2080_CTRL_NVLINK_L1_THRESHOLD_PARAMS {
NvU32 flag;
NvU32 l1Threshold;
} NV2080_CTRL_NVLINK_L1_THRESHOLD_PARAMS;
#define NV2080_CTRL_CMD_NVLINK_L1_THRESHOLD (0x2080303eU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_L1_THRESHOLD_PARAMS_MESSAGE_ID" */
/*
* NV2080_CTRL_CMD_NVLINK_INBAND_SEND_DATA
*
* RPC for sending Inband data
*
* [In] data[]
* data to be sent over inband
* [In] dataSize
* Size of valid data in data array
*/
#define NV2080_CTRL_NVLINK_INBAND_SEND_DATA_PARAMS_MESSAGE_ID (0x3fU)
typedef struct NV2080_CTRL_NVLINK_INBAND_SEND_DATA_PARAMS {
NvU8 buffer[NV2080_CTRL_NVLINK_INBAND_MAX_MSG_SIZE];
NvU32 dataSize;
} NV2080_CTRL_NVLINK_INBAND_SEND_DATA_PARAMS;
#define NV2080_CTRL_CMD_NVLINK_INBAND_SEND_DATA (0x2080303fU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_INBAND_SEND_DATA_PARAMS_MESSAGE_ID" */
/*
* NV2080_CTRL_CMD_NVLINK_IS_GPU_DEGRADED
*
* RPC for Getting GPU degraded status upon link error
*
* [In] linkId
* Id of the link on which error occured
* [In] bIsGpuDegraded
* Boolean to track corresponding GPU is degraded or not
*/
#define NV2080_CTRL_NVLINK_IS_GPU_DEGRADED_PARAMS_MESSAGE_ID (0x40U)
typedef struct NV2080_CTRL_NVLINK_IS_GPU_DEGRADED_PARAMS {
NvU32 linkId;
NvBool bIsGpuDegraded;
} NV2080_CTRL_NVLINK_IS_GPU_DEGRADED_PARAMS;
#define NV2080_CTRL_CMD_NVLINK_IS_GPU_DEGRADED (0x20803040U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_IS_GPU_DEGRADED_PARAMS_MESSAGE_ID" */
/* _ctrl2080nvlink_h_ */

77
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080perf.h
View File

@@ -72,7 +72,6 @@
* NV_ERR_INVALID_ARGUMENT
*/
#define NV2080_CTRL_PERF_BOOST_FLAGS_CMD 1:0
#define NV2080_CTRL_PERF_BOOST_FLAGS_CMD_CLEAR (0x00000000)
#define NV2080_CTRL_PERF_BOOST_FLAGS_CMD_BOOST_1LEVEL (0x00000001)
@@ -86,6 +85,10 @@
#define NV2080_CTRL_PERF_BOOST_FLAGS_ASYNC_NO (0x00000000)
#define NV2080_CTRL_PERF_BOOST_FLAGS_ASYNC_YES (0x00000001)
#define NV2080_CTRL_PERF_BOOST_FLAGS_CUDA_PRIORITY 6:6
#define NV2080_CTRL_PERF_BOOST_FLAGS_CUDA_PRIORITY_DEFAULT (0x00000000)
#define NV2080_CTRL_PERF_BOOST_FLAGS_CUDA_PRIORITY_HIGH (0x00000001)
#define NV2080_CTRL_PERF_BOOST_DURATION_MAX 3600 //The duration can be specified up to 1 hour
#define NV2080_CTRL_PERF_BOOST_DURATION_INFINITE 0xffffffff // If set this way, the boost will last until cleared.
@@ -124,6 +127,76 @@ typedef struct NV2080_CTRL_PERF_RESERVE_PERFMON_HW_PARAMS {
NvBool bAcquire;
} NV2080_CTRL_PERF_RESERVE_PERFMON_HW_PARAMS;
/*
* NV2080_CTRL_PERF_POWERSTATE
*
* This structure describes power state information.
*
* powerState
* This parameter specifies the type of power source.
* Legal values for this parameter include:
* NV2080_CTRL_PERF_POWER_SOURCE_AC
* This values indicates that the power state is AC.
* NV2080_CTRL_PERF_POWER_SOURCE_BATTERY
* This values indicates that the power state is battery.
*/
#define NV2080_CTRL_PERF_POWER_SOURCE_AC (0x00000000)
#define NV2080_CTRL_PERF_POWER_SOURCE_BATTERY (0x00000001)
typedef struct NV2080_CTRL_PERF_POWERSTATE_PARAMS {
NvU32 powerState;
} NV2080_CTRL_PERF_POWERSTATE_PARAMS;
/*
* NV2080_CTRL_CMD_PERF_SET_POWERSTATE
*
* This command can be used to set the perf power state as AC or battery.
*
* powerStateInfo
* This parameter specifies the power source type to set.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
*/
#define NV2080_CTRL_CMD_PERF_SET_POWERSTATE (0x2080205b) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_PERF_INTERFACE_ID << 8) | NV2080_CTRL_PERF_SET_POWERSTATE_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_PERF_SET_POWERSTATE_PARAMS_MESSAGE_ID (0x5BU)
typedef struct NV2080_CTRL_PERF_SET_POWERSTATE_PARAMS {
NV2080_CTRL_PERF_POWERSTATE_PARAMS powerStateInfo;
} NV2080_CTRL_PERF_SET_POWERSTATE_PARAMS;
/*
* NV2080_CTRL_CMD_PERF_SET_AUX_POWER_STATE
*
* This command allows the forcing of a performance level based on auxiliary
* power-states.
*
* powerState
* This parameter specifies the target auxiliary Power state. Legal aux
* power-states for this parameter are defined by the
* NV2080_CTRL_PERF_AUX_POWER_STATE_P* definitions that follow.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_NOT_SUPPORTED
*/
#define NV2080_CTRL_CMD_PERF_SET_AUX_POWER_STATE (0x20802092) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_PERF_INTERFACE_ID << 8) | NV2080_CTRL_PERF_SET_AUX_POWER_STATE_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_PERF_SET_AUX_POWER_STATE_PARAMS_MESSAGE_ID (0x92U)
typedef struct NV2080_CTRL_PERF_SET_AUX_POWER_STATE_PARAMS {
NvU32 powerState;
} NV2080_CTRL_PERF_SET_AUX_POWER_STATE_PARAMS;
#define NV2080_CTRL_PERF_AUX_POWER_STATE_P0 (0x00000000)
#define NV2080_CTRL_PERF_AUX_POWER_STATE_P1 (0x00000001)
#define NV2080_CTRL_PERF_AUX_POWER_STATE_P2 (0x00000002)
#define NV2080_CTRL_PERF_AUX_POWER_STATE_P3 (0x00000003)
#define NV2080_CTRL_PERF_AUX_POWER_STATE_P4 (0x00000004)
#define NV2080_CTRL_PERF_AUX_POWER_STATE_COUNT (0x00000005)
/*!
* Enumeration of the RATED_TDP arbitration clients which make requests to force
* enable/disable VF points above the RATED_TDP point.
@@ -376,7 +449,7 @@ typedef NV2080_CTRL_GPUMON_SAMPLES NV2080_CTRL_PERF_GET_GPUMON_PERFMON_UTIL_SAMP
/*!
* Number of GPU monitoring sample in their respective buffers.
*/
#define NV2080_CTRL_PERF_GPUMON_SAMPLE_COUNT_PERFMON_UTIL 100
#define NV2080_CTRL_PERF_GPUMON_SAMPLE_COUNT_PERFMON_UTIL 72
#define NV2080_CTRL_PERF_GPUMON_PERFMON_UTIL_BUFFER_SIZE \
NV_SIZEOF32(NV2080_CTRL_PERF_GPUMON_PERFMON_UTIL_SAMPLE) * \

35
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080pmgr.h
View File

@@ -30,3 +30,38 @@
// Source file: ctrl/ctrl2080/ctrl2080pmgr.finn
//
#define NV2080_CTRL_PMGR_MODULE_INFO_NVSWITCH_NOT_SUPPORTED 0U
#define NV2080_CTRL_PMGR_MODULE_INFO_NVSWITCH_SUPPORTED 1U
#define NV2080_CTRL_PMGR_MODULE_INFO_NVSWITCH_NOT_APPLICABLE 2U
/*!
* NV2080_CTRL_PMGR_MODULE_INFO_PARAMS
*
* This provides information about different module properties
*
* moduleId[OUT]
* - This is a static HW identifier that is unique for each module on a given baseboard.
* For non-baseboard products this would always be 0.
* nvswitchSupport[OUT]
* - NVSwitch present or not. Possible values are
* NV2080_CTRL_PMGR_MODULE_INFO_NVSWITCH_NOT_SUPPORTED
* NV2080_CTRL_PMGR_MODULE_INFO_NVSWITCH_SUPPORTED
* NV2080_CTRL_PMGR_MODULE_INFO_NVSWITCH_NOT_APPLICABLE
*/
#define NV2080_CTRL_PMGR_MODULE_INFO_PARAMS_MESSAGE_ID (0x9U)
typedef struct NV2080_CTRL_PMGR_MODULE_INFO_PARAMS {
NvU32 moduleId;
NvU8 nvswitchSupport;
} NV2080_CTRL_PMGR_MODULE_INFO_PARAMS;
/*!
* NV2080_CTRL_CMD_PMGR_GET_MODULE_INFO
*
* Control call to query the subdevice module INFO.
*
*/
#define NV2080_CTRL_CMD_PMGR_GET_MODULE_INFO (0x20802609) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_PMGR_INTERFACE_ID << 8) | NV2080_CTRL_PMGR_MODULE_INFO_PARAMS_MESSAGE_ID" */

2
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080ucodefuzzer.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2020-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a

407
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080vgpumgrinternal.h Normal file
View File

@@ -0,0 +1,407 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl2080/ctrl2080vgpumgrinternal.finn
//
#include "ctrl/ctrl2080/ctrl2080base.h"
#include "ctrl/ctrla081.h"
/*
* NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_BOOTLOAD_GSP_VGPU_PLUGIN_TASK
*
* This command is used to bootload GSP VGPU plugin task.
* Can be called only with SR-IOV and with VGPU_GSP_PLUGIN_OFFLOAD feature.
*
* dbdf - domain (31:16), bus (15:8), device (7:3), function (2:0)
* gfid - Gfid
* vgpuType - The Type ID for VGPU profile
* vmPid - Plugin process ID of vGPU guest instance
* swizzId - SwizzId
* numChannels - Number of channels
* numPluginChannels - Number of plugin channels
* bDisableSmcPartitionRestore - If set to true, SMC default execution partition
* save/restore will not be done in host-RM
* guestFbPhysAddrList - list of VMMU segment aligned physical address of guest FB memory
* guestFbLengthList - list of guest FB memory length in bytes
* pluginHeapMemoryPhysAddr - plugin heap memory offset
* pluginHeapMemoryLength - plugin heap memory length in bytes
* bDeviceProfilingEnabled - If set to true, profiling is allowed
*/
#define NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_BOOTLOAD_GSP_VGPU_PLUGIN_TASK (0x20804001) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_VGPU_MGR_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_VGPU_MGR_INTERNAL_BOOTLOAD_GSP_VGPU_PLUGIN_TASK_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_MAX_VMMU_SEGMENTS 384
/* Must match NV2080_ENGINE_TYPE_LAST from cl2080.h */
#define NV2080_GPU_MAX_ENGINES 0x3e
#define NV2080_CTRL_VGPU_MGR_INTERNAL_BOOTLOAD_GSP_VGPU_PLUGIN_TASK_PARAMS_MESSAGE_ID (0x1U)
typedef struct NV2080_CTRL_VGPU_MGR_INTERNAL_BOOTLOAD_GSP_VGPU_PLUGIN_TASK_PARAMS {
NvU32 dbdf;
NvU32 gfid;
NvU32 vgpuType;
NvU32 vmPid;
NvU32 swizzId;
NvU32 numChannels;
NvU32 numPluginChannels;
NvU32 chidOffset[NV2080_GPU_MAX_ENGINES];
NvBool bDisableDefaultSmcExecPartRestore;
NvU32 numGuestFbSegments;
NV_DECLARE_ALIGNED(NvU64 guestFbPhysAddrList[NV2080_CTRL_MAX_VMMU_SEGMENTS], 8);
NV_DECLARE_ALIGNED(NvU64 guestFbLengthList[NV2080_CTRL_MAX_VMMU_SEGMENTS], 8);
NV_DECLARE_ALIGNED(NvU64 pluginHeapMemoryPhysAddr, 8);
NV_DECLARE_ALIGNED(NvU64 pluginHeapMemoryLength, 8);
NV_DECLARE_ALIGNED(NvU64 ctrlBuffOffset, 8);
NvBool bDeviceProfilingEnabled;
} NV2080_CTRL_VGPU_MGR_INTERNAL_BOOTLOAD_GSP_VGPU_PLUGIN_TASK_PARAMS;
/*
* NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_SHUTDOWN_GSP_VGPU_PLUGIN_TASK
*
* This command is used to shutdown GSP VGPU plugin task.
* Can be called only with SR-IOV and with VGPU_GSP_PLUGIN_OFFLOAD feature.
*
* gfid - Gfid
*/
#define NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_SHUTDOWN_GSP_VGPU_PLUGIN_TASK (0x20804002) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_VGPU_MGR_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_VGPU_MGR_INTERNAL_SHUTDOWN_GSP_VGPU_PLUGIN_TASK_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_VGPU_MGR_INTERNAL_SHUTDOWN_GSP_VGPU_PLUGIN_TASK_PARAMS_MESSAGE_ID (0x2U)
typedef struct NV2080_CTRL_VGPU_MGR_INTERNAL_SHUTDOWN_GSP_VGPU_PLUGIN_TASK_PARAMS {
NvU32 gfid;
} NV2080_CTRL_VGPU_MGR_INTERNAL_SHUTDOWN_GSP_VGPU_PLUGIN_TASK_PARAMS;
/*
* NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_PGPU_ADD_VGPU_TYPE
*
* This command is used to add a new vGPU config to the pGPU in physical RM.
* Unlike NVA081_CTRL_CMD_VGPU_CONFIG_SET_INFO, it does no validation
* and is only to be used internally.
*
* discardVgpuTypes [IN]
* This parameter specifies if existing vGPU configuration should be
* discarded for given pGPU
*
* vgpuInfoCount [IN]
* This parameter specifies the number of entries of virtual GPU type
* information
*
* vgpuInfo [IN]
* This parameter specifies virtual GPU type information
*
* Possible status values returned are:
* NV_OK
* NV_ERR_OBJECT_NOT_FOUND
* NV_ERR_NOT_SUPPORTED
*/
#define NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_PGPU_ADD_VGPU_TYPE (0x20804003) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_VGPU_MGR_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_VGPU_MGR_INTERNAL_PGPU_ADD_VGPU_TYPE_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_VGPU_MGR_INTERNAL_PGPU_ADD_VGPU_TYPE_PARAMS_MESSAGE_ID (0x3U)
typedef struct NV2080_CTRL_VGPU_MGR_INTERNAL_PGPU_ADD_VGPU_TYPE_PARAMS {
NvBool discardVgpuTypes;
NvU32 vgpuInfoCount;
NV_DECLARE_ALIGNED(NVA081_CTRL_VGPU_INFO vgpuInfo[NVA081_MAX_VGPU_TYPES_PER_PGPU], 8);
} NV2080_CTRL_VGPU_MGR_INTERNAL_PGPU_ADD_VGPU_TYPE_PARAMS;
/*
* NV2080_GUEST_VM_INFO
*
* This structure represents vGPU guest's (VM's) information
*
* vmPid [OUT]
* This param specifies the vGPU plugin process ID
* guestOs [OUT]
* This param specifies the vGPU guest OS type
* migrationProhibited [OUT]
* This flag indicates whether migration is prohibited for VM or not
* guestNegotiatedVgpuVersion [OUT]
* This param specifies the vGPU version of guest driver after negotiation
* frameRateLimit [OUT]
* This param specifies the current value of FRL set for guest
* licensed [OUT]
* This param specifies whether the VM is Unlicensed/Licensed
* licenseState [OUT]
* This param specifies the current state of the GRID license state machine
* licenseExpiryTimestamp [OUT]
* License expiry time in seconds since UNIX epoch
* licenseExpiryStatus [OUT]
* License expiry status
* guestDriverVersion [OUT]
* This param specifies the driver version of the driver installed on the VM
* guestDriverBranch [OUT]
* This param specifies the driver branch of the driver installed on the VM
* guestVmInfoState [OUT]
* This param stores the current state of guest dependent fields
*
*/
typedef struct NV2080_GUEST_VM_INFO {
NvU32 vmPid;
NvU32 guestOs;
NvU32 migrationProhibited;
NvU32 guestNegotiatedVgpuVersion;
NvU32 frameRateLimit;
NvBool licensed;
NvU32 licenseState;
NvU32 licenseExpiryTimestamp;
NvU8 licenseExpiryStatus;
NvU8 guestDriverVersion[NVA081_VGPU_STRING_BUFFER_SIZE];
NvU8 guestDriverBranch[NVA081_VGPU_STRING_BUFFER_SIZE];
GUEST_VM_INFO_STATE guestVmInfoState;
} NV2080_GUEST_VM_INFO;
/*
* NV2080_GUEST_VGPU_DEVICE
*
* This structure represents host vgpu device's (assigned to VM) information
*
* gfid [OUT]
* This parameter specifies the gfid of vGPU assigned to VM.
* vgpuPciId [OUT]
* This parameter specifies vGPU PCI ID
* vgpuDeviceInstanceId [OUT]
* This paramter specifies the vGPU device instance per VM to be used for supporting
* multiple vGPUs per VM.
* fbUsed [OUT]
* This parameter specifies FB usage in bytes
* eccState [OUT]
* This parameter specifies the ECC state of the virtual GPU.
* One of NVA081_CTRL_ECC_STATE_xxx values.
* bDriverLoaded [OUT]
* This parameter specifies whether driver is loaded on this particular vGPU.
*
*/
typedef struct NV2080_HOST_VGPU_DEVICE {
NvU32 gfid;
NV_DECLARE_ALIGNED(NvU64 vgpuPciId, 8);
NvU32 vgpuDeviceInstanceId;
NV_DECLARE_ALIGNED(NvU64 fbUsed, 8);
NvU32 encoderCapacity;
NvU32 eccState;
NvBool bDriverLoaded;
} NV2080_HOST_VGPU_DEVICE;
/*
* NV2080_VGPU_GUEST
*
* This structure represents a vGPU guest
*
*/
typedef struct NV2080_VGPU_GUEST {
NV2080_GUEST_VM_INFO guestVmInfo;
NV_DECLARE_ALIGNED(NV2080_HOST_VGPU_DEVICE vgpuDevice, 8);
} NV2080_VGPU_GUEST;
/*
* NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_ENUMERATE_VGPU_PER_PGPU
*
* This command enumerates list of vGPU guest instances per pGpu
*
* numVgpu [OUT]
* This parameter specifies the number of virtual GPUs created on this physical GPU
*
* vgpuGuest [OUT]
* This parameter specifies an array containing guest vgpu's information for
* all vGPUs created on this physical GPU
*
* Possible status values returned are:
* NV_OK
* NV_ERR_OBJECT_NOT_FOUND
*/
#define NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_ENUMERATE_VGPU_PER_PGPU (0x20804004) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_VGPU_MGR_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_VGPU_MGR_INTERNAL_ENUMERATE_VGPU_PER_PGPU_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_VGPU_MGR_INTERNAL_ENUMERATE_VGPU_PER_PGPU_PARAMS_MESSAGE_ID (0x4U)
typedef struct NV2080_CTRL_VGPU_MGR_INTERNAL_ENUMERATE_VGPU_PER_PGPU_PARAMS {
NvU32 numVgpu;
NV_DECLARE_ALIGNED(NV2080_VGPU_GUEST vgpuGuest[NVA081_MAX_VGPU_PER_PGPU], 8);
} NV2080_CTRL_VGPU_MGR_INTERNAL_ENUMERATE_VGPU_PER_PGPU_PARAMS;
/*
* NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_CLEAR_GUEST_VM_INFO
*
* This command is used clear guest vm info. It should be used when
* NVA084_CTRL_CMD_KERNEL_HOST_VGPU_DEVICE_SET_VGPU_GUEST_LIFE_CYCLE_STATE
* is called with NVA081_NOTIFIERS_EVENT_VGPU_GUEST_DESTROYED state.
*
* gfid [IN]
* This parameter specifies the gfid of vGPU assigned to VM.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_OBJECT_NOT_FOUND
*/
#define NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_CLEAR_GUEST_VM_INFO (0x20804005) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_VGPU_MGR_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_VGPU_MGR_INTERNAL_CLEAR_GUEST_VM_INFO_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_VGPU_MGR_INTERNAL_CLEAR_GUEST_VM_INFO_PARAMS_MESSAGE_ID (0x5U)
typedef struct NV2080_CTRL_VGPU_MGR_INTERNAL_CLEAR_GUEST_VM_INFO_PARAMS {
NvU32 gfid;
} NV2080_CTRL_VGPU_MGR_INTERNAL_CLEAR_GUEST_VM_INFO_PARAMS;
/*
* NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_GET_VGPU_FB_USAGE
*
* This command is used to get the FB usage of all vGPU instances running on a GPU.
*
* vgpuCount [OUT]
* This field specifies the number of vGPU devices for which FB usage is returned.
* vgpuFbUsage [OUT]
* This is an array of type NV2080_VGPU_FB_USAGE, which contains a list of vGPU gfid
* and their corresponding FB usage in bytes.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_OBJECT_NOT_FOUND
*/
#define NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_GET_VGPU_FB_USAGE (0x20804006) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_VGPU_MGR_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_VGPU_MGR_INTERNAL_GET_VGPU_FB_USAGE_PARAMS_MESSAGE_ID" */
typedef struct NV2080_VGPU_FB_USAGE {
NvU32 gfid;
NV_DECLARE_ALIGNED(NvU64 fbUsed, 8);
} NV2080_VGPU_FB_USAGE;
#define NV2080_CTRL_VGPU_MGR_INTERNAL_GET_VGPU_FB_USAGE_PARAMS_MESSAGE_ID (0x6U)
typedef struct NV2080_CTRL_VGPU_MGR_INTERNAL_GET_VGPU_FB_USAGE_PARAMS {
NvU32 vgpuCount;
NV_DECLARE_ALIGNED(NV2080_VGPU_FB_USAGE vgpuFbUsage[NVA081_MAX_VGPU_PER_PGPU], 8);
} NV2080_CTRL_VGPU_MGR_INTERNAL_GET_VGPU_FB_USAGE_PARAMS;
/*
* NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_SET_VGPU_ENCODER_CAPACITY
*
* This command is used to set vGPU instance's (represented by gfid) encoder Capacity.
*
* gfid [IN]
* This parameter specifies the gfid of vGPU assigned to VM.
* encoderCapacity [IN]
* Encoder capacity value from 0 to 100. Value of 0x00 indicates encoder performance
* may be minimal for this GPU and software should fall back to CPU-based encode.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_OBJECT_NOT_FOUND
*/
#define NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_SET_VGPU_ENCODER_CAPACITY (0x20804007) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_VGPU_MGR_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_ENCODER_CAPACITY_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_ENCODER_CAPACITY_PARAMS_MESSAGE_ID (0x7U)
typedef struct NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_ENCODER_CAPACITY_PARAMS {
NvU32 gfid;
NvU32 encoderCapacity;
} NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_ENCODER_CAPACITY_PARAMS;
/*
* NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_VGPU_PLUGIN_CLEANUP
*
* This command is used to cleanup all the GSP VGPU plugin task allocated resources after its shutdown.
* Can be called only with SR-IOV and with VGPU_GSP_PLUGIN_OFFLOAD feature.
*
* gfid [IN]
* This parameter specifies the gfid of vGPU assigned to VM.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_NOT_SUPPORTED
*/
#define NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_VGPU_PLUGIN_CLEANUP (0x20804008) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_VGPU_MGR_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_VGPU_MGR_INTERNAL_VGPU_PLUGIN_CLEANUP_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_VGPU_MGR_INTERNAL_VGPU_PLUGIN_CLEANUP_PARAMS_MESSAGE_ID (0x8U)
typedef struct NV2080_CTRL_VGPU_MGR_INTERNAL_VGPU_PLUGIN_CLEANUP_PARAMS {
NvU32 gfid;
} NV2080_CTRL_VGPU_MGR_INTERNAL_VGPU_PLUGIN_CLEANUP_PARAMS;
#define NV2080_CTRL_MAX_NVU32_TO_CONVERTED_STR_LEN 8
#define NV2080_CTRL_MAX_GPC_COUNT 32
/*
* NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_GET_PGPU_FS_ENCODING
*
* Reroutes kvgpumgrGetPgpuFSEncoding to vgpuMgrGetPgpuFSEncoding.
*
* pgpuString [OUT]
* Resulting PGPU string
* pgpuStringSize
* PGPU string size
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
*/
#define NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_GET_PGPU_FS_ENCODING (0x20804009) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_VGPU_MGR_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_VGPU_MGR_INTERNAL_GET_PGPU_FS_ENCODING_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_VGPU_MGR_INTERNAL_GET_PGPU_FS_ENCODING_PARAMS_MESSAGE_ID (0x9U)
typedef struct NV2080_CTRL_VGPU_MGR_INTERNAL_GET_PGPU_FS_ENCODING_PARAMS {
NvU8 pgpuString[NVA081_PGPU_METADATA_STRING_SIZE];
NvU32 pgpuStringSize;
} NV2080_CTRL_VGPU_MGR_INTERNAL_GET_PGPU_FS_ENCODING_PARAMS;
/*
* NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_GET_PGPU_MIGRATION_SUPPORT
*
* Reroutes kvgpumgrCheckPgpuMigrationSupport to vgpuMgrCheckPgpuMigrationSupport.
*
* bIsMigrationSupported [OUT]
* Resulting status of the migration support
*
* Possible status values returned are:
* NV_OK
*/
#define NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_GET_PGPU_MIGRATION_SUPPORT (0x2080400a) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_VGPU_MGR_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_VGPU_MGR_INTERNAL_GET_PGPU_MIGRATION_SUPPORT_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_VGPU_MGR_INTERNAL_GET_PGPU_MIGRATION_SUPPORT_PARAMS_MESSAGE_ID (0xAU)
typedef struct NV2080_CTRL_VGPU_MGR_INTERNAL_GET_PGPU_MIGRATION_SUPPORT_PARAMS {
NvBool bIsMigrationSupported;
} NV2080_CTRL_VGPU_MGR_INTERNAL_GET_PGPU_MIGRATION_SUPPORT_PARAMS;
/*
* NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_SET_VGPU_MGR_CONFIG
*
* Sets vgpu manager parameters. This control is used after GSP initialization.
*
* bSupportHeterogeneousTimeSlicedVgpuTypes [IN]
* Enable/disable heterogeneous time-sliced vgpu types
*
* Possible status values returned are:
* NV_OK
*/
#define NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_SET_VGPU_MGR_CONFIG (0x2080400b) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_VGPU_MGR_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_MGR_CONFIG_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_MGR_CONFIG_PARAMS_MESSAGE_ID (0xBU)
typedef struct NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_MGR_CONFIG_PARAMS {
NvBool bSupportHeterogeneousTimeSlicedVgpuTypes;
} NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_MGR_CONFIG_PARAMS;
/* _ctrl2080vgpumgrinternal_h_ */