NVIDIA/open-gpu-kernel-modules
1
0
Fork 0
mirror of https://github.com/NVIDIA/open-gpu-kernel-modules.git synced 2026-02-28 19:03:58 +00:00
Code Issues Packages Projects Releases Wiki Activity

525.53

Browse Source
This commit is contained in:
Andy Ritger
2022-11-10 08:39:33 -08:00
parent 7c345b838b
commit 758b4ee818
1323 changed files with 262135 additions and 60754 deletions
Download Patch File Download Diff File Expand all files Collapse all files

47
src/nvidia/arch/nvalloc/common/inc/fsp/fsp_emem_channels.h Normal file
View File

@@ -0,0 +1,47 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _FSP_EMEM_CHANNELS_H_
#define _FSP_EMEM_CHANNELS_H_
//
// NVDM (NVIDIA Data Model) overlayed on MCTP (Management Component Transport
// Protocol) and sent over EMEM is the communication mechanism used between FSP
// management partition and CPU-RM/other uprocs.
//
// RM uses channel 0 for FSP EMEM.
#define FSP_EMEM_CHANNEL_RM 0x0
// PMU/SOE use channel 4 for FSP EMEM.
#define FSP_EMEM_CHANNEL_PMU_SOE 0x4
#define FSP_EMEM_CHANNEL_MAX 0x8
// EMEM channel 0 (RM) is allocated 1K bytes.
#define FSP_EMEM_CHANNEL_RM_SIZE 1024
// EMEM channel 4 (PMU/SOE) is allocated 1K bytes.
#define FSP_EMEM_CHANNEL_PMU_SOE_SIZE 1024
#define FSP_EMEM_CHANNEL_PMU_SOE_OFFSET 4096
#endif // _FSP_EMEM_CHANNELS_H_

55
src/nvidia/arch/nvalloc/common/inc/fsp/fsp_mctp_format.h Normal file
View File

@@ -0,0 +1,55 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _FSP_MCTP_FORMAT_H_
#define _FSP_MCTP_FORMAT_H_
//
// NVDM (NVIDIA Data Model) overlayed on MCTP (Management Component Transport
// Protocol) and sent over EMEM is the communication mechanism used between FSP
// management partition and CPU-RM/other uprocs.
//
#define MCTP_HEADER_VERSION 3:0
#define MCTP_HEADER_RSVD 7:4
#define MCTP_HEADER_DEID 15:8
#define MCTP_HEADER_SEID 23:16
#define MCTP_HEADER_TAG 26:24
#define MCTP_HEADER_TO 27:27
#define MCTP_HEADER_SEQ 29:28
#define MCTP_HEADER_EOM 30:30
#define MCTP_HEADER_SOM 31:31
#define MCTP_MSG_HEADER_TYPE 6:0
#define MCTP_MSG_HEADER_IC 7:7
#define MCTP_MSG_HEADER_VENDOR_ID 23:8
#define MCTP_MSG_HEADER_NVDM_TYPE 31:24
#define MCTP_MSG_HEADER_TYPE_VENDOR_PCI 0x7e
#define MCTP_MSG_HEADER_VENDOR_ID_NV 0x10de
#endif // _FSP_MCTP_FORMAT_H_

43
src/nvidia/arch/nvalloc/common/inc/fsp/fsp_nvdm_format.h Normal file
View File

@@ -0,0 +1,43 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _FSP_NVDM_FORMAT_H_
#define _FSP_NVDM_FORMAT_H_
#include "fsp/fsp_mctp_format.h"
#include "fsp/fsp_emem_channels.h"
//
// NVDM (NVIDIA Data Model) overlayed on MCTP (Management Component Transport
// Protocol) and sent over EMEM is the communication mechanism used between FSP
// management partition and CPU-RM/other uprocs.
//
#define NVDM_TYPE_HULK 0x11
#define NVDM_TYPE_FIRMWARE_UPDATE 0x12
#define NVDM_TYPE_COT 0x14
#define NVDM_TYPE_FSP_RESPONSE 0x15
#define NVDM_TYPE_INFOROM 0x17
#define NVDM_TYPE_SMBPBI 0x18
#endif // _FSP_NVDM_FORMAT_H_

155
src/nvidia/arch/nvalloc/common/inc/gsp/gsp_fw_wpr_meta.h Normal file
View File

@@ -0,0 +1,155 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
#ifndef GSP_FW_WPR_META_H_
#define GSP_FW_WPR_META_H_
/*!
* GSP firmware WPR metadata
*
* Initialized by CPU-RM and DMA'd to FB, at the end of what will be WPR2.
* Verified, and locked in WPR2 by Booter.
*
* Firmware scrubs the last 256mb of FB, no memory outside of this region
* may be used until the FW RM has scrubbed the remainder of memory.
*
* ---------------------------- <- fbSize (end of FB, 1M aligned)
* | VGA WORKSPACE |
* ---------------------------- <- vbiosReservedOffset (64K? aligned)
* | (potential align. gap) |
* ---------------------------- <- gspFwWprEnd (128K aligned)
* | FRTS data | (frtsSize is 0 on GA100)
* | ------------------------ | <- frtsOffset
* | BOOT BIN (e.g. SK + BL) |
* ---------------------------- <- bootBinOffset
* | GSP FW ELF |
* ---------------------------- <- gspFwOffset
* | GSP FW (WPR) HEAP |
* ---------------------------- <- gspFwHeapOffset
* | Booter-placed metadata |
* | (struct GspFwWprMeta) |
* ---------------------------- <- gspFwWprStart (128K aligned)
* | GSP FW (non-WPR) HEAP |
* ---------------------------- <- nonWprHeapOffset, gspFwRsvdStart
* (GSP_CARVEOUT_SIZE bytes from end of FB)
*/
typedef struct
{
// Magic
// BL to use for verification (i.e. Booter locked it in WPR2)
NvU64 magic; // = 0xdc3aae21371a60b3;
// Revision number of Booter-BL-Sequencer handoff interface
// Bumped up when we change this interface so it is not backward compatible.
// Bumped up when we revoke GSP-RM ucode
NvU64 revision; // = 1;
// ---- Members regarding data in SYSMEM ----------------------------
// Consumed by Booter for DMA
NvU64 sysmemAddrOfRadix3Elf;
NvU64 sizeOfRadix3Elf;
NvU64 sysmemAddrOfBootloader;
NvU64 sizeOfBootloader;
// Offsets inside bootloader image needed by Booter
NvU64 bootloaderCodeOffset;
NvU64 bootloaderDataOffset;
NvU64 bootloaderManifestOffset;
NvU64 sysmemAddrOfSignature;
NvU64 sizeOfSignature;
// ---- Members describing FB layout --------------------------------
NvU64 gspFwRsvdStart;
NvU64 nonWprHeapOffset;
NvU64 nonWprHeapSize;
NvU64 gspFwWprStart;
// GSP-RM to use to setup heap.
NvU64 gspFwHeapOffset;
NvU64 gspFwHeapSize;
// BL to use to find ELF for jump
NvU64 gspFwOffset;
// Size is sizeOfRadix3Elf above.
NvU64 bootBinOffset;
// Size is sizeOfBootloader above.
NvU64 frtsOffset;
NvU64 frtsSize;
NvU64 gspFwWprEnd;
// GSP-RM to use for fbRegionInfo?
NvU64 fbSize;
// ---- Other members -----------------------------------------------
// GSP-RM to use for fbRegionInfo?
NvU64 vgaWorkspaceOffset;
NvU64 vgaWorkspaceSize;
// Boot count. Used to determine whether to load the firmware image.
NvU64 bootCount;
// TODO: the partitionRpc* fields below do not really belong in this
// structure. The values are patched in by the partition bootstrapper
// when GSP-RM is booted in a partition, and this structure was a
// convenient place for the bootstrapper to access them. These should
// be moved to a different comm. mechanism between the bootstrapper
// and the GSP-RM tasks.
// Shared partition RPC memory (physical address)
NvU64 partitionRpcAddr;
// Offsets relative to partitionRpcAddr
NvU16 partitionRpcRequestOffset;
NvU16 partitionRpcReplyOffset;
// Code section and dataSection offset and size.
NvU32 elfCodeOffset;
NvU32 elfDataOffset;
NvU32 elfCodeSize;
NvU32 elfDataSize;
// Pad structure to exactly 256 bytes. Can replace padding with additional
// fields without incrementing revision. Padding initialized to 0.
NvU32 padding[3];
// BL to use for verification (i.e. Booter says OK to boot)
NvU64 verified; // 0x0 -> unverified, 0xa0a0a0a0a0a0a0a0 -> verified
} GspFwWprMeta;
#define GSP_FW_WPR_META_VERIFIED 0xa0a0a0a0a0a0a0a0ULL
#define GSP_FW_WPR_META_REVISION 1
#define GSP_FW_WPR_META_MAGIC 0xdc3aae21371a60b3ULL
#endif // GSP_FW_WPR_META_H_

16
src/nvidia/arch/nvalloc/common/inc/gsp/gspifpub.h
View File

@@ -44,11 +44,11 @@ typedef enum {
/*!
* @brief GSP-CC Microcode Initialization Parameters
*/
typedef struct GSP_CC_INIT_PARAMS
typedef struct GSP_FMC_INIT_PARAMS
{
// CC initialization "registry keys"
NvU32 regkeys;
} GSP_CC_INIT_PARAMS;
} GSP_FMC_INIT_PARAMS;
/*!
* @brief GSP-ACR BOOT_GSP_RM Command Parameters
@@ -68,6 +68,8 @@ typedef struct GSP_ACR_BOOT_GSP_RM_PARAMS
NvU64 wprCarveoutOffset;
// Size in bytes of the WPR containing GSP-RM
NvU32 wprCarveoutSize;
// Whether to boot GSP-RM or GSP-Proxy through ACR
NvBool bIsGspRmBoot;
} GSP_ACR_BOOT_GSP_RM_PARAMS;
/*!
@@ -84,11 +86,11 @@ typedef struct GSP_RM_PARAMS
/*!
* @brief GSP-CC Microcode Parameters for Boot Partitions
*/
typedef struct GSP_CC_BOOT_PARAMS
typedef struct GSP_FMC_BOOT_PARAMS
{
GSP_CC_INIT_PARAMS initParams;
GSP_ACR_BOOT_GSP_RM_PARAMS bootGspRmParams;
GSP_RM_PARAMS gspRmParams;
} GSP_CC_BOOT_PARAMS;
GSP_FMC_INIT_PARAMS initParams;
GSP_ACR_BOOT_GSP_RM_PARAMS bootGspRmParams;
GSP_RM_PARAMS gspRmParams;
} GSP_FMC_BOOT_PARAMS;
#endif // GSPIFPUB_H

62
src/nvidia/arch/nvalloc/common/inc/nv-firmware-chip-family-select.h Normal file
View File

@@ -0,0 +1,62 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef NV_FIRMWARE_CHIP_FAMILY_SELECT_H
#define NV_FIRMWARE_CHIP_FAMILY_SELECT_H
#include <published/nv_arch.h>
#include <nv-firmware.h>
static inline nv_firmware_chip_family_t nv_firmware_get_chip_family(
NvU32 gpuArch,
NvU32 gpuImpl
)
{
switch (gpuArch)
{
case GPU_ARCHITECTURE_TURING:
if (gpuImpl <= GPU_IMPLEMENTATION_TU106)
return NV_FIRMWARE_CHIP_FAMILY_TU10X;
else
return NV_FIRMWARE_CHIP_FAMILY_TU11X;
case GPU_ARCHITECTURE_AMPERE:
if (gpuImpl == GPU_IMPLEMENTATION_GA100)
return NV_FIRMWARE_CHIP_FAMILY_GA100;
else
return NV_FIRMWARE_CHIP_FAMILY_GA10X;
case GPU_ARCHITECTURE_ADA:
return NV_FIRMWARE_CHIP_FAMILY_AD10X;
case GPU_ARCHITECTURE_HOPPER:
if (gpuImpl == GPU_IMPLEMENTATION_GH100)
return NV_FIRMWARE_CHIP_FAMILY_GH100;
}
return NV_FIRMWARE_CHIP_FAMILY_NULL;
}
#endif // NV_FIRMWARE_CHIP_FAMILY_SELECT_H

132
src/nvidia/arch/nvalloc/common/inc/nv-firmware.h Normal file
View File

@@ -0,0 +1,132 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef NV_FIRMWARE_H
#define NV_FIRMWARE_H
#include <nvtypes.h>
#include <nvmisc.h>
typedef enum
{
NV_FIRMWARE_TYPE_GSP,
NV_FIRMWARE_TYPE_GSP_LOG
} nv_firmware_type_t;
typedef enum
{
NV_FIRMWARE_CHIP_FAMILY_NULL = 0,
NV_FIRMWARE_CHIP_FAMILY_TU10X = 1,
NV_FIRMWARE_CHIP_FAMILY_TU11X = 2,
NV_FIRMWARE_CHIP_FAMILY_GA100 = 3,
NV_FIRMWARE_CHIP_FAMILY_GA10X = 4,
NV_FIRMWARE_CHIP_FAMILY_AD10X = 5,
NV_FIRMWARE_CHIP_FAMILY_GH100 = 6,
NV_FIRMWARE_CHIP_FAMILY_END,
} nv_firmware_chip_family_t;
static inline const char *nv_firmware_chip_family_to_string(
nv_firmware_chip_family_t fw_chip_family
)
{
switch (fw_chip_family) {
case NV_FIRMWARE_CHIP_FAMILY_GH100: return "gh100";
case NV_FIRMWARE_CHIP_FAMILY_AD10X: return "ad10x";
case NV_FIRMWARE_CHIP_FAMILY_GA10X: return "ga10x";
case NV_FIRMWARE_CHIP_FAMILY_GA100: return "ga100";
case NV_FIRMWARE_CHIP_FAMILY_TU11X: return "tu11x";
case NV_FIRMWARE_CHIP_FAMILY_TU10X: return "tu10x";
case NV_FIRMWARE_CHIP_FAMILY_END: // fall through
case NV_FIRMWARE_CHIP_FAMILY_NULL:
return NULL;
}
return NULL;
}
// The includer (presumably nv.c) may optionally define
// NV_FIRMWARE_PATH_FOR_FILENAME(filename)
// to return a string "path" given a gsp_*.bin or gsp_log_*.bin filename.
//
// The function nv_firmware_path will then be available.
#if defined(NV_FIRMWARE_PATH_FOR_FILENAME)
static inline const char *nv_firmware_path(
nv_firmware_type_t fw_type,
nv_firmware_chip_family_t fw_chip_family
)
{
if (fw_type == NV_FIRMWARE_TYPE_GSP)
{
switch (fw_chip_family)
{
case NV_FIRMWARE_CHIP_FAMILY_AD10X:
return NV_FIRMWARE_PATH_FOR_FILENAME("gsp_ad10x.bin");
case NV_FIRMWARE_CHIP_FAMILY_GH100: // fall through
case NV_FIRMWARE_CHIP_FAMILY_GA100: // fall through
case NV_FIRMWARE_CHIP_FAMILY_GA10X: // fall through
case NV_FIRMWARE_CHIP_FAMILY_TU11X: // fall through
case NV_FIRMWARE_CHIP_FAMILY_TU10X:
return NV_FIRMWARE_PATH_FOR_FILENAME("gsp_tu10x.bin");
case NV_FIRMWARE_CHIP_FAMILY_END: // fall through
case NV_FIRMWARE_CHIP_FAMILY_NULL:
return "";
}
}
else if (fw_type == NV_FIRMWARE_TYPE_GSP_LOG)
{
switch (fw_chip_family)
{
case NV_FIRMWARE_CHIP_FAMILY_AD10X:
return NV_FIRMWARE_PATH_FOR_FILENAME("gsp_log_ad10x.bin");
case NV_FIRMWARE_CHIP_FAMILY_GH100: // fall through
case NV_FIRMWARE_CHIP_FAMILY_GA100: // fall through
case NV_FIRMWARE_CHIP_FAMILY_GA10X: // fall through
case NV_FIRMWARE_CHIP_FAMILY_TU11X: // fall through
case NV_FIRMWARE_CHIP_FAMILY_TU10X:
return NV_FIRMWARE_PATH_FOR_FILENAME("gsp_log_tu10x.bin");
case NV_FIRMWARE_CHIP_FAMILY_END: // fall through
case NV_FIRMWARE_CHIP_FAMILY_NULL:
return "";
}
}
return "";
}
#endif // defined(NV_FIRMWARE_PATH_FOR_FILENAME)
// The includer (presumably nv.c) may optionally define
// NV_FIRMWARE_DECLARE_GSP_FILENAME(filename)
// which will then be invoked (at the top-level) for each
// gsp_*.bin (but not gsp_log_*.bin)
#if defined(NV_FIRMWARE_DECLARE_GSP_FILENAME)
NV_FIRMWARE_DECLARE_GSP_FILENAME("gsp_ad10x.bin")
NV_FIRMWARE_DECLARE_GSP_FILENAME("gsp_tu10x.bin")
#endif // defined(NV_FIRMWARE_DECLARE_GSP_FILENAME)
#endif // NV_FIRMWARE_DECLARE_GSP_FILENAME

17
src/nvidia/arch/nvalloc/common/inc/nvcst.h
View File

@@ -27,6 +27,7 @@
#include <platform/chipset/chipset.h>
#include <platform/chipset/chipset_info.h>
#include <nvpcie.h>
#include <nvdevid.h>
#define CHIPSET_SETUP_FUNC(name) static NV_STATUS name(OBJCL *pCl);
@@ -86,7 +87,6 @@ CHIPSET_SETUP_FUNC(Huawei_Kunpeng920_setupFunc)
CHIPSET_SETUP_FUNC(Mellanox_BlueField_setupFunc)
CHIPSET_SETUP_FUNC(Amazon_Gravitron2_setupFunc)
CHIPSET_SETUP_FUNC(Fujitsu_A64FX_setupFunc)
CHIPSET_SETUP_FUNC(Phytium_FT2000_setupFunc)
CHIPSET_SETUP_FUNC(Ampere_Altra_setupFunc)
CHIPSET_SETUP_FUNC(Arm_NeoverseN1_setupFunc)
CHIPSET_SETUP_FUNC(Nvidia_T210_setupFunc)
@@ -154,6 +154,7 @@ CSINFO chipsetInfo[] =
{PCI_VENDOR_ID_INTEL, 0xA14A, CS_INTEL_A145, "SkyLake C232", Intel_A145_setupFunc},
{PCI_VENDOR_ID_INTEL, 0xA14D, CS_INTEL_A145, "SkyLake-H", Intel_A145_setupFunc},
{PCI_VENDOR_ID_INTEL, 0xA244, CS_INTEL_A145, "SkyLake C620", Intel_A145_setupFunc},
{PCI_VENDOR_ID_INTEL, 0xA1C8, CS_INTEL_A145, "SkyLake C620", Intel_A145_setupFunc},
{PCI_VENDOR_ID_INTEL, 0x8D47, CS_INTEL_8D47, "IntelX99", Intel_8D47_setupFunc},
{PCI_VENDOR_ID_INTEL, 0x8D44, CS_INTEL_8D47, "IntelC612", Intel_8D44_setupFunc},
{PCI_VENDOR_ID_INTEL, 0xA2C5, CS_INTEL_A2C5, "IntelZ270", Intel_A2C5_setupFunc},
@@ -239,12 +240,6 @@ CSINFO chipsetInfo[] =
{PCI_VENDOR_ID_MELLANOX, 0xA2D5, CS_MELLANOX_BLUEFIELD2, "Mellanox BlueField 2 Crypto disabled", NULL},
{PCI_VENDOR_ID_AMAZON, 0x0200, CS_AMAZON_GRAVITRON2, "Amazon Gravitron2", Amazon_Gravitron2_setupFunc},
{PCI_VENDOR_ID_FUJITSU, 0x1952, CS_FUJITSU_A64FX, "Fujitsu A64FX", Fujitsu_A64FX_setupFunc},
{PCI_VENDOR_ID_CADENCE, 0xDC01, CS_PHYTIUM_FT2000, "Phytium FT2000", Phytium_FT2000_setupFunc},
{PCI_VENDOR_ID_CADENCE, 0xDC08, CS_PHYTIUM_FT2000, "Phytium FT2000", Phytium_FT2000_setupFunc},
{PCI_VENDOR_ID_CADENCE, 0xDC16, CS_PHYTIUM_FT2000, "Phytium FT2000", Phytium_FT2000_setupFunc},
{PCI_VENDOR_ID_CADENCE, 0xFC01, CS_PHYTIUM_FT2000, "Phytium FT2000", Phytium_FT2000_setupFunc},
{PCI_VENDOR_ID_CADENCE, 0xFC08, CS_PHYTIUM_FT2000, "Phytium FT2000", Phytium_FT2000_setupFunc},
{PCI_VENDOR_ID_CADENCE, 0xFC16, CS_PHYTIUM_FT2000, "Phytium FT2000", Phytium_FT2000_setupFunc},
{PCI_VENDOR_ID_CADENCE, 0xDC01, CS_PHYTIUM_S2500, "Phytium S2500", NULL},
{PCI_VENDOR_ID_CADENCE, 0xDC08, CS_PHYTIUM_S2500, "Phytium S2500", NULL},
{PCI_VENDOR_ID_CADENCE, 0xDC16, CS_PHYTIUM_S2500, "Phytium S2500", NULL},
@@ -335,18 +330,12 @@ ARMCSALLOWLISTINFO armChipsetAllowListInfo[] =
{PCI_VENDOR_ID_MELLANOX, 0xA2D5, CS_MELLANOX_BLUEFIELD2},// Mellanox BlueField 2 Crypto disabled
{PCI_VENDOR_ID_AMAZON, 0x0200, CS_AMAZON_GRAVITRON2}, // Amazon Gravitron2
{PCI_VENDOR_ID_FUJITSU, 0x1952, CS_FUJITSU_A64FX}, // Fujitsu A64FX
{PCI_VENDOR_ID_CADENCE, 0xDC01, CS_PHYTIUM_FT2000}, // Phytium FT2000
{PCI_VENDOR_ID_CADENCE, 0xDC08, CS_PHYTIUM_FT2000}, // Phytium FT2000
{PCI_VENDOR_ID_CADENCE, 0xDC16, CS_PHYTIUM_FT2000}, // Phytium FT2000
{PCI_VENDOR_ID_CADENCE, 0xFC01, CS_PHYTIUM_FT2000}, // Phytium FT2000
{PCI_VENDOR_ID_CADENCE, 0xFC08, CS_PHYTIUM_FT2000}, // Phytium FT2000
{PCI_VENDOR_ID_CADENCE, 0xFC16, CS_PHYTIUM_FT2000}, // Phytium FT2000
{PCI_VENDOR_ID_CADENCE, 0xDC01, CS_PHYTIUM_S2500}, // Phytium S2500
{PCI_VENDOR_ID_CADENCE, 0xDC08, CS_PHYTIUM_S2500}, // Phytium S2500
{PCI_VENDOR_ID_CADENCE, 0xDC16, CS_PHYTIUM_S2500}, // Phytium S2500
{PCI_VENDOR_ID_CADENCE, 0xFC01, CS_PHYTIUM_S2500}, // Phytium S2500
{PCI_VENDOR_ID_CADENCE, 0xFC08, CS_PHYTIUM_S2500}, // Phytium S2500
{PCI_VENDOR_ID_CADENCE, 0xDC16, CS_PHYTIUM_S2500}, // Phytium S2500
{PCI_VENDOR_ID_CADENCE, 0xFC16, CS_PHYTIUM_S2500}, // Phytium S2500
{PCI_VENDOR_ID_AMPERE, 0xE000, CS_AMPERE_ALTRA}, // Ampere Altra
{PCI_VENDOR_ID_AMPERE, 0xE00D, CS_AMPERE_ALTRA}, // Ampere Altra
{PCI_VENDOR_ID_AMPERE, 0xE00E, CS_AMPERE_ALTRA}, // Ampere Altra

2
src/nvidia/arch/nvalloc/common/inc/nvdevid.h
View File

@@ -156,6 +156,7 @@
///////////////////////////////////////////////////////////////////////////////////////////
#define NV_PCI_DEVID_DEVICE_PG171_SKU200_PG179_SKU220 0x25B6 /* NVIDIA A16 / NVIDIA A2 */
#define NV_PCI_DEVID_DEVICE_PG189_SKU600 0x1EBA
///////////////////////////////////////////////////////////////////////////////////////////
//
@@ -633,7 +634,6 @@ enum {
, CS_MELLANOX_BLUEFIELD
, CS_AMAZON_GRAVITRON2
, CS_FUJITSU_A64FX
, CS_PHYTIUM_FT2000
, CS_AMPERE_ALTRA
, CS_ARM_NEOVERSEN1
, CS_MARVELL_OCTEON_CN96XX

257
src/nvidia/arch/nvalloc/common/inc/nvpcie.h
View File

@@ -58,26 +58,81 @@
#define PCI_MULTIFUNCTION 0x80
// From PCI Local Bus Specification, Revision 3.0
// and PCI Express Base Specification 6.0
// numbers in comments to right of values indicate
// the referenced section in the PCIE spec
#define CAP_ID_MASK 0xFF
#define CAP_ID_PMI 0x01
#define CAP_ID_AGP 0x02
#define CAP_ID_VPD 0x03
#define CAP_ID_SLOT_ID 0x04
#define CAP_ID_MSI 0x05
#define CAP_ID_HOT_SWAP 0x06
#define CAP_ID_PCI_X 0x07
#define CAP_ID_HYPER_TRANSPORT 0x08
#define CAP_ID_VENDOR_SPECIFIC 0x09
#define CAP_ID_DEBUG_PORT 0x0A
#define CAP_ID_CRC 0x0B
#define CAP_ID_HOT_PLUG 0x0C
#define CAP_ID_SUBSYSTEM_ID 0x0D
#define CAP_ID_AGP8X 0x0E
#define CAP_ID_SECURE 0x0F
#define CAP_ID_PCI_EXPRESS 0x10
#define CAP_ID_MSI_X 0x11
#define CAP_ID_MASK 0xFF
#define CAP_ID_NULL 0x00 // 7.9.28.1
#define CAP_ID_PMI 0x01 // 7.5.2.1
#define CAP_ID_AGP 0x02
#define CAP_ID_VPD 0x03 // 7.9.18.1
#define CAP_ID_SLOT_ID 0x04
#define CAP_ID_MSI 0x05 // 7.7.1.1
#define CAP_ID_HOT_SWAP 0x06
#define CAP_ID_PCI_X 0x07
#define CAP_ID_HYPER_TRANSPORT 0x08
#define CAP_ID_VENDOR_SPECIFIC 0x09
#define CAP_ID_DEBUG_PORT 0x0A
#define CAP_ID_CRC 0x0B
#define CAP_ID_HOT_PLUG 0x0C
#define CAP_ID_SUBSYSTEM_ID 0x0D // 7.9.23.1
#define CAP_ID_AGP8X 0x0E
#define CAP_ID_SECURE 0x0F
#define CAP_ID_PCI_EXPRESS 0x10 // 7.5.3.1
#define CAP_ID_MSI_X 0x11 // 7.7.2.1
#define CAP_ID_ENHANCED_ALLOCATION 0x14 // 7.8.5.1
#define CAP_ID_FPB 0x15 // 7.8.11.1
#define CAP_ID_AF 0x13 // 7.9.21.1
//
// sizes for static PCI capabilities structure
//
#define CAP_NULL_SIZE 0x04 // 7.9.28
#define CAP_PMI_SIZE 0x08 // 7.5.2
#define CAP_VPD_SIZE 0x08 // 7.9.18
#define CAP_PCI_X_SIZE 0x3C // 7.5.3
#define CAP_PCI_EXPRESS_SIZE 0x3C // 7.5.3
#define CAP_FPB_SIZE 0x08 // 7.8.11.1
#define CAP_AF_SIZE 0x08 // 7.9.21
#define CAP_SUBSYSTEM_ID_SIZE 0x08 // 7.9.23
// MSI capability size related fields
#define PCI_MSI_CONTROL 0x02 // 7.7.1.2
#define PCI_MSI_CONTROL_64BIT_CAPABLE 7:7
#define PCI_MSI_CONTROL_64BIT_CAPABLE_FALSE 0
#define PCI_MSI_CONTROL_64BIT_CAPABLE_TRUE 1
#define PCI_MSI_CONTROL_PVM_CAPABLE 8:8
#define PCI_MSI_CONTROL_PVM_CAPABLE_FALSE 0
#define PCI_MSI_CONTROL_PVM_CAPABLE_TRUE 1
#define PCI_MSI_BASE_SIZE 0x0C // 7.7.1
#define PCI_MSI_64BIT_ADDR_CAPABLE_ADJ_SIZE 0x04 // 7.7.1
#define PCI_MSI_PVM_CAPABLE_ADJ_SIZE 0x08 // 7.7.1
// MSI-X capability size related fields
#define PCI_MSI_X_BASE_SIZE 0x0C // 7.7.2
#define PCI_MSI_X_CONTROL 0x02 // 7.7.2.2
#define PCI_MSI_X_CONTROL_TABLE_SIZE 10:0
#define PCI_MSI_X_TABLE_OFFSET_BIR 0x04 // 7.7.2.3
#define PCI_MSI_X_TABLE_OFFSET 31:3
#define PCI_MSI_X_PBR_OFFSET_BIR 0x08 // 7.7.2.4
#define PCI_MSI_X_PBR_OFFSET 31:3
#define PCI_MSI_X_TABLE_ENTRY_SIZE 0x10 // 7.7.2
#define PCI_MSI_X_PBR_ENTRY_SIZE 0x10 // 7.7.2
// Enhanced Allocation Capability size related fields
#define PCI_ENHANCED_ALLOCATION_FIRST_DW 0x00 // 7.8.5.1
#define PCI_ENHANCED_ALLOCATION_FIRST_DW_NUM_ENTRIES 21:16
#define PCI_ENHANCED_ALLOCATION_TYPE_0_BASE_SIZE 0x04 // 7.8.5.1
#define PCI_ENHANCED_ALLOCATION_TYPE_1_BASE_SIZE 0x08 // 7.8.5.2
#define PCI_ENHANCED_ALLOCATION_ENTRY_HEADER 0x00 // 7.8.5.3
#define PCI_ENHANCED_ALLOCATION_ENTRY_HEADER_ENTRY_SIZE 2:0
// PCI Vendor Specific Capability size related fields
#define PCI_VENDOR_SPECIFIC_CAP_HEADER 0x00 // 7.9.4
#define PCI_VENDOR_SPECIFIC_CAP_HEADER_LENGTH 23:16
//
// Extended config space size is 4096 bytes.
@@ -99,6 +154,8 @@
#define PCI_HEADER_TYPE0_CACHE_LINE_SIZE 0x0C
#define PCI_HEADER_TYPE0_LATENCY_TIMER 0x0D
#define PCI_HEADER_TYPE0_HEADER_TYPE 0x0E
#define PCI_HEADER_TYPE0_HEADER_TYPE_0 0
#define PCI_HEADER_TYPE0_HEADER_TYPE_1 1
#define PCI_HEADER_TYPE0_BIST 0x0F
#define PCI_HEADER_TYPE0_BAR0 0x10
#define PCI_HEADER_TYPE0_BAR1 0x14
@@ -229,14 +286,120 @@
#define PCIE_LINK_STATUS_2_DE_EMPHASIS 0:0 // PCIE De-Emphasis Level
#define PCI_COMMON_SUBSYSTEM_VENDOR_ID 0x2c // PCI subsystem Vendor Id
#define PCI_COMMON_SUBSYSTEM_ID 0x2e // PCI subsystem Id
#define PCIE_CAPABILITY_BASE 0x100 // 1st PCIE capability.
// PCI Express Capability ID in the enhanced configuration space
#define PCIE_CAP_ID_ERROR 0x1 // PCIE Advanced Error Reporting
#define PCIE_CAP_ID_VC 0x2 // PCIE Virtual Channel (VC)
#define PCIE_CAP_ID_SERIAL 0x3 // PCIE Device Serial Number
#define PCIE_CAP_ID_POWER 0x4 // PCIE Power Budgeting
#define PCIE_CAP_ID_L1_PM_SUBSTATES 0x1E // PCIE L1 PM Substates
#define PCIE_CAP_ID_NULL 0x00 // 7.9.28.1
#define PCIE_CAP_ID_ERROR 0x01 // 7.8.4.1
#define PCIE_CAP_ID_VC 0x02 // 7.9.1.1
#define PCIE_CAP_ID_SERIAL 0x03 // 7.9.3.1
#define PCIE_CAP_ID_POWER 0x04 // 7.8.1.1
#define PCIE_CAP_ID_ROOT_COMPLEX 0x05 // 7.9.8.1
#define PCIE_CAP_ID_ROOT_COMPLEX_INTERNAL_LINK_CTRL 0x06 // 7.9.9.1
#define PCIE_CAP_ID_ROOT_COMPLEX_EVENT_COLLECTOR_ENDPOINT 0x07 // 7.9.10.1
#define PCIE_CAP_ID_PCIE_CAP_ID_MFVC 0x08 // 7.9.2.1
#define PCIE_CAP_ID_RCRB 0x0A // 7.9.7.1
#define PCIE_CAP_ID_ACS 0x0D // 7.7.11.1
#define PCIE_CAP_ID_ARI 0x0E // 7.8.8.1
#define PCIE_CAP_ID_MULTICAST 0x12 // 7.9.11.1
#define PCIE_CAP_ID_RESIZABLE_BAR 0x15 // 7.8.6.1
#define PCIE_CAP_ID_DYNAMIC_POWER_ALLOCATION 0x16 // 7.9.12.1
#define PCIE_CAP_ID_TPH 0x17 // 7.9.13.1
#define PCIE_CAP_ID_LATENCY_TOLERANCE 0x18 // 7.8.2.1
#define PCIE_CAP_ID_SECONDARY_PCIE_CAPABILITY 0x19 // 7.7.3.1
#define PCIE_CAP_ID_PASID 0x1B // 7.8.9.1
#define PCIE_CAP_ID_DPC 0x1D // 7.9.14.1
#define PCIE_CAP_ID_L1_PM_SUBSTATES 0x1E // 7.8.3.1
#define PCIE_CAP_ID_PTM 0x1F // 7.9.15.1
#define PCIE_CAP_ID_FRS_QUEUING 0x21 // 7.8.10.1
#define PCIE_CAP_ID_READINESS_TIME_REPORTING 0x22 // 7.9.16.1
#define PCIE_CAP_ID_VENDOR_SPECIFIC 0x23 // 7.9.6.1
#define PCIE_CAP_ID_VF_RESIZABLE_BAR 0x24 // 7.8.7.1
#define PCIE_CAP_ID_DATA_LINK 0x25 // 7.7.4.1
#define PCIE_CAP_ID_PHYSLAYER_16_GT 0x26 // 7.7.5.1
#define PCIE_CAP_ID_LANE_MARGINING_AT_RECEVER 0x27 // 7.7.10.1
#define PCIE_CAP_ID_HIERARCHY_ID 0x28 // 7.9.17.1
#define PCIE_CAP_ID_NPEM 0x29 // 7.9.19.1
#define PCIE_CAP_ID_PHYSLAYER_32_GT 0x2A // 7.7.6.1
#define PCIE_CAP_ID_ALTERNATE_PROTOCOL 0x2B // 7.9.20.1
#define PCIE_CAP_ID_SFI 0x2C // 7.9.22.1
#define PCIE_CAP_ID_SHADOW_FUNCTIONS 0x2D // 7.9.25.1
#define PCIE_CAP_ID_DATA_OBJECT_EXCHANGE 0x2E // 7.9.24.1
#define PCIE_CAP_ID_DEVICE_3 0x2F // 7.7.9.1
#define PCIE_CAP_ID_IDE 0x30 // 7.9.26.1
#define PCIE_CAP_ID_PHYSLAYER_64_GT 0x31 // 7.7.7.1
#define PCIE_CAP_ID_FLT_LOGGING 0x32 // 7.7.8.1
#define PCIE_CAP_ID_FLIT_PERF_MEASURMENT 0x33 // 7.8.12.1
#define PCIE_CAP_ID_FLIT_ERROR_INJECTION 0x34 // 7.8.13.1
// static sized structure sizes
#define PCIE_CAP_HEADER_SIZE 0x04 // 7.6.3
#define PCIE_CAP_NULL_SIZE 0x04 // 7.9.28
#define PCIE_CAP_ERROR_SIZE 0x48 // 7.8.4
#define PCIE_CAP_POWER_SIZE 0x10 // 7.8.1
#define PCIE_CAP_ROOT_COMPLEX_INTERNAL_LINK_CTRL_SIZE 0x0C // 7.9.9
#define PCIE_CAP_ROOT_COMPLEX_EVENT_COLLECTOR_ENDPOINT_SIZE 0x0C // 7.9.10
#define PCIE_CAP_SECONDARY_PCIE_SIZE 0x4C // 7.7.3.1
#define PCIE_CAP_DATA_LINK_SIZE 0x0C // 7.7.4
#define PCIE_CAP_PHYSLAYER_16_GT_SIZE 0x40 // 7.7.5
#define PCIE_CAP_PHYSLAYER_32_GT_SIZE 0x40 // 7.7.6
#define PCIE_CAP_PHYSLAYER_64_GT_SIZE 0x20 // 7.7.7
#define PCIE_CAP_FLT_LOGGING_SIZE 0x3C // 7.7.8
#define PCIE_CAP_DEVICE_3_SIZE 0x10 // 7.7.9
#define PCIE_CAP_LANE_MARGINING_AT_RECEVER_SIZE 0x88 // 7.7.10
#define PCIE_CAP_ACS_SIZE 0x10 // 7.7.11
#define PCIE_CAP_LATENCY_TOLERANCE_SIZE 0x08 // 7.8.2
#define PCIE_CAP_L1_PM_SUBSTATE_SIZE 0x14 // 7.8.3
#define PCIE_CAP_RESIZABLE_BAR_SIZE 0x34 // 7.8.6
#define PCIE_CAP_VF_RESIZABLE_BAR_SIZE 0x34 // 7.8.7
#define PCIE_CAP_ARI_SIZE 0x08 // 7.8.8
#define PCIE_CAP_PASID_SIZE 0x08 // 7.8.9
#define PCIE_CAP_FRS_QUEUING_SIZE 0x10 // 7.8.10
#define PCIE_CAP_FPB_SIZE 0x24 // 7.8.11
#define PCIE_CAP_FLIT_PERF_MEASURMENT_SIZE 0x24 // 7.8.12
#define PCIE_CAP_FLIT_ERROR_INJECTION_SIZE 0x24 // 7.8.13
#define PCIE_CAP_DEV_SERIAL_SIZE 0x0C // 7.9.3
#define PCIE_CAP_RCRB_SIZE 0x14 // 7.9.7
#define PCIE_CAP_MULTICAST_SIZE 0x30 // 7.9.11
#define PCIE_CAP_DYNAMIC_POWER_ALLOCATION_SIZE 0x30 // 7.9.12
#define PCIE_CAP_DPC_SIZE 0x5C // 7.9.14
#define PCIE_CAP_PTM_SIZE 0x0C // 7.9.15
#define PCIE_CAP_READINESS_TIME_REPORTING_SIZE 0x0C // 7.9.16
#define PCIE_CAP_HIERARCHY_ID_SIZE 0x0C // 7.9.17
#define PCIE_CAP_NPEM_SIZE 0x10 // 7.9.19
#define PCIE_CAP_ALTERNATE_PROTOCOL_SIZE 0x14 // 7.9.20
#define PCIE_CAP_SFI_SIZE 0x14 // 7.9.22
#define PCIE_CAP_DATA_OBJECT_EXCHANGE_SIZE 0x18 // 7.9.24
#define PCIE_CAP_SHADOW_FUNCTIONS_SIZE 0x1C // 7.9.25
#define PCIE_CAP_IDE_SIZE 0x34 // 7.9.26
// Virtual Channel Capability size related fields
#define PCIE_VC_REGISTER_1 0x04 // 7.9.1.2
#define PCIE_VC_REGISTER_1_EXTENDED_VC_COUNT 2:0
#define PCIE_VIRTUAL_CHANNELS_BASE_SIZE 0x18 // 7.9.1
#define PCIE_VIRTUAL_CHANNELS_EXTENDED_VC_ENTRY_SIZE 0x10 // 7.9.1
// Multi Function Virtual Channel Capability size related fields
#define PCIE_MFVC_REGISTER_1 0x04 // 7.9.2.2
#define PCIE_MFVC_REGISTER_1_EXTENDED_VC_COUNT 2:0
#define PCIE_PCIE_CAP_ID_MFVC_BASE_SIZE 0x18 // 7.9.2
#define PCIE_PCIE_CAP_ID_MFVC_EXTENDED_VC_ENTRY_SIZE 0x10 // 7.9.2
// Vendor Specific Capability size related fields
#define PCIE_VENDOR_SPECIFIC_HEADER_1 0x04 // 7.9.6.2
#define PCIE_VENDOR_SPECIFIC_HEADER_1_LENGTH 31:20
// Root Complex Capability size related fields
#define PCIE_ROOT_COMPLEX_SELF_DESC_REGISTER 0x04 // 7.9.8.2
#define PCIE_ROOT_COMPLEX_SELF_DESC_REGISTER_NUM_LINK_ENTRIES 15:8
#define PCIE_ROOT_COMPLEX_BASE_SIZE 0x0C // 7.9.8
#define PCIE_ROOT_COMPLEX_LINK_ENTRY_SIZE 0x10 // 7.9.8.3
// TPH capability size related fields
#define PCIE_TPH_REQUESTOR_REGISTER 0x04 // 7.9.13.2
#define PCIE_TPH_REQUESTOR_REGISTER_ST_TABLE_SIZE 26:16
#define PCIE_TPH_BASE_SIZE 0x0C // 7.9.13
#define PCIE_TPH_ST_ENTRY_SIZE 0x02 // 7.9.13.4
// Intel CPU family.
#define INTEL_CPU_FAMILY_06 0x06
@@ -249,6 +412,7 @@
#define INTEL_CPU_MODEL_2D 0x2d
#define INTEL_CPU_MODEL_3A 0x3a
#define INTEL_CPU_MODEL_3F 0x3f
// Symbolic defines for each possible virtual channel
enum
{
@@ -263,6 +427,49 @@ enum
RM_PCIE_VIRTUAL_CHANNEL_INVALID
};
// Diagnostic collection actions.
#define RM_PCIE_ACTION_NOP 0
#define RM_PCIE_ACTION_COLLECT_CONFIG_SPACE 1
#define RM_PCIE_ACTION_COLLECT_PCI_CAP_STRUCT 2
#define RM_PCIE_ACTION_COLLECT_PCIE_CAP_STRUCT 3
#define RM_PCIE_ACTION_COLLECT_ALL_PCI_CAPS 4
#define RM_PCIE_ACTION_COLLECT_ALL_PCIE_CAPS 5
#define RM_PCIE_ACTION_REPORT_PCI_CAPS_COUNT 6
#define RM_PCIE_ACTION_REPORT_PCIE_CAPS_COUNT 7
#define RM_PCIE_ACTION_EOS 0xff
// Diagnostic collection device Type ids
#define RM_PCIE_DEVICE_TYPE_NONE 0xff
#define RM_PCIE_DEVICE_TYPE_GPU 0
#define RM_PCIE_DEVICE_TYPE_UPSTREAM_BRIDGE 1
#define RM_PCIE_DEVICE_COUNT 2
// Diagnostic collection capability Type ids
#define RM_PCIE_DC_CAP_TYPE_NONE 0xff
#define RM_PCIE_DC_CAP_TYPE_PCI 0
#define RM_PCIE_DC_CAP_TYPE_PCIE 1
#define RM_PCIE_DC_CAP_TYPE_COUNT 2
typedef struct _def_bif_dc_diagnostic_collection_command
{
NvU8 action;
NvU8 deviceType;
NvU16 locator;
NvU16 length;
} CL_PCIE_DC_DIAGNOSTIC_COLLECTION_ENTRY;
typedef struct _def_cl_pcie_dc_capability_map_entry
{
NvU16 id;
NvU16 blkOffset;
} CL_PCIE_DC_CAPABILITY_MAP_ENTRY;
typedef struct
{
NvU16 count;
CL_PCIE_DC_CAPABILITY_MAP_ENTRY entries[PCI_MAX_CAPS];
} CL_PCIE_DC_CAPABILITY_MAP;
struct OBJCL;
// root port setup functions
NV_STATUS Broadcom_HT2100_setupFunc(OBJGPU *, OBJCL*);
@@ -287,6 +494,6 @@ NV_STATUS AMD_RP1630_setupFunc(OBJGPU *, OBJCL*);
NV_STATUS AMD_RP1483_setupFunc(OBJGPU *, OBJCL*);
// Determines if the GPU is in a multi-GPU board based on devid checks
NvBool gpuIsMultiGpuBoard(OBJGPU *, NvBool *, NvBool *);
NvBool gpuIsMultiGpuBoard(OBJGPU *, NvBool *);
#endif // NVPCIE_H

94
src/nvidia/arch/nvalloc/common/inc/oob/smbpbi.h
View File

@@ -214,6 +214,8 @@
0x0000000f
#define NV_MSGBOX_CMD_ARG1_ASYNC_REQUEST_POWER_HINT_GET \
0x00000010
#define NV_MSGBOX_CMD_ARG1_ASYNC_REQUEST_CONFIGURE_PROGRAMMABLE_EDPP \
0x00000011
#define NV_MSGBOX_CMD_ARG1_ASYNC_REQUEST_POLL 0x000000ff
@@ -310,6 +312,11 @@
#define NV_MSGBOX_CMD_ARG1_BUNDLE_REQUEST_COUNT 11:8
#define NV_MSGBOX_CMD_ARG1_BUNDLE_DISP_RULE_COUNT 15:12
#define NV_MSGBOX_CMD_ARG1_GET_DEM_OLDEST 0x00000000
#define NV_MSGBOX_CMD_ARG1_GET_DEM_BY_SEQ_NUMBER 0x00000001
#define NV_MSGBOX_CMD_ARG1_GET_DEM_BY_TIMESTAMP 0x00000002
#define NV_MSGBOX_CMD_ARG1_ECC_V6_ERROR_TYPE 15:8
#define NV_MSGBOX_CMD_ARG1_ECC_V6_ERROR_TYPE_CORRECTABLE_ERROR 0
#define NV_MSGBOX_CMD_ARG1_ECC_V6_ERROR_TYPE_UNCORRECTABLE_ERROR 1
@@ -346,6 +353,16 @@
#define NV_MSGBOX_CMD_ARG1_GPM_METRIC_NVDEC_UTILIZATION 0x0000000E
#define NV_MSGBOX_CMD_ARG1_GPM_METRIC_NVJPG_UTILIZATION 0x0000000F
#define NV_MSGBOX_CMD_ARG1_GPM_METRIC_NVOFA_UTILIZATION 0x00000010
#define NV_MSGBOX_CMD_ARG1_GPM_METRIC_NVLINK_RAW_TX_BW_PER_LINK 0x00000011
#define NV_MSGBOX_CMD_ARG1_GPM_METRIC_NVLINK_DATA_TX_BW_PER_LINK 0x00000012
#define NV_MSGBOX_CMD_ARG1_GPM_METRIC_NVLINK_RAW_RX_BW_PER_LINK 0x00000013
#define NV_MSGBOX_CMD_ARG1_GPM_METRIC_NVLINK_DATA_RX_BW_PER_LINK 0x00000014
#define NV_MSGBOX_CMD_ARG1_GPM_METRIC_NVDEC_UTIL_PER_INSTANCE 0x00000015
#define NV_MSGBOX_CMD_ARG1_GPM_METRIC_NVJPG_UTIL_PER_INSTANCE 0x00000016
#define NV_MSGBOX_CMD_ARG1_GPM_METRIC_INTEGER_UTILIZATION 0x00000017
#define NV_MSGBOX_CMD_ARG1_GPM_METRIC_DMMA_UTILIZATION 0x00000018
#define NV_MSGBOX_CMD_ARG1_GPM_METRIC_HMMA_UTILIZATION 0x00000019
#define NV_MSGBOX_CMD_ARG1_GPM_METRIC_IMMA_UTILIZATION 0x0000001A
#define NV_MSGBOX_CMD_ARG1_DYN_SYS_INFO_DRIVER_VERSION_V1 0x00000000
@@ -440,8 +457,11 @@
(NV_MSGBOX_CMD_ARG2_GET_POWER_HINT_INFO_PROFILES_PAGE_3 + 1)
// Arg2 for _GPU_PERFORMANCE_MONITORING
#define NV_MSGBOX_CMD_ARG2_GPM_PARTITION 23:16
#define NV_MSGBOX_CMD_ARG2_GPM_PARTITION_AGGREGATE 0x000000FF
#define NV_MSGBOX_CMD_ARG2_GPM_PARTITION_INDEX 21:16
#define NV_MSGBOX_CMD_ARG2_GPM_CI_METRICS_REQUESTED 23:23
#define NV_MSGBOX_CMD_ARG2_GPM_CI_METRICS_REQUESTED_YES 0x00000001
#define NV_MSGBOX_CMD_ARG2_GPM_CI_METRICS_REQUESTED_NO 0x00000000
#define NV_MSGBOX_CMD_ARG2_GPM_MULTIPLIER 23:16
#define NV_MSGBOX_CMD_ARG2_GPM_MULTIPLIER_1X 0x00000001
@@ -816,6 +836,12 @@
#define NV_MSGBOX_DATA_CAP_4_SET_DEVICE_DISABLE 7:7
#define NV_MSGBOX_DATA_CAP_4_SET_DEVICE_DISABLE_NOT_AVAILABLE 0x00000000
#define NV_MSGBOX_DATA_CAP_4_SET_DEVICE_DISABLE_AVAILABLE 0x00000001
#define NV_MSGBOX_DATA_CAP_4_SET_ECC_MODE 8:8
#define NV_MSGBOX_DATA_CAP_4_SET_ECC_MODE_NOT_AVAILABLE 0x00000000
#define NV_MSGBOX_DATA_CAP_4_SET_ECC_MODE_AVAILABLE 0x00000001
#define NV_MSGBOX_DATA_CAP_4_SET_MIG_MODE 10:10
#define NV_MSGBOX_DATA_CAP_4_SET_MIG_MODE_NOT_AVAILABLE 0x00000000
#define NV_MSGBOX_DATA_CAP_4_SET_MIG_MODE_AVAILABLE 0x00000001
#define NV_MSGBOX_DATA_CAP_4_FAN_CURVE_POINTS_GET_SET 11:11
#define NV_MSGBOX_DATA_CAP_4_FAN_CURVE_POINTS_GET_SET_NOT_AVAILABLE 0x00000000
#define NV_MSGBOX_DATA_CAP_4_FAN_CURVE_POINTS_GET_SET_AVAILABLE 0x00000001
@@ -828,6 +854,9 @@
#define NV_MSGBOX_DATA_CAP_4_GPU_PERFORMANCE_MONITORING 24:24
#define NV_MSGBOX_DATA_CAP_4_GPU_PERFORMANCE_MONITORING_NOT_AVAILABLE 0x00000000
#define NV_MSGBOX_DATA_CAP_4_GPU_PERFORMANCE_MONITORING_AVAILABLE 0x00000001
#define NV_MSGBOX_DATA_CAP_4_CONFIGURE_PROGRAMMABLE_EDPP 30:30
#define NV_MSGBOX_DATA_CAP_4_CONFIGURE_PROGRAMMABLE_EDPP_NOT_AVAILABLE 0x00000000
#define NV_MSGBOX_DATA_CAP_4_CONFIGURE_PROGRAMMABLE_EDPP_AVAILABLE 0x00000001
/* ECC counters */
#define NV_MSGBOX_DATA_ECC_CNT_16BIT_DBE 31:16
@@ -1145,6 +1174,20 @@
#define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_2_REPLAY_ROLLOVER_COUNT 15:0
#define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_2_NAKS_RCVD_COUNT 31:16
/*
* Input for NV_MSGBOX_CMD_OPCODE_GPU_PERFORMANCE_MONITORING. Value is valid
* only if Arg2 != GPM_PARTITION_AGGREGATE and Arg2.Bit7 == 1
*/
#define NV_MSGBOX_DATA_GPM_COMPUTE_INSTANCE_INDEX 15:8
/*
* The following three fields correspond to the data which is interpreted
* differently depending on GPM Metric specified in Arg1.
*/
#define NV_MSGBOX_DATA_GPM_NVLINK_INDEX 7:0
#define NV_MSGBOX_DATA_GPM_NVDEC_INSTANCE 7:0
#define NV_MSGBOX_DATA_GPM_NVJPG_INSTANCE 7:0
/* MSGBOX Extended Data Register */
#define NV_MSGBOX_EXT_DATA_REG 31:0
@@ -1265,16 +1308,22 @@
/* Event types */
typedef enum
{
NV_MSGBOX_EVENT_TYPE_SERVER_RESTART = 0,
NV_MSGBOX_EVENT_TYPE_SERVER_RESTART_COLD = 0,
NV_MSGBOX_EVENT_TYPE_GPU_RESET_REQUIRED,
NV_MSGBOX_EVENT_TYPE_DRIVER_ERROR_MESSAGE,
NV_MSGBOX_EVENT_TYPE_DRIVER_ERROR_MESSAGE_OLDEST,
NV_MSGBOX_EVENT_TYPE_TGP_LIMIT_SET_SUCCESS,
NV_MSGBOX_EVENT_TYPE_CLOCK_LIMIT_SET_SUCCESS,
NV_MSGBOX_EVENT_TYPE_ECC_TOGGLE_SUCCESS,
NV_MSGBOX_EVENT_TYPE_MIG_TOGGLE_SUCCESS,
NV_MSGBOX_EVENT_TYPE_SERVER_RESTART_WARM,
NV_MSGBOX_EVENT_TYPE_DRIVER_ERROR_MESSAGE_NEW,
NV_MSGBOX_NUM_EVENTS, /* insert new event types before this line */
} NvMsgboxEventType;
/* Legacy event names for compatipility */
#define NV_MSGBOX_EVENT_TYPE_SERVER_RESTART NV_MSGBOX_EVENT_TYPE_SERVER_RESTART_COLD
#define NV_MSGBOX_EVENT_TYPE_DRIVER_ERROR_MESSAGE NV_MSGBOX_EVENT_TYPE_DRIVER_ERROR_MESSAGE_OLDEST
/* Bit mask of all defined events */
#define NV_MSGBOX_EVENT_TYPE__ALL (NVBIT(NV_MSGBOX_NUM_EVENTS) - 1)
@@ -2012,6 +2061,34 @@ typedef struct
// new param starting from here.
} NV_MSGBOX_POWER_HINT_PARAMS;
/*!
* This param is used for NV_MSGBOX_CMD_ARG1_ASYNC_REQUEST_CONFIGURE_PROGRAMMABLE_EDPP
*/
typedef struct
{
/*!
* [out] Power Hint in mW
*/
NvU32 data;
} NV_MSGBOX_PROGRAMMABLE_EDPP_PARAMS;
#define NV_MSGBOX_PROGRAMMABLE_EDPP_PARAMS_DATA 31:0
#define NV_MSGBOX_PROGRAMMABLE_EDPP_PARAMS_DATA_OPERATION 1:0
#define NV_MSGBOX_PROGRAMMABLE_EDPP_PARAMS_DATA_OPERATION_GET 0x0
#define NV_MSGBOX_PROGRAMMABLE_EDPP_PARAMS_DATA_OPERATION_SET 0x1
#define NV_MSGBOX_PROGRAMMABLE_EDPP_PARAMS_DATA_OPERATION_CLEAR 0x2
#define NV_MSGBOX_PROGRAMMABLE_EDPP_PARAMS_DATA_MODE 3:2
#define NV_MSGBOX_PROGRAMMABLE_EDPP_PARAMS_DATA_MODE_PERSISTENT 0x0
#define NV_MSGBOX_PROGRAMMABLE_EDPP_PARAMS_DATA_MODE_ONESHOT 0x1
#define NV_MSGBOX_PROGRAMMABLE_EDPP_PARAMS_DATA_LIMIT_CURRENT 10:4
#define NV_MSGBOX_PROGRAMMABLE_EDPP_PARAMS_DATA_LIMIT_RATED 17:11
#define NV_MSGBOX_PROGRAMMABLE_EDPP_PARAMS_DATA_LIMIT_MAXIMUM 24:18
#define NV_MSGBOX_PROGRAMMABLE_EDPP_PARAMS_DATA_LIMIT_MINIMUM 31:25
#define NV_MSGBOX_PROGRAMMABLE_EDPP_PARAMS_LIMIT_NOT_SET 0x7F
/*!
* @brief Union of all possible parameter struct. Used to determine the maximum
* amount of space parameter blocks can take.
@@ -2031,6 +2108,7 @@ typedef union {
NV_MSGBOX_CLOCK_LIMIT_GET_PARAMS clockLimitGet;
NV_MSGBOX_THERMAL_FAN_V3_FAN_CURVE_POINTS_PARAMS fanCurvePointsV3;
NV_MSGBOX_POWER_HINT_PARAMS powerHintParams;
NV_MSGBOX_PROGRAMMABLE_EDPP_PARAMS programmableEdppParams;
} NV_MSGBOX_ASYNC_REQ_PARAMS_UNION;
#endif // !NV_MSGBOX_NO_PARAM_STRUCTS
@@ -2446,15 +2524,15 @@ typedef union {
( \
NV_MSGBOX_CMD(_GPU_PERFORMANCE_MONITORING, 0, 0) | \
DRF_DEF(_MSGBOX, _CMD, _ARG1_GPM_ACTION, type) | \
DRF_DEF(_MSGBOX, _CMD, _ARG1_GPM_METRIC, metric) | \
DRF_DEF(_MSGBOX, _CMD, _ARG2_GPM_PARTITION, partition) \
DRF_NUM(_MSGBOX, _CMD, _ARG1_GPM_METRIC, metric) | \
DRF_NUM(_MSGBOX, _CMD, _ARG2_GPM_PARTITION, partition) \
)
#define NV_MSGBOX_CMD_GPM_SET_INTERVAL(interval) \
#define NV_MSGBOX_CMD_GPM_SET_MULTIPLIER(multiplier) \
( \
NV_MSGBOX_CMD(_GPU_PERFORMANCE_MONITORING, 0, 0) | \
DRF_DEF(_MSGBOX, _CMD, _ARG1_GPM_ACTION, _SET_INTERVAL) | \
DRF_DEF(_MSGBOX, _CMD, _ARG1_GPM_INTERVAL, (interval)) \
DRF_DEF(_MSGBOX, _CMD, _ARG1_GPM_ACTION, _SET_MULTIPLIER) | \
DRF_NUM(_MSGBOX, _CMD, _ARG2_GPM_MULTIPLIER, (multiplier)) \
)
#define NV_MSGBOX_GET_CMD_OPCODE(cmd) DRF_VAL(_MSGBOX, _CMD, _OPCODE, (cmd))

7
src/nvidia/arch/nvalloc/common/inc/rmlsfm.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2011-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2011-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -484,6 +484,11 @@ typedef struct _def_acr_reserved_dmem
NvU32 reservedDmem[(LSF_BOOTSTRAP_OWNER_RESERVED_DMEM_SIZE/4)]; // Always first..
} ACR_RESERVED_DMEM, *PACR_RESERVED_DMEM;
typedef struct _def_booter_reserved_dmem
{
NvU32 reservedDmem[(LSF_BOOTSTRAP_OWNER_RESERVED_DMEM_SIZE/4)]; // Always first..
} BOOTER_RESERVED_DMEM;
#define NV_FLCN_ACR_DESC_FLAGS_SIG_VERIF 0:0
#define NV_FLCN_ACR_DESC_FLAGS_SIG_VERIF_DISABLE 0
#define NV_FLCN_ACR_DESC_FLAGS_SIG_VERIF_ENABLE 1