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This commit is contained in:
Andy Ritger
2022-11-10 08:39:33 -08:00
parent 7c345b838b
commit 758b4ee818
1323 changed files with 262135 additions and 60754 deletions
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36
src/nvidia/inc/kernel/gpu/ce/kernel_ce_private.h
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@@ -33,14 +33,19 @@
/*!
* @brief Obtain relative CE index.
*
* @param localEngType NV2080_ENGINE_TYPE_ for this CE, or partition-local engine type.
* @param rmEngineType RM_ENGINE_TYPE_ for this CE, or partition-local engine type.
* @param ceIdx CE index in 0..GPU_MAX_CES-1
*
* @return NV_OK if the conversion is successful.
*/
static NV_INLINE
NV_STATUS ceIndexFromType(OBJGPU *pGpu, NvHandle hClient, NvU32 localEngType, NvU32 *ceIdx)
NV_STATUS ceIndexFromType(OBJGPU *pGpu, NvHandle hClient, RM_ENGINE_TYPE rmEngineType, NvU32 *ceIdx)
{
NV_STATUS status = NV_OK;
RM_ENGINE_TYPE localRmEngType = rmEngineType;
*ceIdx = GPU_MAX_CES;
//
// If MIG is enabled, client passes a logical engineId w.r.t its own partition
// we need to convert this logical Id to a physical engine Id as we use it
@@ -51,29 +56,24 @@ NV_STATUS ceIndexFromType(OBJGPU *pGpu, NvHandle hClient, NvU32 localEngType, Nv
KernelMIGManager *pKernelMIGManager = GPU_GET_KERNEL_MIG_MANAGER(pGpu);
MIG_INSTANCE_REF ref;
NV_CHECK_OK_OR_RETURN(
LEVEL_ERROR,
kmigmgrGetInstanceRefFromClient(pGpu, pKernelMIGManager,
hClient, &ref));
status = kmigmgrGetInstanceRefFromClient(pGpu, pKernelMIGManager, hClient, &ref);
NV_CHECK_OK_OR_RETURN(
LEVEL_ERROR,
kmigmgrGetLocalToGlobalEngineType(pGpu, pKernelMIGManager, ref,
localEngType,
ceIdx));
}
else
{
*ceIdx = localEngType;
if (status != NV_OK)
return status;
status = kmigmgrGetLocalToGlobalEngineType(pGpu, pKernelMIGManager, ref, rmEngineType, &localRmEngType);
if (status != NV_OK)
return status;
}
if (!NV2080_ENGINE_TYPE_IS_COPY(*ceIdx))
if (!RM_ENGINE_TYPE_IS_COPY(localRmEngType))
{
return NV_ERR_INVALID_ARGUMENT;
}
*ceIdx = NV2080_ENGINE_TYPE_COPY_IDX(*ceIdx);
return NV_OK;
*ceIdx = RM_ENGINE_TYPE_COPY_IDX(localRmEngType);
return status;
}
#endif // KERNEL_CE_PRIVATE_H

16
src/nvidia/inc/kernel/gpu/disp/kern_disp_type.h
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@@ -29,6 +29,7 @@
* Defines display type enums that can be used in the KernelDisplay object.
*
******************************************************************************/
#define NV_PDISP_CHN_NUM_ANY 0x7F
typedef enum
{
@@ -39,6 +40,7 @@ typedef enum
dispChnClass_Ovly,
dispChnClass_Winim,
dispChnClass_Win,
dispChnClass_Any,
dispChnClass_Supported
} DISPCHNCLASS;
@@ -49,4 +51,18 @@ enum DISPLAY_ICC_BW_CLIENT
NUM_DISPLAY_ICC_BW_CLIENTS
};
typedef enum
{
dispMemoryTarget_physNVM,
dispMemoryTarget_physPCI,
dispMemoryTarget_physPCICoherent
} DISPMEMORYTARGET;
typedef struct
{
NvU64 addr;
DISPMEMORYTARGET memTarget;
NvBool valid;
} VGAADDRDESC;
#endif // #ifndef KERN_DISP_TYPE_H

243
src/nvidia/inc/kernel/gpu/external_device/dac_p2060.h Normal file
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@@ -0,0 +1,243 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef DAC_P2060_H
#define DAC_P2060_H
/* ------------------------ Includes --------------------------------------- */
#include "gpu/external_device/external_device.h" // DACEXTERNALDEVICE
#include "gpu/external_device/gsync.h" // GSYNCVIDEOMODE, GSYNCSYNCPOLARITY
#include "gpu/disp/kern_disp_max.h"
/* ------------------------ Macros & Defines ------------------------------- */
// Display synchronization interface. (Framelock, Genlock, Swapready, etc)
#define NV_P2060_MAX_ASSOCIATED_GPUS 4
#define NV_P2060_MAX_IFACES_PER_GSYNC 4
#define NV_P2060_MAX_GPUS_PER_IFACE 1
#define NV_P2060_MAX_HEADS_PER_GPU 4
#define NV_P2060_MAX_MOSAIC_SLAVES 3
#define NV_P2060_MAX_MOSAIC_GROUPS 2
#define NV_P2060_IFACE_ONE 0
#define NV_P2060_IFACE_TWO 1
#define NV_P2060_IFACE_THREE 2
#define NV_P2060_IFACE_FOUR 3
#define NV_P2060_SYNC_SKEW_MAX_UNITS_FULL_SUPPORT 65535 // For FPGA with Rev >= 3. Refer Bug 1058215
#define NV_P2060_SYNC_SKEW_MAX_UNITS_LIMITED_SUPPORT 1 // For FPGA with Rev < 3.
#define NV_P2060_SYNC_SKEW_RESOLUTION 977
#define NV_P2060_START_DELAY_MAX_UNITS 65535
#define NV_P2060_START_DELAY_RESOLUTION 7800
#define NV_P2060_SYNC_INTERVAL_MAX_UNITS 7
#define NV_P2060_WATCHDOG_COUNT_DOWN_VALUE 60 // 1 minute, assuming watchdog time interval is 1 second.
#define NV_P2060_FRAME_COUNT_TIMER_INTERVAL 5000000000LL // 5 sec
#define NV_P2060_MAX_GPU_FRAME_COUNT 65535
#define NV_P2060_MAX_GSYNC_FRAME_COUNT 16777215 // 2^24.Gsync frame count is a 24 bit register
/* ------------------------ Types definitions ------------------------------ */
typedef struct EXTDEV_I2C_HANDLES
{
//Internal handles per GPU
NvHandle hClient;
NvHandle hDevice;
NvHandle hSubdevice;
NvHandle hSubscription;
NvU32 gpuId;
} EXTDEV_I2C_HANDLES;
typedef struct
{
NvU8 lossRegStatus;
NvU8 gainRegStatus;
NvU8 miscRegStatus;
DACEXTERNALDEVICE *pExtDevice;
}EXTDEV_INTR_DATA;
// note: NV_P2060_MAX_ASSOCIATED_GPUS = NV_P2060_MAX_IFACES_PER_GSYNC * NV_P2060_MAX_GPUS_PER_IFACE
struct DACP2060EXTERNALDEVICE
{
//Must be at top of struct
DACEXTERNALDEVICE ExternalDevice;
// Stuff for supporting the DisplaySync interface
NvU32 AssociatedCRTCs; // bit mask of crtcs ids associated.
GSYNCVIDEOMODE VideoMode;
GSYNCSYNCPOLARITY SyncPolarity;
NvU32 SyncStartDelay;
NvU32 SyncSkew;
NvU32 NSync;
NvU32 HouseSignal;
NvU32 UseHouseSync;
NvU32 Master;
NvU32 Slaves;
NvU32 EmitTestSignal;
NvU32 InterlaceMode;
NvU32 RefreshRate; // desired frame rate (units of .01Hz)
NvU32 DebugMask;
NvU32 gpuAttachMask;
NvU32 id;
NvU32 watchdogCountDownValue;
NvBool isNonFramelockInterruptEnabled;
NvU32 interruptEnabledInterface;
NvU32 tSwapRdyHi; /* Value of SWAP_LOCKOUT_START in accordance to the
* time in microseconds for which swap Rdy
* lines will remain high.(Provided via a regkey)
*/
NvU32 tSwapRdyHiLsrMinTime; /* Value of LSR_MIN_TIME in accordance to the time (in us)
* swap ready line will remain high.(Provided via a regkey)
*/
struct {
NvU32 currentFrameCount; // gpu frame count register value for current user query
NvU32 previousFrameCount; // gpu frame count register value for previous user query
NvU32 totalFrameCount; // equals to cached gsync frame count = gpu frame count + difference.
NvU32 numberOfRollbacks; // Max value of N where (Gsync Frame Count > N * Gpu frame count)
NvU32 frameTime; // Time to render one frame.
NvU64 lastFrameCounterQueryTime;
NvS32 initialDifference; // Difference between Gsync frame count and (numberOfRollbacks * Gpu framecount)
NvU32 iface;
NvU32 head;
NvU32 vActive; // Vertical Resolution for which system is framelocked.
NvBool bReCheck; // Enabled to verify initialDifference 1 sec after initialization.
NvBool enableFrmCmpMatchIntSlave; // Enable the frmCmpMatchInt for slave, if this bit is set.
NvBool isFrmCmpMatchIntMasterEnabled; // To enable frmCmpMatchInt for master when gsync framecount exceeds (2^24 - 1000)
} FrameCountData;
struct {
NvU32 Status1;
NvU64 lastSyncCheckTime;
NvU64 lastStereoToggleTime;
} Snapshot[NV_P2060_MAX_IFACES_PER_GSYNC];
// These arrays refer to the state of heads with respect to their sync
// source, and their usage can be kind of confusing. This table
// describes how they should be set/used:
//
// Head[i] --> Is Head[i] the frame lock master, or a slave
// SyncSrc --> Where is the sync timing actually coming from (the
// master head or a house sync signal)
//
// Head[i] SyncSrc PM[i] PS[i] PSLS[i]
// -----------------------------------------+---------------------
// Master Head[i] 1 0 0
// Master House 1 1 0
// Slave Head[!i] 0 0 1
// Slave House 0 1 0
// Slave External 0 1 0
// Neither X 0 0 0
//
// (the last row represents the case where the head has not been
// requested to lock).
struct {
struct {
NvU32 Master [OBJ_MAX_HEADS];
NvU32 Slaved [OBJ_MAX_HEADS];
NvU32 LocalSlave[OBJ_MAX_HEADS];
} Sync;
struct {
NvU32 gpuId;
NvBool connected;
} GpuInfo;
struct {
NvU32 OrigLsrMinTime[OBJ_MAX_HEADS];
NvBool saved;
} DsiFliplock;
struct {
NvU32 direction;
NvU32 mode;
NvBool saved;
} RasterSyncGpio;
NvBool SwapReadyRequested;
NvBool skipSwapBarrierWar;
NvU32 lastEventNotified;
NvU32 gainedSync; // Set when we gain sync after enabling framelock.
} Iface[NV_P2060_MAX_IFACES_PER_GSYNC];
EXTDEV_I2C_HANDLES i2cHandles[NV_P2060_MAX_IFACES_PER_GSYNC];
struct {
NvU32 gpuTimingSource;
NvU32 gpuTimingSlaves[NV_P2060_MAX_MOSAIC_SLAVES];
NvU32 slaveGpuCount;
NvBool enabledMosaic;
} MosaicGroup[NV_P2060_MAX_MOSAIC_GROUPS];
};
PDACEXTERNALDEVICE extdevConstruct_P2060 (OBJGPU *, PDACEXTERNALDEVICE);
NvBool gsyncAttachExternalDevice_P2060 (OBJGPU *, PDACEXTERNALDEVICE*);
void extdevDestroy_P2060 (OBJGPU *, PDACEXTERNALDEVICE);
NvBool extdevGetDevice_P2060 (OBJGPU *, PDACEXTERNALDEVICE);
NvBool extdevInit_P2060 (OBJGPU *, PDACEXTERNALDEVICE);
void extdevDestroy_P2060 (OBJGPU *, PDACEXTERNALDEVICE);
void extdevService_P2060 (OBJGPU *, PDACEXTERNALDEVICE, NvU8, NvU8, NvU8, NvBool);
NV_STATUS extdevWatchdog_P2060 (OBJGPU *, OBJTMR *, PDACEXTERNALDEVICE); // OBJTMR routine signature (TIMERPROC).
NvBool extdevSaveI2cHandles_P2060 (OBJGPU *, DACEXTERNALDEVICE *);
NV_STATUS gsyncFindGpuHandleLocation (DACEXTERNALDEVICE *, NvU32 , NvU32 *);
// P2060 hal ifaces
NvBool gsyncGpuCanBeMaster_P2060 (OBJGPU *, PDACEXTERNALDEVICE);
NV_STATUS gsyncGetSyncPolarity_P2060 (OBJGPU *, PDACEXTERNALDEVICE, GSYNCSYNCPOLARITY *);
NV_STATUS gsyncSetSyncPolarity_P2060 (OBJGPU *, PDACEXTERNALDEVICE, GSYNCSYNCPOLARITY);
NV_STATUS gsyncGetVideoMode_P2060 (OBJGPU *, PDACEXTERNALDEVICE, GSYNCVIDEOMODE *);
NV_STATUS gsyncSetVideoMode_P2060 (OBJGPU *, PDACEXTERNALDEVICE, GSYNCVIDEOMODE);
NV_STATUS gsyncGetNSync_P2060 (OBJGPU *, PDACEXTERNALDEVICE, NvU32 *);
NV_STATUS gsyncSetNSync_P2060 (OBJGPU *, PDACEXTERNALDEVICE, NvU32);
NV_STATUS gsyncGetSyncSkew_P2060 (OBJGPU *, PDACEXTERNALDEVICE, NvU32 *);
NV_STATUS gsyncSetSyncSkew_P2060 (OBJGPU *, PDACEXTERNALDEVICE, NvU32);
NV_STATUS gsyncGetUseHouse_P2060 (OBJGPU *, PDACEXTERNALDEVICE, NvU32 *);
NV_STATUS gsyncSetUseHouse_P2060 (OBJGPU *, PDACEXTERNALDEVICE, NvU32);
NV_STATUS gsyncGetSyncStartDelay_P2060 (OBJGPU *, PDACEXTERNALDEVICE, NvU32 *);
NV_STATUS gsyncSetSyncStartDelay_P2060 (OBJGPU *, PDACEXTERNALDEVICE, NvU32);
NV_STATUS gsyncRefSignal_P2060 (OBJGPU *, PDACEXTERNALDEVICE, REFTYPE, GSYNCSYNCSIGNAL, NvBool bRate, NvU32 *);
NV_STATUS gsyncRefMaster_P2060 (OBJGPU *, PDACEXTERNALDEVICE, REFTYPE, NvU32 *DisplayMask, NvU32 *Refresh, NvBool retainMaster, NvBool skipSwapBarrierWar);
NV_STATUS gsyncRefSlaves_P2060 (OBJGPU *, PDACEXTERNALDEVICE, REFTYPE, NvU32 *DisplayMask_s, NvU32 *Refresh);
NV_STATUS gsyncGetCplStatus_P2060 (OBJGPU *, PDACEXTERNALDEVICE, GSYNCSTATUS, NvU32 *);
NV_STATUS gsyncGetEmitTestSignal_P2060 (OBJGPU *, PDACEXTERNALDEVICE, NvU32 *);
NV_STATUS gsyncSetEmitTestSignal_P2060 (OBJGPU *, PDACEXTERNALDEVICE, NvU32);
NV_STATUS gsyncGetInterlaceMode_P2060 (OBJGPU *, PDACEXTERNALDEVICE, NvU32 *);
NV_STATUS gsyncSetInterlaceMode_P2060 (OBJGPU *, PDACEXTERNALDEVICE, NvU32);
NV_STATUS gsyncRefSwapBarrier_P2060 (OBJGPU *, PDACEXTERNALDEVICE, REFTYPE, NvBool *);
NV_STATUS gsyncGetWatchdog_P2060 (OBJGPU *, PDACEXTERNALDEVICE, NvU32 *);
NV_STATUS gsyncSetWatchdog_P2060 (OBJGPU *, PDACEXTERNALDEVICE, NvU32);
NV_STATUS gsyncGetRevision_P2060 (OBJGPU *, PDACEXTERNALDEVICE, GSYNCCAPSPARAMS *);
NV_STATUS gsyncOptimizeTimingParameters_P2060(OBJGPU *, GSYNCTIMINGPARAMS *);
NV_STATUS gsyncGetStereoLockMode_P2060 (OBJGPU *, PDACEXTERNALDEVICE, NvU32 *);
NV_STATUS gsyncSetStereoLockMode_P2060 (OBJGPU *, PDACEXTERNALDEVICE, NvU32);
NV_STATUS gsyncSetMosaic_P2060 (OBJGPU *, PDACEXTERNALDEVICE, NV30F1_CTRL_GSYNC_SET_LOCAL_SYNC_PARAMS *);
NV_STATUS gsyncConfigFlashGsync_P2060 (OBJGPU *, PDACEXTERNALDEVICE, NvU32);
#endif

35
src/nvidia/inc/kernel/gpu/external_device/dac_p2061.h Normal file
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@@ -0,0 +1,35 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef DAC_P2061_H
#define DAC_P2061_H
/* ------------------------ Macros & Defines ------------------------------- */
// P2061 uses P2060's object.
// P2061 hal ifaces
NV_STATUS gsyncGetHouseSyncMode_P2061 (OBJGPU *, PDACEXTERNALDEVICE, NvU8*);
NV_STATUS gsyncSetHouseSyncMode_P2061 (OBJGPU *, PDACEXTERNALDEVICE, NvU8);
NV_STATUS gsyncGetCplStatus_P2061 (OBJGPU *, PDACEXTERNALDEVICE, GSYNCSTATUS, NvU32 *);
#endif // DAC_P2061_H

132
src/nvidia/inc/kernel/gpu/external_device/external_device.h Normal file
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@@ -0,0 +1,132 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef EXTDEV_H_
#define EXTDEV_H_
/* ------------------------ Includes --------------------------------------- */
#include "Nvcm.h"
#include "sweng/dispsw.h"
/* ------------------------ Types definitions ------------------------------ */
typedef struct DACEXTERNALDEVICE DACEXTERNALDEVICE, *PDACEXTERNALDEVICE;
typedef struct DACEXTERNALDEVICEIFACE DACEXTERNALDEVICEIFACE, *PDACEXTERNALDEVICEIFACE;
typedef struct DACP2060EXTERNALDEVICE DACP2060EXTERNALDEVICE, *PDACP2060EXTERNALDEVICE;
typedef enum _DAC_EXTERNAL_DEVICES
{
DAC_EXTERNAL_DEVICE_NONE = 0,
DAC_EXTERNAL_DEVICE_P2060 = 0x2060, // NV30F1_CTRL_GSYNC_GET_CAPS_BOARD_ID_P2060
DAC_EXTERNAL_DEVICE_P2061 = 0x2061, // NV30F1_CTRL_GSYNC_GET_CAPS_BOARD_ID_P2060
} DAC_EXTERNAL_DEVICES;
typedef enum _DAC_EXTERNAL_DEVICE_FPGA_REVS
{
DAC_EXTERNAL_DEVICE_REV_0,
DAC_EXTERNAL_DEVICE_REV_1,
DAC_EXTERNAL_DEVICE_REV_2,
DAC_EXTERNAL_DEVICE_REV_3,
DAC_EXTERNAL_DEVICE_REV_4,
DAC_EXTERNAL_DEVICE_REV_5,
DAC_EXTERNAL_DEVICE_REV_6,
DAC_EXTERNAL_DEVICE_REV_7,
DAC_EXTERNAL_DEVICE_REV_MAX,
DAC_EXTERNAL_DEVICE_REV_NONE,
} DAC_EXTERNAL_DEVICE_REVS;
typedef enum _DAC_EXTDEV_ACTIONS
{
GET,
SET,
} DAC_EXTDEV_ACTIONS;
//
// Not super-sure how "ExternalDevice" fits in with the model vs. say an
// external display encoder (tv, digital, DAC, etc). But perhaps those would
// instantiate one of these guys to become the "CommandChannel". As in an
// external display encoder would "know about" its associated ExternalDevice
// and use it to communicate... later... for now ExternalDevice is the base
// class for the extension boards.
//
struct DACEXTERNALDEVICEIFACE
{
NvBool (*GetDevice) (OBJGPU *, PDACEXTERNALDEVICE); // = 0 ( Pure virtual )
NvBool (*Init) (OBJGPU *, PDACEXTERNALDEVICE); // = 0 ( Pure virtual )
void (*Destroy) (OBJGPU *, PDACEXTERNALDEVICE);
NvBool (*Attach) (OBJGPU *, PDACEXTERNALDEVICE *);
NvBool (*Validate) (OBJGPU *, PDACEXTERNALDEVICE); // check if the config is valid
void (*SetMode) (OBJGPU *, PDACEXTERNALDEVICE, NvU32);
NvBool (*SetupVblankService)(OBJGPU *, PDACEXTERNALDEVICE, NvU32, NvBool);
void (*Service) (OBJGPU *, PDACEXTERNALDEVICE, NvU8, NvU8, NvU8, NvBool);
NV_STATUS (*Watchdog) (OBJGPU *, struct OBJTMR *, PDACEXTERNALDEVICE); // OBJTMR routine signature (TIMERPROC).
NvBool (*setI2cHandles)(OBJGPU *, DACEXTERNALDEVICE *);
};
struct DACEXTERNALDEVICE
{
DACEXTERNALDEVICEIFACE *pI;
NvU32 ReferenceCount;
NvU8 I2CAddr;
NvU32 I2CPort;
NvU32 MaxGpus;
NvU8 revId;
DAC_EXTERNAL_DEVICES deviceId;
DAC_EXTERNAL_DEVICE_REVS deviceRev; //device revision, also known as firmware major version
NvU8 deviceExRev; //device extended revision, also known as firmware minor version
struct {
NvBool Scheduled;
NvU32 TimeOut;
} WatchdogControl;
};
typedef PDACEXTERNALDEVICE (*pfextdevConstruct) (OBJGPU *, PDACEXTERNALDEVICE);
/* ------------------------ Macros & Defines ------------------------------- */
#define NV_P2060_MIN_REV 0x2
void extdevGetBoundHeadsAndDisplayIds(OBJGPU *, NvU32 *);
PDACEXTERNALDEVICE extdevConstruct_Base (OBJGPU *, PDACEXTERNALDEVICE);
void extdevDestroy_Base (OBJGPU *, PDACEXTERNALDEVICE);
NvBool extdevValidate_Default (OBJGPU *, PDACEXTERNALDEVICE);
void extdevInvalidate_Default(OBJGPU *, PDACEXTERNALDEVICE);
NV_STATUS i2c_extdeviceHelper(OBJGPU *, DACEXTERNALDEVICE *, NvU32, NvU8, NvU8 *,NvBool);
NV_STATUS writeregu008_extdevice(OBJGPU *, PDACEXTERNALDEVICE, NvU8, NvU8);
NV_STATUS writeregu008_extdeviceTargeted(OBJGPU *, PDACEXTERNALDEVICE, NvU8, NvU8);
NV_STATUS readregu008_extdevice(OBJGPU *, PDACEXTERNALDEVICE, NvU8, NvU8*);
NV_STATUS readregu008_extdeviceTargeted(OBJGPU *, PDACEXTERNALDEVICE, NvU8, NvU8*);
void extdevDestroy (OBJGPU *);
NV_STATUS extdevScheduleWatchdog(OBJGPU *, PDACEXTERNALDEVICE);
NV_STATUS extdevCancelWatchdog (OBJGPU *, PDACEXTERNALDEVICE);
NV_STATUS extdevServiceWatchdog (OBJGPU *, struct OBJTMR *, void *); // OBJTMR routine signature (TIMERPROC).
void extdevGsyncService(OBJGPU *, NvU8, NvU8, NvU8, NvBool);
#endif

3
src/nvidia/inc/kernel/gpu/external_device/gsync.h Normal file
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@@ -0,0 +1,3 @@
#include "g_gsync_nvoc.h"

3
src/nvidia/inc/kernel/gpu/external_device/gsync_api.h Normal file
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@@ -0,0 +1,3 @@
#include "g_gsync_api_nvoc.h"

107
src/nvidia/inc/kernel/gpu/gpu_acpi_data.h Normal file
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@@ -0,0 +1,107 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _GPU_ACPI_DATA_H_
#define _GPU_ACPI_DATA_H_
#include "ctrl/ctrl0073/ctrl0073system.h"
#include "nvctassert.h"
#include "acpigenfuncs.h"
#include "nvstatus.h"
#include "gpu/gpu_halspec.h"
#define MAX_DSM_SUPPORTED_FUNCS_RTN_LEN 8 // # bytes to store supported functions
typedef struct {
// supported function status and cache
NvU32 suppFuncStatus;
NvU8 suppFuncs[MAX_DSM_SUPPORTED_FUNCS_RTN_LEN];
NvU32 suppFuncsLen;
NvBool bArg3isInteger;
// callback status and cache
NvU32 callbackStatus;
NvU32 callback;
} ACPI_DSM_CACHE;
typedef struct {
ACPI_DSM_CACHE dsm[ACPI_DSM_FUNCTION_COUNT];
ACPI_DSM_FUNCTION dispStatusHotplugFunc;
ACPI_DSM_FUNCTION dispStatusConfigFunc;
ACPI_DSM_FUNCTION perfPostPowerStateFunc;
ACPI_DSM_FUNCTION stereo3dStateActiveFunc;
NvU32 dsmPlatCapsCache[ACPI_DSM_FUNCTION_COUNT];
NvU32 MDTLFeatureSupport;
// cache of generic func/subfunction remappings.
ACPI_DSM_FUNCTION dsmCurrentFunc[NV_ACPI_GENERIC_FUNC_COUNT];
NvU32 dsmCurrentSubFunc[NV_ACPI_GENERIC_FUNC_COUNT];
NvU32 dsmCurrentFuncSupport;
} ACPI_DATA;
typedef struct DOD_METHOD_DATA
{
NV_STATUS status;
NvU32 acpiIdListLen;
NvU32 acpiIdList[NV0073_CTRL_SYSTEM_ACPI_ID_MAP_MAX_DISPLAYS];
} DOD_METHOD_DATA;
typedef struct JT_METHOD_DATA
{
NV_STATUS status;
NvU16 jtRevId;
NvU32 jtCaps;
} JT_METHOD_DATA;
typedef struct MUX_METHOD_DATA_ELEMENT
{
NvU32 acpiId;
NvU32 mode;
NV_STATUS status;
} MUX_METHOD_DATA_ELEMENT;
typedef struct MUX_METHOD_DATA
{
NvU32 tableLen;
MUX_METHOD_DATA_ELEMENT acpiIdMuxModeTable[NV0073_CTRL_SYSTEM_ACPI_ID_MAP_MAX_DISPLAYS];
MUX_METHOD_DATA_ELEMENT acpiIdMuxPartTable[NV0073_CTRL_SYSTEM_ACPI_ID_MAP_MAX_DISPLAYS];
} MUX_METHOD_DATA;
typedef struct CAPS_METHOD_DATA
{
NV_STATUS status;
NvU32 optimusCaps;
} CAPS_METHOD_DATA;
typedef struct ACPI_METHOD_DATA
{
NvBool bValid;
DOD_METHOD_DATA dodMethodData;
JT_METHOD_DATA jtMethodData;
MUX_METHOD_DATA muxMethodData;
CAPS_METHOD_DATA capsMethodData;
} ACPI_METHOD_DATA;
#endif // _GPU_ACPI_DATA_H_

6
src/nvidia/inc/kernel/gpu/gpu_child_list.h
View File

@@ -94,7 +94,7 @@
GPU_CHILD_SINGLE_INST( OBJHSHUBMANAGER, GPU_GET_HSHUBMANAGER, 1, NV_FALSE, NV_FALSE, pHshMgr )
#endif
#if GPU_CHILD_MODULE(HSHUB)
GPU_CHILD_MULTI_INST ( OBJHSHUB, GPU_GET_HSHUB, GPU_MAX_HSHUBS, NV_FALSE, NV_FALSE, pHshub )
GPU_CHILD_MULTI_INST ( Hshub, GPU_GET_HSHUB, GPU_MAX_HSHUBS, NV_FALSE, NV_FALSE, pHshub )
#endif
#if GPU_CHILD_MODULE(SEQ)
GPU_CHILD_SINGLE_INST( OBJSEQ, GPU_GET_SEQ, 1, NV_FALSE, NV_TRUE, pSeq )
@@ -157,7 +157,7 @@
GPU_CHILD_SINGLE_INST( ClockManager, GPU_GET_CLK_MGR, 1, NV_FALSE, NV_FALSE, pClk )
#endif
#if GPU_CHILD_MODULE(FAN)
GPU_CHILD_SINGLE_INST( OBJFAN, GPU_GET_FAN, 1, NV_FALSE, NV_FALSE, pFan )
GPU_CHILD_SINGLE_INST( Fan, GPU_GET_FAN, 1, NV_FALSE, NV_FALSE, pFan )
#endif
#if GPU_CHILD_MODULE(PERF)
GPU_CHILD_SINGLE_INST( Perf, GPU_GET_PERF, 1, NV_FALSE, NV_FALSE, pPerf )
@@ -187,7 +187,7 @@
GPU_CHILD_SINGLE_INST( OBJVOLT, GPU_GET_VOLT, 1, NV_FALSE, NV_FALSE, pVolt )
#endif
#if GPU_CHILD_MODULE(I2C)
GPU_CHILD_SINGLE_INST( OBJI2C, GPU_GET_I2C, 1, NV_FALSE, NV_TRUE, pI2c )
GPU_CHILD_SINGLE_INST( I2c, GPU_GET_I2C, 1, NV_FALSE, NV_TRUE, pI2c )
#endif
#if GPU_CHILD_MODULE(SPI)
GPU_CHILD_SINGLE_INST( Spi, GPU_GET_SPI, 1, NV_FALSE, NV_TRUE, pSpi )

2
src/nvidia/inc/kernel/gpu/gpu_device_mapping.h
View File

@@ -48,7 +48,7 @@ typedef enum
SOC_DEV_MAPPING_DPAUX1, // Update NV_MAX_SOC_DPAUX_NUM_DEVICES if adding new DPAUX mappings
SOC_DEV_MAPPING_HDACODEC,
SOC_DEV_MAPPING_MIPICAL,
SOC_DEV_MAPPING_MAX // Keep this as last entry
SOC_DEV_MAPPING_MAX
} SOC_DEV_MAPPING;
#define GPU_MAX_DEVICE_MAPPINGS (60)

137
src/nvidia/inc/kernel/gpu/gpu_engine_type.h Normal file
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@@ -0,0 +1,137 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _GPU_ENGINE_TYPE_H_
#define _GPU_ENGINE_TYPE_H_
#include "class/cl2080.h"
#include "nvrangetypes.h"
#include "utils/nvbitvector.h"
typedef enum
{
RM_ENGINE_TYPE_NULL = (0x00000000),
RM_ENGINE_TYPE_GR0 = (0x00000001),
RM_ENGINE_TYPE_GR1 = (0x00000002),
RM_ENGINE_TYPE_GR2 = (0x00000003),
RM_ENGINE_TYPE_GR3 = (0x00000004),
RM_ENGINE_TYPE_GR4 = (0x00000005),
RM_ENGINE_TYPE_GR5 = (0x00000006),
RM_ENGINE_TYPE_GR6 = (0x00000007),
RM_ENGINE_TYPE_GR7 = (0x00000008),
RM_ENGINE_TYPE_COPY0 = (0x00000009),
RM_ENGINE_TYPE_COPY1 = (0x0000000a),
RM_ENGINE_TYPE_COPY2 = (0x0000000b),
RM_ENGINE_TYPE_COPY3 = (0x0000000c),
RM_ENGINE_TYPE_COPY4 = (0x0000000d),
RM_ENGINE_TYPE_COPY5 = (0x0000000e),
RM_ENGINE_TYPE_COPY6 = (0x0000000f),
RM_ENGINE_TYPE_COPY7 = (0x00000010),
RM_ENGINE_TYPE_COPY8 = (0x00000011),
RM_ENGINE_TYPE_COPY9 = (0x00000012),
RM_ENGINE_TYPE_NVDEC0 = (0x0000001d),
RM_ENGINE_TYPE_NVDEC1 = (0x0000001e),
RM_ENGINE_TYPE_NVDEC2 = (0x0000001f),
RM_ENGINE_TYPE_NVDEC3 = (0x00000020),
RM_ENGINE_TYPE_NVDEC4 = (0x00000021),
RM_ENGINE_TYPE_NVDEC5 = (0x00000022),
RM_ENGINE_TYPE_NVDEC6 = (0x00000023),
RM_ENGINE_TYPE_NVDEC7 = (0x00000024),
RM_ENGINE_TYPE_NVENC0 = (0x00000025),
RM_ENGINE_TYPE_NVENC1 = (0x00000026),
RM_ENGINE_TYPE_NVENC2 = (0x00000027),
RM_ENGINE_TYPE_VP = (0x00000028),
RM_ENGINE_TYPE_ME = (0x00000029),
RM_ENGINE_TYPE_PPP = (0x0000002a),
RM_ENGINE_TYPE_MPEG = (0x0000002b),
RM_ENGINE_TYPE_SW = (0x0000002c),
RM_ENGINE_TYPE_TSEC = (0x0000002d),
RM_ENGINE_TYPE_VIC = (0x0000002e),
RM_ENGINE_TYPE_MP = (0x0000002f),
RM_ENGINE_TYPE_SEC2 = (0x00000030),
RM_ENGINE_TYPE_HOST = (0x00000031),
RM_ENGINE_TYPE_DPU = (0x00000032),
RM_ENGINE_TYPE_PMU = (0x00000033),
RM_ENGINE_TYPE_FBFLCN = (0x00000034),
RM_ENGINE_TYPE_NVJPEG0 = (0x00000035),
RM_ENGINE_TYPE_NVJPEG1 = (0x00000036),
RM_ENGINE_TYPE_NVJPEG2 = (0x00000037),
RM_ENGINE_TYPE_NVJPEG3 = (0x00000038),
RM_ENGINE_TYPE_NVJPEG4 = (0x00000039),
RM_ENGINE_TYPE_NVJPEG5 = (0x0000003a),
RM_ENGINE_TYPE_NVJPEG6 = (0x0000003b),
RM_ENGINE_TYPE_NVJPEG7 = (0x0000003c),
RM_ENGINE_TYPE_OFA = (0x0000003d),
RM_ENGINE_TYPE_LAST = (0x0000003e),
} RM_ENGINE_TYPE;
//
// The duplicates in the RM_ENGINE_TYPE. Using define instead of putting them
// in the enum to make sure that each item in the enum has a unique number.
//
#define RM_ENGINE_TYPE_GRAPHICS RM_ENGINE_TYPE_GR0
#define RM_ENGINE_TYPE_BSP RM_ENGINE_TYPE_NVDEC0
#define RM_ENGINE_TYPE_MSENC RM_ENGINE_TYPE_NVENC0
#define RM_ENGINE_TYPE_CIPHER RM_ENGINE_TYPE_TSEC
#define RM_ENGINE_TYPE_NVJPG RM_ENGINE_TYPE_NVJPEG0
#define RM_ENGINE_TYPE_COPY_SIZE 10
#define RM_ENGINE_TYPE_NVENC_SIZE 3
#define RM_ENGINE_TYPE_NVJPEG_SIZE 8
#define RM_ENGINE_TYPE_NVDEC_SIZE 8
#define RM_ENGINE_TYPE_GR_SIZE 8
// Indexed engines
#define RM_ENGINE_TYPE_COPY(i) (RM_ENGINE_TYPE_COPY0+(i))
#define RM_ENGINE_TYPE_IS_COPY(i) (((i) >= RM_ENGINE_TYPE_COPY0) && ((i) < RM_ENGINE_TYPE_COPY(RM_ENGINE_TYPE_COPY_SIZE)))
#define RM_ENGINE_TYPE_COPY_IDX(i) ((i) - RM_ENGINE_TYPE_COPY0)
#define RM_ENGINE_TYPE_NVENC(i) (RM_ENGINE_TYPE_NVENC0+(i))
#define RM_ENGINE_TYPE_IS_NVENC(i) (((i) >= RM_ENGINE_TYPE_NVENC0) && ((i) < RM_ENGINE_TYPE_NVENC(RM_ENGINE_TYPE_NVENC_SIZE)))
#define RM_ENGINE_TYPE_NVENC_IDX(i) ((i) - RM_ENGINE_TYPE_NVENC0)
#define RM_ENGINE_TYPE_NVDEC(i) (RM_ENGINE_TYPE_NVDEC0+(i))
#define RM_ENGINE_TYPE_IS_NVDEC(i) (((i) >= RM_ENGINE_TYPE_NVDEC0) && ((i) < RM_ENGINE_TYPE_NVDEC(RM_ENGINE_TYPE_NVDEC_SIZE)))
#define RM_ENGINE_TYPE_NVDEC_IDX(i) ((i) - RM_ENGINE_TYPE_NVDEC0)
#define RM_ENGINE_TYPE_NVJPEG(i) (RM_ENGINE_TYPE_NVJPEG0+(i))
#define RM_ENGINE_TYPE_IS_NVJPEG(i) (((i) >= RM_ENGINE_TYPE_NVJPEG0) && ((i) < RM_ENGINE_TYPE_NVJPEG(RM_ENGINE_TYPE_NVJPEG_SIZE)))
#define RM_ENGINE_TYPE_NVJPEG_IDX(i) ((i) - RM_ENGINE_TYPE_NVJPEG0)
#define RM_ENGINE_TYPE_GR(i) (RM_ENGINE_TYPE_GR0 + (i))
#define RM_ENGINE_TYPE_IS_GR(i) (((i) >= RM_ENGINE_TYPE_GR0) && ((i) < RM_ENGINE_TYPE_GR(RM_ENGINE_TYPE_GR_SIZE)))
#define RM_ENGINE_TYPE_GR_IDX(i) ((i) - RM_ENGINE_TYPE_GR0)
#define RM_ENGINE_TYPE_IS_VALID(i) (((i) > (RM_ENGINE_TYPE_NULL)) && ((i) < (RM_ENGINE_TYPE_LAST)))
// Engine Range defines
#define RM_ENGINE_RANGE_GR() rangeMake(RM_ENGINE_TYPE_GR(0), RM_ENGINE_TYPE_GR(RM_ENGINE_TYPE_GR_SIZE - 1))
#define RM_ENGINE_RANGE_COPY() rangeMake(RM_ENGINE_TYPE_COPY(0), RM_ENGINE_TYPE_COPY(RM_ENGINE_TYPE_COPY_SIZE - 1))
#define RM_ENGINE_RANGE_NVDEC() rangeMake(RM_ENGINE_TYPE_NVDEC(0), RM_ENGINE_TYPE_NVDEC(RM_ENGINE_TYPE_NVDEC_SIZE - 1))
#define RM_ENGINE_RANGE_NVENC() rangeMake(RM_ENGINE_TYPE_NVENC(0), RM_ENGINE_TYPE_NVENC(RM_ENGINE_TYPE_NVENC_SIZE - 1))
#define RM_ENGINE_RANGE_NVJPEG() rangeMake(RM_ENGINE_TYPE_NVJPEG(0), RM_ENGINE_TYPE_NVJPEG(RM_ENGINE_TYPE_NVJPEG_SIZE - 1))
// Bit Vectors
MAKE_BITVECTOR(ENGTYPE_BIT_VECTOR, RM_ENGINE_TYPE_LAST);
#endif //_GPU_ENGINE_TYPE_H_

60
src/nvidia/inc/kernel/gpu/gpu_fabric_probe.h Normal file
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@@ -0,0 +1,60 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef GPU_FABRIC_PROBE_H
#define GPU_FABRIC_PROBE_H
#include "nvlink_inband_msg.h"
#define GPU_FABRIC_PROBE_SEC_TO_NS 1000000000ULL
#define GPU_FABRIC_PROBE_DEFAULT_DELAY 5 // 5 seconds
#define GPU_FABRIC_PROBE_DEFAULT_PROBE_SLOWDOWN_THRESHOLD 10
typedef struct GPU_FABRIC_PROBE_INFO GPU_FABRIC_PROBE_INFO;
NV_STATUS gpuFabricProbeStart(OBJGPU *pGpu,
GPU_FABRIC_PROBE_INFO **ppGpuFabricProbeInfo);
void gpuFabricProbeStop(GPU_FABRIC_PROBE_INFO *pGpuFabricProbeInfo);
void gpuFabricProbeSuspend(GPU_FABRIC_PROBE_INFO *pGpuFabricProbeInfo);
NV_STATUS gpuFabricProbeResume(GPU_FABRIC_PROBE_INFO *pGpuFabricProbeInfo);
NV_STATUS gpuFabricProbeGetGpuFabricHandle(GPU_FABRIC_PROBE_INFO *pInfo, NvU64 *pHandle);
NV_STATUS gpuFabricProbeGetGfId(GPU_FABRIC_PROBE_INFO *pInfo, NvU32 *pGfId);
NV_STATUS gpuFabricProbeGetfmCaps(GPU_FABRIC_PROBE_INFO *pInfo, NvU64 *pFmCaps);
NV_STATUS gpuFabricProbeGetClusterUuid(GPU_FABRIC_PROBE_INFO *pInfo, NvUuid *pClusterUuid);
NV_STATUS gpuFabricProbeGetFabricPartitionId(GPU_FABRIC_PROBE_INFO *pInfo, NvU16 *pFabricPartitionId);
NV_STATUS gpuFabricProbeGetGpaAddress(GPU_FABRIC_PROBE_INFO *pInfo, NvU64 *pGpaAddress);
NV_STATUS gpuFabricProbeGetGpaAddressRange(GPU_FABRIC_PROBE_INFO *pInfo, NvU64 *pGpaAddressRange);
NV_STATUS gpuFabricProbeGetFlaAddress(GPU_FABRIC_PROBE_INFO *pInfo, NvU64 *pFlaAddress);
NV_STATUS gpuFabricProbeGetFlaAddressRange(GPU_FABRIC_PROBE_INFO *pInfo, NvU64 *pFlaAddressRange);
NV_STATUS gpuFabricProbeGetNumProbeReqs(GPU_FABRIC_PROBE_INFO *pInfo, NvU64 *numProbes);
NvBool gpuFabricProbeIsReceived(GPU_FABRIC_PROBE_INFO *pGpuFabricProbeInfo);
NvBool gpuFabricProbeIsSuccess(GPU_FABRIC_PROBE_INFO *pGpuFabricProbeInfo);
NV_STATUS gpuFabricProbeGetFmStatus(GPU_FABRIC_PROBE_INFO *pGpuFabricProbeInfo);
NvBool gpuFabricProbeIsSupported(OBJGPU *pGpu);
#endif // GPU_FABRIC_PROBE_H

50
src/nvidia/inc/kernel/gpu/gpu_shared_data_map.h Normal file
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@@ -0,0 +1,50 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef GPU_SHARED_DATA_MAP_H
#define GPU_SHARED_DATA_MAP_H
#include "core/core.h"
#include "gpu/mem_mgr/mem_desc.h"
#include "class/cl00de.h"
// ****************************************************************************
// Type definitions
// ****************************************************************************
typedef struct GpuSharedDataMap {
MEMORY_DESCRIPTOR *pMemDesc;
NvP64 pMapBuffer;
NvP64 pMapBufferPriv;
NvU32 processId;
NV00DE_SHARED_DATA data;
} GpuSharedDataMap;
// Start data write, returns data struct to write into
NV00DE_SHARED_DATA * gpushareddataWriteStart(OBJGPU *pGpu);
// Finish data write, pushes data cached by above into mapped data
void gpushareddataWriteFinish(OBJGPU *pGpu);
#endif /* GPU_SHARED_DATA_MAP_H */

3
src/nvidia/inc/kernel/gpu/gpu_user_shared_data.h Normal file
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@@ -0,0 +1,3 @@
#include "g_gpu_user_shared_data_nvoc.h"

66
src/nvidia/inc/kernel/gpu/gr/kernel_graphics_context_buffers.h Normal file
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@@ -0,0 +1,66 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef KERNEL_GRAPHICS_CONTEXT_BUFFERS_H
#define KERNEL_GRAPHICS_CONTEXT_BUFFERS_H
#include "utils/nv_enum.h"
/*
* Global buffer types. These are shared between contexts
* each PF/VF context normally. A GraphicsContext may have
* a private allocation for security (VPR) or when
* graphics preemption is enabled.
*
* Not all buffer types are supported on every GPU.
*/
#define GR_GLOBALCTX_BUFFER_DEF(x) \
NV_ENUM_ENTRY(x, GR_GLOBALCTX_BUFFER_BUNDLE_CB, 0x00000000) \
NV_ENUM_ENTRY(x, GR_GLOBALCTX_BUFFER_PAGEPOOL, 0x00000001) \
NV_ENUM_ENTRY(x, GR_GLOBALCTX_BUFFER_ATTRIBUTE_CB, 0x00000002) \
NV_ENUM_ENTRY(x, GR_GLOBALCTX_BUFFER_RTV_CB, 0x00000003) \
NV_ENUM_ENTRY(x, GR_GLOBALCTX_BUFFER_GFXP_POOL, 0x00000004) \
NV_ENUM_ENTRY(x, GR_GLOBALCTX_BUFFER_GFXP_CTRL_BLK, 0x00000005) \
NV_ENUM_ENTRY(x, GR_GLOBALCTX_BUFFER_FECS_EVENT, 0x00000006) \
NV_ENUM_ENTRY(x, GR_GLOBALCTX_BUFFER_PRIV_ACCESS_MAP, 0x00000007) \
NV_ENUM_ENTRY(x, GR_GLOBALCTX_BUFFER_UNRESTRICTED_PRIV_ACCESS_MAP, 0x00000008) \
NV_ENUM_ENTRY(x, GR_GLOBAL_BUFFER_GLOBAL_PRIV_ACCESS_MAP, 0x00000009)
NV_ENUM_DEF(GR_GLOBALCTX_BUFFER, GR_GLOBALCTX_BUFFER_DEF)
#define GR_GLOBALCTX_BUFFER_COUNT NV_ENUM_SIZE(GR_GLOBALCTX_BUFFER)
#define GR_CTX_BUFFER_DEF(x) \
NV_ENUM_ENTRY(x, GR_CTX_BUFFER_MAIN, 0x00000000) \
NV_ENUM_ENTRY(x, GR_CTX_BUFFER_ZCULL, 0x00000001) \
NV_ENUM_ENTRY(x, GR_CTX_BUFFER_PM, 0x00000002) \
NV_ENUM_ENTRY(x, GR_CTX_BUFFER_PREEMPT, 0x00000003) \
NV_ENUM_ENTRY(x, GR_CTX_BUFFER_SPILL, 0x00000004) \
NV_ENUM_ENTRY(x, GR_CTX_BUFFER_BETA_CB, 0x00000005) \
NV_ENUM_ENTRY(x, GR_CTX_BUFFER_PAGEPOOL, 0x00000006) \
NV_ENUM_ENTRY(x, GR_CTX_BUFFER_RTV_CB, 0x00000007) \
NV_ENUM_ENTRY(x, GR_CTX_BUFFER_PATCH, 0x00000008)
NV_ENUM_DEF(GR_CTX_BUFFER, GR_CTX_BUFFER_DEF)
#endif // KERNEL_GRAPHICS_CONTEXT_BUFFERS_H

57
src/nvidia/inc/kernel/gpu/gr/kernel_sm_debugger_exception.h Normal file
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@@ -0,0 +1,57 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef KERNEL_SM_DEBUGGER_EXCEPTION_H
#define KERNEL_SM_DEBUGGER_EXCEPTION_H
#include "utils/nv_enum.h"
#include "nvctassert.h"
#include "nvmisc.h"
#include "ctrl/ctrl83de.h"
#define SMDBG_EXCEPTION_TYPE_DEF(x) \
NV_ENUM_ENTRY(x, SMDBG_EXCEPTION_TYPE_FATAL, 0) \
NV_ENUM_ENTRY(x, SMDBG_EXCEPTION_TYPE_TRAP, 1) \
NV_ENUM_ENTRY(x, SMDBG_EXCEPTION_TYPE_SINGLE_STEP, 2) \
NV_ENUM_ENTRY(x, SMDBG_EXCEPTION_TYPE_INT, 3) \
NV_ENUM_ENTRY(x, SMDBG_EXCEPTION_TYPE_CILP, 4) \
NV_ENUM_ENTRY(x, SMDBG_EXCEPTION_TYPE_PREEMPTION_STARTED, 5)
NV_ENUM_DEF(SMDBG_EXCEPTION_TYPE, SMDBG_EXCEPTION_TYPE_DEF);
ct_assert(NV_ENUM_IS_CONTIGUOUS(SMDBG_EXCEPTION_TYPE));
ct_assert(NVBIT32(SMDBG_EXCEPTION_TYPE_FATAL) ==
NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_FATAL);
ct_assert(NVBIT32(SMDBG_EXCEPTION_TYPE_TRAP) ==
NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_TRAP);
ct_assert(NVBIT32(SMDBG_EXCEPTION_TYPE_SINGLE_STEP) ==
NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_SINGLE_STEP);
ct_assert(NVBIT32(SMDBG_EXCEPTION_TYPE_INT) ==
NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_INT);
ct_assert(NVBIT32(SMDBG_EXCEPTION_TYPE_CILP) ==
NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_CILP);
ct_assert(NVBIT32(SMDBG_EXCEPTION_TYPE_PREEMPTION_STARTED) ==
NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_PREEMPTION_STARTED);
#endif // KERNEL_SM_DEBUGGER_EXCEPTION_H

1
src/nvidia/inc/kernel/gpu/gsp/gsp_init_args.h
View File

@@ -50,6 +50,7 @@ typedef struct
{
MESSAGE_QUEUE_INIT_ARGUMENTS messageQueueInitArguments;
GSP_SR_INIT_ARGUMENTS srInitArguments;
NvU32 gpuInstance;
} GSP_ARGUMENTS_CACHED;
#endif // GSP_INIT_ARGS_H

18
src/nvidia/inc/kernel/gpu/gsp/gsp_static_config.h
View File

@@ -35,11 +35,12 @@
#include "ctrl/ctrl2080/ctrl2080bios.h"
#include "ctrl/ctrl2080/ctrl2080fb.h"
#include "ctrl/ctrl2080/ctrl2080gpu.h"
#include "ctrl/ctrla083.h"
#include "gpu/gpu.h" // COMPUTE_BRANDING_TYPE
#include "gpu/gpu_acpi_data.h" // ACPI_METHOD_DATA
#include "vgpu/rpc_headers.h" // MAX_GPC_COUNT
#include "platform/chipset/chipset.h" // BUSINFO
#include "gpu/nvbitmask.h" // NVGPU_ENGINE_CAPS_MASK_ARRAY_MAX
typedef struct GspSMInfo_t
{
@@ -69,7 +70,7 @@ typedef struct GspStaticConfigInfo_t
NV0080_CTRL_GPU_GET_SRIOV_CAPS_PARAMS sriovCaps;
NvU32 sriovMaxGfid;
NvU64 engineCaps;
NvU32 engineCaps[NVGPU_ENGINE_CAPS_MASK_ARRAY_MAX];
GspSMInfo SM_info;
@@ -96,6 +97,7 @@ typedef struct GspStaticConfigInfo_t
NvBool bGeforceSmb;
NvBool bIsTitan;
NvBool bIsTesla;
NvBool bIsMobile;
NvU64 bar1PdeBase;
NvU64 bar2PdeBase;
@@ -110,8 +112,8 @@ typedef struct GspStaticConfigInfo_t
NvBool bClRootportNeedsNosnoopWAR;
NVA083_CTRL_VIRTUAL_DISPLAY_GET_NUM_HEADS_PARAMS displaylessMaxHeads;
NVA083_CTRL_VIRTUAL_DISPLAY_GET_MAX_RESOLUTION_PARAMS displaylessMaxResolution;
VIRTUAL_DISPLAY_GET_NUM_HEADS_PARAMS displaylessMaxHeads;
VIRTUAL_DISPLAY_GET_MAX_RESOLUTION_PARAMS displaylessMaxResolution;
NvU64 displaylessMaxPixels;
// Client handle for internal RMAPI control.
@@ -142,7 +144,15 @@ typedef struct GspSystemInfo
NvU8 oorArch;
NvU64 clPdbProperties;
NvU32 Chipset;
NvBool bGpuBehindBridge;
NvBool bUpstreamL0sUnsupported;
NvBool bUpstreamL1Unsupported;
NvBool bUpstreamL1PorSupported;
NvBool bUpstreamL1PorMobileOnly;
NvU8 upstreamAddressValid;
BUSINFO FHBBusInfo;
BUSINFO chipsetIDInfo;
ACPI_METHOD_DATA acpiMethodData;
} GspSystemInfo;

171
src/nvidia/inc/kernel/gpu/intr/engine_idx.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 1993-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -44,99 +44,96 @@
#define MC_ENGINE_IDX_VIDEO 5
#define MC_ENGINE_IDX_MD 6
#define MC_ENGINE_IDX_BUS 7
// UNUSED
#define MC_ENGINE_IDX_PMGR 9
#define MC_ENGINE_IDX_VP2 10
#define MC_ENGINE_IDX_CIPHER 11
#define MC_ENGINE_IDX_BIF 12
#define MC_ENGINE_IDX_PPP 13
#define MC_ENGINE_IDX_PRIVRING 14
#define MC_ENGINE_IDX_PMU 15
#define MC_ENGINE_IDX_CE0 16
#define MC_ENGINE_IDX_CE1 17
#define MC_ENGINE_IDX_CE2 18
#define MC_ENGINE_IDX_CE3 19
#define MC_ENGINE_IDX_CE4 20
#define MC_ENGINE_IDX_CE5 21
#define MC_ENGINE_IDX_CE6 22
#define MC_ENGINE_IDX_CE7 23
#define MC_ENGINE_IDX_CE8 24
#define MC_ENGINE_IDX_CE9 25
#define MC_ENGINE_IDX_VIC 26
#define MC_ENGINE_IDX_ISOHUB 27
#define MC_ENGINE_IDX_VGPU 28
#define MC_ENGINE_IDX_MSENC 29
#define MC_ENGINE_IDX_MSENC1 30
#define MC_ENGINE_IDX_MSENC2 31
#define MC_ENGINE_IDX_C2C 32
// UNUSED
#define MC_ENGINE_IDX_LTC 34
#define MC_ENGINE_IDX_FBHUB 35
#define MC_ENGINE_IDX_HDACODEC 36
#define MC_ENGINE_IDX_GMMU 37
#define MC_ENGINE_IDX_SEC2 38
#define MC_ENGINE_IDX_FSP 39
#define MC_ENGINE_IDX_NVLINK 40
#define MC_ENGINE_IDX_GSP 41
#define MC_ENGINE_IDX_NVJPG 42
#define MC_ENGINE_IDX_PMGR 8
#define MC_ENGINE_IDX_VP2 9
#define MC_ENGINE_IDX_CIPHER 10
#define MC_ENGINE_IDX_BIF 11
#define MC_ENGINE_IDX_PPP 12
#define MC_ENGINE_IDX_PRIVRING 13
#define MC_ENGINE_IDX_PMU 14
#define MC_ENGINE_IDX_CE0 15
#define MC_ENGINE_IDX_CE1 16
#define MC_ENGINE_IDX_CE2 17
#define MC_ENGINE_IDX_CE3 18
#define MC_ENGINE_IDX_CE4 19
#define MC_ENGINE_IDX_CE5 20
#define MC_ENGINE_IDX_CE6 21
#define MC_ENGINE_IDX_CE7 22
#define MC_ENGINE_IDX_CE8 23
#define MC_ENGINE_IDX_CE9 24
#define MC_ENGINE_IDX_VIC 35
#define MC_ENGINE_IDX_ISOHUB 36
#define MC_ENGINE_IDX_VGPU 37
#define MC_ENGINE_IDX_MSENC 38
#define MC_ENGINE_IDX_MSENC1 39
#define MC_ENGINE_IDX_MSENC2 40
#define MC_ENGINE_IDX_C2C 41
#define MC_ENGINE_IDX_LTC 42
#define MC_ENGINE_IDX_FBHUB 43
#define MC_ENGINE_IDX_HDACODEC 44
#define MC_ENGINE_IDX_GMMU 45
#define MC_ENGINE_IDX_SEC2 46
#define MC_ENGINE_IDX_FSP 47
#define MC_ENGINE_IDX_NVLINK 48
#define MC_ENGINE_IDX_GSP 49
#define MC_ENGINE_IDX_NVJPG 50
#define MC_ENGINE_IDX_NVJPEG MC_ENGINE_IDX_NVJPG
#define MC_ENGINE_IDX_NVJPEG0 MC_ENGINE_IDX_NVJPEG
#define MC_ENGINE_IDX_NVJPEG1 43
#define MC_ENGINE_IDX_NVJPEG2 44
#define MC_ENGINE_IDX_NVJPEG3 45
#define MC_ENGINE_IDX_NVJPEG4 46
#define MC_ENGINE_IDX_NVJPEG5 47
#define MC_ENGINE_IDX_NVJPEG6 48
#define MC_ENGINE_IDX_NVJPEG7 49
#define MC_ENGINE_IDX_REPLAYABLE_FAULT 50
#define MC_ENGINE_IDX_ACCESS_CNTR 51
#define MC_ENGINE_IDX_NON_REPLAYABLE_FAULT 52
#define MC_ENGINE_IDX_REPLAYABLE_FAULT_ERROR 53
#define MC_ENGINE_IDX_NON_REPLAYABLE_FAULT_ERROR 54
#define MC_ENGINE_IDX_INFO_FAULT 55
#define MC_ENGINE_IDX_BSP 56
#define MC_ENGINE_IDX_NVJPEG1 51
#define MC_ENGINE_IDX_NVJPEG2 52
#define MC_ENGINE_IDX_NVJPEG3 53
#define MC_ENGINE_IDX_NVJPEG4 54
#define MC_ENGINE_IDX_NVJPEG5 55
#define MC_ENGINE_IDX_NVJPEG6 56
#define MC_ENGINE_IDX_NVJPEG7 57
#define MC_ENGINE_IDX_REPLAYABLE_FAULT 58
#define MC_ENGINE_IDX_ACCESS_CNTR 59
#define MC_ENGINE_IDX_NON_REPLAYABLE_FAULT 60
#define MC_ENGINE_IDX_REPLAYABLE_FAULT_ERROR 61
#define MC_ENGINE_IDX_NON_REPLAYABLE_FAULT_ERROR 62
#define MC_ENGINE_IDX_INFO_FAULT 63
#define MC_ENGINE_IDX_BSP 64
#define MC_ENGINE_IDX_NVDEC MC_ENGINE_IDX_BSP
#define MC_ENGINE_IDX_NVDEC0 MC_ENGINE_IDX_NVDEC
#define MC_ENGINE_IDX_NVDEC1 57
#define MC_ENGINE_IDX_NVDEC2 58
#define MC_ENGINE_IDX_NVDEC3 59
#define MC_ENGINE_IDX_NVDEC4 60
#define MC_ENGINE_IDX_NVDEC5 61
#define MC_ENGINE_IDX_NVDEC6 62
#define MC_ENGINE_IDX_NVDEC7 63
#define MC_ENGINE_IDX_CPU_DOORBELL 64
#define MC_ENGINE_IDX_PRIV_DOORBELL 65
#define MC_ENGINE_IDX_MMU_ECC_ERROR 66
#define MC_ENGINE_IDX_BLG 67
#define MC_ENGINE_IDX_PERFMON 68
#define MC_ENGINE_IDX_BUF_RESET 69
#define MC_ENGINE_IDX_XBAR 70
#define MC_ENGINE_IDX_ZPW 71
#define MC_ENGINE_IDX_OFA0 72
#define MC_ENGINE_IDX_TEGRA 73
#define MC_ENGINE_IDX_GR 74
#define MC_ENGINE_IDX_NVDEC1 65
#define MC_ENGINE_IDX_NVDEC2 66
#define MC_ENGINE_IDX_NVDEC3 67
#define MC_ENGINE_IDX_NVDEC4 68
#define MC_ENGINE_IDX_NVDEC5 69
#define MC_ENGINE_IDX_NVDEC6 70
#define MC_ENGINE_IDX_NVDEC7 71
#define MC_ENGINE_IDX_CPU_DOORBELL 72
#define MC_ENGINE_IDX_PRIV_DOORBELL 73
#define MC_ENGINE_IDX_MMU_ECC_ERROR 74
#define MC_ENGINE_IDX_BLG 75
#define MC_ENGINE_IDX_PERFMON 76
#define MC_ENGINE_IDX_BUF_RESET 77
#define MC_ENGINE_IDX_XBAR 78
#define MC_ENGINE_IDX_ZPW 79
#define MC_ENGINE_IDX_OFA0 80
#define MC_ENGINE_IDX_TEGRA 81
#define MC_ENGINE_IDX_GR 82
#define MC_ENGINE_IDX_GR0 MC_ENGINE_IDX_GR
#define MC_ENGINE_IDX_GR1 75
#define MC_ENGINE_IDX_GR2 76
#define MC_ENGINE_IDX_GR3 77
#define MC_ENGINE_IDX_GR4 78
#define MC_ENGINE_IDX_GR5 79
#define MC_ENGINE_IDX_GR6 80
#define MC_ENGINE_IDX_GR7 81
#define MC_ENGINE_IDX_ESCHED 82
#define MC_ENGINE_IDX_GR1 83
#define MC_ENGINE_IDX_GR2 84
#define MC_ENGINE_IDX_GR3 85
#define MC_ENGINE_IDX_GR4 86
#define MC_ENGINE_IDX_GR5 87
#define MC_ENGINE_IDX_GR6 88
#define MC_ENGINE_IDX_GR7 89
#define MC_ENGINE_IDX_ESCHED 90
#define MC_ENGINE_IDX_ESCHED__SIZE 64
#define MC_ENGINE_IDX_GR_FECS_LOG 146
#define MC_ENGINE_IDX_GR_FECS_LOG 154
#define MC_ENGINE_IDX_GR0_FECS_LOG MC_ENGINE_IDX_GR_FECS_LOG
#define MC_ENGINE_IDX_GR1_FECS_LOG 147
#define MC_ENGINE_IDX_GR2_FECS_LOG 148
#define MC_ENGINE_IDX_GR3_FECS_LOG 149
#define MC_ENGINE_IDX_GR4_FECS_LOG 150
#define MC_ENGINE_IDX_GR5_FECS_LOG 151
#define MC_ENGINE_IDX_GR6_FECS_LOG 152
#define MC_ENGINE_IDX_GR7_FECS_LOG 153
#define MC_ENGINE_IDX_TMR_SWRL 154
#define MC_ENGINE_IDX_MAX 155 // This must be kept as the max bit if
#define MC_ENGINE_IDX_GR1_FECS_LOG 155
#define MC_ENGINE_IDX_GR2_FECS_LOG 156
#define MC_ENGINE_IDX_GR3_FECS_LOG 157
#define MC_ENGINE_IDX_GR4_FECS_LOG 158
#define MC_ENGINE_IDX_GR5_FECS_LOG 159
#define MC_ENGINE_IDX_GR6_FECS_LOG 160
#define MC_ENGINE_IDX_GR7_FECS_LOG 161
#define MC_ENGINE_IDX_TMR_SWRL 162
#define MC_ENGINE_IDX_MAX 163 // This must be kept as the max bit if
// we need to add more engines
#define MC_ENGINE_IDX_INVALID 0xFFFFFFFF

3
src/nvidia/inc/kernel/gpu/intrable/intrable.h
View File

@@ -1,3 +0,0 @@
#include "g_intrable_nvoc.h"

3
src/nvidia/inc/kernel/gpu/mem_mgr/mem_mapper.h Normal file
View File

@@ -0,0 +1,3 @@
#include "g_mem_mapper_nvoc.h"

13
src/nvidia/inc/kernel/gpu/mem_mgr/phys_mem_allocator/phys_mem_allocator.h
View File

@@ -156,11 +156,20 @@ typedef struct _RANGELISTTYPE
struct _RANGELISTTYPE *pNext;
} RANGELISTTYPE, *PRANGELISTTYPE;
typedef enum
{
MEMORY_PROTECTION_UNPROTECTED = 0,
MEMORY_PROTECTION_PROTECTED = 1
} MEMORY_PROTECTION;
/*!
* @brief Callbacks to UVM for eviction
*/
typedef NV_STATUS (*pmaEvictPagesCb_t)(void *ctxPtr, NvU32 pageSize, NvU64 *pPages, NvU32 count, NvU64 physBegin, NvU64 physEnd);
typedef NV_STATUS (*pmaEvictRangeCb_t)(void *ctxPtr, NvU64 physBegin, NvU64 physEnd);
typedef NV_STATUS (*pmaEvictPagesCb_t)(void *ctxPtr, NvU32 pageSize, NvU64 *pPages,
NvU32 count, NvU64 physBegin, NvU64 physEnd,
MEMORY_PROTECTION prot);
typedef NV_STATUS (*pmaEvictRangeCb_t)(void *ctxPtr, NvU64 physBegin, NvU64 physEnd,
MEMORY_PROTECTION prot);
/*!
* @brief Pluggable data structure management. Currently we have regmap and address tree.

7
src/nvidia/inc/kernel/gpu/mem_mgr/phys_mem_allocator/phys_mem_allocator_util.h
View File

@@ -42,10 +42,11 @@ void pmaRegionPrint(PMA *pPma, PMA_REGION_DESCRIPTOR *pRegion, void *pMap);
NvBool pmaStateCheck(PMA *pPma);
// Temporary putting these here. TODO refactor them in the next CL.
NV_STATUS _pmaEvictContiguous(PMA *pPma, void *pMap, NvU64 evictStart, NvU64 evictEnd);
NV_STATUS _pmaEvictContiguous(PMA *pPma, void *pMap, NvU64 evictStart, NvU64 evictEnd,
MEMORY_PROTECTION prot);
NV_STATUS _pmaEvictPages(PMA *pPma, void *pMap, NvU64 *evictPages, NvU64 evictPageCount,
NvU64 *allocPages, NvU64 allocPageCount, NvU32 pageSize, NvU64 physBegin,
NvU64 physEnd);
NvU64 *allocPages, NvU64 allocPageCount, NvU32 pageSize,
NvU64 physBegin, NvU64 physEnd, MEMORY_PROTECTION prot);
void _pmaClearScrubBit(PMA *pPma, SCRUB_NODE *pPmaScrubList, NvU64 count);
NV_STATUS _pmaCheckScrubbedPages(PMA *pPma, NvU64 chunkSize, NvU64 *pPages, NvU32 pageCount);
NV_STATUS _pmaPredictOutOfMemory(PMA *pPma, NvLength allocationCount, NvU32 pageSize,

1
src/nvidia/inc/kernel/gpu/mem_mgr/virt_mem_allocator_common.h
View File

@@ -53,6 +53,7 @@ typedef struct EVENTNOTIFICATION EVENTNOTIFICATION;
#define RM_PAGE_MASK 0x0FFF
#define RM_PAGE_SHIFT 12
#define RM_PAGE_SHIFT_64K 16
#define RM_PAGE_SHIFT_128K 17
// Huge page size is 2 MB
#define RM_PAGE_SHIFT_HUGE 21

39
src/nvidia/inc/kernel/gpu/nvbitmask.h Normal file
View File

@@ -0,0 +1,39 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _NVBITMASK_H_
#define _NVBITMASK_H_
#include "kernel/gpu/gpu_engine_type.h"
//
// Engine Type capability mask bit-array helper MACROS to support on growing number of engine types
// The caps is defined as
// NvU32 caps[NVGPU_ENGINE_CAPS_MASK_ARRAY_MAX]
//
#define NVGPU_ENGINE_CAPS_MASK_BITS 32
#define NVGPU_ENGINE_CAPS_MASK_ARRAY_MAX ((RM_ENGINE_TYPE_LAST-1)/NVGPU_ENGINE_CAPS_MASK_BITS + 1)
#define NVGPU_GET_ENGINE_CAPS_MASK(caps, id) (caps[(id)/NVGPU_ENGINE_CAPS_MASK_BITS] & NVBIT((id) % NVGPU_ENGINE_CAPS_MASK_BITS))
#define NVGPU_SET_ENGINE_CAPS_MASK(caps, id) (caps[(id)/NVGPU_ENGINE_CAPS_MASK_BITS] |= NVBIT((id) % NVGPU_ENGINE_CAPS_MASK_BITS))
#endif //_NVBITMASK_H_

35
src/nvidia/inc/kernel/gpu/nvlink/common_nvlink.h Normal file
View File

@@ -0,0 +1,35 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef COMMON_NVLINK_H
#define COMMON_NVLINK_H
#include "core/core.h"
#include "kernel/gpu/nvlink/kernel_nvlink.h"
#include "kernel/gpu/nvlink/kernel_ioctrl.h"
#include "ctrl/ctrl2080/ctrl2080nvlink.h" // rmcontrol params
NV_STATUS nvlinkCtrlCmdBusGetNvlinkCaps(OBJGPU *pGpu, NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS_PARAMS *pParams);
#endif // COMMON_NVLINK_H

71
src/nvidia/inc/kernel/gpu/perf/kern_perf_1hz.h
View File

@@ -1,71 +0,0 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef KERNEL_PERF_1HZ_H
#define KERNEL_PERF_1HZ_H
/* ------------------------ Includes --------------------------------------- */
#include "gpu/gpu_resource.h"
#include "objtmr.h"
/* ------------------------ Macros ----------------------------------------- */
/* ------------------------ Datatypes -------------------------------------- */
/*!
* This structure represents data for managing 1HZ Callback timer
*/
typedef struct
{
/*!
* NV_TRUE if 1Hz callback is in progress
*/
NvBool b1HzTimerCallback;
/*!
* TRUE if AllowMaxPerf and not in Hibernate/Standby
*/
NvBool bEnableTimerUpdates;
} KERNEL_PERF_1HZ;
/* -------------------- Function Prototypes -------------------------------- */
/*!
* @brief Handle 1Hz timer callback from SW interrupts
*
* @param[in] pGpu OBJGPU pointer
* @param[in] pTmr OBJTMR pointer
* @param[in] *ptr timer callback ID
*
* @returns Always return NV_OK
*
*/
NV_STATUS kperfTimerProc(OBJGPU *pGpu, OBJTMR *pTmr, void *ptr);
/*!
* Since the function tmrCancelCallback() needs a distinct value for POBJECT,
* we can not just use any value in the POBJECT field if we intend to use
* tmrCancelCallback() function. For scheduling Kernel Perf related callbacks we
* will use the unique value for the Kernel Perf by using the address of the function
* that will be called when timer elapses.
*/
#define TMR_POBJECT_KERNEL_PERF_1HZ ((void *)(kperfTimerProc))
#endif // KERNEL_PERF_1HZ_H

6
src/nvidia/inc/kernel/gpu/subdevice/subdevice_ctrl_ccu_internal.h
View File

@@ -27,5 +27,9 @@
RMCTRL_EXPORT(NV2080_CTRL_CMD_INTERNAL_CCU_UNMAP,
RMCTRL_FLAGS(KERNEL_PRIVILEGED, ROUTE_TO_PHYSICAL, INTERNAL))
NV_STATUS subdeviceCtrlCmdCcuUnmap(Subdevice *pSubdevice);
NV_STATUS subdeviceCtrlCmdCcuUnmap(Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_CCU_UNMAP_INFO_PARAMS *pParams);
RMCTRL_EXPORT(NV2080_CTRL_CMD_INTERNAL_CCU_SET_STREAM_STATE,
RMCTRL_FLAGS(KERNEL_PRIVILEGED, ROUTE_TO_PHYSICAL, INTERNAL))
NV_STATUS subdeviceCtrlCmdCcuSetStreamState(Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_CCU_STREAM_STATE_PARAMS *pParams);