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Andy Ritger
2022-11-10 08:39:33 -08:00
parent 7c345b838b
commit 758b4ee818
1323 changed files with 262135 additions and 60754 deletions
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src/nvidia/kernel/inc/dev_p2060.h Normal file
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/*
* SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef DEV_P2060_H
#define DEV_P2060_H
#define NV_P2060_STATUS 0x00 /* R--1R */
#define NV_P2060_STATUS_VAL 7:0 /* R-XVF */
#define NV_P2060_STATUS_VCXO 1:0 /* R-XVF */
#define NV_P2060_STATUS_VCXO_NOLOCK_TOO_FAST 0x00 /* R---V */
#define NV_P2060_STATUS_VCXO_NOLOCK_TOO_SLOW 0x01 /* R---V */
#define NV_P2060_STATUS_VCXO_LOCK 0x02 /* R---V */
#define NV_P2060_STATUS_VCXO_NOT_SERVO 0x03 /* R---V */
#define NV_P2060_STATUS_SYNC_LOSS 2:2 /* R-XVF */
#define NV_P2060_STATUS_SYNC_LOSS_FALSE 0x00 /* R---V */
#define NV_P2060_STATUS_SYNC_LOSS_TRUE 0x01 /* R---V */
#define NV_P2060_STATUS_RESERVED1 3:3 /* RWXVF */
#define NV_P2060_STATUS_GPU_STEREO 4:4 /* R-XVF */
#define NV_P2060_STATUS_GPU_STEREO_NOT_ACTIVE 0x00 /* R---V */
#define NV_P2060_STATUS_GPU_STEREO_ACTIVE 0x01 /* R---V */
#define NV_P2060_STATUS_MSTR_STEREO 5:5 /* R-XVF */
#define NV_P2060_STATUS_MSTR_STEREO_NOT_ACTIVE 0x00 /* R---V */
#define NV_P2060_STATUS_MSTR_STEREO_ACTIVE 0x01 /* R---V */
#define NV_P2060_STATUS_STEREO 6:6 /* R-XVF */
#define NV_P2060_STATUS_STEREO_NOLOCK 0x00 /* R---V */
#define NV_P2060_STATUS_STEREO_LOCK 0x01 /* R---V */
#define NV_P2060_STATUS_RESERVED2 7:7 /* RWXVF */
#define NV_P2060_STATUS2 0x01 /* RW-1R */
#define NV_P2060_STATUS2_VAL 7:0 /* R-XVF */
#define NV_P2060_STATUS2_PORT0 0:0 /* RWIVF */
#define NV_P2060_STATUS2_PORT0_INPUT 0x00 /* RWI-V */
#define NV_P2060_STATUS2_PORT0_OUTPUT 0x01 /* RW--V */
#define NV_P2060_STATUS2_PORT1 1:1 /* RWIVF */
#define NV_P2060_STATUS2_PORT1_INPUT 0x00 /* RWI-V */
#define NV_P2060_STATUS2_PORT1_OUTPUT 0x01 /* RW--V */
#define NV_P2060_STATUS2_ETHER0_DETECTED 2:2 /* RWIVF */
#define NV_P2060_STATUS2_ETHER0_DETECTED_FALSE 0x00 /* RWI-V */
#define NV_P2060_STATUS2_ETHER0_DETECTED_TRUE 0x01 /* R---V */
#define NV_P2060_STATUS2_ETHER1_DETECTED 3:3 /* RWIVF */
#define NV_P2060_STATUS2_ETHER1_DETECTED_FALSE 0x00 /* RWI-V */
#define NV_P2060_STATUS2_ETHER1_DETECTED_TRUE 0x01 /* R---V */
#define NV_P2060_STATUS2_HS_DETECT 5:4 /* RWXVF */
#define NV_P2060_STATUS2_HS_DETECT_NONE 0x00 /* R---V */
#define NV_P2060_STATUS2_HS_DETECT_TTL 0x01 /* R---V */
#define NV_P2060_STATUS2_HS_DETECT_COMPOSITE 0x02 /* R---V */
#define NV_P2060_STATUS2_HS_DETECT_NOT_IN_USE 0x03 /* R---V */
#define NV_P2060_STATUS2_GPU_PORT 7:6 /* R-XVF */
#define NV_P2060_STATUS2_GPU_PORT_CONN0 0x00 /* R---V */
#define NV_P2060_STATUS2_GPU_PORT_CONN1 0x01 /* R---V */
#define NV_P2060_STATUS2_GPU_PORT_CONN2 0x02 /* R---V */
#define NV_P2060_STATUS2_GPU_PORT_CONN3 0x03 /* R---V */
#define NV_P2060_STATUS3 0x02 /* RW-1R */
#define NV_P2060_STATUS3_VAL 7:0 /* R-XVF */
#define NV_P2060_STATUS3_RESERVED 0:0 /* R-XVF */
#define NV_P2060_STATUS3_LB_INT_FAIL 1:1 /* R-XVF */
#define NV_P2060_STATUS3_LB_INT_FAIL_FALSE 0x00 /* RW--V */
#define NV_P2060_STATUS3_LB_INT_FAIL_TRUE 0x01 /* RW--V */
#define NV_P2060_STATUS3_LB_VTGRST_FAIL 2:2 /* R-XVF */
#define NV_P2060_STATUS3_LB_VTGRST_FAIL_FALSE 0x00 /* RW--V */
#define NV_P2060_STATUS3_LB_VTGRST_FAIL_TRUE 0x01 /* RW--V */
#define NV_P2060_STATUS3_LB_GSWPRDY_FAIL 3:3 /* R-XVF */
#define NV_P2060_STATUS3_LB_GSWPRDY_FAIL_FALSE 0x00 /* RW--V */
#define NV_P2060_STATUS3_LB_GSWPRDY_FAIL_TRUE 0x01 /* RW--V */
#define NV_P2060_STATUS3_LB_SYNC_FAIL 4:4 /* RWXVF */
#define NV_P2060_STATUS3_LB_SYNC_FAIL_FALSE 0x00 /* RW--V */
#define NV_P2060_STATUS3_LB_SYNC_FAIL_TRUE 0x01 /* RW--V */
#define NV_P2060_STATUS3_LB_STEREO_FAIL 5:5 /* RWXVF */
#define NV_P2060_STATUS3_LB_STEREO_FAIL_FALSE 0x00 /* RW--V */
#define NV_P2060_STATUS3_LB_STEREO_FAIL_TRUE 0x01 /* RW--V */
#define NV_P2060_STATUS3_LB_SWPRDY_FAIL 6:6 /* RWXVF */
#define NV_P2060_STATUS3_LB_SWPRDY_FAIL_FALSE 0x00 /* RW--V */
#define NV_P2060_STATUS3_LB_SWPRDY_FAIL_TRUE 0x01 /* RW--V */
#define NV_P2060_STATUS3_GENLOCKED 7:7 /* RWXVF */
#define NV_P2060_STATUS3_GENLOCKED_FALSE 0x00 /* RW--V */
#define NV_P2060_STATUS3_GENLOCKED_TRUE 0x01 /* RW--V */
#define NV_P2060_STATUS4 0x13 /* RW-1R */
#define NV_P2060_STATUS4_VAL 7:0 /* R-XVF */
#define NV_P2060_STATUS4_INT_GROUP 7:6 /* R-XVF */
#define NV_P2060_STATUS4_INT_GROUP_LOSS 0x00 /* R-XVF */
#define NV_P2060_STATUS4_INT_GROUP_GAIN 0x01 /* R-XVF */
#define NV_P2060_STATUS4_INT_GROUP_MISC 0x02 /* R-XVF */
#define NV_P2060_STATUS4_SYNC 0:0 /* R---V */
#define NV_P2060_STATUS4_STEREO 1:1 /* R---V */
#define NV_P2060_STATUS4_HS 2:2 /* R---V */
#define NV_P2060_STATUS4_RJ45 3:3 /* R---V */
#define NV_P2060_STATUS4_RESERVED_GRP01 5:4 /* R---V */
//Value 1 in bits 0-5 indicate loss and gain depending on interrupt group 00/01 (bit 6-7)
#define NV_P2060_STATUS4_FRM_CNT_MATCH_INT 0:0 /* R-XVF */
#define NV_P2060_STATUS4_FRM_CNT_MATCH_INT_CLEAR 0x00 /* R---V */
#define NV_P2060_STATUS4_FRM_CNT_MATCH_INT_PENDING 0x01 /* R---V */
#define NV_P2060_STATUS4_SWAPRDY_INT 1:1 /* R-XVF */
#define NV_P2060_STATUS4_SWAPRDY_INT_CLEAR 0x00 /* R---V */
#define NV_P2060_STATUS4_SWAPRDY_INT_PENDING 0x01 /* R---V */
#define NV_P2060_STATUS4_ERROR_INT 2:2 /* R-XVF */
#define NV_P2060_STATUS4_ERROR_INT_CLEAR 0x00 /* R---V */
#define NV_P2060_STATUS4_ERROR_INT_PENDING 0x01 /* R---V */
#define NV_P2060_STATUS4_FRM_CNT_ROLLOVER_INT 3:3 /* R-XVF */
#define NV_P2060_STATUS4_FRM_CNT_ROLLOVER_INT_CLEAR 0x00 /* R---V */
#define NV_P2060_STATUS4_FRM_CNT_ROLLOVER_INT_PENDING 0x01 /* R---V */
#define NV_P2060_STATUS4_RESERVED_GRP10 5:4 /* R---V */
//Value 1 in bits 0-5 indicate interrupt pending depending on interrupt group 10 (bit 6-7)
#define NV_P2060_CONTROL 0x03 /* RW-1R */
#define NV_P2060_CONTROL_I_AM 0:0 /* RWXVF */
#define NV_P2060_CONTROL_I_AM_SLAVE 0x00 /* RWI-V */
#define NV_P2060_CONTROL_I_AM_MASTER 0x01 /* RWI-V */
#define NV_P2060_CONTROL_SYNC_POLARITY 2:1 /* RWXVF */
#define NV_P2060_CONTROL_SYNC_POLARITY_RISING_EDGE 0x00 /* RW--V */
#define NV_P2060_CONTROL_SYNC_POLARITY_FALLING_EDGE 0x01 /* RW--V */
#define NV_P2060_CONTROL_SYNC_POLARITY_BOTH 0x02 /* RW--V */
#define NV_P2060_CONTROL_TEST_MODE 3:3 /* RWXVF */
#define NV_P2060_CONTROL_TEST_MODE_OFF 0x00 /* RW--V */
#define NV_P2060_CONTROL_TEST_MODE_ON 0x01 /* RW--V */
#define NV_P2060_CONTROL_SYNC_SRC 5:4 /* RWXVF */
#define NV_P2060_CONTROL_SYNC_SRC_CONN0 0x00 /* RW--V */
#define NV_P2060_CONTROL_SYNC_SRC_CONN1 0x01 /* RW--V */
#define NV_P2060_CONTROL_SYNC_SRC_CONN2 0x02 /* RW--V */
#define NV_P2060_CONTROL_SYNC_SRC_CONN3 0x03 /* RW--V */
#define NV_P2060_CONTROL_INTERLACE_MODE 6:6 /* RWXVF */
#define NV_P2060_CONTROL_INTERLACE_MODE_FALSE 0x00 /* RW--V */
#define NV_P2060_CONTROL_INTERLACE_MODE_TRUE 0x01 /* RW--V */
#define NV_P2060_CONTROL_SYNC_SELECT 7:7 /* RWXVF */
#define NV_P2060_CONTROL_SYNC_SELECT_INTERNAL 0x00 /* RW--V */
#define NV_P2060_CONTROL_SYNC_SELECT_HOUSE 0x01 /* RW--V */
#define NV_P2060_CONTROL2 0x04 /* RW-1R */
#define NV_P2060_CONTROL2_LAMUX 1:0 /* RWXVF */
#define NV_P2060_CONTROL2_LAMUX_0 0x00 /* RWI-V */
#define NV_P2060_CONTROL2_FRAMERATE_RPT 3:2 /* RWXVF */
#define NV_P2060_CONTROL2_FRAMERATE_RPT_LIVE 0x00 /* RW--V */
#define NV_P2060_CONTROL2_FRAMERATE_RPT_MIN 0x02 /* RW--V */
#define NV_P2060_CONTROL2_FRAMERATE_RPT_MAX 0x03 /* RW--V */
#define NV_P2060_CONTROL2_RESET 4:4 /* RWXVF */
#define NV_P2060_CONTROL2_RESET_FALSE 0x00 /* RW--V */
#define NV_P2060_CONTROL2_RESET_TRUE 0x01 /* RW--V */
#define NV_P2060_CONTROL2_SWAP_READY 5:5 /* RWXVF */
#define NV_P2060_CONTROL2_SWAP_READY_DISABLE 0x00 /* RW--V */
#define NV_P2060_CONTROL2_SWAP_READY_ENABLE 0x01 /* RW--V */
#define NV_P2060_CONTROL2_RESERVED 6:6 /* RWXVF */
#define NV_P2060_CONTROL2_LOOPBACK_MODE 7:7 /* RWXVF */
#define NV_P2060_CONTROL2_LOOPBACK_MODE_OFF 0x00 /* RW--V */
#define NV_P2060_CONTROL2_LOOPBACK_MODE_ON 0x01 /* RW--V */
#define NV_P2060_CONTROL3 0x05 /* RW-1R */
#define NV_P2060_CONTROL3_INTERRUPT 6:0 /* RWXVF */
#define NV_P2060_CONTROL3_INTERRUPT_DISABLE 0x00 /* RW--V */
#define NV_P2060_CONTROL3_INTERRUPT_ON_STEREO_CHG 0x01 /* RW--V */
#define NV_P2060_CONTROL3_INTERRUPT_ON_ERROR 0x02 /* RW--V */
#define NV_P2060_CONTROL3_INTERRUPT_ON_FRAME_MATCH 0x04 /* RW--V */
#define NV_P2060_CONTROL3_INTERRUPT_ON_HS_CHG 0x08 /* RW--V */
#define NV_P2060_CONTROL3_INTERRUPT_ON_SYNC_CHG 0x10 /* RW--V */
#define NV_P2060_CONTROL3_INTERRUPT_ON_RJ45_CHG 0x20 /* RW--V */
#define NV_P2060_CONTROL3_INTERRUPT_ON_ALL 0x7f /* RW--V */
#define NV_P2060_CONTROL3_RESYNC 7:7 /* RWXVF */
#define NV_P2060_CONTROL3_RESYNC_OFF 0x00 /* RW--V */
#define NV_P2060_CONTROL3_RESYNC_ON 0x01 /* RW--V */
#define NV_P2060_CONTROL4 0x06 /* RW-1R */
#define NV_P2060_CONTROL4_SWPRDYINT_DELAY 2:0 /* RWXVF */
#define NV_P2060_CONTROL4_STEREO_LOCK_MODE 3:3 /* RWXVF */
#define NV_P2060_CONTROL4_STEREO_LOCK_MODE_OFF 0x00 /* RW--V */
#define NV_P2060_CONTROL4_STEREO_LOCK_MODE_ON 0x01 /* RW--V */
#define NV_P2060_CONTROL4_EXT_STEREO_SYNC 4:4 /* RWXVF */
#define NV_P2060_CONTROL4_EXT_STEREO_SYNC_OFF 0x00 /* RW--V */
#define NV_P2060_CONTROL4_EXT_STEREO_SYNC_ON 0x01 /* RW--V */
#define NV_P2060_CONTROL4_EXT_STEREO_SYNC_POL 5:5 /* RWXVF */
#define NV_P2060_CONTROL4_EXT_STEREO_SYNC_POL_LOW 0x00 /* RW--V */
#define NV_P2060_CONTROL4_EXT_STEREO_SYNC_POL_HI 0x01 /* RW--V */
#define NV_P2060_CONTROL4_RESERVED2 7:6 /* RWXVF */
#define NV_P2060_FPGA 0x07 /* R--1R */
#define NV_P2060_FPGA_REV 3:0 /* R-XVF */
#define NV_P2060_FPGA_ID 7:4 /* R-XVF */
#define NV_P2060_FPGA_ID_0 0x00 /* R---V */
#define NV_P2060_FPGA_ID_5 0x05 /* R---V */
#define NV_P2061_FPGA_ID 7:4 /* R-XVF */
#define NV_P2061_FPGA_ID_4 0x04 /* R---V */
#define NV_P2060_SYNC_SKEW_LOW 0x08 /* RW-1R */
#define NV_P2060_SYNC_SKEW_LOW_VAL 7:0 /* RWIVF */
#define NV_P2060_SYNC_SKEW_LOW_VAL_0 0x00 /* RWI-V */
#define NV_P2060_SYNC_SKEW_HIGH 0x09 /* RW-1R */
#define NV_P2060_SYNC_SKEW_HIGH_VAL 7:0 /* RWIVF */
#define NV_P2060_SYNC_SKEW_HIGH_VAL_0 0x00 /* RWI-V */
#define NV_P2060_START_DELAY_LOW 0x0A /* RW-1R */
#define NV_P2060_START_DELAY_LOW_VAL 7:0 /* RWIVF */
#define NV_P2060_START_DELAY_LOW_VAL_0 0x00 /* RWI-V */
#define NV_P2060_START_DELAY_HIGH 0x0B /* RW-1R */
#define NV_P2060_START_DELAY_HIGH_VAL 7:0 /* RWIVF */
#define NV_P2060_START_DELAY_HIGH_VAL_0 0x00 /* RWI-V */
#define NV_P2060_NSYNC 0x0C /* RW-1R */
#define NV_P2060_NSYNC_FL 2:0 /* RWIVF */
#define NV_P2060_NSYNC_GPU 6:4 /* RWIVF */
#define NV_P2060_NSYNC_ALL 7:0 /* RWIVF */
#define NV_P2060_FRAMECNTR_LOW 0x0D /* R--1R */
#define NV_P2060_FRAMECNTR_LOW_VAL 7:0 /* RWIVF */
#define NV_P2060_FRAMECNTR_LOW_VAL_0 0x00 /* RWI-V */
#define NV_P2060_FRAMECNTR_MID 0x0E /* R--1R */
#define NV_P2060_FRAMECNTR_MID_VAL 7:0 /* RWIVF */
#define NV_P2060_FRAMECNTR_MID_VAL_0 0x00 /* RWI-V */
#define NV_P2060_FRAMECNTR_HIGH 0x0F /* R--1R */
#define NV_P2060_FRAMECNTR_HIGH_VAL 7:0 /* RWIVF */
#define NV_P2060_FRAMECNTR_HIGH_VAL_0 0x00 /* RWI-V */
#define NV_P2060_FRAMERATE_LOW 0x10 /* R--1R */
#define NV_P2060_FRAMERATE_LOW_VAL 7:0 /* RWIVF */
#define NV_P2060_FRAMERATE_LOW_VAL_0 0x00 /* RWI-V */
#define NV_P2060_FRAMERATE_MID 0x11 /* R--1R */
#define NV_P2060_FRAMERATE_MID_VAL 7:0 /* RWIVF */
#define NV_P2060_FRAMERATE_MID_VAL_0 0x00 /* RWI-V */
#define NV_P2060_FRAMERATE_HIGH 0x12 /* R--1R */
#define NV_P2060_FRAMERATE_HIGH_VAL 7:0 /* RWIVF */
#define NV_P2060_FRAMERATE_HIGH_VAL_0 0x00 /* RWI-V */
#define NV_P2060_FPGA_EXREV 0x17 /* R--1R */
#define NV_P2060_FPGA_EXREV_VAL 7:0 /* RWIVF */
#define NV_P2060_FPGA_EXREV_VAL_0 0x00 /* RWI-V */
#define NV_P2060_FPGA_ASGN_ID_0 0x18 /* R--1R */
#define NV_P2060_FPGA_ASGN_ID_0_VAL 7:0 /* RWIVF */
#define NV_P2060_FPGA_ASGN_ID_1 0x19 /* R--1R */
#define NV_P2060_FPGA_ASGN_ID_1_VAL 7:0 /* RWIVF */
#define NV_P2060_FPGA_ASGN_ID_2 0x1A /* R--1R */
#define NV_P2060_FPGA_ASGN_ID_2_VAL 7:0 /* RWIVF */
#define NV_P2060_FPGA_ASGN_ID_3 0x1B /* R--1R */
#define NV_P2060_FPGA_ASGN_ID_3_VAL 7:0 /* RWIVF */
#define NV_P2060_FPGA_ASGN_ID(i) (0x18 + i)
#define NV_P2060_FRAME_CMPR_LOW 0x1D /* R--1R */
#define NV_P2060_FRAME_CMPR_LOW_VAL 7:0 /* RWIVF */
#define NV_P2060_FRAME_CMPR_LOW_VAL_0 0x00 /* RWI-V */
#define NV_P2060_FRAME_CMPR_MID 0x1E /* R--1R */
#define NV_P2060_FRAME_CMPR_MID_VAL 7:0 /* RWIVF */
#define NV_P2060_FRAME_CMPR_MID_VAL_0 0x00 /* RWI-V */
#define NV_P2060_FRAME_CMPR_HIGH 0x1F /* R--1R */
#define NV_P2060_FRAME_CMPR_HIGH_VAL 7:0 /* RWIVF */
#define NV_P2060_FRAME_CMPR_HIGH_VAL_0 0x00 /* RWI-V */
#define NV_P2060_HS_FRAMERATE_LOW 0x20 /* R--1R */
#define NV_P2060_HS_FRAMERATE_LOW_VAL 7:0 /* RWIVF */
#define NV_P2060_HS_FRAMERATE_LOW_VAL_0 0x00 /* RWI-V */
#define NV_P2060_HS_FRAMERATE_MID 0x21 /* R--1R */
#define NV_P2060_HS_FRAMERATE_MID_VAL 7:0 /* RWIVF */
#define NV_P2060_HS_FRAMERATE_MID_VAL_0 0x00 /* RWI-V */
#define NV_P2060_HS_FRAMERATE_HIGH 0x22 /* R--1R */
#define NV_P2060_HS_FRAMERATE_HIGH_VAL 7:0 /* RWIVF */
#define NV_P2060_HS_FRAMERATE_HIGH_VAL_0 0x00 /* RWI-V */
#define NV_P2060_MOSAIC_MODE 0x23 /* RW-1R */
#define NV_P2060_MOSAIC_MODE_TS 1:0 /* RWIVF */
#define NV_P2060_MOSAIC_MODE_TS_CONN0 0x00 /* R---V */
#define NV_P2060_MOSAIC_MODE_TS_CONN1 0x01 /* RW--V */
#define NV_P2060_MOSAIC_MODE_TS_CONN2 0x02 /* RW--V */
#define NV_P2060_MOSAIC_MODE_TS_CONN3 0x03 /* RW--V */
#define NV_P2060_MOSAIC_MODE_GROUP 2:2 /* RWIVF */
#define NV_P2060_MOSAIC_MODE_GROUP_ZERO 0x00 /* RW--V */
#define NV_P2060_MOSAIC_MODE_GROUP_ONE 0x01 /* RW--V */
#define NV_P2060_MOSAIC_MODE_ENABLE 3:3 /* RWIVF */
#define NV_P2060_MOSAIC_MODE_ENABLE_FALSE 0x00 /* RW--V */
#define NV_P2060_MOSAIC_MODE_ENABLE_TRUE 0x01 /* RW--V */
#define NV_P2060_MOSAIC_MODE_RESERVED 7:4 /* RWIVF */
#endif //DEV_P2060_H

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/*
* SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef DEV_P2061_H
#define DEV_P2061_H
#define NV_P2061_CONTROL4 0x06 /* RW-1R */
#define NV_P2061_CONTROL4_HOUSE_SYNC_MODE 6:6 /* RWXVF */
#define NV_P2061_CONTROL4_HOUSE_SYNC_MODE_INPUT 0x0 /* RW--V */
#define NV_P2061_CONTROL4_HOUSE_SYNC_MODE_OUTPUT 0x1 /* RW--V */
#define NV_P2061_STATUS6 0x2E /* RW-1R */
#define NV_P2061_STATUS6_INT_PORT_DIRECTION 7:7 /* RWXVF */
#define NV_P2061_STATUS6_INT_PORT_DIRECTION_INPUT 0 /* RWXVF */
#define NV_P2061_STATUS6_INT_PORT_DIRECTION_OUTPUT 1 /* RWXVF */
#endif //DEV_P2061_H

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/*
* SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef NVPCF_H
#define NVPCF_H
#include "ctrl/ctrl0000/ctrl0000system.h"
/*
* Definitions for the dynamic params table.
*/
#define NVPCF0100_CTRL_DYNAMIC_TABLE_1X_VERSION (0x10)
#define NVPCF0100_CTRL_DYNAMIC_TABLE_1X_ENTRY_SIZE (4U)
//
// This is set to 32UL in windows NVPCF driver. Set it to 2UL which is good
// enough for now to save space
//
#define NVPCF0100_CTRL_DYNAMIC_TABLE_1X_ENTRY_MAX (2UL)
#define NVPCF0100_CTRL_DYNAMIC_TABLE_1X_INPUT_CMD_GET_TPP (0x04)
/*
* Dynamic Params Table Header, v1.x.
*/
typedef struct
{
NvU8 version;
NvU8 size;
//
// Number of entries in the entire table.
//
NvU8 entryCnt;
NvU8 reserved;
} NVPCF0100_CTRL_DYNAMIC_TABLE_1X_HEADER,
*PNVPCF0100_CTRL_DYNAMIC_TABLE_1X_HEADER;
/*
* Define the dynamic params table header and entries used by the ACPI call.
*/
typedef struct
{
NVPCF0100_CTRL_DYNAMIC_TABLE_1X_HEADER header;
NvU32 entries[NVPCF0100_CTRL_DYNAMIC_TABLE_1X_ENTRY_MAX];
} CONTROLLER_DYNAMIC_TABLE_1X_ACPI,
*PCONTROLLER_DYNAMIC_TABLE_1X_ACPI;
/*!
* Config DSM NVPCF 2x version specific defines
*/
#define NVPCF_DYNAMIC_PARAMS_20_VERSION (0x20)
#define NVPCF_DYNAMIC_PARAMS_21_VERSION (0x21)
#define NVPCF_DYNAMIC_PARAMS_2X_HEADER_SIZE_05 (0x05U)
#define NVPCF_DYNAMIC_PARAMS_2X_HEADER_FMT_SIZE_05 ("5b")
#define NVPCF_DYNAMIC_PARAMS_2X_COMMON_SIZE_10 (0x10U)
#define NVPCF_DYNAMIC_PARAMS_2X_COMMON_FMT_SIZE_10 ("4d")
#define NVPCF_DYNAMIC_PARAMS_2X_ENTRY_SIZE_1C (0x1CU)
#define NVPCF_DYNAMIC_PARAMS_2X_ENTRY_FMT_SIZE_1C ("7d")
#define NVPCF_DYNAMIC_PARAMS_2X_ENTRY_MAX (8)
// Power unit used, 125 milli-watts
#define NVPCF_DYNAMIC_PARAMS_2X_POWER_UNIT_MW (125)
/*!
* Dynamic params header, unpacked.
*/
typedef struct
{
/*
* Dynamic params table Version.
*/
NvU32 version;
/*
* Size of dynamic params table header in bytes.
*/
NvU32 headerSize;
/*
* Size of global/common entry in bytes.
*/
NvU32 commonSize;
/*
* Size of each controller entry in bytes.
*/
NvU32 entrySize;
/*
* Number of controller entries.
*/
NvU32 entryCount;
} DYNAMIC_PARAMS_HEADER_2X;
/*!
* Dynamic params table global/common, unpacked.
*/
typedef struct
{
NvU32 param0;
NvU32 param1;
NvU32 param2;
NvU32 param3;
} DYNAMIC_PARAMS_COMMON_2X;
/*!
* Dynamic params table controller entry, unpacked.
*/
typedef struct
{
NvU32 param0;
NvU32 param1;
NvU32 param2;
NvU32 param3;
NvU32 param4;
NvU32 param5;
NvU32 param6;
} DYNAMIC_PARAMS_ENTRY_2X;
/*!
* Dynamic params table header, packed.
*/
typedef struct
{
NvU8 version;
NvU8 headerSize;
NvU8 commonSize;
NvU8 entrySize;
NvU8 entryCount;
} DYNAMIC_PARAMS_HEADER_2X_PACKED;
/*!
* Dynamic params table global/common, packed.
*/
typedef struct
{
NvU32 param0;
NvU32 param1;
NvU32 param2;
NvU32 param3;
} DYNAMIC_PARAMS_COMMON_2X_PACKED;
/*!
* Dynamic params table controller entry, packed.
*/
typedef struct
{
NvU32 param0;
NvU32 param1;
NvU32 param2;
NvU32 param3;
NvU32 param4;
NvU32 param5;
NvU32 param6;
} DYNAMIC_PARAMS_ENTRY_2X_PACKED;
// Input Commands (Input Param0)
#define NVPCF_DYNAMIC_PARAMS_COMMON_2X_INPUT_PARAM0_CMD 1:0
#define NVPCF_DYNAMIC_PARAMS_COMMON_2X_INPUT_PARAM0_CMD_GET (0)
#define NVPCF_DYNAMIC_PARAMS_COMMON_2X_INPUT_PARAM0_CMD_SET (1)
//
// Input Command 0 (Get Controller Parameters)
//
// Global/Common Entry, Output Param0
#define NVPCF_DYNAMIC_PARAMS_COMMON_2X_OUTPUT_PARAM0_CMD0_CTGP_AC_OFFSET 15:0
#define NVPCF_DYNAMIC_PARAMS_COMMON_2X_OUTPUT_PARAM0_CMD0_CTGP_DC_OFFSET 31:16
// Controller Entry, Output Param0
#define NVPCF_DYNAMIC_PARAMS_ENTRY_2X_OUTPUT_PARAM0_CMD0_IDX 7:0
#define NVPCF_DYNAMIC_PARAMS_ENTRY_2X_OUTPUT_PARAM0_CMD0_DISABLE_AC 8:8
#define NVPCF_DYNAMIC_PARAMS_ENTRY_2X_OUTPUT_PARAM0_CMD0_DISABLE_DC 9:9
// Controller Entry, Output Params1
#define NVPCF_DYNAMIC_PARAMS_ENTRY_2X_OUTPUT_PARAM1_CMD0_SIGNED0 15:0
#define NVPCF_DYNAMIC_PARAMS_ENTRY_2X_OUTPUT_PARAM1_CMD0_SIGNED1 31:16
// Controller Entry, Output Params2
#define NVPCF_DYNAMIC_PARAMS_ENTRY_2X_OUTPUT_PARAM2_CMD0_SIGNED0 15:0
#define NVPCF_DYNAMIC_PARAMS_ENTRY_2X_OUTPUT_PARAM2_CMD0_SIGNED1 31:16
// Controller Entry, Output Params3
#define NVPCF_DYNAMIC_PARAMS_ENTRY_2X_OUTPUT_PARAM3_CMD0_SIGNED0 15:0
#define NVPCF_DYNAMIC_PARAMS_ENTRY_2X_OUTPUT_PARAM3_CMD0_SIGNED1 31:16
#endif // NVPCF_H

10
src/nvidia/kernel/inc/objrpc.h
View File

@@ -45,6 +45,13 @@ typedef struct _object_vgpu OBJVGPU, *POBJVGPU;
#include "g_rpc_hal.h" // For RPC_HAL_IFACES
#include "g_rpc_odb.h" // For RPC_HAL_IFACES
#define RPC_HISTORY_DEPTH 8
typedef struct RpcHistoryEntry
{
NvU32 function;
NvU32 data[3];
} RpcHistoryEntry;
struct OBJRPC{
OBJECT_BASE_DEFINITION(RPC);
@@ -71,6 +78,9 @@ struct OBJRPC{
struct _message_queue_info *pMessageQueueInfo;
RmPhysAddr messageQueuePhysMem;
RpcHistoryEntry rpcHistory[RPC_HISTORY_DEPTH];
NvU32 rpcHistoryCurrent;
};
//

4
src/nvidia/kernel/inc/vgpu/rpc.h
View File

@@ -108,7 +108,7 @@ static inline void NV_RM_RPC_SIM_UPDATE_DISP_CHANNEL_INFO(OBJGPU *pGpu, ...) { r
\
root_alloc_params.hClient = hclient; \
\
if (!IsT234D(pGpu)) \
if (!IsT234DorBetter(pGpu)) \
{ \
RmClient *pClient = NULL; \
\
@@ -165,7 +165,7 @@ static inline void NV_RM_RPC_SIM_UPDATE_DISP_CHANNEL_INFO(OBJGPU *pGpu, ...) { r
&& (!(IS_VIRTUAL_WITH_SRIOV(pGpu) && \
!gpuIsWarBug200577889SriovHeavyEnabled(pGpu) && \
!NV_IS_MODS))) { \
if (IS_GSP_CLIENT(pGpu) && IsT234D(pGpu)) \
if (IS_GSP_CLIENT(pGpu) && IsT234DorBetter(pGpu)) \
{ \
RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); \
NV_MEMORY_LIST_ALLOCATION_PARAMS listAllocParams = {0}; \

17
src/nvidia/kernel/inc/vgpu/rpc_global_enums.h
View File

@@ -197,6 +197,14 @@ enum {
X(RM, PMA_SCRUBBER_SHARED_BUFFER_GUEST_PAGES_OPERATION) //188
X(RM, CTRL_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK) //189
X(RM, SET_SYSMEM_DIRTY_PAGE_TRACKING_BUFFER) //190
X(RM, CTRL_SUBDEVICE_GET_P2P_CAPS) // 191
X(RM, CTRL_BUS_SET_P2P_MAPPING) // 192
X(RM, CTRL_BUS_UNSET_P2P_MAPPING) // 193
X(RM, CTRL_FLA_SETUP_INSTANCE_MEM_BLOCK) // 194
X(RM, CTRL_GPU_MIGRATABLE_OPS) // 195
X(RM, CTRL_GET_TOTAL_HS_CREDITS) // 196
X(RM, CTRL_GET_HS_CREDITS) // 197
X(RM, CTRL_SET_HS_CREDITS) // 198
X(RM, NUM_FUNCTIONS) //END
#ifdef DEFINING_X_IN_RPC_GLOBAL_ENUMS_H
};
@@ -228,6 +236,15 @@ enum {
E(PERF_BRIDGELESS_INFO_UPDATE) // 0x100f
E(VGPU_CONFIG) // 0x1010
E(DISPLAY_MODESET) // 0x1011
E(EXTDEV_INTR_SERVICE) // 0x1012
E(NVLINK_INBAND_RECEIVED_DATA_256) // 0x1013
E(NVLINK_INBAND_RECEIVED_DATA_512) // 0x1014
E(NVLINK_INBAND_RECEIVED_DATA_1024) // 0x1015
E(NVLINK_INBAND_RECEIVED_DATA_2048) // 0x1016
E(NVLINK_INBAND_RECEIVED_DATA_4096) // 0x1017
E(TIMED_SEMAPHORE_RELEASE) // 0x1018
E(NVLINK_IS_GPU_DEGRADED) // 0x1019
E(PFM_REQ_HNDLR_STATE_SYNC_CALLBACK) // 0x101a
E(NUM_EVENTS) // END
#ifdef DEFINING_E_IN_RPC_GLOBAL_ENUMS_H
};

19
src/nvidia/kernel/inc/vgpu/rpc_headers.h
View File

@@ -206,6 +206,19 @@ typedef enum
UVM_PAGING_CHANNEL_VASPACE_FREE,
} UVM_PAGING_CHANNEL_VASPACE_OPERATION;
typedef struct VIRTUAL_DISPLAY_GET_MAX_RESOLUTION_PARAMS
{
NvU32 headIndex;
NvU32 maxHResolution;
NvU32 maxVResolution;
} VIRTUAL_DISPLAY_GET_MAX_RESOLUTION_PARAMS;
typedef struct VIRTUAL_DISPLAY_GET_NUM_HEADS_PARAMS
{
NvU32 numHeads;
NvU32 maxNumHeads;
} VIRTUAL_DISPLAY_GET_NUM_HEADS_PARAMS;
/*
* Maximum guest pages that can be mapped for UVM method stream
@@ -214,4 +227,10 @@ typedef enum
#define PMA_SCRUBBER_SHARED_BUFFER_MAX_GUEST_PAGES_v1F_0C 500
/*
* Maximum number of SMs that can be read in one RPC call to get error states
*/
#define VGPU_RPC_CTRL_DEBUG_READ_ALL_SM_ERROR_STATES_PER_RPC_v21_06 80
#endif // __vgpu_rpc_nv_headers_h__

13
src/nvidia/kernel/inc/vgpu/sdk-structures.h
View File

@@ -26,7 +26,6 @@
#define _RPC_SDK_STRUCTURES_H_
#include <ctrl/ctrl83de.h>
#include <ctrl/ctrla083.h>
#include <ctrl/ctrlc36f.h>
#include <ctrl/ctrlc637.h>
#include <ctrl/ctrl0000/ctrl0000system.h>
@@ -63,6 +62,7 @@
#include <class/clc67e.h>
#include "rpc_headers.h"
#include "nvctassert.h"
#include "nv_vgpu_types.h"
@@ -110,6 +110,9 @@ typedef struct vmiopd_SM_info {
#define NV0000_CTRL_P2P_CAPS_INDEX_TABLE_SIZE_v15_02 8
#define NV0000_CTRL_P2P_CAPS_INDEX_TABLE_SIZE_v1F_0D 9
#define NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS_v21_02 32
#define VM_UUID_SIZE_v21_02 16
#define NV2080_CTRL_FB_FS_INFO_MAX_QUERIES_v1A_1D 96
#define NV2080_CTRL_FB_FS_INFO_MAX_QUERY_SIZE_v1A_1D 24
#define NV2080_CTRL_GRMGR_GR_FS_INFO_MAX_QUERIES_v1A_1D 96
@@ -118,6 +121,7 @@ typedef struct vmiopd_SM_info {
#define NV0080_CTRL_GR_INFO_MAX_SIZE_1B_04 (0x0000002C)
#define NV0080_CTRL_GR_INFO_MAX_SIZE_1C_01 (0x00000030)
#define NV0080_CTRL_GR_INFO_MAX_SIZE_1E_02 (0x00000032)
#define NV0080_CTRL_GR_INFO_MAX_SIZE_21_01 (0x00000033)
#define NV2080_CTRL_INTERNAL_GR_MAX_ENGINES_1B_04 8
#define NV2080_CTRL_INTERNAL_GR_MAX_SM_v1B_05 256
#define NV2080_CTRL_INTERNAL_GR_MAX_SM_v1E_03 240
@@ -126,8 +130,13 @@ typedef struct vmiopd_SM_info {
#define NV2080_CTRL_INTERNAL_MAX_TPC_PER_GPC_COUNT_v1C_03 10
#define NV2080_CTRL_INTERNAL_GR_MAX_GPC_v1C_03 12
#define NV2080_CTRL_MC_GET_STATIC_INTR_TABLE_MAX_v1E_09 32
#define NV2080_CTRL_PERF_GPUMON_SAMPLE_COUNT_PERFMON_UTIL_v1F_0E 100
#define NV2080_CTRL_PERF_GPUMON_SAMPLE_COUNT_PERFMON_UTIL_v1F_0E 72
#define NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE__SIZE_v20_04 6
#define NV2080_CTRL_MIGRATABLE_OPS_ARRAY_MAX_v21_07 50
#define NVB0CC_MAX_CREDIT_INFO_ENTRIES_v21_08 63
#define NV2080_CTRL_MAX_PCES_v21_0A 32
#define NV2080_CTRL_CE_CAPS_TBL_SIZE_v21_0A 2
#define NV2080_ENGINE_TYPE_COPY_SIZE_v21_0A 10
// Defined this intermediate RM-RPC structure for making RPC call from Guest as
// we have the restriction of passing max 4kb of data to plugin and the

42
src/nvidia/kernel/inc/vgpu/vgpu_events.h
View File

@@ -35,14 +35,11 @@
#include "rmconfig.h"
#include "ctrl/ctrla083.h"
#include "ctrl/ctrlc637.h"
#include "ctrl/ctrl2080/ctrl2080bios.h"
#include "ctrl/ctrl2080/ctrl2080fb.h"
#include "ctrl/ctrl2080/ctrl2080gpu.h"
#include "ctrl/ctrl2080/ctrl2080gr.h"
#include "ctrl/ctrl0080/ctrl0080nvjpg.h"
#include "vgpu/rpc_headers.h"
#include "gpu/device/device.h"
@@ -51,7 +48,8 @@
#include "kernel/gpu/mig_mgr/kernel_mig_manager.h"
typedef MC_ENGINE_BITVECTOR *PMC_ENGINE_BITVECTOR;
typedef struct HOST_VGPU_DEVICE HOST_VGPU_DEVICE, KERNEL_HOST_VGPU_DEVICE;
typedef struct HOST_VGPU_DEVICE HOST_VGPU_DEVICE;
typedef struct KERNEL_HOST_VGPU_DEVICE KERNEL_HOST_VGPU_DEVICE;
typedef struct _object_vgpu OBJVGPU, *POBJVGPU;
// Create and destroy OBJVGPU *object
@@ -70,36 +68,18 @@ void vgpuInitRegistryOverWrite(OBJGPU *pGpu);
// Get the device pointer from the calling context
Device *vgpuGetCallingContextDevice(OBJGPU *pGpu);
// Stubs for virtualization-disabled builds
static inline NV_STATUS vgpuGetCallingContextHostVgpuDevice(OBJGPU *pGpu, HOST_VGPU_DEVICE **ppHostVgpuDevice)
{
*ppHostVgpuDevice = NULL;
return NV_OK;
}
// Get the host VGPU device pointer from the calling context
NV_STATUS vgpuGetCallingContextHostVgpuDevice(OBJGPU *pGpu, HOST_VGPU_DEVICE **ppHostVgpuDevice);
NV_STATUS vgpuGetCallingContextKernelHostVgpuDevice(OBJGPU *pGpu, KERNEL_HOST_VGPU_DEVICE **ppKernelHostVgpuDevice);
static inline NV_STATUS vgpuGetCallingContextKernelHostVgpuDevice(OBJGPU *pGpu, KERNEL_HOST_VGPU_DEVICE **ppKernelHostVgpuDevice)
{
*ppKernelHostVgpuDevice = NULL;
return NV_OK;
}
// Get the GFID for from the VGPU device of the calling context
NV_STATUS vgpuGetCallingContextGfid(OBJGPU *pGpu, NvU32 *pGfid);
static inline NV_STATUS vgpuGetCallingContextGfid(OBJGPU *pGpu, NvU32 *pGfid)
{
*pGfid = GPU_GFID_PF;
return NV_OK;
}
// Check is the calling context if VGPU plugin
NV_STATUS vgpuIsCallingContextPlugin(OBJGPU *pGpu, NvBool *pIsCallingContextPlugin);
static inline NV_STATUS vgpuIsCallingContextPlugin(OBJGPU *pGpu, NvBool *pIsCallingContextPlugin)
{
*pIsCallingContextPlugin = NV_FALSE;
return NV_OK;
}
static inline NV_STATUS vgpuGetGfidFromDeviceInfo(OBJGPU *pGpu, Device *pDevice, NvU32 *pGfid)
{
*pGfid = GPU_GFID_PF;
return NV_OK;
}
// Get the GFID from DeviceInfo
NV_STATUS vgpuGetGfidFromDeviceInfo(OBJGPU *pGpu, Device *pDevice, NvU32 *pGfid);
// Update Interrupt using shared memory through vGPU
void vgpuUpdateShmIntr(OBJGPU *pGpu, NvU32 offset, NvU32 value, THREAD_STATE_NODE *pThreadState);

69
src/nvidia/kernel/inc/vgpu/vgpu_version.h
View File

@@ -30,12 +30,77 @@
#define RPC_VERSION_FROM_VGX_VERSION(major, minor) ( DRF_NUM(_RPC, _VERSION_NUMBER, _MAJOR, major) | \
DRF_NUM(_RPC, _VERSION_NUMBER, _MINOR, minor))
#define VGX_MAJOR_VERSION_NUMBER 0x20
#define VGX_MINOR_VERSION_NUMBER 0x04
#define VGX_MAJOR_VERSION_NUMBER 0x21
#define VGX_MINOR_VERSION_NUMBER 0x0A
#define VGX_MAJOR_VERSION_NUMBER_VGPU_12_0 0x1A
#define VGX_MINOR_VERSION_NUMBER_VGPU_12_0 0x18
#define VGX_MAJOR_VERSION_NUMBER_VGPU_13_0 0x1C
#define VGX_MINOR_VERSION_NUMBER_VGPU_13_0 0x0A
/**
* This macro have the mapping between internal (RPC) and external version
* and is required to be updated appropriately with every new internal version.
*
* In case a new external version is added, a new entry representing the mapping
* for the external version should be appended. Please note that the external
* version should be updated when both of the following are true:
* 1. The new RPC version update cause a break in migration compatibility.
* 2. This is the first break in migration compatibility after a release.
*/
#define NV_VGPU_GRIDSW_INTERNAL_TO_EXTERNAL_VERSION_MAPPING \
{{0x21, 0x0}, {0x21, 0x0A}, {0x10, 0x1}}, \
{{0x20, 0x0}, {0x20, 0x04}, {0xF, 0x1}}, \
{{0x1F, 0x0}, {0x1F, 0xF}, {0xE, 0x1}}, \
{{0x1E, 0x0}, {0x1E, 0xE}, {0xD, 0x1}}, \
{{0x1D, 0x0}, {0x1D, 0x6}, {0xC, 0x1}}, \
{{0x1C, 0x0}, {0x1C, 0xA}, {0xB, 0x1}}, \
{{0x1C, 0xB}, {0x1C, 0xC}, {0xB, 0x2}}, \
{{0x1B, 0x0}, {0x1B, 0x5}, {0xA, 0x1}}, \
{{0x1A, 0x0}, {0x1A, 0x18}, {0x9, 0x1}}, \
{{0x1A, 0x19}, {0x1A, 0x24}, {0x9, 0x2}}, \
{{0x19, 0x0}, {0x19, 0x1}, {0x8, 0x1}}, \
{{0x18, 0x0}, {0x18, 0x14},{0x7, 0x1}}, \
{{0x18, 0x15}, {0x18, 0x16},{0x7, 0x2}}, \
{{0x17, 0x0}, {0x17, 0x6}, {0x6, 0x1}}, \
{{0x16, 0x0}, {0x16, 0x6}, {0x5, 0x1}}, \
{{0x16, 0x7}, {0x16, 0x7}, {0x5, 0x2}}
/*
* Internal Versioning
*/
#define NV_VGPU_GRIDSW_NUMBER_INTERNAL_MAJOR 63:32
#define NV_VGPU_GRIDSW_NUMBER_INTERNAL_MINOR 31:0
#define GRIDSW_VERSION_INTERNAL(major, minor) (DRF_NUM64(_VGPU, _GRIDSW_NUMBER_INTERNAL, _MAJOR, major) | \
DRF_NUM64(_VGPU, _GRIDSW_NUMBER_INTERNAL, _MINOR, minor))
// The NV_VGPU_GRIDSW_VERSION_MIN_SUPPORTED_INTERNAL macros are auto-generated using the value from rpc-structures.def file.
#define AUTOGENERATE_RPC_MIN_SUPPORTED_VERSION_INFORMATION
#include "g_rpc-structures.h"
#undef AUTOGENERATE_RPC_MIN_SUPPORTED_VERSION_INFORMATION
/*
* Versioning exposed externally
*/
#define NV_VGPU_GRIDSW_NUMBER_EXTERNAL_MAJOR 31:16
#define NV_VGPU_GRIDSW_NUMBER_EXTERNAL_MINOR 15:0
#define GRIDSW_VERSION_EXTERNAL(major, minor) (DRF_NUM(_VGPU, _GRIDSW_NUMBER_EXTERNAL, _MAJOR, major) | \
DRF_NUM(_VGPU, _GRIDSW_NUMBER_EXTERNAL, _MINOR, minor))
/* WARNING: Should be updated with each vGPU release, if there is a break in
* migration compatibility during the development of that release. */
#define NV_VGPU_MAX_SUPPORTED_GRIDSW_VERSION_EXTERNAL_MAJOR 0x10
#define NV_VGPU_MAX_SUPPORTED_GRIDSW_VERSION_EXTERNAL_MINOR 0x1
/* WARNING: Should be updated with each vGPU release, if minimum supported
* version change on the host.
*/
#define NV_VGPU_MIN_SUPPORTED_GRIDSW_VERSION_EXTERNAL_MAJOR 0x7
#define NV_VGPU_MIN_SUPPORTED_GRIDSW_VERSION_EXTERNAL_MINOR 0x1
#endif // __vgpu_vgpu_version_h__

344
src/nvidia/kernel/vgpu/nv/objvgpu.c Normal file
View File

@@ -0,0 +1,344 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2017-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#include "core/core.h"
#include "os/os.h"
#include "gpu/gpu.h"
#include "vgpu/vgpu_version.h"
#include "gpu/device/device.h"
#include "rmapi/rs_utils.h"
#include "virtualization/hypervisor/hypervisor.h"
#include "virtualization/kernel_vgpu_mgr.h"
#include "nvRmReg.h"
// Create vGpu object and initialize RPC infrastructure
NV_STATUS
vgpuCreateObject
(
OBJGPU *pGpu
)
{
NV_STATUS rmStatus = NV_OK;
return rmStatus;
}
// Free RPC infrastructure and vGpu object
void
vgpuDestructObject
(
OBJGPU *pGpu
)
{
}
// Overwrite registry keys
void
vgpuInitRegistryOverWrite
(
OBJGPU *pGpu
)
{
NvU32 data;
// if "RMFermiBigPageSize" regkey is set explicitly, then don't
// overwrite it.
if (NV_OK != osReadRegistryDword(pGpu,
NV_REG_STR_RM_DISABLE_BIG_PAGE_PER_ADDRESS_SPACE,
&data))
{
NV_PRINTF(LEVEL_INFO, "Overwriting big page size to 64K\n");
osWriteRegistryDword(pGpu,
NV_REG_STR_FERMI_BIG_PAGE_SIZE,
NV_REG_STR_FERMI_BIG_PAGE_SIZE_64KB);
if (IS_VIRTUAL(pGpu))
{
pGpu->setProperty(pGpu, PDB_PROP_GPU_VGPU_BIG_PAGE_SIZE_64K, NV_TRUE);
}
}
NvU32 min = 0, max = 0;
/* Default user provided vGPU supported range is set to be the
* same as per the host */
NvU32 user_min_supported_version
= GRIDSW_VERSION_EXTERNAL(NV_VGPU_MIN_SUPPORTED_GRIDSW_VERSION_EXTERNAL_MAJOR,
NV_VGPU_MIN_SUPPORTED_GRIDSW_VERSION_EXTERNAL_MINOR);
NvU32 user_max_supported_version
= GRIDSW_VERSION_EXTERNAL(NV_VGPU_MAX_SUPPORTED_GRIDSW_VERSION_EXTERNAL_MAJOR,
NV_VGPU_MAX_SUPPORTED_GRIDSW_VERSION_EXTERNAL_MINOR);
if (NV_OK == osReadRegistryDword(pGpu,
NV_REG_STR_RM_SET_VGPU_VERSION_MAX,
&max))
{
/* Override max vGPU supported version */
user_max_supported_version = max;
}
if (NV_OK == osReadRegistryDword(pGpu,
NV_REG_STR_RM_SET_VGPU_VERSION_MIN,
&min))
{
/* Override min vGPU supported version */
user_min_supported_version = min;
}
/* Convey the vGPU range information to the vGPU manager */
kvgpumgrSetHostVgpuVersion(user_min_supported_version, user_max_supported_version);
}
/*
* @brief Gets the calling context's device pointer
*
* @param pGpu OBJGPU pointer
*
* @return Pointer to the calling context's device pointer
*/
Device *
vgpuGetCallingContextDevice
(
OBJGPU *pGpu
)
{
RsResourceRef *pDeviceRef = NULL;
Device *pDevice = NULL;
pDeviceRef = resservGetContextRefByType(classId(Device), NV_TRUE);
if (pDeviceRef != NULL)
{
pDevice = dynamicCast(pDeviceRef->pResource, Device);
}
return pDevice;
}
/*
* @brief Gets the calling context's Host VGPU device pointer
*
* @param pGpu OBJGPU pointer
* @param ppHostVgpuDevice Pointer to pointer to the calling
* context's Host VGPU device pointer
*
* @return Error code
*/
NV_STATUS
vgpuGetCallingContextHostVgpuDevice
(
OBJGPU *pGpu,
HOST_VGPU_DEVICE **ppHostVgpuDevice
)
{
*ppHostVgpuDevice = NULL;
if (IS_GSP_CLIENT(pGpu))
return NV_ERR_NOT_SUPPORTED;
return NV_OK;
}
NV_STATUS
vgpuGetCallingContextKernelHostVgpuDevice
(
OBJGPU *pGpu,
KERNEL_HOST_VGPU_DEVICE **ppKernelHostVgpuDevice
)
{
Device *pDevice;
if (RMCFG_FEATURE_PLATFORM_GSP)
return NV_ERR_NOT_SUPPORTED;
*ppKernelHostVgpuDevice = NULL;
// This check is needed to handle cases where this function was called
// without client (for example, during adapter initialization).
if (resservGetTlsCallContext() == NULL)
{
return NV_OK;
}
pDevice = vgpuGetCallingContextDevice(pGpu);
if (pDevice == NULL)
{
// There are several places where this function can be called without TLS call context
// in SRIOV-heavy mode. Return error only for SRIOV-full.
NV_ASSERT_OR_RETURN(!gpuIsSriovEnabled(pGpu) || IS_SRIOV_HEAVY(pGpu), NV_ERR_OBJECT_NOT_FOUND);
return NV_OK;
}
*ppKernelHostVgpuDevice = pDevice->pKernelHostVgpuDevice;
NV_ASSERT_OR_RETURN((pDevice->pKernelHostVgpuDevice != NULL) ==
!!(pDevice->deviceAllocFlags & NV_DEVICE_ALLOCATION_FLAGS_HOST_VGPU_DEVICE),
NV_ERR_INVALID_STATE);
return NV_OK;
}
/*
* @brief Gets the calling context's GFID
* gsp-rm: when the vgpu plugin rpcs to gsp-rm, gfid is stored in an unused
* field, pProcessToken.
* cpu-rm: Retrieve from TLS a host vgpu device, and then gfid from it.
*
* @param pGpu OBJGPU pointer
* @param pGfid calling context's GFID pointer
*
* @return Error code
*/
NV_STATUS
vgpuGetCallingContextGfid
(
OBJGPU *pGpu,
NvU32 *pGfid
)
{
GFID_ALLOC_STATUS gfidState;
*pGfid = GPU_GFID_PF;
if (!gpuIsSriovEnabled(pGpu))
{
return NV_OK;
}
if (RMCFG_FEATURE_PLATFORM_GSP)
{
CALL_CONTEXT *pTls = resservGetTlsCallContext();
if (pTls)
{
*pGfid = (NvU32)(NvU64)pTls->secInfo.pProcessToken;
}
}
else
{
KERNEL_HOST_VGPU_DEVICE *pKernelHostVgpuDevice;
NV_ASSERT_OK_OR_RETURN(vgpuGetCallingContextKernelHostVgpuDevice(pGpu, &pKernelHostVgpuDevice));
if (pKernelHostVgpuDevice != NULL)
{
*pGfid = pKernelHostVgpuDevice->gfid;
}
}
// work around for bug 3432243 where this is called before setting gfid.
if (IS_GFID_PF(*pGfid))
return NV_OK;
NV_ASSERT_OK_OR_RETURN(gpuGetGfidState(pGpu, *pGfid, &gfidState));
// Allow invalidated state to be retreived as GFID is still active in system
NV_ASSERT_OR_RETURN((gfidState != GFID_FREE), NV_ERR_INVALID_STATE);
return NV_OK;
}
NV_STATUS
vgpuGetGfidFromDeviceInfo
(
OBJGPU *pGpu,
Device *pDevice,
NvU32 *pGfid
)
{
KERNEL_HOST_VGPU_DEVICE *pKernelHostVgpuDevice;
if (RMCFG_FEATURE_PLATFORM_GSP)
return NV_ERR_NOT_SUPPORTED;
*pGfid = GPU_GFID_PF;
NV_ASSERT_OR_RETURN(pDevice != NULL, NV_ERR_INVALID_ARGUMENT);
if (!gpuIsSriovEnabled(pGpu))
{
return NV_OK;
}
// TODO: fix the calling sites in VAB and P2P (GPUSWSEC-783)
NV_ASSERT_OR_RETURN(!RMCFG_FEATURE_PLATFORM_GSP, NV_ERR_NOT_SUPPORTED);
// Get the HOST_VGPU_DEVICE from hClient
pKernelHostVgpuDevice = pDevice->pKernelHostVgpuDevice;
NV_ASSERT_OR_RETURN((pKernelHostVgpuDevice != NULL) ==
!!(pDevice->deviceAllocFlags & NV_DEVICE_ALLOCATION_FLAGS_HOST_VGPU_DEVICE),
NV_ERR_INVALID_STATE);
if (pKernelHostVgpuDevice != NULL)
{
GFID_ALLOC_STATUS gfidState;
*pGfid = pKernelHostVgpuDevice->gfid;
NV_ASSERT_OK_OR_RETURN(gpuGetGfidState(pGpu, *pGfid, &gfidState));
NV_ASSERT_OR_RETURN((gfidState != GFID_FREE), NV_ERR_INSUFFICIENT_RESOURCES);
}
return NV_OK;
}
NV_STATUS
vgpuIsCallingContextPlugin
(
OBJGPU *pGpu,
NvBool *pIsCallingContextPlugin
)
{
Device *pDevice = NULL;
*pIsCallingContextPlugin = NV_FALSE;
if (!gpuIsSriovEnabled(pGpu))
{
return NV_OK;
}
// This check is needed to handle cases where this function was called
// without client (for example, during adapter initialization).
if (resservGetTlsCallContext() == NULL)
{
return NV_OK;
}
pDevice = vgpuGetCallingContextDevice(pGpu);
if (pDevice == NULL)
{
// There are several places where this function can be called without TLS call context
// in SRIOV-heavy mode. Return error only for SRIOV-full.
NV_ASSERT_OR_RETURN(!gpuIsSriovEnabled(pGpu) || IS_SRIOV_HEAVY(pGpu), NV_ERR_OBJECT_NOT_FOUND);
return NV_OK;
}
if (pDevice->deviceAllocFlags & NV_DEVICE_ALLOCATION_FLAGS_PLUGIN_CONTEXT)
{
if (!RMCFG_FEATURE_PLATFORM_GSP)
NV_ASSERT_OR_RETURN(pDevice->pKernelHostVgpuDevice, NV_ERR_INVALID_STATE);
*pIsCallingContextPlugin = NV_TRUE;
}
return NV_OK;
}

105
src/nvidia/kernel/vgpu/nv/rpc.c
View File

@@ -42,6 +42,7 @@
#include "resserv/rs_server.h"
#include "rmapi/alloc_size.h"
#include "rmapi/rs_utils.h"
#include "rmapi/rmapi_utils.h"
#include "rmapi/client_resource.h"
#include "gpu/gsp/kernel_gsp.h"
#include "gpu/mem_mgr/mem_mgr.h"
@@ -270,9 +271,9 @@ static NV_STATUS _issueRpcLarge
//
// Copy the initial buffer
// Temporary black magic WAR for bug 3594082: reducing the size by 1
// Temporary black magic WAR for bug 3594082: reducing the size by 2
//
entryLength = NV_MIN(bufSize, pRpc->maxRpcSize - 1);
entryLength = NV_MIN(bufSize, pRpc->maxRpcSize - 2);
if ((NvU8 *)vgpu_rpc_message_header_v != pBuf8)
portMemCopy(vgpu_rpc_message_header_v, entryLength, pBuf8, entryLength);
@@ -299,9 +300,9 @@ static NV_STATUS _issueRpcLarge
//
// Copy the remaining buffers
// Temporary black magic WAR for bug 3594082: reducing the size by 1
// Temporary black magic WAR for bug 3594082: reducing the size by 2
//
entryLength = pRpc->maxRpcSize - sizeof(rpc_message_header_v) - 1;
entryLength = pRpc->maxRpcSize - sizeof(rpc_message_header_v) - 2;
while (remainingSize != 0)
{
if (entryLength > remainingSize)
@@ -651,14 +652,22 @@ NV_STATUS RmRpcSetGuestSystemInfo(OBJGPU *pGpu, OBJRPC *pRpc)
NvS32 message_buffer_remaining;
NvU32 data_len;
if (pGpuMgr->numGpuHandles == 0)
{
rpcVgxVersion.majorNum = 0;
rpcVgxVersion.minorNum = 0;
}
//
// Skip RPC version handshake if we've already done it on one GPU.
//
// For GSP: Multi GPU setup can have pre-Turing GPUs
// and GSP offload is disabled for all pre-Turing GPUs.
// Don't skip RPC version handshake if rpcVgxVersion.majorNum is not set
// Don't skip RPC version handshake for GSP_CLIENT or if VGPU-GSP plugin offload is enabled.
// There are different GSPs/plugins for different GPUs and we need to have a handshake with all of them.
//
if (pGpuMgr->numGpuHandles > 1)
if (pGpuMgr->numGpuHandles > 1 && !IS_GSP_CLIENT(pGpu) && !(IS_VIRTUAL(pGpu) && IS_VGPU_GSP_PLUGIN_OFFLOAD_ENABLED(pGpu)))
{
if (rpcVgxVersion.majorNum != 0)
{
@@ -667,7 +676,7 @@ NV_STATUS RmRpcSetGuestSystemInfo(OBJGPU *pGpu, OBJRPC *pRpc)
gpuGetInstance(pGpu));
goto skip_ver_handshake;
}
else if (!IS_GSP_CLIENT(pGpu))
else
{
status = NV_ERR_GENERIC;
NV_PRINTF(LEVEL_ERROR,
@@ -677,9 +686,6 @@ NV_STATUS RmRpcSetGuestSystemInfo(OBJGPU *pGpu, OBJRPC *pRpc)
}
}
rpcVgxVersion.majorNum = 0;
rpcVgxVersion.minorNum = 0;
message_buffer_remaining = pRpc->maxRpcSize - (sizeof(rpc_message_header_v) +
sizeof(rpc_set_guest_system_info_v));
@@ -783,6 +789,15 @@ NV_STATUS RmRpcSetGuestSystemInfo(OBJGPU *pGpu, OBJRPC *pRpc)
if (status == NV_OK)
{
if (rpcVgxVersion.majorNum != 0)
{
if (rpcVgxVersion.majorNum != rpc_message->set_guest_system_info_v.vgxVersionMajorNum ||
rpcVgxVersion.minorNum != rpc_message->set_guest_system_info_v.vgxVersionMinorNum)
{
return NV_ERR_INVALID_STATE;
}
}
rpcVgxVersion.majorNum = rpc_message->set_guest_system_info_v.vgxVersionMajorNum;
rpcVgxVersion.minorNum = rpc_message->set_guest_system_info_v.vgxVersionMinorNum;
}
@@ -1005,12 +1020,6 @@ NV_STATUS rpcGetStaticInfo_v20_01(OBJGPU *pGpu, OBJRPC *pRpc)
return status;
}
NV_STATUS rpcGetStaticInfo_v20_04(OBJGPU *pGpu, OBJRPC *pRpc)
{
NV_STATUS status = NV_OK;
return status;
}
NV_STATUS rpcGetGspStaticInfo_v14_00(OBJGPU *pGpu, OBJRPC *pRpc)
{
NV_STATUS status = NV_ERR_NOT_SUPPORTED;
@@ -1283,6 +1292,18 @@ NV_STATUS rpcGspSetSystemInfo_v17_00
{
clSyncWithGsp(pCl, rpcInfo);
}
// Fill in the cached ACPI method data
rpcInfo->acpiMethodData = pGpu->acpiMethodData;
// Fill in ASPM related GPU flags
rpcInfo->bGpuBehindBridge = pGpu->getProperty(pGpu, PDB_PROP_GPU_BEHIND_BRIDGE);
rpcInfo->bUpstreamL0sUnsupported = pGpu->getProperty(pGpu, PDB_PROP_GPU_UPSTREAM_PORT_L0S_UNSUPPORTED);
rpcInfo->bUpstreamL1Unsupported = pGpu->getProperty(pGpu, PDB_PROP_GPU_UPSTREAM_PORT_L1_UNSUPPORTED);
rpcInfo->bUpstreamL1PorSupported = pGpu->getProperty(pGpu, PDB_PROP_GPU_UPSTREAM_PORT_L1_POR_SUPPORTED);
rpcInfo->bUpstreamL1PorMobileOnly = pGpu->getProperty(pGpu, PDB_PROP_GPU_UPSTREAM_PORT_L1_POR_MOBILE_ONLY);
rpcInfo->upstreamAddressValid = pGpu->gpuClData.upstreamPort.addr.valid;
status = _issueRpcAsync(pGpu, pRpc);
}
@@ -1502,6 +1523,9 @@ NV_STATUS rpcRmApiControl_GSP
NvU32 serializedSize = 0;
NvU32 origParamsSize = paramsSize;
NvU32 gpuMaskRelease = 0;
NvU32 ctrlFlags = 0;
NvU32 ctrlAccessRight = 0;
NvBool bCacheable;
if (!rmDeviceGpuLockIsOwner(pGpu->gpuInstance))
{
@@ -1513,6 +1537,9 @@ NV_STATUS rpcRmApiControl_GSP
GPU_LOCK_FLAGS_SAFE_LOCK_UPGRADE, RM_LOCK_MODULES_RPC, &gpuMaskRelease));
}
rmapiutilGetControlInfo(cmd, &ctrlFlags, &ctrlAccessRight);
bCacheable = rmapiControlIsCacheable(ctrlFlags, ctrlAccessRight, NV_TRUE);
// Attempt to calculate the serialized size of the param struct using FINN.
serializedSize = FinnRmApiGetSerializedSize(interface_id, message_id, pParamStructPtr);
@@ -1522,6 +1549,14 @@ NV_STATUS rpcRmApiControl_GSP
{
// Allocate twice the amount to account for the return buffer
paramsSize = 2 * serializedSize;
NV_ASSERT_OR_RETURN(!bCacheable, NV_ERR_INVALID_STATE);
}
if (bCacheable)
{
status = rmapiControlCacheGet(hClient, hObject, cmd, pParamStructPtr, paramsSize);
if (status == NV_OK)
goto done;
}
// Initialize these values now that paramsSize is known
@@ -1534,10 +1569,11 @@ NV_STATUS rpcRmApiControl_GSP
rpcWriteCommonHeader(pGpu, pRpc, NV_VGPU_MSG_FUNCTION_GSP_RM_CONTROL, rpc_params_size),
done);
rpc_params->hClient = hClient;
rpc_params->hObject = hObject;
rpc_params->cmd = cmd;
rpc_params->paramsSize = paramsSize;
rpc_params->hClient = hClient;
rpc_params->hObject = hObject;
rpc_params->cmd = cmd;
rpc_params->paramsSize = paramsSize;
rpc_params->copyOutOnError = !!(ctrlFlags & RMCTRL_FLAGS_COPYOUT_ON_ERROR);
// If we have a big payload control, we need to make a local copy...
if (message_buffer_remaining < paramsSize)
@@ -1619,8 +1655,20 @@ NV_STATUS rpcRmApiControl_GSP
status = _issueRpcAndWait(pGpu, pRpc);
}
//
// At this point we have:
// status: The status of the RPC transfer. If NV_OK, we got something back
// rpc_params->status: Status returned by the actual ctrl handler on GSP
//
if (status == NV_OK)
{
// Skip copyout if we got an error from the GSP control handler
if (rpc_params->status != NV_OK && !rpc_params->copyOutOnError)
{
status = rpc_params->status;
goto done;
}
// If FINN was used to serialize the params, they must be deserialized on the way back,
// otherwise do a flat memcpy
if (serializedSize != 0)
@@ -1649,13 +1697,24 @@ NV_STATUS rpcRmApiControl_GSP
if (rpc_params->status != NV_OK)
status = rpc_params->status;
else if (bCacheable)
NV_ASSERT_OK(rmapiControlCacheSet(hClient, hObject, cmd, rpc_params->params, paramsSize));
}
if (status != NV_OK)
{
NV_PRINTF(LEVEL_WARNING,
"GspRmControl failed: hClient=0x%08x; hObject=0x%08x; cmd=0x%08x; paramsSize=0x%08x; paramsStatus=0x%08x; status=0x%08x\n",
hClient, hObject, cmd, paramsSize, rpc_params->status, status);
NvBool bSilentErrorReport = NV_FALSE;
switch (status)
{
case NV_ERR_NOT_SUPPORTED:
case NV_ERR_OBJECT_NOT_FOUND:
bSilentErrorReport = NV_TRUE;
break;
}
NV_PRINTF_COND(bSilentErrorReport, LEVEL_INFO, LEVEL_WARNING,
"GspRmControl failed: hClient=0x%08x; hObject=0x%08x; cmd=0x%08x; paramsSize=0x%08x; paramsStatus=0x%08x; status=0x%08x\n",
hClient, hObject, cmd, paramsSize, rpc_params->status, status);
}
done: