NVIDIA/open-gpu-kernel-modules
1
0
Fork 0
mirror of https://github.com/NVIDIA/open-gpu-kernel-modules.git synced 2026-02-04 07:10:19 +00:00
Code Issues Packages Projects Releases Wiki Activity

520.61.05

Browse Source
This commit is contained in:
Andy Ritger
2022-10-10 14:59:24 -07:00
parent fe0728787f
commit 90eb10774f
758 changed files with 88383 additions and 26493 deletions
Download Patch File Download Diff File Expand all files Collapse all files

31
src/common/nvswitch/kernel/flcn/flcnqueue_nvswitch.c
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2018-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2018-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -1405,29 +1405,14 @@ _flcnQueueCmdPostNonBlocking_IMPL
}
// Falcon must be in a ready state before commands may be submitted.
if (!pFlcn->bOSReady)
status = soeWaitForInitAck_HAL(device, (PSOE)pFlcn->pFlcnable);
if (status != NV_OK)
{
if (pFlcn->engineTag != ENG_TAG_SOE) {
NVSWITCH_PRINT(device, ERROR,
"%s: FLCN not ready for command processing\n",
__FUNCTION__);
return NV_ERR_INVALID_STATE;
}
else
{
SOE *pSoe = (PSOE)pFlcn->pFlcnable;
status = soeWaitForInitAck(device, pSoe);
if (status != NV_OK || !pFlcn->bOSReady)
{
NVSWITCH_PRINT(device, ERROR,
"%s: SOE not ready for command processing\n",
__FUNCTION__);
NVSWITCH_ASSERT(0);
return status;
}
}
NVSWITCH_PRINT(device, ERROR,
"%s: SOE not ready for command processing\n",
__FUNCTION__);
NVSWITCH_ASSERT(0);
return status;
}
// Sanity check the command input.

9
src/common/nvswitch/kernel/inc/common_nvswitch.h
View File

@@ -389,6 +389,9 @@ struct nvswitch_device
// List of client events
NVListRec client_events_list;
// To be removed once newer vbios is on TOT.
NvBool bIsNvlinkVbiosTableVersion2;
};
#define NVSWITCH_IS_DEVICE_VALID(device) \
@@ -485,6 +488,7 @@ typedef struct NVSWITCH_TIMEOUT
#define NVSWITCH_INTERVAL_1MSEC_IN_NS 1000000LL
#define NVSWITCH_INTERVAL_5MSEC_IN_NS 5000000LL
#define NVSWITCH_INTERVAL_1SEC_IN_NS 1000000000LL
#define NVSWITCH_INTERVAL_4SEC_IN_NS 4000000000LL
#define NVSWITCH_HEARTBEAT_INTERVAL_NS NVSWITCH_INTERVAL_1SEC_IN_NS
@@ -505,6 +509,7 @@ do \
#define NVSWITCH_SET_CAP(tbl,cap,field) ((tbl[((1?cap##field)>=cap##_TBL_SIZE) ? 0/0 : (1?cap##field)]) |= (0?cap##field))
NvBool nvswitch_is_lr10_device_id(NvU32 device_id);
NvBool nvswitch_is_ls10_device_id(NvU32 device_id);
NvU32 nvswitch_reg_read_32(nvswitch_device *device, NvU32 offset);
void nvswitch_reg_write_32(nvswitch_device *device, NvU32 offset, NvU32 data);
@@ -529,6 +534,10 @@ void nvswitch_setup_link_loopback_mode(nvswitch_device *device, NvU32 linkN
void nvswitch_reset_persistent_link_hw_state(nvswitch_device *device, NvU32 linkNumber);
void nvswitch_store_topology_information(nvswitch_device *device, nvlink_link *link);
NvlStatus nvswitch_launch_ALI(nvswitch_device *device);
NvlStatus nvswitch_launch_ALI_link_training(nvswitch_device *device, nvlink_link *link, NvBool bSync);
NvlStatus nvswitch_inband_read_data(nvswitch_device *device, NvU8 *dest, NvU32 linkId, NvU32 *dataSize);
void nvswitch_filter_messages(nvswitch_device *device, NvU32 linkId);
NvlStatus nvswitch_set_training_mode(nvswitch_device *device);
NvBool nvswitch_is_link_in_reset(nvswitch_device *device, nvlink_link *link);
void nvswitch_apply_recal_settings(nvswitch_device *device, nvlink_link *link);

20
src/common/nvswitch/kernel/inc/error_nvswitch.h
View File

@@ -61,9 +61,27 @@ typedef struct
NvU32 data[4]; // record of interrupt specific data
} NVSWITCH_INTERRUPT_LOG_TYPE;
#define NVSWITCH_RAW_ERROR_LOG_DATA_SIZE 16
#define NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_ROUTE_TIME BIT(0)
#define NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_ROUTE_MISC BIT(1)
#define NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_ROUTE_HDR BIT(2)
#define NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_INGRESS_TIME BIT(3)
#define NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_INGRESS_MISC BIT(4)
#define NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_INGRESS_HDR BIT(5)
#define NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_EGRESS_TIME BIT(6)
#define NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_EGRESS_MISC BIT(7)
#define NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_EGRESS_HDR BIT(8)
#define NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_EGRESS_MC_TIME BIT(9)
#define NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_EGRESS_MC_MISC BIT(10)
#define NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_EGRESS_MC_HDR BIT(11)
#define NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_MC_TIME BIT(12)
#define NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_RED_TIME BIT(13)
typedef struct
{
NvU32 data[16];
NvU32 flags;
NvU32 data[NVSWITCH_RAW_ERROR_LOG_DATA_SIZE];
} NVSWITCH_RAW_ERROR_LOG_TYPE;
#define NVSWITCH_ERROR_NEXT_LOCAL_NUMBER(log) (log->error_total)

1
src/common/nvswitch/kernel/inc/flcn/haldefs_flcn_nvswitch.h
View File

@@ -97,6 +97,7 @@ void flcnQueueSetupHal(struct FLCN *pFlcn);
void flcnRtosSetupHal(struct FLCN *pFlcn);
void flcnQueueRdSetupHal(struct FLCN *pFlcn);
void flcnSetupHal_LS10(struct FLCN *pFlcn);
void flcnSetupHal_LR10(struct FLCN *pFlcn);
void flcnSetupHal_v03_00(struct FLCN *pFlcn);

27
src/common/nvswitch/kernel/inc/haldef_nvswitch.h
View File

@@ -79,6 +79,8 @@
_op(NvlStatus, nvswitch_ctrl_get_ingress_response_table, (nvswitch_device *device, NVSWITCH_GET_INGRESS_RESPONSE_TABLE_PARAMS *params), _arch) \
_op(NvlStatus, nvswitch_ctrl_set_ingress_response_table, (nvswitch_device *device, NVSWITCH_SET_INGRESS_RESPONSE_TABLE *p), _arch) \
_op(NvlStatus, nvswitch_ctrl_set_ganged_link_table, (nvswitch_device *device, NVSWITCH_SET_GANGED_LINK_TABLE *p), _arch) \
_op(void, nvswitch_init_npg_multicast, (nvswitch_device *device), _arch) \
_op(void, nvswitch_init_warm_reset, (nvswitch_device *device), _arch) \
_op(NvlStatus, nvswitch_ctrl_set_remap_policy, (nvswitch_device *device, NVSWITCH_SET_REMAP_POLICY *p), _arch) \
_op(NvlStatus, nvswitch_ctrl_get_remap_policy, (nvswitch_device *device, NVSWITCH_GET_REMAP_POLICY_PARAMS *params), _arch) \
_op(NvlStatus, nvswitch_ctrl_set_remap_policy_valid, (nvswitch_device *device, NVSWITCH_SET_REMAP_POLICY_VALID *p), _arch) \
@@ -114,15 +116,15 @@
_op(NvlStatus, nvswitch_ctrl_get_fom_values, (nvswitch_device *device, NVSWITCH_GET_FOM_VALUES_PARAMS *p), _arch) \
_op(NvlStatus, nvswitch_deassert_link_reset, (nvswitch_device *device, nvlink_link *link), _arch) \
_op(NvBool, nvswitch_is_soe_supported, (nvswitch_device *device), _arch) \
_op(NvlStatus, nvswitch_soe_set_ucode_core, (nvswitch_device *device, NvBool bFalcon), _arch) \
_op(NvlStatus, nvswitch_init_soe, (nvswitch_device *device), _arch) \
_op(NvBool, nvswitch_is_inforom_supported, (nvswitch_device *device), _arch) \
_op(NvBool, nvswitch_is_spi_supported, (nvswitch_device *device), _arch) \
_op(NvBool, nvswitch_is_smbpbi_supported, (nvswitch_device *device), _arch) \
_op(NvlStatus, nvswitch_soe_prepare_for_reset, (nvswitch_device *device), _arch) \
_op(NvlStatus, nvswitch_post_init_device_setup, (nvswitch_device *device), _arch) \
_op(void, nvswitch_post_init_blacklist_device_setup, (nvswitch_device *device), _arch) \
_op(NvlStatus, nvswitch_setup_link_system_registers, (nvswitch_device *device), _arch) \
_op(NvlStatus, nvswitch_read_vbios_link_entries, (nvswitch_device *device, NvU32 tblPtr,NvU32 expected_link_entriesCount,NVLINK_CONFIG_DATA_LINKENTRY *link_entries, NvU32 *identified_link_entriesCount), _arch) \
_op(NvlStatus, nvswitch_vbios_read_structure, (nvswitch_device *device, void *structure, NvU32 offset, NvU32 *ppacked_size, const char *format), _arch) \
_op(NvlStatus, nvswitch_get_nvlink_ecc_errors, (nvswitch_device *device, NVSWITCH_GET_NVLINK_ECC_ERRORS_PARAMS *p), _arch) \
_op(NvlStatus, nvswitch_inforom_ecc_log_error_event, (nvswitch_device *device, INFOROM_ECC_OBJECT *pEccGeneric, INFOROM_NVS_ECC_ERROR_EVENT *error_event), _arch) \
_op(void, nvswitch_oms_set_device_disable, (INFOROM_OMS_STATE *pOmsState, NvBool bForceDeviceDisable), _arch) \
@@ -184,7 +186,6 @@
_op(NvlStatus, nvswitch_init_nxbar, (nvswitch_device *device), _arch) \
_op(NvlStatus, nvswitch_clear_nport_rams, (nvswitch_device *device), _arch) \
_op(NvlStatus, nvswitch_pri_ring_init, (nvswitch_device *device), _arch) \
_op(NvlStatus, nvswitch_get_soe_ucode_binaries, (nvswitch_device *device, const NvU32 **soe_ucode_data, const NvU32 **soe_ucode_header), _arch) \
_op(NvlStatus, nvswitch_get_remap_table_selector, (nvswitch_device *device, NVSWITCH_TABLE_SELECT_REMAP table_selector, NvU32 *remap_ram_sel), _arch) \
_op(NvU32, nvswitch_get_ingress_ram_size, (nvswitch_device *device, NvU32 ingress_ram_selector), _arch) \
_op(NvlStatus, nvswitch_minion_get_dl_status, (nvswitch_device *device, NvU32 linkId, NvU32 statusIdx, NvU32 statusArgs, NvU32 *statusData), _arch) \
@@ -202,14 +203,22 @@
_op(NvBool, nvswitch_is_link_in_reset, (nvswitch_device *device, nvlink_link *link), _arch) \
_op(void, nvswitch_init_buffer_ready, (nvswitch_device *device, nvlink_link * link, NvBool bNportBufferReady), _arch) \
_op(NvlStatus, nvswitch_ctrl_get_nvlink_lp_counters, (nvswitch_device *device, NVSWITCH_GET_NVLINK_LP_COUNTERS_PARAMS *p), _arch) \
_op(NvlStatus, nvswitch_ctrl_set_residency_bins, (nvswitch_device *device, NVSWITCH_SET_RESIDENCY_BINS *p), _arch) \
_op(NvlStatus, nvswitch_ctrl_get_residency_bins, (nvswitch_device *device, NVSWITCH_GET_RESIDENCY_BINS *p), _arch) \
_op(void, nvswitch_apply_recal_settings, (nvswitch_device *device, nvlink_link *), _arch) \
_op(NvlStatus, nvswitch_service_nvldl_fatal_link, (nvswitch_device *device, NvU32 nvliptInstance, NvU32 link), _arch) \
_op(NvlStatus, nvswitch_ctrl_get_rb_stall_busy, (nvswitch_device *device, NVSWITCH_GET_RB_STALL_BUSY *p), _arch) \
_op(NvlStatus, nvswitch_service_minion_link, (nvswitch_device *device, NvU32 link_id), _arch) \
_op(NvlStatus, nvswitch_ctrl_get_sw_info, (nvswitch_device *device, NVSWITCH_GET_SW_INFO_PARAMS *p), _arch)
#define NVSWITCH_HAL_FUNCTION_LIST_LS10(_op, _arch) \
_op(NvlStatus, nvswitch_launch_ALI, (nvswitch_device *device), _arch) \
_op(NvlStatus, nvswitch_launch_ALI_link_training, (nvswitch_device *device, nvlink_link *link, NvBool bSync), _arch) \
_op(NvlStatus, nvswitch_ctrl_inband_send_data, (nvswitch_device *device, NVSWITCH_INBAND_SEND_DATA_PARAMS *p), _arch) \
_op(NvlStatus, nvswitch_ctrl_inband_read_data, (nvswitch_device *device, NVSWITCH_INBAND_READ_DATA_PARAMS *p), _arch) \
_op(NvlStatus, nvswitch_ctrl_set_residency_bins, (nvswitch_device *device, NVSWITCH_SET_RESIDENCY_BINS *p), _arch) \
_op(NvlStatus, nvswitch_ctrl_get_residency_bins, (nvswitch_device *device, NVSWITCH_GET_RESIDENCY_BINS *p), _arch) \
_op(NvlStatus, nvswitch_ctrl_get_rb_stall_busy, (nvswitch_device *device, NVSWITCH_GET_RB_STALL_BUSY *p), _arch) \
_op(NvlStatus, nvswitch_ctrl_get_multicast_id_error_vector, (nvswitch_device *device, NVSWITCH_GET_MULTICAST_ID_ERROR_VECTOR *p), _arch) \
_op(NvlStatus, nvswitch_ctrl_clear_multicast_id_error_vector, (nvswitch_device *device, NVSWITCH_CLEAR_MULTICAST_ID_ERROR_VECTOR *p), _arch) \
//
// Declare HAL function pointer table
//
@@ -226,6 +235,7 @@
typedef struct nvswitch_hal_functions
{
NVSWITCH_HAL_FUNCTION_LIST(DECLARE_HAL_FUNCTIONS, HAL)
NVSWITCH_HAL_FUNCTION_LIST_LS10(DECLARE_HAL_FUNCTIONS, HAL)
} nvswitch_hal;
@@ -243,6 +253,9 @@ typedef struct nvswitch_hal_functions
#define NVSWITCH_INIT_HAL(device, arch) \
NVSWITCH_HAL_FUNCTION_LIST(CREATE_HAL_FUNCTIONS, arch) \
#define NVSWITCH_INIT_HAL_LS10(device, arch) \
NVSWITCH_HAL_FUNCTION_LIST_LS10(CREATE_HAL_FUNCTIONS, arch) \
//
// Declare HAL function dispatch functions
//
@@ -255,8 +268,10 @@ typedef struct nvswitch_hal_functions
_return _function _params;
NVSWITCH_HAL_FUNCTION_LIST(DECLARE_HAL_DISPATCHERS, unused_argument)
NVSWITCH_HAL_FUNCTION_LIST_LS10(DECLARE_HAL_DISPATCHERS, unused_argument)
// HAL functions
void nvswitch_setup_hal_lr10(nvswitch_device *device);
void nvswitch_setup_hal_ls10(nvswitch_device *device);
#endif //_HALDEF_NVSWITCH_H_

69
src/common/nvswitch/kernel/inc/io_nvswitch.h
View File

@@ -24,6 +24,9 @@
#ifndef _IO_NVSWITCH_H_
#define _IO_NVSWITCH_H_
#include "nv_list.h"
#include "ctrl_dev_nvswitch.h"
// NVSWITCH_REG_* MMIO wrappers are to be used for absolute symbolic BAR0 offset
// register references like SMC, CLOCK, BUS, and PRIV_MASTER.
//
@@ -92,11 +95,7 @@ typedef struct engine_descriptor
// NVSWITCH_REG_RD/WR IO wrappers.
//
#define NVSWITCH_LIST_ALL_ENGINES(_op) \
_op(XVE) \
_op(SAW) \
_op(SOE) \
_op(SMR) \
#define NVSWITCH_LIST_LS10_ONLY_ENGINES(_op) \
_op(GIN) \
_op(XAL) \
_op(XAL_FUNC) \
@@ -124,6 +123,15 @@ typedef struct engine_descriptor
_op(SYSB_PRI_RS_CTRL) \
_op(PRI_MASTER_RS) \
_op(PTIMER) \
_op(CPR) \
_op(TILEOUT) \
_op(TILEOUT_PERFMON) \
#define NVSWITCH_LIST_ALL_ENGINES(_op) \
_op(XVE) \
_op(SAW) \
_op(SOE) \
_op(SMR) \
\
_op(NPG) \
_op(NPORT) \
@@ -134,11 +142,9 @@ typedef struct engine_descriptor
_op(NVLIPT_LNK) \
_op(NVLTLC) \
_op(NVLDL) \
_op(CPR) \
\
_op(NXBAR) \
_op(TILE) \
_op(TILEOUT) \
\
_op(NPG_PERFMON) \
_op(NPORT_PERFMON) \
@@ -149,7 +155,6 @@ typedef struct engine_descriptor
\
_op(NXBAR_PERFMON) \
_op(TILE_PERFMON) \
_op(TILEOUT_PERFMON) \
#define ENGINE_ID_LIST(_eng) \
NVSWITCH_ENGINE_ID_##_eng,
@@ -164,6 +169,7 @@ typedef struct engine_descriptor
typedef enum nvswitch_engine_id
{
NVSWITCH_LIST_ALL_ENGINES(ENGINE_ID_LIST)
NVSWITCH_LIST_LS10_ONLY_ENGINES(ENGINE_ID_LIST)
NVSWITCH_ENGINE_ID_SIZE,
} NVSWITCH_ENGINE_ID;
@@ -312,30 +318,30 @@ typedef enum nvswitch_engine_id
#define NVSWITCH_MAX_SEED_BUFFER_SIZE NVSWITCH_MAX_SEED_NUM + 1
#define NVSWITCH_MAX_INBAND_BUFFER_SIZE 256*8
#define NVSWITCH_MAX_INBAND_BITS_SENT_AT_ONCE 32
#define NVSWITCH_MAX_INBAND_BUFFER_ENTRIES NVSWITCH_MAX_INBAND_BUFFER_SIZE/NVSWITCH_MAX_INBAND_BITS_SENT_AT_ONCE
//
// Inband data structure
// Storing list entries for sending to FM
//
struct nvswitch_inband_data
typedef struct
{
// Inband bufer at sender Minion
NvU32 sendBuffer[NVSWITCH_MAX_INBAND_BUFFER_ENTRIES];
NVListRec entry;
NvU8 data[NVSWITCH_INBAND_DATA_SIZE];
NvU32 dataSize;
} nvswitch_inband_data_list;
// Inband buffer at receiver Minion
NvU32 receiveBuffer[NVSWITCH_MAX_INBAND_BUFFER_ENTRIES];
typedef struct
{
// Temp entry being received
nvswitch_inband_data_list *message;
// Is the current Minion a sender or receiver of Inband Data?
NvBool bIsSenderMinion;
//
// Persistent messages are stored even if the listener (e.g. FM) is
// not present.
//
NVListRec persistent_list;
// Bool to say fail or not
NvBool bTransferFail;
// # of transmisions done - count
// NvU32 txCount;
};
// Stores messages if and only if the listener is present.
NVListRec nonpersistent_list;
} nvswitch_inband_receive_data;
typedef struct
{
@@ -347,14 +353,21 @@ typedef struct
NvBool egress_packet_latched;
NvBool nea; // Near end analog
NvBool ned; // Near end digital
NvBool nedr; // Near end digital
NvBool nedw;
NvU32 lane_rxdet_status_mask;
NvBool bIsRepeaterMode;
// Check if BUFFER_COMPLETE is seen
volatile NvBool isBufferComplete;
// Check if BUFFER_FAIL is seen
volatile NvBool isBufferFail;
// Minion Inband Data structure
struct nvswitch_inband_data inBandData;
nvswitch_inband_receive_data inbandData;
} NVSWITCH_LINK_TYPE;

11
src/common/nvswitch/kernel/inc/lr10/lr10.h
View File

@@ -352,7 +352,7 @@ typedef NVSWITCH_LINK_TYPE NVSWITCH_LINK_TYPE_LR10;
//
//
// LR10 supports CREQ0(0), DNGRD(1), ATR(2), ATSD(3), PROBE(4), RSP0(5), CREQ1(6), and RSP1(7) VCs.
// LR10 supports CREQ0(0), DNGRD(1), ATR(2), ATSD(3), PROBE(4), RSP0(5), CREQ1(6), and RSP1(7) VCs.
// But DNGRD(1), ATR(2), ATSD(3), and PROBE(4) will be never used as PowerPC ATS support is not a POR for LR10 HW.
//
#define NVSWITCH_NUM_VCS_LR10 8
@@ -436,7 +436,7 @@ typedef struct
// In order to collect all the useful unit information into a single container,
// we need to pick where to find each piece within the parsed discovery table.
// Top level IP wrappers like NPG have a BCAST range to broadcast reads/writes,
// but IP sub-units like NPORT have a MULTICAST range within the BCAST IP
// but IP sub-units like NPORT have a MULTICAST range within the BCAST IP
// wrapper to broadcast to all the sub-units in all the IP wrappers.
// So in the lists below top level IP wrappers (NPG, NVLW, and NXBAR) point
// to the _BCAST IP wrapper, but sub-unit point to the _MULTICAST range inside
@@ -627,11 +627,11 @@ NvlStatus nvswitch_get_link_public_id_lr10(nvswitch_device *device, NvU32 linkId
NvlStatus nvswitch_get_link_local_idx_lr10(nvswitch_device *device, NvU32 linkId, NvU32 *localLinkIdx);
NvlStatus nvswitch_set_training_error_info_lr10(nvswitch_device *device,
NVSWITCH_SET_TRAINING_ERROR_INFO_PARAMS *pLinkTrainingErrorInfoParams);
NvlStatus nvswitch_read_vbios_link_entries_lr10(nvswitch_device *device, NvU32 tblPtr,NvU32 entriesCount,NVLINK_CONFIG_DATA_LINKENTRY *link_entries, NvU32 *identified_entriesCount);
NvlStatus nvswitch_ctrl_get_fatal_error_scope_lr10(nvswitch_device *device, NVSWITCH_GET_FATAL_ERROR_SCOPE_PARAMS *pParams);
void nvswitch_init_scratch_lr10(nvswitch_device *device);
void nvswitch_init_dlpl_interrupts_lr10(nvlink_link *link);
NvlStatus nvswitch_init_nport_lr10(nvswitch_device *device);
NvlStatus nvswitch_get_soe_ucode_binaries_lr10(nvswitch_device *device, const NvU32 **soe_ucode_data, const NvU32 **soe_ucode_header);
NvlStatus nvswitch_poll_sublink_state_lr10(nvswitch_device *device, nvlink_link *link);
void nvswitch_setup_link_loopback_mode_lr10(nvswitch_device *device, NvU32 linkNumber);
void nvswitch_reset_persistent_link_hw_state_lr10(nvswitch_device *device, NvU32 linkNumber);
@@ -646,8 +646,13 @@ void nvswitch_corelib_get_uphy_load_lr10(nvlink_link *link, NvBool *bUnlocked);
void nvswitch_init_buffer_ready_lr10(nvswitch_device *device, nvlink_link *link, NvBool bNportBufferReady);
NvlStatus nvswitch_ctrl_get_nvlink_lp_counters_lr10(nvswitch_device *device, NVSWITCH_GET_NVLINK_LP_COUNTERS_PARAMS *params);
NvlStatus nvswitch_service_nvldl_fatal_link_lr10(nvswitch_device *device, NvU32 nvliptInstance, NvU32 link);
NvlStatus nvswitch_ctrl_inband_send_data_lr10(nvswitch_device *device, NVSWITCH_INBAND_SEND_DATA_PARAMS *p);
NvlStatus nvswitch_ctrl_inband_read_data_lr10(nvswitch_device *device, NVSWITCH_INBAND_READ_DATA_PARAMS *p);
NvlStatus nvswitch_launch_ALI_link_training_lr10(nvswitch_device *device, nvlink_link *link, NvBool bSync);
NvlStatus nvswitch_service_minion_link_lr10(nvswitch_device *device, NvU32 nvliptInstance);
void nvswitch_apply_recal_settings_lr10(nvswitch_device *device, nvlink_link *link);
NvlStatus nvswitch_ctrl_get_sw_info_lr10(nvswitch_device *device, NVSWITCH_GET_SW_INFO_PARAMS *p);
NvlStatus nvswitch_launch_ALI_lr10(nvswitch_device *device);
#endif //_LR10_H_

1
src/common/nvswitch/kernel/inc/lr10/minion_lr10.h
View File

@@ -92,4 +92,5 @@ NvU32 nvswitch_minion_get_data_rate_KiBps_lr10(nvswitch_device *device, NvU3
NvlStatus nvswitch_set_minion_initialized_lr10(nvswitch_device *device, NvU32 idx_minion, NvBool initialized);
NvBool nvswitch_is_minion_initialized_lr10(nvswitch_device *device, NvU32 idx_minion);
NvlStatus nvswitch_minion_clear_dl_error_counters_lr10(nvswitch_device *device, NvU32 linkId);
#endif //_MINION_LR10_H_

2
src/common/nvswitch/kernel/inc/lr10/soe_lr10.h
View File

@@ -58,10 +58,8 @@ typedef const struct
// Internal function declarations
//
NvlStatus nvswitch_init_soe_lr10(nvswitch_device *device);
NvlStatus nvswitch_soe_prepare_for_reset_lr10(nvswitch_device *device);
void nvswitch_soe_unregister_events_lr10(nvswitch_device *device);
void nvswitch_therm_soe_callback_lr10(nvswitch_device *device, union RM_FLCN_MSG *pMsg,
void *pParams, NvU32 seqDesc, NV_STATUS status);
NvlStatus nvswitch_soe_set_ucode_core_lr10(nvswitch_device *device, NvBool bFalcon);
NvlStatus nvswitch_soe_register_event_callbacks_lr10(nvswitch_device *device);
#endif //_SOE_LR10_H_

21
src/common/nvswitch/kernel/inc/regkey_nvswitch.h
View File

@@ -229,15 +229,6 @@
#define NV_SWITCH_REGKEY_SOE_DISABLE_NO 0x0
#define NV_SWITCH_REGKEY_SOE_DISABLE_YES 0x1
/*
* NV_SWITCH_REGKEY_SOE_BOOT_CORE - Selects SOE core
*
* Public: Available in release drivers
*/
#define NV_SWITCH_REGKEY_SOE_BOOT_CORE "SoeBootCore"
#define NV_SWITCH_REGKEY_SOE_BOOT_CORE_FALCON 0x0
#define NV_SWITCH_REGKEY_SOE_BOOT_CORE_DEFAULT 0x2
/*
* NV_SWITCH_REGKEY_ENABLE_PM
*
@@ -409,11 +400,18 @@
*
* When the regkey is set to FALCON, the Nvswitch driver will run MINION on Falcon core.
*
* If set to RISCV, the MINION will run on RISCV core in Non-Manifest Mode.
* If set to RISCV_MANIFEST, the MINION will run on RISCV core in Manifest Mode.
*
* In the default option, RISCV_BCR_CTRL register will be used to get the default core.
*
* Private: Debug use only
*/
#define NV_SWITCH_REGKEY_MINION_SET_UCODE_TARGET "MinionSetUcodeTarget"
#define NV_SWITCH_REGKEY_MINION_SET_UCODE_TARGET_DEFAULT 0x0
#define NV_SWITCH_REGKEY_MINION_SET_UCODE_TARGET_FALCON 0x1
#define NV_SWITCH_REGKEY_MINION_SET_UCODE_TARGET_RISCV 0x2
#define NV_SWITCH_REGKEY_MINION_SET_UCODE_TARGET_RISCV_MANIFEST 0x3
/*
* NV_SWITCH_REGKEY_MINION_SET_SIMMODE - Selects simmode settings to send to MINION
@@ -500,13 +498,14 @@
/*
* NV_SWITCH_REGKEY_LINK_TRAINING_SELECT - Select the Link training to be done
*
* This regkey will
* For LS10, links can be trained via non-ALI or ALI training. This regkey will
* allow for overriding System Defaults and can force either training method
* when desired.
*/
#define NV_SWITCH_REGKEY_LINK_TRAINING_SELECT "LinkTrainingMode"
#define NV_SWITCH_REGKEY_LINK_TRAINING_SELECT_DEFAULT 0x0
#define NV_SWITCH_REGKEY_LINK_TRAINING_SELECT_NON_ALI 0x1
#define NV_SWITCH_REGKEY_LINK_TRAINING_SELECT_ALI 0x2
/*
* NV_SWITCH_REGKEY_I2C_ACCESS_CONTROL - Enable access to all I2C Ports/Devices
*

28
src/common/nvswitch/kernel/inc/rom_nvswitch.h
View File

@@ -547,6 +547,9 @@ nvswitch_read_rom_tables
#define NVLINK_CONFIG_DATA_HEADER_20_SIZE 8
#define NVLINK_CONFIG_DATA_HEADER_20_FMT "6b1w"
#define NVLINK_CONFIG_DATA_HEADER_VER_30 0x3
#define NVLINK_CONFIG_DATA_HEADER_30_SIZE 8
typedef struct _PCI_DATA_STRUCT
{
bios_U032 sig; // 00h: Signature, the string "PCIR" or NVIDIA's alternate "NPDS"
@@ -747,7 +750,9 @@ typedef struct _nvlink_Config_Data_Header_20
#define NV_NVLINK_VBIOS_PARAM6_TXTRAIN_MINIMUM_TRAIN_TIME_EXPONENT 7:4
#define NVLINK_CONFIG_DATA_BASEENTRY_FMT "1b"
#define NVLINK_CONFIG_DATA_LINKENTRY_FMT "7b"
#define NVLINK_CONFIG_DATA_LINKENTRY_FMT_20 "7b"
#define NVLINK_CONFIG_DATA_LINKENTRY_FMT_30 "10b"
// Version 2.0 Link Entry and Base Entry
typedef struct _nvlink_config_data_baseentry_20
{
@@ -764,9 +769,11 @@ typedef struct _nvlink_config_data_linkentry_20
NvU8 nvLinkparam4;
NvU8 nvLinkparam5;
NvU8 nvLinkparam6;
NvU8 nvLinkparam7;
NvU8 nvLinkparam8;
NvU8 nvLinkparam9;
} NVLINK_CONFIG_DATA_LINKENTRY;
// Union of different VBIOS configuration table formats
typedef union __nvlink_Config_Data_Header
{
@@ -788,7 +795,22 @@ typedef struct _nvlink_vbios_config_data_linkentry_20
bios_U008 nvLinkparam4;
bios_U008 nvLinkparam5;
bios_U008 nvLinkparam6;
} NVLINK_VBIOS_CONFIG_DATA_LINKENTRY, *PNVLINK_VBIOS_CONFIG_DATA_LINKENTRY;
} NVLINK_VBIOS_CONFIG_DATA_LINKENTRY_20, *PNVLINK_VBIOS_CONFIG_DATA_LINKENTRY_20;
typedef struct _nvlink_vbios_config_data_linkentry_30
{
// VBIOS configuration Data
bios_U008 nvLinkparam0;
bios_U008 nvLinkparam1;
bios_U008 nvLinkparam2;
bios_U008 nvLinkparam3;
bios_U008 nvLinkparam4;
bios_U008 nvLinkparam5;
bios_U008 nvLinkparam6;
bios_U008 nvLinkparam7;
bios_U008 nvLinkparam8;
bios_U008 nvLinkparam9;
} NVLINK_VBIOS_CONFIG_DATA_LINKENTRY_30, *PNVLINK_VBIOS_CONFIG_DATA_LINKENTRY_30;
//
// NVSwitch driver structures

2848
src/common/nvswitch/kernel/inc/soe/bin/g_soeuc_lr10_dbg.h
View File

File diff suppressed because it is too large Load Diff

2848
src/common/nvswitch/kernel/inc/soe/bin/g_soeuc_lr10_prd.h
View File

File diff suppressed because it is too large Load Diff

1
src/common/nvswitch/kernel/inc/soe/haldefs_soe_nvswitch.h
View File

@@ -116,5 +116,6 @@ typedef struct {
// HAL functions
void soeSetupHal_LR10(struct SOE *pSoe);
void soeSetupHal_LS10(struct SOE *pSoe);
#endif //_HALDEFS_SOE_NVSWITCH_H_

6
src/common/nvswitch/kernel/inc/soe/soe_nvswitch.h
View File

@@ -37,10 +37,8 @@ NvlStatus soeInit(struct nvswitch_device *device, PSOE pSoe, NvU32 pci_device_id
void soeDestroy(struct nvswitch_device *device, PSOE pSoe);
//HAL functions
NV_STATUS soeProcessMessages (struct nvswitch_device *device, PSOE pSoe);
NV_STATUS soeWaitForInitAck (struct nvswitch_device *device, PSOE pSoe);
NV_STATUS soeProcessMessages_HAL (struct nvswitch_device *device, PSOE pSoe);
NV_STATUS soeWaitForInitAck_HAL (struct nvswitch_device *device, PSOE pSoe);
NvU32 soeService_HAL (struct nvswitch_device *device, PSOE pSoe);
void soeServiceHalt_HAL (struct nvswitch_device *device, PSOE pSoe);
void soeEmemTransfer_HAL (struct nvswitch_device *device, PSOE pSoe, NvU32 dmemAddr, NvU8 *pBuf, NvU32 sizeBytes, NvU8 port, NvBool bCopyFrom);

450
src/common/nvswitch/kernel/lr10/intr_lr10.c
View File

@@ -1190,34 +1190,286 @@ _nvswitch_service_priv_ring_lr10
return NVL_SUCCESS;
}
static void
_nvswitch_save_route_err_header_lr10
static NvlStatus
_nvswitch_collect_nport_error_info_lr10
(
nvswitch_device *device,
NvU32 link,
NVSWITCH_RAW_ERROR_LOG_TYPE *data,
NvU32 *idx,
NvU32 register_start,
NvU32 register_end
)
{
NvU32 register_block_size;
NvU32 i = *idx;
if ((register_start > register_end) ||
(register_start % sizeof(NvU32) != 0) ||
(register_end % sizeof(NvU32) != 0))
{
return -NVL_BAD_ARGS;
}
register_block_size = (register_end - register_start)/sizeof(NvU32) + 1;
if ((i + register_block_size > NVSWITCH_RAW_ERROR_LOG_DATA_SIZE) ||
(register_block_size > NVSWITCH_RAW_ERROR_LOG_DATA_SIZE))
{
return -NVL_BAD_ARGS;
}
do
{
data->data[i] = NVSWITCH_ENG_OFF_RD32(device, NPORT, , link, register_start);
register_start += sizeof(NvU32);
i++;
}
while (register_start <= register_end);
*idx = i;
return NVL_SUCCESS;
}
static void
_nvswitch_collect_error_info_lr10
(
nvswitch_device *device,
NvU32 link,
NvU32 collect_flags, // NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_*
NVSWITCH_RAW_ERROR_LOG_TYPE *data
)
{
NvU32 val;
NvU32 i = 0;
NvBool data_collect_error = NV_FALSE;
NvlStatus status = NVL_SUCCESS;
//
// The requested data 'collect_flags' is captured, if valid.
// if the error log buffer fills, then the currently captured data block
// could be truncated and subsequent blocks will be skipped.
// The 'flags' field in the log structure describes which blocks are
// actually captured.
// Captured blocks are packed, in order.
//
data->flags = 0;
// ROUTE
if (collect_flags & NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_ROUTE_TIME)
{
status = _nvswitch_collect_nport_error_info_lr10(device, link, data, &i,
NV_ROUTE_ERR_TIMESTAMP_LOG,
NV_ROUTE_ERR_TIMESTAMP_LOG);
if (status == NVL_SUCCESS)
{
data->flags |= NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_ROUTE_TIME;
NVSWITCH_PRINT(device, INFO,
"ROUTE: TIMESTAMP: 0x%08x\n", data->data[i-1]);
}
else
{
data_collect_error = NV_TRUE;
NVSWITCH_PRINT(device, ERROR,
"ROUTE: TIMESTAMP: Error collecting error data\n");
}
}
data->data[i++] = NVSWITCH_NPORT_RD32_LR10(device, link, _ROUTE, _ERR_TIMESTAMP_LOG);
val = NVSWITCH_NPORT_RD32_LR10(device, link, _ROUTE, _ERR_HEADER_LOG_VALID);
if (FLD_TEST_DRF_NUM(_ROUTE, _ERR_HEADER_LOG_VALID, _HEADERVALID0, 1, val))
{
data->data[i++] = NVSWITCH_NPORT_RD32_LR10(device, link, _ROUTE, _ERR_MISC_LOG_0);
data->data[i++] = NVSWITCH_NPORT_RD32_LR10(device, link, _ROUTE, _ERR_HEADER_LOG_0);
data->data[i++] = NVSWITCH_NPORT_RD32_LR10(device, link, _ROUTE, _ERR_HEADER_LOG_1);
data->data[i++] = NVSWITCH_NPORT_RD32_LR10(device, link, _ROUTE, _ERR_HEADER_LOG_2);
data->data[i++] = NVSWITCH_NPORT_RD32_LR10(device, link, _ROUTE, _ERR_HEADER_LOG_3);
data->data[i++] = NVSWITCH_NPORT_RD32_LR10(device, link, _ROUTE, _ERR_HEADER_LOG_4);
data->data[i++] = NVSWITCH_NPORT_RD32_LR10(device, link, _ROUTE, _ERR_HEADER_LOG_5);
data->data[i++] = NVSWITCH_NPORT_RD32_LR10(device, link, _ROUTE, _ERR_HEADER_LOG_6);
data->data[i++] = NVSWITCH_NPORT_RD32_LR10(device, link, _ROUTE, _ERR_HEADER_LOG_7);
data->data[i++] = NVSWITCH_NPORT_RD32_LR10(device, link, _ROUTE, _ERR_HEADER_LOG_8);
data->data[i++] = NVSWITCH_NPORT_RD32_LR10(device, link, _ROUTE, _ERR_HEADER_LOG_9);
data->data[i++] = NVSWITCH_NPORT_RD32_LR10(device, link, _ROUTE, _ERR_HEADER_LOG_10);
if (collect_flags & NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_ROUTE_MISC)
{
status = _nvswitch_collect_nport_error_info_lr10(device, link, data, &i,
NV_ROUTE_ERR_MISC_LOG_0,
NV_ROUTE_ERR_MISC_LOG_0);
if (status == NVL_SUCCESS)
{
data->flags |= NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_ROUTE_MISC;
NVSWITCH_PRINT(device, INFO,
"ROUTE: MISC: 0x%08x\n", data->data[i-1]);
}
else
{
data_collect_error = NV_TRUE;
NVSWITCH_PRINT(device, ERROR,
"ROUTE: MISC: Error collecting error data\n");
}
}
if (collect_flags & NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_ROUTE_HDR)
{
status = _nvswitch_collect_nport_error_info_lr10(device, link, data, &i,
NV_ROUTE_ERR_HEADER_LOG_0,
NV_ROUTE_ERR_HEADER_LOG_10);
if (status == NVL_SUCCESS)
{
data->flags |= NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_ROUTE_HDR;
NVSWITCH_PRINT(device, INFO,
"ROUTE: HEADER: 0x%08x, 0x%08x, 0x%08x, 0x%08x, 0x%08x, 0x%08x, 0x%08x, 0x%08x,\n",
data->data[i-12], data->data[i-11], data->data[i-10], data->data[i-9],
data->data[i-8], data->data[i-7], data->data[i-6], data->data[i-5]);
NVSWITCH_PRINT(device, INFO,
"ROUTE: HEADER: 0x%08x, 0x%08x, 0x%08x, 0x%08x\n",
data->data[i-4], data->data[i-3], data->data[i-2], data->data[i-1]);
}
else
{
data_collect_error = NV_TRUE;
NVSWITCH_PRINT(device, ERROR,
"ROUTE: HEADER: Error collecting error data\n");
}
}
}
// INGRESS
if (collect_flags & NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_INGRESS_TIME)
{
status = _nvswitch_collect_nport_error_info_lr10(device, link, data, &i,
NV_INGRESS_ERR_TIMESTAMP_LOG,
NV_INGRESS_ERR_TIMESTAMP_LOG);
if (status == NVL_SUCCESS)
{
data->flags |= NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_INGRESS_TIME;
NVSWITCH_PRINT(device, INFO,
"INGRESS: TIMESTAMP: 0x%08x\n", data->data[i-1]);
}
else
{
data_collect_error = NV_TRUE;
NVSWITCH_PRINT(device, ERROR,
"INGRESS: TIMESTAMP: Error collecting error data\n");
}
}
val = NVSWITCH_NPORT_RD32_LR10(device, link, _INGRESS, _ERR_HEADER_LOG_VALID);
if (FLD_TEST_DRF_NUM(_INGRESS, _ERR_HEADER_LOG_VALID, _HEADERVALID0, 1, val))
{
if (collect_flags & NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_INGRESS_MISC)
{
status = _nvswitch_collect_nport_error_info_lr10(device, link, data, &i,
NV_INGRESS_ERR_MISC_LOG_0,
NV_INGRESS_ERR_MISC_LOG_0);
if (status == NVL_SUCCESS)
{
data->flags |= NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_INGRESS_MISC;
NVSWITCH_PRINT(device, INFO,
"INGRESS: MISC: 0x%08x\n", data->data[i-1]);
}
else
{
data_collect_error = NV_TRUE;
NVSWITCH_PRINT(device, ERROR,
"INGRESS: MISC: Error collecting error data\n");
}
}
if (collect_flags & NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_INGRESS_HDR)
{
status = _nvswitch_collect_nport_error_info_lr10(device, link, data, &i,
NV_INGRESS_ERR_HEADER_LOG_0,
NV_INGRESS_ERR_HEADER_LOG_10);
if (status == NVL_SUCCESS)
{
data->flags |= NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_INGRESS_HDR;
NVSWITCH_PRINT(device, INFO,
"INGRESS: HEADER: 0x%08x, 0x%08x, 0x%08x, 0x%08x, 0x%08x, 0x%08x, 0x%08x, 0x%08x,\n",
data->data[i-12], data->data[i-11], data->data[i-10], data->data[i-9],
data->data[i-8], data->data[i-7], data->data[i-6], data->data[i-5]);
NVSWITCH_PRINT(device, INFO,
"INGRESS: HEADER: 0x%08x, 0x%08x, 0x%08x, 0x%08x\n",
data->data[i-4], data->data[i-3], data->data[i-2], data->data[i-1]);
}
else
{
data_collect_error = NV_TRUE;
NVSWITCH_PRINT(device, ERROR,
"INGRESS: HEADER: Error collecting error data\n");
}
}
}
// EGRESS
if (collect_flags & NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_EGRESS_TIME)
{
status = _nvswitch_collect_nport_error_info_lr10(device, link, data, &i,
NV_EGRESS_ERR_TIMESTAMP_LOG,
NV_EGRESS_ERR_TIMESTAMP_LOG);
if (status == NVL_SUCCESS)
{
data->flags |= NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_EGRESS_TIME;
NVSWITCH_PRINT(device, INFO,
"EGRESS: TIMESTAMP: 0x%08x\n", data->data[i-1]);
}
else
{
data_collect_error = NV_TRUE;
NVSWITCH_PRINT(device, ERROR,
"EGRESS: TIMESTAMP: Error collecting error data\n");
}
}
val = NVSWITCH_NPORT_RD32_LR10(device, link, _EGRESS, _ERR_HEADER_LOG_VALID);
if (FLD_TEST_DRF_NUM(_EGRESS, _ERR_HEADER_LOG_VALID, _HEADERVALID0, 1, val))
{
if (collect_flags & NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_EGRESS_MISC)
{
status = _nvswitch_collect_nport_error_info_lr10(device, link, data, &i,
NV_EGRESS_ERR_MISC_LOG_0,
NV_EGRESS_ERR_MISC_LOG_0);
if (status == NVL_SUCCESS)
{
data->flags |= NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_EGRESS_MISC;
NVSWITCH_PRINT(device, INFO,
"EGRESS: MISC: 0x%08x\n", data->data[i-1]);
}
else
{
data_collect_error = NV_TRUE;
NVSWITCH_PRINT(device, ERROR,
"EGRESS: MISC: Error collecting error data\n");
}
}
if (collect_flags & NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_EGRESS_HDR)
{
status = _nvswitch_collect_nport_error_info_lr10(device, link, data, &i,
NV_EGRESS_ERR_HEADER_LOG_0,
NV_EGRESS_ERR_HEADER_LOG_10);
if (status == NVL_SUCCESS)
{
data->flags |= NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_EGRESS_HDR;
NVSWITCH_PRINT(device, INFO,
"EGRESS: HEADER: 0x%08x, 0x%08x, 0x%08x, 0x%08x, 0x%08x, 0x%08x, 0x%08x, 0x%08x,\n",
data->data[i-12], data->data[i-11], data->data[i-10], data->data[i-9],
data->data[i-8], data->data[i-7], data->data[i-6], data->data[i-5]);
NVSWITCH_PRINT(device, INFO,
"EGRESS: HEADER: 0x%08x, 0x%08x, 0x%08x, 0x%08x\n",
data->data[i-4], data->data[i-3], data->data[i-2], data->data[i-1]);
}
else
{
data_collect_error = NV_TRUE;
NVSWITCH_PRINT(device, ERROR,
"EGRESS: HEADER: Error collecting error data\n");
}
}
}
while (i < NVSWITCH_RAW_ERROR_LOG_DATA_SIZE)
{
data->data[i++] = 0;
}
if (data_collect_error)
{
NVSWITCH_PRINT(device, ERROR,
"%s: Error collecting error info 0x%x. Only 0x%x error data collected.\n",
__FUNCTION__, collect_flags, data->flags);
}
}
@@ -1231,7 +1483,7 @@ _nvswitch_service_route_fatal_lr10
lr10_device *chip_device = NVSWITCH_GET_CHIP_DEVICE_LR10(device);
NVSWITCH_INTERRUPT_LOG_TYPE report = { 0 };
NvU32 pending, bit, contain, unhandled;
NVSWITCH_RAW_ERROR_LOG_TYPE data = {{ 0 }};
NVSWITCH_RAW_ERROR_LOG_TYPE data = {0, { 0 }};
INFOROM_NVS_ECC_ERROR_EVENT err_event = {0};
report.raw_pending = NVSWITCH_NPORT_RD32_LR10(device, link, _ROUTE, _ERR_STATUS_0);
@@ -1248,7 +1500,11 @@ _nvswitch_service_route_fatal_lr10
report.raw_first = NVSWITCH_NPORT_RD32_LR10(device, link, _ROUTE, _ERR_FIRST_0);
contain = NVSWITCH_NPORT_RD32_LR10(device, link, _ROUTE, _ERR_CONTAIN_EN_0);
_nvswitch_save_route_err_header_lr10(device, link, &data);
_nvswitch_collect_error_info_lr10(device, link,
NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_ROUTE_TIME |
NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_ROUTE_MISC |
NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_ROUTE_HDR,
&data);
bit = DRF_NUM(_ROUTE, _ERR_STATUS_0, _ROUTEBUFERR, 1);
if (nvswitch_test_flags(pending, bit))
@@ -1371,7 +1627,7 @@ _nvswitch_service_route_nonfatal_lr10
lr10_device *chip_device = NVSWITCH_GET_CHIP_DEVICE_LR10(device);
NVSWITCH_INTERRUPT_LOG_TYPE report = { 0 };
NvU32 pending, bit, unhandled;
NVSWITCH_RAW_ERROR_LOG_TYPE data = {{ 0 }};
NVSWITCH_RAW_ERROR_LOG_TYPE data = {0, { 0 }};
INFOROM_NVS_ECC_ERROR_EVENT err_event = {0};
report.raw_pending = NVSWITCH_NPORT_RD32_LR10(device, link, _ROUTE, _ERR_STATUS_0);
@@ -1386,7 +1642,11 @@ _nvswitch_service_route_nonfatal_lr10
unhandled = pending;
report.raw_first = NVSWITCH_NPORT_RD32_LR10(device, link, _ROUTE, _ERR_FIRST_0);
_nvswitch_save_route_err_header_lr10(device, link, &data);
_nvswitch_collect_error_info_lr10(device, link,
NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_ROUTE_TIME |
NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_ROUTE_MISC |
NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_ROUTE_HDR,
&data);
bit = DRF_NUM(_ROUTE, _ERR_STATUS_0, _NOPORTDEFINEDERR, 1);
if (nvswitch_test_flags(pending, bit))
@@ -1463,41 +1723,6 @@ _nvswitch_service_route_nonfatal_lr10
// Ingress
//
static void
_nvswitch_save_ingress_err_header_lr10
(
nvswitch_device *device,
NvU32 link,
NVSWITCH_RAW_ERROR_LOG_TYPE *data
)
{
NvU32 val;
NvU32 i = 0;
data->data[i++] = NVSWITCH_NPORT_RD32_LR10(device, link, _INGRESS, _ERR_TIMESTAMP_LOG);
val = NVSWITCH_NPORT_RD32_LR10(device, link, _INGRESS, _ERR_HEADER_LOG_VALID);
if (FLD_TEST_DRF_NUM(_INGRESS, _ERR_HEADER_LOG_VALID, _HEADERVALID0, 1, val))
{
data->data[i++] = NVSWITCH_NPORT_RD32_LR10(device, link, _INGRESS, _ERR_MISC_LOG_0);
data->data[i++] = NVSWITCH_NPORT_RD32_LR10(device, link, _INGRESS, _ERR_HEADER_LOG_0);
data->data[i++] = NVSWITCH_NPORT_RD32_LR10(device, link, _INGRESS, _ERR_HEADER_LOG_1);
data->data[i++] = NVSWITCH_NPORT_RD32_LR10(device, link, _INGRESS, _ERR_HEADER_LOG_2);
data->data[i++] = NVSWITCH_NPORT_RD32_LR10(device, link, _INGRESS, _ERR_HEADER_LOG_3);
data->data[i++] = NVSWITCH_NPORT_RD32_LR10(device, link, _INGRESS, _ERR_HEADER_LOG_4);
data->data[i++] = NVSWITCH_NPORT_RD32_LR10(device, link, _INGRESS, _ERR_HEADER_LOG_5);
data->data[i++] = NVSWITCH_NPORT_RD32_LR10(device, link, _INGRESS, _ERR_HEADER_LOG_6);
data->data[i++] = NVSWITCH_NPORT_RD32_LR10(device, link, _INGRESS, _ERR_HEADER_LOG_7);
data->data[i++] = NVSWITCH_NPORT_RD32_LR10(device, link, _INGRESS, _ERR_HEADER_LOG_8);
data->data[i++] = NVSWITCH_NPORT_RD32_LR10(device, link, _INGRESS, _ERR_HEADER_LOG_9);
data->data[i++] = NVSWITCH_NPORT_RD32_LR10(device, link, _INGRESS, _ERR_HEADER_LOG_10);
}
else
{
data->data[i++] = 0xdeadbeef;
}
}
static NvlStatus
_nvswitch_service_ingress_fatal_lr10
(
@@ -1508,7 +1733,7 @@ _nvswitch_service_ingress_fatal_lr10
lr10_device *chip_device = NVSWITCH_GET_CHIP_DEVICE_LR10(device);
NVSWITCH_INTERRUPT_LOG_TYPE report = { 0 };
NvU32 pending, bit, contain, unhandled;
NVSWITCH_RAW_ERROR_LOG_TYPE data = {{ 0 }};
NVSWITCH_RAW_ERROR_LOG_TYPE data = {0, { 0 }};
INFOROM_NVS_ECC_ERROR_EVENT err_event = {0};
report.raw_pending = NVSWITCH_NPORT_RD32_LR10(device, link, _INGRESS, _ERR_STATUS_0);
@@ -1524,7 +1749,11 @@ _nvswitch_service_ingress_fatal_lr10
unhandled = pending;
report.raw_first = NVSWITCH_NPORT_RD32_LR10(device, link, _INGRESS, _ERR_FIRST_0);
contain = NVSWITCH_NPORT_RD32_LR10(device, link, _INGRESS, _ERR_CONTAIN_EN_0);
_nvswitch_save_ingress_err_header_lr10(device, link, &data);
_nvswitch_collect_error_info_lr10(device, link,
NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_INGRESS_TIME |
NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_INGRESS_MISC |
NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_INGRESS_HDR,
&data);
bit = DRF_NUM(_INGRESS, _ERR_STATUS_0, _CMDDECODEERR, 1);
if (nvswitch_test_flags(pending, bit))
@@ -1704,7 +1933,7 @@ _nvswitch_service_ingress_nonfatal_lr10
lr10_device *chip_device = NVSWITCH_GET_CHIP_DEVICE_LR10(device);
NVSWITCH_INTERRUPT_LOG_TYPE report = { 0 };
NvU32 pending, bit, unhandled;
NVSWITCH_RAW_ERROR_LOG_TYPE data = {{ 0 }};
NVSWITCH_RAW_ERROR_LOG_TYPE data = {0, { 0 }};
INFOROM_NVS_ECC_ERROR_EVENT err_event = {0};
report.raw_pending = NVSWITCH_NPORT_RD32_LR10(device, link, _INGRESS, _ERR_STATUS_0);
@@ -1719,7 +1948,11 @@ _nvswitch_service_ingress_nonfatal_lr10
unhandled = pending;
report.raw_first = NVSWITCH_NPORT_RD32_LR10(device, link, _INGRESS, _ERR_FIRST_0);
_nvswitch_save_ingress_err_header_lr10(device, link, &data);
_nvswitch_collect_error_info_lr10(device, link,
NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_INGRESS_TIME |
NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_INGRESS_MISC |
NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_INGRESS_HDR,
&data);
bit = DRF_NUM(_INGRESS, _ERR_STATUS_0, _REQCONTEXTMISMATCHERR, 1);
if (nvswitch_test_flags(pending, bit))
@@ -1820,41 +2053,6 @@ _nvswitch_service_ingress_nonfatal_lr10
// Egress
//
static void
_nvswitch_save_egress_err_header_lr10
(
nvswitch_device *device,
NvU32 link,
NVSWITCH_RAW_ERROR_LOG_TYPE *data
)
{
NvU32 val;
NvU32 i = 0;
data->data[i++] = NVSWITCH_NPORT_RD32_LR10(device, link, _EGRESS, _ERR_TIMESTAMP_LOG);
val = NVSWITCH_NPORT_RD32_LR10(device, link, _EGRESS, _ERR_HEADER_LOG_VALID);
if (FLD_TEST_DRF_NUM(_EGRESS, _ERR_HEADER_LOG_VALID, _HEADERVALID0, 1, val))
{
data->data[i++] = NVSWITCH_NPORT_RD32_LR10(device, link, _EGRESS, _ERR_MISC_LOG_0);
data->data[i++] = NVSWITCH_NPORT_RD32_LR10(device, link, _EGRESS, _ERR_HEADER_LOG_0);
data->data[i++] = NVSWITCH_NPORT_RD32_LR10(device, link, _EGRESS, _ERR_HEADER_LOG_1);
data->data[i++] = NVSWITCH_NPORT_RD32_LR10(device, link, _EGRESS, _ERR_HEADER_LOG_2);
data->data[i++] = NVSWITCH_NPORT_RD32_LR10(device, link, _EGRESS, _ERR_HEADER_LOG_3);
data->data[i++] = NVSWITCH_NPORT_RD32_LR10(device, link, _EGRESS, _ERR_HEADER_LOG_4);
data->data[i++] = NVSWITCH_NPORT_RD32_LR10(device, link, _EGRESS, _ERR_HEADER_LOG_5);
data->data[i++] = NVSWITCH_NPORT_RD32_LR10(device, link, _EGRESS, _ERR_HEADER_LOG_6);
data->data[i++] = NVSWITCH_NPORT_RD32_LR10(device, link, _EGRESS, _ERR_HEADER_LOG_7);
data->data[i++] = NVSWITCH_NPORT_RD32_LR10(device, link, _EGRESS, _ERR_HEADER_LOG_8);
data->data[i++] = NVSWITCH_NPORT_RD32_LR10(device, link, _EGRESS, _ERR_HEADER_LOG_9);
data->data[i++] = NVSWITCH_NPORT_RD32_LR10(device, link, _EGRESS, _ERR_HEADER_LOG_10);
}
else
{
data->data[i++] = 0xdeadbeef;
}
}
static NvlStatus
_nvswitch_service_tstate_nonfatal_lr10
(
@@ -1865,7 +2063,7 @@ _nvswitch_service_tstate_nonfatal_lr10
lr10_device *chip_device = NVSWITCH_GET_CHIP_DEVICE_LR10(device);
NVSWITCH_INTERRUPT_LOG_TYPE report = { 0 };
NvU32 pending, bit, unhandled;
NVSWITCH_RAW_ERROR_LOG_TYPE data = {{ 0 }};
NVSWITCH_RAW_ERROR_LOG_TYPE data = {0, { 0 }};
INFOROM_NVS_ECC_ERROR_EVENT err_event = {0};
report.raw_pending = NVSWITCH_NPORT_RD32_LR10(device, link, _TSTATE, _ERR_STATUS_0);
@@ -1906,7 +2104,11 @@ _nvswitch_service_tstate_nonfatal_lr10
NVSWITCH_NPORT_WR32_LR10(device, link, _TSTATE, _ERR_TAGPOOL_ECC_ERROR_COUNTER,
DRF_DEF(_TSTATE, _ERR_TAGPOOL_ECC_ERROR_COUNTER, _ERROR_COUNT, _INIT));
NVSWITCH_REPORT_NONFATAL(_HW_NPORT_TSTATE_TAGPOOL_ECC_LIMIT_ERR, "TS tag store single-bit threshold");
_nvswitch_save_egress_err_header_lr10(device, link, &data);
_nvswitch_collect_error_info_lr10(device, link,
NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_EGRESS_TIME |
NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_EGRESS_MISC |
NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_EGRESS_HDR,
&data);
NVSWITCH_REPORT_DATA(_HW_NPORT_TSTATE_TAGPOOL_ECC_LIMIT_ERR, data);
_nvswitch_construct_ecc_error_event(&err_event,
@@ -1943,7 +2145,11 @@ _nvswitch_service_tstate_nonfatal_lr10
NVSWITCH_NPORT_WR32_LR10(device, link, _TSTATE, _ERR_CRUMBSTORE_ECC_ERROR_COUNTER,
DRF_DEF(_TSTATE, _ERR_CRUMBSTORE_ECC_ERROR_COUNTER, _ERROR_COUNT, _INIT));
NVSWITCH_REPORT_NONFATAL(_HW_NPORT_TSTATE_CRUMBSTORE_ECC_LIMIT_ERR, "TS crumbstore single-bit threshold");
_nvswitch_save_ingress_err_header_lr10(device, link, &data);
_nvswitch_collect_error_info_lr10(device, link,
NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_INGRESS_TIME |
NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_INGRESS_MISC |
NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_INGRESS_HDR,
&data);
NVSWITCH_REPORT_DATA(_HW_NPORT_TSTATE_CRUMBSTORE_ECC_LIMIT_ERR, data);
_nvswitch_construct_ecc_error_event(&err_event,
@@ -1992,7 +2198,7 @@ _nvswitch_service_tstate_fatal_lr10
lr10_device *chip_device = NVSWITCH_GET_CHIP_DEVICE_LR10(device);
NVSWITCH_INTERRUPT_LOG_TYPE report = { 0 };
NvU32 pending, bit, contain, unhandled;
NVSWITCH_RAW_ERROR_LOG_TYPE data = {{ 0 }};
NVSWITCH_RAW_ERROR_LOG_TYPE data = {0, { 0 }};
INFOROM_NVS_ECC_ERROR_EVENT err_event = {0};
report.raw_pending = NVSWITCH_NPORT_RD32_LR10(device, link, _TSTATE, _ERR_STATUS_0);
@@ -2014,7 +2220,11 @@ _nvswitch_service_tstate_fatal_lr10
if (nvswitch_test_flags(pending, bit))
{
NVSWITCH_REPORT_CONTAIN(_HW_NPORT_TSTATE_TAGPOOLBUFERR, "TS pointer crossover", NV_FALSE);
_nvswitch_save_egress_err_header_lr10(device, link, &data);
_nvswitch_collect_error_info_lr10(device, link,
NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_EGRESS_TIME |
NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_EGRESS_MISC |
NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_EGRESS_HDR,
&data);
NVSWITCH_REPORT_CONTAIN_DATA(_HW_NPORT_TSTATE_TAGPOOLBUFERR, data);
nvswitch_clear_flags(&unhandled, bit);
}
@@ -2039,7 +2249,11 @@ _nvswitch_service_tstate_fatal_lr10
NVSWITCH_NPORT_WR32_LR10(device, link, _TSTATE, _ERR_TAGPOOL_ECC_ERROR_COUNTER,
DRF_DEF(_TSTATE, _ERR_TAGPOOL_ECC_ERROR_COUNTER, _ERROR_COUNT, _INIT));
NVSWITCH_REPORT_CONTAIN(_HW_NPORT_TSTATE_TAGPOOL_ECC_DBE_ERR, "TS tag store fatal ECC", NV_FALSE);
_nvswitch_save_egress_err_header_lr10(device, link, &data);
_nvswitch_collect_error_info_lr10(device, link,
NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_EGRESS_TIME |
NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_EGRESS_MISC |
NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_EGRESS_HDR,
&data);
NVSWITCH_REPORT_CONTAIN_DATA(_HW_NPORT_TSTATE_TAGPOOL_ECC_DBE_ERR, data);
nvswitch_clear_flags(&unhandled, bit);
@@ -2061,7 +2275,11 @@ _nvswitch_service_tstate_fatal_lr10
if (nvswitch_test_flags(pending, bit))
{
NVSWITCH_REPORT_CONTAIN(_HW_NPORT_TSTATE_CRUMBSTOREBUFERR, "TS crumbstore", NV_FALSE);
_nvswitch_save_egress_err_header_lr10(device, link, &data);
_nvswitch_collect_error_info_lr10(device, link,
NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_EGRESS_TIME |
NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_EGRESS_MISC |
NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_EGRESS_HDR,
&data);
NVSWITCH_REPORT_CONTAIN_DATA(_HW_NPORT_TSTATE_CRUMBSTOREBUFERR, data);
nvswitch_clear_flags(&unhandled, bit);
}
@@ -2086,7 +2304,11 @@ _nvswitch_service_tstate_fatal_lr10
NVSWITCH_NPORT_WR32_LR10(device, link, _TSTATE, _ERR_CRUMBSTORE_ECC_ERROR_COUNTER,
DRF_DEF(_TSTATE, _ERR_CRUMBSTORE_ECC_ERROR_COUNTER, _ERROR_COUNT, _INIT));
NVSWITCH_REPORT_CONTAIN(_HW_NPORT_TSTATE_CRUMBSTORE_ECC_DBE_ERR, "TS crumbstore fatal ECC", NV_FALSE);
_nvswitch_save_ingress_err_header_lr10(device, link, &data);
_nvswitch_collect_error_info_lr10(device, link,
NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_INGRESS_TIME |
NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_INGRESS_MISC |
NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_INGRESS_HDR,
&data);
NVSWITCH_REPORT_CONTAIN_DATA(_HW_NPORT_TSTATE_CRUMBSTORE_ECC_DBE_ERR, data);
nvswitch_clear_flags(&unhandled, bit);
@@ -2119,7 +2341,11 @@ _nvswitch_service_tstate_fatal_lr10
if (nvswitch_test_flags(pending, bit))
{
NVSWITCH_REPORT_CONTAIN(_HW_NPORT_TSTATE_CAMRSP_ERR, "Rsp Tag value out of range", NV_FALSE);
_nvswitch_save_ingress_err_header_lr10(device, link, &data);
_nvswitch_collect_error_info_lr10(device, link,
NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_INGRESS_TIME |
NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_INGRESS_MISC |
NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_INGRESS_HDR,
&data);
NVSWITCH_REPORT_CONTAIN_DATA(_HW_NPORT_TSTATE_CAMRSP_ERR, data);
nvswitch_clear_flags(&unhandled, bit);
}
@@ -2160,7 +2386,7 @@ _nvswitch_service_egress_nonfatal_lr10
lr10_device *chip_device = NVSWITCH_GET_CHIP_DEVICE_LR10(device);
NVSWITCH_INTERRUPT_LOG_TYPE report = { 0 };
NvU32 pending, bit, unhandled;
NVSWITCH_RAW_ERROR_LOG_TYPE data = { { 0 } };
NVSWITCH_RAW_ERROR_LOG_TYPE data = {0, { 0 }};
INFOROM_NVS_ECC_ERROR_EVENT err_event = {0};
report.raw_pending = NVSWITCH_NPORT_RD32_LR10(device, link, _EGRESS, _ERR_STATUS_0);
@@ -2175,7 +2401,11 @@ _nvswitch_service_egress_nonfatal_lr10
unhandled = pending;
report.raw_first = NVSWITCH_NPORT_RD32_LR10(device, link, _EGRESS, _ERR_FIRST_0);
_nvswitch_save_egress_err_header_lr10(device, link, &data);
_nvswitch_collect_error_info_lr10(device, link,
NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_EGRESS_TIME |
NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_EGRESS_MISC |
NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_EGRESS_HDR,
&data);
bit = DRF_NUM(_EGRESS, _ERR_STATUS_0, _NXBAR_HDR_ECC_LIMIT_ERR, 1);
if (nvswitch_test_flags(pending, bit))
@@ -2293,9 +2523,9 @@ _nvswitch_service_egress_fatal_lr10
lr10_device *chip_device = NVSWITCH_GET_CHIP_DEVICE_LR10(device);
NVSWITCH_INTERRUPT_LOG_TYPE report = { 0 };
NvU32 pending, bit, contain, unhandled;
NVSWITCH_RAW_ERROR_LOG_TYPE data = {{ 0 }};
NVSWITCH_RAW_ERROR_LOG_TYPE credit_data = { { 0 } };
NVSWITCH_RAW_ERROR_LOG_TYPE buffer_data = { { 0 } };
NVSWITCH_RAW_ERROR_LOG_TYPE data = {0, { 0 }};
NVSWITCH_RAW_ERROR_LOG_TYPE credit_data = {0, { 0 }};
NVSWITCH_RAW_ERROR_LOG_TYPE buffer_data = {0, { 0 }};
INFOROM_NVS_ECC_ERROR_EVENT err_event = {0};
report.raw_pending = NVSWITCH_NPORT_RD32_LR10(device, link, _EGRESS, _ERR_STATUS_0);
@@ -2311,7 +2541,11 @@ _nvswitch_service_egress_fatal_lr10
unhandled = pending;
report.raw_first = NVSWITCH_NPORT_RD32_LR10(device, link, _EGRESS, _ERR_FIRST_0);
contain = NVSWITCH_NPORT_RD32_LR10(device, link, _EGRESS, _ERR_CONTAIN_EN_0);
_nvswitch_save_egress_err_header_lr10(device, link, &data);
_nvswitch_collect_error_info_lr10(device, link,
NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_EGRESS_TIME |
NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_EGRESS_MISC |
NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_EGRESS_HDR,
&data);
bit = DRF_NUM(_EGRESS, _ERR_STATUS_0, _EGRESSBUFERR, 1);
if (nvswitch_test_flags(pending, bit))

33
src/common/nvswitch/kernel/lr10/link_lr10.c
View File

@@ -77,10 +77,10 @@ nvswitch_setup_link_loopback_mode_lr10
}
}
if (device->link[link->linkNumber].ned)
if (device->link[link->linkNumber].nedr)
{
NVSWITCH_PRINT(device, ERROR,
"%s: Setting NED on link %d\n",
"%s: Setting NEDR on link %d\n",
__FUNCTION__, link->linkNumber);
// setting NEDR
@@ -92,7 +92,14 @@ nvswitch_setup_link_loopback_mode_lr10
"%s: SETNEDR CMD failed for link %d.\n",
__FUNCTION__, link->linkNumber);
}
}
if (device->link[link->linkNumber].nedw)
{
NVSWITCH_PRINT(device, ERROR,
"%s: Setting NEDW on link %d\n",
__FUNCTION__, link->linkNumber);
// setting NEDW
status = nvswitch_minion_send_command(device, link->linkNumber,
NV_MINION_NVLINK_DL_CMD_COMMAND_SETNEDW, 0);
@@ -147,7 +154,7 @@ _nvswitch_ioctrl_setup_link_plls_lr10
// Request Minion to setup the NVLink clocks
status = nvswitch_minion_send_command(device, linkId,
NV_MINION_NVLINK_DL_CMD_COMMAND_TXCLKSWITCH_PLL, 0);
NV_MINION_NVLINK_DL_CMD_COMMAND_TXCLKSWITCH_PLL, 0);
if (status != NV_OK)
{
NVSWITCH_PRINT(device, ERROR,
@@ -297,8 +304,8 @@ nvswitch_init_dlpl_interrupts_lr10
nvlink_link *link
)
{
nvswitch_device *device = link->dev->pDevInfo;
NvU32 linkNumber = link->linkNumber;
nvswitch_device *device = link->dev->pDevInfo;
NvU32 linkNumber = link->linkNumber;
NvU32 crcShortRegkeyVal = device->regkeys.crc_bit_error_rate_short;
NvU32 crcLongRegkeyVal = device->regkeys.crc_bit_error_rate_long;
NvU32 intrRegVal;
@@ -1027,7 +1034,7 @@ nvswitch_corelib_set_dl_link_mode_lr10
NVSWITCH_PRINT(device, ERROR,
"%s : INITPHASE1 failed for link (%s):(%s).\n",
__FUNCTION__, device->name, link->linkName);
NVSWITCH_ASSERT_INFO(NV_ERR_NVLINK_CONFIGURATION_ERROR,
NVSWITCH_ASSERT_INFO(NV_ERR_NVLINK_CONFIGURATION_ERROR,
NVBIT32(link->linkNumber), INITPHASE1_ERROR);
return NV_ERR_NVLINK_CONFIGURATION_ERROR;
}
@@ -1539,7 +1546,7 @@ nvswitch_corelib_get_tx_mode_lr10
*mode = NVLINK_SUBLINK_STATE_TX_OFF;
return NVL_SUCCESS;
}
data = NVSWITCH_LINK_RD32_LR10(device, link->linkNumber, NVLDL, _NVLDL_TX, _SLSM_STATUS_TX);
tx_sublink_state = DRF_VAL(_NVLDL_TX, _SLSM_STATUS_TX, _PRIMARY_STATE, data);
@@ -1761,7 +1768,7 @@ nvswitch_corelib_get_rx_mode_lr10
*mode = NVLINK_SUBLINK_STATE_RX_OFF;
return NVL_SUCCESS;
}
data = NVSWITCH_LINK_RD32_LR10(device, link->linkNumber, NVLDL, _NVLDL_RX, _SLSM_STATUS_RX);
rx_sublink_state = DRF_VAL(_NVLDL_RX, _SLSM_STATUS_RX, _PRIMARY_STATE, data);
@@ -2036,3 +2043,13 @@ nvswitch_apply_recal_settings_lr10
return;
}
NvlStatus
nvswitch_launch_ALI_link_training_lr10
(
nvswitch_device *device,
nvlink_link *link,
NvBool bSync
)
{
return NVL_ERR_NOT_IMPLEMENTED;
}

192
src/common/nvswitch/kernel/lr10/lr10.c
View File

@@ -400,17 +400,6 @@ _nvswitch_setup_link_system_registers_lr10
DRF_VAL(_NVLINK_VBIOS,_PARAM6,_TXTRAIN_MINIMUM_TRAIN_TIME_MANTISSA, vbios_link_entry->nvLinkparam6),
regval);
}
else
{
//
// Default working configuration for LR10
// This will be provided by VBIOS once support available (bug 2767390)
//
NVSWITCH_PRINT(device, SETUP, "%s: MINIMUM_TRAIN_TIME_MANTISSA = 0x5 forced by driver\n",
__FUNCTION__);
regval = FLD_SET_DRF_NUM(_NVLIPT_LNK_CTRL_SYSTEM_LINK, _CHANNEL_CTRL,
_TXTRAIN_MINIMUM_TRAIN_TIME_MANTISSA, 0x5, regval);
}
fldval = DRF_VAL(_SWITCH_REGKEY, _TXTRAIN_CONTROL, _MINIMUM_TRAIN_TIME_EXPONENT,
device->regkeys.txtrain_control);
@@ -427,17 +416,6 @@ _nvswitch_setup_link_system_registers_lr10
DRF_VAL(_NVLINK_VBIOS,_PARAM6,_TXTRAIN_MINIMUM_TRAIN_TIME_EXPONENT, vbios_link_entry->nvLinkparam6),
regval);
}
else
{
//
// Default working configuration for LR10
// This will be provided by VBIOS once support available (bug 2767390)
//
NVSWITCH_PRINT(device, SETUP, "%s: MINIMUM_TRAIN_TIME_EXPONENT = 0x4 forced by driver\n",
__FUNCTION__);
regval = FLD_SET_DRF_NUM(_NVLIPT_LNK_CTRL_SYSTEM_LINK, _CHANNEL_CTRL,
_TXTRAIN_MINIMUM_TRAIN_TIME_EXPONENT, 0x4, regval);
}
NVSWITCH_LINK_WR32_LR10(device, link->linkNumber, NVLIPT_LNK,
_NVLIPT_LNK_CTRL_SYSTEM_LINK, _CHANNEL_CTRL, regval);
@@ -646,6 +624,27 @@ _nvswitch_vbios_read_structure
&unpacked_bytes, NULL);
}
NvlStatus
nvswitch_vbios_read_structure_lr10
(
nvswitch_device *device,
void *structure,
NvU32 offset,
NvU32 *ppacked_size,
const char *format
)
{
if (NV_OK == _nvswitch_vbios_read_structure(device, structure, offset, ppacked_size, format))
{
return NVL_SUCCESS;
}
else
{
return -NVL_ERR_GENERIC;
}
}
NvU8
_nvswitch_vbios_read8
(
@@ -974,19 +973,19 @@ _nvswitch_read_vbios_link_base_entry
return status;
}
NV_STATUS
_nvswitch_read_vbios_link_entries
NvlStatus
nvswitch_read_vbios_link_entries_lr10
(
nvswitch_device *device,
NvU32 tblPtr,
NvU32 expected_link_entriesCount,
NVLINK_CONFIG_DATA_LINKENTRY *link_entries,
NvU32 *identified_link_entriesCount
nvswitch_device *device,
NvU32 tblPtr,
NvU32 expected_link_entriesCount,
NVLINK_CONFIG_DATA_LINKENTRY *link_entries,
NvU32 *identified_link_entriesCount
)
{
NV_STATUS status = NV_ERR_INVALID_PARAMETER;
NvU32 i;
NVLINK_VBIOS_CONFIG_DATA_LINKENTRY vbios_link_entry;
NVLINK_VBIOS_CONFIG_DATA_LINKENTRY_20 vbios_link_entry;
*identified_link_entriesCount = 0;
for (i = 0; i < expected_link_entriesCount; i++)
@@ -994,7 +993,7 @@ _nvswitch_read_vbios_link_entries
status = _nvswitch_vbios_read_structure(device,
&vbios_link_entry,
tblPtr, (NvU32 *)0,
NVLINK_CONFIG_DATA_LINKENTRY_FMT);
NVLINK_CONFIG_DATA_LINKENTRY_FMT_20);
if (status != NV_OK)
{
NVSWITCH_PRINT(device, ERROR,
@@ -1009,7 +1008,7 @@ _nvswitch_read_vbios_link_entries
link_entries[i].nvLinkparam4 = (NvU8)vbios_link_entry.nvLinkparam4;
link_entries[i].nvLinkparam5 = (NvU8)vbios_link_entry.nvLinkparam5;
link_entries[i].nvLinkparam6 = (NvU8)vbios_link_entry.nvLinkparam6;
tblPtr += sizeof(NVLINK_CONFIG_DATA_LINKENTRY);
tblPtr += (sizeof(NVLINK_VBIOS_CONFIG_DATA_LINKENTRY_20)/sizeof(NvU32));
NVSWITCH_PRINT(device, SETUP,
"<<<---- NvLink ID 0x%x ---->>>\n", i);
@@ -1038,7 +1037,7 @@ NV_STATUS
_nvswitch_vbios_fetch_nvlink_entries
(
nvswitch_device *device,
NVSWITCH_BIOS_NVLINK_CONFIG *bios_config
NVSWITCH_BIOS_NVLINK_CONFIG *bios_config
)
{
NvU32 tblPtr;
@@ -1063,6 +1062,7 @@ _nvswitch_vbios_fetch_nvlink_entries
switch (version)
{
case NVLINK_CONFIG_DATA_HEADER_VER_20:
case NVLINK_CONFIG_DATA_HEADER_VER_30:
size = _nvswitch_vbios_read8(device, tblPtr + 1);
if (size == NVLINK_CONFIG_DATA_HEADER_20_SIZE)
{
@@ -1105,7 +1105,10 @@ _nvswitch_vbios_fetch_nvlink_entries
"Reserved \t0x%x\n", header.ver_20.Reserved);
NVSWITCH_PRINT(device, SETUP,
"<<<---- NvLink Header ---->>>\n");
if (header.ver_20.Version == NVLINK_CONFIG_DATA_HEADER_VER_20)
{
device->bIsNvlinkVbiosTableVersion2 = NV_TRUE;
}
expected_base_entry_count = header.ver_20.BaseEntryCount;
if (expected_base_entry_count > NVSWITCH_NUM_BIOS_NVLINK_CONFIG_BASE_ENTRY)
{
@@ -1130,13 +1133,19 @@ _nvswitch_vbios_fetch_nvlink_entries
// Grab Nvlink Config Data Base Entry
_nvswitch_read_vbios_link_base_entry(device, tblPtr, &bios_config->link_vbios_base_entry[base_entry_index]);
tblPtr += header.ver_20.BaseEntrySize;
_nvswitch_read_vbios_link_entries(device,
device->hal.nvswitch_read_vbios_link_entries(device,
tblPtr,
expected_link_entriesCount,
bios_config->link_vbios_entry[base_entry_index],
&bios_config->identified_Link_entries[base_entry_index]);
tblPtr += (expected_link_entriesCount * sizeof(NVLINK_CONFIG_DATA_LINKENTRY));
if (device->bIsNvlinkVbiosTableVersion2)
{
tblPtr += (expected_link_entriesCount * (sizeof(NVLINK_VBIOS_CONFIG_DATA_LINKENTRY_20)/sizeof(NvU32)));
}
else
{
tblPtr += (expected_link_entriesCount * (sizeof(NVLINK_VBIOS_CONFIG_DATA_LINKENTRY_30)/sizeof(NvU32)));
}
}
vbios_fetch_nvlink_entries_done:
return status;
@@ -1233,7 +1242,7 @@ _nvswitch_setup_link_vbios_overrides
if (_nvswitch_vbios_fetch_nvlink_entries(device, bios_config) != NV_OK)
{
NVSWITCH_PRINT(device, ERROR,
"%s: Error on identifying pci image loc\n",
"%s: Error on fetching nvlink entries\n",
__FUNCTION__);
status = NV_ERR_GENERIC;
goto setup_link_vbios_overrides_done;
@@ -1880,8 +1889,8 @@ nvswitch_initialize_ip_wrappers_lr10
//
// Bring units out of warm reset on boot. Used by driver load.
//
static void
_nvswitch_init_warm_reset_lr10
void
nvswitch_init_warm_reset_lr10
(
nvswitch_device *device
)
@@ -3302,8 +3311,8 @@ _nvswitch_process_firmware_info_lr10
}
}
static void
_nvswitch_init_npg_multicast_lr10
void
nvswitch_init_npg_multicast_lr10
(
nvswitch_device *device
)
@@ -4029,8 +4038,8 @@ nvswitch_initialize_device_state_lr10
goto nvswitch_initialize_device_state_exit;
}
_nvswitch_init_warm_reset_lr10(device);
_nvswitch_init_npg_multicast_lr10(device);
nvswitch_init_warm_reset(device);
nvswitch_init_npg_multicast(device);
retval = nvswitch_clear_nport_rams(device);
if (NVL_SUCCESS != retval)
{
@@ -4352,6 +4361,11 @@ nvswitch_ctrl_get_nvlink_status_lr10
ret->linkInfo[i].nvlinkVersion = NVSWITCH_NVLINK_STATUS_NVLINK_VERSION_3_0;
ret->linkInfo[i].nciVersion = NVSWITCH_NVLINK_STATUS_NCI_VERSION_3_0;
}
else if (nvlink_caps_version == NVSWITCH_NVLINK_CAPS_NVLINK_VERSION_4_0)
{
ret->linkInfo[i].nvlinkVersion = NVSWITCH_NVLINK_STATUS_NVLINK_VERSION_4_0;
ret->linkInfo[i].nciVersion = NVSWITCH_NVLINK_STATUS_NCI_VERSION_4_0;
}
else
{
NVSWITCH_PRINT(device, WARN,
@@ -4872,6 +4886,22 @@ nvswitch_ctrl_get_info_lr10
}
}
break;
case NVSWITCH_GET_INFO_INDEX_REMAP_POLICY_MULTICAST_TABLE_SIZE:
{
NvU32 remap_ram_sel;
NvlStatus status;
status = nvswitch_get_remap_table_selector(device, NVSWITCH_TABLE_SELECT_REMAP_MULTICAST, &remap_ram_sel);
if (status == NVL_SUCCESS)
{
p->info[i] = nvswitch_get_ingress_ram_size(device, remap_ram_sel);
}
else
{
p->info[i] = 0;
}
}
break;
case NVSWITCH_GET_INFO_INDEX_ROUTING_ID_TABLE_SIZE:
p->info[i] = nvswitch_get_ingress_ram_size(device, NV_INGRESS_REQRSPMAPADDR_RAM_SEL_SELECTSRIDROUTERAM);
break;
@@ -5838,6 +5868,9 @@ nvswitch_reset_and_drain_links_lr10
}
FOR_EACH_INDEX_IN_MASK_END;
// Launch ALI training if applicable
(void)nvswitch_launch_ALI(device);
nvswitch_reset_and_drain_links_exit:
nvswitch_os_free(nport_reg_val);
return status;
@@ -6828,6 +6861,62 @@ nvswitch_ctrl_get_rb_stall_busy_lr10
return -NVL_ERR_NOT_SUPPORTED;
}
/*
* CTRL_NVSWITCH_GET_MULTICAST_ID_ERROR_VECTOR
*/
static NvlStatus
nvswitch_ctrl_get_multicast_id_error_vector_lr10
(
nvswitch_device *device,
NVSWITCH_GET_MULTICAST_ID_ERROR_VECTOR *p
)
{
NVSWITCH_PRINT(device, ERROR,
"GET_MULTICAST_ID_ERROR_VECTOR should not be called on LR10\n");
return -NVL_ERR_NOT_SUPPORTED;
}
/*
* CTRL_NVSWITCH_CLEAR_MULTICAST_ID_ERROR_VECTOR
*/
static NvlStatus
nvswitch_ctrl_clear_multicast_id_error_vector_lr10
(
nvswitch_device *device,
NVSWITCH_CLEAR_MULTICAST_ID_ERROR_VECTOR *p
)
{
NVSWITCH_PRINT(device, ERROR,
"CLEAR_MULTICAST_ID_ERROR_VECTOR should not be called on LR10\n");
return -NVL_ERR_NOT_SUPPORTED;
}
/*
* CTRL_NVSWITCH_INBAND_SEND_DATA
*/
NvlStatus
nvswitch_ctrl_inband_send_data_lr10
(
nvswitch_device *device,
NVSWITCH_INBAND_SEND_DATA_PARAMS *p
)
{
return -NVL_ERR_NOT_SUPPORTED;
}
/*
* CTRL_NVSWITCH_INBAND_RECEIVE_DATA
*/
NvlStatus
nvswitch_ctrl_inband_read_data_lr10
(
nvswitch_device *device,
NVSWITCH_INBAND_READ_DATA_PARAMS *p
)
{
return -NVL_ERR_NOT_SUPPORTED;
}
/*
* @brief: This function retrieves the NVLIPT public ID for a given global link idx
* @params[in] device reference to current nvswitch device
@@ -6943,14 +7032,23 @@ void nvswitch_init_scratch_lr10
continue;
}
reg = NVSWITCH_LINK_RD32_LR10(device, linkId, NPORT, _NPORT, _SCRATCH_WARM);
reg = NVSWITCH_LINK_RD32(device, linkId, NPORT, _NPORT, _SCRATCH_WARM);
if (reg == NV_NPORT_SCRATCH_WARM_DATA_INIT)
{
NVSWITCH_LINK_WR32_LR10(device, linkId, NPORT, _NPORT, _SCRATCH_WARM, 0);
NVSWITCH_LINK_WR32(device, linkId, NPORT, _NPORT, _SCRATCH_WARM, 0);
}
}
}
NvlStatus
nvswitch_launch_ALI_lr10
(
nvswitch_device *device
)
{
return -NVL_ERR_NOT_SUPPORTED;
}
NvlStatus
nvswitch_set_training_mode_lr10
(
@@ -6984,6 +7082,7 @@ nvswitch_parse_bios_image_lr10
status = _nvswitch_setup_link_vbios_overrides(device, bios_config);
if ((status != NV_OK) && device->pSoe)
{
//To enable LS10 bringup (VBIOS is not ready and SOE is disabled), fail the device init only when SOE is enabled and vbios overrides has failed
NVSWITCH_PRINT(device, ERROR,
"%s: error=0x%x\n",
__FUNCTION__, status);
@@ -7063,4 +7162,5 @@ void nvswitch_setup_hal_lr10(nvswitch_device *device)
}
NVSWITCH_INIT_HAL(device, lr10);
NVSWITCH_INIT_HAL_LS10(device, lr10);
}

1
src/common/nvswitch/kernel/lr10/pmgr_lr10.c
View File

@@ -30,6 +30,7 @@
#include "lr10/pmgr_lr10.h"
#include "nvswitch/lr10/dev_pmgr.h"
// Shared with LS10
void _nvswitch_i2c_set_port_pmgr(nvswitch_device *device, NvU32 port);
/*! The number of nanoseconds we will wait for slave clock stretching.

451
src/common/nvswitch/kernel/lr10/soe_lr10.c
View File

@@ -45,23 +45,6 @@
#include "rmflcncmdif_nvswitch.h"
/*
* @Brief : Selects SOE core (Falcon or Riscv)
*
* @param[in] device Bootstrap SOE on this device
*
* Does nothing on LR10
*/
NvlStatus
nvswitch_soe_set_ucode_core_lr10
(
nvswitch_device *device,
NvBool bFalcon
)
{
return NVL_SUCCESS;
}
/*
* @Brief : Reset SOE at the engine level.
*
@@ -74,7 +57,6 @@ _nvswitch_reset_soe
)
{
NvU32 value;
NvlStatus status;
// Assert reset
value = NVSWITCH_SOE_RD32_LR10(device, 0, _SOE_FALCON, _ENGINE);
@@ -92,15 +74,6 @@ _nvswitch_reset_soe
value = FLD_SET_DRF(_SOE, _FALCON, _ENGINE_RESET, _FALSE, value);
NVSWITCH_SOE_WR32_LR10(device, 0, _SOE_FALCON, _ENGINE, value);
// Set SOE ucode core to falcon
status = nvswitch_soe_set_ucode_core(device, NV_TRUE);
if (status != NVL_SUCCESS)
{
NVSWITCH_PRINT(device, ERROR,
"Failed to set SOE core\n");
return status;
}
// Wait for reset to complete
if (flcnWaitForResetToFinish_HAL(device, device->pSoe->pFlcn) != NV_OK)
{
@@ -257,8 +230,8 @@ _nvswitch_soe_send_test_cmd
return status;
}
NvlStatus
nvswitch_get_soe_ucode_binaries_lr10
static NvlStatus
_nvswitch_get_soe_ucode_binaries
(
nvswitch_device *device,
const NvU32 **soe_ucode_data,
@@ -307,7 +280,7 @@ _nvswitch_load_soe_ucode_image
const NvU32 *soe_ucode_data;
const NvU32 *soe_ucode_header;
status = nvswitch_get_soe_ucode_binaries(device, &soe_ucode_data, &soe_ucode_header);
status = _nvswitch_get_soe_ucode_binaries(device, &soe_ucode_data, &soe_ucode_header);
if (status != NVL_SUCCESS)
{
NVSWITCH_PRINT(device, ERROR,
@@ -774,8 +747,8 @@ _nvswitch_soe_request_reset_permissions
/*
* @Brief : Execute SOE pre-reset sequence for secure reset.
*/
NvlStatus
nvswitch_soe_prepare_for_reset_lr10
static NvlStatus
_nvswitch_soe_prepare_for_reset
(
nvswitch_device *device
)
@@ -835,7 +808,7 @@ nvswitch_init_soe_lr10
NvlStatus status;
// Prepare SOE for reset.
status = nvswitch_soe_prepare_for_reset(device);
status = _nvswitch_soe_prepare_for_reset(device);
if (status != NVL_SUCCESS)
{
NVSWITCH_PRINT_SXID(device, NVSWITCH_ERR_HW_SOE_RESET,
@@ -1086,7 +1059,7 @@ _soeService_LR10
NVSWITCH_PRINT(device, INFO,
"%s: Received a message from SOE via SWGEN0\n",
__FUNCTION__);
soeProcessMessages(device, pSoe);
soeProcessMessages_HAL(device, pSoe);
bRecheckMsgQ = NV_TRUE;
}
@@ -2161,6 +2134,413 @@ _soeSetPcieLinkSpeed_LR10
return NVL_SUCCESS;
}
/*!
* Use the SOE INIT Message to construct and initialize all SOE Queues.
*
* @param[in] device nvswitch_device pointer
* @param[in] pSoe SOE object pointer
* @param[in] pMsg Pointer to the INIT Message
*
* @return 'NV_OK' upon successful creation of all SOE Queues
*/
static NV_STATUS
_soeQMgrCreateQueuesFromInitMsg
(
nvswitch_device *device,
PFLCNABLE pSoe,
RM_FLCN_MSG_SOE *pMsg
)
{
RM_SOE_INIT_MSG_SOE_INIT *pInit;
NvU32 i;
NvU32 queueLogId;
NV_STATUS status;
FLCNQUEUE *pQueue;
PFLCN pFlcn = ENG_GET_FLCN(pSoe);
PFALCON_QUEUE_INFO pQueueInfo;
NVSWITCH_ASSERT(pFlcn != NULL);
pQueueInfo = pFlcn->pQueueInfo;
NVSWITCH_ASSERT(pQueueInfo != NULL);
pInit = &pMsg->msg.init.soeInit;
NVSWITCH_ASSERT(pInit->numQueues <= pFlcn->numQueues);
for (i = 0; i < pFlcn->numQueues; i++)
{
queueLogId = pInit->qInfo[i].queueLogId;
NVSWITCH_ASSERT(queueLogId < pFlcn->numQueues);
pQueue = &pQueueInfo->pQueues[queueLogId];
status = flcnQueueConstruct_dmem_nvswitch(
device,
pFlcn,
&pQueue, // ppQueue
queueLogId, // Logical ID of the queue
pInit->qInfo[i].queuePhyId, // Physical ID of the queue
pInit->qInfo[i].queueOffset, // offset
pInit->qInfo[i].queueSize, // size
RM_FLCN_QUEUE_HDR_SIZE); // cmdHdrSize
if (status != NV_OK)
{
NVSWITCH_PRINT(device, ERROR,
"%s: Error constructing SOE Queue (status="
"0x%08x).\n", __FUNCTION__, status);
NVSWITCH_ASSERT(0);
return status;
}
}
return NV_OK;
}
/*!
* Purges all the messages from the SOE's message queue. Each message will
* be analyzed, clients will be notified of status, and events will be routed
* to all registered event listeners.
*
* @param[in] device nvswitch_device pointer
* @param[in] pSoe SOE object pointer
*
* @return 'NV_OK' if the message queue was successfully purged.
*/
static NV_STATUS
_soeProcessMessages_LR10
(
nvswitch_device *device,
PSOE pSoe
)
{
RM_FLCN_MSG_SOE soeMessage;
NV_STATUS status;
PFLCN pFlcn = ENG_GET_FLCN(pSoe);
// keep processing messages until no more exist in the message queue
while (NV_OK == (status = flcnQueueReadData(
device,
pFlcn,
SOE_RM_MSGQ_LOG_ID,
(RM_FLCN_MSG *)&soeMessage, NV_TRUE)))
{
NVSWITCH_PRINT(device, INFO,
"%s: unitId=0x%02x, size=0x%02x, ctrlFlags=0x%02x, " \
"seqNumId=0x%02x\n",
__FUNCTION__,
soeMessage.hdr.unitId,
soeMessage.hdr.size,
soeMessage.hdr.ctrlFlags,
soeMessage.hdr.seqNumId);
// check to see if the message is a reply or an event.
if ((soeMessage.hdr.ctrlFlags &= RM_FLCN_QUEUE_HDR_FLAGS_EVENT) != 0)
{
flcnQueueEventHandle(device, pFlcn, (RM_FLCN_MSG *)&soeMessage, NV_OK);
}
// the message is a response from a previously queued command
else
{
flcnQueueResponseHandle(device, pFlcn, (RM_FLCN_MSG *)&soeMessage);
}
}
//
// Status NV_ERR_NOT_READY implies, Queue is empty.
// Log the message in other error cases.
//
if (status != NV_ERR_NOT_READY)
{
NVSWITCH_PRINT(device, ERROR,
"%s: unexpected error while purging message queue (status=0x%x).\n",
__FUNCTION__, (status));
}
return status;
}
/*!
* @brief Read the INIT message directly out of the Message Queue.
*
* This function accesses the Message Queue directly using the HAL. It does
* NOT and may NOT use the queue manager as it has not yet been constructed and
* initialized. The Message Queue may not be empty when this function is called
* and the first message in the queue MUST be the INIT message.
*
* @param[in] device nvswitch_device pointer
* @param[in] pSoe SOE object pointer
* @param[out] pMsg Message structure to fill with the INIT message data
*
* @return 'NV_OK' upon successful extraction of the INIT message.
* @return
* 'NV_ERR_INVALID_STATE' if the first message found was not an INIT
* message or if the message was improperly formatted.
*/
static NV_STATUS
_soeGetInitMessage
(
nvswitch_device *device,
PSOE pSoe,
RM_FLCN_MSG_SOE *pMsg
)
{
PFLCN pFlcn = ENG_GET_FLCN(pSoe);
NV_STATUS status = NV_OK;
NvU32 tail = 0;
PFALCON_QUEUE_INFO pQueueInfo;
// on the GPU, rmEmemPortId = sec2RmEmemPortIdGet_HAL(...);
NvU8 rmEmemPortId = 0;
if (pFlcn == NULL)
{
NVSWITCH_ASSERT(pFlcn != NULL);
return NV_ERR_INVALID_POINTER;
}
pQueueInfo = pFlcn->pQueueInfo;
if (pQueueInfo == NULL)
{
NVSWITCH_ASSERT(pQueueInfo != NULL);
return NV_ERR_INVALID_POINTER;
}
//
// Message queue 0 is used by SOE to communicate with RM
// Check SOE_CMDMGMT_MSG_QUEUE_RM in //uproc/soe/inc/soe_cmdmgmt.h
//
pQueueInfo->pQueues[SOE_RM_MSGQ_LOG_ID].queuePhyId = 0;
// read the header starting at the current tail position
(void)flcnMsgQueueTailGet(device, pFlcn,
&pQueueInfo->pQueues[SOE_RM_MSGQ_LOG_ID], &tail);
if (pFlcn->bEmemEnabled)
{
//
// We use the offset in DMEM for the src address, since
// EmemCopyFrom automatically converts it to the offset in EMEM
//
flcnableEmemCopyFrom(
device, pFlcn->pFlcnable,
tail, // src
(NvU8 *)&pMsg->hdr, // pDst
RM_FLCN_QUEUE_HDR_SIZE, // numBytes
rmEmemPortId); // port
}
else
{
status = flcnDmemCopyFrom(device,
pFlcn,
tail, // src
(NvU8 *)&pMsg->hdr, // pDst
RM_FLCN_QUEUE_HDR_SIZE, // numBytes
0); // port
if (status != NV_OK)
{
NVSWITCH_PRINT(device, ERROR,
"%s: Failed to copy from SOE DMEM\n", __FUNCTION__);
NVSWITCH_ASSERT(0);
goto _soeGetInitMessage_exit;
}
}
if (pMsg->hdr.unitId != RM_SOE_UNIT_INIT)
{
status = NV_ERR_INVALID_STATE;
NVSWITCH_ASSERT(0);
goto _soeGetInitMessage_exit;
}
// read the message body and update the tail position
if (pFlcn->bEmemEnabled)
{
//
// We use the offset in DMEM for the src address, since
// EmemCopyFrom automatically converts it to the offset in EMEM
//
flcnableEmemCopyFrom(
device, pFlcn->pFlcnable,
tail + RM_FLCN_QUEUE_HDR_SIZE, // src
(NvU8 *)&pMsg->msg, // pDst
pMsg->hdr.size - RM_FLCN_QUEUE_HDR_SIZE, // numBytes
rmEmemPortId); // port
}
else
{
status = flcnDmemCopyFrom(device,
pFlcn,
tail + RM_FLCN_QUEUE_HDR_SIZE, // src
(NvU8 *)&pMsg->msg, // pDst
pMsg->hdr.size - RM_FLCN_QUEUE_HDR_SIZE, // numBytes
0); // port
if (status != NV_OK)
{
NVSWITCH_PRINT(device, ERROR,
"%s: Failed to copy from SOE DMEM\n", __FUNCTION__);
NVSWITCH_ASSERT(0);
goto _soeGetInitMessage_exit;
}
}
tail += NV_ALIGN_UP(pMsg->hdr.size, SOE_DMEM_ALIGNMENT);
flcnMsgQueueTailSet(device, pFlcn,
&pQueueInfo->pQueues[SOE_RM_MSGQ_LOG_ID], tail);
_soeGetInitMessage_exit:
return status;
}
/*!
* This function exists to solve a natural chicken-and-egg problem that arises
* due to the fact that queue information (location, size, id, etc...) is
* relayed to the RM as a message in a queue. Queue construction is done when
* the message arrives and the normal queue read/write functions are not
* available until construction is complete. Construction cannot be done until
* the message is read from the queue. Therefore, the very first message read
* from the Message Queue must be considered as a special-case and must NOT use
* any functionality provided by the SOE's queue manager.
*
* @param[in] device nvswitch_device pointer
* @param[in] pSoe SOE object pointer
*
* @return 'NV_OK'
* Upon successful extraction and processing of the first SOE message.
*/
static NV_STATUS
_soeProcessMessagesPreInit_LR10
(
nvswitch_device *device,
PSOE pSoe
)
{
RM_FLCN_MSG_SOE msg;
NV_STATUS status;
PFLCN pFlcn = ENG_GET_FLCN(pSoe);
// extract the "INIT" message (this is never expected to fail)
status = _soeGetInitMessage(device, pSoe, &msg);
if (status != NV_OK)
{
NVSWITCH_PRINT(device, ERROR,
"%s: Failed to extract the INIT message "
"from the SOE Message Queue (status=0x%08x).",
__FUNCTION__, status);
NVSWITCH_ASSERT(0);
return status;
}
//
// Now hookup the "real" message-processing function and handle the "INIT"
// message.
//
pSoe->base.pHal->processMessages = _soeProcessMessages_LR10;
return flcnQueueEventHandle(device, pFlcn, (RM_FLCN_MSG *)&msg, NV_OK);
}
/*!
* @brief Process the "INIT" message sent from the SOE ucode application.
*
* When the SOE ucode is done initializing, it will post an INIT message in
* the Message Queue that contains all the necessary attributes that are
* needed to enqueuing commands and extracting messages from the queues.
* The packet will also contain the offset and size of portion of DMEM that
* the RM must manage. Upon receiving this message it will be assume that
* the SOE is ready to start accepting commands.
*
* @param[in] device nvswitch_device pointer
* @param[in] pSoe SOE object pointer
* @param[in] pMsg Pointer to the event's message data
*
* @return 'NV_OK' if the event was successfully handled.
*/
static NV_STATUS
_soeHandleInitEvent_LR10
(
nvswitch_device *device,
PFLCNABLE pSoe,
RM_FLCN_MSG *pGenMsg
)
{
NV_STATUS status;
PFLCN pFlcn = ENG_GET_FLCN(pSoe);
RM_FLCN_MSG_SOE *pMsg = (RM_FLCN_MSG_SOE *)pGenMsg;
if (pFlcn == NULL)
{
NVSWITCH_ASSERT(pFlcn != NULL);
return NV_ERR_INVALID_POINTER;
}
NVSWITCH_PRINT(device, INFO,
"%s: Received INIT message from SOE\n",
__FUNCTION__);
//
// Pass the INIT message to the queue manager to allow it to create the
// queues.
//
status = _soeQMgrCreateQueuesFromInitMsg(device, pSoe, pMsg);
if (status != NV_OK)
{
NVSWITCH_ASSERT(0);
return status;
}
flcnDbgInfoDmemOffsetSet(device, pFlcn,
pMsg->msg.init.soeInit.osDebugEntryPoint);
// the SOE ucode is now initialized and ready to accept commands
pFlcn->bOSReady = NV_TRUE;
return NV_OK;
}
/*!
* Loop until SOE RTOS is loaded and gives us an INIT message
*
* @param[in] device nvswitch_device object pointer
* @param[in] pSoe SOE object pointer
*/
static NV_STATUS
_soeWaitForInitAck_LR10
(
nvswitch_device *device,
PSOE pSoe
)
{
PFLCN pFlcn = ENG_GET_FLCN(pSoe);
NVSWITCH_TIMEOUT timeout;
NvBool bKeepPolling;
// If INIT message is already loaded, return.
if (pFlcn->bOSReady)
{
return NV_OK;
}
nvswitch_timeout_create(NVSWITCH_INTERVAL_1SEC_IN_NS * 5, &timeout);
do
{
bKeepPolling = (nvswitch_timeout_check(&timeout)) ? NV_FALSE : NV_TRUE;
soeService_HAL(device, pSoe);
if (pFlcn->bOSReady)
{
return NV_OK;
}
nvswitch_os_sleep(1);
}
while (bKeepPolling);
if (!pFlcn->bOSReady)
{
NVSWITCH_PRINT(device, ERROR,
"%s Timeout while waiting for SOE bootup\n",
__FUNCTION__);
NVSWITCH_ASSERT(0);
return NV_ERR_TIMEOUT;
}
return NV_OK;
}
/*!
* @brief set hal function pointers for functions defined in LR10 (i.e. this file)
*
@@ -2182,6 +2562,7 @@ soeSetupHal_LR10
pParentHal->destruct = _soeDestruct_LR10;
pParentHal->getExternalConfig = _soeGetExternalConfig_LR10;
pParentHal->fetchEngines = _soeFetchEngines_LR10;
pParentHal->handleInitEvent = _soeHandleInitEvent_LR10;
// set any functions specific to SOE
pHal->service = _soeService_LR10;
@@ -2201,4 +2582,6 @@ soeSetupHal_LR10
pHal->forceThermalSlowdown = _soeForceThermalSlowdown_LR10;
pHal->setPcieLinkSpeed = _soeSetPcieLinkSpeed_LR10;
pHal->getPexEomStatus = _soeGetPexEomStatus_LR10;
pHal->processMessages = _soeProcessMessagesPreInit_LR10;
pHal->waitForInitAck = _soeWaitForInitAck_LR10;
}

367
src/common/nvswitch/kernel/nvswitch.c
View File

@@ -61,17 +61,22 @@
break; \
} \
//
// HW's device id list can be found here -
// P4hw:2001: hw\doc\engr\Dev_ID\DeviceID_master_list.txt
//
const static NvU32 nvswitch_lr10_device_ids[] =
{
0x1AE8, 0x1AF0, 0x1AF1, 0x1AF2, 0x1AF3, 0x1AF4, 0x1AF5, 0x1AF6, 0x1AF7,
0x1AF8, 0x1AF9, 0x1AFA, 0x1AFB, 0x1AFC, 0x1AFD, 0x1AFE, 0x1AFF
};
const static NvU32 nvswitch_ls10_device_ids[] =
{
// PCIE endpoint to manage the NVLink switch HW
0x22A0, 0x22A1, 0x22A2, 0x22A3, 0x22A4, 0x22A5, 0x22A6, 0x22A7,
// PCI-PCI Bridge, Laguna Switch Function 0
0x22A8, 0x22A9, 0x22AA, 0x22AB,
// Non-Transparent Bridge, Laguna Switch Function 1
0x22AC, 0x22AD, 0x22AE, 0x22AF
};
nvlink_link_handlers link_handlers;
static NvBool
@@ -107,6 +112,18 @@ nvswitch_is_lr10_device_id
return _nvswitch_is_device_id_present(nvswitch_lr10_device_ids, count, device_id);
}
NvBool
nvswitch_is_ls10_device_id
(
NvU32 device_id
)
{
NvU32 count = (sizeof(nvswitch_ls10_device_ids) /
sizeof(nvswitch_ls10_device_ids[0]));
return _nvswitch_is_device_id_present(nvswitch_ls10_device_ids, count, device_id);
}
/*
* NVLink corelib callbacks are used by the NVLink library separate from the
* NVSwitch driver, therefore they do not take a device lock and can not modify
@@ -283,6 +300,16 @@ _nvswitch_corelib_write_discovery_token
return NVL_SUCCESS;
}
static NV_API_CALL NvlStatus
_nvswitch_corelib_ali_training
(
nvlink_link *link
)
{
nvswitch_device *device = link->dev->pDevInfo;
return device->hal.nvswitch_launch_ALI_link_training(device, link, NV_FALSE);
}
void
nvswitch_get_link_handlers
(
@@ -310,6 +337,7 @@ nvswitch_get_link_handlers
nvswitch_link_handlers->training_complete = _nvswitch_corelib_training_complete;
nvswitch_link_handlers->get_uphy_load = _nvswitch_corelib_get_uphy_load;
nvswitch_link_handlers->write_discovery_token = _nvswitch_corelib_write_discovery_token;
nvswitch_link_handlers->ali_training = _nvswitch_corelib_ali_training;
}
#define NVSWITCH_INIT_REGKEY(_private, _regkey, _string, _default_val) \
@@ -358,7 +386,7 @@ _nvswitch_init_device_regkeys
NV_SWITCH_REGKEY_CRC_BIT_ERROR_RATE_LONG_OFF);
//
// Private internal use regkeys
// Debug use regkeys
// Not available on release build kernel drivers
//
NVSWITCH_INIT_REGKEY(_PRIVATE, external_fabric_mgmt,
@@ -429,9 +457,6 @@ _nvswitch_init_device_regkeys
NV_SWITCH_REGKEY_SOE_DISABLE,
NV_SWITCH_REGKEY_SOE_DISABLE_NO);
NVSWITCH_INIT_REGKEY(_PUBLIC, soe_boot_core,
NV_SWITCH_REGKEY_SOE_BOOT_CORE,
NV_SWITCH_REGKEY_SOE_BOOT_CORE_DEFAULT);
NVSWITCH_INIT_REGKEY(_PRIVATE, latency_counter,
NV_SWITCH_REGKEY_LATENCY_COUNTER_LOGGING,
NV_SWITCH_REGKEY_LATENCY_COUNTER_LOGGING_ENABLE);
@@ -472,6 +497,10 @@ _nvswitch_init_device_regkeys
NV_SWITCH_REGKEY_MINION_SELECT_UPHY_TABLES,
NV_SWITCH_REGKEY_MINION_SELECT_UPHY_TABLES_DEFAULT);
NVSWITCH_INIT_REGKEY(_PRIVATE, link_training_mode,
NV_SWITCH_REGKEY_LINK_TRAINING_SELECT,
NV_SWITCH_REGKEY_LINK_TRAINING_SELECT_DEFAULT);
NVSWITCH_INIT_REGKEY(_PRIVATE, i2c_access_control,
NV_SWITCH_REGKEY_I2C_ACCESS_CONTROL,
NV_SWITCH_REGKEY_I2C_ACCESS_CONTROL_DEFAULT);
@@ -604,15 +633,6 @@ nvswitch_is_smbpbi_supported
return device->hal.nvswitch_is_smbpbi_supported(device);
}
NvlStatus
nvswitch_soe_prepare_for_reset
(
nvswitch_device *device
)
{
return device->hal.nvswitch_soe_prepare_for_reset(device);
}
NvBool
nvswitch_is_soe_supported
(
@@ -628,16 +648,6 @@ nvswitch_is_soe_supported
return device->hal.nvswitch_is_soe_supported(device);
}
NvlStatus
nvswitch_soe_set_ucode_core
(
nvswitch_device *device,
NvBool bFalcon
)
{
return device->hal.nvswitch_soe_set_ucode_core(device, bFalcon);
}
NvlStatus
nvswitch_init_soe
(
@@ -1145,6 +1155,12 @@ nvswitch_lib_initialize_device
nvListInit(&device->client_events_list);
for (link_num=0; link_num < nvswitch_get_num_links(device); link_num++)
{
nvListInit(&device->link[link_num].inbandData.persistent_list);
nvListInit(&device->link[link_num].inbandData.nonpersistent_list);
}
retval = nvswitch_lib_load_platform_info(device);
if (retval != NVL_SUCCESS)
{
@@ -1363,6 +1379,10 @@ nvswitch_lib_validate_device_id
{
return NV_TRUE;
}
if (nvswitch_is_ls10_device_id(device_id))
{
return NV_TRUE;
}
return NV_FALSE;
}
@@ -1414,6 +1434,8 @@ nvswitch_lib_post_init_device
nvswitch_smbpbi_post_init(device);
(void)nvswitch_launch_ALI(device);
return NVL_SUCCESS;
}
@@ -1862,6 +1884,10 @@ nvswitch_lib_register_device
//
_nvswitch_init_device_regkeys(device);
// After regkeys have been set then only set the enableALI field.
device->nvlink_device->enableALI = (device->regkeys.link_training_mode ==
NV_SWITCH_REGKEY_LINK_TRAINING_SELECT_ALI) ? NV_TRUE:NV_FALSE;
retval = nvlink_lib_register_device(device->nvlink_device);
if (NVL_SUCCESS != retval)
{
@@ -2390,6 +2416,24 @@ _nvswitch_ctrl_set_ganged_link_table
return device->hal.nvswitch_ctrl_set_ganged_link_table(device, p);
}
void
nvswitch_init_npg_multicast
(
nvswitch_device *device
)
{
return device->hal.nvswitch_init_npg_multicast(device);
}
void
nvswitch_init_warm_reset
(
nvswitch_device *device
)
{
return device->hal.nvswitch_init_warm_reset(device);
}
static NvlStatus
_nvswitch_ctrl_set_remap_policy
(
@@ -2710,6 +2754,150 @@ _nvswitch_ctrl_get_rb_stall_busy
return device->hal.nvswitch_ctrl_get_rb_stall_busy(device, p);
}
NvlStatus
nvswitch_ctrl_get_multicast_id_error_vector
(
nvswitch_device *device,
NVSWITCH_GET_MULTICAST_ID_ERROR_VECTOR *p
)
{
return device->hal.nvswitch_ctrl_get_multicast_id_error_vector(device, p);
}
NvlStatus
nvswitch_ctrl_clear_multicast_id_error_vector
(
nvswitch_device *device,
NVSWITCH_CLEAR_MULTICAST_ID_ERROR_VECTOR *p
)
{
return device->hal.nvswitch_ctrl_clear_multicast_id_error_vector(device, p);
}
static NvlStatus
_nvswitch_ctrl_inband_send_data
(
nvswitch_device *device,
NVSWITCH_INBAND_SEND_DATA_PARAMS *p
)
{
return device->hal.nvswitch_ctrl_inband_send_data(device, p);
}
static NvlStatus
_nvswitch_ctrl_inband_read_data
(
nvswitch_device *device,
NVSWITCH_INBAND_READ_DATA_PARAMS *p
)
{
return device->hal.nvswitch_ctrl_inband_read_data(device, p);
}
/*
* @Brief : Deletes all the entires in persistant or nonpersistant list
*
* @Description :
*
* @param[in] device NvSwitch device to contain this link
* @param[in] linkId link number of the link
*
*/
static void
_nvswitch_inband_clear_list
(
nvswitch_device *device,
NvU32 linkId
)
{
nvswitch_inband_data_list *curr = NULL;
nvswitch_inband_data_list *next = NULL;
nvListForEachEntry_safe(curr, next, &device->link[linkId].inbandData.persistent_list, entry)
{
nvListDel(&curr->entry);
nvswitch_os_free(curr);
}
nvListForEachEntry_safe(curr, next, &device->link[linkId].inbandData.nonpersistent_list, entry)
{
nvListDel(&curr->entry);
nvswitch_os_free(curr);
}
}
static NvlStatus
_nvswitch_ctrl_inband_flush_data
(
nvswitch_device *device,
NVSWITCH_INBAND_FLUSH_DATA_PARAMS *p
)
{
NvU32 i;
NvU64 enabledLinkMask;
if (p->linkMask == 0)
{
NVSWITCH_PRINT(device, ERROR, "Nothing to clear\n");
return NVL_SUCCESS;
}
enabledLinkMask = nvswitch_get_enabled_link_mask(device);
FOR_EACH_INDEX_IN_MASK(64, i, p->linkMask)
{
if (nvswitch_is_link_valid(device, i) &&
(enabledLinkMask & NVBIT(i)))
{
_nvswitch_inband_clear_list(device, i);
}
}
FOR_EACH_INDEX_IN_MASK_END;
return NVL_SUCCESS;
}
static NvlStatus
_nvswitch_ctrl_inband_pending_data_stats
(
nvswitch_device *device,
NVSWITCH_INBAND_PENDING_DATA_STATS_PARAMS *p
)
{
NvU32 link_num;
NvU64 enabledLinkMask, persistent_mask = 0, nonpersistent_mask = 0;
enabledLinkMask = nvswitch_get_enabled_link_mask(device);
for (link_num = 0; link_num < nvswitch_get_num_links(device); link_num++)
{
if (nvswitch_is_link_valid(device, link_num) &&
(enabledLinkMask & NVBIT(link_num)))
{
if (!nvListIsEmpty(&device->link[link_num].inbandData.persistent_list))
{
persistent_mask |= NVBIT(link_num);
}
if (!nvListIsEmpty(&device->link[link_num].inbandData.nonpersistent_list))
{
nonpersistent_mask |= NVBIT(link_num);
}
}
}
if (persistent_mask > 0)
{
p->linkMask = persistent_mask;
}
else
{
p->linkMask = nonpersistent_mask;
}
return NVL_SUCCESS;
}
static NvlStatus
_nvswitch_ctrl_i2c_smbus_command
(
@@ -2884,6 +3072,72 @@ _nvswitch_lib_validate_privileged_ctrl
return -NVL_ERR_INSUFFICIENT_PERMISSIONS;
}
/*
* @Brief : Copy the data from the persistant or nonpersistant list
*
* @Description :
*
* @param[in] device NvSwitch device to contain this link
* @param[out] data Destination Data
* @param[in] linkId link number of the link
* @param[out] dataSize Size of data copied
*
* @returns NVL_SUCCESS if action succeeded,
* -NVL_NOT_FOUND if link doesnt have data
*/
NvlStatus
nvswitch_inband_read_data
(
nvswitch_device *device,
NvU8 *dest,
NvU32 linkId,
NvU32 *dataSize
)
{
nvswitch_inband_data_list *curr = NULL;
NVListRec *list;
if (nvListIsEmpty(&device->link[linkId].inbandData.persistent_list) &&
nvListIsEmpty(&device->link[linkId].inbandData.nonpersistent_list))
{
*dataSize = 0;
return -NVL_NOT_FOUND;
}
list = nvListIsEmpty(&device->link[linkId].inbandData.persistent_list) ?
&device->link[linkId].inbandData.nonpersistent_list :
&device->link[linkId].inbandData.persistent_list;
nvListForEachEntry(curr, list, entry)
{
*dataSize = curr->dataSize;
nvswitch_os_memcpy(dest, curr->data, curr->dataSize);
nvListDel(&curr->entry);
nvswitch_os_free(curr);
break;
}
return NVL_SUCCESS;
}
/*
* @Brief : Moves the data into persistant or nonpersistant list
*
* @Description :
*
* @param[in] device NvSwitch device to contain this link
* @param[in] linkId link number of the link
*
*/
void
nvswitch_filter_messages
(
nvswitch_device *device,
NvU32 linkId
)
{
}
/*
* @Brief : Constructs an NVS link struct with the given data
*
@@ -3769,17 +4023,6 @@ nvswitch_pri_ring_init
return(device->hal.nvswitch_pri_ring_init(device));
}
NvlStatus
nvswitch_get_soe_ucode_binaries
(
nvswitch_device *device,
const NvU32 **soe_ucode_data,
const NvU32 **soe_ucode_header
)
{
return device->hal.nvswitch_get_soe_ucode_binaries(device, soe_ucode_data, soe_ucode_header);
}
NvlStatus
nvswitch_get_remap_table_selector
(
@@ -3874,6 +4117,15 @@ nvswitch_init_lpwr_regs
device->hal.nvswitch_init_lpwr_regs(link);
}
NvlStatus
nvswitch_launch_ALI
(
nvswitch_device *device
)
{
return device->hal.nvswitch_launch_ALI(device);
}
NvlStatus
nvswitch_set_training_mode
(
@@ -3935,6 +4187,17 @@ nvswitch_apply_recal_settings
return device->hal.nvswitch_apply_recal_settings(device, link);
}
NvlStatus
nvswitch_launch_ALI_link_training
(
nvswitch_device *device,
nvlink_link *link,
NvBool bSync
)
{
return device->hal.nvswitch_launch_ALI_link_training(device, link, bSync);
}
NvlStatus
nvswitch_lib_ctrl
(
@@ -4195,6 +4458,32 @@ nvswitch_lib_ctrl
NVSWITCH_DEV_CMD_DISPATCH(CTRL_NVSWITCH_GET_RB_STALL_BUSY,
_nvswitch_ctrl_get_rb_stall_busy,
NVSWITCH_GET_RB_STALL_BUSY);
NVSWITCH_DEV_CMD_DISPATCH(CTRL_NVSWITCH_GET_MULTICAST_ID_ERROR_VECTOR,
nvswitch_ctrl_get_multicast_id_error_vector,
NVSWITCH_GET_MULTICAST_ID_ERROR_VECTOR);
NVSWITCH_DEV_CMD_DISPATCH(CTRL_NVSWITCH_CLEAR_MULTICAST_ID_ERROR_VECTOR,
nvswitch_ctrl_clear_multicast_id_error_vector,
NVSWITCH_CLEAR_MULTICAST_ID_ERROR_VECTOR);
NVSWITCH_DEV_CMD_DISPATCH_PRIVILEGED(
CTRL_NVSWITCH_INBAND_SEND_DATA,
_nvswitch_ctrl_inband_send_data,
NVSWITCH_INBAND_SEND_DATA_PARAMS,
osPrivate, flags);
NVSWITCH_DEV_CMD_DISPATCH_PRIVILEGED(
CTRL_NVSWITCH_INBAND_READ_DATA,
_nvswitch_ctrl_inband_read_data,
NVSWITCH_INBAND_READ_DATA_PARAMS,
osPrivate, flags);
NVSWITCH_DEV_CMD_DISPATCH_PRIVILEGED(
CTRL_NVSWITCH_INBAND_FLUSH_DATA,
_nvswitch_ctrl_inband_flush_data,
NVSWITCH_INBAND_FLUSH_DATA_PARAMS,
osPrivate, flags);
NVSWITCH_DEV_CMD_DISPATCH_PRIVILEGED(
CTRL_NVSWITCH_INBAND_PENDING_DATA_STATS,
_nvswitch_ctrl_inband_pending_data_stats,
NVSWITCH_INBAND_PENDING_DATA_STATS_PARAMS,
osPrivate, flags);
NVSWITCH_DEV_CMD_DISPATCH_PRIVILEGED(
CTRL_NVSWITCH_GET_SW_INFO,
_nvswitch_ctrl_get_sw_info,

32
src/common/nvswitch/kernel/soe/soe_call_hal_nvswitch.c
View File

@@ -343,3 +343,35 @@ soeSetPcieLinkSpeed_HAL
return pSoe->base.pHal->setPcieLinkSpeed(device, linkSpeed);
}
NV_STATUS
soeProcessMessages_HAL
(
nvswitch_device *device,
PSOE pSoe
)
{
if (pSoe->base.pHal->processMessages == NULL)
{
NVSWITCH_ASSERT(0);
return 0;
}
return pSoe->base.pHal->processMessages(device, pSoe);
}
NV_STATUS
soeWaitForInitAck_HAL
(
nvswitch_device *device,
PSOE pSoe
)
{
if (pSoe->base.pHal->waitForInitAck == NULL)
{
NVSWITCH_ASSERT(0);
return 0;
}
return pSoe->base.pHal->waitForInitAck(device, pSoe);
}

401
src/common/nvswitch/kernel/soe/soe_nvswitch.c
View File

@@ -31,365 +31,6 @@
#include "rmflcncmdif_nvswitch.h"
#include "common_nvswitch.h"
static NV_STATUS _soeGetInitMessage(nvswitch_device *device, PSOE pSoe, RM_FLCN_MSG_SOE *pMsg);
/*!
* Use the SOE INIT Message to construct and initialize all SOE Queues.
*
* @param[in] device nvswitch_device pointer
* @param[in] pSoe SOE object pointer
* @param[in] pMsg Pointer to the INIT Message
*
* @return 'NV_OK' upon successful creation of all SOE Queues
*/
static NV_STATUS
_soeQMgrCreateQueuesFromInitMsg
(
nvswitch_device *device,
PFLCNABLE pSoe,
RM_FLCN_MSG_SOE *pMsg
)
{
RM_SOE_INIT_MSG_SOE_INIT *pInit;
NvU32 i;
NvU32 queueLogId;
NV_STATUS status;
FLCNQUEUE *pQueue;
PFLCN pFlcn = ENG_GET_FLCN(pSoe);
PFALCON_QUEUE_INFO pQueueInfo;
NVSWITCH_ASSERT(pFlcn != NULL);
pQueueInfo = pFlcn->pQueueInfo;
NVSWITCH_ASSERT(pQueueInfo != NULL);
pInit = &pMsg->msg.init.soeInit;
NVSWITCH_ASSERT(pInit->numQueues <= pFlcn->numQueues);
for (i = 0; i < pFlcn->numQueues; i++)
{
queueLogId = pInit->qInfo[i].queueLogId;
NVSWITCH_ASSERT(queueLogId < pFlcn->numQueues);
pQueue = &pQueueInfo->pQueues[queueLogId];
status = flcnQueueConstruct_dmem_nvswitch(
device,
pFlcn,
&pQueue, // ppQueue
queueLogId, // Logical ID of the queue
pInit->qInfo[i].queuePhyId, // Physical ID of the queue
pInit->qInfo[i].queueOffset, // offset
pInit->qInfo[i].queueSize, // size
RM_FLCN_QUEUE_HDR_SIZE); // cmdHdrSize
if (status != NV_OK)
{
NVSWITCH_PRINT(device, ERROR,
"%s: Error constructing SOE Queue (status="
"0x%08x).\n", __FUNCTION__, status);
NVSWITCH_ASSERT(0);
return status;
}
}
return NV_OK;
}
/*!
* Purges all the messages from the SOE's message queue. Each message will
* be analyzed, clients will be notified of status, and events will be routed
* to all registered event listeners.
*
* @param[in] device nvswitch_device pointer
* @param[in] pSoe SOE object pointer
*
* @return 'NV_OK' if the message queue was successfully purged.
*/
static NV_STATUS
_soeProcessMessages_IMPL
(
nvswitch_device *device,
PSOE pSoe
)
{
RM_FLCN_MSG_SOE soeMessage;
NV_STATUS status;
PFLCN pFlcn = ENG_GET_FLCN(pSoe);
// keep processing messages until no more exist in the message queue
while (NV_OK == (status = flcnQueueReadData(
device,
pFlcn,
SOE_RM_MSGQ_LOG_ID,
(RM_FLCN_MSG *)&soeMessage, NV_TRUE)))
{
NVSWITCH_PRINT(device, INFO,
"%s: unitId=0x%02x, size=0x%02x, ctrlFlags=0x%02x, " \
"seqNumId=0x%02x\n",
__FUNCTION__,
soeMessage.hdr.unitId,
soeMessage.hdr.size,
soeMessage.hdr.ctrlFlags,
soeMessage.hdr.seqNumId);
// check to see if the message is a reply or an event.
if ((soeMessage.hdr.ctrlFlags &= RM_FLCN_QUEUE_HDR_FLAGS_EVENT) != 0)
{
flcnQueueEventHandle(device, pFlcn, (RM_FLCN_MSG *)&soeMessage, NV_OK);
}
// the message is a response from a previously queued command
else
{
flcnQueueResponseHandle(device, pFlcn, (RM_FLCN_MSG *)&soeMessage);
}
}
//
// Status NV_ERR_NOT_READY implies, Queue is empty.
// Log the message in other error cases.
//
if (status != NV_ERR_NOT_READY)
{
NVSWITCH_PRINT(device, ERROR,
"%s: unexpected error while purging message queue (status=0x%x).\n",
__FUNCTION__, (status));
}
return status;
}
/*!
* This function exists to solve a natural chicken-and-egg problem that arises
* due to the fact that queue information (location, size, id, etc...) is
* relayed to the RM as a message in a queue. Queue construction is done when
* the message arives and the normal queue read/write functions are not
* available until construction is complete. Construction cannot be done until
* the message is read from the queue. Therefore, the very first message read
* from the Message Queue must be considered as a special-case and must NOT use
* any functionality provided by the SOE's queue manager.
*
* @param[in] device nvswitch_device pointer
* @param[in] pSoe SOE object pointer
*
* @return 'NV_OK'
* Upon successful extraction and processing of the first SOE message.
*/
static NV_STATUS
_soeProcessMessagesPreInit_IMPL
(
nvswitch_device *device,
PSOE pSoe
)
{
RM_FLCN_MSG_SOE msg;
NV_STATUS status;
PFLCN pFlcn = ENG_GET_FLCN(pSoe);
// extract the "INIT" message (this is never expected to fail)
status = _soeGetInitMessage(device, pSoe, &msg);
if (status != NV_OK)
{
NVSWITCH_PRINT(device, ERROR,
"%s: Failed to extract the INIT message "
"from the SOE Message Queue (status=0x%08x).",
__FUNCTION__, status);
NVSWITCH_ASSERT(0);
return status;
}
//
// Now hookup the "real" message-processing function and handle the "INIT"
// message.
//
pSoe->base.pHal->processMessages = _soeProcessMessages_IMPL;
return flcnQueueEventHandle(device, pFlcn, (RM_FLCN_MSG *)&msg, NV_OK);
}
/*!
* @brief Process the "INIT" message sent from the SOE ucode application.
*
* When the SOE ucode is done initializing, it will post an INIT message in
* the Message Queue that contains all the necessary attributes that are
* needed to enqueuing commands and extracting messages from the queues.
* The packet will also contain the offset and size of portion of DMEM that
* the RM must manage. Upon receiving this message it will be assume that
* the SOE is ready to start accepting commands.
*
* @param[in] device nvswitch_device pointer
* @param[in] pSoe SOE object pointer
* @param[in] pMsg Pointer to the event's message data
*
* @return 'NV_OK' if the event was successfully handled.
*/
static NV_STATUS
_soeHandleInitEvent_IMPL
(
nvswitch_device *device,
PFLCNABLE pSoe,
RM_FLCN_MSG *pGenMsg
)
{
NV_STATUS status;
PFLCN pFlcn = ENG_GET_FLCN(pSoe);
RM_FLCN_MSG_SOE *pMsg = (RM_FLCN_MSG_SOE *)pGenMsg;
if (pFlcn == NULL)
{
NVSWITCH_ASSERT(pFlcn != NULL);
return NV_ERR_INVALID_POINTER;
}
NVSWITCH_PRINT(device, INFO,
"%s: Received INIT message from SOE\n",
__FUNCTION__);
//
// Pass the INIT message to the queue manager to allow it to create the
// queues.
//
status = _soeQMgrCreateQueuesFromInitMsg(device, pSoe, pMsg);
if (status != NV_OK)
{
NVSWITCH_ASSERT(0);
return status;
}
flcnDbgInfoDmemOffsetSet(device, pFlcn,
pMsg->msg.init.soeInit.osDebugEntryPoint);
// the SOE ucode is now initialized and ready to accept commands
pFlcn->bOSReady = NV_TRUE;
return NV_OK;
}
/*!
* @brief Read the INIT message directly out of the Message Queue.
*
* This function accesses the Message Queue directly using the HAL. It does
* NOT and may NOT use the queue manager as it has not yet been constructed and
* initialized. The Message Queue may not be empty when this function is called
* and the first message in the queue MUST be the INIT message.
*
* @param[in] device nvswitch_device pointer
* @param[in] pSoe SOE object pointer
* @param[out] pMsg Message structure to fill with the INIT message data
*
* @return 'NV_OK' upon successful extraction of the INIT message.
* @return
* 'NV_ERR_INVALID_STATE' if the first message found was not an INIT
* message or if the message was improperly formatted.
*/
static NV_STATUS
_soeGetInitMessage
(
nvswitch_device *device,
PSOE pSoe,
RM_FLCN_MSG_SOE *pMsg
)
{
PFLCN pFlcn = ENG_GET_FLCN(pSoe);
NV_STATUS status = NV_OK;
NvU32 tail = 0;
PFALCON_QUEUE_INFO pQueueInfo;
// on the GPU, rmEmemPortId = sec2RmEmemPortIdGet_HAL(...);
NvU8 rmEmemPortId = 0;
if (pFlcn == NULL)
{
NVSWITCH_ASSERT(pFlcn != NULL);
return NV_ERR_INVALID_POINTER;
}
pQueueInfo = pFlcn->pQueueInfo;
if (pQueueInfo == NULL)
{
NVSWITCH_ASSERT(pQueueInfo != NULL);
return NV_ERR_INVALID_POINTER;
}
//
// Message queue 0 is used by SOE to communicate with RM
// Check SOE_CMDMGMT_MSG_QUEUE_RM in //uproc/soe/inc/soe_cmdmgmt.h
//
pQueueInfo->pQueues[SOE_RM_MSGQ_LOG_ID].queuePhyId = 0;
// read the header starting at the current tail position
(void)flcnMsgQueueTailGet(device, pFlcn,
&pQueueInfo->pQueues[SOE_RM_MSGQ_LOG_ID], &tail);
if (pFlcn->bEmemEnabled)
{
//
// We use the offset in DMEM for the src address, since
// EmemCopyFrom automatically converts it to the offset in EMEM
//
flcnableEmemCopyFrom(
device, pFlcn->pFlcnable,
tail, // src
(NvU8 *)&pMsg->hdr, // pDst
RM_FLCN_QUEUE_HDR_SIZE, // numBytes
rmEmemPortId); // port
}
else
{
status = flcnDmemCopyFrom(device,
pFlcn,
tail, // src
(NvU8 *)&pMsg->hdr, // pDst
RM_FLCN_QUEUE_HDR_SIZE, // numBytes
0); // port
if (status != NV_OK)
{
NVSWITCH_PRINT(device, ERROR,
"%s: Failed to copy from SOE DMEM\n", __FUNCTION__);
NVSWITCH_ASSERT(0);
goto _soeGetInitMessage_exit;
}
}
if (pMsg->hdr.unitId != RM_SOE_UNIT_INIT)
{
status = NV_ERR_INVALID_STATE;
NVSWITCH_ASSERT(0);
goto _soeGetInitMessage_exit;
}
// read the message body and update the tail position
if (pFlcn->bEmemEnabled)
{
//
// We use the offset in DMEM for the src address, since
// EmemCopyFrom automatically converts it to the offset in EMEM
//
flcnableEmemCopyFrom(
device, pFlcn->pFlcnable,
tail + RM_FLCN_QUEUE_HDR_SIZE, // src
(NvU8 *)&pMsg->msg, // pDst
pMsg->hdr.size - RM_FLCN_QUEUE_HDR_SIZE, // numBytes
rmEmemPortId); // port
}
else
{
status = flcnDmemCopyFrom(device,
pFlcn,
tail + RM_FLCN_QUEUE_HDR_SIZE, // src
(NvU8 *)&pMsg->msg, // pDst
pMsg->hdr.size - RM_FLCN_QUEUE_HDR_SIZE, // numBytes
0); // port
if (status != NV_OK)
{
NVSWITCH_PRINT(device, ERROR,
"%s: Failed to copy from SOE DMEM\n", __FUNCTION__);
NVSWITCH_ASSERT(0);
goto _soeGetInitMessage_exit;
}
}
tail += NV_ALIGN_UP(pMsg->hdr.size, SOE_DMEM_ALIGNMENT);
flcnMsgQueueTailSet(device, pFlcn,
&pQueueInfo->pQueues[SOE_RM_MSGQ_LOG_ID], tail);
_soeGetInitMessage_exit:
return status;
}
/*!
* Copies 'sizeBytes' from DMEM address 'src' to 'pDst' using EMEM access port.
*
@@ -444,43 +85,6 @@ _soeEmemCopyTo_IMPL
soeEmemTransfer_HAL(device, (PSOE)pSoe, dst, pSrc, sizeBytes, port, NV_FALSE);
}
/*!
* Loop until SOE RTOS is loaded and gives us an INIT message
*
* @param[in] device nvswitch_device object pointer
* @param[in] pSoe SOE object pointer
*/
static NV_STATUS
_soeWaitForInitAck_IMPL
(
nvswitch_device *device,
PSOE pSoe
)
{
PFLCN pFlcn = ENG_GET_FLCN(pSoe);
// POBJMC pMc = GPU_GET_MC(device);
NVSWITCH_TIMEOUT timeout;
nvswitch_timeout_create(NVSWITCH_INTERVAL_1SEC_IN_NS * 5, &timeout);
while (!pFlcn->bOSReady && !nvswitch_timeout_check(&timeout))
{
// Once interrupt handling is ready, might need to replace this with
//mcServiceSingle_HAL(device, pMc, MC_ENGINE_IDX_SOE, NV_FALSE);
soeService_HAL(device, pSoe);
nvswitch_os_sleep(1);
}
if (!pFlcn->bOSReady)
{
NVSWITCH_PRINT(device, ERROR,
"%s Timeout while waiting for SOE bootup\n",
__FUNCTION__);
NVSWITCH_ASSERT(0);
return NV_ERR_TIMEOUT;
}
return NV_OK;
}
/*!
* @brief Retrieves a pointer to the engine specific SEQ_INFO structure.
*
@@ -585,15 +189,10 @@ soeSetupHal
pHal = pSoe->base.pHal;
pParentHal = (flcnable_hal *)pHal;
//set any functions we want to override
pParentHal->handleInitEvent = _soeHandleInitEvent_IMPL;
pParentHal->ememCopyTo = _soeEmemCopyTo_IMPL;
pParentHal->ememCopyFrom = _soeEmemCopyFrom_IMPL;
pParentHal->queueSeqInfoGet = _soeQueueSeqInfoGet_IMPL;
pParentHal->queueCmdValidate = _soeQueueCmdValidate_IMPL;
//set any functions specific to SOE
pHal->processMessages = _soeProcessMessagesPreInit_IMPL;
pHal->waitForInitAck = _soeWaitForInitAck_IMPL;
}
SOE *