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This commit is contained in:
Andy Ritger
2022-10-10 14:59:24 -07:00
parent fe0728787f
commit 90eb10774f
758 changed files with 88383 additions and 26493 deletions
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3
src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073base.h
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@@ -28,9 +28,6 @@
// Source file: ctrl/ctrl0073/ctrl0073base.finn
//
#include "ctrl/ctrlxxxx.h"
/* NV04_DISPLAY_COMMON control commands and parameters */

142
src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073dfp.h
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@@ -30,9 +30,6 @@
// Source file: ctrl/ctrl0073/ctrl0073dfp.finn
//
#include "ctrl/ctrl0073/ctrl0073base.h"
/* NV04_DISPLAY_COMMON dfp-display-specific control commands and parameters */
@@ -1095,11 +1092,53 @@ typedef struct NV0073_CTRL_CMD_DFP_GET_DISP_MUX_STATUS_PARAMS {
* vActive
* This parameter specifies the vertical lines of the active pixel
* data in the raster.
* hFrontPorch
* This parameter specifies the number of horizontal front porch
* blanking pixels in the raster.
* vFrontPorch
* This parameter specifies the numer of lines of the vertical front
* porch in the raster.
* hBackPorch
* This parameter specifies the number of horizontal back porch
* blanking pixels in the raster.
* vBackPorch
* This parameter specifies the numer of lines of the vertical back
* porch in the raster.
* hSyncWidth
* This parameter specifies the number of horizontal sync pixels in
* the raster.
* vSyncWidth
* This parameter specifies the numer of lines of the vertical sync
* in the raster.
* bpp
* This parameter specifies the depth (Bits per Pixel) of the output
* display stream.
* refresh
* This parameter specifies the refresh rate of the panel (in Hz).
* pclkHz
* This parameter specifies the pixel clock rate in Hz.
* numLanes
* Number of DSI data lanes.
* dscEnable
* Flag to indicate if DSC an be enabled, which in turn indicates if
* panel supports DSC.
* dscBpp
* DSC Bits per pixel
* dscNumSlices
* Number of slices for DSC.
* dscDuaDsc
* Flag to indicate if panel supports DSC streams from two DSI
* controllers.
* dscSliceHeight
* Height of DSC slices.
* dscBlockPrediction
* Flag to indicate if DSC Block Prediction needs to be enabled.
* dscDecoderVersionMajor
* Major version number of DSC decoder on Panel.
* dscDecoderVersionMinor
* Minor version number of DSC decoder on Panel.
* dscEncoderCaps
* Capabilities of DSC encoder in SoC.
*
* Possible status values returned are:
* NV_OK
@@ -1116,10 +1155,107 @@ typedef struct NV0073_CTRL_CMD_DFP_GET_DSI_MODE_TIMING_PARAMS {
NvU32 displayId;
NvU32 hActive;
NvU32 vActive;
NvU32 hFrontPorch;
NvU32 vFrontPorch;
NvU32 hBackPorch;
NvU32 vBackPorch;
NvU32 hSyncWidth;
NvU32 vSyncWidth;
NvU32 bpp;
NvU32 refresh;
NvU32 pclkHz;
NvU32 numLanes;
NvU32 dscEnable;
NvU32 dscBpp;
NvU32 dscNumSlices;
NvU32 dscDualDsc;
NvU32 dscSliceHeight;
NvU32 dscBlockPrediction;
NvU32 dscDecoderVersionMajor;
NvU32 dscDecoderVersionMinor;
struct {
NvBool bDscSupported;
NvU32 encoderColorFormatMask;
NvU32 lineBufferSizeKB;
NvU32 rateBufferSizeKB;
NvU32 bitsPerPixelPrecision;
NvU32 maxNumHztSlices;
NvU32 lineBufferBitDepth;
} dscEncoderCaps;
} NV0073_CTRL_CMD_DFP_GET_DSI_MODE_TIMING_PARAMS;
/*
* NV0073_CTRL_CMD_DFP_GET_FIXED_MODE_TIMING
*
* This control call is used to retrieve the display mode timing info that's
* specified for a given DFP from an offline configuration blob (e.g., Device Tree).
* This display timing info is intended to replace the timings exposed in a
* sink's EDID.
*
* subDeviceInstance (in)
* This parameter specifies the subdevice instance within the
* NV04_DISPLAY_COMMON parent device to which the operation should be
* directed.
* displayId (in)
* ID of the display device for which the timings should be retrieved.
* stream (in)
* For MST connectors with static topologies (e.g., DP serializers),
* this parameter further identifies the video stream for which the
* timings should be retrieved.
* valid (out)
* Indicates whether a valid display timing was found for this DFP.
* hActive (out)
* Horizontal active width in pixels
* hFrontPorch (out)
* Horizontal front porch
* hSyncWidth (out)
* Horizontal sync width
* hBackPorch (out)
* Horizontal back porch
* vActive (out)
* Vertical active height in lines
* vFrontPorch (out)
* Vertical front porch
* vSyncWidth (out)
* Vertical sync width
* vBackPorch (out)
* Vertical back porch
* pclkKHz (out)
* Pixel clock frequency in KHz
* rrx1k (out)
* Refresh rate in units of 0.001Hz
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_NOT_SUPPORTED
*/
#define NV0073_CTRL_CMD_DFP_GET_FIXED_MODE_TIMING (0x731172) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DFP_INTERFACE_ID << 8 | NV0073_CTRL_DFP_GET_FIXED_MODE_TIMING_PARAMS_MESSAGE_ID)" */
#define NV0073_CTRL_DFP_GET_FIXED_MODE_TIMING_PARAMS_MESSAGE_ID (0x72U)
typedef struct NV0073_CTRL_DFP_GET_FIXED_MODE_TIMING_PARAMS {
NvU32 subDeviceInstance;
NvU32 displayId;
NvU8 stream;
NvBool valid;
NvU16 hActive;
NvU16 hFrontPorch;
NvU16 hSyncWidth;
NvU16 hBackPorch;
NvU16 vActive;
NvU16 vFrontPorch;
NvU16 vSyncWidth;
NvU16 vBackPorch;
NvU32 pclkKHz;
NvU32 rrx1k;
} NV0073_CTRL_DFP_GET_FIXED_MODE_TIMING_PARAMS;
/* _ctrl0073dfp_h_ */

93
src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073dp.h
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@@ -30,9 +30,6 @@
// Source file: ctrl/ctrl0073/ctrl0073dp.finn
//
#include "ctrl/ctrl0073/ctrl0073base.h"
/* NV04_DISPLAY_COMMON dfp-display-specific control commands and parameters */
@@ -1839,40 +1836,6 @@ typedef struct NV0073_CTRL_CMD_DP_GET_CAPS_PARAMS {
#define NV0073_CTRL_CMD_DP_GET_CAPS_DSC_BITS_PER_PIXEL_PRECISION_1_2 (0x00000004U)
#define NV0073_CTRL_CMD_DP_GET_CAPS_DSC_BITS_PER_PIXEL_PRECISION_1 (0x00000005U)
/*
* NV0073_CTRL_CMD_DP_SET_MSA_PROPERTIES
*
* This command returns the following info
*
* subDeviceInstance
* This parameter specifies the subdevice instance within the
* NV04_DISPLAY_COMMON parent device to which the operation should be
* directed. This parameter must specify a value between zero and the
* total number of subdevices within the parent device. This parameter
* should be set to zero for default behavior.
* displayId
* should be for DP only
* bEnableMSA
* To enable or disable MSA
* bStereoPhaseInverse
* To enable or disable Stereo Phase Inverse value
* bCacheMsaOverrideForNextModeset
* Cache the values and don't apply them until next modeset
* featureMask
* Enable/Disable mask of individual MSA property
* featureValues
* MSA property value to write
* pFeatureDebugValues
* It will actual MSA property value being written on HW.
* If its NULL then no error but return nothing
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_NOT_SUPPORTED
* NV_ERR_TIMEOUT
*
*/
#define NV0073_CTRL_CMD_DP_SET_MSA_PROPERTIES (0x73136aU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_DP_SET_MSA_PROPERTIES_PARAMS_MESSAGE_ID" */
#define NV0073_CTRL_CMD_DP_MSA_PROPERTIES_SYNC_POLARITY_LOW (0U)
@@ -2730,8 +2693,6 @@ typedef struct NV0073_CTRL_CMD_DP_AUXCH_OD_CTRL_PARAMS {
NvBool bOdStatus;
} NV0073_CTRL_CMD_DP_AUXCH_OD_CTRL_PARAMS;
/* _ctrl0073dp_h_ */
/* valid commands */
#define NV0073_CTRL_CMD_DP_AUXCHQUERY_OD_CAPABLE 0x00000000
#define NV0073_CTRL_CMD_DP_AUXCHQUERY_OD_CTL_CAPABLE 0x00000001
@@ -2742,3 +2703,57 @@ typedef struct NV0073_CTRL_CMD_DP_AUXCH_OD_CTRL_PARAMS {
#define NV0073_CTRL_CMD_DP_AUXCH_OD_CTL_SET_AUTONOMOUS 0x00000000
#define NV0073_CTRL_CMD_DP_AUXCH_OD_CTL_SET_DISABLE_OD 0x00000002
#define NV0073_CTRL_CMD_DP_AUXCH_OD_CTL_SET_ENABLE_OD 0x00000003
/*
* NV0073_CTRL_CMD_DP_SET_MSA_PROPERTIES_V2
*
* This command returns the following info
*
* subDeviceInstance
* This parameter specifies the subdevice instance within the
* NV04_DISPLAY_COMMON parent device to which the operation should be
* directed. This parameter must specify a value between zero and the
* total number of subdevices within the parent device. This parameter
* should be set to zero for default behavior.
* displayId
* should be for DP only
* bEnableMSA
* To enable or disable MSA
* bStereoPhaseInverse
* To enable or disable Stereo Phase Inverse value
* bCacheMsaOverrideForNextModeset
* Cache the values and don't apply them until next modeset
* featureMask
* Enable/Disable mask of individual MSA property
* featureValues
* MSA property value to write
* bDebugValues
* To inform whether actual MSA values need to be returned
* pFeatureDebugValues
* It will actual MSA property value being written on HW.
* If its NULL then no error but return nothing
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_NOT_SUPPORTED
* NV_ERR_TIMEOUT
*
*/
#define NV0073_CTRL_CMD_DP_SET_MSA_PROPERTIES_V2 (0x731381U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_DP_SET_MSA_PROPERTIES_V2_PARAMS_MESSAGE_ID" */
#define NV0073_CTRL_CMD_DP_SET_MSA_PROPERTIES_V2_PARAMS_MESSAGE_ID (0x81U)
typedef struct NV0073_CTRL_CMD_DP_SET_MSA_PROPERTIES_V2_PARAMS {
NvU32 subDeviceInstance;
NvU32 displayId;
NvBool bEnableMSA;
NvBool bStereoPhaseInverse;
NvBool bCacheMsaOverrideForNextModeset;
NV0073_CTRL_DP_MSA_PROPERTIES_MASK featureMask;
NV0073_CTRL_DP_MSA_PROPERTIES_VALUES featureValues;
NvBool bDebugValues;
NV0073_CTRL_DP_MSA_PROPERTIES_VALUES featureDebugValues;
} NV0073_CTRL_CMD_DP_SET_MSA_PROPERTIES_V2_PARAMS;
/* _ctrl0073dp_h_ */

3
src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073internal.h
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@@ -28,9 +28,6 @@
// Source file: ctrl/ctrl0073/ctrl0073internal.finn
//
#include "ctrl/ctrl0073/ctrl0073base.h"
#include "ctrl/ctrl0073/ctrl0073system.h"

54
src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073specific.h
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@@ -30,9 +30,6 @@
// Source file: ctrl/ctrl0073/ctrl0073specific.finn
//
#include "ctrl/ctrl0073/ctrl0073base.h"
#include "ctrl/ctrlxxxx.h"
@@ -1790,4 +1787,55 @@ typedef struct NV0073_CTRL_SPECIFIC_RELEASE_SHARED_GENERIC_PACKET_PARAMS {
NvU32 infoframeIndex;
} NV0073_CTRL_SPECIFIC_RELEASE_SHARED_GENERIC_PACKET_PARAMS;
/*
* NV0073_CTRL_CMD_SPECIFIC_DISP_I2C_READ_WRITE
*
* This command is used to do I2C R/W to slave on display i2c instance.
*
* subDeviceInstance
* This parameter specifies the subdevice instance within the
* NV04_DISPLAY_COMMON parent device to which the operation should be
* directed. This parameter must specify a value between zero and the
* total number of subdevices within the parent device. This parameter
* should be set to zero for default behavior.
* i2cPort
* This parameter specifies the I2C CCB port ID.
* i2cSlaveAddress
* This parameter specifies the I2C slave address.
* readWriteFlag
* This parameter specifies whether its read/write operation.
* readWriteLen
* This parameter specifies the length of the read/write buffer
* readBuffer
* This parameter reads the data from slave address and copies to this
* buffer
* writeBuffer
* This parameter specifies this buffer data that would be written to
* slave address
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_PARAM_STRUCT
* NV_ERR_INVALID_ARGUMENT
*/
#define NV0073_CTRL_CMD_SPECIFIC_DISP_I2C_READ_WRITE (0x7302acU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_SPECIFIC_DISP_I2C_READ_WRITE_PARAMS_MESSAGE_ID" */
#define NV0073_CTRL_SPECIFIC_DISP_I2C_READ_WRITE_BUF_LEN 128U
#define NV0073_CTRL_SPECIFIC_DISP_I2C_READ_WRITE_PARAMS_MESSAGE_ID (0xACU)
typedef struct NV0073_CTRL_SPECIFIC_DISP_I2C_READ_WRITE_PARAMS {
NvU32 subDeviceInstance;
NvU32 i2cPort;
NvU32 i2cSlaveAddress;
NvU32 readWriteFlag;
NvU32 readWriteLen;
NvU8 readBuffer[NV0073_CTRL_SPECIFIC_DISP_I2C_READ_WRITE_BUF_LEN];
NvU8 writeBuffer[NV0073_CTRL_SPECIFIC_DISP_I2C_READ_WRITE_BUF_LEN];
} NV0073_CTRL_SPECIFIC_DISP_I2C_READ_WRITE_PARAMS;
#define NV0073_CTRL_SPECIFIC_DISP_I2C_READ_MODE (0x00000001)
#define NV0073_CTRL_SPECIFIC_DISP_I2C_WRITE_MODE (0x00000000)
/* _ctrl0073specific_h_ */

3
src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073stereo.h
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@@ -30,9 +30,6 @@
// Source file: ctrl/ctrl0073/ctrl0073stereo.finn
//
#include "ctrl/ctrl0073/ctrl0073base.h"

3
src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073system.h
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@@ -30,9 +30,6 @@
// Source file: ctrl/ctrl0073/ctrl0073system.finn
//
#include "ctrl/ctrl0073/ctrl0073base.h"
/* NV04_DISPLAY_COMMON system-level control commands and parameters */