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This commit is contained in:
Andy Ritger
2022-10-10 14:59:24 -07:00
parent fe0728787f
commit 90eb10774f
758 changed files with 88383 additions and 26493 deletions
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3
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080base.h
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@@ -28,9 +28,6 @@
// Source file: ctrl/ctrl2080/ctrl2080base.finn
//
#include "ctrl/ctrlxxxx.h"
/* NV20_SUBDEVICE_XX control commands and parameters */

2
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080bios.h
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@@ -30,8 +30,6 @@
// Source file: ctrl/ctrl2080/ctrl2080bios.finn
//
#include "ctrl/ctrl2080/ctrl2080base.h"
/* NV20_SUBDEVICE_XX bios-related control commands and parameters */

206
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080bus.h
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@@ -30,9 +30,7 @@
// Source file: ctrl/ctrl2080/ctrl2080bus.finn
//
#include "nvcfg_sdk.h"
#include "ctrl/ctrl2080/ctrl2080base.h"
/* NV20_SUBDEVICE_XX bus control commands and parameters */
@@ -1264,7 +1262,172 @@ typedef struct NV2080_CTRL_BUS_GET_EOM_STATUS_PARAMS {
NvU16 eomStatus[NV2080_CTRL_BUS_MAX_NUM_LANES];
} NV2080_CTRL_BUS_GET_EOM_STATUS_PARAMS;
/*
* NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS
*
* This command returns the PCIe requester atomics operation capabilities
* from GPU to coherent SYSMEM.
*
* atomicsCaps[OUT]
* Mask of supported PCIe atomic operations in the form of
* NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_*
*
* Possible status values returned are:
* NV_OK
* NV_ERR_NOT_SUPPORTED
*/
#define NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS (0x20801829) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_PARAMS_MESSAGE_ID (0x29U)
typedef struct NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_PARAMS {
NvU32 atomicsCaps;
} NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_PARAMS;
#define NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_FETCHADD_32 0:0
#define NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_FETCHADD_32_YES (0x00000001)
#define NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_FETCHADD_32_NO (0x00000000)
#define NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_FETCHADD_64 1:1
#define NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_FETCHADD_64_YES (0x00000001)
#define NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_FETCHADD_64_NO (0x00000000)
#define NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_SWAP_32 2:2
#define NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_SWAP_32_YES (0x00000001)
#define NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_SWAP_32_NO (0x00000000)
#define NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_SWAP_64 3:3
#define NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_SWAP_64_YES (0x00000001)
#define NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_SWAP_64_NO (0x00000000)
#define NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_CAS_32 4:4
#define NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_CAS_32_YES (0x00000001)
#define NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_CAS_32_NO (0x00000000)
#define NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_CAS_64 5:5
#define NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_CAS_64_YES (0x00000001)
#define NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_CAS_64_NO (0x00000000)
#define NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_CAS_128 6:6
#define NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_CAS_128_YES (0x00000001)
#define NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_CAS_128_NO (0x00000000)
/*
* NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS
*
* This command returns the supported GPU atomic operations
* that map to the capable PCIe atomic operations from GPU to
* coherent SYSMEM.
*
* atomicOp[OUT]
* Array of structure that contains the atomic operation
* supported status and its attributes. The array can be
* indexed using one of NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_*
*
* bSupported[OUT]
* Is the GPU atomic operation natively supported by the PCIe?
*
* attributes[OUT]
* Provides the attributes mask of the GPU atomic operation when supported
* in the form of
* NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_REDUCTION_*
*
*/
#define NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS (0x2080182a) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_IADD 0
#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_IMIN 1
#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_IMAX 2
#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_INC 3
#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_DEC 4
#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_IAND 5
#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_IOR 6
#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_IXOR 7
#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_EXCH 8
#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_CAS 9
#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_FADD 10
#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_FMIN 11
#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_FMAX 12
#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_COUNT 13
#define NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS_PARAMS_MESSAGE_ID (0x2AU)
typedef struct NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS_PARAMS {
struct {
NvBool bSupported;
NvU32 attributes;
} atomicOp[NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_COUNT];
} NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS_PARAMS;
#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SCALAR 0:0
#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SCALAR_YES 1
#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SCALAR_NO 0
#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_VECTOR 1:1
#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_VECTOR_YES 1
#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_VECTOR_NO 0
#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_REDUCTION 2:2
#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_REDUCTION_YES 1
#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_REDUCTION_NO 0
#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SIZE_32 3:3
#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SIZE_32_YES 1
#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SIZE_32_NO 0
#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SIZE_64 4:4
#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SIZE_64_YES 1
#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SIZE_64_NO 0
#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SIZE_128 5:5
#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SIZE_128_YES 1
#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SIZE_128_NO 0
#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SIGNED 6:6
#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SIGNED_YES 1
#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SIGNED_NO 0
#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_UNSIGNED 7:7
#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_UNSIGNED_YES 1
#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_UNSIGNED_NO 0
/*
* NV2080_CTRL_CMD_BUS_GET_C2C_INFO
*
* This command returns the C2C links information.
*
* bIsLinkUp[OUT]
* NV_TRUE if the C2C links are present and the links are up.
* The below remaining fields are valid only if return value is
* NV_OK and bIsLinkUp is NV_TRUE.
* nrLinks[OUT]
* Total number of C2C links that are up.
* linkMask[OUT]
* Bitmask of the C2C links present and up.
* perLinkBwMBps[OUT]
* Theoretical per link bandwidth in MBps.
* remoteType[OUT]
* Type of the device connected to the remote end of the C2C link.
* Valid values are :
* NV2080_CTRL_BUS_GET_C2C_INFO_REMOTE_TYPE_CPU - connected to a CPU
* NV2080_CTRL_BUS_GET_C2C_INFO_REMOTE_TYPE_GPU - connected to another GPU
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_STATE
*
* Please also review the information below for additional information on
* select fields:
*
* remoteType[OUT]
* NV2080_CTRL_BUS_GET_C2C_INFO_REMOTE_TYPE_CPU - connected to a CPU
*/
#define NV2080_CTRL_CMD_BUS_GET_C2C_INFO (0x2080182b) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS_MESSAGE_ID (0x2BU)
typedef struct NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS {
NvBool bIsLinkUp;
NvU32 nrLinks;
NvU32 linkMask;
NvU32 perLinkBwMBps;
NvU32 remoteType;
} NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS;
#define NV2080_CTRL_BUS_GET_C2C_INFO_REMOTE_TYPE_CPU 1
#define NV2080_CTRL_BUS_GET_C2C_INFO_REMOTE_TYPE_GPU 2
/*
* NV2080_CTRL_CMD_BUS_SYSMEM_ACCESS
@@ -1290,5 +1453,42 @@ typedef struct NV2080_CTRL_BUS_SYSMEM_ACCESS_PARAMS {
NvBool bDisable;
} NV2080_CTRL_BUS_SYSMEM_ACCESS_PARAMS;
/*
* NV2080_CTRL_CMD_BUS_GET_C2C_ERR_INFO
*
* This command returns the C2C error info for a C2C links.
*
* errCnts[OUT]
* Array of structure that contains the error counts for
* number of times one of C2C fatal error interrupt has happened.
* The array size should be NV2080_CTRL_BUS_GET_C2C_ERR_INFO_MAX_NUM_C2C_INSTANCES
* * NV2080_CTRL_BUS_GET_C2C_ERR_INFO_MAX_C2C_LINKS_PER_INSTANCE.
*
* nrCrcErrIntr[OUT]
* Number of times CRC error interrupt triggered.
* nrReplayErrIntr[OUT]
* Number of times REPLAY error interrupt triggered.
* nrReplayB2bErrIntr[OUT]
* Number of times REPLAY_B2B error interrupt triggered.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_STATE
* NV_ERR_NOT_SUPPORTED
*/
#define NV2080_CTRL_CMD_BUS_GET_C2C_ERR_INFO (0x2080182d) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_BUS_GET_C2C_ERR_INFO_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_BUS_GET_C2C_ERR_INFO_MAX_NUM_C2C_INSTANCES 2
#define NV2080_CTRL_BUS_GET_C2C_ERR_INFO_MAX_C2C_LINKS_PER_INSTANCE 5
#define NV2080_CTRL_BUS_GET_C2C_ERR_INFO_PARAMS_MESSAGE_ID (0x2DU)
typedef struct NV2080_CTRL_BUS_GET_C2C_ERR_INFO_PARAMS {
struct {
NvU32 nrCrcErrIntr;
NvU32 nrReplayErrIntr;
NvU32 nrReplayB2bErrIntr;
} errCnts[NV2080_CTRL_BUS_GET_C2C_ERR_INFO_MAX_NUM_C2C_INSTANCES * NV2080_CTRL_BUS_GET_C2C_ERR_INFO_MAX_C2C_LINKS_PER_INSTANCE];
} NV2080_CTRL_BUS_GET_C2C_ERR_INFO_PARAMS;

11
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080ce.h
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@@ -182,7 +182,7 @@ typedef struct NV2080_CTRL_CE_GET_CE_PCE_MASK_PARAMS {
#define NV2080_CTRL_CMD_CE_SET_PCE_LCE_CONFIG (0x20802a04) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_CE_INTERFACE_ID << 8) | NV2080_CTRL_CE_SET_PCE_LCE_CONFIG_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_MAX_PCES 18
#define NV2080_CTRL_MAX_PCES 32
#define NV2080_CTRL_MAX_GRCES 2
#define NV2080_CTRL_CE_SET_PCE_LCE_CONFIG_PARAMS_MESSAGE_ID (0x4U)
@@ -199,10 +199,13 @@ typedef struct NV2080_CTRL_CE_SET_PCE_LCE_CONFIG_PARAMS {
* This command updates the PCE-LCE mappings
*
* pPceLceMap [IN]
* This parameter tracks the array of PCE-LCE mappings.
* This parameter contains the array of PCE to LCE mappings.
* The array is indexed by the PCE index, and contains the
* LCE index that the PCE is assigned to. A unused PCE is
* tagged with NV2080_CTRL_CE_UPDATE_PCE_LCE_MAPPINGS_INVALID_LCE.
*
* pGrceConfig [IN]
* This parameter tracks the array of GRCE configs.
* This parameter contains the array of GRCE configs.
* 0xF -> GRCE does not share with any LCE
* 0-MAX_LCE -> GRCE shares with the given LCE
*
@@ -233,6 +236,8 @@ typedef struct NV2080_CTRL_CE_UPDATE_PCE_LCE_MAPPINGS_PARAMS {
NvBool bUpdateNvlinkPceLce;
} NV2080_CTRL_CE_UPDATE_PCE_LCE_MAPPINGS_PARAMS;
#define NV2080_CTRL_CE_UPDATE_PCE_LCE_MAPPINGS_INVALID_LCE 0xf
#define NV2080_CTRL_CMD_CE_UPDATE_CLASS_DB (0x20802a06) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_CE_INTERFACE_ID << 8) | NV2080_CTRL_CE_UPDATE_CLASS_DB_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_CE_UPDATE_CLASS_DB_PARAMS_MESSAGE_ID (0x6U)

2
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080clk.h
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@@ -31,8 +31,6 @@
/* _ctrl2080clk_h_ */
#include "nvfixedtypes.h"
#include "ctrl/ctrl2080/ctrl2080base.h"
#include "ctrl/ctrl2080/ctrl2080boardobj.h"

3
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080clkavfs.h
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@@ -30,9 +30,6 @@
#include "ctrl/ctrl2080/ctrl2080base.h"
#include "ctrl/ctrl2080/ctrl2080boardobj.h"
#include "ctrl/ctrl2080/ctrl2080volt.h"

3
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080dma.h
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@@ -30,9 +30,6 @@
// Source file: ctrl/ctrl2080/ctrl2080dma.finn
//
#include "ctrl/ctrl2080/ctrl2080base.h"
/* NV20_SUBDEVICE_XX dma control commands and parameters */

3
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080ecc.h
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@@ -30,9 +30,6 @@
// Source file: ctrl/ctrl2080/ctrl2080ecc.finn
//
#include "ctrl/ctrl2080/ctrl2080base.h"

3
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080event.h
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@@ -30,9 +30,6 @@
// Source file: ctrl/ctrl2080/ctrl2080event.finn
//
#include "ctrl/ctrl2080/ctrl2080base.h"
#include "nv_vgpu_types.h"

3
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080fb.h
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@@ -30,9 +30,6 @@
// Source file: ctrl/ctrl2080/ctrl2080fb.finn
//
#include "ctrl/ctrl2080/ctrl2080base.h"
/* NV20_SUBDEVICE_XX fb control commands and parameters */

3
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080fifo.h
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@@ -30,9 +30,6 @@
// Source file: ctrl/ctrl2080/ctrl2080fifo.finn
//
#include "ctrl/ctrl2080/ctrl2080base.h"
/*

3
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080fla.h
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@@ -30,9 +30,6 @@
// Source file: ctrl/ctrl2080/ctrl2080fla.finn
//
#include "ctrl/ctrl2080/ctrl2080base.h"
/* NV20_SUBDEVICE_XX FLA control commands and parameters */

257
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080flcn.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2014-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2014-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -30,9 +30,6 @@
// Source file: ctrl/ctrl2080/ctrl2080flcn.finn
//
#include "ctrl/ctrl2080/ctrl2080base.h"
@@ -83,196 +80,26 @@ typedef struct NV2080_CTRL_FLCN_GET_DMEM_USAGE_PARAMS {
* @defgroup NVOS_INST_EVT Instrumentation event types.
* @{
*/
#define NV2080_CTRL_FLCN_NVOS_INST_EVT_RECALIBRATE 0x00U
#define NV2080_CTRL_FLCN_NVOS_INST_EVT_CTXSW_TICK 0x01U
#define NV2080_CTRL_FLCN_NVOS_INST_EVT_CTXSW_YIELD 0x02U
#define NV2080_CTRL_FLCN_NVOS_INST_EVT_CTXSW_INT0 0x03U
#define NV2080_CTRL_FLCN_NVOS_INST_EVT_CTXSW_BLOCK 0x04U
#define NV2080_CTRL_FLCN_NVOS_INST_EVT_UNBLOCK 0x05U
#define NV2080_CTRL_FLCN_NVOS_INST_EVT_HANDLER_BEGIN 0x06U
#define NV2080_CTRL_FLCN_NVOS_INST_EVT_HANDLER_END 0x07U
#define NV2080_CTRL_FLCN_NVOS_INST_EVT_QUEUE_SEND 0x08U
#define NV2080_CTRL_FLCN_NVOS_INST_EVT_QUEUE_RECV 0x09U
#define NV2080_CTRL_FLCN_NVOS_INST_EVT_RPC_BEGIN 0x0AU
#define NV2080_CTRL_FLCN_NVOS_INST_EVT_RPC_END 0x0BU
#define NV2080_CTRL_FLCN_NVOS_INST_EVT_SKIPPED 0x0CU
#define NV2080_CTRL_FLCN_NVOS_INST_EVT_TASK_EXEC_PROFILE_BEGIN 0x0DU
#define NV2080_CTRL_FLCN_NVOS_INST_EVT_TASK_EXEC_PROFILE_END 0x0EU
#define NV2080_CTRL_FLCN_NVOS_INST_EVT_TASK_LOAD_PROFILE_BEGIN 0x0FU
#define NV2080_CTRL_FLCN_NVOS_INST_EVT_TASK_LOAD_PROFILE_END 0x10U
#define NV2080_CTRL_FLCN_NVOS_INST_EVT_TASK_ODP_CODE_BEGIN 0x11U
#define NV2080_CTRL_FLCN_NVOS_INST_EVT_TASK_ODP_CODE_END 0x12U
#define NV2080_CTRL_FLCN_NVOS_INST_EVT_TASK_ODP_DATA_BEGIN 0x13U
#define NV2080_CTRL_FLCN_NVOS_INST_EVT_TASK_ODP_DATA_END 0x14U
#define NV2080_CTRL_FLCN_NVOS_INST_EVT_TASK_DMA_PROFILE_BEGIN 0x15U
#define NV2080_CTRL_FLCN_NVOS_INST_EVT_TASK_DMA_PROFILE_END 0x16U
#define NV2080_CTRL_FLCN_NVOS_INST_EVT_TASK_DMA_ODP_PROFILE_BEGIN 0x17U
#define NV2080_CTRL_FLCN_NVOS_INST_EVT_TASK_DMA_ODP_PROFILE_END 0x18U
#define NV2080_CTRL_FLCN_NVOS_INST_EVT_USER_CUSTOM_BEGIN 0x19U
#define NV2080_CTRL_FLCN_NVOS_INST_EVT_USER_CUSTOM_END 0x1AU
#define NV2080_CTRL_FLCN_NVOS_INST_EVT_USER_CUSTOM_2_BEGIN 0x1BU
#define NV2080_CTRL_FLCN_NVOS_INST_EVT_USER_CUSTOM_2_END 0x1CU
#define NV2080_CTRL_FLCN_NVOS_INST_EVT_USER_CUSTOM_3_BEGIN 0x1DU
#define NV2080_CTRL_FLCN_NVOS_INST_EVT_USER_CUSTOM_3_END 0x1EU
#define NV2080_CTRL_FLCN_NVOS_INST_EVT_RSVD_DO_NOT_USE 0x00U
#define NV2080_CTRL_FLCN_NVOS_INST_EVT_CTXSW_END 0x01U
#define NV2080_CTRL_FLCN_NVOS_INST_EVT_HW_IRQ_BEGIN 0x02U
#define NV2080_CTRL_FLCN_NVOS_INST_EVT_HW_IRQ_END 0x03U
#define NV2080_CTRL_FLCN_NVOS_INST_EVT_TIMER_TICK 0x04U
#define NV2080_CTRL_FLCN_NVOS_INST_EVT_TASK_EVENT_BEGIN 0x05U
#define NV2080_CTRL_FLCN_NVOS_INST_EVT_TASK_EVENT_END 0x06U
#define NV2080_CTRL_FLCN_NVOS_INST_EVT_RM_QUEUE_LATENCY 0x07U
#define NV2080_CTRL_FLCN_NVOS_INST_EVT_TASK_SPECIAL_EVENT 0x08U
#define NV2080_CTRL_FLCN_NVOS_INST_EVT_DMA_BEGIN 0x09U
#define NV2080_CTRL_FLCN_NVOS_INST_EVT_DMA_END 0x0AU
//! Begin/end for arbitrary block of code. The payload contains a sub-ID for each location profiled.
#define NV2080_CTRL_FLCN_NVOS_INST_EVT_GENERIC_BEGIN 0x0BU
#define NV2080_CTRL_FLCN_NVOS_INST_EVT_GENERIC_END 0x0CU
#define NV2080_CTRL_FLCN_NVOS_INST_EVT_TASK_EVENT_LATENCY 0x0DU
/*!@}*/
#define NV2080_CTRL_FLCN_NVOS_INST_INVALID_TASK_ID 0xFFU
/*!
* Interrupts and exceptions both use the same event type. Set the first bit
* for exceptions to differentiate between the two.
*/
#define NV2080_CTRL_FLCN_NVOS_INST_IRQ_ID(_irqId) (_irqId)
#define NV2080_CTRL_FLCN_NVOS_INST_EXCI_ID(_exciId) (_exciId | (1 << 7))
/*!
* @defgroup NV_INSTRUMENTATION_EVENT_DATA Instrumentation event struct entry.
*
* This is a binary-packed representation of event type and additional data,
* including timing data and tracking IDs.
*
* @{
*/
/*!
* Below DRF needs constants assigned to start and end so it can be represented in FINN properly
* This is because FINN v1 will not have the ability to represent DRF's and bit fields yet
*/
#define NV_INSTRUMENTATION_EVENT_DATA_EVENT_TYPE_DRF_EXTENT (31)
#define NV_INSTRUMENTATION_EVENT_DATA_EVENT_TYPE_DRF_BASE (27)
#define NV_INSTRUMENTATION_EVENT_DATA_EVENT_TYPE \
(NV_INSTRUMENTATION_EVENT_DATA_EVENT_TYPE_DRF_EXTENT) : \
(NV_INSTRUMENTATION_EVENT_DATA_EVENT_TYPE_DRF_BASE)
#define NV_INSTRUMENTATION_EVENT_DATA_TASK_ID 26:19
#define NV_INSTRUMENTATION_EVENT_DATA_EXTRA 26:19
#define NV_INSTRUMENTATION_EVENT_DATA_TIME_DELTA 18:0
#define NV_INSTRUMENTATION_EVENT_DATA_TIME_ABS 26:0
/*!@}*/
/*!
* The maximum number of event types, calculated from the number of bits in the
* event structure.
*/
#define NV2080_CTRL_FLCN_NVOS_INST_NUM_EVT_TYPES (0x20U) /* finn: Evaluated from "(1 << (NV_INSTRUMENTATION_EVENT_DATA_EVENT_TYPE_DRF_EXTENT - NV_INSTRUMENTATION_EVENT_DATA_EVENT_TYPE_DRF_BASE + 1))" */
/*!
* The number of bytes required in the event mask to contain all event types.
*/
#define NV2080_CTRL_FLCN_NVOS_INST_MASK_SIZE_BYTES (0x4U) /* finn: Evaluated from "(NV2080_CTRL_FLCN_NVOS_INST_NUM_EVT_TYPES / 8)" */
/*!
* Instrumentation event bitfield structure. Exact structure depends on the
* first five bits, which represent event type.
*
* For most event types, the structure is:
* - 5 bits of event type
* - 8 bits of ID
* - 19 bits of delta time (time since last event). If we've missed some
* events, it's the amount of time since the last event that was not
* skipped. If this time would overflow, a recalibration event is inserted
* instead (see below).
*
* The main exception is the recalibration event, which has no ID/delta time
* fields and instead has a 27-bit absolute timestamp. This event is used
* when the gap between two events is greater than the maximum 20-bit integer.
*
* All timestamps are represented in increments of 32ns
* (the finest possible timer resolution).
*/
typedef struct NVOS_INSTRUMENTATION_EVENT {
/*!
* Field containing the event type and data.
*
* Bitmask of @ref NV_INSTRUMENTATION_EVENT_DATA.
*/
NvU32 data;
} NVOS_INSTRUMENTATION_EVENT;
typedef struct NVOS_INSTRUMENTATION_EVENT *PNVOS_INSTRUMENTATION_EVENT;
/*
* NV2080_CTRL_CMD_FLCN_INSTRUMENTATION_MAP/UNMAP
*
* Params for both RmCtrls are the same (out for _MAP, in for _UNMAP)
*/
#define NV2080_CTRL_CMD_FLCN_INSTRUMENTATION_MAP (0x20803112) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FLCN_INTERFACE_ID << 8) | 0x12" */
#define NV2080_CTRL_CMD_FLCN_INSTRUMENTATION_UNMAP (0x20803113) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FLCN_INTERFACE_ID << 8) | 0x13" */
typedef struct NV2080_CTRL_FLCN_INSTRUMENTATION_MAP_PARAMS {
//! The engine type, from NV2080_ENGINE_TYPE_*
NvU32 engine;
//! The beginning of the instrumentation buffer, mapped to user memory.
NV_DECLARE_ALIGNED(NvP64 begin, 8);
// Priv pointer for memory mapping.
NV_DECLARE_ALIGNED(NvP64 pPriv, 8);
// The size of the user-mapped instrumentation buffer.
NV_DECLARE_ALIGNED(NvU64 size, 8);
} NV2080_CTRL_FLCN_INSTRUMENTATION_MAP_PARAMS;
/*
* NV2080_CTRL_CMD_FLCN_INSTRUMENTATION_GET_INFO
*
* Get static information about FLCN instrumentation.
*/
#define NV2080_CTRL_CMD_FLCN_INSTRUMENTATION_GET_INFO (0x20803114) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FLCN_INTERFACE_ID << 8) | NV2080_CTRL_FLCN_INSTRUMENTATION_GET_INFO_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_FLCN_INSTRUMENTATION_GET_INFO_PARAMS_MESSAGE_ID (0x14U)
typedef struct NV2080_CTRL_FLCN_INSTRUMENTATION_GET_INFO_PARAMS {
//! The engine type, from NV2080_ENGINE_TYPE_*
NvU32 engine;
//! Whether or not instrumentation is enabled
NvBool bEnabled;
/*!
* Whether we use PTIMER (resolution 32ns) or the 30us timer tick (NV_TRUE
* is PTIMER).
*/
NvBool bIsTimerPrecise;
} NV2080_CTRL_FLCN_INSTRUMENTATION_GET_INFO_PARAMS;
/*
* NV2080_CTRL_CMD_FLCN_INSTRUMENTATION_GET/SET_CONTROL
*
* Get/set the event bitmask.
*/
#define NV2080_CTRL_CMD_FLCN_INSTRUMENTATION_GET_CONTROL (0x20803115) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FLCN_INTERFACE_ID << 8) | 0x15" */
#define NV2080_CTRL_CMD_FLCN_INSTRUMENTATION_SET_CONTROL (0x20803116) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FLCN_INTERFACE_ID << 8) | 0x16" */
typedef struct NV2080_CTRL_FLCN_INSTRUMENTATION_CONTROL_PARAMS {
//! The engine type, from NV2080_ENGINE_TYPE_*
NvU32 engine;
/*!
* The bitmask of which event types to log. An event type corresponding to
* a bit with a zero will be ignored at the log site, which prevents it
* from filling up the resident buffer in the PMU. In general, set this to
* only log the event types you actually want to use.
* Refer to NVOS_BM_* in nvos_utility.h for usage.
*/
NvU8 mask[4];
} NV2080_CTRL_FLCN_INSTRUMENTATION_CONTROL_PARAMS;
/*
* NV2080_CTRL_CMD_FLCN_INSTRUMENTATION_RECALIBRATE
*
* Send a recalibrate event to the intstrumentation.
*/
#define NV2080_CTRL_CMD_FLCN_INSTRUMENTATION_RECALIBRATE (0x20803117) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FLCN_INTERFACE_ID << 8) | NV2080_CTRL_FLCN_INSTRUMENTATION_RECALIBRATE_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_FLCN_INSTRUMENTATION_RECALIBRATE_PARAMS_MESSAGE_ID (0x17U)
typedef struct NV2080_CTRL_FLCN_INSTRUMENTATION_RECALIBRATE_PARAMS {
//! The engine type, from NV2080_ENGINE_TYPE_*
NvU32 engine;
} NV2080_CTRL_FLCN_INSTRUMENTATION_RECALIBRATE_PARAMS;
#define NV2080_CTRL_FLCN_NVOS_INST_INVALID_TASK_ID 0xFFU
/*
* NV2080_CTRL_CMD_FLCN_GET_ENGINE_ARCH
@@ -280,7 +107,7 @@ typedef struct NV2080_CTRL_FLCN_INSTRUMENTATION_RECALIBRATE_PARAMS {
* Get the egine arch i.e FALCON, RISCV etc given the NV2080_ENGINE_TYPE_*.
*
*/
#define NV2080_CTRL_CMD_FLCN_GET_ENGINE_ARCH (0x20803118) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FLCN_INTERFACE_ID << 8) | NV2080_CTRL_FLCN_GET_ENGINE_ARCH_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_CMD_FLCN_GET_ENGINE_ARCH (0x20803118) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FLCN_INTERFACE_ID << 8) | NV2080_CTRL_FLCN_GET_ENGINE_ARCH_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_FLCN_GET_ENGINE_ARCH_PARAMS_MESSAGE_ID (0x18U)
@@ -340,6 +167,50 @@ typedef struct NV2080_CTRL_FLCN_GET_ENGINE_ARCH_PARAMS {
/*!@}*/
/*!
* @defgroup NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_BREAKDOWN
*
* These DRFs define breakdown of the compact payload for various event IDs.
*
* @{
*/
#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_CTXSW_END_TASK_ID 7:0
#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_CTXSW_END_REASON 10:8
#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_CTXSW_END_REASON_YIELD 0x0
#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_CTXSW_END_REASON_INT0 0x1
#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_CTXSW_END_REASON_TIMER_TICK 0x2
#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_CTXSW_END_REASON_QUEUE_BLOCK 0x3
#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_CTXSW_END_REASON_DMA_SUSPENDED 0x4
#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_CTXSW_END_ODP_MISS_COUNT 23:11
#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_TIMER_TICK_TIME_SLIP 23:0
#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_TASK_EVENT_BEGIN_TASK_ID 7:0
#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_TASK_EVENT_BEGIN_UNIT_ID 15:8
#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_TASK_EVENT_BEGIN_EVENT_TYPE 23:16
#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_TASK_EVENT_END_TASK_ID 7:0
#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_TASK_EVENT_END_RPC_FUNC 15:8
#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_TASK_EVENT_END_RPC_FUNC_BOBJ_CMD_BASE 0xF0
#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_TASK_EVENT_END_CLASS_ID 23:16
#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_RM_QUEUE_LATENCY_SHIFT 10U
#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_TASK_SPECIAL_EVENT_TASK_ID 7:0
#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_TASK_SPECIAL_EVENT_ID 23:8
#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_TASK_SPECIAL_EVENT_ID_RESERVED 0x000000
#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_TASK_SPECIAL_EVENT_ID_CB_ENQUEUE_FAIL 0x000001
#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_TASK_EVENT_LATENCY_SHIFT 6U
#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_GENERIC_ID 11:0
#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_GENERIC_ID_INVALID 0x000
#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_GENERIC_ID_VF_SWITCH_TOTAL 0x001
/*!@}*/
/*!
* @defgroup NV2080_CTRL_FLCN_USTREAMER_FEATURE
*

1
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080fuse.h
View File

@@ -32,4 +32,3 @@
/* _ctrl2080fuse_h_ */

2
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080gpio.h
View File

@@ -32,7 +32,5 @@
/* _ctrl2080gpio_h_ */
#include "ctrl/ctrl2080/ctrl2080base.h"

191
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080gpu.h
View File

@@ -29,12 +29,10 @@
// Source file: ctrl/ctrl2080/ctrl2080gpu.finn
//
#include "ctrl/ctrl2080/ctrl2080base.h"
#include "ctrl/ctrl2080/ctrl2080gr.h"
#include "ctrl/ctrl0000/ctrl0000system.h"
#include "nvcfg_sdk.h"
@@ -366,7 +364,7 @@ typedef struct NV2080_CTRL_GPU_GET_SDM_PARAMS {
* This command sets the subdevice instance and mask value for the associated subdevice.
* The subdevice mask value can be used with the SET_SUBDEVICE_MASK instruction
* provided by the NV36_CHANNEL_DMA and newer channel dma classes.
* It must be called before the GPU HW is initialized otherwise
* It must be called before the GPU HW is initialized otherwise
* NV_ERR_INVALID_STATE is being returned.
*
* subdeviceMask [in]
@@ -903,9 +901,9 @@ typedef struct NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ENTRY {
* promoteEntry
* List of context buffer entries to issue promotions for.
*
* When not using promoteEntry, only hVirtMemory or (virtAddress, size) should be
* specified, the code cases based on hVirtMemory(NULL vs non-NULL) so
* if both are specified, hVirtMemory has precedence.
* When not using promoteEntry, only hVirtMemory or (virtAddress, size) should be
* specified, the code cases based on hVirtMemory(NULL vs non-NULL) so
* if both are specified, hVirtMemory has precedence.
*
* Possible status values returned are:
* NV_OK
@@ -1080,7 +1078,7 @@ typedef struct NV2080_CTRL_GPU_QUERY_ECC_INTR_PARAMS {
#define NV2080_CTRL_CMD_GPU_QUERY_ECC_STATUS (0x2080012f) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_GPU_ECC_UNIT_COUNT (0x00000016)
#define NV2080_CTRL_GPU_ECC_UNIT_COUNT (0x00000018)
@@ -2398,28 +2396,6 @@ typedef struct NV2080_CTRL_GPU_SET_FABRIC_BASE_ADDR_PARAMS {
#define NV2080_CTRL_CMD_GPU_SET_FABRIC_BASE_ADDR (0x2080016f) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_SET_FABRIC_BASE_ADDR_PARAMS_MESSAGE_ID" */
/*
* NV2080_CTRL_CMD_GPU_INTERRUPT_FUNCTION
*
* The command will trigger an interrupt to a specified PCIe Function.
*
* gfid[IN]
* - The GPU function identifier
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_NOT_SUPPORTED
*/
#define NV2080_CTRL_GPU_INTERRUPT_FUNCTION_PARAMS_MESSAGE_ID (0x71U)
typedef struct NV2080_CTRL_GPU_INTERRUPT_FUNCTION_PARAMS {
NvU32 gfid;
} NV2080_CTRL_GPU_INTERRUPT_FUNCTION_PARAMS;
#define NV2080_CTRL_CMD_GPU_INTERRUPT_FUNCTION (0x20800171) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_INTERRUPT_FUNCTION_PARAMS_MESSAGE_ID" */
/*
* NV2080_CTRL_CMD_GPU_VIRTUAL_INTERRUPT
*
@@ -2545,34 +2521,43 @@ typedef struct NV2080_CTRL_GPU_SET_PARTITION_INFO {
NV_DECLARE_ALIGNED(NV2080_CTRL_GPU_PARTITION_SPAN placement, 8);
} NV2080_CTRL_GPU_SET_PARTITION_INFO;
#define PARTITIONID_INVALID NV2080_CTRL_GPU_PARTITION_ID_INVALID
#define NV2080_CTRL_GPU_PARTITION_ID_INVALID 0xFFFFFFFF
#define NV2080_CTRL_GPU_MAX_PARTITIONS 0x00000008
#define NV2080_CTRL_GPU_MAX_PARTITION_IDS 0x00000009
#define NV2080_CTRL_GPU_MAX_SMC_IDS 0x00000008
#define NV2080_CTRL_GPU_MAX_GPC_PER_SMC 0x0000000c
#define NV2080_CTRL_GPU_MAX_CE_PER_SMC 0x00000008
#define PARTITIONID_INVALID NV2080_CTRL_GPU_PARTITION_ID_INVALID
#define NV2080_CTRL_GPU_PARTITION_ID_INVALID 0xFFFFFFFF
#define NV2080_CTRL_GPU_MAX_PARTITIONS 0x00000008
#define NV2080_CTRL_GPU_MAX_PARTITION_IDS 0x00000009
#define NV2080_CTRL_GPU_MAX_SMC_IDS 0x00000008
#define NV2080_CTRL_GPU_MAX_GPC_PER_SMC 0x0000000c
#define NV2080_CTRL_GPU_MAX_CE_PER_SMC 0x00000008
#define NV2080_CTRL_GPU_PARTITION_FLAG_MEMORY_SIZE 1:0
#define NV2080_CTRL_GPU_PARTITION_FLAG_MEMORY_SIZE_FULL 0x00000000
#define NV2080_CTRL_GPU_PARTITION_FLAG_MEMORY_SIZE_HALF 0x00000001
#define NV2080_CTRL_GPU_PARTITION_FLAG_MEMORY_SIZE_QUARTER 0x00000002
#define NV2080_CTRL_GPU_PARTITION_FLAG_MEMORY_SIZE_EIGHTH 0x00000003
#define NV2080_CTRL_GPU_PARTITION_FLAG_MEMORY_SIZE__SIZE 4
#define NV2080_CTRL_GPU_PARTITION_FLAG_MEMORY_SIZE_FULL 0x00000000
#define NV2080_CTRL_GPU_PARTITION_FLAG_MEMORY_SIZE_HALF 0x00000001
#define NV2080_CTRL_GPU_PARTITION_FLAG_MEMORY_SIZE_QUARTER 0x00000002
#define NV2080_CTRL_GPU_PARTITION_FLAG_MEMORY_SIZE_EIGHTH 0x00000003
#define NV2080_CTRL_GPU_PARTITION_FLAG_MEMORY_SIZE__SIZE 4
#define NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE 4:2
#define NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_FULL 0x00000000
#define NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_HALF 0x00000001
#define NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_MINI_HALF 0x00000002
#define NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_QUARTER 0x00000003
#define NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_EIGHTH 0x00000004
#define NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE__SIZE 5
#define NV2080_CTRL_GPU_PARTITION_MAX_TYPES 8
#define NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_FULL 0x00000000
#define NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_HALF 0x00000001
#define NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_MINI_HALF 0x00000002
#define NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_QUARTER 0x00000003
#define NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_MINI_QUARTER 0x00000004
#define NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_EIGHTH 0x00000005
#define NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE__SIZE 6
#define NV2080_CTRL_GPU_PARTITION_FLAG_GFX_SIZE 7:5
#define NV2080_CTRL_GPU_PARTITION_FLAG_GFX_SIZE_FULL 0x00000001
#define NV2080_CTRL_GPU_PARTITION_FLAG_GFX_SIZE_HALF 0x00000002
#define NV2080_CTRL_GPU_PARTITION_FLAG_GFX_SIZE_MINI_HALF 0x00000003
#define NV2080_CTRL_GPU_PARTITION_FLAG_GFX_SIZE_QUARTER 0x00000004
#define NV2080_CTRL_GPU_PARTITION_FLAG_GFX_SIZE_EIGHTH 0x00000005
#define NV2080_CTRL_GPU_PARTITION_FLAG_GFX_SIZE_NONE 0x00000000
#define NV2080_CTRL_GPU_PARTITION_FLAG_GFX_SIZE__SIZE 6
#define NV2080_CTRL_GPU_PARTITION_MAX_TYPES 8
#define NV2080_CTRL_GPU_PARTITION_FLAG_REQ_DEC_JPG_OFA 30:30
#define NV2080_CTRL_GPU_PARTITION_FLAG_REQ_DEC_JPG_OFA_DISABLE 0
#define NV2080_CTRL_GPU_PARTITION_FLAG_REQ_DEC_JPG_OFA_ENABLE 1
#define NV2080_CTRL_GPU_PARTITION_FLAG_REQ_DEC_JPG_OFA_DISABLE 0
#define NV2080_CTRL_GPU_PARTITION_FLAG_REQ_DEC_JPG_OFA_ENABLE 1
#define NV2080_CTRL_GPU_PARTITION_FLAG_PLACE_AT_SPAN 31:31
#define NV2080_CTRL_GPU_PARTITION_FLAG_PLACE_AT_SPAN_DISABLE 0
#define NV2080_CTRL_GPU_PARTITION_FLAG_PLACE_AT_SPAN_ENABLE 1
#define NV2080_CTRL_GPU_PARTITION_FLAG_PLACE_AT_SPAN_DISABLE 0
#define NV2080_CTRL_GPU_PARTITION_FLAG_PLACE_AT_SPAN_ENABLE 1
// TODO XXX Bug 2657907 Remove these once clients update
#define NV2080_CTRL_GPU_PARTITION_FLAG_FULL_GPU (DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _MEMORY_SIZE, _FULL) | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _COMPUTE_SIZE, _FULL))
@@ -2633,10 +2618,22 @@ typedef struct NV2080_CTRL_GPU_SET_PARTITIONS_PARAMS {
* - NvJpg Engines assigned to a partition.
*
* gpcCount[OUT]
* - Max GPCs assigned to a partition.
* - Max GPCs assigned to a partition, including the GfxCapable ones.
*
* virtualGpcCount[OUT]
* - Virtualized GPC count assigned to partition
*
* gfxGpcCount[OUT]
* - Max GFX GPCs assigned to a partition. This is a subset of the GPCs incuded in gpcCount.
*
* gpcsPerGr[NV2080_CTRL_GPU_MAX_SMC_IDS][OUT]
* - GPC count associated with every valid SMC/Gr.
* - GPC count associated with every valid SMC/Gr, including the GPCs capable of GFX
*
* virtualGpcsPerGr[NV2080_CTRL_GPU_MAX_SMC_IDS][OUT]
* - Virtualized GPC count associated with every valid SMC/Gr, including the GPCs capable of GFX
*
* gfxGpcsPerGr[NV2080_CTRL_GPU_MAX_SMC_IDS][OUT]
* - GFX GPC count associated with every valid SMC/Gr. This is a subset of the GPCs included in gfxGpcCount
*
* veidsPerGr[NV2080_CTRL_GPU_MAX_SMC_IDS][OUT]
* - VEID count associated with every valid SMC. VEIDs within this SMC
@@ -2670,7 +2667,11 @@ typedef struct NV2080_CTRL_GPU_GET_PARTITION_INFO {
NvU32 nvJpgCount;
NvU32 nvOfaCount;
NvU32 gpcCount;
NvU32 virtualGpcCount;
NvU32 gfxGpcCount;
NvU32 gpcsPerGr[NV2080_CTRL_GPU_MAX_SMC_IDS];
NvU32 virtualGpcsPerGr[NV2080_CTRL_GPU_MAX_SMC_IDS];
NvU32 gfxGpcPerGr[NV2080_CTRL_GPU_MAX_SMC_IDS];
NvU32 veidsPerGr[NV2080_CTRL_GPU_MAX_SMC_IDS];
NV_DECLARE_ALIGNED(NvU64 memSize, 8);
NV_DECLARE_ALIGNED(NV2080_CTRL_GPU_PARTITION_SPAN span, 8);
@@ -3179,10 +3180,19 @@ typedef struct NV2080_CTRL_GPU_SET_PARTITIONING_MODE_PARAMS {
* partition
*
* [OUT] grCount
* - Number of SMC engines/GR engines
* - Total Number of SMC engines/GR engines (including GFX capable ones in this parition)
*
* [OUT] gfxGrCount
* - Number of SMC engines/GR engines capable of GFX. This is a subset of the engines included in grCount
*
* [OUT] gpcCount
* - Number of GPCs in this partition
* - Number of GPCs in this partition, including the GFX Capable ones.
*
* [OUT] virtualGpcCount
* - Number of virtualized GPCs in this partition, including the GFX Capable ones.
*
* [OUT] gfxGpcCount
* - Number of GFX Capable GPCs in this partition. This is a subset of the GPCs included in gpcCount.
*
* [OUT] veidCount
* - Number of VEIDS in this partition
@@ -3210,7 +3220,10 @@ typedef struct NV2080_CTRL_GPU_SET_PARTITIONING_MODE_PARAMS {
typedef struct NV2080_CTRL_GPU_DESCRIBE_PARTITIONS_INFO {
NvU32 partitionFlag;
NvU32 grCount;
NvU32 gfxGrCount;
NvU32 gpcCount;
NvU32 virtualGpcCount;
NvU32 grGpcCount;
NvU32 veidCount;
NvU32 smCount;
NvU32 ceCount;
@@ -3282,9 +3295,9 @@ typedef struct NV2080_CTRL_GPU_GET_MAX_SUPPORTED_PAGE_SIZE_PARAMS {
* Logical GPC id
* count [OUT]
* The number of MMUs per GPC
* grRouteInfo
* This parameter specifies the routing information used to
* disambiguate the target GR engine. When SMC is enabled, this
* grRouteInfo
* This parameter specifies the routing information used to
* disambiguate the target GR engine. When SMC is enabled, this
* is a mandatory parameter.
*/
#define NV2080_CTRL_GPU_GET_NUM_MMUS_PER_GPC_PARAMS_MESSAGE_ID (0x8AU)
@@ -3619,7 +3632,7 @@ typedef struct NV2080_CTRL_GPU_VALIDATE_MEM_MAP_REQUEST_PARAMS {
* NV2080_CTRL_CMD_GPU_GET_ENGINE_LOAD_TIMES
*
* This command is used to retrieve the load time (latency) of each engine.
*
*
* engineCount
* This field specifies the number of entries of the following
* three arrays.
@@ -3653,10 +3666,10 @@ typedef struct NV2080_CTRL_GPU_GET_ENGINE_LOAD_TIMES_PARAMS {
* NV2080_CTRL_CMD_GPU_GET_ID_NAME_MAPPING
*
* This command is used to retrieve the mapping of engine ID and engine Name.
*
*
* engineCount
* This field specifies the size of the mapping.
*
*
* engineID
* An array of NvU32 which stores each engine's descriptor.
*
@@ -3681,7 +3694,7 @@ typedef struct NV2080_CTRL_GPU_GET_ID_NAME_MAPPING_PARAMS {
*
* Same as above NV2080_CTRL_CMD_GPU_EXEC_REG_OPS except that this CTRL CMD will
* not allow any embedded pointers. The regOps array is inlined as part of the
* struct.
* struct.
* NOTE: This intended for gsp plugin only as it may override regOp access
* restrictions
*
@@ -3779,4 +3792,54 @@ typedef struct NV2080_CTRL_GET_P2P_CAPS_PARAMS {
NV2080_CTRL_GPU_P2P_PEER_CAPS_PEER_INFO peerGpuCaps[NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS];
} NV2080_CTRL_GET_P2P_CAPS_PARAMS;
/*!
* NV2080_CTRL_GPU_COMPUTE_PROFILE
*
* This structure specifies resources in an execution partition
*
* id[OUT]
* - Total Number of GPCs in this partition
*
* computeSize[OUT]
* - NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_* associated with this profile
*
* gpcCount[OUT]
* - Total Number of GPCs in this partition (including GFX Supported GPCs)
*
* veidCount[OUT]
* - Number of VEIDs allocated to this profile
*
* smCount[OUT]
* - Number of SMs usable in this profile
*/
typedef struct NV2080_CTRL_GPU_COMPUTE_PROFILE {
NvU8 computeSize;
NvU32 gfxGpcCount;
NvU32 gpcCount;
NvU32 veidCount;
NvU32 smCount;
} NV2080_CTRL_GPU_COMPUTE_PROFILE;
/*!
* NV2080_CTRL_GPU_GET_COMPUTE_PROFILES_PARAMS
*
* This structure specifies resources in an execution partition
*
* profileCount[OUT]
* - Total Number of profiles filled
*
* profiles[OUT]
* - NV2080_CTRL_GPU_COMPUTE_PROFILE filled with valid compute instance profiles
*/
#define NV2080_CTRL_GPU_GET_COMPUTE_PROFILES_PARAMS_MESSAGE_ID (0xA2U)
typedef struct NV2080_CTRL_GPU_GET_COMPUTE_PROFILES_PARAMS {
NvU32 profileCount;
NV2080_CTRL_GPU_COMPUTE_PROFILE profiles[NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE__SIZE];
} NV2080_CTRL_GPU_GET_COMPUTE_PROFILES_PARAMS;
#define NV2080_CTRL_CMD_GPU_GET_COMPUTE_PROFILES (0x208001a2) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_COMPUTE_PROFILES_PARAMS_MESSAGE_ID" */
/* _ctrl2080gpu_h_ */

33
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080gr.h
View File

@@ -30,9 +30,6 @@
// Source file: ctrl/ctrl2080/ctrl2080gr.finn
//
#include "ctrl/ctrl2080/ctrl2080base.h"
#include "ctrl/ctrl0080/ctrl0080gr.h" /* 2080 is partially derivative of 0080 */
@@ -514,7 +511,8 @@ typedef struct NV2080_CTRL_GR_CTXSW_PM_MODE_PARAMS {
*
* hClient
* This parameter specifies the client handle of
* that owns the zcull context buffer.
* that owns the zcull context buffer. This field must match
* the hClient used in the control call for non-kernel clients.
* hChannel
* This parameter specifies the channel handle of
* the channel that is to have its zcull context switch mode changed.
@@ -1086,6 +1084,8 @@ typedef struct NV2080_CTRL_GR_GET_CTX_BUFFER_INFO_PARAMS {
#define NV2080_CTRL_CMD_GR_GET_GLOBAL_SM_ORDER_MAX_SM_COUNT 512U
#define NV2080_CTRL_GR_DISABLED_SM_VGPC_ID 0xFFU
#define NV2080_CTRL_GR_GET_GLOBAL_SM_ORDER_PARAMS_MESSAGE_ID (0x1BU)
typedef struct NV2080_CTRL_GR_GET_GLOBAL_SM_ORDER_PARAMS {
@@ -1786,4 +1786,29 @@ typedef struct NV2080_CTRL_GR_FECS_BIND_EVTBUF_FOR_UID_V2_PARAMS {
NvU32 reasonCode;
} NV2080_CTRL_GR_FECS_BIND_EVTBUF_FOR_UID_V2_PARAMS;
/*
* NV2080_CTRL_CMD_GR_GET_GFX_GPC_AND_TPC_INFO
*
* This command grabs information on GFX capable GPC's and TPC's for a specifc GR engine
*
* grRouteInfo[IN]
* This parameter specifies the routing information used to
* disambiguate the target GR engine.
*
* physGfxGpcMask [OUT]
* Physical mask of Gfx capable GPC's
*
* numGfxTpc [OUT]
* Total number of Gfx capable TPC's
*/
#define NV2080_CTRL_CMD_GR_GET_GFX_GPC_AND_TPC_INFO (0x20801239U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_GET_GFX_GPC_AND_TPC_INFO_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_GR_GET_GFX_GPC_AND_TPC_INFO_PARAMS_MESSAGE_ID (0x39U)
typedef struct NV2080_CTRL_GR_GET_GFX_GPC_AND_TPC_INFO_PARAMS {
NV_DECLARE_ALIGNED(NV2080_CTRL_GR_ROUTE_INFO grRouteInfo, 8);
NvU32 physGfxGpcMask;
NvU32 numGfxTpc;
} NV2080_CTRL_GR_GET_GFX_GPC_AND_TPC_INFO_PARAMS;
/* _ctrl2080gr_h_ */

3
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080grmgr.h
View File

@@ -30,9 +30,6 @@
// Source file: ctrl/ctrl2080/ctrl2080grmgr.finn
//
#include "ctrl/ctrl2080/ctrl2080base.h"
/* NV20_SUBDEVICE_XX grmgr control commands and parameters */

3
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080gsp.h
View File

@@ -30,9 +30,6 @@
// Source file: ctrl/ctrl2080/ctrl2080gsp.finn
//
#include "ctrl/ctrl2080/ctrl2080base.h"
/* NV20_SUBDEVICE_XX GSP control commands and parameters */

3
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080hshub.h
View File

@@ -30,9 +30,6 @@
// Source file: ctrl/ctrl2080/ctrl2080hshub.finn
//
#include "ctrl/ctrl2080/ctrl2080base.h"
/*

3
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080i2c.h
View File

@@ -30,9 +30,6 @@
// Source file: ctrl/ctrl2080/ctrl2080i2c.finn
//
#include "ctrl/ctrl2080/ctrl2080base.h"
/* NV20_SUBDEVICE_XX i2c-related control commands and parameters */

169
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080internal.h
View File

@@ -31,9 +31,6 @@
//
#include "nvimpshared.h"
#include "ctrl/ctrl2080/ctrl2080base.h"
#include "ctrl/ctrl2080/ctrl2080gpu.h"
@@ -316,6 +313,9 @@ typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_FLOORSWEEPING_MASKS {
* zcullMask is always indexed by physical GPC ID
*/
NvU32 zcullMask[NV2080_CTRL_INTERNAL_GR_MAX_GPC];
NvU32 physGfxGpcMask;
NvU32 numGfxTpc;
} NV2080_CTRL_INTERNAL_STATIC_GR_FLOORSWEEPING_MASKS;
typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_FLOORSWEEPING_MASKS_PARAMS {
@@ -662,7 +662,7 @@ typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES_PARAMS {
/**
* NV2080_CTRL_CMD_INTERNAL_GET_DEVICE_INFO_TABLE
*
*
* Parse the DEVICE_INFO2_TABLE on the physical side and return it to kernel.
*/
typedef struct NV2080_CTRL_INTERNAL_DEVICE_INFO {
@@ -852,10 +852,19 @@ typedef struct NV2080_CTRL_INTERNAL_DISPLAY_SETUP_RG_LINE_INTR_PARAMS {
* Allocation flag to be used to allocate a partition with this profile.
*
* grCount [OUT]
* # GR engines
* # GR engines, including the GFX capable ones.
*
* gfxGrCount [OUT]
* # GR engines capable of Gfx, which is a subset of the GR engines included in grCount
*
* gpcCount [OUT]
* # total gpcs
* # total gpcs, including the GFX capable ones.
*
* virtualGpcCount [OUT]
* # virtualized gpcs, including the GFX capable ones.
*
* gfxGpcCount [OUT]
* # total gpcs capable of Gfx. This is a subset of the GPCs included in gpcCount.
*
* veidCount [OUT]
* # total veids
@@ -878,14 +887,17 @@ typedef struct NV2080_CTRL_INTERNAL_DISPLAY_SETUP_RG_LINE_INTR_PARAMS {
* nvOfaCount [OUT]
* # NVOFA engines
*/
#define NV2080_CTRL_INTERNAL_GRMGR_PARTITION_MAX_TYPES 10
#define NV2080_CTRL_INTERNAL_GRMGR_PARTITION_MAX_TYPES 20
typedef struct NV2080_CTRL_INTERNAL_MIGMGR_PROFILE_INFO {
NvU32 partitionFlag;
NvU32 grCount;
NvU32 gfxGrCount;
NvU32 gpcCount;
NvU32 virtualGpcCount;
NvU32 gfxGpcCount;
NvU32 veidCount;
NvU32 smCount;
NvU32 ceCount;
@@ -1484,7 +1496,7 @@ typedef struct NV2080_CTRL_INTERNAL_FIFO_GET_NUM_CHANNELS_PARAMS {
*
* memBoundaryCfg [OUT]
* Memory boundary config (64KB aligned)
*
*
* memBoundaryCfgValInit [OUT]
* Memory boundary config initial value (64KB aligned)
*/
@@ -1591,7 +1603,7 @@ typedef struct NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_CONTROL_PARAMS {
*
* bBridgeless [IN]
* Bridgeless information, for now supporting only MIO bridges
*
*
* currLimits
* Array of limits that will be applied
*
@@ -1618,7 +1630,7 @@ typedef struct NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_SET_LIMITS_PARAMS {
* hysteresis algorithm for SLI GPU Boost synchronization:
* NV_TRUE -> enabled,
* NV_FALSE -> disabled
*
*
* bSliGpuBoostSyncEnable [OUT]
* SLI GPU Boost feature is:
* NV_TRUE -> enabled,
@@ -1736,20 +1748,25 @@ typedef struct NV2080_CTRL_INTERNAL_GMMU_REGISTER_CLIENT_SHADOW_FAULT_BUFFER_PAR
* gfId [IN]
* This specifies Id of the Kernel RM that is requesting the Boost
*
* bOverrideInfinite[IN]
* This parameter specifies if we want to override already registered infinite boost for the specific Kernel RM.
* This should be NV_TRUE only in case when we are removing the current infinite boost for a specific Kernel RM
* and setting the boost duration to a next maximum duration registered for the Kernel RM in question.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_PARAM_STRUCT
* NV_ERR_INVALID_ARGUMENT *
* NV_ERR_INVALID_ARGUMENT
*/
#define NV2080_CTRL_CMD_INTERNAL_PERF_BOOST_SET_3X (0x20800aa0) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_PERF_BOOST_SET_PARAMS_3X_MESSAGE_ID" */
#define NV2080_CTRL_INTERNAL_PERF_BOOST_SET_PARAMS_3X_MESSAGE_ID (0xA0U)
typedef struct NV2080_CTRL_INTERNAL_PERF_BOOST_SET_PARAMS_3X {
NvU32 flags;
NvU32 boostDuration;
NvU32 gfId;
NvU32 flags;
NvU32 boostDuration;
NvU32 gfId;
NvBool bOverrideInfinite;
} NV2080_CTRL_INTERNAL_PERF_BOOST_SET_PARAMS_3X;
/*!
@@ -1893,6 +1910,7 @@ typedef struct NV2080_CTRL_INTERNAL_KMIGMGR_EXPORTED_GPU_INSTANCE_INFO {
NV_DECLARE_ALIGNED(NvU64 enginesMask[NV2080_CTRL_INTERNAL_KMIGMGR_EXPORTED_GPU_INSTANCE_MAX_ENGINES_MASK_SIZE], 8);
NvU32 partitionFlags;
NvU32 gpcMask;
NvU32 virtualGpcCount;
NvU32 veidOffset;
NvU32 veidCount;
} NV2080_CTRL_INTERNAL_KMIGMGR_EXPORTED_GPU_INSTANCE_INFO;
@@ -1934,8 +1952,6 @@ typedef struct NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_PARAMS {
*/
#define NV2080_CTRL_CMD_INTERNAL_MEMSYS_FLUSH_L2_ALL_RAMS_AND_CACHES (0x20800a6d) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x6D" */
/*!
* NV2080_CTRL_CMD_INTERNAL_BIF_GET_STATIC_INFO
*
@@ -1997,7 +2013,7 @@ typedef struct NV2080_CTRL_INTERNAL_HSHUB_PEER_CONN_CONFIG_PARAMS {
*
* Possible status values returned are:
* NV_OK
*
*
*/
#define NV2080_CTRL_CMD_INTERNAL_HSHUB_FIRST_LINK_PEER_ID (0x20800a89) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_HSHUB_FIRST_LINK_PEER_ID_PARAMS_MESSAGE_ID" */
@@ -2166,6 +2182,35 @@ typedef struct NV2080_CTRL_INTERNAL_MEMSYS_PROGRAM_RAW_COMPRESSION_MODE_PARAMS {
NvBool bRawMode;
} NV2080_CTRL_INTERNAL_MEMSYS_PROGRAM_RAW_COMPRESSION_MODE_PARAMS;
/*
* NV2080_CTRL_CMD_INTERNAL_CCU_MAP
*
* This command gets the shared buffer memory descriptor from the CPU-RM and maps to it
* in physical-RM.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_INVALID_ADDRESS
*/
#define NV2080_CTRL_CMD_INTERNAL_CCU_MAP (0x20800ab3) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_CCU_MAP_INFO_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_INTERNAL_CCU_DEV_SHRBUF_COUNT_MAX 1
#define NV2080_CTRL_INTERNAL_CCU_MAP_INFO_PARAMS_MESSAGE_ID (0xB3U)
typedef struct NV2080_CTRL_INTERNAL_CCU_MAP_INFO_PARAMS {
NV_DECLARE_ALIGNED(NvU64 phyAddr[NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_PARTITION_TABLE_SIZE + NV2080_CTRL_INTERNAL_CCU_DEV_SHRBUF_COUNT_MAX], 8);
} NV2080_CTRL_INTERNAL_CCU_MAP_INFO_PARAMS;
/*
* NV2080_CTRL_CMD_INTERNAL_CCU_UNMAP
*
* This command unmaps the shared buffer memory mapping in physical-RM
*
* Possible status values returned are:
* NV_OK
*/
#define NV2080_CTRL_CMD_INTERNAL_CCU_UNMAP (0x20800ab4) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0xB4" */
/*!
@@ -2223,15 +2268,99 @@ typedef struct NV2080_CTRL_INTERNAL_BIF_SET_PCIE_RO_PARAMS {
NvBool enableRo;
} NV2080_CTRL_INTERNAL_BIF_SET_PCIE_RO_PARAMS;
/*!
* @ref NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_COMPUTE_PROFILES
* @ref NV2080_CTRL_CMD_INTERNAL_STATIC_MIGMGR_GET_COMPUTE_PROFILES
*/
#define NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_COMPUTE_PROFILES (0x20800aba) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0xba" */
/*!
* NV2080_CTRL_INTERNAL_MIGMGR_COMPUTE_PROFILE
*
* This structure specifies resources in an execution partition
*
* computeSize[OUT]
* - NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_* associated with this profile
*
* gfxGpcCount[OUT]
* - Total Number of GFX Supporting GPCs in this partition
*
* gpcCount[OUT]
* - Total Number of GPCs in this partition (including GFX Supported GPCs)
*
* veidCount[OUT]
* - Number of VEIDs allocated to this profile
*
* smCount[OUT]
* - Number of SMs usable in this profile
*/
typedef struct NV2080_CTRL_INTERNAL_MIGMGR_COMPUTE_PROFILE {
NvU8 computeSize;
NvU32 gfxGpcCount;
NvU32 gpcCount;
NvU32 veidCount;
NvU32 smCount;
} NV2080_CTRL_INTERNAL_MIGMGR_COMPUTE_PROFILE;
/*!
* NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_COMPUTE_PROFILES_PARAMS
*
* This structure specifies resources in an execution partition
*
* profileCount[OUT]
* - Total Number of profiles filled
*
* profiles[OUT]
* - NV2080_CTRL_GPU_COMPUTE_PROFILE filled with valid compute instance profiles
*/
#define NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_COMPUTE_PROFILES_PARAMS_MESSAGE_ID (0xbbU)
typedef struct NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_COMPUTE_PROFILES_PARAMS {
NvU32 profileCount;
NV2080_CTRL_INTERNAL_MIGMGR_COMPUTE_PROFILE profiles[NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE__SIZE];
} NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_COMPUTE_PROFILES_PARAMS;
/*
* NV2080_CTRL_INTERNAL_NVLINK_GET_NUM_ACTIVE_LINK_PER_IOCTRL
*
* Returns number of active links allowed per IOCTRL
*
* [Out] numActiveLinksPerIoctrl
*/
#define NV2080_CTRL_INTERNAL_NVLINK_GET_NUM_ACTIVE_LINK_PER_IOCTRL_PARAMS_MESSAGE_ID (0xD8U)
typedef struct NV2080_CTRL_INTERNAL_NVLINK_GET_NUM_ACTIVE_LINK_PER_IOCTRL_PARAMS {
NvU32 numActiveLinksPerIoctrl;
} NV2080_CTRL_INTERNAL_NVLINK_GET_NUM_ACTIVE_LINK_PER_IOCTRL_PARAMS;
#define NV2080_CTRL_INTERNAL_NVLINK_GET_NUM_ACTIVE_LINK_PER_IOCTRL (0x20800ad8U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_NVLINK_GET_NUM_ACTIVE_LINK_PER_IOCTRL_PARAMS_MESSAGE_ID" */
/*
* NV2080_CTRL_INTERNAL_NVLINK_GET_TOTAL_NUM_LINK_PER_IOCTRL
*
* Returns number of links per IOCTRL
*
* [Out] numLinksPerIoctrl
*/
#define NV2080_CTRL_INTERNAL_NVLINK_GET_TOTAL_NUM_LINK_PER_IOCTRL_PARAMS_MESSAGE_ID (0xD9U)
typedef struct NV2080_CTRL_INTERNAL_NVLINK_GET_TOTAL_NUM_LINK_PER_IOCTRL_PARAMS {
NvU32 numLinksPerIoctrl;
} NV2080_CTRL_INTERNAL_NVLINK_GET_TOTAL_NUM_LINK_PER_IOCTRL_PARAMS;
#define NV2080_CTRL_INTERNAL_NVLINK_GET_TOTAL_NUM_LINK_PER_IOCTRL (0x20800ad9U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_NVLINK_GET_TOTAL_NUM_LINK_PER_IOCTRL_PARAMS_MESSAGE_ID" */
/*!
* NV2080_CTRL_CMD_INTERNAL_GET_COHERENT_FB_APERTURE_SIZE
*
* Query Coherent FB Aperture Size.
*
*/
#define NV2080_CTRL_CMD_INTERNAL_GET_COHERENT_FB_APERTURE_SIZE (0x20800aba) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GET_COHERENT_FB_APERTURE_SIZE_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_CMD_INTERNAL_GET_COHERENT_FB_APERTURE_SIZE (0x20800ada) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GET_COHERENT_FB_APERTURE_SIZE_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_INTERNAL_GET_COHERENT_FB_APERTURE_SIZE_PARAMS_MESSAGE_ID (0xbaU)
#define NV2080_CTRL_INTERNAL_GET_COHERENT_FB_APERTURE_SIZE_PARAMS_MESSAGE_ID (0xDAU)
typedef struct NV2080_CTRL_INTERNAL_GET_COHERENT_FB_APERTURE_SIZE_PARAMS {
// Get Coherent Fb Aperture Size

3
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080lpwr.h
View File

@@ -32,6 +32,3 @@
// _ctrl2080lpwr_h_

5
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080mc.h
View File

@@ -30,9 +30,8 @@
// Source file: ctrl/ctrl2080/ctrl2080mc.finn
//
#include "ctrl/ctrl2080/ctrl2080base.h"
#include "nvcfg_sdk.h"
/* NV20_SUBDEVICE_XX mc control commands and parameters */
@@ -82,6 +81,8 @@ typedef struct NV2080_CTRL_MC_GET_ARCH_INFO_PARAMS {
/* valid ARCHITECTURE_T23X implementation values */
#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_T234 (0x00000004)
#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_T234D (0x00000005)

4
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080nvd.h
View File

@@ -30,10 +30,6 @@
// Source file: ctrl/ctrl2080/ctrl2080nvd.finn
//
#include "ctrl/ctrl2080/ctrl2080base.h"
#include "ctrl/ctrlxxxx.h"

197
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080nvlink.h
View File

@@ -30,9 +30,6 @@
// Source file: ctrl/ctrl2080/ctrl2080nvlink.finn
//
#include "ctrl/ctrl2080/ctrl2080base.h"
/* NV20_SUBDEVICE_XX bus control commands and parameters */
@@ -136,16 +133,14 @@ typedef struct NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS_PARAMS {
#define NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_2_2 (0x00000004U)
#define NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_3_0 (0x00000005U)
#define NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_3_1 (0x00000006U)
#define NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_4_0 (0x00000007U)
#define NV2080_CTRL_NVLINK_CAPS_NCI_VERSION_INVALID (0x00000000U)
#define NV2080_CTRL_NVLINK_CAPS_NCI_VERSION_1_0 (0x00000001U)
#define NV2080_CTRL_NVLINK_CAPS_NCI_VERSION_2_0 (0x00000002U)
#define NV2080_CTRL_NVLINK_CAPS_NCI_VERSION_2_2 (0x00000004U)
#define NV2080_CTRL_NVLINK_CAPS_NCI_VERSION_3_0 (0x00000005U)
#define NV2080_CTRL_NVLINK_CAPS_NCI_VERSION_3_1 (0x00000006U)
#define NV2080_CTRL_NVLINK_CAPS_NCI_VERSION_4_0 (0x00000007U)
/*
* NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS
@@ -322,8 +317,7 @@ typedef struct NV2080_CTRL_NVLINK_LINK_STATUS_INFO {
#define NV2080_CTRL_NVLINK_STATUS_LINK_STATE_SWCFG (0x00000002U)
#define NV2080_CTRL_NVLINK_STATUS_LINK_STATE_ACTIVE (0x00000003U)
#define NV2080_CTRL_NVLINK_STATUS_LINK_STATE_FAULT (0x00000004U)
#define NV2080_CTRL_NVLINK_STATUS_LINK_STATE_SLEEP (0x00000005U)
#define NV2080_CTRL_NVLINK_STATUS_LINK_STATE_RECOVERY (0x00000006U)
#define NV2080_CTRL_NVLINK_STATUS_LINK_STATE_RECOVERY_AC (0x00000008U)
#define NV2080_CTRL_NVLINK_STATUS_LINK_STATE_RECOVERY_RX (0x0000000aU)
@@ -331,7 +325,9 @@ typedef struct NV2080_CTRL_NVLINK_LINK_STATUS_INFO {
// NVLink Rx sublink states
#define NV2080_CTRL_NVLINK_STATUS_SUBLINK_RX_STATE_HIGH_SPEED_1 (0x00000000U)
#define NV2080_CTRL_NVLINK_STATUS_SUBLINK_RX_STATE_SINGLE_LANE (0x00000004U)
// TODO: @achaudhry remove SINGLE_LANE define once references switch to LOW_POWER
#define NV2080_CTRL_NVLINK_STATUS_SUBLINK_RX_STATE_SINGLE_LANE (0x00000004) // Deprecated
#define NV2080_CTRL_NVLINK_STATUS_SUBLINK_RX_STATE_LOW_POWER (0x00000004)
#define NV2080_CTRL_NVLINK_STATUS_SUBLINK_RX_STATE_TRAINING (0x00000005U)
#define NV2080_CTRL_NVLINK_STATUS_SUBLINK_RX_STATE_SAFE_MODE (0x00000006U)
#define NV2080_CTRL_NVLINK_STATUS_SUBLINK_RX_STATE_OFF (0x00000007U)
@@ -341,7 +337,9 @@ typedef struct NV2080_CTRL_NVLINK_LINK_STATUS_INFO {
// NVLink Tx sublink states
#define NV2080_CTRL_NVLINK_STATUS_SUBLINK_TX_STATE_HIGH_SPEED_1 (0x00000000U)
#define NV2080_CTRL_NVLINK_STATUS_SUBLINK_TX_STATE_SINGLE_LANE (0x00000004U)
// TODO: @achaudhry remove SINGLE_LANE define once references switch to LOW_POWER
#define NV2080_CTRL_NVLINK_STATUS_SUBLINK_TX_STATE_SINGLE_LANE (0x00000004) // Deprecated
#define NV2080_CTRL_NVLINK_STATUS_SUBLINK_TX_STATE_LOW_POWER (0x00000004)
#define NV2080_CTRL_NVLINK_STATUS_SUBLINK_TX_STATE_TRAINING (0x00000005U)
#define NV2080_CTRL_NVLINK_STATUS_SUBLINK_TX_STATE_SAFE_MODE (0x00000006U)
#define NV2080_CTRL_NVLINK_STATUS_SUBLINK_TX_STATE_OFF (0x00000007U)
@@ -396,7 +394,8 @@ typedef struct NV2080_CTRL_NVLINK_LINK_STATUS_INFO {
#define NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS_PARAMS_MESSAGE_ID (0x2U)
typedef struct NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS_PARAMS {
NvU32 enabledLinkMask;
NvU32 enabledLinkMask;
NvBool bSublinkStateInst; // whether instantaneous sublink state is needed
NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_LINK_STATUS_INFO linkInfo[NV2080_CTRL_NVLINK_MAX_LINKS], 8);
} NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS_PARAMS;
@@ -1341,8 +1340,100 @@ typedef struct NV2080_CTRL_NVLINK_INJECT_TLC_ERROR_PARAMS {
NV2080_CTRL_NVLINK_INJECT_TLC_ERROR_TYPE errorType;
} NV2080_CTRL_NVLINK_INJECT_TLC_ERROR_PARAMS;
/*
* NV2080_CTRL_CMD_NVLINK_CHECK_BRIDGE
*
* This command returns the presence and data fields of an NVLink Bridge EEPROM.
*
* [in] linkId
* The NVLink ID to check for a bridge EEPROM
* [out] bPresent
* NV_TRUE if the EEPROM chip is detected.
* [out] bValid
* NV_TRUE if the the data read passes validity checks. If so, the following
* fields are populated.
* [out] firmwareVersion
* The firmware version formatted as PPPP.SSSS.BB, e.g. 4931.0200.01.01,
* padded with one or more 0x00
* [out] bridgeVendor
* The bridge vendor name, padded with one or more 0x00
* [out] boardPartNumber
* The board part number, formatted as CCC-FPPPP-SSSS-RRR
* (e.g. 699-24931-0200-000), padded with one or more 0x00
* [out] boardRevision
* The board revision, e.g. A00, padded with one or more 0x00
* [out] configuration
* Bridge form factor (2-way/3-way/4-way).
* See NV2080_CTRL_NVLINK_BRIDGE_CONFIGURATION_*
* [out] spacing
* # of slots spacing identifier. See NV2080_CTRL_NVLINK_BRIDGE_SPACING_*
* [out] interconnectType
* Type of interconnect. See NV2080_CTRL_NVLINK_BRIDGE_INTERCONNECT_TYPE_*
* [out] interconnectWidth
* Width of interconnect NVHS lanes.
* See NV2080_CTRL_NVLINK_BRIDGE_INTERCONNECT_WIDTH_*
* [out] maximumLandDataRate
* Maximum data transfer rate in T/s, as an IEEE-754 32-bit float
* [out] featureIllumination
* Illumination feature supported.
* See NV2080_CTRL_NVLINK_BRIDGE_ILLUMINATION_FEATURE_*
* [out] businessUnit
* Business unit identifier.
*/
#define NV2080_CTRL_CMD_NVLINK_CHECK_BRIDGE (0x20803010U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_CHECK_BRIDGE_PARAMS_MESSAGE_ID" */
// ASCII bytes plus space for null terminator
#define NV2080_CTRL_NVLINK_BRIDGE_FIRMWARE_VERSION_LENGTH (0x11U) /* finn: Evaluated from "(16 + 1)" */
#define NV2080_CTRL_NVLINK_BRIDGE_VENDOR_LENGTH (0x15U) /* finn: Evaluated from "(20 + 1)" */
#define NV2080_CTRL_NVLINK_BRIDGE_BOARD_PART_NUMBER_LENGTH (0x15U) /* finn: Evaluated from "(20 + 1)" */
#define NV2080_CTRL_NVLINK_BRIDGE_BOARD_REVISION_LENGTH (0x4U) /* finn: Evaluated from "(3 + 1)" */
#define NV2080_CTRL_NVLINK_BRIDGE_CONFIGURATION_UNDEFINED (0x00U)
#define NV2080_CTRL_NVLINK_BRIDGE_CONFIGURATION_2_WAY (0x02U)
#define NV2080_CTRL_NVLINK_BRIDGE_CONFIGURATION_3_WAY (0x03U)
#define NV2080_CTRL_NVLINK_BRIDGE_CONFIGURATION_4_WAY (0x04U)
#define NV2080_CTRL_NVLINK_BRIDGE_SPACING_UNDEFINED (0x00U)
#define NV2080_CTRL_NVLINK_BRIDGE_SPACING_2_SLOT (0x02U)
#define NV2080_CTRL_NVLINK_BRIDGE_SPACING_3_SLOT (0x03U)
#define NV2080_CTRL_NVLINK_BRIDGE_SPACING_4_SLOT (0x04U)
#define NV2080_CTRL_NVLINK_BRIDGE_INTERCONNECT_TYPE_UNDEFINED (0x00U)
#define NV2080_CTRL_NVLINK_BRIDGE_INTERCONNECT_TYPE_NVLINK_2 (0x02U)
#define NV2080_CTRL_NVLINK_BRIDGE_INTERCONNECT_TYPE_NVLINK_3 (0x03U)
#define NV2080_CTRL_NVLINK_BRIDGE_INTERCONNECT_WIDTH_UNDEFINED (0x00U)
#define NV2080_CTRL_NVLINK_BRIDGE_INTERCONNECT_WIDTH_4_LANES (0x02U)
#define NV2080_CTRL_NVLINK_BRIDGE_INTERCONNECT_WIDTH_8_LANES (0x03U)
#define NV2080_CTRL_NVLINK_BRIDGE_INTERCONNECT_WIDTH_16_LANES (0x04U)
#define NV2080_CTRL_NVLINK_BRIDGE_ILLUMINATION_FEATURE_NONE (0x00U)
#define NV2080_CTRL_NVLINK_BRIDGE_ILLUMINATION_FEATURE_SINGLE_COLOR (0x01U)
#define NV2080_CTRL_NVLINK_BRIDGE_ILLUMINATION_FEATURE_RGB (0x02U)
#define NV2080_CTRL_NVLINK_CHECK_BRIDGE_PARAMS_MESSAGE_ID (0x10U)
typedef struct NV2080_CTRL_NVLINK_CHECK_BRIDGE_PARAMS {
NvU32 linkId;
NvBool bPresent;
NvBool bValid;
char firmwareVersion[NV2080_CTRL_NVLINK_BRIDGE_FIRMWARE_VERSION_LENGTH];
char bridgeVendor[NV2080_CTRL_NVLINK_BRIDGE_VENDOR_LENGTH];
char boardPartNumber[NV2080_CTRL_NVLINK_BRIDGE_BOARD_PART_NUMBER_LENGTH];
char boardRevision[NV2080_CTRL_NVLINK_BRIDGE_BOARD_REVISION_LENGTH];
NvU8 businessUnit;
NvU8 configuration;
NvU8 spacing;
NvU8 interconnectType;
NvU8 interconnectWidth;
NvF32 maximumLaneDataRate;
NvU8 featureIllumination;
} NV2080_CTRL_NVLINK_CHECK_BRIDGE_PARAMS;
/*
* NV2080_CTRL_CMD_NVLINK_GET_LINK_FOM_VALUES
*
@@ -1659,8 +1750,7 @@ typedef struct NV2080_CTRL_NVLINK_GET_LP_COUNTERS_PARAMS {
#define NV2080_NVLINK_CORE_LINK_STATE_RESET 0x07U
#define NV2080_NVLINK_CORE_LINK_STATE_ENABLE_PM 0x08U
#define NV2080_NVLINK_CORE_LINK_STATE_DISABLE_PM 0x09U
#define NV2080_NVLINK_CORE_LINK_STATE_SLEEP 0x0AU
#define NV2080_NVLINK_CORE_LINK_STATE_SAVE_STATE 0x0BU
#define NV2080_NVLINK_CORE_LINK_STATE_RESTORE_STATE 0x0CU
#define NV2080_NVLINK_CORE_LINK_STATE_PRE_HS 0x0EU
@@ -1676,8 +1766,9 @@ typedef struct NV2080_CTRL_NVLINK_GET_LP_COUNTERS_PARAMS {
#define NV2080_NVLINK_CORE_LINK_STATE_DISABLE_HEARTBEAT 0x18U
#define NV2080_NVLINK_CORE_LINK_STATE_CONTAIN 0x19U
#define NV2080_NVLINK_CORE_LINK_STATE_INITTL 0x1AU
#define NV2080_NVLINK_CORE_LINK_STATE_INITPHASE5 0x1BU
#define NV2080_NVLINK_CORE_LINK_STATE_ALI 0x1CU
#define NV2080_NVLINK_CORE_LINK_STATE_ACTIVE_PENDING 0x1DU
#define NV2080_NVLINK_CORE_LINK_STATE_INVALID 0xFFU
/*
@@ -1686,6 +1777,7 @@ typedef struct NV2080_CTRL_NVLINK_GET_LP_COUNTERS_PARAMS {
*/
#define NV2080_NVLINK_CORE_SUBLINK_STATE_TX_HS 0x00U
#define NV2080_NVLINK_CORE_SUBLINK_STATE_TX_SINGLE_LANE 0x04U
#define NV2080_NVLINK_CORE_SUBLINK_STATE_TX_LOW_POWER 0x04U
#define NV2080_NVLINK_CORE_SUBLINK_STATE_TX_TRAIN 0x05U
#define NV2080_NVLINK_CORE_SUBLINK_STATE_TX_SAFE 0x06U
#define NV2080_NVLINK_CORE_SUBLINK_STATE_TX_OFF 0x07U
@@ -1702,6 +1794,7 @@ typedef struct NV2080_CTRL_NVLINK_GET_LP_COUNTERS_PARAMS {
*/
#define NV2080_NVLINK_CORE_SUBLINK_STATE_RX_HS 0x00U
#define NV2080_NVLINK_CORE_SUBLINK_STATE_RX_SINGLE_LANE 0x04U
#define NV2080_NVLINK_CORE_SUBLINK_STATE_RX_LOW_POWER 0x04U
#define NV2080_NVLINK_CORE_SUBLINK_STATE_RX_TRAIN 0x05U
#define NV2080_NVLINK_CORE_SUBLINK_STATE_RX_SAFE 0x06U
#define NV2080_NVLINK_CORE_SUBLINK_STATE_RX_OFF 0x07U
@@ -1970,7 +2063,21 @@ typedef struct NV2080_CTRL_NVLINK_CORE_CALLBACK_PARAMS {
#define NV2080_CTRL_CMD_NVLINK_CORE_CALLBACK (0x20803019U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_CORE_CALLBACK_PARAMS_MESSAGE_ID" */
/*
* NV2080_CTRL_CMD_NVLINK_GET_ALI_ENABLED
*
* Returns if ALI is enabled
*
* [Out] bEnableAli
* Output boolean for ALI enablement
*/
#define NV2080_CTRL_NVLINK_GET_ALI_ENABLED_PARAMS_MESSAGE_ID (0x1aU)
typedef struct NV2080_CTRL_NVLINK_GET_ALI_ENABLED_PARAMS {
NvBool bEnableAli;
} NV2080_CTRL_NVLINK_GET_ALI_ENABLED_PARAMS;
#define NV2080_CTRL_CMD_NVLINK_GET_ALI_ENABLED (0x2080301aU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_GET_ALI_ENABLED_PARAMS_MESSAGE_ID" */
/*
* NV2080_CTRL_CMD_NVLINK_UPDATE_REMOTE_LOCAL_SID
@@ -2229,7 +2336,22 @@ typedef struct NV2080_CTRL_NVLINK_ENABLE_LINKS_POST_TOPOLOGY_PARAMS {
#define NV2080_CTRL_CMD_NVLINK_ENABLE_LINKS_POST_TOPOLOGY (0x20803026U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_ENABLE_LINKS_POST_TOPOLOGY_PARAMS_MESSAGE_ID" */
/*
* NV2080_CTRL_CMD_NVLINK_PRE_LINK_TRAIN_ALI
*
* [In] linkMask
* Mask of enabled links to train
* [In] bSync
* The input sync boolean
*/
#define NV2080_CTRL_NVLINK_PRE_LINK_TRAIN_ALI_PARAMS_MESSAGE_ID (0x27U)
typedef struct NV2080_CTRL_NVLINK_PRE_LINK_TRAIN_ALI_PARAMS {
NvU32 linkMask;
NvBool bSync;
} NV2080_CTRL_NVLINK_PRE_LINK_TRAIN_ALI_PARAMS;
#define NV2080_CTRL_CMD_NVLINK_PRE_LINK_TRAIN_ALI (0x20803027U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_PRE_LINK_TRAIN_ALI_PARAMS_MESSAGE_ID" */
//
// Read Refresh counter - the pass/fail occurrences
@@ -2301,7 +2423,22 @@ typedef struct NV2080_CTRL_NVLINK_GET_LINK_MASK_POST_RX_DET_PARAMS {
#define NV2080_CTRL_CMD_NVLINK_GET_LINK_MASK_POST_RX_DET (0x2080302aU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_GET_LINK_MASK_POST_RX_DET_PARAMS_MESSAGE_ID" */
/*
* NV2080_CTRL_CMD_NVLINK_LINK_TRAIN_ALI
*
* [In] linkMask
* Mask of enabled links to train
* [In] bSync
* The input sync boolean
*/
#define NV2080_CTRL_NVLINK_LINK_TRAIN_ALI_PARAMS_MESSAGE_ID (0x2bU)
typedef struct NV2080_CTRL_NVLINK_LINK_TRAIN_ALI_PARAMS {
NvU32 linkMask;
NvBool bSync;
} NV2080_CTRL_NVLINK_LINK_TRAIN_ALI_PARAMS;
#define NV2080_CTRL_CMD_NVLINK_LINK_TRAIN_ALI (0x2080302bU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_LINK_TRAIN_ALI_PARAMS_MESSAGE_ID" */
typedef struct NV2080_CTRL_NVLINK_DEVICE_LINK_VALUES {
NvBool bValid;
@@ -2524,6 +2661,7 @@ typedef struct NV2080_CTRL_NVLINK_GET_LINK_AND_CLOCK_VALUES {
typedef struct NV2080_CTRL_NVLINK_GET_LINK_AND_CLOCK_INFO_PARAMS {
NvU32 linkMask;
NvU32 nvlinkRefClkSpeedKHz;
NvBool bSublinkStateInst; // whether instantaneous sublink state is needed
NV2080_CTRL_NVLINK_GET_LINK_AND_CLOCK_VALUES linkInfo[NV2080_CTRL_NVLINK_MAX_LINKS];
} NV2080_CTRL_NVLINK_GET_LINK_AND_CLOCK_INFO_PARAMS;
@@ -2720,4 +2858,31 @@ typedef struct NV2080_CTRL_NVLINK_PROCESS_INIT_DISABLED_LINKS_PARAMS {
#define NV2080_CTRL_CMD_NVLINK_PROCESS_INIT_DISABLED_LINKS (0x2080303bU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_PROCESS_INIT_DISABLED_LINKS_PARAMS_MESSAGE_ID" */
/*
* NV2080_CTRL_CMD_NVLINK_EOM_CONTROL
*
* cmd [IN] enum identifying the EOM related command for the driver to process
* link [IN] linkId
* params [IN] NvU32 word that is written into NV_PMINION_SCRATCH_SWRW_0 before calling CONFIGEOM dlcmd
*
* Params Packing is specified in Minion IAS
*/
typedef enum NV2080_CTRL_CMD_NVLINK_EOM_CONTROL_PARAMS_COMMAND {
NVLINK_EOM_CONTROL_START_EOM = 0,
NVLINK_EOM_CONTROL_END_EOM = 1,
NVLINK_EOM_CONTROL_CONFIG_EOM = 2,
NVLINK_EOM_CONTROL_FULL_EOM_SEQUENCE = 3,
} NV2080_CTRL_CMD_NVLINK_EOM_CONTROL_PARAMS_COMMAND;
#define NV2080_CTRL_NVLINK_EOM_CONTROL_PARAMS_MESSAGE_ID (0x3cU)
typedef struct NV2080_CTRL_NVLINK_EOM_CONTROL_PARAMS {
NV2080_CTRL_CMD_NVLINK_EOM_CONTROL_PARAMS_COMMAND cmd;
NvU32 linkId;
NvU32 params;
} NV2080_CTRL_NVLINK_EOM_CONTROL_PARAMS;
#define NV2080_CTRL_CMD_NVLINK_EOM_CONTROL (0x2080303c) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_EOM_CONTROL_PARAMS_MESSAGE_ID" */
/* _ctrl2080nvlink_h_ */

3
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080perf.h
View File

@@ -30,9 +30,6 @@
// Source file: ctrl/ctrl2080/ctrl2080perf.finn
//
#include "nvfixedtypes.h"
#include "ctrl/ctrl2080/ctrl2080base.h"

1
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080perf_cf.h
View File

@@ -31,4 +31,3 @@
/* _ctrl2080perf_cf_h_ */

3
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080rc.h
View File

@@ -30,9 +30,6 @@
// Source file: ctrl/ctrl2080/ctrl2080rc.finn
//
#include "ctrl/ctrl2080/ctrl2080base.h"
/*

3
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080tmr.h
View File

@@ -30,9 +30,6 @@
// Source file: ctrl/ctrl2080/ctrl2080tmr.finn
//
#include "ctrl/ctrl2080/ctrl2080base.h"
/* NV20_SUBDEVICE_TIMER related control commands and parameters */

3
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080unix.h
View File

@@ -30,9 +30,6 @@
// Source file: ctrl/ctrl2080/ctrl2080unix.finn
//
#include "ctrl/ctrl2080/ctrl2080base.h"
/* NV20_SUBDEVICE_XX OS control commands and parameters */

2
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080vfe.h
View File

@@ -31,8 +31,6 @@
/* _ctrl2080vfe_h_ */
#include "nvfixedtypes.h"
#include "ctrl/ctrl2080/ctrl2080base.h"
#include "ctrl/ctrl2080/ctrl2080boardobj.h"

3
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080volt.h
View File

@@ -32,9 +32,6 @@
/* _ctrl2080volt_h_ */
#include "ctrl/ctrl2080/ctrl2080base.h"
#include "ctrl/ctrl2080/ctrl2080boardobj.h"
#include "ctrl/ctrl2080/ctrl2080pmumon.h"