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This commit is contained in:
Andy Ritger
2022-10-10 14:59:24 -07:00
parent fe0728787f
commit 90eb10774f
758 changed files with 88383 additions and 26493 deletions
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6
src/nvidia/arch/nvalloc/common/inc/flcnretval.h
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@@ -130,6 +130,7 @@ typedef NvU8 FLCN_STATUS;
// because that will affect other binaries and their signatures
//
#define FLCN_ERR_CTXSW_ERROR (0x4EU)
#define FLCN_ERR_SE_SNPKA_HW_CRYPTO_OPERATION_FAILED (0x4FU)
// VPR SEC2 task errors
#define FLCN_ERR_VPR_APP_INVALID_REQUEST_END_ADDR (0x51U)
@@ -232,6 +233,8 @@ typedef NvU8 FLCN_STATUS;
#define FLCN_ERR_HS_APM_FECS_NOT_HALTED (0xCEU)
#define FLCN_ERR_HS_APM_SCRATCH_PLM_INVALID (0xCFU)
#define FLCN_ERR_HS_APM_SCRATCH_INIT_INVALID (0xD0U)
#define FLCN_ERR_HS_INVALID_KEY (0xD1U)
#define FLCN_ERR_HS_SWKG_INVALID_SIGNATURE (0xD2U)
//
@@ -283,4 +286,7 @@ typedef NvU8 FLCN_STATUS;
#define FLCN_ERR_AUTH_GSP_RM_HANDOFF_FAILED (0xF8U)
#define FLCN_ERR_INVALID_WPRMETA_MAGIC_OR_REVISION (0xF9U)
// Arithmetic errors
#define FLCN_ERR_ARITHMETIC_OVERFLOW (0xFAU)
#endif // FLCNRETVAL_H

44
src/nvidia/arch/nvalloc/common/inc/fsp/nvdm_payload_cmd_response.h Normal file
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@@ -0,0 +1,44 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
/*
* @file nvdm_payload_cmd_response.h
* @brief Header file containing the definition for the
* NVDM_PAYLOAD_COMMAND_RESPONSE structure, which
* is required for SMBPBI-specific payloads and needs
* to be visible by bothe the PMU and the driver sides.
*/
#ifndef _NVDM_PAYLOAD_CMD_RESPONSE_H
#define _NVDM_PAYLOAD_CMD_RESPONSE_H
#pragma pack(1)
typedef struct
{
NvU32 taskId;
NvU32 commandNvdmType;
NvU32 errorCode;
} NVDM_PAYLOAD_COMMAND_RESPONSE;
#pragma pack()
#endif // _NVDM_PAYLOAD_CMD_RESPONSE_H

94
src/nvidia/arch/nvalloc/common/inc/gsp/gspifpub.h Normal file
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@@ -0,0 +1,94 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef GSPIFPUB_H
#define GSPIFPUB_H
#include <nvtypes.h>
/*!
* @file gspifpub.h
* @brief GSP Command/Message Interfaces - Published
*/
/*!
* Target physical memory apertures supported for DMA
*/
typedef enum {
GSP_DMA_TARGET_LOCAL_FB,
GSP_DMA_TARGET_COHERENT_SYSTEM,
GSP_DMA_TARGET_NONCOHERENT_SYSTEM,
GSP_DMA_TARGET_COUNT
} GSP_DMA_TARGET;
/*!
* @brief GSP-CC Microcode Initialization Parameters
*/
typedef struct GSP_CC_INIT_PARAMS
{
// CC initialization "registry keys"
NvU32 regkeys;
} GSP_CC_INIT_PARAMS;
/*!
* @brief GSP-ACR BOOT_GSP_RM Command Parameters
*
* The wprCarveout fields have no effect in environments where the WPR can be allocated
* implicitly by ACR.
*/
typedef struct GSP_ACR_BOOT_GSP_RM_PARAMS
{
// Physical memory aperture through which gspRmDescPa is accessed
GSP_DMA_TARGET target;
// Size in bytes of the GSP-RM descriptor structure
NvU32 gspRmDescSize;
// Physical offset in the target aperture of the GSP-RM descriptor structure
NvU64 gspRmDescOffset;
// Physical offset in FB to set the start of the WPR containing GSP-RM
NvU64 wprCarveoutOffset;
// Size in bytes of the WPR containing GSP-RM
NvU32 wprCarveoutSize;
} GSP_ACR_BOOT_GSP_RM_PARAMS;
/*!
* @brief GSP-RM Parameters
*/
typedef struct GSP_RM_PARAMS
{
// Physical memory aperture through which bootArgsPa is accessed
GSP_DMA_TARGET target;
// Physical address that will be stuffed in NV_PGSP_FALCON_MAILBOX(0|1)
NvU64 bootArgsOffset;
} GSP_RM_PARAMS;
/*!
* @brief GSP-CC Microcode Parameters for Boot Partitions
*/
typedef struct GSP_CC_BOOT_PARAMS
{
GSP_CC_INIT_PARAMS initParams;
GSP_ACR_BOOT_GSP_RM_PARAMS bootGspRmParams;
GSP_RM_PARAMS gspRmParams;
} GSP_CC_BOOT_PARAMS;
#endif // GSPIFPUB_H

10
src/nvidia/arch/nvalloc/common/inc/nvcst.h
View File

@@ -61,6 +61,7 @@ CHIPSET_SETUP_FUNC(Intel_A2D2_setupFunc)
CHIPSET_SETUP_FUNC(Intel_A2C9_setupFunc)
CHIPSET_SETUP_FUNC(Intel_A301_setupFunc)
CHIPSET_SETUP_FUNC(Intel_0685_setupFunc)
CHIPSET_SETUP_FUNC(Intel_IceLake_setupFunc)
CHIPSET_SETUP_FUNC(Intel_4381_setupFunc)
CHIPSET_SETUP_FUNC(Intel_7A82_setupFunc)
CHIPSET_SETUP_FUNC(Intel_7A04_setupFunc)
@@ -177,13 +178,13 @@ CSINFO chipsetInfo[] =
{PCI_VENDOR_ID_INTEL, 0xA30D, CS_INTEL_A2C9, "IntelH370", Intel_A2C9_setupFunc},
{PCI_VENDOR_ID_INTEL, 0xA301, CS_INTEL_A301, "Intel-CannonLake", Intel_A301_setupFunc},
{PCI_VENDOR_ID_INTEL, 0x0685, CS_INTEL_0685, "Intel-CometLake", Intel_0685_setupFunc},
{PCI_VENDOR_ID_INTEL, 0xA1CB, CS_INTEL_C620, "Intel-IceLake", NULL},
{PCI_VENDOR_ID_INTEL, 0xA1CB, CS_INTEL_C620, "Intel-IceLake", Intel_IceLake_setupFunc},
{PCI_VENDOR_ID_INTEL, 0x4381, CS_INTEL_4381, "Intel-RocketLake", Intel_4381_setupFunc},
{PCI_VENDOR_ID_INTEL, 0x4385, CS_INTEL_4381, "Intel-RocketLake", Intel_4381_setupFunc},
{PCI_VENDOR_ID_INTEL, 0x7A82, CS_INTEL_7A82, "Intel-AlderLake", Intel_7A82_setupFunc},
{PCI_VENDOR_ID_INTEL, 0x7A84, CS_INTEL_7A82, "Intel-AlderLake", Intel_7A82_setupFunc},
{PCI_VENDOR_ID_INTEL, 0x1B81, CS_INTEL_1B81, "Intel-SapphireRapids", NULL},
{PCI_VENDOR_ID_INTEL, 0x18DC, CS_INTEL_18DC, "Intel-IceLake", NULL},
{PCI_VENDOR_ID_INTEL, 0x18DC, CS_INTEL_18DC, "Intel-IceLake", Intel_IceLake_setupFunc},
{PCI_VENDOR_ID_INTEL, 0x7A04, CS_INTEL_7A04, "Intel-RaptorLake", Intel_7A04_setupFunc},
{PCI_VENDOR_ID_NVIDIA, 0x0FAE, CS_NVIDIA_T210, "T210", Nvidia_T210_setupFunc},
@@ -196,7 +197,8 @@ CSINFO chipsetInfo[] =
{PCI_VENDOR_ID_NVIDIA, 0x229A, CS_NVIDIA_T234, "T234", Nvidia_T194_setupFunc},
{PCI_VENDOR_ID_NVIDIA, 0x229C, CS_NVIDIA_T234, "T234", Nvidia_T194_setupFunc},
{PCI_VENDOR_ID_NVIDIA, 0x229E, CS_NVIDIA_T234, "T234", Nvidia_T194_setupFunc},
{PCI_VENDOR_ID_NVIDIA, 0x22C2, CS_NVIDIA_T23x, "T23x", Nvidia_T194_setupFunc},
{PCI_VENDOR_ID_NVIDIA, 0x22C3, CS_NVIDIA_T23x, "T23x", Nvidia_T194_setupFunc},
{PCI_VENDOR_ID_SIS, 0x0649, CS_SIS_649, "649", SiS_656_setupFunc},
{PCI_VENDOR_ID_SIS, 0x0656, CS_SIS_656, "656", SiS_656_setupFunc},
@@ -313,6 +315,8 @@ ARMCSALLOWLISTINFO armChipsetAllowListInfo[] =
{PCI_VENDOR_ID_NVIDIA, 0x229A, CS_NVIDIA_T234}, // NVIDIA Tegra Orin RP0
{PCI_VENDOR_ID_NVIDIA, 0x229C, CS_NVIDIA_T234}, // NVIDIA Tegra Orin RP1
{PCI_VENDOR_ID_NVIDIA, 0x229E, CS_NVIDIA_T234}, // NVIDIA Tegra Orin RP2
{PCI_VENDOR_ID_NVIDIA, 0x22C2, CS_NVIDIA_T23x}, // NVIDIA Tegra RP0
{PCI_VENDOR_ID_NVIDIA, 0x22C3, CS_NVIDIA_T23x}, // NVIDIA Tegra RP1
{PCI_VENDOR_ID_APM, 0xe004, CS_APM_STORM}, // Applied Micro X-Gene "Storm"
{PCI_VENDOR_ID_MARVELL, 0xAF00, CS_MARVELL_THUNDERX2}, // Marvell ThunderX2

1
src/nvidia/arch/nvalloc/common/inc/nvdevid.h
View File

@@ -625,6 +625,7 @@ enum {
, CS_NVIDIA_T186
, CS_NVIDIA_T194
, CS_NVIDIA_T234
, CS_NVIDIA_T23x
, CS_MARVELL_THUNDERX2
, CS_REDHAT_QEMU
, CS_AMPERE_EMAG

118
src/nvidia/arch/nvalloc/common/inc/oob/smbpbi.h
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@@ -96,6 +96,8 @@
#define NV_MSGBOX_CMD_OPCODE_RESERVED_0 0x00000024
#define NV_MSGBOX_CMD_OPCODE_RESERVED_1 0x00000025
#define NV_MSGBOX_CMD_OPCODE_GET_POWER_HINT_INFO 0x00000026
#define NV_MSGBOX_CMD_OPCODE_DYNAMIC_SYSTEM_INFORMATION 0x00000027
#define NV_MSGBOX_CMD_OPCODE_GPU_PERFORMANCE_MONITORING 0x00000028
#define NV_MSGBOX_CMD_ARG1 15:8
#define NV_MSGBOX_CMD_ARG1_NULL 0x00000000
@@ -105,7 +107,8 @@
#define NV_MSGBOX_CMD_ARG1_TEMP_BOARD 0x00000004
#define NV_MSGBOX_CMD_ARG1_TEMP_MEMORY 0x00000005
#define NV_MSGBOX_CMD_ARG1_TEMP_PWR_SUPPLY 0x00000006
#define NV_MSGBOX_CMD_ARG1_TEMP_NUM_SENSORS 7
#define NV_MSGBOX_CMD_ARG1_TEMP_T_LIMIT 0x00000007
#define NV_MSGBOX_CMD_ARG1_TEMP_NUM_SENSORS 8
#define NV_MSGBOX_CMD_ARG1_POWER_TOTAL 0x00000000
#define NV_MSGBOX_CMD_ARG1_SMBPBI_POWER 0x00000001
/* SysId info type encodings for opcode NV_MSGBOX_CMD_OPCODE_GET_SYS_ID_DATA (0x05) */
@@ -318,6 +321,33 @@
#define NV_MSGBOX_CMD_ARG1_GET_POWER_HINT_INFO_NUM \
(NV_MSGBOX_CMD_ARG1_GET_POWER_HINT_INFO_PROFILES + 1)
// Arg1 for _GPU_PERFORMANCE_MONITORING
#define NV_MSGBOX_CMD_ARG1_GPM_ACTION 15:14
#define NV_MSGBOX_CMD_ARG1_GPM_ACTION_GET_INSTANTANEOUS_METRIC 0x00000000
#define NV_MSGBOX_CMD_ARG1_GPM_ACTION_GET_SNAPSHOT_METRIC 0x00000001
#define NV_MSGBOX_CMD_ARG1_GPM_ACTION_CAPTURE_SNAPSHOT 0x00000002
#define NV_MSGBOX_CMD_ARG1_GPM_ACTION_SET_MULTIPLIER 0x00000003
#define NV_MSGBOX_CMD_ARG1_GPM_METRIC 13:8
#define NV_MSGBOX_CMD_ARG1_GPM_METRIC_GRAPHICS_ENGINE 0x00000000
#define NV_MSGBOX_CMD_ARG1_GPM_METRIC_SM_ACTIVITY 0x00000001
#define NV_MSGBOX_CMD_ARG1_GPM_METRIC_SM_OCCUPANCY 0x00000002
#define NV_MSGBOX_CMD_ARG1_GPM_METRIC_TENSOR_CORE_ACTIVITY 0x00000003
#define NV_MSGBOX_CMD_ARG1_GPM_METRIC_DRAM_USAGE 0x00000004
#define NV_MSGBOX_CMD_ARG1_GPM_METRIC_FP64_ACTIVITY 0x00000005
#define NV_MSGBOX_CMD_ARG1_GPM_METRIC_FP32_ACTIVITY 0x00000006
#define NV_MSGBOX_CMD_ARG1_GPM_METRIC_FP16_ACTIVITY 0x00000007
#define NV_MSGBOX_CMD_ARG1_GPM_METRIC_PCIE_TX_BANDWIDTH 0x00000008
#define NV_MSGBOX_CMD_ARG1_GPM_METRIC_PCIE_RX_BANDWIDTH 0x00000009
#define NV_MSGBOX_CMD_ARG1_GPM_METRIC_NVLINK_RAW_TX_BANDWIDTH 0x0000000A
#define NV_MSGBOX_CMD_ARG1_GPM_METRIC_NVLINK_DATA_TX_BANDWIDTH 0x0000000B
#define NV_MSGBOX_CMD_ARG1_GPM_METRIC_NVLINK_RAW_RX_BANDWIDTH 0x0000000C
#define NV_MSGBOX_CMD_ARG1_GPM_METRIC_NVLINK_DATA_RX_BANDWIDTH 0x0000000D
#define NV_MSGBOX_CMD_ARG1_GPM_METRIC_NVDEC_UTILIZATION 0x0000000E
#define NV_MSGBOX_CMD_ARG1_GPM_METRIC_NVJPG_UTILIZATION 0x0000000F
#define NV_MSGBOX_CMD_ARG1_GPM_METRIC_NVOFA_UTILIZATION 0x00000010
#define NV_MSGBOX_CMD_ARG1_DYN_SYS_INFO_DRIVER_VERSION_V1 0x00000000
#define NV_MSGBOX_CMD_ARG2 23:16
#define NV_MSGBOX_CMD_ARG2_NULL 0x00000000
@@ -409,6 +439,17 @@
#define NV_MSGBOX_CMD_ARG2_GET_POWER_HINT_INFO_PROFILES_TOTAL_PAGES \
(NV_MSGBOX_CMD_ARG2_GET_POWER_HINT_INFO_PROFILES_PAGE_3 + 1)
// Arg2 for _GPU_PERFORMANCE_MONITORING
#define NV_MSGBOX_CMD_ARG2_GPM_PARTITION 23:16
#define NV_MSGBOX_CMD_ARG2_GPM_PARTITION_AGGREGATE 0x000000FF
#define NV_MSGBOX_CMD_ARG2_GPM_MULTIPLIER 23:16
#define NV_MSGBOX_CMD_ARG2_GPM_MULTIPLIER_1X 0x00000001
#define NV_MSGBOX_CMD_ARG2_GPM_MULTIPLIER_2X 0x00000002
#define NV_MSGBOX_CMD_ARG2_GPM_MULTIPLIER_5X 0x00000005
#define NV_MSGBOX_CMD_ARG2_GPM_MULTIPLIER_10X 0x0000000A
#define NV_MSGBOX_CMD_ARG2_GPM_MULTIPLIER_100X 0x00000064
#define NV_MSGBOX_CMD_STATUS 28:24
#define NV_MSGBOX_CMD_STATUS_NULL 0x00000000
@@ -502,6 +543,22 @@
*/
#define NV_MSGBOX_CMD_NVLINK_INFO_GET_NVLINK_INFO_AVAILABILTY_PAGE_0 0x00000000
/**
* This field is populated as response to the following metrics:
* - NV_MSGBOX_CMD_ARG1_GPM_METRIC_DRAM_USAGE
* - NV_MSGBOX_CMD_ARG1_GPM_METRIC_PCIE_TX_BANDWIDTH
* - NV_MSGBOX_CMD_ARG1_GPM_METRIC_PCIE_RX_BANDWIDTH
* - NV_MSGBOX_CMD_ARG1_GPM_METRIC_NVLINK_RAW_TX_BANDWIDTH
* - NV_MSGBOX_CMD_ARG1_GPM_METRIC_NVLINK_DATA_TX_BANDWIDTH
* - NV_MSGBOX_CMD_ARG1_GPM_METRIC_NVLINK_RAW_RX_BANDWIDTH
* - NV_MSGBOX_CMD_ARG1_GPM_METRIC_NVLINK_DATA_RX_BANDWIDTH
*/
#define NV_MSGBOX_CMD_GPM_DATA_GRANULARITY 2:0
#define NV_MSGBOX_CMD_GPM_DATA_GRANULARITY_B 0x00000000
#define NV_MSGBOX_CMD_GPM_DATA_GRANULARITY_KIB 0x00000001
#define NV_MSGBOX_CMD_GPM_DATA_GRANULARITY_MIB 0x00000002
#define NV_MSGBOX_CMD_GPM_DATA_GRANULARITY_GIB 0x00000003
/* MSGBOX data, capability dword structure */
#define NV_MSGBOX_DATA_REG 31:0
@@ -526,6 +583,9 @@
#define NV_MSGBOX_DATA_CAP_0_TEMP_PWR_SUPPLY 6:6
#define NV_MSGBOX_DATA_CAP_0_TEMP_PWR_SUPPLY_NOT_AVAILABLE 0x00000000
#define NV_MSGBOX_DATA_CAP_0_TEMP_PWR_SUPPLY_AVAILABLE 0x00000001
#define NV_MSGBOX_DATA_CAP_0_TEMP_T_LIMIT 7:7
#define NV_MSGBOX_DATA_CAP_0_TEMP_T_LIMIT_NOT_AVAILABLE 0x00000000
#define NV_MSGBOX_DATA_CAP_0_TEMP_T_LIMIT_AVAILABLE 0x00000001
#define NV_MSGBOX_DATA_CAP_0_EXT_TEMP_BITS 11:8
#define NV_MSGBOX_DATA_CAP_0_EXT_TEMP_BITS_ZERO 0x00000000
#define NV_MSGBOX_DATA_CAP_0_EXT_TEMP_BITS_ADT7473 0x00000002
@@ -759,9 +819,15 @@
#define NV_MSGBOX_DATA_CAP_4_FAN_CURVE_POINTS_GET_SET 11:11
#define NV_MSGBOX_DATA_CAP_4_FAN_CURVE_POINTS_GET_SET_NOT_AVAILABLE 0x00000000
#define NV_MSGBOX_DATA_CAP_4_FAN_CURVE_POINTS_GET_SET_AVAILABLE 0x00000001
#define NV_MSGBOX_DATA_CAP_4_POWER_HINT 22:22
#define NV_MSGBOX_DATA_CAP_4_POWER_HINT_NOT_AVAILABLE 0x00000000
#define NV_MSGBOX_DATA_CAP_4_POWER_HINT_AVAILABLE 0x00000001
#define NV_MSGBOX_DATA_CAP_4_POWER_HINT 22:22
#define NV_MSGBOX_DATA_CAP_4_POWER_HINT_NOT_AVAILABLE 0x00000000
#define NV_MSGBOX_DATA_CAP_4_POWER_HINT_AVAILABLE 0x00000001
#define NV_MSGBOX_DATA_CAP_4_DRIVER_VERSION_V1 23:23
#define NV_MSGBOX_DATA_CAP_4_DRIVER_VERSION_V1_NOT_AVAILABLE 0x00000000
#define NV_MSGBOX_DATA_CAP_4_DRIVER_VERSION_V1_AVAILABLE 0x00000001
#define NV_MSGBOX_DATA_CAP_4_GPU_PERFORMANCE_MONITORING 24:24
#define NV_MSGBOX_DATA_CAP_4_GPU_PERFORMANCE_MONITORING_NOT_AVAILABLE 0x00000000
#define NV_MSGBOX_DATA_CAP_4_GPU_PERFORMANCE_MONITORING_AVAILABLE 0x00000001
/* ECC counters */
#define NV_MSGBOX_DATA_ECC_CNT_16BIT_DBE 31:16
@@ -1194,6 +1260,8 @@
#define NV_MSGBOX_DATA_POWER_HINT_INFO_PROFILES_PAGE_0_CUSTOMER_CUSTOM_7_NOT_AVAILABLE 0
#define NV_MSGBOX_DATA_POWER_HINT_INFO_PROFILES_PAGE_0_CUSTOMER_CUSTOM_7_AVAILABLE 1
#define NV_MSGBOX_DATA_DYN_SYS_INFO_SIZE_DRIVER_VERSION 64
/* Event types */
typedef enum
{
@@ -1944,6 +2012,27 @@ typedef struct
// new param starting from here.
} NV_MSGBOX_POWER_HINT_PARAMS;
/*!
* @brief Union of all possible parameter struct. Used to determine the maximum
* amount of space parameter blocks can take.
*/
typedef union {
NV_MSGBOX_PMGR_PWR_TGP_LIMIT_CONTROL_PARAMS tgpLimitControl;
NV_MSGBOX_THERMAL_FAN_V1_COUNT_PARAMS fanCountV1Get;
NV_MSGBOX_THERMAL_FAN_V1_INFO_PARAMS fanCountV1Info;
NV_MSGBOX_THERMAL_FAN_V1_STATUS_PARAMS fanCountV1Status;
NV_MSGBOX_OVERCLOCKING_LIMIT_CONTROL_PARAMS overclockingLimitControl;
NV_MSGBOX_ENERGY_COUNTER_STATUS_PARAMS energyCounterStatus;
NV_MSGBOX_VIOLATION_COUNTERS_STATUS_PARAMS violationCountersStatus;
NV_MSGBOX_UTILIZATION_RATE_PARAMS utilizationRate;
NV_MSGBOX_OOB_CLOCK_LIMIT_CTRL_PARAMS oobClockLimitCtrlParams;
NV_MSGBOX_DEVICE_MODE_CONTROL_PARAMS deviceModeControlParams;
NV_MSGBOX_TEST_MESSAGE_SEND_PARAMS testMessageSend;
NV_MSGBOX_CLOCK_LIMIT_GET_PARAMS clockLimitGet;
NV_MSGBOX_THERMAL_FAN_V3_FAN_CURVE_POINTS_PARAMS fanCurvePointsV3;
NV_MSGBOX_POWER_HINT_PARAMS powerHintParams;
} NV_MSGBOX_ASYNC_REQ_PARAMS_UNION;
#endif // !NV_MSGBOX_NO_PARAM_STRUCTS
/* Utility command constructor macros */
@@ -2348,9 +2437,24 @@ typedef struct
DRF_DEF(_MSGBOX, _CMD, _ARG2_ECC_V5_ERR_BUF_TYPE, _ADDR) \
)
#define NV_MSGBOX_CMD_SET_COPY_DATA(cmd) \
( \
FLD_SET_DRF(_MSGBOX, _CMD, _COPY_DATA, _ON, (cmd)) \
#define NV_MSGBOX_CMD_SET_COPY_DATA(cmd) \
( \
FLD_SET_DRF(_MSGBOX, _CMD, _COPY_DATA, _ON, (cmd)) \
)
#define NV_MSGBOX_CMD_GPM_GET_METRIC(type, metric, partition) \
( \
NV_MSGBOX_CMD(_GPU_PERFORMANCE_MONITORING, 0, 0) | \
DRF_DEF(_MSGBOX, _CMD, _ARG1_GPM_ACTION, type) | \
DRF_DEF(_MSGBOX, _CMD, _ARG1_GPM_METRIC, metric) | \
DRF_DEF(_MSGBOX, _CMD, _ARG2_GPM_PARTITION, partition) \
)
#define NV_MSGBOX_CMD_GPM_SET_INTERVAL(interval) \
( \
NV_MSGBOX_CMD(_GPU_PERFORMANCE_MONITORING, 0, 0) | \
DRF_DEF(_MSGBOX, _CMD, _ARG1_GPM_ACTION, _SET_INTERVAL) | \
DRF_DEF(_MSGBOX, _CMD, _ARG1_GPM_INTERVAL, (interval)) \
)
#define NV_MSGBOX_GET_CMD_OPCODE(cmd) DRF_VAL(_MSGBOX, _CMD, _OPCODE, (cmd))

13
src/nvidia/arch/nvalloc/common/inc/rmRiscvUcode.h
View File

@@ -37,8 +37,9 @@ typedef struct {
//
// Version 1
// Version 2
// Vesrion 3 = for Partition boot
// Vesrion 4 = for eb riscv boot
// Version 3 = for Partition boot
// Version 4 = for eb riscv boot
// Version 5 = Support signing entire RISC-V image as "code" in code section for hopper and later.
//
NvU32 version; // structure version
NvU32 bootloaderOffset;
@@ -75,6 +76,14 @@ typedef struct {
//
NvU32 swbromDataOffset;
NvU32 swbromDataSize;
//
// Total size of FB carveout (image and reserved space).
//
NvU32 fbReservedSize;
//
// Indicates whether the entire RISC-V image is signed as "code" in code section.
//
NvU32 bSignedAsCode;
} RM_RISCV_UCODE_DESC;
#endif // RM_RISCV_UCODE_H

5
src/nvidia/arch/nvalloc/common/inc/rmlsfm.h
View File

@@ -488,6 +488,11 @@ typedef struct _def_acr_reserved_dmem
#define NV_FLCN_ACR_DESC_FLAGS_SIG_VERIF_DISABLE 0
#define NV_FLCN_ACR_DESC_FLAGS_SIG_VERIF_ENABLE 1
// Macro defines to be consumed by RM to get GH100 GSP Inst_in_sys FMC boot status.
#define GSP_INST_IN_SYS_COMPLETION_STATUS_OK 0x55
#define GSP_INST_IN_SYS_COMPLETION_STATUS_ERROR 0xAA
#define GSP_INST_IN_SYS_COMPLETION_STATUS_IN_PROGRESS 0x00
/*!
* Size of ACR phase in dword
*/

23
src/nvidia/arch/nvalloc/unix/include/nv.h
View File

@@ -281,6 +281,7 @@ typedef struct nv_usermap_access_params_s
NvU64 access_size;
NvU64 remap_prot_extra;
NvBool contig;
NvU32 caching;
} nv_usermap_access_params_t;
/*
@@ -298,6 +299,7 @@ typedef struct nv_alloc_mapping_context_s {
NvU64 remap_prot_extra;
NvU32 prot;
NvBool valid;
NvU32 caching;
} nv_alloc_mapping_context_t;
typedef enum
@@ -326,6 +328,9 @@ typedef struct nv_soc_irq_info_s {
#define NV_MAX_DPAUX_NUM_DEVICES 4
#define NV_MAX_SOC_DPAUX_NUM_DEVICES 2 // From SOC_DEV_MAPPING
#define NV_IGPU_LEGACY_STALL_IRQ 70
#define NV_IGPU_MAX_STALL_IRQS 3
#define NV_IGPU_MAX_NONSTALL_IRQS 1
/*
* per device state
*/
@@ -362,6 +367,7 @@ typedef struct nv_state_t
nv_aperture_t *hdacodec_regs;
nv_aperture_t *mipical_regs;
nv_aperture_t *fb, ud;
nv_aperture_t *simregs;
NvU32 num_dpaux_instance;
NvU32 interrupt_line;
@@ -374,6 +380,11 @@ typedef struct nv_state_t
NvU32 soc_dcb_size;
NvU32 disp_sw_soc_chip_id;
NvU32 igpu_stall_irq[NV_IGPU_MAX_STALL_IRQS];
NvU32 igpu_nonstall_irq;
NvU32 num_stall_irqs;
NvU64 dma_mask;
NvBool primary_vga;
NvU32 sim_env;
@@ -451,6 +462,9 @@ typedef struct nv_state_t
NvBool printed_openrm_enable_unsupported_gpus_error;
/* Check if NVPCF DSM function is implemented under NVPCF or GPU device scope */
NvBool nvpcf_dsm_in_gpu_scope;
} nv_state_t;
// These define need to be in sync with defines in system.h
@@ -515,7 +529,7 @@ typedef NV_STATUS (*nvPmaEvictRangeCallback)(void *, NvU64, NvU64);
#define NV_FLAG_USES_MSIX 0x0040
#define NV_FLAG_PASSTHRU 0x0080
#define NV_FLAG_SUSPENDED 0x0100
// Unused 0x0200
#define NV_FLAG_SOC_IGPU 0x0200
// Unused 0x0400
#define NV_FLAG_PERSISTENT_SW_STATE 0x0800
#define NV_FLAG_IN_RECOVERY 0x1000
@@ -564,6 +578,9 @@ typedef enum
#define NV_IS_SOC_DISPLAY_DEVICE(nv) \
((nv)->flags & NV_FLAG_SOC_DISPLAY)
#define NV_IS_SOC_IGPU_DEVICE(nv) \
((nv)->flags & NV_FLAG_SOC_IGPU)
#define NV_IS_DEVICE_IN_SURPRISE_REMOVAL(nv) \
(((nv)->flags & NV_FLAG_IN_SURPRISE_REMOVAL) != 0)
@@ -782,7 +799,7 @@ void NV_API_CALL nv_put_firmware(const void *);
nv_file_private_t* NV_API_CALL nv_get_file_private(NvS32, NvBool, void **);
void NV_API_CALL nv_put_file_private(void *);
NV_STATUS NV_API_CALL nv_get_device_memory_config(nv_state_t *, NvU64 *, NvU64 *, NvU32 *, NvU32 *, NvS32 *);
NV_STATUS NV_API_CALL nv_get_device_memory_config(nv_state_t *, NvU64 *, NvU64 *, NvU32 *, NvS32 *);
NV_STATUS NV_API_CALL nv_get_ibmnpu_genreg_info(nv_state_t *, NvU64 *, NvU64 *, void**);
NV_STATUS NV_API_CALL nv_get_ibmnpu_relaxed_ordering_mode(nv_state_t *nv, NvBool *mode);
@@ -961,7 +978,7 @@ void NV_API_CALL rm_acpi_notify(nvidia_stack_t *, nv_state_t *, NvU32);
NV_STATUS NV_API_CALL rm_get_clientnvpcf_power_limits(nvidia_stack_t *, nv_state_t *, NvU32 *, NvU32 *);
/* vGPU VFIO specific functions */
NV_STATUS NV_API_CALL nv_vgpu_create_request(nvidia_stack_t *, nv_state_t *, const NvU8 *, NvU32, NvU16 *, NvU32);
NV_STATUS NV_API_CALL nv_vgpu_create_request(nvidia_stack_t *, nv_state_t *, const NvU8 *, NvU32, NvU16 *, NvU32, NvBool *);
NV_STATUS NV_API_CALL nv_vgpu_delete(nvidia_stack_t *, const NvU8 *, NvU16);
NV_STATUS NV_API_CALL nv_vgpu_get_type_ids(nvidia_stack_t *, nv_state_t *, NvU32 *, NvU32 **, NvBool);
NV_STATUS NV_API_CALL nv_vgpu_get_type_info(nvidia_stack_t *, nv_state_t *, NvU32, char *, int, NvU8);

8
src/nvidia/arch/nvalloc/unix/include/os-interface.h
View File

@@ -125,6 +125,7 @@ NvU32 NV_API_CALL os_get_cpu_number (void);
void NV_API_CALL os_disable_console_access (void);
void NV_API_CALL os_enable_console_access (void);
NV_STATUS NV_API_CALL os_registry_init (void);
NvU64 NV_API_CALL os_get_max_user_va (void);
NV_STATUS NV_API_CALL os_schedule (void);
NV_STATUS NV_API_CALL os_alloc_spinlock (void **);
void NV_API_CALL os_free_spinlock (void *);
@@ -193,6 +194,13 @@ void NV_API_CALL os_nv_cap_destroy_entry (nv_cap_t *);
int NV_API_CALL os_nv_cap_validate_and_dup_fd(const nv_cap_t *, int);
void NV_API_CALL os_nv_cap_close_fd (int);
enum os_pci_req_atomics_type {
OS_INTF_PCIE_REQ_ATOMICS_32BIT,
OS_INTF_PCIE_REQ_ATOMICS_64BIT,
OS_INTF_PCIE_REQ_ATOMICS_128BIT
};
NV_STATUS NV_API_CALL os_enable_pci_req_atomics (void *, enum os_pci_req_atomics_type);
extern NvU32 os_page_size;
extern NvU64 os_page_mask;
extern NvU8 os_page_shift;

2
src/nvidia/arch/nvalloc/unix/include/osapi.h
View File

@@ -144,7 +144,7 @@ NV_STATUS rm_free_os_event (NvHandle, NvU32);
NV_STATUS rm_get_event_data (nv_file_private_t *, NvP64, NvU32 *);
void rm_client_free_os_events (NvHandle);
NV_STATUS rm_create_mmap_context (nv_state_t *, NvHandle, NvHandle, NvHandle, NvP64, NvU64, NvU64, NvU32);
NV_STATUS rm_create_mmap_context (nv_state_t *, NvHandle, NvHandle, NvHandle, NvP64, NvU64, NvU64, NvU32, NvU32);
NV_STATUS rm_update_device_mapping_info (NvHandle, NvHandle, NvHandle, void *, void *);
NV_STATUS rm_access_registry (NvHandle, NvHandle, NvU32, NvP64, NvU32, NvP64, NvU32, NvP64, NvU32 *, NvU32 *, NvU32 *);

7
src/nvidia/arch/nvalloc/unix/src/escape.c
View File

@@ -285,6 +285,7 @@ NV_STATUS RmIoctl(
if (rm_create_mmap_context(nv, pParms->hRoot,
pParms->hObjectParent, pParms->hObjectNew,
pParms->pMemory, pParms->limit + 1, 0,
NV_MEMORY_DEFAULT,
pApi->fd) != NV_OK)
{
NV_PRINTF(LEVEL_WARNING,
@@ -457,6 +458,8 @@ NV_STATUS RmIoctl(
goto done;
}
// Don't allow userspace to override the caching type
pParms->flags = FLD_SET_DRF(OS33, _FLAGS, _CACHING_TYPE, _DEFAULT, pParms->flags);
Nv04MapMemoryWithSecInfo(pParms, secInfo);
if (pParms->status == NV_OK)
@@ -464,7 +467,9 @@ NV_STATUS RmIoctl(
pParms->status = rm_create_mmap_context(nv, pParms->hClient,
pParms->hDevice, pParms->hMemory,
pParms->pLinearAddress, pParms->length,
pParms->offset, pApi->fd);
pParms->offset,
DRF_VAL(OS33, _FLAGS, _CACHING_TYPE, pParms->flags),
pApi->fd);
if (pParms->status != NV_OK)
{
NVOS34_PARAMETERS params;

3
src/nvidia/arch/nvalloc/unix/src/os-hypervisor-stubs.c
View File

@@ -75,7 +75,8 @@ NV_STATUS NV_API_CALL nv_vgpu_create_request(
const NvU8 *pMdevUuid,
NvU32 vgpuTypeId,
NvU16 *vgpuId,
NvU32 gpuPciBdf
NvU32 gpuPciBdf,
NvBool *is_driver_vm
)
{
return NV_ERR_NOT_SUPPORTED;

72
src/nvidia/arch/nvalloc/unix/src/os.c
View File

@@ -718,6 +718,11 @@ void osSpinLoop(void)
{
}
NvU64 osGetMaxUserVa(void)
{
return os_get_max_user_va();
}
NV_STATUS osSchedule(void)
{
return os_schedule();
@@ -3497,17 +3502,14 @@ osRemoveGpuSupported
* - All address values are in the System Physical Address (SPA) space
* - Targets can either be "Local" (bIsPeer=False) or for a specified "Peer"
* (bIsPeer=True, peerIndex=#) GPU
* - Granularity of the target address space is returned as a bit shift value
* (e.g. granularity=37 implies a granularity of 128GiB)
* - Target address and mask values have a specified bit width, and represent
* the higher order bits above the target address granularity
*
* @param[in] pGpu GPU object pointer
* @param[out] pAddrSysPhys Pointer to hold SPA aligned at 128GB boundary
* @param[out] pAddrSysPhys Pointer to hold SPA
* @param[out] pAddrWidth Address range width value pointer
* @param[out] pMask Mask value pointer
* @param[out] pMaskWidth Mask width value pointer
* @param[out] pGranularity Granularity value pointer
* @param[in] bIsPeer NV_TRUE if this is a peer, local GPU otherwise
* @param[in] peerIndex Peer index
*
@@ -3520,11 +3522,10 @@ NV_STATUS
osGetAtsTargetAddressRange
(
OBJGPU *pGpu,
NvU32 *pAddrSysPhys,
NvU64 *pAddrSysPhys,
NvU32 *pAddrWidth,
NvU32 *pMask,
NvU32 *pMaskWidth,
NvU32 *pGranularity,
NvBool bIsPeer,
NvU32 peerIndex
)
@@ -3548,27 +3549,21 @@ osGetAtsTargetAddressRange
if (bIsPeer)
{
const int addrWidth = 0x10;
const NvU32 guestAddrGranularity = 37;
*pAddrSysPhys = 0;
*pAddrWidth = addrWidth;
*pMask = 0;
*pMaskWidth = addrMaskWidth;
*pGranularity = guestAddrGranularity;
return NV_OK;
}
else
{
NvU64 addrSysPhys;
NV_STATUS status = nv_get_device_memory_config(nv, &addrSysPhys, NULL,
pAddrWidth, pGranularity, NULL);
NV_STATUS status = nv_get_device_memory_config(nv, pAddrSysPhys, NULL,
pAddrWidth, NULL);
if (status == NV_OK)
{
*pMask = NVBIT(*pAddrWidth) - 1U;
*pMaskWidth = addrMaskWidth;
*pAddrSysPhys = addrSysPhys >> *pGranularity;
}
return status;
}
@@ -3615,7 +3610,7 @@ osGetFbNumaInfo
nv = NV_GET_NV_STATE(pGpu);
NV_STATUS status = nv_get_device_memory_config(nv, NULL, pAddrPhys, NULL, NULL, pNodeId);
NV_STATUS status = nv_get_device_memory_config(nv, NULL, pAddrPhys, NULL, pNodeId);
return status;
#endif
@@ -3901,7 +3896,7 @@ osNumaOnliningEnabled
// Note that this numaNodeId value fetched from Linux layer might not be
// accurate since it is possible to overwrite it with regkey on some configs
//
if (nv_get_device_memory_config(pOsGpuInfo, NULL, NULL, NULL, NULL,
if (nv_get_device_memory_config(pOsGpuInfo, NULL, NULL, NULL,
&numaNodeId) != NV_OK)
{
return NV_FALSE;
@@ -4959,6 +4954,51 @@ osGetSyncpointAperture
return NV_ERR_NOT_SUPPORTED;
}
/*!
* @brief Enable PCIe AtomicOp Requester Enable and return
* the completer side capabilities that the requester can send.
*
* @param[in] pOsGpuInfo OS_GPU_INFO OS specific GPU information pointer
* @param[out] pMask mask of supported atomic size, including one or more of:
* OS_PCIE_CAP_MASK_REQ_ATOMICS_32
* OS_PCIE_CAP_MASK_REQ_ATOMICS_64
* OS_PCIE_CAP_MASK_REQ_ATOMICS_128
*
* @returns NV_STATUS, NV_OK if success
* NV_ERR_NOT_SUPPORTED if platform doesn't support this
* feature.
* NV_ERR_GENERIC for any other error
*/
NV_STATUS
osConfigurePcieReqAtomics
(
OS_GPU_INFO *pOsGpuInfo,
NvU32 *pMask
)
{
if (pMask)
{
*pMask = 0U;
if (pOsGpuInfo)
{
if (os_enable_pci_req_atomics(pOsGpuInfo->handle,
OS_INTF_PCIE_REQ_ATOMICS_32BIT) == NV_OK)
*pMask |= OS_PCIE_CAP_MASK_REQ_ATOMICS_32;
if (os_enable_pci_req_atomics(pOsGpuInfo->handle,
OS_INTF_PCIE_REQ_ATOMICS_64BIT) == NV_OK)
*pMask |= OS_PCIE_CAP_MASK_REQ_ATOMICS_64;
if (os_enable_pci_req_atomics(pOsGpuInfo->handle,
OS_INTF_PCIE_REQ_ATOMICS_128BIT) == NV_OK)
*pMask |= OS_PCIE_CAP_MASK_REQ_ATOMICS_128;
if (*pMask != 0)
return NV_OK;
}
}
return NV_ERR_NOT_SUPPORTED;
}
/*!
* @brief Check GPU is accessible or not
*

39
src/nvidia/arch/nvalloc/unix/src/osapi.c
View File

@@ -1843,6 +1843,7 @@ static NV_STATUS RmCreateMmapContextLocked(
NvP64 address,
NvU64 size,
NvU64 offset,
NvU32 cachingType,
NvU32 fd
)
{
@@ -1884,6 +1885,7 @@ static NV_STATUS RmCreateMmapContextLocked(
nvuap->addr = addr;
nvuap->size = size;
nvuap->offset = offset;
nvuap->caching = cachingType;
//
// Assume the allocation is contiguous until RmGetMmapPteArray
@@ -1975,6 +1977,7 @@ NV_STATUS rm_create_mmap_context(
NvP64 address,
NvU64 size,
NvU64 offset,
NvU32 cachingType,
NvU32 fd
)
{
@@ -1995,7 +1998,7 @@ NV_STATUS rm_create_mmap_context(
else if ((rmStatus = rmGpuLocksAcquire(GPUS_LOCK_FLAGS_NONE, RM_LOCK_MODULES_OSAPI)) == NV_OK)
{
rmStatus = RmCreateMmapContextLocked(hClient, hDevice, hMemory,
address, size, offset, fd);
address, size, offset, cachingType, fd);
// UNLOCK: release GPUs lock
rmGpuLocksRelease(GPUS_LOCK_FLAGS_NONE, NULL);
}
@@ -3364,13 +3367,29 @@ static NV_STATUS RmNonDPAuxI2CTransfer
break;
case NV_I2C_CMD_SMBUS_WRITE:
params->transData.smbusByteData.bWrite = NV_TRUE;
if (len == 2)
{
params->transData.smbusWordData.bWrite = NV_TRUE;
}
else
{
params->transData.smbusByteData.bWrite = NV_TRUE;
}
/* fall through*/
case NV_I2C_CMD_SMBUS_READ:
params->transType = NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_BYTE_RW;
params->transData.smbusByteData.message = pData[0];
params->transData.smbusByteData.registerAddress = command;
if (len == 2)
{
params->transType = NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_WORD_RW;
params->transData.smbusWordData.message = pData[0] | ((NvU16)pData[1] << 8);
params->transData.smbusWordData.registerAddress = command;
}
else
{
params->transType = NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_BYTE_RW;
params->transData.smbusByteData.message = pData[0];
params->transData.smbusByteData.registerAddress = command;
}
break;
case NV_I2C_CMD_SMBUS_BLOCK_WRITE:
@@ -3408,7 +3427,15 @@ static NV_STATUS RmNonDPAuxI2CTransfer
//
if (rmStatus == NV_OK && type == NV_I2C_CMD_SMBUS_READ)
{
pData[0] = params->transData.smbusByteData.message;
if (len == 2)
{
pData[0] = (params->transData.smbusWordData.message & 0xff);
pData[1] = params->transData.smbusWordData.message >> 8;
}
else
{
pData[0] = params->transData.smbusByteData.message;
}
}
portMemFree(params);

38
src/nvidia/arch/nvalloc/unix/src/osinit.c
View File

@@ -58,6 +58,7 @@
#include <nvSha256.h>
#include <gpu/gsp/kernel_gsp.h>
#include <logdecode.h>
#include <gpu/fsp/kern_fsp.h>
#include <mem_mgr/virt_mem_mgr.h>
@@ -637,6 +638,15 @@ osInitNvMapping(
sysApplyLockingPolicy(pSys);
pGpu->busInfo.IntLine = nv->interrupt_line;
//
// Set the DMA address size as soon as we have the HAL to call to
// determine the precise number of physical address bits supported
// by the architecture. DMA allocations should not be made before
// this point.
//
nv_set_dma_address_size(nv, gpuGetPhysAddrWidth_HAL(pGpu, ADDR_SYSMEM));
pGpu->dmaStartAddress = (RmPhysAddr)nv_get_dma_start_address(nv);
if (nv->fb != NULL)
{
@@ -725,15 +735,6 @@ osTeardownScalability(
return clTeardownPcie(pGpu, pCl);
}
static inline void
RmSetDeviceDmaAddressSize(
nv_state_t *nv,
NvU8 numDmaAddressBits
)
{
nv_set_dma_address_size(nv, numDmaAddressBits);
}
static void
populateDeviceAttributes(
OBJGPU *pGpu,
@@ -883,8 +884,6 @@ RmInitNvDevice(
return;
}
RmSetDeviceDmaAddressSize(nv, gpuGetPhysAddrWidth_HAL(pGpu, ADDR_SYSMEM));
os_disable_console_access();
status->rmStatus = gpumgrStateInitGpu(pGpu);
@@ -1188,7 +1187,7 @@ NvBool RmInitPrivateState(
// Set up a reasonable default DMA address size, based on the minimum
// possible on currently supported GPUs.
//
RmSetDeviceDmaAddressSize(pNv, NV_GPU_MIN_SUPPORTED_DMA_ADDR_WIDTH);
nv_set_dma_address_size(pNv, NV_GPU_MIN_SUPPORTED_DMA_ADDR_WIDTH);
os_mem_set(nvp, 0, sizeof(*nvp));
nvp->status = NV_ERR_INVALID_STATE;
@@ -1582,7 +1581,7 @@ NvBool RmInitAdapter(
//
if (nv->request_firmware)
{
RmSetDeviceDmaAddressSize(nv, NV_GSP_GPU_MIN_SUPPORTED_DMA_ADDR_WIDTH);
nv_set_dma_address_size(nv, NV_GSP_GPU_MIN_SUPPORTED_DMA_ADDR_WIDTH);
gspFwHandle = nv_get_firmware(nv, NV_FIRMWARE_GSP,
&gspFw.pBuf,
@@ -1655,6 +1654,17 @@ NvBool RmInitAdapter(
goto shutdown;
}
KernelFsp *pKernelFsp = GPU_GET_KERNEL_FSP(pGpu);
if ((pKernelFsp != NULL) && !IS_GSP_CLIENT(pGpu) && !IS_VIRTUAL(pGpu))
{
status.rmStatus = kfspSendBootCommands_HAL(pGpu, pKernelFsp);
if (status.rmStatus != NV_OK)
{
NV_PRINTF(LEVEL_ERROR, "FSP boot command failed.\n");
goto shutdown;
}
}
RmSetConsolePreservationParams(pGpu);
//
@@ -1830,7 +1840,7 @@ NvBool RmInitAdapter(
RmInitS0ixPowerManagement(nv);
RmInitDeferredDynamicPowerManagement(nv);
if (!NV_IS_SOC_DISPLAY_DEVICE(nv))
if (!NV_IS_SOC_DISPLAY_DEVICE(nv) && !NV_IS_SOC_IGPU_DEVICE(nv))
{
status.rmStatus = RmRegisterGpudb(pGpu);
if (status.rmStatus != NV_OK)

24
src/nvidia/arch/nvalloc/unix/src/osnvlink.c
View File

@@ -534,6 +534,27 @@ static void NV_API_CALL rm_nvlink_ops_training_complete
NV_EXIT_RM_RUNTIME(sp, fp);
}
static NvlStatus NV_API_CALL rm_nvlink_ops_ali_training
(
struct nvlink_link *link
)
{
void *fp;
NvlStatus status;
THREAD_STATE_NODE threadState = {0};
KNVLINK_RM_LINK * pLink = link->link_info;
nvidia_stack_t * sp = (nvidia_stack_t *)pLink->pOsInfo;
NV_ENTER_RM_RUNTIME(sp, fp);
threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE);
status = knvlinkCoreAliTrainingCallback(link);
threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE);
NV_EXIT_RM_RUNTIME(sp, fp);
return status;
}
#endif /* defined(INCLUDE_NVLINK_LIB) */
const struct nvlink_link_handlers* osGetNvlinkLinkCallbacks(void)
@@ -560,6 +581,7 @@ const struct nvlink_link_handlers* osGetNvlinkLinkCallbacks(void)
.read_discovery_token = rm_nvlink_ops_read_link_discovery_token,
.training_complete = rm_nvlink_ops_training_complete,
.get_uphy_load = rm_nvlink_get_uphy_load,
.ali_training = rm_nvlink_ops_ali_training,
};
return &rm_nvlink_link_ops;
@@ -647,7 +669,7 @@ osGetPlatformNvlinkLinerate
)
{
#if defined(NVCPU_PPC64LE)
nv_state_t *nv = NV_GET_NV_STATE(pGpu);
nv_state_t *nv = NV_GET_NV_STATE(pGpu);
KernelNvlink *pKernelNvlink = GPU_GET_KERNEL_NVLINK(pGpu);
if (!pKernelNvlink)

5
src/nvidia/arch/nvalloc/unix/src/rm-gpu-ops.c
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2020-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -396,12 +396,13 @@ NV_STATUS NV_API_CALL rm_gpu_ops_dup_allocation(nvidia_stack_t *sp,
gpuAddressSpaceHandle srcVaSpace,
NvU64 srcAddress,
gpuAddressSpaceHandle dstVaSpace,
NvU64 dstVaAlignment,
NvU64 *dstAddress)
{
NV_STATUS rmStatus;
void *fp;
NV_ENTER_RM_RUNTIME(sp,fp);
rmStatus = nvGpuOpsDupAllocation(srcVaSpace, srcAddress, dstVaSpace, dstAddress);
rmStatus = nvGpuOpsDupAllocation(srcVaSpace, srcAddress, dstVaSpace, dstVaAlignment, dstAddress);
NV_EXIT_RM_RUNTIME(sp,fp);
return rmStatus;
}

1
src/nvidia/arch/nvalloc/unix/src/unix_intr.c
View File

@@ -339,6 +339,7 @@ void osEnableInterrupts(OBJGPU *pGpu)
intrRestoreNonStall_HAL(pGpu, pIntr, intrGetIntrEn(pIntr), NULL);
}
}
}
}