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This commit is contained in:
Andy Ritger
2022-10-10 14:59:24 -07:00
parent fe0728787f
commit 90eb10774f
758 changed files with 88383 additions and 26493 deletions
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6
src/nvidia/arch/nvalloc/common/inc/flcnretval.h
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@@ -130,6 +130,7 @@ typedef NvU8 FLCN_STATUS;
// because that will affect other binaries and their signatures
//
#define FLCN_ERR_CTXSW_ERROR (0x4EU)
#define FLCN_ERR_SE_SNPKA_HW_CRYPTO_OPERATION_FAILED (0x4FU)
// VPR SEC2 task errors
#define FLCN_ERR_VPR_APP_INVALID_REQUEST_END_ADDR (0x51U)
@@ -232,6 +233,8 @@ typedef NvU8 FLCN_STATUS;
#define FLCN_ERR_HS_APM_FECS_NOT_HALTED (0xCEU)
#define FLCN_ERR_HS_APM_SCRATCH_PLM_INVALID (0xCFU)
#define FLCN_ERR_HS_APM_SCRATCH_INIT_INVALID (0xD0U)
#define FLCN_ERR_HS_INVALID_KEY (0xD1U)
#define FLCN_ERR_HS_SWKG_INVALID_SIGNATURE (0xD2U)
//
@@ -283,4 +286,7 @@ typedef NvU8 FLCN_STATUS;
#define FLCN_ERR_AUTH_GSP_RM_HANDOFF_FAILED (0xF8U)
#define FLCN_ERR_INVALID_WPRMETA_MAGIC_OR_REVISION (0xF9U)
// Arithmetic errors
#define FLCN_ERR_ARITHMETIC_OVERFLOW (0xFAU)
#endif // FLCNRETVAL_H

44
src/nvidia/arch/nvalloc/common/inc/fsp/nvdm_payload_cmd_response.h Normal file
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@@ -0,0 +1,44 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
/*
* @file nvdm_payload_cmd_response.h
* @brief Header file containing the definition for the
* NVDM_PAYLOAD_COMMAND_RESPONSE structure, which
* is required for SMBPBI-specific payloads and needs
* to be visible by bothe the PMU and the driver sides.
*/
#ifndef _NVDM_PAYLOAD_CMD_RESPONSE_H
#define _NVDM_PAYLOAD_CMD_RESPONSE_H
#pragma pack(1)
typedef struct
{
NvU32 taskId;
NvU32 commandNvdmType;
NvU32 errorCode;
} NVDM_PAYLOAD_COMMAND_RESPONSE;
#pragma pack()
#endif // _NVDM_PAYLOAD_CMD_RESPONSE_H

94
src/nvidia/arch/nvalloc/common/inc/gsp/gspifpub.h Normal file
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@@ -0,0 +1,94 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef GSPIFPUB_H
#define GSPIFPUB_H
#include <nvtypes.h>
/*!
* @file gspifpub.h
* @brief GSP Command/Message Interfaces - Published
*/
/*!
* Target physical memory apertures supported for DMA
*/
typedef enum {
GSP_DMA_TARGET_LOCAL_FB,
GSP_DMA_TARGET_COHERENT_SYSTEM,
GSP_DMA_TARGET_NONCOHERENT_SYSTEM,
GSP_DMA_TARGET_COUNT
} GSP_DMA_TARGET;
/*!
* @brief GSP-CC Microcode Initialization Parameters
*/
typedef struct GSP_CC_INIT_PARAMS
{
// CC initialization "registry keys"
NvU32 regkeys;
} GSP_CC_INIT_PARAMS;
/*!
* @brief GSP-ACR BOOT_GSP_RM Command Parameters
*
* The wprCarveout fields have no effect in environments where the WPR can be allocated
* implicitly by ACR.
*/
typedef struct GSP_ACR_BOOT_GSP_RM_PARAMS
{
// Physical memory aperture through which gspRmDescPa is accessed
GSP_DMA_TARGET target;
// Size in bytes of the GSP-RM descriptor structure
NvU32 gspRmDescSize;
// Physical offset in the target aperture of the GSP-RM descriptor structure
NvU64 gspRmDescOffset;
// Physical offset in FB to set the start of the WPR containing GSP-RM
NvU64 wprCarveoutOffset;
// Size in bytes of the WPR containing GSP-RM
NvU32 wprCarveoutSize;
} GSP_ACR_BOOT_GSP_RM_PARAMS;
/*!
* @brief GSP-RM Parameters
*/
typedef struct GSP_RM_PARAMS
{
// Physical memory aperture through which bootArgsPa is accessed
GSP_DMA_TARGET target;
// Physical address that will be stuffed in NV_PGSP_FALCON_MAILBOX(0|1)
NvU64 bootArgsOffset;
} GSP_RM_PARAMS;
/*!
* @brief GSP-CC Microcode Parameters for Boot Partitions
*/
typedef struct GSP_CC_BOOT_PARAMS
{
GSP_CC_INIT_PARAMS initParams;
GSP_ACR_BOOT_GSP_RM_PARAMS bootGspRmParams;
GSP_RM_PARAMS gspRmParams;
} GSP_CC_BOOT_PARAMS;
#endif // GSPIFPUB_H

10
src/nvidia/arch/nvalloc/common/inc/nvcst.h
View File

@@ -61,6 +61,7 @@ CHIPSET_SETUP_FUNC(Intel_A2D2_setupFunc)
CHIPSET_SETUP_FUNC(Intel_A2C9_setupFunc)
CHIPSET_SETUP_FUNC(Intel_A301_setupFunc)
CHIPSET_SETUP_FUNC(Intel_0685_setupFunc)
CHIPSET_SETUP_FUNC(Intel_IceLake_setupFunc)
CHIPSET_SETUP_FUNC(Intel_4381_setupFunc)
CHIPSET_SETUP_FUNC(Intel_7A82_setupFunc)
CHIPSET_SETUP_FUNC(Intel_7A04_setupFunc)
@@ -177,13 +178,13 @@ CSINFO chipsetInfo[] =
{PCI_VENDOR_ID_INTEL, 0xA30D, CS_INTEL_A2C9, "IntelH370", Intel_A2C9_setupFunc},
{PCI_VENDOR_ID_INTEL, 0xA301, CS_INTEL_A301, "Intel-CannonLake", Intel_A301_setupFunc},
{PCI_VENDOR_ID_INTEL, 0x0685, CS_INTEL_0685, "Intel-CometLake", Intel_0685_setupFunc},
{PCI_VENDOR_ID_INTEL, 0xA1CB, CS_INTEL_C620, "Intel-IceLake", NULL},
{PCI_VENDOR_ID_INTEL, 0xA1CB, CS_INTEL_C620, "Intel-IceLake", Intel_IceLake_setupFunc},
{PCI_VENDOR_ID_INTEL, 0x4381, CS_INTEL_4381, "Intel-RocketLake", Intel_4381_setupFunc},
{PCI_VENDOR_ID_INTEL, 0x4385, CS_INTEL_4381, "Intel-RocketLake", Intel_4381_setupFunc},
{PCI_VENDOR_ID_INTEL, 0x7A82, CS_INTEL_7A82, "Intel-AlderLake", Intel_7A82_setupFunc},
{PCI_VENDOR_ID_INTEL, 0x7A84, CS_INTEL_7A82, "Intel-AlderLake", Intel_7A82_setupFunc},
{PCI_VENDOR_ID_INTEL, 0x1B81, CS_INTEL_1B81, "Intel-SapphireRapids", NULL},
{PCI_VENDOR_ID_INTEL, 0x18DC, CS_INTEL_18DC, "Intel-IceLake", NULL},
{PCI_VENDOR_ID_INTEL, 0x18DC, CS_INTEL_18DC, "Intel-IceLake", Intel_IceLake_setupFunc},
{PCI_VENDOR_ID_INTEL, 0x7A04, CS_INTEL_7A04, "Intel-RaptorLake", Intel_7A04_setupFunc},
{PCI_VENDOR_ID_NVIDIA, 0x0FAE, CS_NVIDIA_T210, "T210", Nvidia_T210_setupFunc},
@@ -196,7 +197,8 @@ CSINFO chipsetInfo[] =
{PCI_VENDOR_ID_NVIDIA, 0x229A, CS_NVIDIA_T234, "T234", Nvidia_T194_setupFunc},
{PCI_VENDOR_ID_NVIDIA, 0x229C, CS_NVIDIA_T234, "T234", Nvidia_T194_setupFunc},
{PCI_VENDOR_ID_NVIDIA, 0x229E, CS_NVIDIA_T234, "T234", Nvidia_T194_setupFunc},
{PCI_VENDOR_ID_NVIDIA, 0x22C2, CS_NVIDIA_T23x, "T23x", Nvidia_T194_setupFunc},
{PCI_VENDOR_ID_NVIDIA, 0x22C3, CS_NVIDIA_T23x, "T23x", Nvidia_T194_setupFunc},
{PCI_VENDOR_ID_SIS, 0x0649, CS_SIS_649, "649", SiS_656_setupFunc},
{PCI_VENDOR_ID_SIS, 0x0656, CS_SIS_656, "656", SiS_656_setupFunc},
@@ -313,6 +315,8 @@ ARMCSALLOWLISTINFO armChipsetAllowListInfo[] =
{PCI_VENDOR_ID_NVIDIA, 0x229A, CS_NVIDIA_T234}, // NVIDIA Tegra Orin RP0
{PCI_VENDOR_ID_NVIDIA, 0x229C, CS_NVIDIA_T234}, // NVIDIA Tegra Orin RP1
{PCI_VENDOR_ID_NVIDIA, 0x229E, CS_NVIDIA_T234}, // NVIDIA Tegra Orin RP2
{PCI_VENDOR_ID_NVIDIA, 0x22C2, CS_NVIDIA_T23x}, // NVIDIA Tegra RP0
{PCI_VENDOR_ID_NVIDIA, 0x22C3, CS_NVIDIA_T23x}, // NVIDIA Tegra RP1
{PCI_VENDOR_ID_APM, 0xe004, CS_APM_STORM}, // Applied Micro X-Gene "Storm"
{PCI_VENDOR_ID_MARVELL, 0xAF00, CS_MARVELL_THUNDERX2}, // Marvell ThunderX2

1
src/nvidia/arch/nvalloc/common/inc/nvdevid.h
View File

@@ -625,6 +625,7 @@ enum {
, CS_NVIDIA_T186
, CS_NVIDIA_T194
, CS_NVIDIA_T234
, CS_NVIDIA_T23x
, CS_MARVELL_THUNDERX2
, CS_REDHAT_QEMU
, CS_AMPERE_EMAG

118
src/nvidia/arch/nvalloc/common/inc/oob/smbpbi.h
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@@ -96,6 +96,8 @@
#define NV_MSGBOX_CMD_OPCODE_RESERVED_0 0x00000024
#define NV_MSGBOX_CMD_OPCODE_RESERVED_1 0x00000025
#define NV_MSGBOX_CMD_OPCODE_GET_POWER_HINT_INFO 0x00000026
#define NV_MSGBOX_CMD_OPCODE_DYNAMIC_SYSTEM_INFORMATION 0x00000027
#define NV_MSGBOX_CMD_OPCODE_GPU_PERFORMANCE_MONITORING 0x00000028
#define NV_MSGBOX_CMD_ARG1 15:8
#define NV_MSGBOX_CMD_ARG1_NULL 0x00000000
@@ -105,7 +107,8 @@
#define NV_MSGBOX_CMD_ARG1_TEMP_BOARD 0x00000004
#define NV_MSGBOX_CMD_ARG1_TEMP_MEMORY 0x00000005
#define NV_MSGBOX_CMD_ARG1_TEMP_PWR_SUPPLY 0x00000006
#define NV_MSGBOX_CMD_ARG1_TEMP_NUM_SENSORS 7
#define NV_MSGBOX_CMD_ARG1_TEMP_T_LIMIT 0x00000007
#define NV_MSGBOX_CMD_ARG1_TEMP_NUM_SENSORS 8
#define NV_MSGBOX_CMD_ARG1_POWER_TOTAL 0x00000000
#define NV_MSGBOX_CMD_ARG1_SMBPBI_POWER 0x00000001
/* SysId info type encodings for opcode NV_MSGBOX_CMD_OPCODE_GET_SYS_ID_DATA (0x05) */
@@ -318,6 +321,33 @@
#define NV_MSGBOX_CMD_ARG1_GET_POWER_HINT_INFO_NUM \
(NV_MSGBOX_CMD_ARG1_GET_POWER_HINT_INFO_PROFILES + 1)
// Arg1 for _GPU_PERFORMANCE_MONITORING
#define NV_MSGBOX_CMD_ARG1_GPM_ACTION 15:14
#define NV_MSGBOX_CMD_ARG1_GPM_ACTION_GET_INSTANTANEOUS_METRIC 0x00000000
#define NV_MSGBOX_CMD_ARG1_GPM_ACTION_GET_SNAPSHOT_METRIC 0x00000001
#define NV_MSGBOX_CMD_ARG1_GPM_ACTION_CAPTURE_SNAPSHOT 0x00000002
#define NV_MSGBOX_CMD_ARG1_GPM_ACTION_SET_MULTIPLIER 0x00000003
#define NV_MSGBOX_CMD_ARG1_GPM_METRIC 13:8
#define NV_MSGBOX_CMD_ARG1_GPM_METRIC_GRAPHICS_ENGINE 0x00000000
#define NV_MSGBOX_CMD_ARG1_GPM_METRIC_SM_ACTIVITY 0x00000001
#define NV_MSGBOX_CMD_ARG1_GPM_METRIC_SM_OCCUPANCY 0x00000002
#define NV_MSGBOX_CMD_ARG1_GPM_METRIC_TENSOR_CORE_ACTIVITY 0x00000003
#define NV_MSGBOX_CMD_ARG1_GPM_METRIC_DRAM_USAGE 0x00000004
#define NV_MSGBOX_CMD_ARG1_GPM_METRIC_FP64_ACTIVITY 0x00000005
#define NV_MSGBOX_CMD_ARG1_GPM_METRIC_FP32_ACTIVITY 0x00000006
#define NV_MSGBOX_CMD_ARG1_GPM_METRIC_FP16_ACTIVITY 0x00000007
#define NV_MSGBOX_CMD_ARG1_GPM_METRIC_PCIE_TX_BANDWIDTH 0x00000008
#define NV_MSGBOX_CMD_ARG1_GPM_METRIC_PCIE_RX_BANDWIDTH 0x00000009
#define NV_MSGBOX_CMD_ARG1_GPM_METRIC_NVLINK_RAW_TX_BANDWIDTH 0x0000000A
#define NV_MSGBOX_CMD_ARG1_GPM_METRIC_NVLINK_DATA_TX_BANDWIDTH 0x0000000B
#define NV_MSGBOX_CMD_ARG1_GPM_METRIC_NVLINK_RAW_RX_BANDWIDTH 0x0000000C
#define NV_MSGBOX_CMD_ARG1_GPM_METRIC_NVLINK_DATA_RX_BANDWIDTH 0x0000000D
#define NV_MSGBOX_CMD_ARG1_GPM_METRIC_NVDEC_UTILIZATION 0x0000000E
#define NV_MSGBOX_CMD_ARG1_GPM_METRIC_NVJPG_UTILIZATION 0x0000000F
#define NV_MSGBOX_CMD_ARG1_GPM_METRIC_NVOFA_UTILIZATION 0x00000010
#define NV_MSGBOX_CMD_ARG1_DYN_SYS_INFO_DRIVER_VERSION_V1 0x00000000
#define NV_MSGBOX_CMD_ARG2 23:16
#define NV_MSGBOX_CMD_ARG2_NULL 0x00000000
@@ -409,6 +439,17 @@
#define NV_MSGBOX_CMD_ARG2_GET_POWER_HINT_INFO_PROFILES_TOTAL_PAGES \
(NV_MSGBOX_CMD_ARG2_GET_POWER_HINT_INFO_PROFILES_PAGE_3 + 1)
// Arg2 for _GPU_PERFORMANCE_MONITORING
#define NV_MSGBOX_CMD_ARG2_GPM_PARTITION 23:16
#define NV_MSGBOX_CMD_ARG2_GPM_PARTITION_AGGREGATE 0x000000FF
#define NV_MSGBOX_CMD_ARG2_GPM_MULTIPLIER 23:16
#define NV_MSGBOX_CMD_ARG2_GPM_MULTIPLIER_1X 0x00000001
#define NV_MSGBOX_CMD_ARG2_GPM_MULTIPLIER_2X 0x00000002
#define NV_MSGBOX_CMD_ARG2_GPM_MULTIPLIER_5X 0x00000005
#define NV_MSGBOX_CMD_ARG2_GPM_MULTIPLIER_10X 0x0000000A
#define NV_MSGBOX_CMD_ARG2_GPM_MULTIPLIER_100X 0x00000064
#define NV_MSGBOX_CMD_STATUS 28:24
#define NV_MSGBOX_CMD_STATUS_NULL 0x00000000
@@ -502,6 +543,22 @@
*/
#define NV_MSGBOX_CMD_NVLINK_INFO_GET_NVLINK_INFO_AVAILABILTY_PAGE_0 0x00000000
/**
* This field is populated as response to the following metrics:
* - NV_MSGBOX_CMD_ARG1_GPM_METRIC_DRAM_USAGE
* - NV_MSGBOX_CMD_ARG1_GPM_METRIC_PCIE_TX_BANDWIDTH
* - NV_MSGBOX_CMD_ARG1_GPM_METRIC_PCIE_RX_BANDWIDTH
* - NV_MSGBOX_CMD_ARG1_GPM_METRIC_NVLINK_RAW_TX_BANDWIDTH
* - NV_MSGBOX_CMD_ARG1_GPM_METRIC_NVLINK_DATA_TX_BANDWIDTH
* - NV_MSGBOX_CMD_ARG1_GPM_METRIC_NVLINK_RAW_RX_BANDWIDTH
* - NV_MSGBOX_CMD_ARG1_GPM_METRIC_NVLINK_DATA_RX_BANDWIDTH
*/
#define NV_MSGBOX_CMD_GPM_DATA_GRANULARITY 2:0
#define NV_MSGBOX_CMD_GPM_DATA_GRANULARITY_B 0x00000000
#define NV_MSGBOX_CMD_GPM_DATA_GRANULARITY_KIB 0x00000001
#define NV_MSGBOX_CMD_GPM_DATA_GRANULARITY_MIB 0x00000002
#define NV_MSGBOX_CMD_GPM_DATA_GRANULARITY_GIB 0x00000003
/* MSGBOX data, capability dword structure */
#define NV_MSGBOX_DATA_REG 31:0
@@ -526,6 +583,9 @@
#define NV_MSGBOX_DATA_CAP_0_TEMP_PWR_SUPPLY 6:6
#define NV_MSGBOX_DATA_CAP_0_TEMP_PWR_SUPPLY_NOT_AVAILABLE 0x00000000
#define NV_MSGBOX_DATA_CAP_0_TEMP_PWR_SUPPLY_AVAILABLE 0x00000001
#define NV_MSGBOX_DATA_CAP_0_TEMP_T_LIMIT 7:7
#define NV_MSGBOX_DATA_CAP_0_TEMP_T_LIMIT_NOT_AVAILABLE 0x00000000
#define NV_MSGBOX_DATA_CAP_0_TEMP_T_LIMIT_AVAILABLE 0x00000001
#define NV_MSGBOX_DATA_CAP_0_EXT_TEMP_BITS 11:8
#define NV_MSGBOX_DATA_CAP_0_EXT_TEMP_BITS_ZERO 0x00000000
#define NV_MSGBOX_DATA_CAP_0_EXT_TEMP_BITS_ADT7473 0x00000002
@@ -759,9 +819,15 @@
#define NV_MSGBOX_DATA_CAP_4_FAN_CURVE_POINTS_GET_SET 11:11
#define NV_MSGBOX_DATA_CAP_4_FAN_CURVE_POINTS_GET_SET_NOT_AVAILABLE 0x00000000
#define NV_MSGBOX_DATA_CAP_4_FAN_CURVE_POINTS_GET_SET_AVAILABLE 0x00000001
#define NV_MSGBOX_DATA_CAP_4_POWER_HINT 22:22
#define NV_MSGBOX_DATA_CAP_4_POWER_HINT_NOT_AVAILABLE 0x00000000
#define NV_MSGBOX_DATA_CAP_4_POWER_HINT_AVAILABLE 0x00000001
#define NV_MSGBOX_DATA_CAP_4_POWER_HINT 22:22
#define NV_MSGBOX_DATA_CAP_4_POWER_HINT_NOT_AVAILABLE 0x00000000
#define NV_MSGBOX_DATA_CAP_4_POWER_HINT_AVAILABLE 0x00000001
#define NV_MSGBOX_DATA_CAP_4_DRIVER_VERSION_V1 23:23
#define NV_MSGBOX_DATA_CAP_4_DRIVER_VERSION_V1_NOT_AVAILABLE 0x00000000
#define NV_MSGBOX_DATA_CAP_4_DRIVER_VERSION_V1_AVAILABLE 0x00000001
#define NV_MSGBOX_DATA_CAP_4_GPU_PERFORMANCE_MONITORING 24:24
#define NV_MSGBOX_DATA_CAP_4_GPU_PERFORMANCE_MONITORING_NOT_AVAILABLE 0x00000000
#define NV_MSGBOX_DATA_CAP_4_GPU_PERFORMANCE_MONITORING_AVAILABLE 0x00000001
/* ECC counters */
#define NV_MSGBOX_DATA_ECC_CNT_16BIT_DBE 31:16
@@ -1194,6 +1260,8 @@
#define NV_MSGBOX_DATA_POWER_HINT_INFO_PROFILES_PAGE_0_CUSTOMER_CUSTOM_7_NOT_AVAILABLE 0
#define NV_MSGBOX_DATA_POWER_HINT_INFO_PROFILES_PAGE_0_CUSTOMER_CUSTOM_7_AVAILABLE 1
#define NV_MSGBOX_DATA_DYN_SYS_INFO_SIZE_DRIVER_VERSION 64
/* Event types */
typedef enum
{
@@ -1944,6 +2012,27 @@ typedef struct
// new param starting from here.
} NV_MSGBOX_POWER_HINT_PARAMS;
/*!
* @brief Union of all possible parameter struct. Used to determine the maximum
* amount of space parameter blocks can take.
*/
typedef union {
NV_MSGBOX_PMGR_PWR_TGP_LIMIT_CONTROL_PARAMS tgpLimitControl;
NV_MSGBOX_THERMAL_FAN_V1_COUNT_PARAMS fanCountV1Get;
NV_MSGBOX_THERMAL_FAN_V1_INFO_PARAMS fanCountV1Info;
NV_MSGBOX_THERMAL_FAN_V1_STATUS_PARAMS fanCountV1Status;
NV_MSGBOX_OVERCLOCKING_LIMIT_CONTROL_PARAMS overclockingLimitControl;
NV_MSGBOX_ENERGY_COUNTER_STATUS_PARAMS energyCounterStatus;
NV_MSGBOX_VIOLATION_COUNTERS_STATUS_PARAMS violationCountersStatus;
NV_MSGBOX_UTILIZATION_RATE_PARAMS utilizationRate;
NV_MSGBOX_OOB_CLOCK_LIMIT_CTRL_PARAMS oobClockLimitCtrlParams;
NV_MSGBOX_DEVICE_MODE_CONTROL_PARAMS deviceModeControlParams;
NV_MSGBOX_TEST_MESSAGE_SEND_PARAMS testMessageSend;
NV_MSGBOX_CLOCK_LIMIT_GET_PARAMS clockLimitGet;
NV_MSGBOX_THERMAL_FAN_V3_FAN_CURVE_POINTS_PARAMS fanCurvePointsV3;
NV_MSGBOX_POWER_HINT_PARAMS powerHintParams;
} NV_MSGBOX_ASYNC_REQ_PARAMS_UNION;
#endif // !NV_MSGBOX_NO_PARAM_STRUCTS
/* Utility command constructor macros */
@@ -2348,9 +2437,24 @@ typedef struct
DRF_DEF(_MSGBOX, _CMD, _ARG2_ECC_V5_ERR_BUF_TYPE, _ADDR) \
)
#define NV_MSGBOX_CMD_SET_COPY_DATA(cmd) \
( \
FLD_SET_DRF(_MSGBOX, _CMD, _COPY_DATA, _ON, (cmd)) \
#define NV_MSGBOX_CMD_SET_COPY_DATA(cmd) \
( \
FLD_SET_DRF(_MSGBOX, _CMD, _COPY_DATA, _ON, (cmd)) \
)
#define NV_MSGBOX_CMD_GPM_GET_METRIC(type, metric, partition) \
( \
NV_MSGBOX_CMD(_GPU_PERFORMANCE_MONITORING, 0, 0) | \
DRF_DEF(_MSGBOX, _CMD, _ARG1_GPM_ACTION, type) | \
DRF_DEF(_MSGBOX, _CMD, _ARG1_GPM_METRIC, metric) | \
DRF_DEF(_MSGBOX, _CMD, _ARG2_GPM_PARTITION, partition) \
)
#define NV_MSGBOX_CMD_GPM_SET_INTERVAL(interval) \
( \
NV_MSGBOX_CMD(_GPU_PERFORMANCE_MONITORING, 0, 0) | \
DRF_DEF(_MSGBOX, _CMD, _ARG1_GPM_ACTION, _SET_INTERVAL) | \
DRF_DEF(_MSGBOX, _CMD, _ARG1_GPM_INTERVAL, (interval)) \
)
#define NV_MSGBOX_GET_CMD_OPCODE(cmd) DRF_VAL(_MSGBOX, _CMD, _OPCODE, (cmd))

13
src/nvidia/arch/nvalloc/common/inc/rmRiscvUcode.h
View File

@@ -37,8 +37,9 @@ typedef struct {
//
// Version 1
// Version 2
// Vesrion 3 = for Partition boot
// Vesrion 4 = for eb riscv boot
// Version 3 = for Partition boot
// Version 4 = for eb riscv boot
// Version 5 = Support signing entire RISC-V image as "code" in code section for hopper and later.
//
NvU32 version; // structure version
NvU32 bootloaderOffset;
@@ -75,6 +76,14 @@ typedef struct {
//
NvU32 swbromDataOffset;
NvU32 swbromDataSize;
//
// Total size of FB carveout (image and reserved space).
//
NvU32 fbReservedSize;
//
// Indicates whether the entire RISC-V image is signed as "code" in code section.
//
NvU32 bSignedAsCode;
} RM_RISCV_UCODE_DESC;
#endif // RM_RISCV_UCODE_H

5
src/nvidia/arch/nvalloc/common/inc/rmlsfm.h
View File

@@ -488,6 +488,11 @@ typedef struct _def_acr_reserved_dmem
#define NV_FLCN_ACR_DESC_FLAGS_SIG_VERIF_DISABLE 0
#define NV_FLCN_ACR_DESC_FLAGS_SIG_VERIF_ENABLE 1
// Macro defines to be consumed by RM to get GH100 GSP Inst_in_sys FMC boot status.
#define GSP_INST_IN_SYS_COMPLETION_STATUS_OK 0x55
#define GSP_INST_IN_SYS_COMPLETION_STATUS_ERROR 0xAA
#define GSP_INST_IN_SYS_COMPLETION_STATUS_IN_PROGRESS 0x00
/*!
* Size of ACR phase in dword
*/