520.61.05

This commit is contained in:
Andy Ritger
2022-10-10 14:59:24 -07:00
parent fe0728787f
commit 90eb10774f
758 changed files with 88383 additions and 26493 deletions

View File

@@ -707,3 +707,295 @@ gpuGetClassDescriptorList_GA107(POBJGPU pGpu, NvU32 *pNumClasses)
}
const CLASSDESCRIPTOR *
gpuGetClassDescriptorList_AD102(POBJGPU pGpu, NvU32 *pNumClasses)
{
static const CLASSDESCRIPTOR halAD102ClassDescriptorList[] = {
{ ACCESS_COUNTER_NOTIFY_BUFFER, ENG_GR(0) },
{ ADA_A, ENG_GR(0) },
{ ADA_COMPUTE_A, ENG_GR(0) },
{ AMPERE_CHANNEL_GPFIFO_A, ENG_KERNEL_FIFO },
{ AMPERE_DMA_COPY_B, ENG_CE(0) },
{ AMPERE_DMA_COPY_B, ENG_CE(1) },
{ AMPERE_DMA_COPY_B, ENG_CE(2) },
{ AMPERE_DMA_COPY_B, ENG_CE(3) },
{ AMPERE_DMA_COPY_B, ENG_CE(4) },
{ AMPERE_USERMODE_A, ENG_GPU },
{ FERMI_CONTEXT_SHARE_A, ENG_KERNEL_FIFO },
{ FERMI_TWOD_A, ENG_GR(0) },
{ FERMI_VASPACE_A, ENG_DMA },
{ G84_PERFBUFFER, ENG_BUS },
{ GF100_DISP_SW, ENG_SW },
{ GF100_HDACODEC, ENG_HDACODEC },
{ GF100_SUBDEVICE_MASTER, ENG_GPU },
{ GF100_TIMED_SEMAPHORE_SW, ENG_SW },
{ GF100_ZBC_CLEAR, ENG_KERNEL_MEMORY_SYSTEM },
{ GP100_UVM_SW, ENG_SW },
{ KEPLER_CHANNEL_GROUP_A, ENG_KERNEL_FIFO },
{ KEPLER_INLINE_TO_MEMORY_B, ENG_GR(0) },
{ MMU_FAULT_BUFFER, ENG_GR(0) },
{ NV0060_SYNC_GPU_BOOST, ENG_GPU },
{ NV01_MEMORY_VIRTUAL, ENG_DMA },
{ NV04_DISPLAY_COMMON, ENG_KERNEL_DISPLAY },
{ NV04_SOFTWARE_TEST, ENG_SW },
{ NV50_DEFERRED_API_CLASS, ENG_SW },
{ NV50_MEMORY_VIRTUAL, ENG_DMA },
{ NV50_P2P, ENG_BUS },
{ NV50_THIRD_PARTY_P2P, ENG_BUS },
{ NVC372_DISPLAY_SW, ENG_KERNEL_DISPLAY },
{ NVC67A_CURSOR_IMM_CHANNEL_PIO, ENG_KERNEL_DISPLAY },
{ NVC67B_WINDOW_IMM_CHANNEL_DMA, ENG_KERNEL_DISPLAY },
{ NVC67E_WINDOW_CHANNEL_DMA, ENG_KERNEL_DISPLAY },
{ NVC770_DISPLAY, ENG_KERNEL_DISPLAY },
{ NVC771_DISP_SF_USER, ENG_KERNEL_DISPLAY },
{ NVC773_DISP_CAPABILITIES, ENG_KERNEL_DISPLAY },
{ NVC77D_CORE_CHANNEL_DMA, ENG_KERNEL_DISPLAY },
{ NVC9B0_VIDEO_DECODER, ENG_NVDEC(0) },
{ NVC9B0_VIDEO_DECODER, ENG_NVDEC(1) },
{ NVC9B0_VIDEO_DECODER, ENG_NVDEC(2) },
{ NVC9B0_VIDEO_DECODER, ENG_NVDEC(3) },
{ NVC9B7_VIDEO_ENCODER, ENG_MSENC(0) },
{ NVC9B7_VIDEO_ENCODER, ENG_MSENC(1) },
{ NVC9B7_VIDEO_ENCODER, ENG_MSENC(2) },
{ NVC9D1_VIDEO_NVJPG, ENG_NVJPEG(0) },
{ NVC9D1_VIDEO_NVJPG, ENG_NVJPEG(1) },
{ NVC9D1_VIDEO_NVJPG, ENG_NVJPEG(2) },
{ NVC9D1_VIDEO_NVJPG, ENG_NVJPEG(3) },
{ NVC9FA_VIDEO_OFA, ENG_OFA },
{ TURING_CHANNEL_GPFIFO_A, ENG_KERNEL_FIFO },
{ TURING_USERMODE_A, ENG_GPU },
{ VOLTA_CHANNEL_GPFIFO_A, ENG_KERNEL_FIFO },
{ VOLTA_USERMODE_A, ENG_GPU },
};
#define HALAD102_NUM_CLASS_DESCS (sizeof(halAD102ClassDescriptorList) / sizeof(CLASSDESCRIPTOR))
ct_assert(NV0080_CTRL_GPU_CLASSLIST_MAX_SIZE >= HALAD102_NUM_CLASS_DESCS);
*pNumClasses = HALAD102_NUM_CLASS_DESCS;
return halAD102ClassDescriptorList;
}
const CLASSDESCRIPTOR *
gpuGetClassDescriptorList_AD103(POBJGPU pGpu, NvU32 *pNumClasses)
{
static const CLASSDESCRIPTOR halAD103ClassDescriptorList[] = {
{ ACCESS_COUNTER_NOTIFY_BUFFER, ENG_GR(0) },
{ ADA_A, ENG_GR(0) },
{ ADA_COMPUTE_A, ENG_GR(0) },
{ AMPERE_CHANNEL_GPFIFO_A, ENG_KERNEL_FIFO },
{ AMPERE_DMA_COPY_B, ENG_CE(0) },
{ AMPERE_DMA_COPY_B, ENG_CE(1) },
{ AMPERE_DMA_COPY_B, ENG_CE(2) },
{ AMPERE_DMA_COPY_B, ENG_CE(3) },
{ AMPERE_DMA_COPY_B, ENG_CE(4) },
{ AMPERE_USERMODE_A, ENG_GPU },
{ FERMI_CONTEXT_SHARE_A, ENG_KERNEL_FIFO },
{ FERMI_TWOD_A, ENG_GR(0) },
{ FERMI_VASPACE_A, ENG_DMA },
{ G84_PERFBUFFER, ENG_BUS },
{ GF100_DISP_SW, ENG_SW },
{ GF100_HDACODEC, ENG_HDACODEC },
{ GF100_SUBDEVICE_MASTER, ENG_GPU },
{ GF100_TIMED_SEMAPHORE_SW, ENG_SW },
{ GF100_ZBC_CLEAR, ENG_KERNEL_MEMORY_SYSTEM },
{ GP100_UVM_SW, ENG_SW },
{ KEPLER_CHANNEL_GROUP_A, ENG_KERNEL_FIFO },
{ KEPLER_INLINE_TO_MEMORY_B, ENG_GR(0) },
{ MMU_FAULT_BUFFER, ENG_GR(0) },
{ NV0060_SYNC_GPU_BOOST, ENG_GPU },
{ NV01_MEMORY_VIRTUAL, ENG_DMA },
{ NV04_DISPLAY_COMMON, ENG_KERNEL_DISPLAY },
{ NV04_SOFTWARE_TEST, ENG_SW },
{ NV50_DEFERRED_API_CLASS, ENG_SW },
{ NV50_MEMORY_VIRTUAL, ENG_DMA },
{ NV50_P2P, ENG_BUS },
{ NV50_THIRD_PARTY_P2P, ENG_BUS },
{ NVC372_DISPLAY_SW, ENG_KERNEL_DISPLAY },
{ NVC67A_CURSOR_IMM_CHANNEL_PIO, ENG_KERNEL_DISPLAY },
{ NVC67B_WINDOW_IMM_CHANNEL_DMA, ENG_KERNEL_DISPLAY },
{ NVC67E_WINDOW_CHANNEL_DMA, ENG_KERNEL_DISPLAY },
{ NVC770_DISPLAY, ENG_KERNEL_DISPLAY },
{ NVC771_DISP_SF_USER, ENG_KERNEL_DISPLAY },
{ NVC773_DISP_CAPABILITIES, ENG_KERNEL_DISPLAY },
{ NVC77D_CORE_CHANNEL_DMA, ENG_KERNEL_DISPLAY },
{ NVC9B0_VIDEO_DECODER, ENG_NVDEC(0) },
{ NVC9B0_VIDEO_DECODER, ENG_NVDEC(1) },
{ NVC9B0_VIDEO_DECODER, ENG_NVDEC(2) },
{ NVC9B0_VIDEO_DECODER, ENG_NVDEC(3) },
{ NVC9B7_VIDEO_ENCODER, ENG_MSENC(0) },
{ NVC9B7_VIDEO_ENCODER, ENG_MSENC(1) },
{ NVC9B7_VIDEO_ENCODER, ENG_MSENC(2) },
{ NVC9D1_VIDEO_NVJPG, ENG_NVJPEG(0) },
{ NVC9D1_VIDEO_NVJPG, ENG_NVJPEG(1) },
{ NVC9D1_VIDEO_NVJPG, ENG_NVJPEG(2) },
{ NVC9D1_VIDEO_NVJPG, ENG_NVJPEG(3) },
{ NVC9FA_VIDEO_OFA, ENG_OFA },
{ TURING_CHANNEL_GPFIFO_A, ENG_KERNEL_FIFO },
{ TURING_USERMODE_A, ENG_GPU },
{ VOLTA_CHANNEL_GPFIFO_A, ENG_KERNEL_FIFO },
{ VOLTA_USERMODE_A, ENG_GPU },
};
#define HALAD103_NUM_CLASS_DESCS (sizeof(halAD103ClassDescriptorList) / sizeof(CLASSDESCRIPTOR))
ct_assert(NV0080_CTRL_GPU_CLASSLIST_MAX_SIZE >= HALAD103_NUM_CLASS_DESCS);
*pNumClasses = HALAD103_NUM_CLASS_DESCS;
return halAD103ClassDescriptorList;
}
const CLASSDESCRIPTOR *
gpuGetClassDescriptorList_AD104(POBJGPU pGpu, NvU32 *pNumClasses)
{
static const CLASSDESCRIPTOR halAD104ClassDescriptorList[] = {
{ ACCESS_COUNTER_NOTIFY_BUFFER, ENG_GR(0) },
{ ADA_A, ENG_GR(0) },
{ ADA_COMPUTE_A, ENG_GR(0) },
{ AMPERE_CHANNEL_GPFIFO_A, ENG_KERNEL_FIFO },
{ AMPERE_DMA_COPY_B, ENG_CE(0) },
{ AMPERE_DMA_COPY_B, ENG_CE(1) },
{ AMPERE_DMA_COPY_B, ENG_CE(2) },
{ AMPERE_DMA_COPY_B, ENG_CE(3) },
{ AMPERE_DMA_COPY_B, ENG_CE(4) },
{ AMPERE_USERMODE_A, ENG_GPU },
{ FERMI_CONTEXT_SHARE_A, ENG_KERNEL_FIFO },
{ FERMI_TWOD_A, ENG_GR(0) },
{ FERMI_VASPACE_A, ENG_DMA },
{ G84_PERFBUFFER, ENG_BUS },
{ GF100_DISP_SW, ENG_SW },
{ GF100_HDACODEC, ENG_HDACODEC },
{ GF100_SUBDEVICE_MASTER, ENG_GPU },
{ GF100_TIMED_SEMAPHORE_SW, ENG_SW },
{ GF100_ZBC_CLEAR, ENG_KERNEL_MEMORY_SYSTEM },
{ GP100_UVM_SW, ENG_SW },
{ KEPLER_CHANNEL_GROUP_A, ENG_KERNEL_FIFO },
{ KEPLER_INLINE_TO_MEMORY_B, ENG_GR(0) },
{ MMU_FAULT_BUFFER, ENG_GR(0) },
{ NV0060_SYNC_GPU_BOOST, ENG_GPU },
{ NV01_MEMORY_VIRTUAL, ENG_DMA },
{ NV04_DISPLAY_COMMON, ENG_KERNEL_DISPLAY },
{ NV04_SOFTWARE_TEST, ENG_SW },
{ NV50_DEFERRED_API_CLASS, ENG_SW },
{ NV50_MEMORY_VIRTUAL, ENG_DMA },
{ NV50_P2P, ENG_BUS },
{ NV50_THIRD_PARTY_P2P, ENG_BUS },
{ NVC372_DISPLAY_SW, ENG_KERNEL_DISPLAY },
{ NVC67A_CURSOR_IMM_CHANNEL_PIO, ENG_KERNEL_DISPLAY },
{ NVC67B_WINDOW_IMM_CHANNEL_DMA, ENG_KERNEL_DISPLAY },
{ NVC67E_WINDOW_CHANNEL_DMA, ENG_KERNEL_DISPLAY },
{ NVC770_DISPLAY, ENG_KERNEL_DISPLAY },
{ NVC771_DISP_SF_USER, ENG_KERNEL_DISPLAY },
{ NVC773_DISP_CAPABILITIES, ENG_KERNEL_DISPLAY },
{ NVC77D_CORE_CHANNEL_DMA, ENG_KERNEL_DISPLAY },
{ NVC9B0_VIDEO_DECODER, ENG_NVDEC(0) },
{ NVC9B0_VIDEO_DECODER, ENG_NVDEC(1) },
{ NVC9B0_VIDEO_DECODER, ENG_NVDEC(2) },
{ NVC9B0_VIDEO_DECODER, ENG_NVDEC(3) },
{ NVC9B7_VIDEO_ENCODER, ENG_MSENC(0) },
{ NVC9B7_VIDEO_ENCODER, ENG_MSENC(1) },
{ NVC9B7_VIDEO_ENCODER, ENG_MSENC(2) },
{ NVC9D1_VIDEO_NVJPG, ENG_NVJPEG(0) },
{ NVC9D1_VIDEO_NVJPG, ENG_NVJPEG(1) },
{ NVC9D1_VIDEO_NVJPG, ENG_NVJPEG(2) },
{ NVC9D1_VIDEO_NVJPG, ENG_NVJPEG(3) },
{ NVC9FA_VIDEO_OFA, ENG_OFA },
{ TURING_CHANNEL_GPFIFO_A, ENG_KERNEL_FIFO },
{ TURING_USERMODE_A, ENG_GPU },
{ VOLTA_CHANNEL_GPFIFO_A, ENG_KERNEL_FIFO },
{ VOLTA_USERMODE_A, ENG_GPU },
};
#define HALAD104_NUM_CLASS_DESCS (sizeof(halAD104ClassDescriptorList) / sizeof(CLASSDESCRIPTOR))
ct_assert(NV0080_CTRL_GPU_CLASSLIST_MAX_SIZE >= HALAD104_NUM_CLASS_DESCS);
*pNumClasses = HALAD104_NUM_CLASS_DESCS;
return halAD104ClassDescriptorList;
}
const CLASSDESCRIPTOR *
gpuGetClassDescriptorList_GH100(POBJGPU pGpu, NvU32 *pNumClasses)
{
static const CLASSDESCRIPTOR halGH100ClassDescriptorList[] = {
{ ACCESS_COUNTER_NOTIFY_BUFFER, ENG_GR(0) },
{ AMPERE_CHANNEL_GPFIFO_A, ENG_KERNEL_FIFO },
{ AMPERE_USERMODE_A, ENG_GPU },
{ FERMI_CONTEXT_SHARE_A, ENG_KERNEL_FIFO },
{ FERMI_TWOD_A, ENG_GR(0) },
{ FERMI_VASPACE_A, ENG_DMA },
{ G84_PERFBUFFER, ENG_BUS },
{ GF100_SUBDEVICE_MASTER, ENG_GPU },
{ GF100_TIMED_SEMAPHORE_SW, ENG_SW },
{ GF100_ZBC_CLEAR, ENG_KERNEL_MEMORY_SYSTEM },
{ GP100_UVM_SW, ENG_SW },
{ HOPPER_A, ENG_GR(0) },
{ HOPPER_CHANNEL_GPFIFO_A, ENG_KERNEL_FIFO },
{ HOPPER_COMPUTE_A, ENG_GR(0) },
{ HOPPER_COMPUTE_A, ENG_GR(1) },
{ HOPPER_COMPUTE_A, ENG_GR(2) },
{ HOPPER_COMPUTE_A, ENG_GR(3) },
{ HOPPER_COMPUTE_A, ENG_GR(4) },
{ HOPPER_COMPUTE_A, ENG_GR(5) },
{ HOPPER_COMPUTE_A, ENG_GR(6) },
{ HOPPER_COMPUTE_A, ENG_GR(7) },
{ HOPPER_DMA_COPY_A, ENG_CE(0) },
{ HOPPER_DMA_COPY_A, ENG_CE(1) },
{ HOPPER_DMA_COPY_A, ENG_CE(2) },
{ HOPPER_DMA_COPY_A, ENG_CE(3) },
{ HOPPER_DMA_COPY_A, ENG_CE(4) },
{ HOPPER_DMA_COPY_A, ENG_CE(5) },
{ HOPPER_DMA_COPY_A, ENG_CE(6) },
{ HOPPER_DMA_COPY_A, ENG_CE(7) },
{ HOPPER_DMA_COPY_A, ENG_CE(8) },
{ HOPPER_DMA_COPY_A, ENG_CE(9) },
{ HOPPER_USERMODE_A, ENG_GPU },
{ KEPLER_CHANNEL_GROUP_A, ENG_KERNEL_FIFO },
{ KEPLER_INLINE_TO_MEMORY_B, ENG_GR(0) },
{ MMU_FAULT_BUFFER, ENG_GR(0) },
{ NV0060_SYNC_GPU_BOOST, ENG_GPU },
{ NV01_MEMORY_VIRTUAL, ENG_DMA },
{ NV04_SOFTWARE_TEST, ENG_SW },
{ NV50_DEFERRED_API_CLASS, ENG_SW },
{ NV50_MEMORY_VIRTUAL, ENG_DMA },
{ NV50_P2P, ENG_BUS },
{ NV50_THIRD_PARTY_P2P, ENG_BUS },
{ NVB8B0_VIDEO_DECODER, ENG_NVDEC(0) },
{ NVB8B0_VIDEO_DECODER, ENG_NVDEC(1) },
{ NVB8B0_VIDEO_DECODER, ENG_NVDEC(2) },
{ NVB8B0_VIDEO_DECODER, ENG_NVDEC(3) },
{ NVB8B0_VIDEO_DECODER, ENG_NVDEC(4) },
{ NVB8B0_VIDEO_DECODER, ENG_NVDEC(5) },
{ NVB8B0_VIDEO_DECODER, ENG_NVDEC(6) },
{ NVB8B0_VIDEO_DECODER, ENG_NVDEC(7) },
{ NVB8D1_VIDEO_NVJPG, ENG_NVJPEG(0) },
{ NVB8D1_VIDEO_NVJPG, ENG_NVJPEG(1) },
{ NVB8D1_VIDEO_NVJPG, ENG_NVJPEG(2) },
{ NVB8D1_VIDEO_NVJPG, ENG_NVJPEG(3) },
{ NVB8D1_VIDEO_NVJPG, ENG_NVJPEG(4) },
{ NVB8D1_VIDEO_NVJPG, ENG_NVJPEG(5) },
{ NVB8D1_VIDEO_NVJPG, ENG_NVJPEG(6) },
{ NVB8D1_VIDEO_NVJPG, ENG_NVJPEG(7) },
{ NVB8FA_VIDEO_OFA, ENG_OFA },
{ TURING_CHANNEL_GPFIFO_A, ENG_KERNEL_FIFO },
{ TURING_USERMODE_A, ENG_GPU },
{ VOLTA_CHANNEL_GPFIFO_A, ENG_KERNEL_FIFO },
{ VOLTA_USERMODE_A, ENG_GPU },
};
#define HALGH100_NUM_CLASS_DESCS (sizeof(halGH100ClassDescriptorList) / sizeof(CLASSDESCRIPTOR))
ct_assert(NV0080_CTRL_GPU_CLASSLIST_MAX_SIZE >= HALGH100_NUM_CLASS_DESCS);
*pNumClasses = HALGH100_NUM_CLASS_DESCS;
return halGH100ClassDescriptorList;
}