NVIDIA/open-gpu-kernel-modules
1
0
Fork 0
mirror of https://github.com/NVIDIA/open-gpu-kernel-modules.git synced 2026-01-30 13:09:47 +00:00
Code Issues Packages Projects Releases Wiki Activity

550.40.07

Browse Source
This commit is contained in:
Bernhard Stoeckner
2024-01-24 17:51:53 +01:00
parent bb2dac1f20
commit 91676d6628
1411 changed files with 261367 additions and 145959 deletions
Download Patch File Download Diff File Expand all files Collapse all files

18
src/common/displayport/inc/dp_configcaps.h
View File

@@ -229,15 +229,15 @@ namespace DisplayPort
// Physical layer feature set
//
virtual NvU64 getMaxLinkRate() = 0; // Maximum byte-block in Hz
virtual unsigned getMaxLaneCount() = 0; // DPCD offset 2
virtual unsigned getMaxLaneCount() = 0; // DPCD offset 0x0002h
virtual unsigned getMaxLaneCountSupportedAtLinkRate(LinkRate linkRate) = 0;
virtual bool getEnhancedFraming() = 0;
virtual bool getSupportsNoHandshakeTraining() = 0;
virtual bool getMsaTimingparIgnored() = 0;
virtual bool getDownstreamPort(NvU8 *portType) = 0; // DPCD offset 5
virtual bool getSupportsMultistream() = 0; // DPCD offset 21h
virtual bool getNoLinkTraining() = 0; // DPCD offset 330h
virtual unsigned getPhyRepeaterCount() = 0; // DPCD offset F0002h
virtual bool getDownstreamPort(NvU8 *portType) = 0; // DPCD offset 0x0005h
virtual bool getSupportsMultistream() = 0; // DPCD offset 0x0021h
virtual bool getNoLinkTraining() = 0; // DPCD offset 0x0330h
virtual unsigned getPhyRepeaterCount() = 0; // DPCD offset 0xF0002h
};
class OUI
@@ -306,7 +306,7 @@ namespace DisplayPort
virtual bool getSDPExtnForColorimetry() = 0;
virtual bool getRootAsyncSDPSupported() = 0;
bool isAtLeastVersion(unsigned major, unsigned minor)
bool isAtLeastVersion(unsigned major, unsigned minor)
{
if (getRevisionMajor() > major)
return true;
@@ -317,7 +317,7 @@ namespace DisplayPort
return getRevisionMinor() >= minor;
}
bool isVersion(unsigned major, unsigned minor)
bool isVersion(unsigned major, unsigned minor)
{
if ((getRevisionMajor() == major) &&
(getRevisionMinor() == minor))
@@ -326,7 +326,7 @@ namespace DisplayPort
return false;
}
bool lttprIsAtLeastVersion(unsigned major, unsigned minor)
bool lttprIsAtLeastVersion(unsigned major, unsigned minor)
{
if (lttprGetRevisionMajor() > major)
return true;
@@ -337,7 +337,7 @@ namespace DisplayPort
return lttprGetRevisionMinor() >= minor;
}
bool lttprIsVersion(unsigned major, unsigned minor)
bool lttprIsVersion(unsigned major, unsigned minor)
{
if ((lttprGetRevisionMajor() == major) &&
(lttprGetRevisionMinor() == minor))

13
src/common/displayport/inc/dp_connector.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -48,7 +48,10 @@
namespace DisplayPort
{
class EvoInterface;
#define SET_DP_IMP_ERROR(pErrorCode, errorCode) \
if (pErrorCode && *pErrorCode == DP_IMP_ERROR_NONE) *pErrorCode = errorCode;
typedef enum
{
DP_IMP_ERROR_NONE,
@@ -497,8 +500,8 @@ namespace DisplayPort
virtual bool compoundQueryAttach(Group * target,
const DpModesetParams &modesetParams, // Modeset info
DscParams *pDscParams, // DSC parameters
DP_IMP_ERROR *errorStatus = NULL) = 0; // Error Status code
DscParams *pDscParams, // DSC parameters
DP_IMP_ERROR *errorStatus = NULL) = 0; // Error Status code
virtual bool endCompoundQuery() = 0;
@@ -729,7 +732,7 @@ namespace DisplayPort
virtual bool readPsrErrorStatus(vesaPsrErrorStatus *psrErr) = 0;
virtual bool writePsrEvtIndicator(vesaPsrEventIndicator psrErr) = 0;
virtual bool readPsrEvtIndicator(vesaPsrEventIndicator *psrErr) = 0;
virtual bool updatePsrLinkState(bool bTrainLink) = 0;
virtual bool updatePsrLinkState(bool bTurnOnLink) = 0;
virtual bool readPrSinkDebugInfo(panelReplaySinkDebugInfo *prDbgInfo) = 0;

20
src/common/displayport/inc/dp_connectorimpl.h
View File

@@ -194,7 +194,9 @@ namespace DisplayPort
unsigned compoundQueryLocalLinkPBN;
bool compoundQueryForceEnableFEC;
unsigned freeSlots, maximumSlots;
unsigned freeSlots;
unsigned maximumSlots;
int firstFreeSlot;
// Multistream messaging
MessageManager * messageManager;
@@ -346,12 +348,22 @@ namespace DisplayPort
//
bool bPowerDownPhyBeforeD3;
//
// Reset the MSTM_CTRL registers on branch device irrespective of
// IRQ VECTOR register having stale message. Certain branch devices
// need to reset the topology before issuing new discovery commands
// as there can be case where previous is still in process and a
// possibility that clearPendingMessage() might not be able to catch
// the stale messages from previous discovery.
//
bool bForceClearPendingMsg;
Group *perHeadAttachedGroup[NV_MAX_HEADS];
NvU32 inTransitionHeadMask;
void sharedInit();
ConnectorImpl(MainLink * main, AuxBus * auxBus, Timer * timer, Connector::EventSink * sink);
void setPolicyModesetOrderMitigation(bool enabled);
void setPolicyForceLTAtNAB(bool enabled);
void setPolicyAssessLinkSafely(bool enabled);
@@ -599,6 +611,8 @@ namespace DisplayPort
bool beforeAddStreamMST(GroupImpl * group, bool force = false, bool forFlushMode = false);
virtual bool checkIsModePossibleMST(GroupImpl * group);
bool deleteAllVirtualChannels();
void clearTimeslices();
bool allocateTimeslice(GroupImpl * targetGroup);
@@ -664,7 +678,7 @@ namespace DisplayPort
virtual bool writePsrEvtIndicator(vesaPsrEventIndicator psrErr);
virtual bool readPsrEvtIndicator(vesaPsrEventIndicator *psrErr);
virtual bool readPsrState(vesaPsrState *psrState);
virtual bool updatePsrLinkState(bool bTrainLink);
virtual bool updatePsrLinkState(bool bTurnOnLink);
virtual bool readPrSinkDebugInfo(panelReplaySinkDebugInfo *prDbgInfo);

2
src/common/displayport/inc/dp_deviceimpl.h
View File

@@ -449,6 +449,8 @@ namespace DisplayPort
NvBool getDSCSupport();
bool getFECSupport();
NvBool isDSCPassThroughSupported();
NvBool isDynamicPPSSupported();
NvBool isDynamicDscToggleSupported();
NvBool isDSCSupported();
NvBool isDSCDecompressionSupported();
NvBool isDSCPossible();

27
src/common/displayport/inc/dp_evoadapter.h
View File

@@ -39,6 +39,8 @@
#include "dp_regkeydatabase.h"
#include <nvos.h>
#include <ctrl/ctrl0073/ctrl0073dfp.h>
#include <ctrl/ctrl0073/ctrl0073dp.h>
#define HDCP_DUMMY_CN (0x1)
#define HDCP_DUMMY_CKSV (0xFFFFF)
@@ -131,10 +133,7 @@ namespace DisplayPort
class EvoMainLink : public MainLink
{
EvoInterface * provider;
Timer * timer;
NvU32 displayId;
NvU32 subdeviceIndex;
private:
NvU32 _maxLinkRateSupportedGpu;
NvU32 _maxLinkRateSupportedDfp;
unsigned allHeadMask;
@@ -160,6 +159,7 @@ namespace DisplayPort
bool _enableMSAOverrideOverMST;
bool _isLTPhyRepeaterSupported;
bool _isMSTPCONCapsReadDisabled;
//
// LTTPR count reported by RM, it might not be the same with DPLib probe
// For example, some Intel LTTPR might not be ready to response 0xF0000 probe
@@ -178,11 +178,19 @@ namespace DisplayPort
unsigned maxNumHztSlices;
unsigned lineBufferBitDepth;
}_DSC;
private:
void initializeRegkeyDatabase();
void applyRegkeyOverrides();
protected:
EvoInterface * provider;
Timer * timer;
NvU32 displayId;
NvU32 subdeviceIndex;
NV0073_CTRL_DFP_GET_INFO_PARAMS dfpParams;
NV0073_CTRL_CMD_DP_GET_CAPS_PARAMS dpParams;
public:
EvoMainLink(EvoInterface * provider, Timer * timer);
@@ -379,8 +387,8 @@ namespace DisplayPort
bool isActive();
bool isEDP();
bool skipPowerdownEdpPanelWhenHeadDetach();
bool isMSTPCONCapsReadDisabled();
bool supportMSAOverMST();
bool queryAndUpdateDfpParams();
bool controlRateGoverning(NvU32 head, bool enable, bool updateNow);
bool getDpTestPattern(NV0073_CTRL_DP_TESTPATTERN *testPattern);
@@ -393,14 +401,15 @@ namespace DisplayPort
NvU32 monitorDenylistInfo(NvU32 ManufacturerID, NvU32 ProductID, DpMonitorDenylistData *pDenylistData);
NvU32 allocDisplayId();
bool freeDisplayId(NvU32 displayId);
void queryGPUCapability();
virtual bool queryAndUpdateDfpParams();
virtual bool queryGPUCapability();
bool getEdpPowerData(bool *panelPowerOn, bool *dpcdPowerStateD0);
virtual bool vrrRunEnablementStage(unsigned stage, NvU32 *status);
void configureTriggerSelect(NvU32 head,
DP_SINGLE_HEAD_MULTI_STREAM_PIPELINE_ID streamIdentifier = DP_SINGLE_HEAD_MULTI_STREAM_PIPELINE_ID_PRIMARY);
void configureTriggerAll(NvU32 head, bool enable);
bool configureLinkRateTable(const NvU16 *pLinkRateTable, LinkRates *pLinkRates);
virtual bool configureLinkRateTable(const NvU16 *pLinkRateTable, LinkRates *pLinkRates);
bool configureFec(const bool bEnableFec);
};

122
src/common/displayport/inc/dp_linkconfig.h
View File

@@ -242,7 +242,6 @@ namespace DisplayPort
bool disablePostLTRequest;
bool bEnableFEC;
bool bDisableLTTPR;
//
// The counter to record how many times link training happens.
// Client can reset the counter by calling setLTCounter(0)
@@ -252,7 +251,8 @@ namespace DisplayPort
LinkConfiguration() :
lanes(0), peakRatePossible(0), peakRate(0), minRate(0),
enhancedFraming(false), multistream(false), disablePostLTRequest(false),
bEnableFEC(false), bDisableLTTPR(false), linkTrainCounter(0) {};
bEnableFEC(false), bDisableLTTPR(false),
linkTrainCounter(0) {};
LinkConfiguration(LinkPolicy * p, unsigned lanes, LinkRate peakRate,
bool enhancedFraming, bool MST, bool disablePostLTRequest = false,
@@ -316,42 +316,113 @@ namespace DisplayPort
bDisableLTTPR(false),
linkTrainCounter(0)
{
//
// Reverse engineer a link configuration from Total TotalLinkPBN
// Note that HBR2 twice HBR. The table below treats HBR2x1 and HBRx2, etc.
//
// BW Effective Lanes Total TotalLinkPBN
// 165 1 195.5555556
// 165 2 391.1111111
// 165 4 782.2222222
// 270 1 320
// 270 2 640
// 270 4 1280
// 270 8 2560
// PBN Calculation
// Definition of PBN is "54/64 MBps".
// Note this is the "data" actually transmitted in the main link.
// So we need to take channel coding into consideration.
// Formula: PBN = Lane Count * Link Rate (Gbps) * 1000 * (1/8) * ChannelCoding Efficiency * (64 / 54)
// Example:
// 1. 4 * HBR2: 4 * 5.4 * 1000 * (1/8) * (8/10) * (64/54) = 2560
// 2. 2 * UHBR10: 2 * 10 * 1000 * (1/8) * (128/132) * (64/54) = 2873
//
// Full list:
//
// BW (Gbps) Lanes TotalLinkPBN
// 1.62 1 192
// 1.62 2 384
// 1.62 4 768
// 2.70 1 320
// 2.70 2 640
// 2.70 4 1280
// 5.40 1 640
// 5.40 2 1280
// 5.40 4 2560
// 8.10 1 960
// 8.10 2 1920
// 8.10 4 3840
// 10.00 1 1436
// 10.00 2 2873
// 10.00 4 5746
// 13.50 1 1939
// 13.50 2 3878
// 13.50 4 7757
// 20.00 1 2873
// 20.00 2 5746
// 20.00 4 11492
//
if (TotalLinkPBN <= 90)
peakRatePossible = peakRate = RBR, minRate = linkOverhead(RBR), lanes=0; // FAIL
if (TotalLinkPBN <= 195)
peakRatePossible = peakRate = RBR, minRate = linkOverhead(RBR), lanes=1;
{
peakRatePossible = peakRate = RBR;
minRate = linkOverhead(RBR);
lanes = 0; // FAIL
}
if (TotalLinkPBN <= 192)
{
peakRatePossible = peakRate = RBR;
minRate = linkOverhead(RBR);
lanes = 1;
}
else if (TotalLinkPBN <= 320)
peakRatePossible = peakRate = HBR, minRate=linkOverhead(HBR), lanes = 1;
else if (TotalLinkPBN <= 391)
peakRatePossible = peakRate = RBR, minRate=linkOverhead(RBR), lanes = 2;
{
peakRatePossible = peakRate = HBR;
minRate = linkOverhead(HBR);
lanes = 1;
}
else if (TotalLinkPBN <= 384)
{
peakRatePossible = peakRate = RBR;
minRate = linkOverhead(RBR);
lanes = 2;
}
else if (TotalLinkPBN <= 640)
peakRatePossible = peakRate = HBR, minRate=linkOverhead(HBR), lanes = 2; // could be HBR2x1, but TotalLinkPBN works out same
else if (TotalLinkPBN <= 782)
peakRatePossible = peakRate = RBR, minRate=linkOverhead(RBR), lanes = 4;
{
// could be HBR2 x 1, but TotalLinkPBN works out same
peakRatePossible = peakRate = HBR;
minRate = linkOverhead(HBR);
lanes = 2;
}
else if (TotalLinkPBN <= 768)
{
peakRatePossible = peakRate = RBR;
minRate = linkOverhead(RBR);
lanes = 4;
}
else if (TotalLinkPBN <= 960)
peakRatePossible = peakRate = HBR3, minRate=linkOverhead(HBR3), lanes = 1;
{
peakRatePossible = peakRate = HBR3;
minRate = linkOverhead(HBR3);
lanes = 1;
}
else if (TotalLinkPBN <= 1280)
peakRatePossible = peakRate = HBR, minRate=linkOverhead(HBR), lanes = 4; // could be HBR2x2
{
// could be HBR2 x 2
peakRatePossible = peakRate = HBR;
minRate = linkOverhead(HBR);
lanes = 4;
}
else if (TotalLinkPBN <= 1920)
peakRatePossible = peakRate = HBR3, minRate=linkOverhead(HBR3), lanes = 2; // could be HBR2x
{
peakRatePossible = peakRate = HBR3;
minRate = linkOverhead(HBR3);
lanes = 2;
}
else if (TotalLinkPBN <= 2560)
peakRatePossible = peakRate = HBR2, minRate=linkOverhead(HBR2), lanes = 4;
{
peakRatePossible = peakRate = HBR2;
minRate = linkOverhead(HBR2);
lanes = 4;
}
else if (TotalLinkPBN <= 3840)
peakRatePossible = peakRate = HBR3, minRate=linkOverhead(HBR3), lanes = 4;
{
peakRatePossible = peakRate = HBR3;
minRate = linkOverhead(HBR3);
lanes = 4;
}
else {
peakRatePossible = peakRate = RBR, minRate = linkOverhead(RBR), lanes = 0; // FAIL
DP_ASSERT(0 && "Unknown configuration");
@@ -412,7 +483,6 @@ namespace DisplayPort
}
minRate = linkOverhead(peakRate);
return lanes != laneCount_0;
}

5
src/common/displayport/inc/dp_mainlink.h
View File

@@ -144,6 +144,9 @@ namespace DisplayPort
// Check if we should skip power down eDP when head detached.
virtual bool skipPowerdownEdpPanelWhenHeadDetach() = 0;
// Check if we should skip reading PCON Caps in MST case.
virtual bool isMSTPCONCapsReadDisabled() = 0;
// Get GPU DSC capabilities
virtual void getDscCaps(bool *pbDscSupported = NULL,
unsigned *pEncoderColorFormatMask = NULL,
@@ -242,7 +245,7 @@ namespace DisplayPort
virtual NvU32 getRootDisplayId() = 0;
virtual NvU32 allocDisplayId() = 0;
virtual bool freeDisplayId(NvU32 displayId) = 0;
virtual void queryGPUCapability() = 0;
virtual bool queryGPUCapability() {return false;}
virtual bool queryAndUpdateDfpParams() = 0;
virtual bool getEdpPowerData(bool *panelPowerOn, bool *bDPCDPowerStateD0) = 0;
virtual bool vrrRunEnablementStage(unsigned stage, NvU32 *status) = 0;

8
src/common/displayport/inc/dp_regkeydatabase.h
View File

@@ -63,7 +63,7 @@
#define NV_DP_REGKEY_POWER_DOWN_PHY "DP_POWER_DOWN_PHY"
//
// Regkey to re-assess max link if the first assessed link config
// Regkey to re-assess max link if the first assessed link config
// is lower than the panel max
//
#define NV_DP_REGKEY_REASSESS_MAX_LINK "DP_REASSESS_MAX_LINK"
@@ -74,6 +74,11 @@
//
#define NV_DP_DSC_MST_CAP_BUG_3143315 "DP_DSC_MST_CAP_BUG_3143315"
//
// Bug 4388987 : This regkey will disable reading PCON caps for MST.
//
#define NV_DP_REGKEY_MST_PCON_CAPS_READ_DISABLED "DP_BUG_4388987_WAR"
//
// Data Base used to store all the regkey values.
// The actual data base is declared statically in dp_evoadapter.cpp.
@@ -107,6 +112,7 @@ struct DP_REGKEY_DATABASE
bool bDscMstCapBug3143315;
bool bPowerDownPhyBeforeD3;
bool bReassessMaxLink;
bool bMSTPCONCapsReadDisabled;
};
#endif //INCLUDED_DP_REGKEYDATABASE_H

1
src/common/displayport/inc/dp_timer.h
View File

@@ -65,7 +65,6 @@ namespace DisplayPort
private:
RawTimer * raw;
NvU64 nextTimestamp;
List pending;
struct PendingCallback : ListElement
{

42
src/common/displayport/inc/dp_watermark.h
View File

@@ -38,13 +38,13 @@ namespace DisplayPort
{
class LinkConfiguration;
struct ModesetInfo
struct ModesetInfo
{
unsigned twoChannelAudioHz; // if you need 192khz stereo specify 192000 here
unsigned eightChannelAudioHz; // Same setting for multi channel audio.
// DisplayPort encodes 3-8 channel streams as 8 channel
NvU64 pixelClockHz; // Requested pixel clock for the mode
unsigned rasterWidth;
unsigned rasterWidth;
unsigned rasterHeight;
unsigned surfaceWidth; // RasterBlankStartX - newRasterBlankEndX
unsigned surfaceHeight; // Active region height
@@ -56,35 +56,35 @@ namespace DisplayPort
DSC_MODE mode; // DSC Mode
bool bEnablePassThroughForPCON;
ModesetInfo(): twoChannelAudioHz(0),
eightChannelAudioHz(0),
pixelClockHz(0),
rasterWidth(0),
rasterHeight(0),
surfaceWidth(0),
ModesetInfo(): twoChannelAudioHz(0),
eightChannelAudioHz(0),
pixelClockHz(0),
rasterWidth(0),
rasterHeight(0),
surfaceWidth(0),
surfaceHeight(0),
depth(0),
rasterBlankStartX(0),
rasterBlankStartX(0),
rasterBlankEndX(0),
bitsPerComponent(0),
bEnableDsc(false),
mode(DSC_SINGLE),
bEnablePassThroughForPCON(false) {}
ModesetInfo(unsigned newTwoChannelAudioHz, unsigned newEightChannelAudioHz, NvU64 newPixelClockHz,
unsigned newRasterWidth, unsigned newRasterHeight,
ModesetInfo(unsigned newTwoChannelAudioHz, unsigned newEightChannelAudioHz, NvU64 newPixelClockHz,
unsigned newRasterWidth, unsigned newRasterHeight,
unsigned newSurfaceWidth, unsigned newSurfaceHeight, unsigned newDepth,
unsigned newRasterBlankStartX=0, unsigned newRasterBlankEndX=0, bool newBEnableDsc = false,
DSC_MODE newMode = DSC_SINGLE, bool newBEnablePassThroughForPCON = false):
twoChannelAudioHz(newTwoChannelAudioHz),
eightChannelAudioHz(newEightChannelAudioHz),
pixelClockHz(newPixelClockHz),
rasterWidth(newRasterWidth),
twoChannelAudioHz(newTwoChannelAudioHz),
eightChannelAudioHz(newEightChannelAudioHz),
pixelClockHz(newPixelClockHz),
rasterWidth(newRasterWidth),
rasterHeight(newRasterHeight),
surfaceWidth(newSurfaceWidth),
surfaceHeight(newSurfaceHeight),
depth(newDepth),
rasterBlankStartX(newRasterBlankStartX),
rasterBlankStartX(newRasterBlankStartX),
rasterBlankEndX(newRasterBlankEndX),
bitsPerComponent(0),
bEnableDsc(newBEnableDsc),
@@ -98,6 +98,7 @@ namespace DisplayPort
unsigned tuSize;
unsigned hBlankSym;
unsigned vBlankSym;
NvU32 effectiveBpp;
};
bool isModePossibleSST
@@ -130,6 +131,13 @@ namespace DisplayPort
Watermark * dpInfo
);
bool dp2xIsModePossibleMSTWithFEC
(
const LinkConfiguration & linkConfig,
const ModesetInfo & modesetInfo,
Watermark * dpInfo
);
// Return Payload Bandwidth Number(PBN)for requested mode
unsigned pbnForMode(const ModesetInfo & modesetInfo);
}

29
src/common/displayport/src/dp_configcaps.cpp
View File

@@ -115,6 +115,8 @@ struct DPCDHALImpl : DPCDHAL
// DPCD Offset 0119h [0] - If we grant the extendedSleepWakeTimeoutRequest
bool bExtendedSleepWakeTimeoutGranted;
bool bFECSupported;
// DPCD Offset F0002h - Number of Physical Repeaters present (after mapping) between Source and Sink
unsigned phyRepeaterCount;
// DPCD offset 700 - EDP_DPCD_REV
@@ -126,6 +128,10 @@ struct DPCDHALImpl : DPCDHAL
LinkRate maxLinkRate; // DPCD offset F0001h
unsigned maxLaneCount; // DPCD offset F0004h
unsigned phyRepeaterExtendedWakeTimeoutMs; // DPCD offset F0005h
// The array to keep track of FEC capability of each LTTPR
bool bFECSupportedRepeater[NV_DPCD14_PHY_REPEATER_CNT_MAX];
// If all the LTTPRs supports FEC
bool bFECSupported;
} repeaterCaps;
PCONCaps pconCaps;
@@ -280,6 +286,11 @@ struct DPCDHALImpl : DPCDHAL
NvU8 byte = 0;
AuxRetry::status status;
unsigned retries = 16;
NvU8 lttprIdx = 0;
caps.phyRepeaterCount = 0;
// Burst read from 0x00 to 0x0F.
//
@@ -530,6 +541,24 @@ struct DPCDHALImpl : DPCDHAL
_PHY_REPEATER_EXTENDED_WAKE_TIMEOUT,
_REQ, buffer[0x5]) * 10;
for (lttprIdx = 0; lttprIdx < caps.phyRepeaterCount; lttprIdx++)
{
caps.repeaterCaps.bFECSupported = true;
if (AuxRetry::ack ==
bus.read(NV_DPCD14_PHY_REPEATER_FEC_CAP_0(lttprIdx), &byte, 1))
{
caps.repeaterCaps.bFECSupportedRepeater[lttprIdx] =
FLD_TEST_DRF(_DPCD14,
_PHY_REPEATER_FEC_CAP_0,
_FEC_CAPABLE,
_YES,
byte);
// bFECSupported is only true if all LTTPR supports FEC.
caps.repeaterCaps.bFECSupported &=
caps.repeaterCaps.bFECSupportedRepeater[lttprIdx];
}
}
}
else
{

334
src/common/displayport/src/dp_connectorimpl.cpp
View File

@@ -48,9 +48,6 @@
#include "ctrl/ctrl0073/ctrl0073dp.h"
#include "dp_tracing.h"
#define SET_DP_IMP_ERROR(pErrorCode, errorCode) \
if (pErrorCode && *pErrorCode == DP_IMP_ERROR_NONE) *pErrorCode = errorCode;
using namespace DisplayPort;
ConnectorImpl::ConnectorImpl(MainLink * main, AuxBus * auxBus, Timer * timer, Connector::EventSink * sink)
@@ -141,12 +138,12 @@ ConnectorImpl::ConnectorImpl(MainLink * main, AuxBus * auxBus, Timer * timer, Co
// Set if LTTPR training is supported per regKey
hal->setLttprSupported(main->isLttprSupported());
const DP_REGKEY_DATABASE& dpRegkeyDatabase = main->getRegkeyDatabase();
this->applyRegkeyOverrides(dpRegkeyDatabase);
hal->applyRegkeyOverrides(dpRegkeyDatabase);
highestAssessedLC = getMaxLinkConfig();
}
void ConnectorImpl::applyRegkeyOverrides(const DP_REGKEY_DATABASE& dpRegkeyDatabase)
@@ -687,8 +684,11 @@ create:
//
else if (newDev->parent && (newDev->parent)->isVirtualPeerDevice())
{
newDev->parent->getPCONCaps(&(newDev->pconCaps));
newDev->connectorType = newDev->parent->getConnectorType();
if (!main->isMSTPCONCapsReadDisabled())
{
newDev->parent->getPCONCaps(&(newDev->pconCaps));
newDev->connectorType = newDev->parent->getConnectorType();
}
}
}
@@ -890,6 +890,9 @@ void ConnectorImpl::hardwareWasReset()
g->setHeadAttached(false);
}
while (!dscEnabledDevices.isEmpty())
(void) dscEnabledDevices.pop();
}
Group * ConnectorImpl::resume(bool firmwareLinkHandsOff,
@@ -999,19 +1002,19 @@ LinkConfiguration ConnectorImpl::getMaxLinkConfig()
}
LinkRate linkRate = maxLinkRate ?
DP_MIN(maxLinkRate, main->maxLinkRateSupported()) :
main->maxLinkRateSupported();
DP_MIN(maxLinkRate, main->maxLinkRateSupported()) :
main->maxLinkRateSupported();
unsigned laneCount = hal->getMaxLaneCount() ?
DP_MIN(hal->getMaxLaneCountSupportedAtLinkRate(linkRate), hal->getMaxLaneCount()) :
4;
DP_MIN(hal->getMaxLaneCountSupportedAtLinkRate(linkRate), hal->getMaxLaneCount()) :
4U;
return LinkConfiguration (&this->linkPolicy,
laneCount, linkRate,
this->hal->getEnhancedFraming(),
linkUseMultistream(),
false, /* disablePostLTRequest */
this->bFECEnable);
laneCount, linkRate,
this->hal->getEnhancedFraming(),
linkUseMultistream(),
false, /* disablePostLTRequest */
this->bFECEnable);
}
LinkConfiguration ConnectorImpl::getActiveLinkConfig()
@@ -1311,36 +1314,20 @@ bool ConnectorImpl::compoundQueryAttachMSTIsDscPossible
{
if (dev && dev->isDSCPossible())
{
if (dev->devDoingDscDecompression != dev)
if ((dev->devDoingDscDecompression != dev) ||
((dev->devDoingDscDecompression == dev) &&
(dev->isLogical() && dev->parent)))
{
//
// If DSC decoding is going to happen at sink's parent then
// we have to make sure the path from source to sink's parent
// is fec is capable.
// If DSC decoding is going to happen at sink's parent or
// decoding will be done by sink but sink is a logical port,
// where intermediate link between Branch DFP and Rx Panel can be
// anything other than DP (i.e. DSI, LVDS or something else),
// then we have to only make sure the path from source to sink's
// parent is fec is capable.
// Refer DP 1.4 Spec 5.4.5
//
if(dev->address.size() == 2)
{
//
// if there is only one branch between source and sink then branch
// should be directly connected to source (sst-case) and dpcd cap
// should already be available.
//
bFecCapable = dev->parent->isFECSupported();
}
else
{
//
// If there are multiple branches in the path, we have to check
// fecCapability field in epr reply to sink's parent's parent.
// Epr reply for each branch should already be updated with inferLeafLink.
// fecCapability field being true here means up to sink's parent,
// which is "downstream end of path" for sink's parent's parent,
// is fec capable.
// Refer DP 1.4 Spec 2.11.9.4.1
//
bFecCapable = dev->parent->parent->isFECSupported();
}
bFecCapable = dev->parent->isFECSupported();
}
else
{
@@ -1480,27 +1467,59 @@ bool ConnectorImpl::compoundQueryAttachMSTDsc(Group * target,
warData.connectorType = DSC_DP;
DSC_GENERATE_PPS_OPAQUE_WORKAREA *pScratchBuffer = nullptr;
pScratchBuffer = (DSC_GENERATE_PPS_OPAQUE_WORKAREA*) dpMalloc(sizeof(DSC_GENERATE_PPS_OPAQUE_WORKAREA));
pScratchBuffer = (DSC_GENERATE_PPS_OPAQUE_WORKAREA*)
dpMalloc(sizeof(DSC_GENERATE_PPS_OPAQUE_WORKAREA));
result = DSC_GeneratePPS(&dscInfo, &modesetInfoDSC,
&warData, availableBandwidthBitsPerSecond,
(NvU32*)(PPS), (NvU32*)(&bitsPerPixelX16),
pScratchBuffer);
pScratchBuffer,
(NvU32*)(PPS), (NvU32*)(&bitsPerPixelX16));
// Try max dsc compression bpp = 8 once to check if that can support that mode.
if (result != NVT_STATUS_SUCCESS && !bDscBppForced)
//
// From NVD 5.0 later, Dplib needs to pass sliceCountMask to clients
// with all slice counts that can support the mode since clients
// might need to use a slice count other than the minimum slice count
// that supports the mode. Currently we keep the same policy of
// trying 10 bpp first and if that does not pass, try 8pp. But later
// with dynamic PPS update, this will be moved a better algorithm,
// that optimizes bpp for requested mode on each display.
//
if (dscInfo.gpuCaps.maxNumHztSlices > 4U)
{
result = DSC_GeneratePPSWithSliceCountMask(&dscInfo, &modesetInfoDSC,
&warData, availableBandwidthBitsPerSecond,
(NvU32*)(PPS),
(NvU32*)(&bitsPerPixelX16),
&(pDscParams->sliceCountMask));
// Try max dsc compression bpp = 8 once to check if that can support that mode.
if (result != NVT_STATUS_SUCCESS && !bDscBppForced)
{
pDscParams->bitsPerPixelX16 = MAX_DSC_COMPRESSION_BPPX16;
bitsPerPixelX16 = pDscParams->bitsPerPixelX16;
result = DSC_GeneratePPSWithSliceCountMask(&dscInfo, &modesetInfoDSC,
&warData, availableBandwidthBitsPerSecond,
(NvU32*)(PPS),
(NvU32*)(&bitsPerPixelX16),
&(pDscParams->sliceCountMask));
}
}
else
{
pDscParams->bitsPerPixelX16 = MAX_DSC_COMPRESSION_BPPX16;
bitsPerPixelX16 = pDscParams->bitsPerPixelX16;
result = DSC_GeneratePPS(&dscInfo, &modesetInfoDSC,
&warData, availableBandwidthBitsPerSecond,
(NvU32*)(PPS), (NvU32*)(&bitsPerPixelX16),
pScratchBuffer);
pScratchBuffer, (NvU32*)(PPS),
(NvU32*)(&bitsPerPixelX16));
// Try max dsc compression bpp = 8 once to check if that can support that mode.
if (result != NVT_STATUS_SUCCESS && !bDscBppForced)
{
pDscParams->bitsPerPixelX16 = MAX_DSC_COMPRESSION_BPPX16;
bitsPerPixelX16 = pDscParams->bitsPerPixelX16;
result = DSC_GeneratePPS(&dscInfo, &modesetInfoDSC,
&warData, availableBandwidthBitsPerSecond,
pScratchBuffer, (NvU32*)(PPS),
(NvU32*)(&bitsPerPixelX16));
}
}
if (pScratchBuffer)
if (pScratchBuffer != nullptr)
{
dpFree(pScratchBuffer);
pScratchBuffer = nullptr;
@@ -1557,9 +1576,9 @@ bool ConnectorImpl::compoundQueryAttachMSTDsc(Group * target,
//
if (dev->pconCaps.maxHdmiLinkBandwidthGbps != 0)
{
NvU64 requiredBW = (NvU64)(modesetParams.modesetInfo.pixelClockHz * modesetParams.modesetInfo.depth);
NvU64 availableBw = (NvU64)(dev->pconCaps.maxHdmiLinkBandwidthGbps * 1000000000);
if (requiredBW > availableBw)
NvU64 requiredBw = (NvU64)(modesetParams.modesetInfo.pixelClockHz * modesetParams.modesetInfo.depth);
NvU64 availableBw = (NvU64)(dev->pconCaps.maxHdmiLinkBandwidthGbps * (NvU64)1000000000U);
if (requiredBw > availableBw)
{
compoundQueryResult = false;
SET_DP_IMP_ERROR(pErrorCode, DP_IMP_ERROR_DSC_PCON_FRL_BANDWIDTH)
@@ -1574,10 +1593,10 @@ bool ConnectorImpl::compoundQueryAttachMSTDsc(Group * target,
else if (dev->pconCaps.maxTmdsClkRate != 0)
{
NvU64 maxTmdsClkRateU64 = (NvU64)(dev->pconCaps.maxTmdsClkRate);
NvU64 requireBw = (NvU64)(modesetParams.modesetInfo.pixelClockHz * modesetParams.modesetInfo.depth);
NvU64 requiredBw = (NvU64)(modesetParams.modesetInfo.pixelClockHz * modesetParams.modesetInfo.depth);
if (modesetParams.colorFormat == dpColorFormat_YCbCr420)
{
if (maxTmdsClkRateU64 < ((requireBw/24)/2))
if (maxTmdsClkRateU64 < ((requiredBw/24)/2))
{
compoundQueryResult = false;
SET_DP_IMP_ERROR(pErrorCode, DP_IMP_ERROR_DSC_PCON_HDMI2_BANDWIDTH)
@@ -1586,7 +1605,7 @@ bool ConnectorImpl::compoundQueryAttachMSTDsc(Group * target,
}
else
{
if (maxTmdsClkRateU64 < (requireBw/24))
if (maxTmdsClkRateU64 < (requiredBw/24))
{
compoundQueryResult = false;
SET_DP_IMP_ERROR(pErrorCode, DP_IMP_ERROR_DSC_PCON_HDMI2_BANDWIDTH)
@@ -1829,14 +1848,14 @@ bool ConnectorImpl::compoundQueryAttachSST(Group * target,
warData.connectorType = DSC_DP;
DSC_GENERATE_PPS_OPAQUE_WORKAREA *pScratchBuffer = nullptr;
pScratchBuffer = (DSC_GENERATE_PPS_OPAQUE_WORKAREA*) dpMalloc(sizeof(DSC_GENERATE_PPS_OPAQUE_WORKAREA));
pScratchBuffer = (DSC_GENERATE_PPS_OPAQUE_WORKAREA*)
dpMalloc(sizeof(DSC_GENERATE_PPS_OPAQUE_WORKAREA));
NVT_STATUS ppsStatus = DSC_GeneratePPS(&dscInfo, &modesetInfoDSC,
&warData, availableBandwidthBitsPerSecond,
pScratchBuffer,
(NvU32*)(PPS),
(NvU32*)(&bitsPerPixelX16),
pScratchBuffer);
if (pScratchBuffer)
(NvU32*)(&bitsPerPixelX16));
if (pScratchBuffer != nullptr)
{
dpFree(pScratchBuffer);
pScratchBuffer = nullptr;
@@ -2836,24 +2855,17 @@ bool ConnectorImpl::setDeviceDscState(Device * dev, bool bEnableDsc)
if (bEnableDsc)
{
if (dscEnabledDevices.contains(dev))
{
DP_LOG(("DP> DSC already enabled on device"));
return true;
}
if(!(((DeviceImpl *)dev)->setDscEnable(true /*bEnableDsc*/)))
{
DP_ASSERT(!"DP-CONN> Failed to configure DSC on Sink!");
return false;
}
dscEnabledDevices.insertFront(dev);
if (!dscEnabledDevices.contains(dev))
dscEnabledDevices.insertFront(dev);
}
else
{
if (!dscEnabledDevices.contains(dev))
{
return true;
}
bool bCurrDscEnable = false;
// Get Current DSC Enable State
if (!((DeviceImpl *)dev)->getDscEnable(&bCurrDscEnable))
@@ -2875,13 +2887,16 @@ bool ConnectorImpl::setDeviceDscState(Device * dev, bool bEnableDsc)
break;
}
}
if(bDisableDsc && !((DeviceImpl *)dev)->setDscEnable(false /*bEnableDsc*/))
{
DP_ASSERT(!"DP-CONN> Failed to configure DSC on Sink!");
return false;
}
}
dscEnabledDevices.remove(dev);
if (dscEnabledDevices.contains(dev))
dscEnabledDevices.remove(dev);
}
return true;
}
@@ -3139,8 +3154,8 @@ bool ConnectorImpl::notifyAttachBegin(Group * target, // Gr
if (linkUseMultistream())
{
// Which pipeline to take the affect out of trigger ACT
if ((DP_SINGLE_HEAD_MULTI_STREAM_MODE_MST != targetImpl->singleHeadMultiStreamMode) ||
(DP_SINGLE_HEAD_MULTI_STREAM_PIPELINE_ID_PRIMARY == targetImpl->singleHeadMultiStreamID))
if ((targetImpl->singleHeadMultiStreamMode != DP_SINGLE_HEAD_MULTI_STREAM_MODE_MST) ||
(targetImpl->singleHeadMultiStreamID == DP_SINGLE_HEAD_MULTI_STREAM_PIPELINE_ID_PRIMARY))
{
main->configureTriggerSelect(targetImpl->headIndex, targetImpl->singleHeadMultiStreamID);
}
@@ -3244,8 +3259,8 @@ void ConnectorImpl::notifyAttachEnd(bool modesetCancelled)
// Add rest of the streams (other than primary) in notifyAE, since this can't be done
// unless a SOR is attached to a Head (part of modeset), and trigger ACT immediate
//
if ((DP_SINGLE_HEAD_MULTI_STREAM_MODE_MST == currentModesetDeviceGroup->singleHeadMultiStreamMode) &&
(currentModesetDeviceGroup->singleHeadMultiStreamID > DP_SINGLE_HEAD_MULTI_STREAM_PIPELINE_ID_PRIMARY))
if ((currentModesetDeviceGroup->singleHeadMultiStreamMode == DP_SINGLE_HEAD_MULTI_STREAM_MODE_MST) &&
(currentModesetDeviceGroup->singleHeadMultiStreamID > DP_SINGLE_HEAD_MULTI_STREAM_PIPELINE_ID_PRIMARY))
{
DP_ASSERT(linkUseMultistream() && "it should be multistream link to configure single head MST");
hal->payloadTableClearACT();
@@ -3307,13 +3322,13 @@ void ConnectorImpl::notifyDetachBegin(Group * target)
// Set the trigger select so as to which frontend corresponding to the stream
// to take the affect
//
if(linkUseMultistream())
if (linkUseMultistream())
{
main->configureTriggerSelect(group->headIndex, group->singleHeadMultiStreamID);
// Clear payload of other than primary streams and trigger ACT immediate
if ((DP_SINGLE_HEAD_MULTI_STREAM_MODE_MST == group->singleHeadMultiStreamMode) &&
(DP_SINGLE_HEAD_MULTI_STREAM_PIPELINE_ID_PRIMARY != group->singleHeadMultiStreamID))
if ((group->singleHeadMultiStreamMode == DP_SINGLE_HEAD_MULTI_STREAM_MODE_MST) &&
(group->singleHeadMultiStreamID != DP_SINGLE_HEAD_MULTI_STREAM_PIPELINE_ID_PRIMARY))
{
main->triggerACT();
if (!hal->payloadWaitForACTReceived())
@@ -4162,7 +4177,7 @@ bool ConnectorImpl::handleCPIRQ()
if (pGroupAttached &&
(pGroupAttached->singleHeadMultiStreamMode == DP_SINGLE_HEAD_MULTI_STREAM_MODE_SST) &&
(pGroupAttached->singleHeadMultiStreamID == DP_SINGLE_HEAD_MULTI_STREAM_PIPELINE_ID_SECONDARY))
(pGroupAttached->singleHeadMultiStreamID == DP_SINGLE_HEAD_MULTI_STREAM_PIPELINE_ID_SECONDARY))
{
DP_ASSERT(this->pCoupledConnector);
sstPrim = this->pCoupledConnector;
@@ -5063,20 +5078,17 @@ bool ConnectorImpl::train(const LinkConfiguration & lConfig, bool force,
LinkTrainingType trainType)
{
LinkTrainingType preferredTrainingType = trainType;
bool result;
bool result = true;
//
// Validate link config against caps
//
if (!force)
if (!force && !validateLinkConfiguration(lConfig))
{
if (!validateLinkConfiguration(lConfig))
return false;
return false;
}
if (!lConfig.multistream)
{
for (Device * i = enumDevices(0); i; i=enumDevices(i))
for (Device * i = enumDevices(0); i; i=enumDevices(i))
{
DeviceImpl * dev = (DeviceImpl *)i;
if (dev->powerOnMonitorBeforeLt() && lConfig.lanes != 0)
@@ -5100,7 +5112,6 @@ bool ConnectorImpl::train(const LinkConfiguration & lConfig, bool force,
else if (hal->getSupportsNoHandshakeTraining())
preferredTrainingType = FAST_LINK_TRAINING;
}
}
//
@@ -5145,7 +5156,15 @@ bool ConnectorImpl::train(const LinkConfiguration & lConfig, bool force,
if (!result)
activeLinkConfig.lanes = 0;
else
{
if (activeLinkConfig.multistream)
{
// Total slot is 64, reserve slot 0 for header
maximumSlots = 63;
firstFreeSlot = 1;
}
bNoLtDoneAfterHeadDetach = false;
}
if (!force && result)
this->hal->setDirtyLinkStatus(true);
@@ -5184,6 +5203,13 @@ bool ConnectorImpl::train(const LinkConfiguration & lConfig, bool force,
// fallback happens, returns fail to make sure clients notice it.
result = false;
}
if (result)
{
// update PSR link cache on successful LT
this->psrLinkConfig = activeLinkConfig;
}
return result;
}
@@ -5414,11 +5440,8 @@ void ConnectorImpl::freeTimeslice(GroupImpl * targetGroup)
targetGroup->timeslot.hardwareDirty = true;
}
bool ConnectorImpl::allocateTimeslice(GroupImpl * targetGroup)
bool ConnectorImpl::checkIsModePossibleMST(GroupImpl *targetGroup)
{
unsigned base_pbn, slot_count, slots_pbn;
DP_ASSERT(isLinkActive());
if (this->isFECSupported())
{
if (!isModePossibleMSTWithFEC(activeLinkConfig,
@@ -5426,7 +5449,7 @@ bool ConnectorImpl::allocateTimeslice(GroupImpl * targetGroup)
&targetGroup->timeslot.watermarks))
{
DP_ASSERT(0 && "DisplayDriver bug! This mode is not possible at any "
"link configuration. It would have been reject at mode filtering time!");
"link configuration. It should have been rejected at mode filtering time!");
return false;
}
}
@@ -5437,10 +5460,22 @@ bool ConnectorImpl::allocateTimeslice(GroupImpl * targetGroup)
&targetGroup->timeslot.watermarks))
{
DP_ASSERT(0 && "DisplayDriver bug! This mode is not possible at any "
"link configuration. It would have been reject at mode filtering time!");
"link configuration. It should have been rejected at mode filtering time!");
return false;
}
}
return true;
}
bool ConnectorImpl::allocateTimeslice(GroupImpl * targetGroup)
{
unsigned base_pbn, slot_count, slots_pbn;
int firstSlot = firstFreeSlot;
DP_ASSERT(isLinkActive());
if (!checkIsModePossibleMST(targetGroup))
return false;
activeLinkConfig.pbnRequired(targetGroup->lastModesetInfo, base_pbn, slot_count, slots_pbn);
@@ -5448,16 +5483,14 @@ bool ConnectorImpl::allocateTimeslice(GroupImpl * targetGroup)
if (slot_count > freeSlots)
return false;
int firstFreeSlot = 1;
for (ListElement * i = activeGroups.begin(); i != activeGroups.end(); i = i->next)
{
GroupImpl * group = (GroupImpl *)i;
if (group->timeslot.count != 0 &&
(group->timeslot.begin + group->timeslot.count) >= firstFreeSlot)
(group->timeslot.begin + group->timeslot.count) >= firstSlot)
{
firstFreeSlot = group->timeslot.begin + group->timeslot.count;
firstSlot = group->timeslot.begin + group->timeslot.count;
}
}
@@ -5467,7 +5500,7 @@ bool ConnectorImpl::allocateTimeslice(GroupImpl * targetGroup)
DP_ASSERT(!targetGroup->timeslot.count && "Reallocation of stream that is already present");
targetGroup->timeslot.count = slot_count;
targetGroup->timeslot.begin = firstFreeSlot;
targetGroup->timeslot.begin = firstSlot;
targetGroup->timeslot.PBN = base_pbn;
targetGroup->timeslot.hardwareDirty = true;
freeSlots -= slot_count;
@@ -5494,17 +5527,17 @@ void ConnectorImpl::flushTimeslotsToHardware()
}
main->configureMultiStream(group->headIndex,
group->timeslot.watermarks.hBlankSym,
group->timeslot.watermarks.vBlankSym,
group->timeslot.begin,
group->timeslot.begin+group->timeslot.count-1,
group->timeslot.PBN,
activeLinkConfig.PBNForSlots(group->timeslot.count),
group->colorFormat,
group->singleHeadMultiStreamID,
group->singleHeadMultiStreamMode,
bAudioOverRightPanel,
bEnable2Head1Or);
group->timeslot.watermarks.hBlankSym,
group->timeslot.watermarks.vBlankSym,
group->timeslot.begin,
group->timeslot.begin+group->timeslot.count - 1,
group->timeslot.PBN,
activeLinkConfig.PBNForSlots(group->timeslot.count),
group->colorFormat,
group->singleHeadMultiStreamID,
group->singleHeadMultiStreamMode,
bAudioOverRightPanel,
bEnable2Head1Or);
}
}
}
@@ -5577,8 +5610,8 @@ void ConnectorImpl::beforeDeleteStream(GroupImpl * group, bool forFlushMode)
// RG at loadv
//
if (forFlushMode ||
((DP_SINGLE_HEAD_MULTI_STREAM_MODE_MST == group->singleHeadMultiStreamMode) &&
(DP_SINGLE_HEAD_MULTI_STREAM_PIPELINE_ID_PRIMARY != group->singleHeadMultiStreamID)))
((group->singleHeadMultiStreamMode == DP_SINGLE_HEAD_MULTI_STREAM_MODE_MST) &&
(group->singleHeadMultiStreamID != DP_SINGLE_HEAD_MULTI_STREAM_PIPELINE_ID_PRIMARY)))
{
main->controlRateGoverning(group->headIndex, true/*enable*/, forFlushMode /*Immediate/loadv*/);
}
@@ -6140,7 +6173,17 @@ void ConnectorImpl::notifyLongPulseInternal(bool statusConnected)
//
// Shutdown the old message manager if there was one
// If there is a previous stale messageManager or discoveryManager
// present then there is a chance on certain docks where MSTM bits
// needs to be cleared as previous transactions might still be in
// flight. Just checking IRQ VECTOR field might not be enough to
// check for stale messages.
// Please see bug 3928070/4066192
//
if (discoveryManager || messageManager)
{
bForceClearPendingMsg = true;
}
delete discoveryManager;
isDiscoveryDetectComplete = false;
bIsDiscoveryDetectActive = true;
@@ -6180,7 +6223,7 @@ void ConnectorImpl::notifyLongPulseInternal(bool statusConnected)
discoveryManager = new DiscoveryManager(messageManager, this, timer, hal);
// Check and clear if any pending message here
if (hal->clearPendingMsg())
if (hal->clearPendingMsg() || bForceClearPendingMsg)
{
DP_LOG(("DP> Stale MSG found: set branch to D3 and back to D0..."));
if (hal->isAtLeastVersion(1, 4))
@@ -6423,7 +6466,9 @@ void ConnectorImpl::notifyLongPulseInternal(bool statusConnected)
}
completed:
previousPlugged = statusConnected;
fireEvents();
{
fireEvents();
}
if (!statusConnected)
{
@@ -6939,7 +6984,7 @@ void ConnectorImpl::createFakeMuxDevice(const NvU8 *buffer, NvU32 bufferSize)
return;
// Return immediately if DSC is not supported
if(FLD_TEST_DRF(_DPCD14, _DSC_SUPPORT, _DSC_SUPPORT, _YES, buffer[0]) != 1)
if(FLD_TEST_DRF(_DPCD14, _DSC_SUPPORT, _DECOMPRESSION, _YES, buffer[0]) != 1)
return;
DeviceImpl * existingDev = findDeviceInList(Address());
@@ -7241,31 +7286,45 @@ bool ConnectorImpl::readPsrEvtIndicator(vesaPsrEventIndicator *psrEvt)
return hal->readPsrEvtIndicator(psrEvt);
}
bool ConnectorImpl::updatePsrLinkState(bool bTrainLink)
bool ConnectorImpl::updatePsrLinkState(bool bTurnOnLink)
{
bool bRet = true;
if (bTrainLink)
{
// Bug 3438892 If the panel is turned off the reciever on its side,
// force panel link on by writting 600 = 1
this->hal->setDirtyLinkStatus(true);
if (this->isLinkLost())
{
hal->setPowerState(PowerStateD0);
return false;
}
bool bEnteredFlushMode = false;
// Check if Link config is valid
if (!this->psrLinkConfig.isValid())
if (bTurnOnLink)
{
hal->setPowerState(PowerStateD0);
if (isLinkLost())
{
return false;
if (!this->psrLinkConfig.isValid())
{
DP_ASSERT(0 && "Invalid PSR link config");
return false;
}
// NOTE: always verify changes to below line with 2H1OR case
if (!(bEnteredFlushMode = this->enableFlush()))
{
DP_ASSERT(0 && "Flush fails");
}
bRet = this->train(this->psrLinkConfig, false);
if (bEnteredFlushMode)
{
this->disableFlush(true);
}
}
else
{
// return early if link is already up
return true;
}
// Restore Link config/do Link Train
bRet = setPreferredLinkConfig(this->psrLinkConfig, false, true, NORMAL_LINK_TRAINING);
}
else
{
// Save the link config
// Save the current link config
this->psrLinkConfig = getActiveLinkConfig();
}
return bRet;
@@ -7417,5 +7476,6 @@ void ConnectorImpl::configInit()
bNoFallbackInPostLQA = 0;
LT2FecLatencyMs = 0;
bDscCapBasedOnParent = false;
bForceClearPendingMsg = false;
}

34
src/common/displayport/src/dp_deviceimpl.cpp
View File

@@ -1564,11 +1564,11 @@ NvBool DeviceImpl::getDSCSupport()
if(AuxBus::success == this->getDpcdData(NV_DPCD14_DSC_SUPPORT,
&byte, sizeof(byte), &size, &nakReason))
{
if (FLD_TEST_DRF(_DPCD14, _DSC_SUPPORT, _DSC_SUPPORT, _YES, byte))
if (FLD_TEST_DRF(_DPCD14, _DSC_SUPPORT, _DECOMPRESSION, _YES, byte))
{
dscCaps.bDSCDecompressionSupported = true;
}
if (FLD_TEST_DRF(_DPCD20, _DSC_SUPPORT, _PASS_THROUGH_SUPPORT, _YES, byte))
if (FLD_TEST_DRF(_DPCD20, _DSC_SUPPORT, _PASS_THROUGH, _YES, byte))
{
dscCaps.bDSCPassThroughSupported = true;
}
@@ -1712,6 +1712,16 @@ NvBool DeviceImpl::isDSCPassThroughSupported()
return dscCaps.bDSCPassThroughSupported;
}
NvBool DeviceImpl::isDynamicPPSSupported()
{
return dscCaps.bDynamicPPSSupported;
}
NvBool DeviceImpl::isDynamicDscToggleSupported()
{
return dscCaps.bDynamicDscToggleSupported;
}
NvBool DeviceImpl::isDSCPossible()
{
return this->bDSCPossible;
@@ -1731,11 +1741,21 @@ bool DeviceImpl::parseDscCaps(const NvU8 *buffer, NvU32 bufferSize)
return false;
}
if (FLD_TEST_DRF(_DPCD20, _DSC_SUPPORT, _PASS_THROUGH_SUPPORT, _YES, buffer[0x0]))
if (FLD_TEST_DRF(_DPCD20, _DSC_SUPPORT, _PASS_THROUGH, _YES, buffer[0x0]))
{
dscCaps.bDSCPassThroughSupported = true;
}
if (FLD_TEST_DRF(_DPCD20, _DSC_SUPPORT, _DYNAMIC_PPS_COMPRESSED_TO_COMPRESSED, _YES, buffer[0x0]))
{
dscCaps.bDynamicPPSSupported = true;
}
if (FLD_TEST_DRF(_DPCD20, _DSC_SUPPORT, _DYNAMIC_PPS_UNCOMPRESSED_TO_FROM_COMPRESSED, _YES, buffer[0x0]))
{
dscCaps.bDynamicDscToggleSupported = true;
}
dscCaps.versionMajor = DRF_VAL(_DPCD14, _DSC_ALGORITHM_REVISION, _MAJOR, buffer[0x1]);
dscCaps.versionMinor = DRF_VAL(_DPCD14, _DSC_ALGORITHM_REVISION, _MINOR, buffer[0x1]);
@@ -1987,7 +2007,7 @@ bool DeviceImpl::getDscEnable(bool *pEnable)
return false;
}
*pEnable = FLD_TEST_DRF(_DPCD14, _DSC_ENABLE, _SINK, _YES, byte);
*pEnable = FLD_TEST_DRF(_DPCD14, _DSC_ENABLE, _DECOMPRESSION, _YES, byte);
return true;
}
@@ -2145,7 +2165,7 @@ bool DeviceImpl::setDscEnable(bool enable)
if (!bCurrDscEnable)
{
dscEnableByte = FLD_SET_DRF(_DPCD14, _DSC_ENABLE, _SINK, _YES, dscEnableByte);
dscEnableByte = FLD_SET_DRF(_DPCD14, _DSC_ENABLE, _DECOMPRESSION, _YES, dscEnableByte);
DP_LOG(("DP-DEV> Enabling DSC decompression on device - %s",
this->devDoingDscDecompression->getTopologyAddress().toString(buffer)));
}
@@ -2166,7 +2186,7 @@ bool DeviceImpl::setDscEnable(bool enable)
if (bCurrDscEnable)
{
dscEnableByte = FLD_SET_DRF(_DPCD14, _DSC_ENABLE, _SINK, _NO, dscEnableByte);
dscEnableByte = FLD_SET_DRF(_DPCD14, _DSC_ENABLE, _DECOMPRESSION, _NO, dscEnableByte);
DP_LOG(("DP-DEV> Disabling DSC decompression on device - %s",
this->devDoingDscDecompression->getTopologyAddress().toString(buffer)));
}
@@ -2237,7 +2257,7 @@ bool DeviceImpl::setDscEnableDPToHDMIPCON(bool bDscEnable, bool bEnablePassThrou
}
else
{
dscEnableByte = FLD_SET_DRF(_DPCD14, _DSC_ENABLE, _SINK, _YES, dscEnableByte);
dscEnableByte = FLD_SET_DRF(_DPCD14, _DSC_ENABLE, _DECOMPRESSION, _YES, dscEnableByte);
DP_LOG(("DP-DEV> Enabling DSC decompression on DP to HDMI PCON device - %s",
this->getTopologyAddress().toString(buffer)));
}

128
src/common/displayport/src/dp_evoadapter.cpp
View File

@@ -35,8 +35,6 @@
#include "dp_vrr.h"
#include <nvmisc.h>
#include <ctrl/ctrl0073/ctrl0073dfp.h>
#include <ctrl/ctrl0073/ctrl0073dp.h>
#include <ctrl/ctrl0073/ctrl0073specific.h>
#include <ctrl/ctrl0073/ctrl0073system.h>
#include <ctrl/ctrl5070/ctrl5070or.h>
@@ -95,7 +93,8 @@ const struct
{NV_DP_REGKEY_FORCE_EDP_ILR, &dpRegkeyDatabase.bBypassEDPRevCheck, DP_REG_VAL_BOOL},
{NV_DP_DSC_MST_CAP_BUG_3143315, &dpRegkeyDatabase.bDscMstCapBug3143315, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_POWER_DOWN_PHY, &dpRegkeyDatabase.bPowerDownPhyBeforeD3, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_REASSESS_MAX_LINK, &dpRegkeyDatabase.bReassessMaxLink, DP_REG_VAL_BOOL}
{NV_DP_REGKEY_REASSESS_MAX_LINK, &dpRegkeyDatabase.bReassessMaxLink, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_MST_PCON_CAPS_READ_DISABLED, &dpRegkeyDatabase.bMSTPCONCapsReadDisabled, DP_REG_VAL_BOOL}
};
EvoMainLink::EvoMainLink(EvoInterface * provider, Timer * timer) :
@@ -113,10 +112,12 @@ EvoMainLink::EvoMainLink(EvoInterface * provider, Timer * timer) :
this->initializeRegkeyDatabase();
this->applyRegkeyOverrides();
_isDynamicMuxCapable = false;
_isLTPhyRepeaterSupported = true;
_rmPhyRepeaterCount = 0;
dpMemZero(&_DSC, sizeof(_DSC));
_isDynamicMuxCapable = false;
_isLTPhyRepeaterSupported = true;
_rmPhyRepeaterCount = 0;
dpMemZero(&_DSC, sizeof(_DSC));
dpMemZero(&dfpParams, sizeof(dfpParams));
dpMemZero(&dpParams, sizeof(dpParams));
//
// Tell RM to hands off on the DisplayPort hardware
@@ -257,63 +258,60 @@ NvU32 EvoMainLink::headToStream(NvU32 head, DP_SINGLE_HEAD_MULTI_STREAM_PIPELINE
return streamIndex;
}
void EvoMainLink::queryGPUCapability()
bool EvoMainLink::queryGPUCapability()
{
NV0073_CTRL_CMD_DP_GET_CAPS_PARAMS params;
dpMemZero(&params, sizeof(params));
params.subDeviceInstance = subdeviceIndex;
params.sorIndex = provider->getSorIndex();
NvU32 code = provider->rmControl0073(NV0073_CTRL_CMD_DP_GET_CAPS, &params, sizeof(params));
dpMemZero(&dpParams, sizeof(dpParams));
dpParams.subDeviceInstance = subdeviceIndex;
dpParams.sorIndex = provider->getSorIndex();
NvU32 code = provider->rmControl0073(NV0073_CTRL_CMD_DP_GET_CAPS, &dpParams, sizeof(dpParams));
if (code != NVOS_STATUS_SUCCESS)
{
DP_ASSERT(0 && "Unable to process GPU caps");
return false;
}
//
// Check if MST feature needs to be disabled by regkey. This is requirement by few OEMs, they don't want to support
// MST feature on particular sku, whenever requested through INF.
//
_hasMultistream = (dpParams.bIsMultistreamSupported == NV_TRUE) && !_isMstDisabledByRegkey;
_gpuSupportedDpVersions = dpParams.dpVersionsSupported;
_isStreamCloningEnabled = (dpParams.bIsSCEnabled == NV_TRUE) ? true : false;
_hasIncreasedWatermarkLimits = (dpParams.bHasIncreasedWatermarkLimits == NV_TRUE) ? true : false;
_isFECSupported = (dpParams.bFECSupported == NV_TRUE) ? true : false;
_useDfpMaxLinkRateCaps = (dpParams.bOverrideLinkBw == NV_TRUE) ? true : false;
_isLTPhyRepeaterSupported = (dpParams.bIsTrainPhyRepeater == NV_TRUE) ? true : false;
if (FLD_TEST_DRF(0073, _CTRL_CMD_DP_GET_CAPS, _MAX_LINK_RATE, _1_62, dpParams.maxLinkRate))
_maxLinkRateSupportedGpu = RBR; //in Hz
else if (FLD_TEST_DRF(0073, _CTRL_CMD_DP_GET_CAPS, _MAX_LINK_RATE, _2_70, dpParams.maxLinkRate))
_maxLinkRateSupportedGpu = HBR; //in Hz
else if (FLD_TEST_DRF(0073, _CTRL_CMD_DP_GET_CAPS, _MAX_LINK_RATE, _5_40, dpParams.maxLinkRate))
_maxLinkRateSupportedGpu = HBR2; //in Hz
else if (FLD_TEST_DRF(0073, _CTRL_CMD_DP_GET_CAPS, _MAX_LINK_RATE, _8_10, dpParams.maxLinkRate))
_maxLinkRateSupportedGpu = HBR3; //in Hz
else
{
//
// Check if MST feature needs to be disabled by regkey. This is requirement by few OEMs, they don't want to support
// MST feature on particular sku, whenever requested through INF.
//
_hasMultistream = (params.bIsMultistreamSupported == NV_TRUE) && !_isMstDisabledByRegkey;
_gpuSupportedDpVersions = params.dpVersionsSupported;
_isStreamCloningEnabled = (params.bIsSCEnabled == NV_TRUE) ? true : false;
_hasIncreasedWatermarkLimits = (params.bHasIncreasedWatermarkLimits == NV_TRUE) ? true : false;
_isFECSupported = (params.bFECSupported == NV_TRUE) ? true : false;
_useDfpMaxLinkRateCaps = (params.bOverrideLinkBw == NV_TRUE) ? true : false;
_isLTPhyRepeaterSupported = (params.bIsTrainPhyRepeater == NV_TRUE) ? true : false;
if (FLD_TEST_DRF(0073, _CTRL_CMD_DP_GET_CAPS, _MAX_LINK_RATE, _1_62, params.maxLinkRate))
_maxLinkRateSupportedGpu = RBR; //in Hz
else if (FLD_TEST_DRF(0073, _CTRL_CMD_DP_GET_CAPS, _MAX_LINK_RATE, _2_70, params.maxLinkRate))
_maxLinkRateSupportedGpu = HBR; //in Hz
else if (FLD_TEST_DRF(0073, _CTRL_CMD_DP_GET_CAPS, _MAX_LINK_RATE, _5_40, params.maxLinkRate))
_maxLinkRateSupportedGpu = HBR2; //in Hz
else if (FLD_TEST_DRF(0073, _CTRL_CMD_DP_GET_CAPS, _MAX_LINK_RATE, _8_10, params.maxLinkRate))
_maxLinkRateSupportedGpu = HBR3; //in Hz
else
{
DP_ASSERT(0 && "Unable to get max link rate");
// Assume that we can at least support RBR.
_maxLinkRateSupportedGpu = RBR;
}
if (!_isDscDisabledByRegkey)
{
_DSC.isDscSupported = params.DSC.bDscSupported ? true : false;
_DSC.encoderColorFormatMask = params.DSC.encoderColorFormatMask;
_DSC.lineBufferSizeKB = params.DSC.lineBufferSizeKB;
_DSC.rateBufferSizeKB = params.DSC.rateBufferSizeKB;
_DSC.bitsPerPixelPrecision = params.DSC.bitsPerPixelPrecision;
_DSC.maxNumHztSlices = params.DSC.maxNumHztSlices;
_DSC.lineBufferBitDepth = params.DSC.lineBufferBitDepth;
}
DP_ASSERT(0 && "Unable to get max link rate");
// Assume that we can at least support RBR.
_maxLinkRateSupportedGpu = RBR;
}
if (!_isDscDisabledByRegkey)
{
_DSC.isDscSupported = dpParams.DSC.bDscSupported ? true : false;
_DSC.encoderColorFormatMask = dpParams.DSC.encoderColorFormatMask;
_DSC.lineBufferSizeKB = dpParams.DSC.lineBufferSizeKB;
_DSC.rateBufferSizeKB = dpParams.DSC.rateBufferSizeKB;
_DSC.bitsPerPixelPrecision = dpParams.DSC.bitsPerPixelPrecision;
_DSC.maxNumHztSlices = dpParams.DSC.maxNumHztSlices;
_DSC.lineBufferBitDepth = dpParams.DSC.lineBufferBitDepth;
}
return true;
}
void EvoMainLink::triggerACT()
@@ -643,18 +641,18 @@ bool EvoMainLink::physicalLayerSetTestPattern(PatternInfo * patternInfo)
{
ctrlPattern.testPattern = NV0073_CTRL_DP_TESTPATTERN_DATA_CSTM;
params.cstm.lower = patternInfo->ctsmLower;
params.cstm.middle = patternInfo->ctsmMiddle;
params.cstm.upper = patternInfo->ctsmUpper;
params.cstm.field_31_0 = patternInfo->ctsmLower;
params.cstm.field_63_32 = patternInfo->ctsmMiddle;
params.cstm.field_95_64 = patternInfo->ctsmUpper;
break;
}
#ifdef NV0073_CTRL_DP_TESTPATTERN_DATA_HBR2COMPLIANCE
case LINK_QUAL_HBR2_COMPLIANCE_EYE:
{
ctrlPattern.testPattern = NV0073_CTRL_DP_TESTPATTERN_DATA_HBR2COMPLIANCE;
params.cstm.lower = 0;
params.cstm.middle = 0;
params.cstm.upper = 0;
params.cstm.field_31_0 = 0;
params.cstm.field_63_32 = 0;
params.cstm.field_95_64 = 0;
break;
}
#endif
@@ -893,6 +891,7 @@ void EvoMainLink::applyRegkeyOverrides()
_skipPowerdownEDPPanelWhenHeadDetach = dpRegkeyDatabase.bPoweroffEdpInHeadDetachSkipped;
_applyLinkBwOverrideWarRegVal = dpRegkeyDatabase.bLinkBwOverrideWarApplied;
_enableMSAOverrideOverMST = dpRegkeyDatabase.bMsaOverMstEnabled;
_isMSTPCONCapsReadDisabled = dpRegkeyDatabase.bMSTPCONCapsReadDisabled;
}
NvU32 EvoMainLink::getRegkeyValue(const char *key)
@@ -1373,7 +1372,6 @@ bool EvoMainLink::getMaxLinkConfigFromUefi(NvU8 &linkRate, NvU8 &laneCount)
bool EvoMainLink::queryAndUpdateDfpParams()
{
NV0073_CTRL_DFP_GET_INFO_PARAMS dfpParams;
NvU32 dfpFlags;
dpMemZero(&dfpParams, sizeof(dfpParams));
dfpParams.subDeviceInstance = subdeviceIndex;
@@ -1516,6 +1514,10 @@ bool EvoMainLink::skipPowerdownEdpPanelWhenHeadDetach()
return _skipPowerdownEDPPanelWhenHeadDetach;
}
bool EvoMainLink::isMSTPCONCapsReadDisabled()
{
return _isMSTPCONCapsReadDisabled;
}
bool EvoMainLink::isActive()
{

2
src/common/displayport/src/dp_wardatabase.cpp
View File

@@ -561,7 +561,7 @@ void Edid::applyEdidWorkArounds(NvU32 warFlag, const DpMonitorDenylistData *pDen
// NCP
case 0x7038:
if ((ProductID == 0x005F))
if (ProductID == 0x005F)
{
this->WARFlags.bIgnoreDscCap = true;
DP_LOG(("DP-WAR> NCP panels incorrectly exposing DSC capability. Ignoring it."));

5
src/common/inc/displayport/displayport.h
View File

@@ -23,6 +23,7 @@
#ifndef _DISPLAYPORT_H_
#define _DISPLAYPORT_H_
#include "nvcfg_sdk.h"
#include "nvmisc.h"
#include "dpcd.h"
@@ -161,7 +162,7 @@ typedef enum
trainingPattern_1 = 0x1,
trainingPattern_2 = 0x2,
trainingPattern_3 = 0x3,
trainingPattern_4 = 0xB
trainingPattern_4 = 0xB,
} DP_TRAININGPATTERN;
typedef enum
@@ -245,6 +246,8 @@ typedef struct DscCaps
{
NvBool bDSCSupported;
NvBool bDSCDecompressionSupported;
NvBool bDynamicPPSSupported;
NvBool bDynamicDscToggleSupported;
NvBool bDSCPassThroughSupported;
unsigned versionMajor, versionMinor;
unsigned rcBufferBlockSize;

8
src/common/inc/displayport/dpcd.h
View File

@@ -697,6 +697,14 @@ number of Downstream ports will be limited to 32.
#define NV_DPCD_ADJUST_REQ_POST_CURSOR2_LANE6 5:4 /* R-XUF */
#define NV_DPCD_ADJUST_REQ_POST_CURSOR2_LANE7 7:6 /* R-XUF */
#define NV_DPCD_EDP_LINK_CONFIG_STATUS (0x0000020c) /* RWXUR */
#define NV_DPCD_EDP_LINK_CONFIG_STATUS_SET 0:0 /* R-XUF */
#define NV_DPCD_EDP_LINK_CONFIG_STATUS_SET_LINK_BW (0x00000000) /* R-XUV */
#define NV_DPCD_EDP_LINK_CONFIG_STATUS_SET_LINK_RATE (0x00000001) /* R-XUV */
#define NV_DPCD_EDP_LINK_CONFIG_STATUS_VALID 1:1 /* R-XUF */
#define NV_DPCD_EDP_LINK_CONFIG_STATUS_VALID_NO (0x00000000) /* R-XUV */
#define NV_DPCD_EDP_LINK_CONFIG_STATUS_VALID_YES (0x00000001) /* R-XUV */
// 0020Fh: RESERVED. Read all 0s
#define NV_DPCD_SYMBOL_ERROR_COUNT_LANEX_BYTE0(i) (0x00000210+(i)*2) /* R--1A */

96
src/common/inc/displayport/dpcd14.h
View File

@@ -43,9 +43,9 @@
#define NV_DPCD14_TRAINING_AUX_RD_INTERVAL_EXTENDED_RX_CAP_YES (0x00000001) /* R-XUV */
#define NV_DPCD14_DSC_SUPPORT (0x00000060) /* R-XUR */
#define NV_DPCD14_DSC_SUPPORT_DSC_SUPPORT 0:0 /* R-XUF */
#define NV_DPCD14_DSC_SUPPORT_DSC_SUPPORT_NO (0x00000000) /* R-XUV */
#define NV_DPCD14_DSC_SUPPORT_DSC_SUPPORT_YES (0x00000001) /* R-XUV */
#define NV_DPCD14_DSC_SUPPORT_DECOMPRESSION 0:0 /* R-XUF */
#define NV_DPCD14_DSC_SUPPORT_DECOMPRESSION_NO (0x00000000) /* R-XUV */
#define NV_DPCD14_DSC_SUPPORT_DECOMPRESSION_YES (0x00000001) /* R-XUV */
#define NV_DPCD14_DSC_ALGORITHM_REVISION (0x00000061) /* R-XUR */
#define NV_DPCD14_DSC_ALGORITHM_REVISION_MAJOR 3:0 /* R-XUF */
@@ -190,9 +190,9 @@
#define NV_DPCD14_DSC_BITS_PER_PIXEL_INCREMENT_SUPPORTED_1 (0x00000004) /* R-XUV */
#define NV_DPCD14_DSC_ENABLE (0x00000160) /* R-XUR */
#define NV_DPCD14_DSC_ENABLE_SINK 0:0 /* R-XUF */
#define NV_DPCD14_DSC_ENABLE_SINK_NO (0x00000000) /* R-XUV */
#define NV_DPCD14_DSC_ENABLE_SINK_YES (0x00000001) /* R-XUV */
#define NV_DPCD14_DSC_ENABLE_DECOMPRESSION 0:0 /* R-XUF */
#define NV_DPCD14_DSC_ENABLE_DECOMPRESSION_NO (0x00000000) /* R-XUV */
#define NV_DPCD14_DSC_ENABLE_DECOMPRESSION_YES (0x00000001) /* R-XUV */
#define NV_DPCD14_FEC_CAPABILITY (0x00000090) /* R-XUR */
#define NV_DPCD14_FEC_CAPABILITY_FEC_CAPABLE 0:0 /* R-XUF */
@@ -213,7 +213,9 @@
#define NV_DPCD14_FEC_CAPABILITY_PARITY_ERROR_COUNT_CAPABLE 5:5 /* R-XUF */
#define NV_DPCD14_FEC_CAPABILITY_PARITY_ERROR_COUNT_CAPABLE_NO (0x00000000) /* R-XUV */
#define NV_DPCD14_FEC_CAPABILITY_PARITY_ERROR_COUNT_CAPABLE_YES (0x00000001) /* R-XUV */
// Bit 6 : RESERVED. Read 0
#define NV_DPCD14_FEC_CAPABILITY_FEC_RUNNING_INDICATOR_SUPPORT 6:6 /* R-XUF */
#define NV_DPCD14_FEC_CAPABILITY_FEC_RUNNING_INDICATOR_SUPPORT_NO (0x00000000) /* R-XUV */
#define NV_DPCD14_FEC_CAPABILITY_FEC_RUNNING_INDICATOR_SUPPORT_YES (0x00000001) /* R-XUV */
#define NV_DPCD14_FEC_CAPABILITY_FEC_ERROR_REPORTING_POLICY_SUPPORTED 7:7 /* R-XUF */
#define NV_DPCD14_FEC_CAPABILITY_FEC_ERROR_REPORTING_POLICY_SUPPORTED_NO (0x00000000) /* R-XUV */
#define NV_DPCD14_FEC_CAPABILITY_FEC_ERROR_REPORTING_POLICY_SUPPORTED_YES (0x00000001) /* R-XUV */
@@ -629,36 +631,6 @@
#define NV_DPCD14_PHY_REPEATER_EXTENDED_WAKE_TIMEOUT_REQ 6:0 /* R-XUF */
#define NV_DPCD14_PHY_REPEATER_EXTENDED_WAKE_TIMEOUT_GRANT 7:7 /* RWXUF */
#define NV_DPCD14_PHY_REPEATER_EQ_DONE (0x000F0008) /* R-XUR */
#define NV_DPCD14_PHY_REPEATER_EQ_DONE_LTTPR(i) (i):(i) /* R-XUF */
#define NV_DPCD14_PHY_REPEATER_EQ_DONE_LTTPR_NO (0x00000000) /* R-XUF */
#define NV_DPCD14_PHY_REPEATER_EQ_DONE_LTTPR_YES (0x00000001) /* R-XUF */
#define NV_DPCD14_PHY_REPEATER_EQ_DONE_LTTPR_0 0:0 /* R-XUF */
#define NV_DPCD14_PHY_REPEATER_EQ_DONE_LTTPR_0_NO (0x00000000) /* R-XUF */
#define NV_DPCD14_PHY_REPEATER_EQ_DONE_LTTPR_0_YES (0x00000001) /* R-XUF */
#define NV_DPCD14_PHY_REPEATER_EQ_DONE_LTTPR_1 1:1 /* R-XUF */
#define NV_DPCD14_PHY_REPEATER_EQ_DONE_LTTPR_1_NO (0x00000000) /* R-XUF */
#define NV_DPCD14_PHY_REPEATER_EQ_DONE_LTTPR_1_YES (0x00000001) /* R-XUF */
#define NV_DPCD14_PHY_REPEATER_EQ_DONE_LTTPR_2 2:2 /* R-XUF */
#define NV_DPCD14_PHY_REPEATER_EQ_DONE_LTTPR_2_NO (0x00000000) /* R-XUF */
#define NV_DPCD14_PHY_REPEATER_EQ_DONE_LTTPR_2_YES (0x00000001) /* R-XUF */
#define NV_DPCD14_PHY_REPEATER_EQ_DONE_LTTPR_3 3:3 /* R-XUF */
#define NV_DPCD14_PHY_REPEATER_EQ_DONE_LTTPR_3_NO (0x00000000) /* R-XUF */
#define NV_DPCD14_PHY_REPEATER_EQ_DONE_LTTPR_3_YES (0x00000001) /* R-XUF */
#define NV_DPCD14_PHY_REPEATER_EQ_DONE_LTTPR_4 4:4 /* R-XUF */
#define NV_DPCD14_PHY_REPEATER_EQ_DONE_LTTPR_4_NO (0x00000000) /* R-XUF */
#define NV_DPCD14_PHY_REPEATER_EQ_DONE_LTTPR_4_YES (0x00000001) /* R-XUF */
#define NV_DPCD14_PHY_REPEATER_EQ_DONE_LTTPR_5 5:5 /* R-XUF */
#define NV_DPCD14_PHY_REPEATER_EQ_DONE_LTTPR_5_NO (0x00000000) /* R-XUF */
#define NV_DPCD14_PHY_REPEATER_EQ_DONE_LTTPR_5_YES (0x00000001) /* R-XUF */
#define NV_DPCD14_PHY_REPEATER_EQ_DONE_LTTPR_6 6:6 /* R-XUF */
#define NV_DPCD14_PHY_REPEATER_EQ_DONE_LTTPR_6_NO (0x00000000) /* R-XUF */
#define NV_DPCD14_PHY_REPEATER_EQ_DONE_LTTPR_6_YES (0x00000001) /* R-XUF */
#define NV_DPCD14_PHY_REPEATER_EQ_DONE_LTTPR_7 7:7 /* R-XUF */
#define NV_DPCD14_PHY_REPEATER_EQ_DONE_LTTPR_7_NO (0x00000000) /* R-XUF */
#define NV_DPCD14_PHY_REPEATER_EQ_DONE_LTTPR_7_YES (0x00000001) /* R-XUF */
#define NV_DPCD14_PHY_REPEATER_START(i) (0x000F0010+(i)*0x50) /* RW-1A */
#define NV_DPCD14_PHY_REPEATER_START__SIZE 8 /* R---S */
// Following defines are offsets
@@ -689,6 +661,56 @@
#define NV_DPCD14_ADJUST_REQUEST_LANE0_1_PHY_REPEATER (0x00000023) /* R-XUR */
#define NV_DPCD14_ADJUST_REQUEST_LANE2_3_PHY_REPEATER (0x00000024) /* R-XUR */
#define NV_DPCD14_PHY_REPEATER_FEC__SIZE NV_DPCD14_PHY_REPEATER_CNT_MAX /* R---S */
#define NV_DPCD14_PHY_REPEATER_FEC_STATUS(i) (0x000F0290+(i)*8) /* R--1A */
#define NV_DPCD14_PHY_REPEATER_FEC_STATUS_FEC_DECODE_EN_DETECTED 0:0 /* R-XUF */
#define NV_DPCD14_PHY_REPEATER_FEC_STATUS_FEC_DECODE_EN_DETECTED_NO (0x00000000) /* R-XUV */
#define NV_DPCD14_PHY_REPEATER_FEC_STATUS_FEC_DECODE_EN_DETECTED_YES (0x00000001) /* R-XUV */
#define NV_DPCD14_PHY_REPEATER_FEC_STATUS_FEC_DECODE_DIS_DETECTED 1:1 /* R-XUF */
#define NV_DPCD14_PHY_REPEATER_FEC_STATUS_FEC_DECODE_DIS_DETECTED_NO (0x00000000) /* R-XUV */
#define NV_DPCD14_PHY_REPEATER_FEC_STATUS_FEC_DECODE_DIS_DETECTED_YES (0x00000001) /* R-XUV */
#define NV_DPCD14_PHY_REPEATER_FEC_STATUS_FEC_RUNNING_INDICATOR 2:2 /* R-XUF */
#define NV_DPCD14_PHY_REPEATER_FEC_STATUS_FEC_RUNNING_INDICATOR_NO (0x00000000) /* R-XUV */
#define NV_DPCD14_PHY_REPEATER_FEC_STATUS_FEC_RUNNING_INDICATOR_YES (0x00000001) /* R-XUV */
#define NV_DPCD14_PHY_REPEATER_FEC_ERR_COUNT(i) (0x000F0291+(i)*8) /* R--2A */
#define NV_DPCD14_PHY_REPEATER_FEC_ERR_COUNT_LOW_BYTE(i) (NV_DPCD14_PHY_REPEATER_FEC_ERR_COUNT(i))
#define NV_DPCD14_PHY_REPEATER_FEC_ERR_COUNT_HIGH_BYTE(i) ((0x000F0292+(i)*8)) /* R-XUR */
#define NV_DPCD14_PHY_REPEATER_FEC_ERR_COUNT_VALID 7:7 /* R-XUF */
#define NV_DPCD14_PHY_REPEATER_FEC_ERR_COUNT_VALID_NO (0x00000000) /* R-XUV */
#define NV_DPCD14_PHY_REPEATER_FEC_ERR_COUNT_VALID_YES (0x00000001) /* R-XUV */
#define NV_DPCD14_PHY_REPEATER_FEC_CAP_0(i) (0x000F0294+(i)*8) /* R--1A */
#define NV_DPCD14_PHY_REPEATER_FEC_CAP_0_FEC_CAPABLE 0:0 /* R-XUF */
#define NV_DPCD14_PHY_REPEATER_FEC_CAP_0_FEC_CAPABLE_NO (0x00000000) /* R-XUV */
#define NV_DPCD14_PHY_REPEATER_FEC_CAP_0_FEC_CAPABLE_YES (0x00000001) /* R-XUV */
#define NV_DPCD14_PHY_REPEATER_FEC_CAP_0_UNCORRECTED_BLOCK_ERROR_COUNT_CAPABLE 1:1 /* R-XUF */
#define NV_DPCD14_PHY_REPEATER_FEC_CAP_0_UNCORRECTED_BLOCK_ERROR_COUNT_CAPABLE_NO (0x00000000) /* R-XUV */
#define NV_DPCD14_PHY_REPEATER_FEC_CAP_0_UNCORRECTED_BLOCK_ERROR_COUNT_CAPABLE_YES (0x00000001) /* R-XUV */
#define NV_DPCD14_PHY_REPEATER_FEC_CAP_0_CORRECTED_BLOCK_ERROR_COUNT_CAPABLE 2:2 /* R-XUF */
#define NV_DPCD14_PHY_REPEATER_FEC_CAP_0CORRECTED_BLOCK_ERROR_COUNT_CAPABLE_NO (0x00000000) /* R-XUV */
#define NV_DPCD14_PHY_REPEATER_FEC_CAP_0_CORRECTED_BLOCK_ERROR_COUNT_CAPABLE_YES (0x00000001) /* R-XUV */
#define NV_DPCD14_PHY_REPEATER_FEC_CAP_0_BIT_ERROR_COUNT_CAPABLE 3:3 /* R-XUF */
#define NV_DPCD14_PHY_REPEATER_FEC_CAP_0_BIT_ERROR_COUNT_CAPABLE_NO (0x00000000) /* R-XUV */
#define NV_DPCD14_PHY_REPEATER_FEC_CAP_0_BIT_ERROR_COUNT_CAPABLE_YES (0x00000001) /* R-XUV */
#define NV_DPCD14_PHY_REPEATER_FEC_CAP_0_PARITY_BLOCK_ERROR_COUNT_CAPABLE 4:4 /* R-XUF */
#define NV_DPCD14_PHY_REPEATER_FEC_CAP_0_PARITY_BLOCK_ERROR_COUNT_CAPABLE_NO (0x00000000) /* R-XUV */
#define NV_DPCD14_PHY_REPEATER_FEC_CAP_0_PARITY_BLOCK_ERROR_COUNT_CAPABLE_YES (0x00000001) /* R-XUV */
#define NV_DPCD14_PHY_REPEATER_FEC_CAP_0_PARITY_ERROR_COUNT_CAPABLE 5:5 /* R-XUF */
#define NV_DPCD14_PHY_REPEATER_FEC_CAP_0_PARITY_ERROR_COUNT_CAPABLE_NO (0x00000000) /* R-XUV */
#define NV_DPCD14_PHY_REPEATER_FEC_CAP_0_PARITY_ERROR_COUNT_CAPABLE_YES (0x00000001) /* R-XUV */
#define NV_DPCD14_PHY_REPEATER_FEC_CAP_0_FEC_RUNNING_INDICATOR_SUPPORT 6:6 /* R-XUF */
#define NV_DPCD14_PHY_REPEATER_FEC_CAP_0_FEC_RUNNING_INDICATOR_SUPPORT_NO (0x00000000) /* R-XUV */
#define NV_DPCD14_PHY_REPEATER_FEC_CAP_0_FEC_RUNNING_INDICATOR_SUPPORT_YES (0x00000001) /* R-XUV */
#define NV_DPCD14_PHY_REPEATER_FEC_CAP_0_FEC_ERROR_REPORTING_POLICY_SUPPORTED 7:7 /* R-XUF */
#define NV_DPCD14_PHY_REPEATER_FEC_CAP_0_FEC_ERROR_REPORTING_POLICY_SUPPORTED_NO (0x00000000) /* R-XUV */
#define NV_DPCD14_PHY_REPEATER_FEC_CAP_0_FEC_ERROR_REPORTING_POLICY_SUPPORTED_YES (0x00000001) /* R-XUV */
#define NV_DPCD14_PHY_REPEATER_FEC_CAP_1(i) (0x000F0295+(i)*8) /* R--1A */
#define NV_DPCD14_PHY_REPEATER_FEC_CAP_1_AGGREGATE_ERR_COUNT_CAPABLE 0:0 /* R-XUF */
#define NV_DPCD14_PHY_REPEATER_FEC_CAP_1_AGGREGATE_ERR_COUNT_CAPABLE_CAPABLE_N (0x00000000) /* R-XUV */
#define NV_DPCD14_PHY_REPEATER_FEC_CAP_1_AGGREGATE_ERR_COUNT_CAPABLE_CAPABLE_YES (0x00000001) /* R-XUV */
// BRANCH SPECIFIC DSC CAPS
#define NV_DPCD14_BRANCH_DSC_OVERALL_THROUGHPUT_MODE_0 (0x000000A0)
#define NV_DPCD14_BRANCH_DSC_OVERALL_THROUGHPUT_MODE_0_VALUE 7:0

16
src/common/inc/displayport/dpcd20.h
View File

@@ -25,14 +25,24 @@
#include "nvcfg_sdk.h"
// DSC Pass Through related DPCD. New bits in DPCD 0x0060h defined in DPCD2.0.
#define NV_DPCD20_DSC_SUPPORT_PASS_THROUGH_SUPPORT 1:1 /* R-XUF */
#define NV_DPCD20_DSC_SUPPORT_PASS_THROUGH_SUPPORT_NO (0x00000000) /* R-XUV */
#define NV_DPCD20_DSC_SUPPORT_PASS_THROUGH_SUPPORT_YES (0x00000001) /* R-XUV */
#define NV_DPCD20_DSC_SUPPORT_PASS_THROUGH 1:1 /* R-XUF */
#define NV_DPCD20_DSC_SUPPORT_PASS_THROUGH_NO (0x00000000) /* R-XUV */
#define NV_DPCD20_DSC_SUPPORT_PASS_THROUGH_YES (0x00000001) /* R-XUV */
// DSC Pass Through related DPCD. New bits in DPCD 0x0160h defined in DPCD2.0.
#define NV_DPCD20_DSC_ENABLE_PASS_THROUGH 1:1 /* R-XUF */
#define NV_DPCD20_DSC_ENABLE_PASS_THROUGH_NO (0x00000000) /* R-XUV */
#define NV_DPCD20_DSC_ENABLE_PASS_THROUGH_YES (0x00000001) /* R-XUV */
// DSC Dynamic PPS related DPCD. New bits in DPCD 0x0060h defined in DPCD2.0.
#define NV_DPCD20_DSC_SUPPORT_DYNAMIC_PPS_COMPRESSED_TO_COMPRESSED 2:2
#define NV_DPCD20_DSC_SUPPORT_DYNAMIC_PPS_COMPRESSED_TO_COMPRESSED_NO (0x00000000)
#define NV_DPCD20_DSC_SUPPORT_DYNAMIC_PPS_COMPRESSED_TO_COMPRESSED_YES (0x00000001)
// DSC Dynamic PPS related DPCD. New bits in DPCD 0x0060h defined in DPCD2.0.
#define NV_DPCD20_DSC_SUPPORT_DYNAMIC_PPS_UNCOMPRESSED_TO_FROM_COMPRESSED 3:3
#define NV_DPCD20_DSC_SUPPORT_DYNAMIC_PPS_UNCOMPRESSED_TO_FROM_COMPRESSED_NO (0x00000000)
#define NV_DPCD20_DSC_SUPPORT_DYNAMIC_PPS_UNCOMPRESSED_TO_FROM_COMPRESSED_YES (0x00000001)
// PANEL REPLAY RELATED DPCD
#define NV_DPCD20_PANEL_REPLAY_CAPABILITY (0x000000B0)
#define NV_DPCD20_PANEL_REPLAY_CAPABILITY_SUPPORTED 0:0

22
src/common/inc/nvBldVer.h
View File

@@ -36,26 +36,26 @@
// and then checked back in. You cannot make changes to these sections without
// corresponding changes to the buildmeister script
#ifndef NV_BUILD_BRANCH
#define NV_BUILD_BRANCH r545_96
#define NV_BUILD_BRANCH r551_06
#endif
#ifndef NV_PUBLIC_BRANCH
#define NV_PUBLIC_BRANCH r545_96
#define NV_PUBLIC_BRANCH r551_06
#endif
#if defined(NV_LINUX) || defined(NV_BSD) || defined(NV_SUNOS)
#define NV_BUILD_BRANCH_VERSION "rel/gpu_drv/r545/r545_96-124"
#define NV_BUILD_CHANGELIST_NUM (33538619)
#define NV_BUILD_BRANCH_VERSION "rel/gpu_drv/r550/r551_06-132"
#define NV_BUILD_CHANGELIST_NUM (33773930)
#define NV_BUILD_TYPE "Official"
#define NV_BUILD_NAME "rel/gpu_drv/r545/r545_96-124"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (33538619)
#define NV_BUILD_NAME "rel/gpu_drv/r550/r551_06-132"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (33773930)
#else /* Windows builds */
#define NV_BUILD_BRANCH_VERSION "r545_96-8"
#define NV_BUILD_CHANGELIST_NUM (33517029)
#define NV_BUILD_BRANCH_VERSION "r551_06-14"
#define NV_BUILD_CHANGELIST_NUM (33773930)
#define NV_BUILD_TYPE "Official"
#define NV_BUILD_NAME "546.17"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (33517029)
#define NV_BUILD_BRANCH_BASE_VERSION R545
#define NV_BUILD_NAME "551.23"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (33773930)
#define NV_BUILD_BRANCH_BASE_VERSION R550
#endif
// End buildmeister python edited section

2
src/common/inc/nvPNPVendorIds.h
View File

@@ -157,6 +157,7 @@ static const PNPVendorId PNPVendorIds[] =
{ "CRS", _VENDOR_NAME_ENTRY("Cisco") },
{ "CSE", _VENDOR_NAME_ENTRY("Compu Shack") },
{ "CSI", _VENDOR_NAME_ENTRY("Cabletron") },
{ "CSO", _VENDOR_NAME_ENTRY("California institute of Technology")},
{ "CSS", _VENDOR_NAME_ENTRY("CSS Laboratories") },
{ "CSW", _VENDOR_NAME_ENTRY("China Star Optoelectronics Technology Co., Ltd") },
{ "CTN", _VENDOR_NAME_ENTRY("Computone") },
@@ -294,6 +295,7 @@ static const PNPVendorId PNPVendorIds[] =
{ "ITK", _VENDOR_NAME_ENTRY("NTI Group") },
{ "IVK", _VENDOR_NAME_ENTRY("Iiyama") },
{ "IVM", _VENDOR_NAME_ENTRY("Idek Iiyama") },
{ "IVO", _VENDOR_NAME_ENTRY("InfoVision OptoElectronics Co., Ltd")},
{ "IVR", _VENDOR_NAME_ENTRY("Inlife-Handnet Co., Ltd.") },
{ "IWR", _VENDOR_NAME_ENTRY("Icuiti Corporation") },

2
src/common/inc/nvUnixVersion.h
View File

@@ -4,7 +4,7 @@
#if defined(NV_LINUX) || defined(NV_BSD) || defined(NV_SUNOS) || defined(NV_VMWARE) || defined(NV_QNX) || defined(NV_INTEGRITY) || \
(defined(RMCFG_FEATURE_PLATFORM_GSP) && RMCFG_FEATURE_PLATFORM_GSP == 1)
#define NV_VERSION_STRING "545.29.06"
#define NV_VERSION_STRING "550.40.07"
#else

2
src/common/inc/nvVer.h
View File

@@ -3,7 +3,7 @@
#define NV_COMPANY_NAME_STRING_SHORT "NVIDIA"
#define NV_COMPANY_NAME_STRING_FULL "NVIDIA Corporation"
#define NV_COMPANY_NAME_STRING NV_COMPANY_NAME_STRING_FULL
#define NV_COPYRIGHT_YEAR "2023"
#define NV_COPYRIGHT_YEAR "2024"
#define NV_COPYRIGHT "(C) " NV_COPYRIGHT_YEAR " NVIDIA Corporation. All rights reserved." // Please do not use the non-ascii copyright symbol for (C).
#if defined(NV_LINUX) || defined(NV_BSD) || defined(NV_SUNOS) || defined(NV_VMWARE) || defined(NV_QNX) || defined(NV_INTEGRITY) || \

217
src/common/inc/nveGPUConfig.h
View File

@@ -1,217 +0,0 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2018-2019 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _NVEGPUCONFIG_H_
#define _NVEGPUCONFIG_H_
#include <nvtypes.h>
#ifdef __cplusplus
extern "C" {
#endif
#ifdef __cplusplus
#define EGPU_INLINE NV_FORCEINLINE
#else //!__cplusplus
#if defined(NV_UNIX) || defined(NVCPU_RISCV64) || defined(NV_MODS)
#define EGPU_INLINE static NV_INLINE
#else //NV_UNIX
#define EGPU_INLINE NV_INLINE
#endif //NV_UNIX
#endif //!__cplusplus
// Surprise removal capable TB3 and TB2 BUS Device ID
#define BUS_DEVICE_ID_TB3_ALPINE_RIDGE_01 0x1578
#define BUS_DEVICE_ID_TB3_02 0x1576
#define BUS_DEVICE_ID_TB3_03 0x15C0
#define BUS_DEVICE_ID_TB3_04 0x15D3
#define BUS_DEVICE_ID_TB3_05 0x15DA
#define BUS_DEVICE_ID_TB3_06 0x15EA
#define BUS_DEVICE_ID_TB3_07 0x15E7
#define BUS_DEVICE_ID_TB3_08 0x15EF
#define BUS_DEVICE_ID_TB3_09 0x1133
#define BUS_DEVICE_ID_TB3_10 0x1136
// IceLake-U TB3 device ids. Below TB3 would be integrated to CPU.
#define BUS_DEVICE_ID_ICELAKE_TB3_01 0x8A1D
#define BUS_DEVICE_ID_ICELAKE_TB3_02 0x8A1F
#define BUS_DEVICE_ID_ICELAKE_TB3_03 0x8A21
#define BUS_DEVICE_ID_ICELAKE_TB3_04 0x8A23
#define BUS_DEVICE_ID_ICELAKE_TB3_05 0x8A0D
#define BUS_DEVICE_ID_ICELAKE_TB3_06 0x8A17
// TigerLake Thunderbolt device ids.
#define BUS_DEVICE_ID_TIGERLAKE_TB3_01 0x9A1B
#define BUS_DEVICE_ID_TIGERLAKE_TB3_02 0x9A1D
#define BUS_DEVICE_ID_TIGERLAKE_TB3_03 0x9A1F
#define BUS_DEVICE_ID_TIGERLAKE_TB3_04 0x9A21
#define BUS_DEVICE_ID_TIGERLAKE_TB3_05 0x9A23
#define BUS_DEVICE_ID_TIGERLAKE_TB3_06 0x9A25
#define BUS_DEVICE_ID_TIGERLAKE_TB3_07 0x9A27
#define BUS_DEVICE_ID_TIGERLAKE_TB3_08 0x9A29
#define BUS_DEVICE_ID_TIGERLAKE_TB3_09 0x9A2B
#define BUS_DEVICE_ID_TIGERLAKE_TB3_10 0x9A2D
// Meteor Lake ThunderBolt Device IDs
#define BUS_DEVICE_ID_METEOR_TB3_01 0x7EB2
#define BUS_DEVICE_ID_METEOR_TB3_02 0x7EC2
#define BUS_DEVICE_ID_METEOR_TB3_03 0x7EC3
#define BUS_DEVICE_ID_METEOR_TB3_04 0x7EB4
#define BUS_DEVICE_ID_METEOR_TB3_05 0x7EC4
#define BUS_DEVICE_ID_METEOR_TB3_06 0x7EB5
#define BUS_DEVICE_ID_METEOR_TB3_07 0x7EC5
#define BUS_DEVICE_ID_METEOR_TB3_08 0x7EC6
#define BUS_DEVICE_ID_METEOR_TB3_09 0x7EC7
// Raptor Lake ThunderBolt Device IDs
#define BUS_DEVICE_ID_RAPTOR_TB3_01 0xA73E
#define BUS_DEVICE_ID_RAPTOR_TB3_02 0xA76D
#define BUS_DEVICE_ID_RAPTOR_TB3_03 0x466E
#define BUS_DEVICE_ID_RAPTOR_TB3_04 0x463F
#define BUS_DEVICE_ID_RAPTOR_TB3_05 0x462F
#define BUS_DEVICE_ID_RAPTOR_TB3_06 0x461F
//#define BUS_DEVICE_ID_TB2_FALCON_RIDGE_DSL5520_01 0X156C // obsolete
#define BUS_DEVICE_ID_TB2_FALCON_RIDGE_DSL5520_02 0X156D
#define BUS_DEVICE_ID_TB2_03 0x157E
#define BUS_DEVICE_ID_TB2_04 0x156B
#define BUS_DEVICE_ID_TB2_05 0x1567
#define BUS_DEVICE_ID_TB2_06 0x1569
//#define BUS_DEVICE_ID_TB2_07 0x1548 // obsolete
#define BUS_DEVICE_ID_TB2_08 0x151B
#define BUS_DEVICE_ID_TB2_09 0x1549
#define BUS_DEVICE_ID_TB2_10 0x1513
//*****************************************************************************
// Function: isTB3DeviceID
//
// Routine Description:
//
// Function to match the specified Device ID with the known TB3 BUS's
// device IDs.
//
// Arguments:
//
// deviceID[IN]: Device ID to match with the TB3 Bus
//
// Return Value:
//
// true: When the passed Dev ID match with TB3's BUS Device ID
// false: When the passed Dev ID is not matching with known TB3's
// BUS Device ID
//*****************************************************************************
EGPU_INLINE NvBool isTB3DeviceID(NvU16 deviceID)
{
NvU32 index;
NvU16 tb3DeviceIDList[]={ BUS_DEVICE_ID_TB3_ALPINE_RIDGE_01,
BUS_DEVICE_ID_TB3_02,
BUS_DEVICE_ID_TB3_03,
BUS_DEVICE_ID_TB3_04,
BUS_DEVICE_ID_TB3_05,
BUS_DEVICE_ID_TB3_06,
BUS_DEVICE_ID_TB3_07,
BUS_DEVICE_ID_TB3_08,
BUS_DEVICE_ID_TB3_09,
BUS_DEVICE_ID_TB3_10,
BUS_DEVICE_ID_ICELAKE_TB3_01,
BUS_DEVICE_ID_ICELAKE_TB3_02,
BUS_DEVICE_ID_ICELAKE_TB3_03,
BUS_DEVICE_ID_ICELAKE_TB3_04,
BUS_DEVICE_ID_ICELAKE_TB3_05,
BUS_DEVICE_ID_ICELAKE_TB3_06,
BUS_DEVICE_ID_TIGERLAKE_TB3_01,
BUS_DEVICE_ID_TIGERLAKE_TB3_02,
BUS_DEVICE_ID_TIGERLAKE_TB3_03,
BUS_DEVICE_ID_TIGERLAKE_TB3_04,
BUS_DEVICE_ID_TIGERLAKE_TB3_05,
BUS_DEVICE_ID_TIGERLAKE_TB3_06,
BUS_DEVICE_ID_TIGERLAKE_TB3_07,
BUS_DEVICE_ID_TIGERLAKE_TB3_08,
BUS_DEVICE_ID_TIGERLAKE_TB3_09,
BUS_DEVICE_ID_TIGERLAKE_TB3_10,
BUS_DEVICE_ID_METEOR_TB3_01,
BUS_DEVICE_ID_METEOR_TB3_02,
BUS_DEVICE_ID_METEOR_TB3_03,
BUS_DEVICE_ID_METEOR_TB3_04,
BUS_DEVICE_ID_METEOR_TB3_05,
BUS_DEVICE_ID_METEOR_TB3_06,
BUS_DEVICE_ID_METEOR_TB3_07,
BUS_DEVICE_ID_METEOR_TB3_08,
BUS_DEVICE_ID_METEOR_TB3_09,
BUS_DEVICE_ID_RAPTOR_TB3_01,
BUS_DEVICE_ID_RAPTOR_TB3_02,
BUS_DEVICE_ID_RAPTOR_TB3_03,
BUS_DEVICE_ID_RAPTOR_TB3_04,
BUS_DEVICE_ID_RAPTOR_TB3_05,
BUS_DEVICE_ID_RAPTOR_TB3_06
};
for (index = 0; index < (sizeof(tb3DeviceIDList)/sizeof(NvU16)); index++)
{
if (deviceID == tb3DeviceIDList[index])
{
return NV_TRUE;
}
}
return NV_FALSE;
} // isTB3DeviceID
//*****************************************************************************
// Function: isTB2DeviceID
//
// Routine Description:
//
// Function to match the specified Device ID with the known TB2 BUS's
// device IDs.
//
// Arguments:
//
// deviceID[IN]: Device ID to match with the TB2 Bus
//
// Return Value:
//
// true: When the passed Dev ID match with TB2's BUS Device ID
// false: When the passed Dev ID is not matching with known TB2's
// BUS Device ID
//*****************************************************************************
EGPU_INLINE NvBool isTB2DeviceID(NvU16 deviceID)
{
NvU32 index;
NvU16 tb2DeviceIDList[]={ BUS_DEVICE_ID_TB2_FALCON_RIDGE_DSL5520_02,
BUS_DEVICE_ID_TB2_03, BUS_DEVICE_ID_TB2_04,
BUS_DEVICE_ID_TB2_05, BUS_DEVICE_ID_TB2_06,
BUS_DEVICE_ID_TB2_08, BUS_DEVICE_ID_TB2_09,
BUS_DEVICE_ID_TB2_10
};
for (index = 0; index < (sizeof(tb2DeviceIDList)/sizeof(NvU16)); index++)
{
if (deviceID == tb2DeviceIDList[index])
{
return NV_TRUE;
}
}
return NV_FALSE;
} // isTB2DeviceID
#ifdef __cplusplus
}
#endif
#endif //_NVEGPUCONFIG_H_

33
src/common/inc/nvhybridacpi.h
View File

@@ -68,6 +68,39 @@ extern "C"
#define NVHG_ERROR_UNSUPPORTED 0x80000002 // FunctionCode or SubFunctionCode not supported by this system
#define NVHG_ERROR_PARM_INVALID 0x80000003 // Parameter is invalid (i.e. start page beyond end of buffer)
// ****************************************************
// For MXDS Display Output Mux Control Method
// ****************************************************
#define MXDS_METHOD_GET_MUX_STATE 0x00000000
#define MXDS_METHOD_SET_DISP_MUX_TO_THISGPU 0x00000001
#define MXDS_METHOD_SET_BACKLIGHT_MUX_TO_THISGPU 0x00000002
#define MXDS_METHOD_SET_DISP_AND_BACKLIGHT_MUX_TO_THISGPU 0x00000003
// return buffer definitions
#define MXDS_METHOD_MUX_STATE_NOT_MUXED 0x00000000
#define MXDS_METHOD_MUX_STATE_IS_MUXED 0x00000001
//
// ACPI _MXDS (Switch DispMux state) specific defines
// These defines are as per the ACPI spec from Bug 2297713
//
#define MXDS_METHOD_MUX_OP 3:0
#define MXDS_METHOD_MUX_OP_GET 0x00000000
#define MXDS_METHOD_MUX_OP_SET 0x00000001
#define MXDS_METHOD_MUX_SET_MODE 4:4
#define MXDS_METHOD_MUX_SET_MODE_IGPU 0x00000000
#define MXDS_METHOD_MUX_SET_MODE_DGPU 0x00000001
//
// ACPI _LRST (LCD VDD force reset) specific defines
// These defines are as per the ACPI spec from NVIDIA
// DDS Partner Guidelines For Notebook (OEM Doc)
//
#define LRST_METHOD_FORCE_RESET_OP 2:0
#define LRST_METHOD_FORCE_RESET_OP_GET 0x00000000
#define LRST_METHOD_FORCE_RESET_OP_SET_LOW 0x00000001
#define LRST_METHOD_FORCE_RESET_OP_SET_HIGH 0x00000002
#if defined(__cplusplus)
} // extern "C"
#endif // defined(__cplusplus)

6
src/common/inc/nvlog_defs.h
View File

@@ -103,14 +103,8 @@ struct _NVLOG_BUFFER
#define NVLOG_MAX_BUFFERS_v11 16
#define NVLOG_MAX_BUFFERS_v12 256
#if NVOS_IS_UNIX
#define NVLOG_MAX_BUFFERS NVLOG_MAX_BUFFERS_v12
#define NVLOG_LOGGER_VERSION 12 // v1.2
#else
#define NVLOG_MAX_BUFFERS NVLOG_MAX_BUFFERS_v11
#define NVLOG_LOGGER_VERSION 11 // v1.1
#endif // NVOS_IS_UNIX
// Due to this file's peculiar location, NvPort may or may not be includable
typedef struct PORT_SPINLOCK PORT_SPINLOCK;

14
src/common/inc/swref/published/ada/ad102/dev_bus.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2022-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -28,6 +28,18 @@
#define NV_PBUS_SW_SCRATCH__SIZE_1 64 /* */
#define NV_PBUS_SW_SCRATCH_FIELD 31:0 /* RWIVF */
#define NV_PBUS_SW_SCRATCH_FIELD_INIT 0x00000000 /* RWI-V */
#define NV_PBUS_BAR1_BLOCK 0x00001704 /* RW-4R */
#define NV_PBUS_BAR1_BLOCK_MAP 29:0 /* */
#define NV_PBUS_BAR1_BLOCK_PTR 27:0 /* RWIUF */
#define NV_PBUS_BAR1_BLOCK_PTR_0 0x00000000 /* RWI-V */
#define NV_PBUS_BAR1_BLOCK_TARGET 29:28 /* RWIUF */
#define NV_PBUS_BAR1_BLOCK_TARGET_VID_MEM 0x00000000 /* RWI-V */
#define NV_PBUS_BAR1_BLOCK_TARGET_SYS_MEM_COHERENT 0x00000002 /* RW--V */
#define NV_PBUS_BAR1_BLOCK_TARGET_SYS_MEM_NONCOHERENT 0x00000003 /* RW--V */
#define NV_PBUS_BAR1_BLOCK_MODE 31:31 /* RWIUF */
#define NV_PBUS_BAR1_BLOCK_MODE_PHYSICAL 0x00000000 /* RWI-V */
#define NV_PBUS_BAR1_BLOCK_MODE_VIRTUAL 0x00000001 /* RW--V */
#define NV_PBUS_BAR1_BLOCK_PTR_SHIFT 12 /* */
#endif // ad102_dev_nv_bus_h

63
src/common/inc/swref/published/ada/ad102/dev_fault.h Normal file
View File

@@ -0,0 +1,63 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2023 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __ad102_dev_fault_h__
#define __ad102_dev_fault_h__
#define NV_PFAULT_MMU_ENG_ID_DISPLAY 1 /* */
#define NV_PFAULT_MMU_ENG_ID_IFB 9 /* */
#define NV_PFAULT_MMU_ENG_ID_FLA 4 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1 128 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2 192 /* */
#define NV_PFAULT_MMU_ENG_ID_SEC 14 /* */
#define NV_PFAULT_MMU_ENG_ID_PERF 8 /* */
#define NV_PFAULT_MMU_ENG_ID_NVDEC 25 /* */
#define NV_PFAULT_MMU_ENG_ID_NVDEC0 25 /* */
#define NV_PFAULT_MMU_ENG_ID_NVDEC1 26 /* */
#define NV_PFAULT_MMU_ENG_ID_NVDEC2 27 /* */
#define NV_PFAULT_MMU_ENG_ID_NVDEC3 28 /* */
#define NV_PFAULT_MMU_ENG_ID_NVDEC4 29 /* */
#define NV_PFAULT_MMU_ENG_ID_NVJPG0 21 /* */
#define NV_PFAULT_MMU_ENG_ID_NVJPG1 22 /* */
#define NV_PFAULT_MMU_ENG_ID_NVJPG2 23 /* */
#define NV_PFAULT_MMU_ENG_ID_NVJPG3 24 /* */
#define NV_PFAULT_MMU_ENG_ID_GRCOPY 15 /* */
#define NV_PFAULT_MMU_ENG_ID_CE0 15 /* */
#define NV_PFAULT_MMU_ENG_ID_CE1 16 /* */
#define NV_PFAULT_MMU_ENG_ID_CE2 17 /* */
#define NV_PFAULT_MMU_ENG_ID_CE3 18 /* */
#define NV_PFAULT_MMU_ENG_ID_CE4 19 /* */
#define NV_PFAULT_MMU_ENG_ID_CE5 20 /* */
#define NV_PFAULT_MMU_ENG_ID_PWR_PMU 6 /* */
#define NV_PFAULT_MMU_ENG_ID_PTP 3 /* */
#define NV_PFAULT_MMU_ENG_ID_NVENC0 11 /* */
#define NV_PFAULT_MMU_ENG_ID_NVENC1 12 /* */
#define NV_PFAULT_MMU_ENG_ID_NVENC2 13 /* */
#define NV_PFAULT_MMU_ENG_ID_OFA0 10 /* */
#define NV_PFAULT_MMU_ENG_ID_PHYSICAL 31 /* */
#define NV_PFAULT_CLIENT_HUB_NVJPG1 0x00000072 /* */
#define NV_PFAULT_CLIENT_HUB_NVJPG2 0x00000073 /* */
#define NV_PFAULT_CLIENT_HUB_NVJPG3 0x00000074 /* */
#endif // __ad102_dev_fault_h__

8
src/common/inc/swref/published/ampere/ga100/dev_boot.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES
* SPDX-FileCopyrightText: Copyright (c) 2003-2023 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -33,6 +33,12 @@
#define NV_PMC_ENABLE_NVDEC 15:15 /* */
#define NV_PMC_ENABLE_NVDEC_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_NVDEC_ENABLED 0x00000001 /* */
#define NV_PMC_ENABLE_PERFMON 28:28 /* RWIVF */
#define NV_PMC_ENABLE_PERFMON_DISABLED 0x00000000 /* RWI-V */
#define NV_PMC_ENABLE_PERFMON_ENABLED 0x00000001 /* RW--V */
#define NV_PMC_ENABLE_PDISP 30:30 /* RWIVF */
#define NV_PMC_ENABLE_PDISP_DISABLED 0x00000000 /* RW--V */
#define NV_PMC_ENABLE_PDISP_ENABLED 0x00000001 /* RWI-V */
#define NV_PMC_DEVICE_ENABLE(i) (0x000000600+(i)*4) /* RW-4A */
#define NV_PMC_DEVICE_ENABLE__SIZE_1 1 /* */
#define NV_PMC_DEVICE_ENABLE__PRIV_LEVEL_MASK 0x00000084 /* */

14
src/common/inc/swref/published/ampere/ga100/dev_bus.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES
* SPDX-FileCopyrightText: Copyright (c) 2022-2023 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -28,5 +28,17 @@
#define NV_PBUS_SW_SCRATCH__SIZE_1 64 /* */
#define NV_PBUS_SW_SCRATCH_FIELD 31:0 /* RWIVF */
#define NV_PBUS_SW_SCRATCH_FIELD_INIT 0x00000000 /* RWI-V */
#define NV_PBUS_BAR1_BLOCK 0x00001704 /* RW-4R */
#define NV_PBUS_BAR1_BLOCK_MAP 29:0 /* */
#define NV_PBUS_BAR1_BLOCK_PTR 27:0 /* RWIUF */
#define NV_PBUS_BAR1_BLOCK_PTR_0 0x00000000 /* RWI-V */
#define NV_PBUS_BAR1_BLOCK_TARGET 29:28 /* RWIUF */
#define NV_PBUS_BAR1_BLOCK_TARGET_VID_MEM 0x00000000 /* RWI-V */
#define NV_PBUS_BAR1_BLOCK_TARGET_SYS_MEM_COHERENT 0x00000002 /* RW--V */
#define NV_PBUS_BAR1_BLOCK_TARGET_SYS_MEM_NONCOHERENT 0x00000003 /* RW--V */
#define NV_PBUS_BAR1_BLOCK_MODE 31:31 /* RWIUF */
#define NV_PBUS_BAR1_BLOCK_MODE_PHYSICAL 0x00000000 /* RWI-V */
#define NV_PBUS_BAR1_BLOCK_MODE_VIRTUAL 0x00000001 /* RW--V */
#define NV_PBUS_BAR1_BLOCK_PTR_SHIFT 12 /* */
#endif // ga100_dev_nv_bus_h

206
src/common/inc/swref/published/ampere/ga100/dev_fault.h Normal file
View File

@@ -0,0 +1,206 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2023 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __ga100_dev_fault_h__
#define __ga100_dev_fault_h__
#define NV_PFAULT_MMU_ENG_ID_DISPLAY 1 /* */
#define NV_PFAULT_MMU_ENG_ID_IFB 9 /* */
#define NV_PFAULT_MMU_ENG_ID_FLA 4 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1 128 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2 192 /* */
#define NV_PFAULT_MMU_ENG_ID_SEC 14 /* */
#define NV_PFAULT_MMU_ENG_ID_PERF 8 /* */
#define NV_PFAULT_MMU_ENG_ID_NVDEC 25 /* */
#define NV_PFAULT_MMU_ENG_ID_NVDEC0 25 /* */
#define NV_PFAULT_MMU_ENG_ID_NVDEC1 26 /* */
#define NV_PFAULT_MMU_ENG_ID_NVDEC2 27 /* */
#define NV_PFAULT_MMU_ENG_ID_NVDEC3 28 /* */
#define NV_PFAULT_MMU_ENG_ID_NVDEC4 29 /* */
#define NV_PFAULT_MMU_ENG_ID_NVJPG0 30 /* */
#define NV_PFAULT_MMU_ENG_ID_GRCOPY 15 /* */
#define NV_PFAULT_MMU_ENG_ID_CE0 15 /* */
#define NV_PFAULT_MMU_ENG_ID_CE1 16 /* */
#define NV_PFAULT_MMU_ENG_ID_CE2 17 /* */
#define NV_PFAULT_MMU_ENG_ID_CE3 18 /* */
#define NV_PFAULT_MMU_ENG_ID_CE4 19 /* */
#define NV_PFAULT_MMU_ENG_ID_CE5 20 /* */
#define NV_PFAULT_MMU_ENG_ID_CE6 21 /* */
#define NV_PFAULT_MMU_ENG_ID_CE7 22 /* */
#define NV_PFAULT_MMU_ENG_ID_CE8 23 /* */
#define NV_PFAULT_MMU_ENG_ID_CE9 24 /* */
#define NV_PFAULT_MMU_ENG_ID_PWR_PMU 6 /* */
#define NV_PFAULT_MMU_ENG_ID_PTP 3 /* */
#define NV_PFAULT_MMU_ENG_ID_NVENC0 11 /* */
#define NV_PFAULT_MMU_ENG_ID_NVENC1 12 /* */
#define NV_PFAULT_MMU_ENG_ID_NVENC2 13 /* */
#define NV_PFAULT_MMU_ENG_ID_OFA0 10 /* */
#define NV_PFAULT_MMU_ENG_ID_PHYSICAL 31 /* */
#define NV_PFAULT_FAULT_TYPE_UNBOUND_INST_BLOCK 0x00000004 /* */
#define NV_PFAULT_CLIENT_GPC_T1_0 0x00000000 /* */
#define NV_PFAULT_CLIENT_GPC_T1_1 0x00000001 /* */
#define NV_PFAULT_CLIENT_GPC_T1_2 0x00000002 /* */
#define NV_PFAULT_CLIENT_GPC_T1_3 0x00000003 /* */
#define NV_PFAULT_CLIENT_GPC_T1_4 0x00000004 /* */
#define NV_PFAULT_CLIENT_GPC_T1_5 0x00000005 /* */
#define NV_PFAULT_CLIENT_GPC_T1_6 0x00000006 /* */
#define NV_PFAULT_CLIENT_GPC_T1_7 0x00000007 /* */
#define NV_PFAULT_CLIENT_GPC_PE_0 0x00000008 /* */
#define NV_PFAULT_CLIENT_GPC_PE_1 0x00000009 /* */
#define NV_PFAULT_CLIENT_GPC_PE_2 0x0000000A /* */
#define NV_PFAULT_CLIENT_GPC_PE_3 0x0000000B /* */
#define NV_PFAULT_CLIENT_GPC_PE_4 0x0000000C /* */
#define NV_PFAULT_CLIENT_GPC_PE_5 0x0000000D /* */
#define NV_PFAULT_CLIENT_GPC_PE_6 0x0000000E /* */
#define NV_PFAULT_CLIENT_GPC_PE_7 0x0000000F /* */
#define NV_PFAULT_CLIENT_GPC_RAST 0x00000010 /* */
#define NV_PFAULT_CLIENT_GPC_GCC 0x00000011 /* */
#define NV_PFAULT_CLIENT_GPC_GPCCS 0x00000012 /* */
#define NV_PFAULT_CLIENT_GPC_PROP_0 0x00000013 /* */
#define NV_PFAULT_CLIENT_GPC_PROP_1 0x00000014 /* */
#define NV_PFAULT_CLIENT_GPC_T1_8 0x00000021 /* */
#define NV_PFAULT_CLIENT_GPC_T1_9 0x00000022 /* */
#define NV_PFAULT_CLIENT_GPC_T1_10 0x00000023 /* */
#define NV_PFAULT_CLIENT_GPC_T1_11 0x00000024 /* */
#define NV_PFAULT_CLIENT_GPC_T1_12 0x00000025 /* */
#define NV_PFAULT_CLIENT_GPC_T1_13 0x00000026 /* */
#define NV_PFAULT_CLIENT_GPC_T1_14 0x00000027 /* */
#define NV_PFAULT_CLIENT_GPC_T1_15 0x00000028 /* */
#define NV_PFAULT_CLIENT_GPC_TPCCS_0 0x00000029 /* */
#define NV_PFAULT_CLIENT_GPC_TPCCS_1 0x0000002A /* */
#define NV_PFAULT_CLIENT_GPC_TPCCS_2 0x0000002B /* */
#define NV_PFAULT_CLIENT_GPC_TPCCS_3 0x0000002C /* */
#define NV_PFAULT_CLIENT_GPC_TPCCS_4 0x0000002D /* */
#define NV_PFAULT_CLIENT_GPC_TPCCS_5 0x0000002E /* */
#define NV_PFAULT_CLIENT_GPC_TPCCS_6 0x0000002F /* */
#define NV_PFAULT_CLIENT_GPC_TPCCS_7 0x00000030 /* */
#define NV_PFAULT_CLIENT_GPC_PE_8 0x00000031 /* */
#define NV_PFAULT_CLIENT_GPC_TPCCS_8 0x00000033 /* */
#define NV_PFAULT_CLIENT_GPC_T1_16 0x00000035 /* */
#define NV_PFAULT_CLIENT_GPC_T1_17 0x00000036 /* */
#define NV_PFAULT_CLIENT_GPC_ROP_0 0x00000070 /* */
#define NV_PFAULT_CLIENT_GPC_ROP_1 0x00000071 /* */
#define NV_PFAULT_CLIENT_GPC_GPM 0x00000017 /* */
#define NV_PFAULT_CLIENT_HUB_VIP 0x00000000 /* */
#define NV_PFAULT_CLIENT_HUB_CE0 0x00000001 /* */
#define NV_PFAULT_CLIENT_HUB_CE1 0x00000002 /* */
#define NV_PFAULT_CLIENT_HUB_DNISO 0x00000003 /* */
#define NV_PFAULT_CLIENT_HUB_DISPNISO 0x00000003 /* */
#define NV_PFAULT_CLIENT_HUB_FE0 0x00000004 /* */
#define NV_PFAULT_CLIENT_HUB_FE 0x00000004 /* */
#define NV_PFAULT_CLIENT_HUB_FECS0 0x00000005 /* */
#define NV_PFAULT_CLIENT_HUB_FECS 0x00000005 /* */
#define NV_PFAULT_CLIENT_HUB_HOST 0x00000006 /* */
#define NV_PFAULT_CLIENT_HUB_HOST_CPU 0x00000007 /* */
#define NV_PFAULT_CLIENT_HUB_HOST_CPU_NB 0x00000008 /* */
#define NV_PFAULT_CLIENT_HUB_ISO 0x00000009 /* */
#define NV_PFAULT_CLIENT_HUB_MMU 0x0000000A /* */
#define NV_PFAULT_CLIENT_HUB_NVDEC0 0x0000000B /* */
#define NV_PFAULT_CLIENT_HUB_NVDEC 0x0000000B /* */
#define NV_PFAULT_CLIENT_HUB_NVENC1 0x0000000D /* */
#define NV_PFAULT_CLIENT_HUB_NISO 0x0000000E /* */
#define NV_PFAULT_CLIENT_HUB_ACTRS 0x0000000E /* */
#define NV_PFAULT_CLIENT_HUB_P2P 0x0000000F /* */
#define NV_PFAULT_CLIENT_HUB_PD 0x00000010 /* */
#define NV_PFAULT_CLIENT_HUB_PERF0 0x00000011 /* */
#define NV_PFAULT_CLIENT_HUB_PERF 0x00000011 /* */
#define NV_PFAULT_CLIENT_HUB_PMU 0x00000012 /* */
#define NV_PFAULT_CLIENT_HUB_RASTERTWOD 0x00000013 /* */
#define NV_PFAULT_CLIENT_HUB_SCC 0x00000014 /* */
#define NV_PFAULT_CLIENT_HUB_SCC_NB 0x00000015 /* */
#define NV_PFAULT_CLIENT_HUB_SEC 0x00000016 /* */
#define NV_PFAULT_CLIENT_HUB_SSYNC 0x00000017 /* */
#define NV_PFAULT_CLIENT_HUB_GRCOPY 0x00000018 /* */
#define NV_PFAULT_CLIENT_HUB_CE2 0x00000018 /* */
#define NV_PFAULT_CLIENT_HUB_XV 0x00000019 /* */
#define NV_PFAULT_CLIENT_HUB_MMU_NB 0x0000001A /* */
#define NV_PFAULT_CLIENT_HUB_NVENC0 0x0000001B /* */
#define NV_PFAULT_CLIENT_HUB_NVENC 0x0000001B /* */
#define NV_PFAULT_CLIENT_HUB_DFALCON 0x0000001C /* */
#define NV_PFAULT_CLIENT_HUB_SKED0 0x0000001D /* */
#define NV_PFAULT_CLIENT_HUB_SKED 0x0000001D /* */
#define NV_PFAULT_CLIENT_HUB_AFALCON 0x0000001E /* */
#define NV_PFAULT_CLIENT_HUB_DONT_CARE 0x0000001F /* */
#define NV_PFAULT_CLIENT_HUB_HSCE0 0x00000020 /* */
#define NV_PFAULT_CLIENT_HUB_HSCE1 0x00000021 /* */
#define NV_PFAULT_CLIENT_HUB_HSCE2 0x00000022 /* */
#define NV_PFAULT_CLIENT_HUB_HSCE3 0x00000023 /* */
#define NV_PFAULT_CLIENT_HUB_HSCE4 0x00000024 /* */
#define NV_PFAULT_CLIENT_HUB_HSCE5 0x00000025 /* */
#define NV_PFAULT_CLIENT_HUB_HSCE6 0x00000026 /* */
#define NV_PFAULT_CLIENT_HUB_HSCE7 0x00000027 /* */
#define NV_PFAULT_CLIENT_HUB_HSCE8 0x00000028 /* */
#define NV_PFAULT_CLIENT_HUB_HSCE9 0x00000029 /* */
#define NV_PFAULT_CLIENT_HUB_HSHUB 0x0000002A /* */
#define NV_PFAULT_CLIENT_HUB_PTP_X0 0x0000002B /* */
#define NV_PFAULT_CLIENT_HUB_PTP_X1 0x0000002C /* */
#define NV_PFAULT_CLIENT_HUB_PTP_X2 0x0000002D /* */
#define NV_PFAULT_CLIENT_HUB_PTP_X3 0x0000002E /* */
#define NV_PFAULT_CLIENT_HUB_PTP_X4 0x0000002F /* */
#define NV_PFAULT_CLIENT_HUB_PTP_X5 0x00000030 /* */
#define NV_PFAULT_CLIENT_HUB_NVENC2 0x00000033 /* */
#define NV_PFAULT_CLIENT_HUB_VPR_SCRUBBER0 0x00000034 /* */
#define NV_PFAULT_CLIENT_HUB_VPR_SCRUBBER1 0x00000035 /* */
#define NV_PFAULT_CLIENT_HUB_DWBIF 0x00000036 /* */
#define NV_PFAULT_CLIENT_HUB_FBFALCON 0x00000037 /* */
#define NV_PFAULT_CLIENT_HUB_CE_SHIM 0x00000038 /* */
#define NV_PFAULT_CLIENT_HUB_GSP 0x00000039 /* */
#define NV_PFAULT_CLIENT_HUB_NVDEC1 0x0000003A /* */
#define NV_PFAULT_CLIENT_HUB_NVDEC2 0x0000003B /* */
#define NV_PFAULT_CLIENT_HUB_NVJPG0 0x0000003C /* */
#define NV_PFAULT_CLIENT_HUB_NVDEC3 0x0000003D /* */
#define NV_PFAULT_CLIENT_HUB_NVDEC4 0x0000003E /* */
#define NV_PFAULT_CLIENT_HUB_OFA0 0x0000003F /* */
#define NV_PFAULT_CLIENT_HUB_HSCE10 0x00000040 /* */
#define NV_PFAULT_CLIENT_HUB_HSCE11 0x00000041 /* */
#define NV_PFAULT_CLIENT_HUB_HSCE12 0x00000042 /* */
#define NV_PFAULT_CLIENT_HUB_HSCE13 0x00000043 /* */
#define NV_PFAULT_CLIENT_HUB_HSCE14 0x00000044 /* */
#define NV_PFAULT_CLIENT_HUB_HSCE15 0x00000045 /* */
#define NV_PFAULT_CLIENT_HUB_FE1 0x0000004E /* */
#define NV_PFAULT_CLIENT_HUB_FE2 0x0000004F /* */
#define NV_PFAULT_CLIENT_HUB_FE3 0x00000050 /* */
#define NV_PFAULT_CLIENT_HUB_FE4 0x00000051 /* */
#define NV_PFAULT_CLIENT_HUB_FE5 0x00000052 /* */
#define NV_PFAULT_CLIENT_HUB_FE6 0x00000053 /* */
#define NV_PFAULT_CLIENT_HUB_FE7 0x00000054 /* */
#define NV_PFAULT_CLIENT_HUB_FECS1 0x00000055 /* */
#define NV_PFAULT_CLIENT_HUB_FECS2 0x00000056 /* */
#define NV_PFAULT_CLIENT_HUB_FECS3 0x00000057 /* */
#define NV_PFAULT_CLIENT_HUB_FECS4 0x00000058 /* */
#define NV_PFAULT_CLIENT_HUB_FECS5 0x00000059 /* */
#define NV_PFAULT_CLIENT_HUB_FECS6 0x0000005A /* */
#define NV_PFAULT_CLIENT_HUB_FECS7 0x0000005B /* */
#define NV_PFAULT_CLIENT_HUB_SKED1 0x0000005C /* */
#define NV_PFAULT_CLIENT_HUB_SKED2 0x0000005D /* */
#define NV_PFAULT_CLIENT_HUB_SKED3 0x0000005E /* */
#define NV_PFAULT_CLIENT_HUB_SKED4 0x0000005F /* */
#define NV_PFAULT_CLIENT_HUB_SKED5 0x00000060 /* */
#define NV_PFAULT_CLIENT_HUB_SKED6 0x00000061 /* */
#define NV_PFAULT_CLIENT_HUB_SKED7 0x00000062 /* */
#define NV_PFAULT_CLIENT_HUB_ESC 0x00000063 /* */
#endif // __ga100_dev_fault_h__

28
src/common/inc/swref/published/ampere/ga100/hwproject.h Normal file
View File

@@ -0,0 +1,28 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __ga100_hwproject_h__
#define __ga100_hwproject_h__
#define NV_SCAL_LITTER_NUM_FBPAS 24
#endif // __ga100_hwproject_h__

1
src/common/inc/swref/published/ampere/ga102/dev_vm.h
View File

@@ -61,4 +61,5 @@
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF_TRIGGER 0x00001640 /* -W-4R */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF_TRIGGER_VECTOR 11:0 /* -WXVF */
#define NV_VIRTUAL_FUNCTION_PRIV_DOORBELL 0x2200 /* -W-4R */
#define NV_VIRTUAL_FUNCTION_PRIV_MAILBOX_SCRATCH(i) (0x2100+(i)*4) /* RW-4A */
#endif // __ga102_dev_vm_h__

32
src/common/inc/swref/published/hopper/gh100/dev_bus.h Normal file
View File

@@ -0,0 +1,32 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef gh100_dev_nv_bus_h
#define gh100_dev_nv_bus_h
#define NV_PBUS_SW_SCRATCH(i) (0x00001400+(i)*4) /* RW-4A */
#define NV_PBUS_SW_SCRATCH__SIZE_1 64 /* */
#define NV_PBUS_SW_SCRATCH_FIELD 31:0 /* RWIVF */
#define NV_PBUS_SW_SCRATCH_FIELD_INIT 0x00000000 /* RWI-V */
#endif // gh100_dev_nv_bus_h

47
src/common/inc/swref/published/hopper/gh100/dev_bus_addendum.h Normal file
View File

@@ -0,0 +1,47 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef gh100_dev_nv_bus_addendum_h
#define gh100_dev_nv_bus_addendum_h
/*!
* @defgroup FRTS_INSECURE_SCRATCH_REGISTERS
*
* Used to communicate the location/size of insecure FRTS
*
* @{
*/
#define NV_PBUS_SW_FRTS_INSECURE_ADDR_LO32 NV_PBUS_SW_SCRATCH(0x3D)
#define NV_PBUS_SW_FRTS_INSECURE_ADDR_HI32 NV_PBUS_SW_SCRATCH(0x3E)
#define NV_PBUS_SW_FRTS_INSECURE_CONFIG NV_PBUS_SW_SCRATCH(0x3F)
#define NV_PBUS_SW_FRTS_INSECURE_CONFIG_SIZE_4K 15U:0U
#define NV_PBUS_SW_FRTS_INSECURE_CONFIG_SIZE_4K_INVALID 0x0000
#define NV_PBUS_SW_FRTS_INSECURE_CONFIG_SIZE_4K_SHIFT 12U
#define NV_PBUS_SW_FRTS_INSECURE_CONFIG_MEDIA_TYPE 16U:16U
#define NV_PBUS_SW_FRTS_INSECURE_CONFIG_MEDIA_TYPE_FB 0U
#define NV_PBUS_SW_FRTS_INSECURE_CONFIG_MEDIA_TYPE_SYSMEM 1U
/*!@}*/
#endif // gh100_dev_nv_bus_addendum_h

181
src/common/inc/swref/published/hopper/gh100/dev_fault.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES
* SPDX-FileCopyrightText: Copyright (c) 2003-2023 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -24,6 +24,183 @@
#ifndef __gh100_dev_fault_h__
#define __gh100_dev_fault_h__
#define NV_PFAULT_MMU_ENG_ID_GRAPHICS 384 /* */
#define NV_PFAULT_MMU_ENG_ID_GRAPHICS 384 /* */
#define NV_PFAULT_MMU_ENG_ID_DISPLAY 1 /* */
#define NV_PFAULT_MMU_ENG_ID_GSP 2 /* */
#define NV_PFAULT_MMU_ENG_ID_FLA 4 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1 256 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2 320 /* */
#define NV_PFAULT_MMU_ENG_ID_FSP 7 /* */
#define NV_PFAULT_MMU_ENG_ID_PERF 10 /* */
#define NV_PFAULT_MMU_ENG_ID_PERF0 10 /* */
#define NV_PFAULT_MMU_ENG_ID_PWR_PMU 5 /* */
#define NV_PFAULT_MMU_ENG_ID_PTP 3 /* */
#define NV_PFAULT_MMU_ENG_ID_PHYSICAL 56 /* */
#define NV_PFAULT_MMU_ENG_ID_CE0 43 /* */
#define NV_PFAULT_MMU_ENG_ID_CE1 44 /* */
#define NV_PFAULT_MMU_ENG_ID_CE2 45 /* */
#define NV_PFAULT_MMU_ENG_ID_CE3 46 /* */
#define NV_PFAULT_MMU_ENG_ID_CE4 47 /* */
#define NV_PFAULT_MMU_ENG_ID_CE5 48 /* */
#define NV_PFAULT_MMU_ENG_ID_CE6 49 /* */
#define NV_PFAULT_MMU_ENG_ID_CE7 50 /* */
#define NV_PFAULT_MMU_ENG_ID_CE8 51 /* */
#define NV_PFAULT_MMU_ENG_ID_CE9 52 /* */
#define NV_PFAULT_CLIENT_GPC_T1_0 0x00000000 /* */
#define NV_PFAULT_CLIENT_GPC_T1_1 0x00000001 /* */
#define NV_PFAULT_CLIENT_GPC_T1_2 0x00000002 /* */
#define NV_PFAULT_CLIENT_GPC_T1_3 0x00000003 /* */
#define NV_PFAULT_CLIENT_GPC_T1_4 0x00000004 /* */
#define NV_PFAULT_CLIENT_GPC_T1_5 0x00000005 /* */
#define NV_PFAULT_CLIENT_GPC_T1_6 0x00000006 /* */
#define NV_PFAULT_CLIENT_GPC_T1_7 0x00000007 /* */
#define NV_PFAULT_CLIENT_GPC_PE_0 0x00000008 /* */
#define NV_PFAULT_CLIENT_GPC_PE_1 0x00000009 /* */
#define NV_PFAULT_CLIENT_GPC_PE_2 0x0000000A /* */
#define NV_PFAULT_CLIENT_GPC_PE_3 0x0000000B /* */
#define NV_PFAULT_CLIENT_GPC_PE_4 0x0000000C /* */
#define NV_PFAULT_CLIENT_GPC_PE_5 0x0000000D /* */
#define NV_PFAULT_CLIENT_GPC_PE_6 0x0000000E /* */
#define NV_PFAULT_CLIENT_GPC_PE_7 0x0000000F /* */
#define NV_PFAULT_CLIENT_GPC_RAST 0x00000010 /* */
#define NV_PFAULT_CLIENT_GPC_GCC 0x00000011 /* */
#define NV_PFAULT_CLIENT_GPC_GPCCS 0x00000012 /* */
#define NV_PFAULT_CLIENT_GPC_PROP_0 0x00000013 /* */
#define NV_PFAULT_CLIENT_GPC_PROP_1 0x00000014 /* */
#define NV_PFAULT_CLIENT_GPC_T1_8 0x00000021 /* */
#define NV_PFAULT_CLIENT_GPC_T1_9 0x00000022 /* */
#define NV_PFAULT_CLIENT_GPC_T1_10 0x00000023 /* */
#define NV_PFAULT_CLIENT_GPC_T1_11 0x00000024 /* */
#define NV_PFAULT_CLIENT_GPC_T1_12 0x00000025 /* */
#define NV_PFAULT_CLIENT_GPC_T1_13 0x00000026 /* */
#define NV_PFAULT_CLIENT_GPC_T1_14 0x00000027 /* */
#define NV_PFAULT_CLIENT_GPC_T1_15 0x00000028 /* */
#define NV_PFAULT_CLIENT_GPC_TPCCS_0 0x00000029 /* */
#define NV_PFAULT_CLIENT_GPC_TPCCS_1 0x0000002A /* */
#define NV_PFAULT_CLIENT_GPC_TPCCS_2 0x0000002B /* */
#define NV_PFAULT_CLIENT_GPC_TPCCS_3 0x0000002C /* */
#define NV_PFAULT_CLIENT_GPC_TPCCS_4 0x0000002D /* */
#define NV_PFAULT_CLIENT_GPC_TPCCS_5 0x0000002E /* */
#define NV_PFAULT_CLIENT_GPC_TPCCS_6 0x0000002F /* */
#define NV_PFAULT_CLIENT_GPC_TPCCS_7 0x00000030 /* */
#define NV_PFAULT_CLIENT_GPC_PE_8 0x00000031 /* */
#define NV_PFAULT_CLIENT_GPC_TPCCS_8 0x00000033 /* */
#define NV_PFAULT_CLIENT_GPC_T1_16 0x00000035 /* */
#define NV_PFAULT_CLIENT_GPC_T1_17 0x00000036 /* */
#define NV_PFAULT_CLIENT_GPC_ROP_0 0x00000070 /* */
#define NV_PFAULT_CLIENT_GPC_ROP_1 0x00000071 /* */
#define NV_PFAULT_CLIENT_GPC_GPM 0x00000017 /* */
#define NV_PFAULT_CLIENT_HUB_VIP 0x00000000 /* */
#define NV_PFAULT_CLIENT_HUB_CE0 0x00000001 /* */
#define NV_PFAULT_CLIENT_HUB_CE1 0x00000002 /* */
#define NV_PFAULT_CLIENT_HUB_DNISO 0x00000003 /* */
#define NV_PFAULT_CLIENT_HUB_DISPNISO 0x00000003 /* */
#define NV_PFAULT_CLIENT_HUB_FE0 0x00000004 /* */
#define NV_PFAULT_CLIENT_HUB_FE 0x00000004 /* */
#define NV_PFAULT_CLIENT_HUB_FECS0 0x00000005 /* */
#define NV_PFAULT_CLIENT_HUB_FECS 0x00000005 /* */
#define NV_PFAULT_CLIENT_HUB_HOST 0x00000006 /* */
#define NV_PFAULT_CLIENT_HUB_HOST_CPU 0x00000007 /* */
#define NV_PFAULT_CLIENT_HUB_HOST_CPU_NB 0x00000008 /* */
#define NV_PFAULT_CLIENT_HUB_ISO 0x00000009 /* */
#define NV_PFAULT_CLIENT_HUB_MMU 0x0000000A /* */
#define NV_PFAULT_CLIENT_HUB_NVDEC0 0x0000000B /* */
#define NV_PFAULT_CLIENT_HUB_NVDEC 0x0000000B /* */
#define NV_PFAULT_CLIENT_HUB_CE3 0x0000000C /* */
#define NV_PFAULT_CLIENT_HUB_NVENC1 0x0000000D /* */
#define NV_PFAULT_CLIENT_HUB_NISO 0x0000000E /* */
#define NV_PFAULT_CLIENT_HUB_ACTRS 0x0000000E /* */
#define NV_PFAULT_CLIENT_HUB_P2P 0x0000000F /* */
#define NV_PFAULT_CLIENT_HUB_PD 0x00000010 /* */
#define NV_PFAULT_CLIENT_HUB_PERF0 0x00000011 /* */
#define NV_PFAULT_CLIENT_HUB_PERF 0x00000011 /* */
#define NV_PFAULT_CLIENT_HUB_PMU 0x00000012 /* */
#define NV_PFAULT_CLIENT_HUB_RASTERTWOD 0x00000013 /* */
#define NV_PFAULT_CLIENT_HUB_SCC 0x00000014 /* */
#define NV_PFAULT_CLIENT_HUB_SCC_NB 0x00000015 /* */
#define NV_PFAULT_CLIENT_HUB_SEC 0x00000016 /* */
#define NV_PFAULT_CLIENT_HUB_SSYNC 0x00000017 /* */
#define NV_PFAULT_CLIENT_HUB_GRCOPY 0x00000018 /* */
#define NV_PFAULT_CLIENT_HUB_CE2 0x00000018 /* */
#define NV_PFAULT_CLIENT_HUB_XV 0x00000019 /* */
#define NV_PFAULT_CLIENT_HUB_MMU_NB 0x0000001A /* */
#define NV_PFAULT_CLIENT_HUB_NVENC0 0x0000001B /* */
#define NV_PFAULT_CLIENT_HUB_NVENC 0x0000001B /* */
#define NV_PFAULT_CLIENT_HUB_DFALCON 0x0000001C /* */
#define NV_PFAULT_CLIENT_HUB_SKED0 0x0000001D /* */
#define NV_PFAULT_CLIENT_HUB_SKED 0x0000001D /* */
#define NV_PFAULT_CLIENT_HUB_AFALCON 0x0000001E /* */
#define NV_PFAULT_CLIENT_HUB_DONT_CARE 0x0000001F /* */
#define NV_PFAULT_CLIENT_HUB_HSCE0 0x00000020 /* */
#define NV_PFAULT_CLIENT_HUB_HSCE1 0x00000021 /* */
#define NV_PFAULT_CLIENT_HUB_HSCE2 0x00000022 /* */
#define NV_PFAULT_CLIENT_HUB_HSCE3 0x00000023 /* */
#define NV_PFAULT_CLIENT_HUB_HSCE4 0x00000024 /* */
#define NV_PFAULT_CLIENT_HUB_HSCE5 0x00000025 /* */
#define NV_PFAULT_CLIENT_HUB_HSCE6 0x00000026 /* */
#define NV_PFAULT_CLIENT_HUB_HSCE7 0x00000027 /* */
#define NV_PFAULT_CLIENT_HUB_HSCE8 0x00000028 /* */
#define NV_PFAULT_CLIENT_HUB_HSCE9 0x00000029 /* */
#define NV_PFAULT_CLIENT_HUB_HSHUB 0x0000002A /* */
#define NV_PFAULT_CLIENT_HUB_PTP_X0 0x0000002B /* */
#define NV_PFAULT_CLIENT_HUB_PTP_X1 0x0000002C /* */
#define NV_PFAULT_CLIENT_HUB_PTP_X2 0x0000002D /* */
#define NV_PFAULT_CLIENT_HUB_PTP_X3 0x0000002E /* */
#define NV_PFAULT_CLIENT_HUB_PTP_X4 0x0000002F /* */
#define NV_PFAULT_CLIENT_HUB_PTP_X5 0x00000030 /* */
#define NV_PFAULT_CLIENT_HUB_NVENC2 0x00000033 /* */
#define NV_PFAULT_CLIENT_HUB_VPR_SCRUBBER0 0x00000034 /* */
#define NV_PFAULT_CLIENT_HUB_VPR_SCRUBBER1 0x00000035 /* */
#define NV_PFAULT_CLIENT_HUB_DWBIF 0x00000036 /* */
#define NV_PFAULT_CLIENT_HUB_FBFALCON 0x00000037 /* */
#define NV_PFAULT_CLIENT_HUB_CE_SHIM 0x00000038 /* */
#define NV_PFAULT_CLIENT_HUB_GSP 0x00000039 /* */
#define NV_PFAULT_CLIENT_HUB_NVDEC1 0x0000003A /* */
#define NV_PFAULT_CLIENT_HUB_NVDEC2 0x0000003B /* */
#define NV_PFAULT_CLIENT_HUB_NVJPG0 0x0000003C /* */
#define NV_PFAULT_CLIENT_HUB_NVDEC3 0x0000003D /* */
#define NV_PFAULT_CLIENT_HUB_NVDEC4 0x0000003E /* */
#define NV_PFAULT_CLIENT_HUB_OFA0 0x0000003F /* */
#define NV_PFAULT_CLIENT_HUB_HSCE10 0x00000040 /* */
#define NV_PFAULT_CLIENT_HUB_HSCE11 0x00000041 /* */
#define NV_PFAULT_CLIENT_HUB_HSCE12 0x00000042 /* */
#define NV_PFAULT_CLIENT_HUB_HSCE13 0x00000043 /* */
#define NV_PFAULT_CLIENT_HUB_HSCE14 0x00000044 /* */
#define NV_PFAULT_CLIENT_HUB_HSCE15 0x00000045 /* */
#define NV_PFAULT_CLIENT_HUB_FE1 0x0000004E /* */
#define NV_PFAULT_CLIENT_HUB_FE2 0x0000004F /* */
#define NV_PFAULT_CLIENT_HUB_FE3 0x00000050 /* */
#define NV_PFAULT_CLIENT_HUB_FE4 0x00000051 /* */
#define NV_PFAULT_CLIENT_HUB_FE5 0x00000052 /* */
#define NV_PFAULT_CLIENT_HUB_FE6 0x00000053 /* */
#define NV_PFAULT_CLIENT_HUB_FE7 0x00000054 /* */
#define NV_PFAULT_CLIENT_HUB_FECS1 0x00000055 /* */
#define NV_PFAULT_CLIENT_HUB_FECS2 0x00000056 /* */
#define NV_PFAULT_CLIENT_HUB_FECS3 0x00000057 /* */
#define NV_PFAULT_CLIENT_HUB_FECS4 0x00000058 /* */
#define NV_PFAULT_CLIENT_HUB_FECS5 0x00000059 /* */
#define NV_PFAULT_CLIENT_HUB_FECS6 0x0000005A /* */
#define NV_PFAULT_CLIENT_HUB_FECS7 0x0000005B /* */
#define NV_PFAULT_CLIENT_HUB_SKED1 0x0000005C /* */
#define NV_PFAULT_CLIENT_HUB_SKED2 0x0000005D /* */
#define NV_PFAULT_CLIENT_HUB_SKED3 0x0000005E /* */
#define NV_PFAULT_CLIENT_HUB_SKED4 0x0000005F /* */
#define NV_PFAULT_CLIENT_HUB_SKED5 0x00000060 /* */
#define NV_PFAULT_CLIENT_HUB_SKED6 0x00000061 /* */
#define NV_PFAULT_CLIENT_HUB_SKED7 0x00000062 /* */
#define NV_PFAULT_CLIENT_HUB_ESC 0x00000063 /* */
#define NV_PFAULT_CLIENT_HUB_NVDEC5 0x0000006F /* */
#define NV_PFAULT_CLIENT_HUB_NVDEC6 0x00000070 /* */
#define NV_PFAULT_CLIENT_HUB_NVDEC7 0x00000071 /* */
#define NV_PFAULT_CLIENT_HUB_NVJPG1 0x00000072 /* */
#define NV_PFAULT_CLIENT_HUB_NVJPG2 0x00000073 /* */
#define NV_PFAULT_CLIENT_HUB_NVJPG3 0x00000074 /* */
#define NV_PFAULT_CLIENT_HUB_NVJPG4 0x00000075 /* */
#define NV_PFAULT_CLIENT_HUB_NVJPG5 0x00000076 /* */
#define NV_PFAULT_CLIENT_HUB_NVJPG6 0x00000077 /* */
#define NV_PFAULT_CLIENT_HUB_NVJPG7 0x00000078 /* */
#define NV_PFAULT_CLIENT_HUB_FSP 0x00000079 /* */
#endif // __gh100_dev_fault_h__

20
src/common/inc/swref/published/hopper/gh100/dev_fb.h
View File

@@ -30,24 +30,4 @@
#define NV_PFB_FBHUB_PCIE_FLUSH_SYSMEM_ADDR_HI_ADR 31:0 /* RWIVF */
#define NV_PFB_FBHUB_PCIE_FLUSH_SYSMEM_ADDR_HI_ADR_MASK 0x000FFFFF /* ----V */
#define NV_PFB_PRI_MMU_L2TLB_ECC_UNCORRECTED_ERR_COUNT 0x00100E78 /* RW-4R */
#define NV_PFB_PRI_MMU_L2TLB_ECC_UNCORRECTED_ERR_COUNT 0x00100E78 /* RW-4R */
#define NV_PFB_PRI_MMU_L2TLB_ECC_UNCORRECTED_ERR_COUNT_TOTAL 15:0 /* RWEVF */
#define NV_PFB_PRI_MMU_L2TLB_ECC_UNCORRECTED_ERR_COUNT_TOTAL_INIT 0 /* RWE-V */
#define NV_PFB_PRI_MMU_L2TLB_ECC_UNCORRECTED_ERR_COUNT_UNIQUE 31:16 /* RWEVF */
#define NV_PFB_PRI_MMU_L2TLB_ECC_UNCORRECTED_ERR_COUNT_UNIQUE_INIT 0 /* RWE-V */
#define NV_PFB_PRI_MMU_HUBTLB_ECC_UNCORRECTED_ERR_COUNT 0x00100E8C /* RW-4R */
#define NV_PFB_PRI_MMU_HUBTLB_ECC_UNCORRECTED_ERR_COUNT 0x00100E8C /* RW-4R */
#define NV_PFB_PRI_MMU_HUBTLB_ECC_UNCORRECTED_ERR_COUNT_TOTAL 15:0 /* RWEVF */
#define NV_PFB_PRI_MMU_HUBTLB_ECC_UNCORRECTED_ERR_COUNT_TOTAL_INIT 0 /* RWE-V */
#define NV_PFB_PRI_MMU_HUBTLB_ECC_UNCORRECTED_ERR_COUNT_UNIQUE 31:16 /* RWEVF */
#define NV_PFB_PRI_MMU_HUBTLB_ECC_UNCORRECTED_ERR_COUNT_UNIQUE_INIT 0 /* RWE-V */
#define NV_PFB_PRI_MMU_FILLUNIT_ECC_UNCORRECTED_ERR_COUNT 0x00100EA0 /* RW-4R */
#define NV_PFB_PRI_MMU_FILLUNIT_ECC_UNCORRECTED_ERR_COUNT 0x00100EA0 /* RW-4R */
#define NV_PFB_PRI_MMU_FILLUNIT_ECC_UNCORRECTED_ERR_COUNT_TOTAL 15:0 /* RWEVF */
#define NV_PFB_PRI_MMU_FILLUNIT_ECC_UNCORRECTED_ERR_COUNT_TOTAL_INIT 0 /* RWE-V */
#define NV_PFB_PRI_MMU_FILLUNIT_ECC_UNCORRECTED_ERR_COUNT_UNIQUE 31:16 /* RWEVF */
#define NV_PFB_PRI_MMU_FILLUNIT_ECC_UNCORRECTED_ERR_COUNT_UNIQUE_INIT 0 /* RWE-V */
#endif // __gh100_dev_fb_h_

18
src/common/inc/swref/published/hopper/gh100/dev_gsp.h
View File

@@ -31,4 +31,22 @@
#define NV_PGSP_FALCON_ENGINE_RESET_STATUS_ASSERTED 0x00000000 /* R-E-V */
#define NV_PGSP_FALCON_ENGINE_RESET_STATUS_DEASSERTED 0x00000002 /* R---V */
#define NV_PGSP_MAILBOX(i) (0x110804+(i)*4) /* RW-4A */
#define NV_PGSP_EMEMC(i) (0x110ac0+(i)*8) /* RW-4A */
#define NV_PGSP_EMEMC__SIZE_1 8 /* */
#define NV_PGSP_EMEMC_OFFS 7:2 /* RWIVF */
#define NV_PGSP_EMEMC_OFFS_INIT 0x00000000 /* RWI-V */
#define NV_PGSP_EMEMC_BLK 15:8 /* RWIVF */
#define NV_PGSP_EMEMC_BLK_INIT 0x00000000 /* RWI-V */
#define NV_PGSP_EMEMC_AINCW 24:24 /* RWIVF */
#define NV_PGSP_EMEMC_AINCW_INIT 0x00000000 /* RWI-V */
#define NV_PGSP_EMEMC_AINCW_TRUE 0x00000001 /* RW--V */
#define NV_PGSP_EMEMC_AINCW_FALSE 0x00000000 /* RW--V */
#define NV_PGSP_EMEMC_AINCR 25:25 /* RWIVF */
#define NV_PGSP_EMEMC_AINCR_INIT 0x00000000 /* RWI-V */
#define NV_PGSP_EMEMC_AINCR_TRUE 0x00000001 /* RW--V */
#define NV_PGSP_EMEMC_AINCR_FALSE 0x00000000 /* RW--V */
#define NV_PGSP_EMEMD(i) (0x110ac4+(i)*8) /* RW-4A */
#define NV_PGSP_EMEMD__SIZE_1 8 /* */
#define NV_PGSP_EMEMD_DATA 31:0 /* RWXVF */
#endif // __gh100_dev_gsp_h__

29
src/common/inc/swref/published/hopper/gh100/dev_perf.h Normal file
View File

@@ -0,0 +1,29 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gh100_dev_perf_h__
#define __gh100_dev_perf_h__
#define NV_PERF_PMMSYSROUTER_NUM_USER_STREAMING_CHANNELS 9 /* */
#endif // __gh100_dev_perf_h__

44
src/common/inc/swref/published/hopper/gh100/dev_vm.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2022-23 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2022-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -65,4 +65,46 @@
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF_EN_CLEAR_VALUE 31:0 /* RWIVF */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF_EN_CLEAR_VALUE_INIT 0x00000000 /* R-I-V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_PAGE_FAULT_CTRL 0x00003070 /* RW-4R */
#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR1_BLOCK_LOW_ADDR 0x00000F60 /* RW-4R */
#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR1_BLOCK_LOW_ADDR_MAP 31:10 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR1_BLOCK_LOW_ADDR_BAR1_PENDING 0:0 /* R-IUF */
#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR1_BLOCK_LOW_ADDR_BAR1_PENDING_EMPTY 0x00000000 /* R-I-V */
#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR1_BLOCK_LOW_ADDR_BAR1_PENDING_BUSY 0x00000001 /* R---V */
#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR1_BLOCK_LOW_ADDR_BAR1_OUTSTANDING 1:1 /* R-IUF */
#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR1_BLOCK_LOW_ADDR_BAR1_OUTSTANDING_FALSE 0x00000000 /* R-I-V */
#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR1_BLOCK_LOW_ADDR_BAR1_OUTSTANDING_TRUE 0x00000001 /* R---V */
#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR1_BLOCK_LOW_ADDR_MODE 9:9 /* RWIUF */
#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR1_BLOCK_LOW_ADDR_MODE_PHYSICAL 0x00000000 /* RWI-V */
#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR1_BLOCK_LOW_ADDR_MODE_VIRTUAL 0x00000001 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR1_BLOCK_LOW_ADDR_TARGET 11:10 /* RWIUF */
#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR1_BLOCK_LOW_ADDR_TARGET_VID_MEM 0x00000000 /* RWI-V */
#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR1_BLOCK_LOW_ADDR_TARGET_SYS_MEM_COHERENT 0x00000002 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR1_BLOCK_LOW_ADDR_TARGET_SYS_MEM_NONCOHERENT 0x00000003 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR1_BLOCK_LOW_ADDR_PTR 31:12 /* RWIUF */
#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR1_BLOCK_LOW_ADDR_PTR_0 0x00000000 /* RWI-V */
#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR1_BLOCK_HIGH_ADDR 0x00000F64 /* RW-4R */
#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR1_BLOCK_HIGH_ADDR_PTR 31:0 /* RWIUF */
#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR1_BLOCK_HIGH_ADDR_PTR_0 0x00000000 /* RWI-V */
#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR1_BLOCK_PTR_SHIFT 12 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR2_BLOCK_LOW_ADDR 0x00000F70 /* RW-4R */
#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR2_BLOCK_LOW_ADDR_MAP 31:10 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR2_BLOCK_LOW_ADDR_BAR2_PENDING 0:0 /* R-IUF */
#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR2_BLOCK_LOW_ADDR_BAR2_PENDING_EMPTY 0x00000000 /* R-I-V */
#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR2_BLOCK_LOW_ADDR_BAR2_PENDING_BUSY 0x00000001 /* R---V */
#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR2_BLOCK_LOW_ADDR_BAR2_OUTSTANDING 1:1 /* R-IUF */
#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR2_BLOCK_LOW_ADDR_BAR2_OUTSTANDING_FALSE 0x00000000 /* R-I-V */
#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR2_BLOCK_LOW_ADDR_BAR2_OUTSTANDING_TRUE 0x00000001 /* R---V */
#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR2_BLOCK_LOW_ADDR_MODE 9:9 /* RWIUF */
#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR2_BLOCK_LOW_ADDR_MODE_PHYSICAL 0x00000000 /* RWI-V */
#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR2_BLOCK_LOW_ADDR_MODE_VIRTUAL 0x00000001 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR2_BLOCK_LOW_ADDR_TARGET 11:10 /* RWIUF */
#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR2_BLOCK_LOW_ADDR_TARGET_VID_MEM 0x00000000 /* RWI-V */
#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR2_BLOCK_LOW_ADDR_TARGET_SYS_MEM_COHERENT 0x00000002 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR2_BLOCK_LOW_ADDR_TARGET_SYS_MEM_NONCOHERENT 0x00000003 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR2_BLOCK_LOW_ADDR_PTR 31:12 /* RWIUF */
#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR2_BLOCK_LOW_ADDR_PTR_0 0x00000000 /* RWI-V */
#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR2_BLOCK_HIGH_ADDR 0x00000F74 /* RW-4R */
#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR2_BLOCK_HIGH_ADDR_PTR (52-33):0 /* RWIUF */
#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR2_BLOCK_HIGH_ADDR_PTR_0 0x00000000 /* RWI-V */
#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR2_BLOCK_PTR_SHIFT 12 /* */
#endif // __gh100_dev_vm_h__

3
src/common/inc/swref/published/hopper/gh100/dev_xtl_ep_pcfg_gpu.h
View File

@@ -24,6 +24,8 @@
#ifndef __gh100_dev_xtl_ep_pcfg_gpu_h__
#define __gh100_dev_xtl_ep_pcfg_gpu_h__
#define NV_EP_PCFG_GPU_ID 0x00000000 /* R--4R */
#define NV_EP_PCFG_GPU_ID_VENDOR 15:0 /* R-EVF */
#define NV_EP_PCFG_GPU_ID_VENDOR_NVIDIA 0x000010DE /* R-E-V */
#define NV_EP_PCFG_GPU_CTRL_CMD_AND_STATUS 0x00000004 /* RW-4R */
#define NV_EP_PCFG_GPU_CTRL_CMD_AND_STATUS_CMD_IO_SPACE 0:0 /* RWIVF */
#define NV_EP_PCFG_GPU_CTRL_CMD_AND_STATUS_CMD_IO_SPACE_ENABLE 0x00000001 /* RW--V */
@@ -114,4 +116,5 @@
#define NV_EP_PCFG_GPU_VSEC_DEBUG_SEC_FAULT_WDG 14:14 /* R-CVF */
#define NV_EP_PCFG_GPU_VSEC_DEBUG_SEC_FAULT_BOOTFSM 15:15 /* R-CVF */
#define NV_EP_PCFG_GPU_VSEC_DEBUG_SEC_IFF_POS 22:16 /* R-CVF */
#define NV_EP_PCFG_GPU_L1_PM_SS_CONTROL_1_REGISTER 0x00000298 /* RW-4R */
#endif // __gh100_dev_xtl_ep_pcfg_gpu_h__

5
src/common/inc/swref/published/hopper/gh100/hwproject.h
View File

@@ -21,9 +21,6 @@
* DEALINGS IN THE SOFTWARE.
*/
#define NV_CHIP_EXTENDED_SYSTEM_PHYSICAL_ADDRESS_BITS 52
#define NV_LTC_PRI_STRIDE 8192
#define NV_LTS_PRI_STRIDE 512
#define NV_FBPA_PRI_STRIDE 16384
#define NV_SCAL_LITTER_NUM_FBPAS 24
#define NV_XPL_BASE_ADDRESS 540672
#define NV_XTL_BASE_ADDRESS 593920
#define NV_FBPA_PRI_STRIDE 16384

5
src/common/inc/swref/published/maxwell/gm107/dev_boot.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2021 NVIDIA CORPORATION & AFFILIATES
* SPDX-FileCopyrightText: Copyright (c) 2003-2023 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -40,4 +40,7 @@
#define NV_PMC_ENABLE_DEVICE__SIZE_1 32 /* */
#define NV_PMC_ENABLE_DEVICE_DISABLE 0x00000000 /* */
#define NV_PMC_ENABLE_DEVICE_ENABLE 0x00000001 /* */
#define NV_PMC_ENABLE_PDISP 30:30 /* RWIVF */
#define NV_PMC_ENABLE_PDISP_DISABLED 0x00000000 /* RW--V */
#define NV_PMC_ENABLE_PDISP_ENABLED 0x00000001 /* RWI-V */
#endif // __gm107_dev_boot_h__

33
src/common/inc/swref/published/maxwell/gm107/dev_bus.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES
* SPDX-FileCopyrightText: Copyright (c) 2003-2023 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -48,6 +48,18 @@
#define NV_PBUS_BAR0_WINDOW_TARGET_SYS_MEM_COHERENT 0x00000002 /* RW--V */
#define NV_PBUS_BAR0_WINDOW_TARGET_SYS_MEM_NONCOHERENT 0x00000003 /* RW--V */
#define NV_PBUS_BAR0_WINDOW_BASE_SHIFT 16 /* */
#define NV_PBUS_BAR1_BLOCK 0x00001704 /* RW-4R */
#define NV_PBUS_BAR1_BLOCK_MAP 29:0 /* RWXUF */
#define NV_PBUS_BAR1_BLOCK_PTR 27:0 /* RWIUF */
#define NV_PBUS_BAR1_BLOCK_PTR_0 0x00000000 /* RWI-V */
#define NV_PBUS_BAR1_BLOCK_TARGET 29:28 /* RWIUF */
#define NV_PBUS_BAR1_BLOCK_TARGET_VID_MEM 0x00000000 /* RWI-V */
#define NV_PBUS_BAR1_BLOCK_TARGET_SYS_MEM_COHERENT 0x00000002 /* RW--V */
#define NV_PBUS_BAR1_BLOCK_TARGET_SYS_MEM_NONCOHERENT 0x00000003 /* RW--V */
#define NV_PBUS_BAR1_BLOCK_MODE 31:31 /* RWIUF */
#define NV_PBUS_BAR1_BLOCK_MODE_PHYSICAL 0x00000000 /* RWI-V */
#define NV_PBUS_BAR1_BLOCK_MODE_VIRTUAL 0x00000001 /* RW--V */
#define NV_PBUS_BAR1_BLOCK_PTR_SHIFT 12 /* */
#define NV_PBUS_BAR2_BLOCK 0x00001714 /* RW-4R */
#define NV_PBUS_BAR2_BLOCK_MAP 29:0 /* RWXUF */
#define NV_PBUS_BAR2_BLOCK_PTR 27:0 /* RWIUF */
@@ -64,4 +76,23 @@
#define NV_PBUS_BAR2_BLOCK_MODE_PHYSICAL 0x00000000 /* RWI-V */
#define NV_PBUS_BAR2_BLOCK_MODE_VIRTUAL 0x00000001 /* RW--V */
#define NV_PBUS_BAR2_BLOCK_PTR_SHIFT 12 /* */
#define NV_PBUS_BIND_STATUS 0x00001710 /* R--4R */
#define NV_PBUS_BIND_STATUS_BAR1_PENDING 0:0 /* R-IUF */
#define NV_PBUS_BIND_STATUS_BAR1_PENDING_EMPTY 0x00000000 /* R-I-V */
#define NV_PBUS_BIND_STATUS_BAR1_PENDING_BUSY 0x00000001 /* R---V */
#define NV_PBUS_BIND_STATUS_BAR1_OUTSTANDING 1:1 /* R-IUF */
#define NV_PBUS_BIND_STATUS_BAR1_OUTSTANDING_FALSE 0x00000000 /* R-I-V */
#define NV_PBUS_BIND_STATUS_BAR1_OUTSTANDING_TRUE 0x00000001 /* R---V */
#define NV_PBUS_BIND_STATUS_BAR2_PENDING 2:2 /* R-IUF */
#define NV_PBUS_BIND_STATUS_BAR2_PENDING_EMPTY 0x00000000 /* R-I-V */
#define NV_PBUS_BIND_STATUS_BAR2_PENDING_BUSY 0x00000001 /* R---V */
#define NV_PBUS_BIND_STATUS_BAR2_OUTSTANDING 3:3 /* R-IUF */
#define NV_PBUS_BIND_STATUS_BAR2_OUTSTANDING_FALSE 0x00000000 /* R-I-V */
#define NV_PBUS_BIND_STATUS_BAR2_OUTSTANDING_TRUE 0x00000001 /* R---V */
#define NV_PBUS_BIND_STATUS_IFB_PENDING 4:4 /* R-IUF */
#define NV_PBUS_BIND_STATUS_IFB_PENDING_EMPTY 0x00000000 /* R-I-V */
#define NV_PBUS_BIND_STATUS_IFB_PENDING_BUSY 0x00000001 /* R---V */
#define NV_PBUS_BIND_STATUS_IFB_OUTSTANDING 5:5 /* R-IUF */
#define NV_PBUS_BIND_STATUS_IFB_OUTSTANDING_FALSE 0x00000000 /* R-I-V */
#define NV_PBUS_BIND_STATUS_IFB_OUTSTANDING_TRUE 0x00000001 /* R---V */
#endif // __gm107_dev_bus_h__

33
src/common/inc/swref/published/maxwell/gm107/dev_fifo.h Normal file
View File

@@ -0,0 +1,33 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gm107_dev_fifo_h__
#define __gm107_dev_fifo_h__
#define NV_PFIFO_FB_IFACE 0x000026f0 /* RW-4R */
#define NV_PFIFO_FB_IFACE_CONTROL 0:0 /* RWIUF */
#define NV_PFIFO_FB_IFACE_CONTROL_DISABLE 0x00000000 /* RW--V */
#define NV_PFIFO_FB_IFACE_CONTROL_ENABLE 0x00000001 /* RWI-V */
#define NV_PFIFO_FB_IFACE_STATUS 4:4 /* R-IUF */
#define NV_PFIFO_FB_IFACE_STATUS_DISABLED 0x00000000 /* R---V */
#define NV_PFIFO_FB_IFACE_STATUS_ENABLED 0x00000001 /* R-I-V */
#endif // __gm107_dev_fifo_h__

4
src/common/inc/swref/published/maxwell/gm107/dev_nv_xve.h
View File

@@ -160,5 +160,7 @@
#define NV_XVE_AER_CORR_ERR_ADVISORY_NONFATAL_NOT_ACTIVE 0x00000000 /* R-C-V */
#define NV_XVE_AER_CORR_ERR_ADVISORY_NONFATAL_ACTIVE 0x00000001 /* R---V */
#define NV_XVE_AER_CORR_ERR_ADVISORY_NONFATAL_CLEAR 0x00000001 /* -W--C */
#define NV_XVE_CYA_2 0x00000704 /* RW-4R */
#define NV_XVE_CYA_2 0x00000704 /* RW-4R */
#define NV_XVE_DEVICE_CONTROL_STATUS_2 0x000000A0 /* RWI4R */
#define NV_XVE_L1_PM_SUBSTATES_CTRL1 0x00000260 /* RW-4R */
#endif // __gm107_dev_nv_xve_h__

44
src/common/inc/swref/published/maxwell/gm107/dev_pri_ringstation_sys.h Normal file
View File

@@ -0,0 +1,44 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gm107_dev_pri_ringstation_sys_h__
#define __gm107_dev_pri_ringstation_sys_h__
#define NV_PPRIV_SYS_PRI_ERROR_CODE 31:8 /* --XVF */
#define NV_PPRIV_SYS_PRI_ERROR_CODE_HOST_FECS_ERR 0xBAD00F /* ----V */
#define NV_PPRIV_SYS_PRI_ERROR_CODE_HOST_PRI_TIMEOUT 0xBAD001 /* ----V */
#define NV_PPRIV_SYS_PRI_ERROR_CODE_HOST_FB_ACK_TIMEOUT 0xBAD0B0 /* ----V */
#define NV_PPRIV_SYS_PRI_ERROR_CODE_FECS_PRI_TIMEOUT 0xBADF10 /* ----V */
#define NV_PPRIV_SYS_PRI_ERROR_CODE_FECS_PRI_DECODE 0xBADF11 /* ----V */
#define NV_PPRIV_SYS_PRI_ERROR_CODE_FECS_PRI_RESET 0xBADF12 /* ----V */
#define NV_PPRIV_SYS_PRI_ERROR_CODE_FECS_PRI_FLOORSWEEP 0xBADF13 /* ----V */
#define NV_PPRIV_SYS_PRI_ERROR_CODE_FECS_PRI_STUCK_ACK 0xBADF14 /* ----V */
#define NV_PPRIV_SYS_PRI_ERROR_CODE_FECS_PRI_0_EXPECTED_ACK 0xBADF15 /* ----V */
#define NV_PPRIV_SYS_PRI_ERROR_CODE_FECS_PRI_FENCE_ERROR 0xBADF16 /* ----V */
#define NV_PPRIV_SYS_PRI_ERROR_CODE_FECS_PRI_SUBID_ERROR 0xBADF17 /* ----V */
#define NV_PPRIV_SYS_PRI_ERROR_CODE_FECS_PRI_ORPHAN 0xBADF20 /* ----V */
#define NV_PPRIV_SYS_PRI_ERROR_CODE_FECS_DEAD_RING 0xBADF30 /* ----V */
#define NV_PPRIV_SYS_PRI_ERROR_CODE_FECS_TRAP 0xBADF40 /* ----V */
#define NV_PPRIV_SYS_PRI_ERROR_CODE_FECS_PRI_CLIENT_ERR 0xBADF50 /* ----V */
#endif // __gm107_dev_pri_ringstation_sys_h__

13
src/common/inc/swref/published/maxwell/gm107/dev_ram.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2021 NVIDIA CORPORATION & AFFILIATES
* SPDX-FileCopyrightText: Copyright (c) 2003-2023 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -55,4 +55,15 @@
#define NV_RAMRL_ENTRY_TIMESLICE_TIMEOUT_128 0x00000080 /* RWI-V */
#define NV_RAMRL_ENTRY_SIZE 8 /* */
#define NV_RAMRL_ENTRY_TSG_LENGTH_MAX 0x00000020 /* RW--V */
#define NV_RAMIN_PAGE_DIR_BASE_TARGET (128*32+1):(128*32+0) /* RWXUF */
#define NV_RAMIN_PAGE_DIR_BASE_TARGET_VID_MEM 0x00000000 /* RW--V */
#define NV_RAMIN_PAGE_DIR_BASE_TARGET_SYS_MEM_COHERENT 0x00000002 /* RW--V */
#define NV_RAMIN_PAGE_DIR_BASE_TARGET_SYS_MEM_NONCOHERENT 0x00000003 /* RW--V */
#define NV_RAMIN_PAGE_DIR_BASE_VOL (128*32+2):(128*32+2) /* RWXUF */
#define NV_RAMIN_PAGE_DIR_BASE_VOL_TRUE 0x00000001 /* RW--V */
#define NV_RAMIN_PAGE_DIR_BASE_VOL_FALSE 0x00000000 /* RW--V */
#define NV_RAMIN_PAGE_DIR_BASE_LO (128*32+31):(128*32+12) /* RWXUF */
#define NV_RAMIN_PAGE_DIR_BASE_HI (129*32+7):(129*32+0) /* RWXUF */
#define NV_RAMIN_ADR_LIMIT_LO (130*32+31):(130*32+12) /* RWXUF */
#define NV_RAMIN_ADR_LIMIT_HI (131*32+7):(131*32+0) /* RWXUF */
#endif // __gm107_dev_ram_h__

63
src/common/inc/swref/published/maxwell/gm200/dev_boot.h Normal file
View File

@@ -0,0 +1,63 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2021 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gm200_dev_boot_h__
#define __gm200_dev_boot_h__
#define NV_PMC_ENABLE 0x00000200 /* RW-4R */
#define NV_PMC_ENABLE_PMEDIA 4:4 /* */
#define NV_PMC_ENABLE_PMEDIA_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_PMEDIA_ENABLED 0x00000001 /* */
#define NV_PMC_ENABLE_PFIFO 8:8 /* RWIVF */
#define NV_PMC_ENABLE_PFIFO_DISABLED 0x00000000 /* RWI-V */
#define NV_PMC_ENABLE_PFIFO_ENABLED 0x00000001 /* RW--V */
#define NV_PMC_ENABLE_PWR 13:13 /* */
#define NV_PMC_ENABLE_PWR_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_PWR_ENABLED 0x00000001 /* */
#define NV_PMC_ENABLE_PGRAPH 12:12 /* */
#define NV_PMC_ENABLE_PGRAPH_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_PGRAPH_ENABLED 0x00000001 /* */
#define NV_PMC_ENABLE_SEC 14:14 /* */
#define NV_PMC_ENABLE_SEC_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_SEC_ENABLED 0x00000001 /* */
#define NV_PMC_ENABLE_CE0 6:6 /* */
#define NV_PMC_ENABLE_CE0_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_CE0_ENABLED 0x00000001 /* */
#define NV_PMC_ENABLE_CE1 7:7 /* */
#define NV_PMC_ENABLE_CE1_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_CE1_ENABLED 0x00000001 /* */
#define NV_PMC_ENABLE_CE2 21:21 /* */
#define NV_PMC_ENABLE_CE2_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_CE2_ENABLED 0x00000001 /* */
#define NV_PMC_ENABLE_NVDEC 15:15 /* */
#define NV_PMC_ENABLE_NVDEC_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_NVDEC_ENABLED 0x00000001 /* */
#define NV_PMC_ENABLE_PDISP 30:30 /* RWIVF */
#define NV_PMC_ENABLE_PDISP_DISABLED 0x00000000 /* RW--V */
#define NV_PMC_ENABLE_PDISP_ENABLED 0x00000001 /* RWI-V */
#define NV_PMC_ENABLE_NVENC0 18:18 /* */
#define NV_PMC_ENABLE_NVENC0_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_NVENC0_ENABLED 0x00000001 /* */
#define NV_PMC_ENABLE_NVENC1 19:19 /* */
#define NV_PMC_ENABLE_NVENC1_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_NVENC1_ENABLED 0x00000001 /* */
#endif // __gm200_dev_boot_h__

28
src/common/inc/swref/published/maxwell/gm200/dev_fifo.h Normal file
View File

@@ -0,0 +1,28 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gm200_dev_fifo_h__
#define __gm200_dev_fifo_h__
#define NV_PFIFO_CFG0 0x00002004 /* R--4R */
#define NV_PFIFO_CFG0_NUM_PBDMA 7:0 /* R-IUF */
#endif // __gm200_dev_fifo_h__

8
src/common/inc/swref/published/nv_arch.h
View File

@@ -47,7 +47,6 @@
#define GPU_ARCHITECTURE_TURING GPU_ARCHITECTURE(_CLASSIC, 0x0160)
#define GPU_ARCHITECTURE_AMPERE GPU_ARCHITECTURE(_CLASSIC, 0x0170)
#define GPU_ARCHITECTURE_HOPPER GPU_ARCHITECTURE(_CLASSIC, 0x0180)
#define GPU_ARCHITECTURE_ADA GPU_ARCHITECTURE(_CLASSIC, 0x0190)
#define GPU_ARCHITECTURE_T12X GPU_ARCHITECTURE(_TEGRA, 0x0040)
@@ -93,18 +92,11 @@
#define GPU_IMPLEMENTATION_GA106 0x06
#define GPU_IMPLEMENTATION_GA107 0x07
#define GPU_IMPLEMENTATION_GA102F 0x0F
#define GPU_IMPLEMENTATION_GH100 0x00
#define GPU_IMPLEMENTATION_AD102 0x02
#define GPU_IMPLEMENTATION_AD103 0x03
#define GPU_IMPLEMENTATION_AD104 0x04
#define GPU_IMPLEMENTATION_AD106 0x06
#define GPU_IMPLEMENTATION_AD107 0x07
#define GPU_IMPLEMENTATION_T124 0x00

2
src/common/inc/swref/published/nv_ref.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 1993-2021 NVIDIA CORPORATION & AFFILIATES
* SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a

19
src/common/inc/swref/published/nvswitch/ls10/dev_fsp_pri.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2003-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -30,4 +30,21 @@
#define NV_PFSP_FALCON_COMMON_SCRATCH_GROUP_2__DEVICE_MAP 0x00000016 /* */
#define NV_PFSP_FALCON_COMMON_SCRATCH_GROUP_2_VAL 31:0 /* RWIVF */
#define NV_PFSP_FALCON_COMMON_SCRATCH_GROUP_2_VAL_INIT 0x00000000 /* RWI-V */
#define NV_PFSP_QUEUE_HEAD(i) (0x008F2c00+(i)*8) /* RW-4A */
#define NV_PFSP_QUEUE_TAIL(i) (0x008F2c04+(i)*8) /* RW-4A */
#define NV_PFSP_MSGQ_HEAD(i) (0x008F2c80+(i)*8) /* RW-4A */
#define NV_PFSP_MSGQ_TAIL(i) (0x008F2c84+(i)*8) /* RW-4A */
#define NV_PFSP_EMEMC(i) (0x008F2ac0+(i)*8) /* RW-4A */
#define NV_PFSP_EMEMC_OFFS 7:2 /* RWIVF */
#define NV_PFSP_EMEMC_BLK 15:8 /* RWIVF */
#define NV_PFSP_EMEMC_AINCW 24:24 /* RWIVF */
#define NV_PFSP_EMEMC_AINCW_TRUE 0x00000001 /* RW--V */
#define NV_PFSP_EMEMC_AINCR 25:25 /* RWIVF */
#define NV_PFSP_EMEMC_AINCR_TRUE 0x00000001 /* RW--V */
#define NV_PFSP_EMEMD(i) (0x008F2ac4+(i)*8) /* RW-4A */
#endif // __ls10_dev_fsp_pri_h__

47
src/common/inc/swref/published/nvswitch/ls10/dev_nvldl_ip.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2003-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -300,6 +300,51 @@
#define NV_NVLDL_TX_ERROR_COUNT_CTRL_CLEAR_R4_RETRY_CLEAR 0x00000001 /* -W--V */
#define NV_NVLDL_TX_ERROR_COUNT_CTRL_CLEAR_REPLAY 8:8 /* -WXVF */
#define NV_NVLDL_TX_ERROR_COUNT_CTRL_CLEAR_REPLAY_CLEAR 0x00000001 /* -W--V */
#define NV_NVLDL_TXIOBIST_SKIPCOMINSERTERGEN_0 0x00002e00 /* RW-4R */
#define NV_NVLDL_TXIOBIST_SKIPCOMINSERTERGEN_0__PRIV_LEVEL_MASK 0x00002ff4 /* */
#define NV_NVLDL_TXIOBIST_SKIPCOMINSERTERGEN_0_COM_SYMBOL_0 31:0 /* RWEUF */
#define NV_NVLDL_TXIOBIST_SKIPCOMINSERTERGEN_0_COM_SYMBOL_0_INIT 0x00000000 /* RWE-V */
#define NV_NVLDL_TXIOBIST_SKIPCOMINSERTERGEN_1 0x00002e04 /* RW-4R */
#define NV_NVLDL_TXIOBIST_SKIPCOMINSERTERGEN_1__PRIV_LEVEL_MASK 0x00002ff4 /* */
#define NV_NVLDL_TXIOBIST_SKIPCOMINSERTERGEN_1_COM_SYMBOL_1 31:0 /* RWEUF */
#define NV_NVLDL_TXIOBIST_SKIPCOMINSERTERGEN_1_COM_SYMBOL_1_INIT 0x00000000 /* RWE-V */
#define NV_NVLDL_TXIOBIST_SKIPCOMINSERTERGEN_2 0x00002e08 /* RW-4R */
#define NV_NVLDL_TXIOBIST_SKIPCOMINSERTERGEN_2__PRIV_LEVEL_MASK 0x00002ff4 /* */
#define NV_NVLDL_TXIOBIST_SKIPCOMINSERTERGEN_2_SKIP_SYMBOL_0 31:0 /* RWEUF */
#define NV_NVLDL_TXIOBIST_SKIPCOMINSERTERGEN_2_SKIP_SYMBOL_0_INIT 0x00000000 /* RWE-V */
#define NV_NVLDL_TXIOBIST_SKIPCOMINSERTERGEN_3 0x00002e0c /* RW-4R */
#define NV_NVLDL_TXIOBIST_SKIPCOMINSERTERGEN_3__PRIV_LEVEL_MASK 0x00002ff4 /* */
#define NV_NVLDL_TXIOBIST_SKIPCOMINSERTERGEN_3_SKIP_SYMBOL_1 31:0 /* RWEUF */
#define NV_NVLDL_TXIOBIST_SKIPCOMINSERTERGEN_3_SKIP_SYMBOL_1_INIT 0x00000000 /* RWE-V */
#define NV_NVLDL_TXIOBIST_SKIPCOMINSERTERGEN_4 0x00002e10 /* RW-4R */
#define NV_NVLDL_TXIOBIST_SKIPCOMINSERTERGEN_4__PRIV_LEVEL_MASK 0x00002ff4 /* */
#define NV_NVLDL_TXIOBIST_SKIPCOMINSERTERGEN_4_MASK_COM_OUT 0:0 /* RWEUF */
#define NV_NVLDL_TXIOBIST_SKIPCOMINSERTERGEN_4_MASK_COM_OUT_INIT 0x00000001 /* RWE-V */
#define NV_NVLDL_TXIOBIST_SKIPCOMINSERTERGEN_4_MASK_SKIP_OUT 1:1 /* RWEUF */
#define NV_NVLDL_TXIOBIST_SKIPCOMINSERTERGEN_4_MASK_SKIP_OUT_INIT 0x00000001 /* RWE-V */
#define NV_NVLDL_TXIOBIST_SKIPCOMINSERTERGEN_4_SEND_DATA_OUT 2:2 /* RWEUF */
#define NV_NVLDL_TXIOBIST_SKIPCOMINSERTERGEN_4_SEND_DATA_OUT_INIT 0x00000001 /* RWE-V */
#define NV_NVLDL_TXIOBIST_SKIPCOMINSERTERGEN_4_RESET_WORD_CNT_OUT 11:3 /* RWEUF */
#define NV_NVLDL_TXIOBIST_SKIPCOMINSERTERGEN_4_RESET_WORD_CNT_OUT_INIT 0x00000100 /* RWE-V */
#define NV_NVLDL_TXIOBIST_CONFIG 0x00002e14 /* RW-4R */
#define NV_NVLDL_TXIOBIST_CONFIG__PRIV_LEVEL_MASK 0x00002ff0 /* */
#define NV_NVLDL_TXIOBIST_CONFIG_STARTTEST 0:0 /* RWEUF */
#define NV_NVLDL_TXIOBIST_CONFIG_STARTTEST_INIT 0x00000000 /* RWE-V */
#define NV_NVLDL_TXIOBIST_CONFIG_CFGCLKGATEEN 1:1 /* RWEUF */
#define NV_NVLDL_TXIOBIST_CONFIG_CFGCLKGATEEN_INIT 0x00000000 /* RWE-V */
#define NV_NVLDL_TXIOBIST_CONFIG_DPG_PRBSSEEDLD 2:2 /* RWEUF */
#define NV_NVLDL_TXIOBIST_CONFIG_DPG_PRBSSEEDLD_INIT 0x00000000 /* RWE-V */
#define NV_NVLDL_TXIOBIST_CONFIG_PRBSALT 3:3 /* RWEUF */
#define NV_NVLDL_TXIOBIST_CONFIG_PRBSALT_NRZ 0x00000000 /* RWE-V */
#define NV_NVLDL_TXIOBIST_CONFIG_PRBSALT_PAM4 0x00000001 /* RW--V */
#define NV_NVLDL_TXIOBIST_CONFIGREG 0x00002e18 /* RW-4R */
#define NV_NVLDL_TXIOBIST_CONFIGREG__PRIV_LEVEL_MASK 0x00002ff0 /* */
#define NV_NVLDL_TXIOBIST_CONFIGREG_TX_BIST_EN_IN 2:2 /* RWEUF */
#define NV_NVLDL_TXIOBIST_CONFIGREG_TX_BIST_EN_IN_INIT 0x00000000 /* RWE-V */
#define NV_NVLDL_TXIOBIST_CONFIGREG_DISABLE_WIRED_ENABLE_IN 3:3 /* RWEUF */
#define NV_NVLDL_TXIOBIST_CONFIGREG_DISABLE_WIRED_ENABLE_IN_INIT 0x00000000 /* RWE-V */
#define NV_NVLDL_TXIOBIST_CONFIGREG_IO_BIST_MODE_IN 17:17 /* RWEUF */
#define NV_NVLDL_TXIOBIST_CONFIGREG_IO_BIST_MODE_IN_INIT 0x00000000 /* RWE-V */
#define NV_NVLDL_RX_SLSM_STATUS_RX 0x00003014 /* R--4R */
#define NV_NVLDL_RX_SLSM_STATUS_RX_SUBSTATE 3:0 /* R-EVF */
#define NV_NVLDL_RX_SLSM_STATUS_RX_SUBSTATE_STABLE 0x00000000 /* R-E-V */

14
src/common/inc/swref/published/nvswitch/ls10/dev_nvldl_ip_addendum.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2003-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -24,6 +24,18 @@
#ifndef __ls10_dev_nvldl_ip_addendum_h__
#define __ls10_dev_nvldl_ip_addendum_h__
#define NV_NVLDL_TXIOBIST_CONFIG_CFGCLKGATEEN_ENABLE 0x00000001 /* RWI-V */
#define NV_NVLDL_TXIOBIST_SKIPCOMINSERTERGEN_2_SKIP_SYMBOL_0_SYMBOL 0x7845bdcd /* RWIUF */
#define NV_NVLDL_TXIOBIST_SKIPCOMINSERTERGEN_3_SKIP_SYMBOL_1_SYMBOL 0x124507ff /* RWIUF */
#define NV_NVLDL_TXIOBIST_SKIPCOMINSERTERGEN_0_COM_SYMBOL_0_SYMBOL 0xad3d6c5b /* RWIUF */
#define NV_NVLDL_TXIOBIST_SKIPCOMINSERTERGEN_1_COM_SYMBOL_1_SYMBOL 0xbe35879e /* RWIUF */
#define NV_NVLDL_TXIOBIST_SKIPCOMINSERTERGEN_4_RESET_WORD_CNT_OUT_COUNT 0x000000bd /* RWI-V */
#define NV_NVLDL_TXIOBIST_CONFIGREG_TX_BIST_EN_IN_ENABLE 0x00000001 /* RWI-V */
#define NV_NVLDL_TXIOBIST_CONFIGREG_DISABLE_WIRED_ENABLE_IN_ENABLE 0x00000001 /* RWI-V */
#define NV_NVLDL_TXIOBIST_CONFIGREG_IO_BIST_MODE_IN_ENABLE 0x00000001 /* RWI-V */
#define NV_NVLDL_TXIOBIST_CONFIG_STARTTEST_ENABLE 0x00000001 /* RWI-V */
#define NV_NVLDL_TXIOBIST_CONFIG_DPG_PRBSSEEDLD_ENABLE 0x00000001 /* RWI-V */
#define NV_NVLDL_CRC_BIT_ERROR_RATE_SHORT_THRESHOLD_MAN 2:0
#define NV_NVLDL_CRC_BIT_ERROR_RATE_SHORT_THRESHOLD_MAN_DEFAULT 0x00000003
#define NV_NVLDL_CRC_BIT_ERROR_RATE_SHORT_THRESHOLD_EXP 3:3

9
src/common/inc/swref/published/nvswitch/ls10/dev_nvlipt_lnk_ip.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2003-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -635,4 +635,11 @@
#define NV_NVLIPT_LNK_CTRL_CAP_LOCAL_LINK_CHANNEL_ALI_SUPPORT 28:28 /* RWIVF */
#define NV_NVLIPT_LNK_CTRL_CAP_LOCAL_LINK_CHANNEL_ALI_SUPPORT_SUPPORTED 0x00000001 /* RWI-V */
#define NV_NVLIPT_LNK_CTRL_CAP_LOCAL_LINK_CHANNEL_ALI_SUPPORT_NOT_SUPPORTED 0x00000000 /* RW--V */
#define NV_NVLIPT_LNK_CTRL_CAP_LOCAL_LINK_AN1 0x00000688 /* RW-4R */
#define NV_NVLIPT_LNK_CTRL_CAP_LOCAL_LINK_AN1_PWRM_L1_SUPPORT 1:1 /* RWIVF */
#define NV_NVLIPT_LNK_CTRL_CAP_LOCAL_LINK_AN1_PWRM_L1_SUPPORT_SUPPORTED 0x00000001 /* RWI-V */
#define NV_NVLIPT_LNK_CTRL_CAP_LOCAL_LINK_AN1_PWRM_L1_SUPPORT_NOT_SUPPORTED 0x00000000 /* RW--V */
#define NV_NVLIPT_LNK_SCRATCH_WARM 0x000007c0 /* RW-4R */
#define NV_NVLIPT_LNK_SCRATCH_WARM_DATA 31:0 /* RWEVF */
#define NV_NVLIPT_LNK_SCRATCH_WARM_DATA_INIT 0xdeadbaad /* RWE-V */
#endif // __ls10_dev_nvlipt_lnk_ip_h__

16
src/common/inc/swref/published/nvswitch/ls10/dev_pmgr.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2003-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -82,4 +82,18 @@
#define NV_PMGR_GPIO_INPUT_CNTL_BYPASS_FILTER 10:10 /* */
#define NV_PMGR_GPIO_INPUT_CNTL_BYPASS_FILTER_NO 0x00000000 /* */
#define NV_PMGR_GPIO_INPUT_CNTL_BYPASS_FILTER_YES 0x00000001 /* */
#define NV_GPIO_OUTPUT_CNTL(i) (0x00021200 +((i) * 0x4)) /* RW-4A */
#define NV_GPIO_OUTPUT_CNTL_IO_OUTPUT 12:12 /* RWIVF */
#define NV_GPIO_OUTPUT_CNTL_IO_OUTPUT_INIT 0x00000000 /* R-I-V */
#define NV_GPIO_OUTPUT_CNTL_IO_OUTPUT_0 0x00000000 /* RW--V */
#define NV_GPIO_OUTPUT_CNTL_IO_OUTPUT_1 0x00000001 /* RW--V */
#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_1 0x00021644 /* RWI4R */
#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_1_GPIO15_RISING 15:15 /* RWIVF */
#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_1_GPIO15_RISING_INIT 0x00000001 /* RWI-V */
#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_1_GPIO15_RISING_DISABLED 0x00000000 /* RW--V */
#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_1_GPIO15_RISING_ENABLED 0x00000001 /* RW--V */
#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_1_GPIO15_FALLING 31:31 /* RWIVF */
#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_1_GPIO15_FALLING_INIT 0x00000001 /* RWI-V */
#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_1_GPIO15_FALLING_DISABLED 0x00000000 /* RW--V */
#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_1_GPIO15_FALLING_ENABLED 0x00000001 /* RW--V */
#endif // __ls10_dev_pmgr_h__

10
src/common/inc/swref/published/nvswitch/ls10/dev_timer_ip.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2003-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -24,14 +24,18 @@
#ifndef __ls10_dev_timer_ip_h__
#define __ls10_dev_timer_ip_h__
/* This file is autogenerated. Do not edit */
#define NV_PTIMER 0x00000FFF:0x00000000 /* RW--D */
#define NV_PTIMER 0x00000FFF:0x00000000 /* RW--D */
#define NV_PTIMER_PRI_TMR_CG1 0x00000600 /* RW-4R */
#define NV_PTIMER_PRI_TMR_CG1_MONITOR_CG_EN 0:0 /* RWIVF */
#define NV_PTIMER_PRI_TMR_CG1_MONITOR_CG_EN_ENABLED 0x00000001 /* RW--V */
#define NV_PTIMER_PRI_TMR_CG1_MONITOR_CG_EN_DISABLED 0x00000000 /* RWI-V */
#define NV_PTIMER_PRI_TMR_CG1_MONITOR_CG_EN__PROD 0x00000000 /* RW--V */
#define NV_PTIMER_PRI_TMR_CG1_SLCG 1:1 /* RWIVF */
#define NV_PTIMER_PRI_TMR_CG1_SLCG 1:1 /* RWIVF */
#define NV_PTIMER_PRI_TMR_CG1_SLCG_ENABLED 0x00000000 /* RW--V */
#define NV_PTIMER_PRI_TMR_CG1_SLCG_DISABLED 0x00000001 /* RWI-V */
#define NV_PTIMER_PRI_TMR_CG1_SLCG__PROD 0x00000000 /* RW--V */
#define NV_PTIMER_TIME_0 0x00000400 /* R--4R */
#define NV_PTIMER_TIME_0_NSEC 31:5 /* R-XUF */
#define NV_PTIMER_TIME_1 0x00000410 /* R--4R */
#define NV_PTIMER_TIME_1_NSEC 28:0 /* R-XUF */
#endif // __ls10_dev_timer_ip_h__

28
src/common/inc/swref/published/nvswitch/ls10/ptop_discovery_ip.h Normal file
View File

@@ -0,0 +1,28 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the Software),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __ls10_ptop_discovery_ip_h__
#define __ls10_ptop_discovery_ip_h__
/* This file is autogenerated. Do not edit */
#define NV_PTOP_UNICAST_SW_DEVICE_BASE_SAW_0 0x00028000 /* */
#endif // __ls10_ptop_discovery_ip_h__

51
src/common/inc/swref/published/pascal/gp100/dev_boot.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2021 NVIDIA CORPORATION & AFFILIATES
* SPDX-FileCopyrightText: Copyright (c) 2003-2023 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -44,4 +44,53 @@
#define NV_PMC_INTR_EN_CLEAR_DEVICE__SIZE_1 32 /* */
#define NV_PMC_INTR_EN_CLEAR_DEVICE_SET 0x00000001 /* */
#define NV_PMC_INTR_EN_CLEAR_VALUE 31:0 /* -W-VF */
#define NV_PMC_ENABLE 0x00000200 /* RW-4R */
#define NV_PMC_ENABLE_PMEDIA 4:4 /* */
#define NV_PMC_ENABLE_PMEDIA_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_PMEDIA_ENABLED 0x00000001 /* */
#define NV_PMC_ENABLE_PFIFO 8:8 /* RWIVF */
#define NV_PMC_ENABLE_PFIFO_DISABLED 0x00000000 /* RWI-V */
#define NV_PMC_ENABLE_PFIFO_ENABLED 0x00000001 /* RW--V */
#define NV_PMC_ENABLE_PWR 13:13 /* */
#define NV_PMC_ENABLE_PWR_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_PWR_ENABLED 0x00000001 /* */
#define NV_PMC_ENABLE_PGRAPH 12:12 /* */
#define NV_PMC_ENABLE_PGRAPH_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_PGRAPH_ENABLED 0x00000001 /* */
#define NV_PMC_ENABLE_SEC 14:14 /* */
#define NV_PMC_ENABLE_SEC_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_SEC_ENABLED 0x00000001 /* */
#define NV_PMC_ENABLE_CE0 6:6 /* */
#define NV_PMC_ENABLE_CE0_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_CE0_ENABLED 0x00000001 /* */
#define NV_PMC_ENABLE_CE1 7:7 /* */
#define NV_PMC_ENABLE_CE1_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_CE1_ENABLED 0x00000001 /* */
#define NV_PMC_ENABLE_CE2 21:21 /* */
#define NV_PMC_ENABLE_CE2_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_CE2_ENABLED 0x00000001 /* */
#define NV_PMC_ENABLE_CE3 22:22 /* */
#define NV_PMC_ENABLE_CE3_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_CE3_ENABLED 0x00000001 /* */
#define NV_PMC_ENABLE_CE4 23:23 /* */
#define NV_PMC_ENABLE_CE4_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_CE4_ENABLED 0x00000001 /* */
#define NV_PMC_ENABLE_CE5 24:24 /* */
#define NV_PMC_ENABLE_CE5_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_CE5_ENABLED 0x00000001 /* */
#define NV_PMC_ENABLE_NVDEC 15:15 /* */
#define NV_PMC_ENABLE_NVDEC_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_NVDEC_ENABLED 0x00000001 /* */
#define NV_PMC_ENABLE_PDISP 30:30 /* RWIVF */
#define NV_PMC_ENABLE_PDISP_DISABLED 0x00000000 /* RW--V */
#define NV_PMC_ENABLE_PDISP_ENABLED 0x00000001 /* RWI-V */
#define NV_PMC_ENABLE_NVENC0 18:18 /* */
#define NV_PMC_ENABLE_NVENC0_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_NVENC0_ENABLED 0x00000001 /* */
#define NV_PMC_ENABLE_NVENC1 19:19 /* */
#define NV_PMC_ENABLE_NVENC1_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_NVENC1_ENABLED 0x00000001 /* */
#define NV_PMC_ENABLE_NVENC2 4:4 /* */
#define NV_PMC_ENABLE_NVENC2_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_NVENC2_ENABLED 0x00000001 /* */
#endif // __gp100_dev_boot_h__

69
src/common/inc/swref/published/pascal/gp100/dev_fb.h Normal file
View File

@@ -0,0 +1,69 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2023 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gp100_dev_fb_h__
#define __gp100_dev_fb_h__
#define NV_PFB_PRI_MMU_INVALIDATE_ALL_VA 0:0 /* RWXVF */
#define NV_PFB_PRI_MMU_INVALIDATE_ALL_VA_FALSE 0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_INVALIDATE_ALL_VA_TRUE 0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_INVALIDATE_ALL_PDB 1:1 /* RWXVF */
#define NV_PFB_PRI_MMU_INVALIDATE_ALL_PDB_FALSE 0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_INVALIDATE_ALL_PDB_TRUE 0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_INVALIDATE_HUBTLB_ONLY 2:2 /* RWXVF */
#define NV_PFB_PRI_MMU_INVALIDATE_HUBTLB_ONLY_FALSE 0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_INVALIDATE_HUBTLB_ONLY_TRUE 0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_INVALIDATE_REPLAY 5:3 /* RWXVF */
#define NV_PFB_PRI_MMU_INVALIDATE_REPLAY_NONE 0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_INVALIDATE_REPLAY_START 0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_INVALIDATE_REPLAY_START_ACK_ALL 0x00000002 /* RW--V */
#define NV_PFB_PRI_MMU_INVALIDATE_REPLAY_CANCEL_TARGETED 0x00000003 /* RW--V */
#define NV_PFB_PRI_MMU_INVALIDATE_REPLAY_CANCEL_GLOBAL 0x00000004 /* RW--V */
#define NV_PFB_PRI_MMU_INVALIDATE_REPLAY_CANCEL 0x00000004 /* */
#define NV_PFB_PRI_MMU_INVALIDATE_SYS_MEMBAR 6:6 /* RWXVF */
#define NV_PFB_PRI_MMU_INVALIDATE_SYS_MEMBAR_FALSE 0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_INVALIDATE_SYS_MEMBAR_TRUE 0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_INVALIDATE_ACK 8:7 /* RWXVF */
#define NV_PFB_PRI_MMU_INVALIDATE_ACK_NONE_REQUIRED 0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_INVALIDATE_ACK_INTRANODE 0x00000002 /* RW--V */
#define NV_PFB_PRI_MMU_INVALIDATE_ACK_GLOBALLY 0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_INVALIDATE_CANCEL_CLIENT_ID 14:9 /* RWXVF */
#define NV_PFB_PRI_MMU_INVALIDATE_CANCEL_GPC_ID 19:15 /* RWXVF */
#define NV_PFB_PRI_MMU_INVALIDATE_CANCEL_CLIENT_TYPE 20:20 /* RWXVF */
#define NV_PFB_PRI_MMU_INVALIDATE_CANCEL_CLIENT_TYPE_GPC 0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_INVALIDATE_CANCEL_CLIENT_TYPE_HUB 0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_INVALIDATE_CACHE_LEVEL 26:24 /* RWXVF */
#define NV_PFB_PRI_MMU_INVALIDATE_CACHE_LEVEL_ALL 0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_INVALIDATE_CACHE_LEVEL_PTE_ONLY 0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_INVALIDATE_CACHE_LEVEL_UP_TO_PDE0 0x00000002 /* RW--V */
#define NV_PFB_PRI_MMU_INVALIDATE_CACHE_LEVEL_UP_TO_PDE1 0x00000003 /* RW--V */
#define NV_PFB_PRI_MMU_INVALIDATE_CACHE_LEVEL_UP_TO_PDE2 0x00000004 /* RW--V */
#define NV_PFB_PRI_MMU_INVALIDATE_CACHE_LEVEL_UP_TO_PDE3 0x00000005 /* RW--V */
#define NV_PFB_PRI_MMU_INVALIDATE_CACHE_LEVEL_UP_TO_PDE4 0x00000006 /* RW--V */
#define NV_PFB_PRI_MMU_INVALIDATE_CACHE_LEVEL_UP_TO_PDE5 0x00000007 /* RW--V */
#define NV_PFB_PRI_MMU_INVALIDATE_TRIGGER 31:31 /* -WEVF */
#define NV_PFB_PRI_MMU_INVALIDATE_TRIGGER_FALSE 0x00000000 /* -WE-V */
#define NV_PFB_PRI_MMU_INVALIDATE_TRIGGER_TRUE 0x00000001 /* -W--T */
#endif // __gv100_dev_fb_h__

75
src/common/inc/swref/published/pascal/gp102/dev_boot.h Normal file
View File

@@ -0,0 +1,75 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2021 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gp102_dev_boot_h__
#define __gp102_dev_boot_h__
#define NV_PMC_ENABLE 0x00000200 /* RW-4R */
#define NV_PMC_ENABLE_PMEDIA 4:4 /* */
#define NV_PMC_ENABLE_PMEDIA_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_PMEDIA_ENABLED 0x00000001 /* */
#define NV_PMC_ENABLE_PFIFO 8:8 /* RWIVF */
#define NV_PMC_ENABLE_PFIFO_DISABLED 0x00000000 /* RWI-V */
#define NV_PMC_ENABLE_PFIFO_ENABLED 0x00000001 /* RW--V */
#define NV_PMC_ENABLE_PWR 13:13 /* */
#define NV_PMC_ENABLE_PWR_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_PWR_ENABLED 0x00000001 /* */
#define NV_PMC_ENABLE_PGRAPH 12:12 /* */
#define NV_PMC_ENABLE_PGRAPH_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_PGRAPH_ENABLED 0x00000001 /* */
#define NV_PMC_ENABLE_SEC 14:14 /* */
#define NV_PMC_ENABLE_SEC_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_SEC_ENABLED 0x00000001 /* */
#define NV_PMC_ENABLE_CE0 6:6 /* */
#define NV_PMC_ENABLE_CE0_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_CE0_ENABLED 0x00000001 /* */
#define NV_PMC_ENABLE_CE1 7:7 /* */
#define NV_PMC_ENABLE_CE1_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_CE1_ENABLED 0x00000001 /* */
#define NV_PMC_ENABLE_CE2 21:21 /* */
#define NV_PMC_ENABLE_CE2_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_CE2_ENABLED 0x00000001 /* */
#define NV_PMC_ENABLE_CE3 22:22 /* */
#define NV_PMC_ENABLE_CE3_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_CE3_ENABLED 0x00000001 /* */
#define NV_PMC_ENABLE_CE4 23:23 /* */
#define NV_PMC_ENABLE_CE4_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_CE4_ENABLED 0x00000001 /* */
#define NV_PMC_ENABLE_CE5 24:24 /* */
#define NV_PMC_ENABLE_CE5_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_CE5_ENABLED 0x00000001 /* */
#define NV_PMC_ENABLE_NVDEC 15:15 /* */
#define NV_PMC_ENABLE_NVDEC_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_NVDEC_ENABLED 0x00000001 /* */
#define NV_PMC_ENABLE_PDISP 30:30 /* RWIVF */
#define NV_PMC_ENABLE_PDISP_DISABLED 0x00000000 /* RW--V */
#define NV_PMC_ENABLE_PDISP_ENABLED 0x00000001 /* RWI-V */
#define NV_PMC_ENABLE_NVENC0 18:18 /* */
#define NV_PMC_ENABLE_NVENC0_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_NVENC0_ENABLED 0x00000001 /* */
#define NV_PMC_ENABLE_NVENC1 19:19 /* */
#define NV_PMC_ENABLE_NVENC1_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_NVENC1_ENABLED 0x00000001 /* */
#define NV_PMC_ENABLE_NVENC2 4:4 /* */
#define NV_PMC_ENABLE_NVENC2_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_NVENC2_ENABLED 0x00000001 /* */
#endif // __gp102_dev_boot_h__

69
src/common/inc/swref/published/turing/tu102/dev_boot.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES
* SPDX-FileCopyrightText: Copyright (c) 2003-2023 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -49,7 +49,74 @@
#define NV_PMC_ENABLE_DEVICE__SIZE_1 32 /* */
#define NV_PMC_ENABLE_DEVICE_DISABLE 0x00000000 /* */
#define NV_PMC_ENABLE_DEVICE_ENABLE 0x00000001 /* */
#define NV_PMC_ENABLE_PMEDIA 4:4 /* */
#define NV_PMC_ENABLE_PMEDIA_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_PMEDIA_ENABLED 0x00000001 /* */
#define NV_PMC_ENABLE_PFIFO 8:8 /* RWIVF */
#define NV_PMC_ENABLE_PFIFO_DISABLED 0x00000000 /* RWI-V */
#define NV_PMC_ENABLE_PFIFO_ENABLED 0x00000001 /* RW--V */
#define NV_PMC_ENABLE_PWR 13:13 /* */
#define NV_PMC_ENABLE_PWR_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_PWR_ENABLED 0x00000001 /* */
#define NV_PMC_ENABLE_CE0 6:6 /* */
#define NV_PMC_ENABLE_CE0_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_CE0_ENABLED 0x00000001 /* */
#define NV_PMC_ENABLE_CE1 7:7 /* */
#define NV_PMC_ENABLE_CE1_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_CE1_ENABLED 0x00000001 /* */
#define NV_PMC_ENABLE_CE2 21:21 /* */
#define NV_PMC_ENABLE_CE2_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_CE2_ENABLED 0x00000001 /* */
#define NV_PMC_ENABLE_CE3 22:22 /* */
#define NV_PMC_ENABLE_CE3_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_CE3_ENABLED 0x00000001 /* */
#define NV_PMC_ENABLE_CE4 23:23 /* */
#define NV_PMC_ENABLE_CE4_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_CE4_ENABLED 0x00000001 /* */
#define NV_PMC_ENABLE_CE5 24:24 /* */
#define NV_PMC_ENABLE_CE5_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_CE5_ENABLED 0x00000001 /* */
#define NV_PMC_ENABLE_CE6 9:9 /* */
#define NV_PMC_ENABLE_CE6_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_CE6_ENABLED 0x00000001 /* */
#define NV_PMC_ENABLE_CE7 10:10 /* */
#define NV_PMC_ENABLE_CE7_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_CE7_ENABLED 0x00000001 /* */
#define NV_PMC_ENABLE_CE8 11:11 /* */
#define NV_PMC_ENABLE_CE8_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_CE8_ENABLED 0x00000001 /* */
#define NV_PMC_ENABLE_PGRAPH 12:12 /* */
#define NV_PMC_ENABLE_PGRAPH_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_PGRAPH_ENABLED 0x00000001 /* */
#define NV_PMC_ENABLE_SEC 14:14 /* */
#define NV_PMC_ENABLE_SEC_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_SEC_ENABLED 0x00000001 /* */
#define NV_PMC_ENABLE_NVDEC 15:15 /* */
#define NV_PMC_ENABLE_NVDEC_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_NVDEC_ENABLED 0x00000001 /* */
#define NV_PMC_ENABLE_NVDEC0 15:15 /* */
#define NV_PMC_ENABLE_NVDEC0_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_NVDEC0_ENABLED 0x00000001 /* */
#define NV_PMC_ENABLE_NVDEC1 16:16 /* */
#define NV_PMC_ENABLE_NVDEC1_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_NVDEC1_ENABLED 0x00000001 /* */
#define NV_PMC_ENABLE_NVDEC2 20:20 /* */
#define NV_PMC_ENABLE_NVENC0 18:18 /* */
#define NV_PMC_ENABLE_NVENC0_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_NVENC0_ENABLED 0x00000001 /* */
#define NV_PMC_ENABLE_NVENC1 19:19 /* */
#define NV_PMC_ENABLE_NVENC1_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_NVENC1_ENABLED 0x00000001 /* */
#define NV_PMC_ENABLE_NVDEC2 20:20 /* */
#define NV_PMC_ENABLE_NVDEC2_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_NVDEC2_ENABLED 0x00000001 /* */
#define NV_PMC_ENABLE_PERFMON 28:28 /* RWIVF */
#define NV_PMC_ENABLE_PERFMON_DISABLED 0x00000000 /* RWI-V */
#define NV_PMC_ENABLE_PERFMON_ENABLED 0x00000001 /* RW--V */
#define NV_PMC_ENABLE_PDISP 30:30 /* RWIVF */
#define NV_PMC_ENABLE_PDISP_DISABLED 0x00000000 /* RW--V */
#define NV_PMC_ENABLE_PDISP_ENABLED 0x00000001 /* RWI-V */
#define NV_PMC_ENABLE_NVJPG0 31:31 /* */
#define NV_PMC_ENABLE_NVJPG0_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_NVJPG0_ENABLED 0x00000001 /* */
#endif // __tu102_dev_boot_h__

45
src/common/inc/swref/published/turing/tu102/dev_bus.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES
* SPDX-FileCopyrightText: Copyright (c) 2003-2023 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -35,4 +35,47 @@
#define NV_PBUS_IFR_FMT_FIXED2 0x00000008 /* */
#define NV_PBUS_IFR_FMT_FIXED2_TOTAL_DATA_SIZE 19:0 /* */
#define NV_PBUS_BAR1_BLOCK 0x00001704 /* RW-4R */
#define NV_PBUS_BAR1_BLOCK_MAP 29:0 /* */
#define NV_PBUS_BAR1_BLOCK_PTR 27:0 /* RWIUF */
#define NV_PBUS_BAR1_BLOCK_PTR_0 0x00000000 /* RWI-V */
#define NV_PBUS_BAR1_BLOCK_TARGET 29:28 /* RWIUF */
#define NV_PBUS_BAR1_BLOCK_TARGET_VID_MEM 0x00000000 /* RWI-V */
#define NV_PBUS_BAR1_BLOCK_TARGET_SYS_MEM_COHERENT 0x00000002 /* RW--V */
#define NV_PBUS_BAR1_BLOCK_TARGET_SYS_MEM_NONCOHERENT 0x00000003 /* RW--V */
#define NV_PBUS_BAR1_BLOCK_MODE 31:31 /* RWIUF */
#define NV_PBUS_BAR1_BLOCK_MODE_PHYSICAL 0x00000000 /* RWI-V */
#define NV_PBUS_BAR1_BLOCK_MODE_VIRTUAL 0x00000001 /* RW--V */
#define NV_PBUS_BAR1_BLOCK_PTR_SHIFT 12 /* */
#define NV_PBUS_BAR2_BLOCK 0x00001714 /* RW-4R */
#define NV_PBUS_BAR2_BLOCK_MAP 29:0 /* */
#define NV_PBUS_BAR2_BLOCK_PTR 27:0 /* RWIUF */
#define NV_PBUS_BAR2_BLOCK_PTR_0 0x00000000 /* RWI-V */
#define NV_PBUS_BAR2_BLOCK_TARGET 29:28 /* RWIUF */
#define NV_PBUS_BAR2_BLOCK_TARGET_VID_MEM 0x00000000 /* RWI-V */
#define NV_PBUS_BAR2_BLOCK_TARGET_SYS_MEM_COHERENT 0x00000002 /* RW--V */
#define NV_PBUS_BAR2_BLOCK_TARGET_SYS_MEM_NONCOHERENT 0x00000003 /* RW--V */
#define NV_PBUS_BAR2_BLOCK_DEBUG_CYA 30:30 /* RWIUF */
#define NV_PBUS_BAR2_BLOCK_DEBUG_CYA_OFF 0x00000001 /* RW--V */
#define NV_PBUS_BAR2_BLOCK_DEBUG_CYA_ON 0x00000000 /* RW--V */
#define NV_PBUS_BAR2_BLOCK_DEBUG_CYA_INIT 0x00000001 /* RWI-V */
#define NV_PBUS_BAR2_BLOCK_MODE 31:31 /* RWIUF */
#define NV_PBUS_BAR2_BLOCK_MODE_PHYSICAL 0x00000000 /* RWI-V */
#define NV_PBUS_BAR2_BLOCK_MODE_VIRTUAL 0x00000001 /* RW--V */
#define NV_PBUS_BAR2_BLOCK_PTR_SHIFT 12 /* */
#define NV_PBUS_BAR2_BLOCK_RESERVED 30:30 /* */
#define NV_PBUS_BAR2_BLOCK_RESERVED_DEFAULT 0x00000001 /* */
#define NV_PBUS_BIND_STATUS_BAR1_PENDING 0:0 /* R-IUF */
#define NV_PBUS_BIND_STATUS_BAR1_PENDING_EMPTY 0x00000000 /* R-I-V */
#define NV_PBUS_BIND_STATUS_BAR1_PENDING_BUSY 0x00000001 /* R---V */
#define NV_PBUS_BIND_STATUS_BAR1_OUTSTANDING 1:1 /* R-IUF */
#define NV_PBUS_BIND_STATUS_BAR1_OUTSTANDING_FALSE 0x00000000 /* R-I-V */
#define NV_PBUS_BIND_STATUS_BAR1_OUTSTANDING_TRUE 0x00000001 /* R---V */
#define NV_PBUS_BIND_STATUS_BAR2_PENDING 2:2 /* R-IUF */
#define NV_PBUS_BIND_STATUS_BAR2_PENDING_EMPTY 0x00000000 /* R-I-V */
#define NV_PBUS_BIND_STATUS_BAR2_PENDING_BUSY 0x00000001 /* R---V */
#define NV_PBUS_BIND_STATUS_BAR2_OUTSTANDING 3:3 /* R-IUF */
#define NV_PBUS_BIND_STATUS_BAR2_OUTSTANDING_FALSE 0x00000000 /* R-I-V */
#define NV_PBUS_BIND_STATUS_BAR2_OUTSTANDING_TRUE 0x00000001 /* R---V */
#endif // __tu102_dev_bus_h__

149
src/common/inc/swref/published/turing/tu102/dev_fault.h Normal file
View File

@@ -0,0 +1,149 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2023 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __ad102_dev_fault_h__
#define __ad102_dev_fault_h__
#define NV_PFAULT_MMU_ENG_ID_DISPLAY 1 /* */
#define NV_PFAULT_MMU_ENG_ID_IFB 9 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1 128 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2 192 /* */
#define NV_PFAULT_MMU_ENG_ID_SEC 14 /* */
#define NV_PFAULT_MMU_ENG_ID_PERF 8 /* */
#define NV_PFAULT_MMU_ENG_ID_NVDEC 10 /* */
#define NV_PFAULT_MMU_ENG_ID_NVDEC0 10 /* */
#define NV_PFAULT_MMU_ENG_ID_NVDEC1 25 /* */
#define NV_PFAULT_MMU_ENG_ID_NVDEC2 26 /* */
#define NV_PFAULT_MMU_ENG_ID_NVJPG0 24 /* */
#define NV_PFAULT_MMU_ENG_ID_GRCOPY 15 /* */
#define NV_PFAULT_MMU_ENG_ID_CE0 15 /* */
#define NV_PFAULT_MMU_ENG_ID_CE1 16 /* */
#define NV_PFAULT_MMU_ENG_ID_CE2 17 /* */
#define NV_PFAULT_MMU_ENG_ID_CE3 18 /* */
#define NV_PFAULT_MMU_ENG_ID_CE4 19 /* */
#define NV_PFAULT_MMU_ENG_ID_CE5 20 /* */
#define NV_PFAULT_MMU_ENG_ID_CE6 21 /* */
#define NV_PFAULT_MMU_ENG_ID_CE7 22 /* */
#define NV_PFAULT_MMU_ENG_ID_CE8 23 /* */
#define NV_PFAULT_MMU_ENG_ID_PWR_PMU 6 /* */
#define NV_PFAULT_MMU_ENG_ID_PTP 3 /* */
#define NV_PFAULT_MMU_ENG_ID_NVENC0 11 /* */
#define NV_PFAULT_MMU_ENG_ID_NVENC1 12 /* */
#define NV_PFAULT_MMU_ENG_ID_NVENC2 13 /* */
#define NV_PFAULT_MMU_ENG_ID_PHYSICAL 31 /* */
#define NV_PFAULT_CLIENT_GPC_T1_0 0x00000000 /* */
#define NV_PFAULT_CLIENT_GPC_T1_1 0x00000001 /* */
#define NV_PFAULT_CLIENT_GPC_T1_2 0x00000002 /* */
#define NV_PFAULT_CLIENT_GPC_T1_3 0x00000003 /* */
#define NV_PFAULT_CLIENT_GPC_T1_4 0x00000004 /* */
#define NV_PFAULT_CLIENT_GPC_T1_5 0x00000005 /* */
#define NV_PFAULT_CLIENT_GPC_T1_6 0x00000006 /* */
#define NV_PFAULT_CLIENT_GPC_T1_7 0x00000007 /* */
#define NV_PFAULT_CLIENT_GPC_PE_0 0x00000008 /* */
#define NV_PFAULT_CLIENT_GPC_PE_1 0x00000009 /* */
#define NV_PFAULT_CLIENT_GPC_PE_2 0x0000000A /* */
#define NV_PFAULT_CLIENT_GPC_PE_3 0x0000000B /* */
#define NV_PFAULT_CLIENT_GPC_PE_4 0x0000000C /* */
#define NV_PFAULT_CLIENT_GPC_PE_5 0x0000000D /* */
#define NV_PFAULT_CLIENT_GPC_PE_6 0x0000000E /* */
#define NV_PFAULT_CLIENT_GPC_PE_7 0x0000000F /* */
#define NV_PFAULT_CLIENT_GPC_RAST 0x00000010 /* */
#define NV_PFAULT_CLIENT_GPC_GCC 0x00000011 /* */
#define NV_PFAULT_CLIENT_GPC_GPCCS 0x00000012 /* */
#define NV_PFAULT_CLIENT_GPC_PROP_0 0x00000013 /* */
#define NV_PFAULT_CLIENT_GPC_PROP_1 0x00000014 /* */
#define NV_PFAULT_CLIENT_GPC_T1_8 0x00000021 /* */
#define NV_PFAULT_CLIENT_GPC_T1_9 0x00000022 /* */
#define NV_PFAULT_CLIENT_GPC_T1_10 0x00000023 /* */
#define NV_PFAULT_CLIENT_GPC_T1_11 0x00000024 /* */
#define NV_PFAULT_CLIENT_GPC_T1_12 0x00000025 /* */
#define NV_PFAULT_CLIENT_GPC_T1_13 0x00000026 /* */
#define NV_PFAULT_CLIENT_GPC_T1_14 0x00000027 /* */
#define NV_PFAULT_CLIENT_GPC_T1_15 0x00000028 /* */
#define NV_PFAULT_CLIENT_GPC_TPCCS_0 0x00000029 /* */
#define NV_PFAULT_CLIENT_GPC_TPCCS_1 0x0000002A /* */
#define NV_PFAULT_CLIENT_GPC_TPCCS_2 0x0000002B /* */
#define NV_PFAULT_CLIENT_GPC_TPCCS_3 0x0000002C /* */
#define NV_PFAULT_CLIENT_GPC_TPCCS_4 0x0000002D /* */
#define NV_PFAULT_CLIENT_GPC_TPCCS_5 0x0000002E /* */
#define NV_PFAULT_CLIENT_GPC_TPCCS_6 0x0000002F /* */
#define NV_PFAULT_CLIENT_GPC_TPCCS_7 0x00000030 /* */
#define NV_PFAULT_CLIENT_GPC_PE_8 0x00000031 /* */
#define NV_PFAULT_CLIENT_GPC_TPCCS_8 0x00000033 /* */
#define NV_PFAULT_CLIENT_GPC_T1_16 0x00000035 /* */
#define NV_PFAULT_CLIENT_GPC_T1_17 0x00000036 /* */
#define NV_PFAULT_CLIENT_HUB_CE0 0x00000001 /* */
#define NV_PFAULT_CLIENT_HUB_CE1 0x00000002 /* */
#define NV_PFAULT_CLIENT_HUB_DNISO 0x00000003 /* */
#define NV_PFAULT_CLIENT_HUB_FE 0x00000004 /* */
#define NV_PFAULT_CLIENT_HUB_FECS 0x00000005 /* */
#define NV_PFAULT_CLIENT_HUB_HOST 0x00000006 /* */
#define NV_PFAULT_CLIENT_HUB_HOST_CPU 0x00000007 /* */
#define NV_PFAULT_CLIENT_HUB_HOST_CPU_NB 0x00000008 /* */
#define NV_PFAULT_CLIENT_HUB_ISO 0x00000009 /* */
#define NV_PFAULT_CLIENT_HUB_MMU 0x0000000A /* */
#define NV_PFAULT_CLIENT_HUB_NVDEC 0x0000000B /* */
#define NV_PFAULT_CLIENT_HUB_NVDEC0 0x0000000B /* */
#define NV_PFAULT_CLIENT_HUB_NVENC1 0x0000000D /* */
#define NV_PFAULT_CLIENT_HUB_NVENC2 0x00000033 /* */
#define NV_PFAULT_CLIENT_HUB_NISO 0x0000000E /* */
#define NV_PFAULT_CLIENT_HUB_P2P 0x0000000F /* */
#define NV_PFAULT_CLIENT_HUB_PD 0x00000010 /* */
#define NV_PFAULT_CLIENT_HUB_PERF 0x00000011 /* */
#define NV_PFAULT_CLIENT_HUB_PMU 0x00000012 /* */
#define NV_PFAULT_CLIENT_HUB_RASTERTWOD 0x00000013 /* */
#define NV_PFAULT_CLIENT_HUB_SCC 0x00000014 /* */
#define NV_PFAULT_CLIENT_HUB_SCC_NB 0x00000015 /* */
#define NV_PFAULT_CLIENT_HUB_SEC 0x00000016 /* */
#define NV_PFAULT_CLIENT_HUB_SSYNC 0x00000017 /* */
#define NV_PFAULT_CLIENT_HUB_NVDEC1 0x0000003A /* */
#define NV_PFAULT_CLIENT_HUB_NVDEC2 0x0000003B /* */
#define NV_PFAULT_CLIENT_HUB_NVJPG0 0x0000003C /* */
#define NV_PFAULT_CLIENT_HUB_VIP 0x00000000 /* */
#define NV_PFAULT_CLIENT_HUB_GRCOPY 0x00000018 /* */
#define NV_PFAULT_CLIENT_HUB_CE2 0x00000018 /* */
#define NV_PFAULT_CLIENT_HUB_XV 0x00000019 /* */
#define NV_PFAULT_CLIENT_HUB_MMU_NB 0x0000001A /* */
#define NV_PFAULT_CLIENT_HUB_NVENC 0x0000001B /* */
#define NV_PFAULT_CLIENT_HUB_NVENC0 0x0000001B /* */
#define NV_PFAULT_CLIENT_HUB_DFALCON 0x0000001C /* */
#define NV_PFAULT_CLIENT_HUB_SKED 0x0000001D /* */
#define NV_PFAULT_CLIENT_HUB_AFALCON 0x0000001E /* */
#define NV_PFAULT_CLIENT_HUB_HSCE0 0x00000020 /* */
#define NV_PFAULT_CLIENT_HUB_HSCE1 0x00000021 /* */
#define NV_PFAULT_CLIENT_HUB_HSCE2 0x00000022 /* */
#define NV_PFAULT_CLIENT_HUB_HSCE3 0x00000023 /* */
#define NV_PFAULT_CLIENT_HUB_HSCE4 0x00000024 /* */
#define NV_PFAULT_CLIENT_HUB_HSCE5 0x00000025 /* */
#define NV_PFAULT_CLIENT_HUB_HSCE6 0x00000026 /* */
#define NV_PFAULT_CLIENT_HUB_HSCE7 0x00000027 /* */
#define NV_PFAULT_CLIENT_HUB_HSCE8 0x00000028 /* */
#define NV_PFAULT_CLIENT_HUB_HSCE9 0x00000029 /* */
#define NV_PFAULT_CLIENT_HUB_DWBIF 0x00000036 /* */
#define NV_PFAULT_CLIENT_HUB_FBFALCON 0x00000037 /* */
#define NV_PFAULT_CLIENT_HUB_GSP 0x00000039 /* */
#define NV_PFAULT_CLIENT_HUB_DONT_CARE 0x0000001F /* */
#endif // _ad102_dev_fault_h__

33
src/common/inc/swref/published/turing/tu102/dev_fb.h
View File

@@ -38,4 +38,37 @@
#define NV_PFB_PRI_MMU_WPR2_ADDR_HI_VAL 31:4 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR2_ADDR_HI_ALIGNMENT 0x0000000c /* */
#define NV_PFB_PRI_MMU_FAULT_BUFFER_SIZE_VAL 19:0 /* RWEVF */
#define NV_PFB_PRI_MMU_FAULT_BUFFER_SIZE_VAL_RESET 0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FAULT_BUFFER_SIZE_OVERFLOW_INTR 29:29 /* RWEVF */
#define NV_PFB_PRI_MMU_FAULT_BUFFER_SIZE_OVERFLOW_INTR_DISABLE 0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FAULT_BUFFER_SIZE_OVERFLOW_INTR_ENABLE 0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_FAULT_BUFFER_SIZE_SET_DEFAULT 30:30 /* RWEVF */
#define NV_PFB_PRI_MMU_FAULT_BUFFER_SIZE_SET_DEFAULT_NO 0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FAULT_BUFFER_SIZE_SET_DEFAULT_YES 0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_FAULT_BUFFER_SIZE_ENABLE 31:31 /* RWEVF */
#define NV_PFB_PRI_MMU_FAULT_BUFFER_SIZE_ENABLE_FALSE 0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FAULT_BUFFER_SIZE_ENABLE_TRUE 0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_L2TLB_ECC_UNCORRECTED_ERR_COUNT 0x00100E78 /* RW-4R */
#define NV_PFB_PRI_MMU_L2TLB_ECC_UNCORRECTED_ERR_COUNT 0x00100E78 /* RW-4R */
#define NV_PFB_PRI_MMU_L2TLB_ECC_UNCORRECTED_ERR_COUNT_TOTAL 15:0 /* RWEVF */
#define NV_PFB_PRI_MMU_L2TLB_ECC_UNCORRECTED_ERR_COUNT_TOTAL_INIT 0 /* RWE-V */
#define NV_PFB_PRI_MMU_L2TLB_ECC_UNCORRECTED_ERR_COUNT_UNIQUE 31:16 /* RWEVF */
#define NV_PFB_PRI_MMU_L2TLB_ECC_UNCORRECTED_ERR_COUNT_UNIQUE_INIT 0 /* RWE-V */
#define NV_PFB_PRI_MMU_HUBTLB_ECC_UNCORRECTED_ERR_COUNT 0x00100E8C /* RW-4R */
#define NV_PFB_PRI_MMU_HUBTLB_ECC_UNCORRECTED_ERR_COUNT 0x00100E8C /* RW-4R */
#define NV_PFB_PRI_MMU_HUBTLB_ECC_UNCORRECTED_ERR_COUNT_TOTAL 15:0 /* RWEVF */
#define NV_PFB_PRI_MMU_HUBTLB_ECC_UNCORRECTED_ERR_COUNT_TOTAL_INIT 0 /* RWE-V */
#define NV_PFB_PRI_MMU_HUBTLB_ECC_UNCORRECTED_ERR_COUNT_UNIQUE 31:16 /* RWEVF */
#define NV_PFB_PRI_MMU_HUBTLB_ECC_UNCORRECTED_ERR_COUNT_UNIQUE_INIT 0 /* RWE-V */
#define NV_PFB_PRI_MMU_FILLUNIT_ECC_UNCORRECTED_ERR_COUNT 0x00100EA0 /* RW-4R */
#define NV_PFB_PRI_MMU_FILLUNIT_ECC_UNCORRECTED_ERR_COUNT 0x00100EA0 /* RW-4R */
#define NV_PFB_PRI_MMU_FILLUNIT_ECC_UNCORRECTED_ERR_COUNT_TOTAL 15:0 /* RWEVF */
#define NV_PFB_PRI_MMU_FILLUNIT_ECC_UNCORRECTED_ERR_COUNT_TOTAL_INIT 0 /* RWE-V */
#define NV_PFB_PRI_MMU_FILLUNIT_ECC_UNCORRECTED_ERR_COUNT_UNIQUE 31:16 /* RWEVF */
#define NV_PFB_PRI_MMU_FILLUNIT_ECC_UNCORRECTED_ERR_COUNT_UNIQUE_INIT 0 /* RWE-V */
#endif // __tu102_dev_fb_h__

29
src/common/inc/swref/published/turing/tu102/dev_fbpa.h Normal file
View File

@@ -0,0 +1,29 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __tu102_dev_fbpa_h_
#define __tu102_dev_fbpa_h_
#define NV_PFB_FBPA_0_ECC_DED_COUNT__SIZE_1 2 /* */
#define NV_PFB_FBPA_0_ECC_DED_COUNT(i) (0x00900488+(i)*4) /* RW-4A */
#endif // __tu102_dev_fbpa_h_

1
src/common/inc/swref/published/turing/tu102/dev_gc6_island.h
View File

@@ -24,6 +24,7 @@
#ifndef __tu102_dev_gc6_island_h__
#define __tu102_dev_gc6_island_h__
#define NV_PGC6 0x118fff:0x118000 /* RW--D */
#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_PRIV_LEVEL_MASK 0x00118128 /* RW-4R */
#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */

17
src/common/inc/swref/published/turing/tu102/dev_gsp.h
View File

@@ -38,5 +38,22 @@
#define NV_PGSP_QUEUE_HEAD(i) (0x110c00+(i)*8) /* RW-4A */
#define NV_PGSP_QUEUE_HEAD__SIZE_1 8 /* */
#define NV_PGSP_QUEUE_HEAD_ADDRESS 31:0 /* RWIVF */
#define NV_PGSP_EMEMC(i) (0x110ac0+(i)*8) /* RW-4A */
#define NV_PGSP_EMEMC__SIZE_1 4 /* */
#define NV_PGSP_EMEMC_OFFS 7:2 /* RWIVF */
#define NV_PGSP_EMEMC_OFFS_INIT 0x00000000 /* RWI-V */
#define NV_PGSP_EMEMC_BLK 15:8 /* RWIVF */
#define NV_PGSP_EMEMC_BLK_INIT 0x00000000 /* RWI-V */
#define NV_PGSP_EMEMC_AINCW 24:24 /* RWIVF */
#define NV_PGSP_EMEMC_AINCW_INIT 0x00000000 /* RWI-V */
#define NV_PGSP_EMEMC_AINCW_TRUE 0x00000001 /* RW--V */
#define NV_PGSP_EMEMC_AINCW_FALSE 0x00000000 /* RW--V */
#define NV_PGSP_EMEMC_AINCR 25:25 /* RWIVF */
#define NV_PGSP_EMEMC_AINCR_INIT 0x00000000 /* RWI-V */
#define NV_PGSP_EMEMC_AINCR_TRUE 0x00000001 /* RW--V */
#define NV_PGSP_EMEMC_AINCR_FALSE 0x00000000 /* RW--V */
#define NV_PGSP_EMEMD(i) (0x110ac4+(i)*8) /* RW-4A */
#define NV_PGSP_EMEMD__SIZE_1 4 /* */
#define NV_PGSP_EMEMD_DATA 31:0 /* RW-VF */
#endif // __tu102_dev_gsp_h__

6
src/common/inc/swref/published/hopper/gh100/dev_ltc.h → src/common/inc/swref/published/turing/tu102/dev_ltc.h
View File

@@ -21,8 +21,8 @@
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gh100_dev_ltc_h_
#define __gh100_dev_ltc_h_
#ifndef __tu102_dev_ltc_h_
#define __tu102_dev_ltc_h_
#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_UNCORRECTED_ERR_COUNT 0x001404f8 /* RW-4R */
#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_UNCORRECTED_ERR_COUNT_TOTAL 15:0 /* RWIVF */
@@ -30,4 +30,4 @@
#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_UNCORRECTED_ERR_COUNT_UNIQUE 31:16 /* RWIVF */
#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_UNCORRECTED_ERR_COUNT_UNIQUE_INIT 0x0000 /* RWI-V */
#endif // __gh100_dev_ltc_h_
#endif // __tu102_dev_ltc_h_

8
src/common/inc/swref/published/turing/tu102/dev_nv_xve.h
View File

@@ -24,6 +24,10 @@
#ifndef __tu102_dev_nv_xve_h__
#define __tu102_dev_nv_xve_h__
#define NV_PCFG 0x00088FFF:0x00088000 /* RW--D */
#define NV_XVE_ID 0x00000000 /* R--4R */
#define NV_XVE_ID_VENDOR 15:0 /* C--VF */
#define NV_XVE_ID_VENDOR_NVIDIA 0x000010DE /* C---V */
#define NV_XVE_SW_RESET 0x00000718 /* RW-4R */
#define NV_XVE_DEVICE_CAPABILITY 0x0000007C /* R--4R */
#define NV_XVE_DEVICE_CAPABILITY_FUNCTION_LEVEL_RESET 28:28 /* R-XVF */
#define NV_XVE_DEVICE_CAPABILITY_FUNCTION_LEVEL_RESET_NOT_SUPPORTED 0x00000000 /* R---V */
@@ -35,6 +39,10 @@
#define NV_XVE_MSIX_CAP_HDR_ENABLE 31:31 /* RWIVF */
#define NV_XVE_MSIX_CAP_HDR_ENABLE_ENABLED 0x00000001 /* RW--V */
#define NV_XVE_MSIX_CAP_HDR_ENABLE_DISABLED 0x00000000 /* RWI-V */
#define NV_XVE_PRIV_MISC_1 0x0000041C /* RW-4R */
#define NV_XVE_PRIV_MISC_1_CYA_HIDE_MSIX_CAP 29:29 /* RWCVF */
#define NV_XVE_PRIV_MISC_1_CYA_HIDE_MSIX_CAP_TRUE 0x00000001 /* RW--V */
#define NV_XVE_PRIV_MISC_1_CYA_HIDE_MSIX_CAP_FALSE 0x00000000 /* RWC-V */
#define NV_XVE_SRIOV_CAP_HDR3 0x00000BD8 /* R--4R */
#define NV_XVE_SRIOV_CAP_HDR3_TOTAL_VFS 31:16 /* R-EVF */
#define NV_XVE_SRIOV_CAP_HDR5 0x00000BE0 /* R--4R */

68
src/common/inc/swref/published/turing/tu102/dev_vm.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES
* SPDX-FileCopyrightText: Copyright (c) 2003-2023 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -23,6 +23,8 @@
#ifndef __tu102_dev_vm_h__
#define __tu102_dev_vm_h__
#define NV_VIRTUAL_FUNCTION_PRIV 0x0002FFFF:0x00000000 /* RW--D */
#define NV_VIRTUAL_FUNCTION 0x0003FFFF:0x00030000 /* RW--D */
#define NV_VIRTUAL_FUNCTION_FULL_PHYS_OFFSET 0x00BBFFFF:0x00B80000 /* RW--D */
#define NV_VIRTUAL_FUNCTION_PRIV_L2_SYSMEM_INVALIDATE 0x00000F00 /* RW-4R */
#define NV_VIRTUAL_FUNCTION_PRIV_L2_PEERMEM_INVALIDATE 0x00000F04 /* RW-4R */
@@ -97,7 +99,23 @@
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_PUT_OVERFLOW_YES 0x00000001 /* R---V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_SIZE(i) (0x00003010+(i)*32) /* RW-4A */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_SIZE__SIZE_1 2 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_SIZE_VAL 19:0 /* RWEVF */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_SIZE_VAL_RESET 0x00000000 /* RWE-V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_SIZE_OVERFLOW_INTR 29:29 /* RWEVF */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_SIZE_OVERFLOW_INTR_DISABLE 0x00000000 /* RWE-V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_SIZE_OVERFLOW_INTR_ENABLE 0x00000001 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_SIZE_SET_DEFAULT 30:30 /* RWEVF */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_SIZE_SET_DEFAULT_NO 0x00000000 /* RWE-V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_SIZE_SET_DEFAULT_YES 0x00000001 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_SIZE_ENABLE 31:31 /* RWEVF */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_SIZE_ENABLE_FALSE 0x00000000 /* RWE-V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_SIZE_ENABLE_TRUE 0x00000001 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_PAGE_FAULT_CTRL 0x00003070 /* RW-4R */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_ADDR_LO 0x00003080 /* R--4R */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_ADDR_HI 0x00003084 /* R--4R */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_INST_LO 0x00003088 /* R--4R */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_INST_HI 0x0000308C /* R--4R */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_INFO 0x00003090 /* R--4R */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_STATUS 0x00003094 /* RW-4R */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_PDB 0x000030A0 /* RW-4R */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_PDB_APERTURE 1:1 /* RWEVF */
@@ -210,5 +228,51 @@
#define NV_VIRTUAL_FUNCTION_PRIV_DOORBELL 0x2200 /* -W-4R */
#define NV_VIRTUAL_FUNCTION_DOORBELL 0x30090 /* -W-4R */
#define NV_VIRTUAL_FUNCTION_ERR_CONT 0x30094 /* R--4R */
#define NV_VIRTUAL_FUNCTION_PRIV_MSIX_TABLE_VECTOR_CONTROL__SIZE_1 6 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_BAR1_BLOCK 0x00000F40 /* RW-4R */
#define NV_VIRTUAL_FUNCTION_PRIV_BAR1_BLOCK__VFALIAS NV_VBUS_VF_BAR1_BLOCK(f) /* */
#define NV_VIRTUAL_FUNCTION_PRIV_BAR1_BLOCK_MAP 29:0 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_BAR1_BLOCK_PTR 27:0 /* RWIUF */
#define NV_VIRTUAL_FUNCTION_PRIV_BAR1_BLOCK_PTR_0 0x00000000 /* RWI-V */
#define NV_VIRTUAL_FUNCTION_PRIV_BAR1_BLOCK_TARGET 29:28 /* RWIUF */
#define NV_VIRTUAL_FUNCTION_PRIV_BAR1_BLOCK_TARGET_VID_MEM 0x00000000 /* RWI-V */
#define NV_VIRTUAL_FUNCTION_PRIV_BAR1_BLOCK_TARGET_SYS_MEM_COHERENT 0x00000002 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_BAR1_BLOCK_TARGET_SYS_MEM_NONCOHERENT 0x00000003 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_BAR1_BLOCK_MODE 31:31 /* RWIUF */
#define NV_VIRTUAL_FUNCTION_PRIV_BAR1_BLOCK_MODE_PHYSICAL 0x00000000 /* RWI-V */
#define NV_VIRTUAL_FUNCTION_PRIV_BAR1_BLOCK_MODE_VIRTUAL 0x00000001 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_BAR2_BLOCK 0x00000F48 /* RW-4R */
#define NV_VIRTUAL_FUNCTION_PRIV_BAR2_BLOCK__VFALIAS NV_VBUS_VF_BAR2_BLOCK(f) /* */
#define NV_VIRTUAL_FUNCTION_PRIV_BAR2_BLOCK_MAP 29:0 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_BAR2_BLOCK_PTR 27:0 /* RWIUF */
#define NV_VIRTUAL_FUNCTION_PRIV_BAR2_BLOCK_PTR_0 0x00000000 /* RWI-V */
#define NV_VIRTUAL_FUNCTION_PRIV_BAR2_BLOCK_TARGET 29:28 /* RWIUF */
#define NV_VIRTUAL_FUNCTION_PRIV_BAR2_BLOCK_TARGET_VID_MEM 0x00000000 /* RWI-V */
#define NV_VIRTUAL_FUNCTION_PRIV_BAR2_BLOCK_TARGET_SYS_MEM_COHERENT 0x00000002 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_BAR2_BLOCK_TARGET_SYS_MEM_NONCOHERENT 0x00000003 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_BAR2_BLOCK_DEBUG_CYA 30:30 /* RWIUF */
#define NV_VIRTUAL_FUNCTION_PRIV_BAR2_BLOCK_DEBUG_CYA_OFF 0x00000001 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_BAR2_BLOCK_DEBUG_CYA_ON 0x00000000 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_BAR2_BLOCK_DEBUG_CYA_INIT 0x00000001 /* RWI-V */
#define NV_VIRTUAL_FUNCTION_PRIV_BAR2_BLOCK_MODE 31:31 /* RWIUF */
#define NV_VIRTUAL_FUNCTION_PRIV_BAR2_BLOCK_MODE_PHYSICAL 0x00000000 /* RWI-V */
#define NV_VIRTUAL_FUNCTION_PRIV_BAR2_BLOCK_MODE_VIRTUAL 0x00000001 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_BIND_STATUS 0x00000F50 /* R--4R */
#define NV_VIRTUAL_FUNCTION_PRIV_BIND_STATUS__VFALIAS NV_VBUS_VF_BIND_STATUS(f) /* */
#define NV_VIRTUAL_FUNCTION_PRIV_BIND_STATUS_BAR1_PENDING 0:0 /* R-IUF */
#define NV_VIRTUAL_FUNCTION_PRIV_BIND_STATUS_BAR1_PENDING_EMPTY 0x00000000 /* R-I-V */
#define NV_VIRTUAL_FUNCTION_PRIV_BIND_STATUS_BAR1_PENDING_BUSY 0x00000001 /* R---V */
#define NV_VIRTUAL_FUNCTION_PRIV_BIND_STATUS_BAR1_OUTSTANDING 1:1 /* R-IUF */
#define NV_VIRTUAL_FUNCTION_PRIV_BIND_STATUS_BAR1_OUTSTANDING_FALSE 0x00000000 /* R-I-V */
#define NV_VIRTUAL_FUNCTION_PRIV_BIND_STATUS_BAR1_OUTSTANDING_TRUE 0x00000001 /* R---V */
#define NV_VIRTUAL_FUNCTION_PRIV_BIND_STATUS_BAR2_PENDING 2:2 /* R-IUF */
#define NV_VIRTUAL_FUNCTION_PRIV_BIND_STATUS_BAR2_PENDING_EMPTY 0x00000000 /* R-I-V */
#define NV_VIRTUAL_FUNCTION_PRIV_BIND_STATUS_BAR2_PENDING_BUSY 0x00000001 /* R---V */
#define NV_VIRTUAL_FUNCTION_PRIV_BIND_STATUS_BAR2_OUTSTANDING 3:3 /* R-IUF */
#define NV_VIRTUAL_FUNCTION_PRIV_BIND_STATUS_BAR2_OUTSTANDING_FALSE 0x00000000 /* R-I-V */
#define NV_VIRTUAL_FUNCTION_PRIV_BIND_STATUS_BAR2_OUTSTANDING_TRUE 0x00000001 /* R---V */
#define NV_VIRTUAL_FUNCTION_PRIV_MSIX_TABLE_VECTOR_CONTROL(i) (0x0001000C+(i)*16) /* RW-4A */
#define NV_VIRTUAL_FUNCTION_PRIV_MSIX_TABLE_VECTOR_CONTROL__SIZE_1 6 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_MSIX_TABLE_VECTOR_CONTROL_MASK_BIT 0:0 /* RWIVF */
#define NV_VIRTUAL_FUNCTION_PRIV_MSIX_TABLE_VECTOR_CONTROL_MASK_BIT_UNMASKED 0x00000000 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_MSIX_TABLE_VECTOR_CONTROL_MASK_BIT_MASKED 0x00000001 /* RWI-V */
#endif // __tu102_dev_vm_h__

7
src/common/inc/swref/published/turing/tu102/hwproject.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2021-2021 NVIDIA CORPORATION & AFFILIATES
* SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -25,5 +25,10 @@
#define __tu102_hwproject_h__
#define NV_CHIP_EXTENDED_SYSTEM_PHYSICAL_ADDRESS_BITS 47
#define NV_HOST_NUM_PBDMA 12
#define NV_SCAL_LITTER_NUM_FBPAS 16
#define NV_FBPA_PRI_STRIDE 16384
#define NV_LTC_PRI_STRIDE 8192
#define NV_LTS_PRI_STRIDE 512
#endif // __tu102_hwproject_h__

60
src/common/inc/swref/published/volta/gv100/dev_boot.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2021 NVIDIA CORPORATION & AFFILIATES
* SPDX-FileCopyrightText: Copyright (c) 2003-2023 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -44,4 +44,62 @@
#define NV_PMC_INTR_EN_CLEAR_DEVICE__SIZE_1 32 /* */
#define NV_PMC_INTR_EN_CLEAR_DEVICE_SET 0x00000001 /* */
#define NV_PMC_INTR_EN_CLEAR_VALUE 31:0 /* -W-VF */
#define NV_PMC_ENABLE 0x00000200 /* RW-4R */
#define NV_PMC_ENABLE_PMEDIA 4:4 /* */
#define NV_PMC_ENABLE_PMEDIA_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_PMEDIA_ENABLED 0x00000001 /* */
#define NV_PMC_ENABLE_PFIFO 8:8 /* RWIVF */
#define NV_PMC_ENABLE_PFIFO_DISABLED 0x00000000 /* RWI-V */
#define NV_PMC_ENABLE_PFIFO_ENABLED 0x00000001 /* RW--V */
#define NV_PMC_ENABLE_PWR 13:13 /* */
#define NV_PMC_ENABLE_PWR_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_PWR_ENABLED 0x00000001 /* */
#define NV_PMC_ENABLE_PGRAPH 12:12 /* */
#define NV_PMC_ENABLE_PGRAPH_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_PGRAPH_ENABLED 0x00000001 /* */
#define NV_PMC_ENABLE_SEC 14:14 /* */
#define NV_PMC_ENABLE_SEC_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_SEC_ENABLED 0x00000001 /* */
#define NV_PMC_ENABLE_CE0 6:6 /* */
#define NV_PMC_ENABLE_CE0_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_CE0_ENABLED 0x00000001 /* */
#define NV_PMC_ENABLE_CE1 7:7 /* */
#define NV_PMC_ENABLE_CE1_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_CE1_ENABLED 0x00000001 /* */
#define NV_PMC_ENABLE_CE2 21:21 /* */
#define NV_PMC_ENABLE_CE2_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_CE2_ENABLED 0x00000001 /* */
#define NV_PMC_ENABLE_CE3 22:22 /* */
#define NV_PMC_ENABLE_CE3_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_CE3_ENABLED 0x00000001 /* */
#define NV_PMC_ENABLE_CE4 23:23 /* */
#define NV_PMC_ENABLE_CE4_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_CE4_ENABLED 0x00000001 /* */
#define NV_PMC_ENABLE_CE5 24:24 /* */
#define NV_PMC_ENABLE_CE5_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_CE5_ENABLED 0x00000001 /* */
#define NV_PMC_ENABLE_CE6 9:9 /* */
#define NV_PMC_ENABLE_CE6_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_CE6_ENABLED 0x00000001 /* */
#define NV_PMC_ENABLE_CE7 10:10 /* */
#define NV_PMC_ENABLE_CE7_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_CE7_ENABLED 0x00000001 /* */
#define NV_PMC_ENABLE_CE8 11:11 /* */
#define NV_PMC_ENABLE_CE8_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_CE8_ENABLED 0x00000001 /* */
#define NV_PMC_ENABLE_NVDEC 15:15 /* */
#define NV_PMC_ENABLE_NVDEC_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_NVDEC_ENABLED 0x00000001 /* */
#define NV_PMC_ENABLE_PDISP 30:30 /* RWIVF */
#define NV_PMC_ENABLE_PDISP_DISABLED 0x00000000 /* RW--V */
#define NV_PMC_ENABLE_PDISP_ENABLED 0x00000001 /* RWI-V */
#define NV_PMC_ENABLE_NVENC0 18:18 /* */
#define NV_PMC_ENABLE_NVENC0_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_NVENC0_ENABLED 0x00000001 /* */
#define NV_PMC_ENABLE_NVENC1 19:19 /* */
#define NV_PMC_ENABLE_NVENC1_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_NVENC1_ENABLED 0x00000001 /* */
#define NV_PMC_ENABLE_NVENC2 4:4 /* */
#define NV_PMC_ENABLE_NVENC2_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_NVENC2_ENABLED 0x00000001 /* */
#endif // __gv100_dev_boot_h__

40
src/common/inc/swref/published/volta/gv100/dev_fault.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2021 NVIDIA CORPORATION & AFFILIATES
* SPDX-FileCopyrightText: Copyright (c) 2003-2023 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -24,4 +24,42 @@
#ifndef __gv100_dev_fault_h__
#define __gv100_dev_fault_h__
#define NV_PFAULT_MMU_ENG_ID_GRAPHICS 64 /* */
#define NV_PFAULT_MMU_ENG_ID_PHYSICAL 31 /* */
#define NV_PFAULT_ACCESS_TYPE_VIRT_READ 0x00000000 /* */
#define NV_PFAULT_ACCESS_TYPE_VIRT_WRITE 0x00000001 /* */
#define NV_PFAULT_ACCESS_TYPE_VIRT_ATOMIC 0x00000002 /* */
#define NV_PFAULT_ACCESS_TYPE_VIRT_ATOMIC_STRONG 0x00000002 /* */
#define NV_PFAULT_ACCESS_TYPE_VIRT_PREFETCH 0x00000003 /* */
#define NV_PFAULT_ACCESS_TYPE_VIRT_ATOMIC_WEAK 0x00000004 /* */
#define NV_PFAULT_ACCESS_TYPE_PHYS_READ 0x00000008 /* */
#define NV_PFAULT_ACCESS_TYPE_PHYS_WRITE 0x00000009 /* */
#define NV_PFAULT_ACCESS_TYPE_PHYS_ATOMIC 0x0000000a /* */
#define NV_PFAULT_ACCESS_TYPE_PHYS_PREFETCH 0x0000000b /* */
#define NV_PFAULT_MMU_ENG_ID_CE0 15 /* */
#define NV_PFAULT_MMU_ENG_ID_CE1 16 /* */
#define NV_PFAULT_MMU_ENG_ID_CE2 17 /* */
#define NV_PFAULT_MMU_ENG_ID_CE3 18 /* */
#define NV_PFAULT_MMU_ENG_ID_CE4 19 /* */
#define NV_PFAULT_MMU_ENG_ID_CE5 20 /* */
#define NV_PFAULT_MMU_ENG_ID_CE6 21 /* */
#define NV_PFAULT_MMU_ENG_ID_CE7 22 /* */
#define NV_PFAULT_MMU_ENG_ID_CE8 23 /* */
#define NV_PFAULT_FAULT_TYPE_PDE 0x00000000 /* */
#define NV_PFAULT_FAULT_TYPE_PDE_SIZE 0x00000001 /* */
#define NV_PFAULT_FAULT_TYPE_PTE 0x00000002 /* */
#define NV_PFAULT_FAULT_TYPE_VA_LIMIT_VIOLATION 0x00000003 /* */
#define NV_PFAULT_FAULT_TYPE_UNBOUND_INST_BLOCK 0x00000004 /* */
#define NV_PFAULT_FAULT_TYPE_PRIV_VIOLATION 0x00000005 /* */
#define NV_PFAULT_FAULT_TYPE_RO_VIOLATION 0x00000006 /* */
#define NV_PFAULT_FAULT_TYPE_WO_VIOLATION 0x00000007 /* */
#define NV_PFAULT_FAULT_TYPE_PITCH_MASK_VIOLATION 0x00000008 /* */
#define NV_PFAULT_FAULT_TYPE_WORK_CREATION 0x00000009 /* */
#define NV_PFAULT_FAULT_TYPE_UNSUPPORTED_APERTURE 0x0000000a /* */
#define NV_PFAULT_FAULT_TYPE_COMPRESSION_FAILURE 0x0000000b /* */
#define NV_PFAULT_FAULT_TYPE_UNSUPPORTED_KIND 0x0000000c /* */
#define NV_PFAULT_FAULT_TYPE_REGION_VIOLATION 0x0000000d /* */
#define NV_PFAULT_FAULT_TYPE_POISONED 0x0000000e /* */
#define NV_PFAULT_FAULT_TYPE_ATOMIC_VIOLATION 0x0000000f /* */
#define NV_PFAULT_MMU_CLIENT_TYPE_GPC 0x00000000 /* */
#define NV_PFAULT_MMU_CLIENT_TYPE_HUB 0x00000001 /* */
#endif // __gv100_dev_fault_h__

51
src/common/inc/swref/published/volta/gv100/dev_fb.h
View File

@@ -73,6 +73,8 @@
#define NV_PFB_NISO_ACCESS_COUNTER_NOTIFY_BUFFER_CLR_WRITE_NACK 31:31 /* -WIVF */
#define NV_PFB_NISO_ACCESS_COUNTER_NOTIFY_BUFFER_CLR_WRITE_NACK_INIT 0x0 /* -WI-V */
#define NV_PFB_NISO_ACCESS_COUNTER_NOTIFY_BUFFER_CLR_WRITE_NACK_CLR 0x1 /* -W--V */
#define NV_PFB_PRI_MMU_NON_REPLAY_FAULT_BUFFER 0
#define NV_PFB_PRI_MMU_REPLAY_FAULT_BUFFER 1
#define NV_PFB_PRI_MMU_FAULT_BUFFER_GET(i) (0x00100E2C+(i)*20) /* RW-4A */
#define NV_PFB_PRI_MMU_FAULT_BUFFER_GET__SIZE_1 2 /* */
#define NV_PFB_PRI_MMU_FAULT_BUFFER_GET_PTR 19:0 /* RWEVF */
@@ -95,6 +97,44 @@
#define NV_PFB_PRI_MMU_FAULT_BUFFER_PUT_OVERFLOW 31:31 /* R-EVF */
#define NV_PFB_PRI_MMU_FAULT_BUFFER_PUT_OVERFLOW_NO 0x00000000 /* R-E-V */
#define NV_PFB_PRI_MMU_FAULT_BUFFER_PUT_OVERFLOW_YES 0x00000001 /* R---V */
#define NV_PFB_PRI_MMU_FAULT_ADDR_LO_ADDR 31:12 /* R-EVF */
#define NV_PFB_PRI_MMU_FAULT_ADDR_HI_ADDR 31:0 /* R-EVF */
#define NV_PFB_PRI_MMU_FAULT_INST_LO_ENGINE_ID 8:0 /* R-EVF */
#define NV_PFB_PRI_MMU_FAULT_INST_LO_APERTURE 11:10 /* R-EVF */
#define NV_PFB_PRI_MMU_FAULT_INST_LO_ADDR 31:12 /* R-EVF */
#define NV_PFB_PRI_MMU_FAULT_INST_HI_ADDR 31:0 /* R-EVF */
#define NV_PFB_PRI_MMU_FAULT_INFO_FAULT_TYPE 4:0 /* R-EVF */
#define NV_PFB_PRI_MMU_FAULT_INFO_FAULT_TYPE_RESET 0x00000000 /* R-E-V */
#define NV_PFB_PRI_MMU_FAULT_INFO_REPLAYABLE_FAULT 7:7 /* R-EVF */
#define NV_PFB_PRI_MMU_FAULT_INFO_REPLAYABLE_FAULT_RESET 0x00000000 /* R-E-V */
#define NV_PFB_PRI_MMU_FAULT_INFO_CLIENT 14:8 /* R-EVF */
#define NV_PFB_PRI_MMU_FAULT_INFO_CLIENT_RESET 0x00000000 /* R-E-V */
#define NV_PFB_PRI_MMU_FAULT_INFO_ACCESS_TYPE 19:16 /* R-EVF */
#define NV_PFB_PRI_MMU_FAULT_INFO_ACCESS_TYPE_READ 0x00000000 /* R---V */
#define NV_PFB_PRI_MMU_FAULT_INFO_ACCESS_TYPE_WRITE 0x00000001 /* R---V */
#define NV_PFB_PRI_MMU_FAULT_INFO_ACCESS_TYPE_ATOMIC 0x00000002 /* R---V */
#define NV_PFB_PRI_MMU_FAULT_INFO_ACCESS_TYPE_PREFETCH 0x00000003 /* R---V */
#define NV_PFB_PRI_MMU_FAULT_INFO_ACCESS_TYPE_VIRT_READ 0x00000000 /* R---V */
#define NV_PFB_PRI_MMU_FAULT_INFO_ACCESS_TYPE_VIRT_WRITE 0x00000001 /* R---V */
#define NV_PFB_PRI_MMU_FAULT_INFO_ACCESS_TYPE_VIRT_ATOMIC 0x00000002 /* R---V */
#define NV_PFB_PRI_MMU_FAULT_INFO_ACCESS_TYPE_VIRT_ATOMIC_STRONG 0x00000002 /* R---V */
#define NV_PFB_PRI_MMU_FAULT_INFO_ACCESS_TYPE_VIRT_PREFETCH 0x00000003 /* R---V */
#define NV_PFB_PRI_MMU_FAULT_INFO_ACCESS_TYPE_VIRT_ATOMIC_WEAK 0x00000004 /* R---V */
#define NV_PFB_PRI_MMU_FAULT_INFO_ACCESS_TYPE_PHYS_READ 0x00000008 /* R---V */
#define NV_PFB_PRI_MMU_FAULT_INFO_ACCESS_TYPE_PHYS_WRITE 0x00000009 /* R---V */
#define NV_PFB_PRI_MMU_FAULT_INFO_ACCESS_TYPE_PHYS_ATOMIC 0x0000000a /* R---V */
#define NV_PFB_PRI_MMU_FAULT_INFO_ACCESS_TYPE_PHYS_PREFETCH 0x0000000b /* R---V */
#define NV_PFB_PRI_MMU_FAULT_INFO_ACCESS_TYPE_RESET 0x00000000 /* R-E-V */
#define NV_PFB_PRI_MMU_FAULT_INFO_CLIENT_TYPE 20:20 /* R-EVF */
#define NV_PFB_PRI_MMU_FAULT_INFO_CLIENT_TYPE_RESET 0x00000000 /* R-E-V */
#define NV_PFB_PRI_MMU_FAULT_INFO_GPC_ID 28:24 /* R-EVF */
#define NV_PFB_PRI_MMU_FAULT_INFO_GPC_ID_RESET 0x00000000 /* R-E-V */
#define NV_PFB_PRI_MMU_FAULT_INFO_PROTECTED_MODE 29:29 /* R-EVF */
#define NV_PFB_PRI_MMU_FAULT_INFO_PROTECTED_MODE_RESET 0x00000000 /* R-E-V */
#define NV_PFB_PRI_MMU_FAULT_INFO_REPLAYABLE_FAULT_EN 30:30 /* R-EVF */
#define NV_PFB_PRI_MMU_FAULT_INFO_REPLAYABLE_FAULT_EN_RESET 0x00000000 /* R-E-V */
#define NV_PFB_PRI_MMU_FAULT_INFO_VALID 31:31 /* R-EVF */
#define NV_PFB_PRI_MMU_FAULT_INFO_VALID_RESET 0x00000000 /* R-E-V */
#define NV_PFB_PRI_MMU_FAULT_STATUS 0x00100E60 /* RW-4R */
#define NV_PFB_PRI_MMU_FAULT_STATUS_DROPPED_BAR1_PHYS 0:0 /* RWEVF */
#define NV_PFB_PRI_MMU_FAULT_STATUS_DROPPED_BAR1_PHYS_RESET 0x00000000 /* RWE-V */
@@ -159,4 +199,15 @@
#define NV_PFB_PRI_MMU_FAULT_STATUS_VALID_RESET 0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FAULT_STATUS_VALID_CLEAR 0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_FAULT_STATUS_VALID_SET 0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_FAULT_BUFFER_SIZE_VAL 19:0 /* RWEVF */
#define NV_PFB_PRI_MMU_FAULT_BUFFER_SIZE_VAL_RESET 0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FAULT_BUFFER_SIZE_OVERFLOW_INTR 29:29 /* RWEVF */
#define NV_PFB_PRI_MMU_FAULT_BUFFER_SIZE_OVERFLOW_INTR_DISABLE 0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FAULT_BUFFER_SIZE_OVERFLOW_INTR_ENABLE 0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_FAULT_BUFFER_SIZE_SET_DEFAULT 30:30 /* RWEVF */
#define NV_PFB_PRI_MMU_FAULT_BUFFER_SIZE_SET_DEFAULT_NO 0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FAULT_BUFFER_SIZE_SET_DEFAULT_YES 0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_FAULT_BUFFER_SIZE_ENABLE 31:31 /* RWEVF */
#define NV_PFB_PRI_MMU_FAULT_BUFFER_SIZE_ENABLE_FALSE 0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FAULT_BUFFER_SIZE_ENABLE_TRUE 0x00000001 /* RW--V */
#endif // __gv100_dev_fb_h__

66
src/common/inc/swref/published/volta/gv11b/dev_boot.h Normal file
View File

@@ -0,0 +1,66 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2021 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gv11b_dev_boot_h__
#define __gv11b_dev_boot_h__
#define NV_PMC_ENABLE 0x00000200 /* RW-4R */
#define NV_PMC_ENABLE_PMEDIA 4:4 /* */
#define NV_PMC_ENABLE_PMEDIA_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_PMEDIA_ENABLED 0x00000001 /* */
#define NV_PMC_ENABLE_PFIFO 8:8 /* RWIVF */
#define NV_PMC_ENABLE_PFIFO_DISABLED 0x00000000 /* RWI-V */
#define NV_PMC_ENABLE_PFIFO_ENABLED 0x00000001 /* RW--V */
#define NV_PMC_ENABLE_PWR 13:13 /* */
#define NV_PMC_ENABLE_PWR_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_PWR_ENABLED 0x00000001 /* */
#define NV_PMC_ENABLE_PGRAPH 12:12 /* */
#define NV_PMC_ENABLE_PGRAPH_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_PGRAPH_ENABLED 0x00000001 /* */
#define NV_PMC_ENABLE_SEC 14:14 /* */
#define NV_PMC_ENABLE_SEC_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_SEC_ENABLED 0x00000001 /* */
#define NV_PMC_ENABLE_CE0 6:6 /* */
#define NV_PMC_ENABLE_CE0_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_CE0_ENABLED 0x00000001 /* */
#define NV_PMC_ENABLE_CE1 7:7 /* */
#define NV_PMC_ENABLE_CE1_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_CE1_ENABLED 0x00000001 /* */
#define NV_PMC_ENABLE_CE2 21:21 /* */
#define NV_PMC_ENABLE_CE2_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_CE2_ENABLED 0x00000001 /* */
#define NV_PMC_ENABLE_NVDEC 15:15 /* */
#define NV_PMC_ENABLE_NVDEC_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_NVDEC_ENABLED 0x00000001 /* */
#define NV_PMC_ENABLE_PDISP 30:30 /* RWIVF */
#define NV_PMC_ENABLE_PDISP_DISABLED 0x00000000 /* RW--V */
#define NV_PMC_ENABLE_PDISP_ENABLED 0x00000001 /* RWI-V */
#define NV_PMC_ENABLE_NVENC0 18:18 /* */
#define NV_PMC_ENABLE_NVENC0_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_NVENC0_ENABLED 0x00000001 /* */
#define NV_PMC_ENABLE_NVENC1 19:19 /* */
#define NV_PMC_ENABLE_NVENC1_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_NVENC1_ENABLED 0x00000001 /* */
#define NV_PMC_ENABLE_NVENC2 4:4 /* */
#define NV_PMC_ENABLE_NVENC2_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_NVENC2_ENABLED 0x00000001 /* */
#endif // __gv11b_dev_boot_h__

2
src/common/modeset/hdmipacket/nvhdmipkt.c
View File

@@ -243,7 +243,7 @@ NvHdmiPkt_PacketWrite(NvHdmiPkt_Handle libHandle,
((infoframeType == hdmi_pktType_GamutMetadata) && (packetLen < sizeof(NVT_GAMUT_METADATA))) ||
((infoframeType == hdmi_pktType_ExtendedMetadata) && (packetLen < sizeof(NVT_EXTENDED_METADATA_PACKET_INFOFRAME)))||
((infoframeType == hdmi_pktType_VendorSpecInfoFrame) && (packetLen < 8)) ||
((infoframeType == hdmi_pktType_AviInfoFrame) && (packetLen < sizeof(NVT_VIDEO_INFOFRAME))) ||
((infoframeType == hdmi_pktType_AviInfoFrame) && (packetLen < 13)) ||
((infoframeType == hdmi_pktType_SrcProdDescInfoFrame) && (packetLen < sizeof(NVT_SPD_INFOFRAME))) ||
((infoframeType == hdmi_pktType_DynamicRangeMasteringInfoFrame) && (packetLen < sizeof(NVT_HDR_INFOFRAME))))
// Unused: hdmi_pktType_AudioClkRegeneration

6
src/common/modeset/hdmipacket/nvhdmipkt.h
View File

@@ -127,6 +127,12 @@ typedef enum _NVHDMIPKT_TC
DRF_DEF(_HDMI_PKT, _TRANSMIT_CTRL, _SINGLE, _DIS) |
DRF_DEF(_HDMI_PKT, _TRANSMIT_CTRL, _CHKSUM_HW, _EN)),
NVHDMIPKT_TRANSMIT_CONTROL_ENABLE_EVERY_FRAME_SW_CHECKSUM =
(DRF_DEF(_HDMI_PKT, _TRANSMIT_CTRL, _ENABLE, _EN) |
DRF_DEF(_HDMI_PKT, _TRANSMIT_CTRL, _OTHER, _DIS) |
DRF_DEF(_HDMI_PKT, _TRANSMIT_CTRL, _SINGLE, _DIS) |
DRF_DEF(_HDMI_PKT, _TRANSMIT_CTRL, _CHKSUM_HW, _DIS)),
NVHDMIPKT_TRANSMIT_CONTROL_ENABLE_SINGLE_FRAME =
(DRF_DEF(_HDMI_PKT, _TRANSMIT_CTRL, _ENABLE, _EN) |
DRF_DEF(_HDMI_PKT, _TRANSMIT_CTRL, _OTHER, _DIS) |

4
src/common/modeset/hdmipacket/nvhdmipkt_9171.c
View File

@@ -36,7 +36,6 @@
#include "ctrl/ctrl0073/ctrl0073specific.h"
#define NVHDMIPKT_9171_INVALID_PKT_TYPE ((NV9171_SF_HDMI_INFO_IDX_VSI) + 1)
#define NVHDMIPKT_CTAIF_MAX_PKT_BYTES 31 // 3 bytes header + 28 bytes data (CTA infoframe max payload size)
#define NVHDMIPKT_9171_MAX_PKT_BYTES_AVI 17 // 3 bytes header + 14 bytes data
NVHDMIPKT_RESULT
@@ -157,8 +156,7 @@ hdmiWriteAviPacket9171(NVHDMIPKT_CLASS* pThis,
if (packetLen > NVHDMIPKT_9171_MAX_PKT_BYTES_AVI)
{
NvHdmiPkt_Print(pThis, "ERROR - input AVI packet length incorrect. Write will be capped to max allowable bytes");
NvHdmiPkt_Assert(0);
NvHdmiPkt_Print(pThis, "WARNING - input AVI packet length incorrect. Write will be capped to max allowable bytes");
}
data = REG_RD32(pBaseReg, NV9171_SF_HDMI_AVI_INFOFRAME_HEADER(head));

12
src/common/modeset/hdmipacket/nvhdmipkt_C671.c
View File

@@ -777,11 +777,15 @@ hdmiQueryFRLConfigC671(NVHDMIPKT_CLASS *pThis,
calcBppMinMax(pSrcCaps, pSinkCaps, pVidTransInfo, &bppMinX16, &bppMaxX16);
bCanUseDSC = evaluateIsDSCPossible(pThis, pSrcCaps, pSinkCaps, pVidTransInfo, &frlParams);
const NvU32 numHeadsDrivingSink = pVidTransInfo->bDualHeadMode ? 2 : 1;
// Input validation
// Note, maxNumHztSlices src cap is per head. account for total number of heads driving the sink
if ((pClientCtrl->forceFRLRate && (pClientCtrl->frlRate > pSinkCaps->linkMaxFRLRate)) ||
(pClientCtrl->enableDSC && !bCanUseDSC) ||
(pClientCtrl->forceSliceCount && (pClientCtrl->sliceCount > (NvU32)(NV_MIN(pSrcCaps->dscCaps.maxNumHztSlices, pSinkCaps->pHdmiForumInfo->dsc_MaxSlices)))) ||
(pClientCtrl->forceSliceCount && (pClientCtrl->sliceCount >
(NvU32)(NV_MIN(pSrcCaps->dscCaps.maxNumHztSlices * numHeadsDrivingSink,
pSinkCaps->pHdmiForumInfo->dsc_MaxSlices)))) ||
(pClientCtrl->forceSliceWidth && (pClientCtrl->sliceWidth > NV_MIN(pSrcCaps->dscCaps.maxWidthPerSlice, MAX_RECONSTRUCTED_HACTIVE_PIXELS))) ||
(pClientCtrl->forceBppx16 && ((pClientCtrl->bitsPerPixelX16 < bppMinX16) || (pClientCtrl->bitsPerPixelX16 > bppMaxX16))) ||
(pClientCtrl->forceBppx16 && !pSinkCaps->pHdmiForumInfo->dsc_All_bpp))
@@ -1171,20 +1175,18 @@ frlQuery_Success:
DSC_GENERATE_PPS_OPAQUE_WORKAREA *pDscScratchBuffer = NULL;
pDscScratchBuffer = (DSC_GENERATE_PPS_OPAQUE_WORKAREA*)pThis->callback.malloc(pThis->cbHandle,
sizeof(DSC_GENERATE_PPS_OPAQUE_WORKAREA));
if ((DSC_GeneratePPS(&dscInfo,
&dscModesetInfo,
&warData,
availableLinkBw,
pDscScratchBuffer,
pFRLConfig->dscInfo.pps,
&bitsPerPixelX16,
pDscScratchBuffer)) != NVT_STATUS_SUCCESS)
&bitsPerPixelX16)) != NVT_STATUS_SUCCESS)
{
NvHdmiPkt_Print(pThis, "ERROR - DSC PPS calculation failed.");
NvHdmiPkt_Assert(0);
result = NVHDMIPKT_FAIL;
}
if (pDscScratchBuffer != NULL)
{
pThis->callback.free(pThis->cbHandle, pDscScratchBuffer);

3
src/common/modeset/hdmipacket/nvhdmipkt_internal.h
View File

@@ -34,6 +34,9 @@
#define toHdmiPktHandle(p) ((NvHdmiPkt_Handle)(p))
#define fromHdmiPktHandle(h) ((NVHDMIPKT_CLASS*)(h))
// CTA infoframe max payload size
#define NVHDMIPKT_CTAIF_MAX_PKT_BYTES 31 // 3 bytes header + 28 bytes data
extern void initializeHdmiPktInterface0073(NVHDMIPKT_CLASS*);
extern void initializeHdmiPktInterface9171(NVHDMIPKT_CLASS*);
extern void initializeHdmiPktInterface9271(NVHDMIPKT_CLASS*);

599
src/common/modeset/timing/nvt_dsc_pps.c
View File

File diff suppressed because it is too large Load Diff

47
src/common/modeset/timing/nvt_dsc_pps.h
View File

@@ -42,7 +42,6 @@
#define DSC_MAX_PPS_SIZE_DWORD 32
/* ------------------------ Datatypes -------------------------------------- */
typedef struct
{
NvU32 versionMajor;
@@ -257,14 +256,8 @@ typedef struct
}dpData;
} WAR_DATA;
//
// DSC PPS calculations need large scratch buffer to work with, which can be too
// big for some platforms. These buffers need to be allocated on heap rather
// than local stack variable. Clients are expected to pre-allocate
// this buffer and pass it in to DSC PPS interface
//
typedef struct {
NvU8 data[512U]; // an upper bound of total size of DSC_IN/OUTPUT_PARAMS
NvU8 data[492U]; // total size of DSC_IN/OUTPUT_PARAMS
} DSC_GENERATE_PPS_OPAQUE_WORKAREA;
/*
@@ -281,6 +274,7 @@ typedef struct {
#ifdef __cplusplus
extern "C" {
#endif
/*
* @brief Calculate PPS parameters based on passed down Sink,
* GPU capability and modeset info
@@ -290,6 +284,8 @@ extern "C" {
* @param[in] pWARData Data required for providing WAR for issues
* @param[in] availableBandwidthBitsPerSecond Available bandwidth for video
* transmission(After FEC/Downspread overhead consideration)
* @param[in] pOpaqueWorkarea Scratch buffer of sufficient size pre-allocated
by client for DSC PPS calculations use
* @param[out] pps Calculated PPS parameter.
* The data can be send to SetDscPpsData* methods directly.
* @param[out] pBitsPerPixelX16 Bits per pixel multiplied by 16
@@ -301,9 +297,40 @@ NVT_STATUS DSC_GeneratePPS(const DSC_INFO *pDscInfo,
const MODESET_INFO *pModesetInfo,
const WAR_DATA *pWARData,
NvU64 availableBandwidthBitsPerSecond,
DSC_GENERATE_PPS_OPAQUE_WORKAREA *pOpaqueWorkarea,
NvU32 pps[DSC_MAX_PPS_SIZE_DWORD],
NvU32 *pBitsPerPixelX16,
DSC_GENERATE_PPS_OPAQUE_WORKAREA *pOpaqueWorkarea);
NvU32 *pBitsPerPixelX16);
/*
* @brief Calculate PPS parameters and slice count mask based on passed down
* Sink, GPU capability and modeset info
*
*
* @param[in] pDscInfo Includes Sink and GPU DSC capabilities
* @param[in] pModesetInfo Modeset related information
* @param[in] pWARData Data required for providing WAR for issues
* @param[in] availableBandwidthBitsPerSecond Available bandwidth for video
* transmission(After FEC/Downspread overhead consideration)
* @param[out] pps Calculated PPS parameter.
* The data can be send to SetDscPpsData* methods directly.
* @param[out] pBitsPerPixelX16 Bits per pixel multiplied by 16
* @param[out] pSliceCountMask Mask of all slice counts supported by the mode.
*
* @returns NVT_STATUS_SUCCESS if successful;
* NVT_STATUS_ERR if unsuccessful;
* In case this returns failure consider that PPS is not possible.
*/
NVT_STATUS
DSC_GeneratePPSWithSliceCountMask
(
const DSC_INFO *pDscInfo,
const MODESET_INFO *pModesetInfo,
const WAR_DATA *pWARData,
NvU64 availableBandwidthBitsPerSecond,
NvU32 pps[DSC_MAX_PPS_SIZE_DWORD],
NvU32 *pBitsPerPixelX16,
NvU32 *sliceCountMask
);
#ifdef __cplusplus
}

61
src/common/modeset/timing/nvt_edid.c
View File

@@ -1076,6 +1076,7 @@ NVT_STATUS NV_STDCALL NvTiming_ParseEDIDInfo(NvU8 *pEdid, NvU32 length, NVT_EDID
if (p861Info->revision >= NVT_CTA861_REV_H)
{
if (p861Info->total_vfdb != 0) parseCta861VideoFormatDataBlock(p861Info, pInfo);
if (p861Info->total_did_type7db != 0) parseCta861DIDType7VideoTimingDataBlock(p861Info, pInfo);
if (p861Info->total_did_type8db != 0) parseCta861DIDType8VideoTimingDataBlock(p861Info, pInfo);
if (p861Info->total_did_type10db != 0) parseCta861DIDType10VideoTimingDataBlock(p861Info, pInfo);
@@ -1105,9 +1106,14 @@ NVT_STATUS NV_STDCALL NvTiming_ParseEDIDInfo(NvU8 *pEdid, NvU32 length, NVT_EDID
pInfo->ext_displayid20.interface_features.yuv420_min_pclk = 0;
}
if (!pInfo->ext861.basic_caps)
if (pInfo->ext861.revision == 0 && pInfo->ext_displayid20.valid_data_blocks.interface_feature_present)
{
pInfo->ext861.basic_caps = pInfo->ext_displayid20.basic_caps;
pInfo->ext861.revision = NVT_CEA861_REV_B;
}
if (pInfo->ext_displayid20.valid_data_blocks.interface_feature_present)
{
pInfo->ext861.basic_caps |= pInfo->ext_displayid20.basic_caps;
}
}
}
@@ -1161,7 +1167,7 @@ NVT_STATUS NV_STDCALL NvTiming_ParseEDIDInfo(NvU8 *pEdid, NvU32 length, NVT_EDID
}
// check for cvt timings - in display range limits or cvt 3-byte LDD, only for EDID1.4 and above
if (pInfo->version > 0x0103)
if (pInfo->version > NVT_EDID_VER_1_3)
{
parseEdidCvtTiming(pInfo);
}
@@ -1436,7 +1442,7 @@ NVT_STATUS NvTiming_Get18ByteLongDescriptorIndex(NVT_EDID_INFO *pEdidInfo, NvU8
// get the edid timing
CODE_SEGMENT(PAGE_DD_CODE)
NVT_STATUS NvTiming_GetEdidTimingEx(NvU32 width, NvU32 height, NvU32 rr, NvU32 flag, NVT_EDID_INFO *pEdidInfo, NVT_TIMING *pT, NvU32 rrx1k)
NVT_STATUS NvTiming_GetEdidTimingExWithPclk(NvU32 width, NvU32 height, NvU32 rr, NvU32 flag, NVT_EDID_INFO *pEdidInfo, NVT_TIMING *pT, NvU32 rrx1k, NvU32 pclk)
{
NvU8 kth = 0;
NvU32 i, j;
@@ -1449,7 +1455,7 @@ NVT_STATUS NvTiming_GetEdidTimingEx(NvU32 width, NvU32 height, NvU32 rr, NvU32 f
if (pEdidInfo == NULL || pEdidInfo->total_timings == 0 || pT == 0)
return NVT_STATUS_ERR;
if (width == 0 || height == 0 || rr == 0) // rrx1k is optional, can be 0.
if (width == 0 || height == 0 || rr == 0 ) // rrx1k and pclk are optional, can be 0.
return NVT_STATUS_ERR;
pEdidTiming = pEdidInfo->timing;
@@ -1473,7 +1479,7 @@ NVT_STATUS NvTiming_GetEdidTimingEx(NvU32 width, NvU32 height, NvU32 rr, NvU32 f
if (pEdidInfo->ext861.total_svr > 1)
{
kth = getHighestPrioritySVRIdx(pEdidInfo->ext861.svr_vfpdb[0]);
kth = getHighestPrioritySVRIdx(&pEdidInfo->ext861);
}
for (i = 0; i < pEdidInfo->total_timings; i++)
@@ -1492,7 +1498,7 @@ NVT_STATUS NvTiming_GetEdidTimingEx(NvU32 width, NvU32 height, NvU32 rr, NvU32 f
((rrx1k == 0) || (rrx1k == pEdidTiming[i].etc.rrx1k)) &&
!!(flag & NVT_PVT_INTERLACED_MASK) == !!pEdidTiming[i].interlaced)
{
if (map0 >= pEdidInfo->total_timings)
if (map0 >= pEdidInfo->total_timings || pEdidTiming[i].pclk == pclk)
{
// make sure we take the priority as "detailed>standard>established". (The array timing[] always have the detailed timings in the front and then the standard and established.)
map0 = i;
@@ -1906,6 +1912,12 @@ NVT_STATUS NvTiming_GetEdidTimingEx(NvU32 width, NvU32 height, NvU32 rr, NvU32 f
return NVT_STATUS_SUCCESS;
}
CODE_SEGMENT(PAGE_DD_CODE)
NVT_STATUS NvTiming_GetEdidTimingEx(NvU32 width, NvU32 height, NvU32 rr, NvU32 flag, NVT_EDID_INFO *pEdidInfo, NVT_TIMING *pT, NvU32 rrx1k)
{
return NvTiming_GetEdidTimingExWithPclk(width, height, rr, flag, pEdidInfo, pT, rrx1k, 0);
}
// get the edid timing
CODE_SEGMENT(PAGE_DD_CODE)
NVT_STATUS NvTiming_GetEdidTiming(NvU32 width, NvU32 height, NvU32 rr, NvU32 flag, NVT_EDID_INFO *pEdidInfo, NVT_TIMING *pT)
@@ -2814,28 +2826,35 @@ NvBool assignNextAvailableTiming(NVT_EDID_INFO *pInfo,
}
/**
* @brief Return the first high priority nth index based on the different SVR
* @brief Return the nth highest priority index based on the different SVR
* @param svr Short Video Reference
*/
CODE_SEGMENT(PAGE_DD_CODE)
NvU8 getHighestPrioritySVRIdx(NvU8 svr)
NvU8 getHighestPrioritySVRIdx(const NVT_EDID_CEA861_INFO *pExt861)
{
// In general sink shall define the first one timing sequence
// In general, sink shall define the first one timing sequence
NvU8 kth = 1;
NvU8 i = 0;
// Reserved
if (svr == 0 || svr == 128 || (svr >= 176 && svr <= 192) || svr == 255)
return 0;
if (svr >= 129 && svr <= 144) return svr - 128; // Interpret as the Kth 18-byte DTD in both base0 and CTA block (for N = 1 to 16)
else if (svr >= 145 && svr <= 160) return svr - 144; // Interpret as the Nth 20-byte DTD or 6- or 7-byte CVT-based descriptor. (for N = 1 to 16)
else if (svr >= 161 && svr <= 175) return svr - 160; // Interpret as the video format indicated by the first VFD of the first VFDB with Frame Rates of Rate Index N (for N = 1 to 15)
else if (svr == 254) return kth; // Interpret as the timing format indicated by the first code of the first T8VTDB (for N = 1)
else // assign corresponding CTA format's timing from pre-defined CE timing table, EIA861B
for (i = 0; i < pExt861->total_svr; i++)
{
// ( SVR >= 1 and SVR <= 127) and (SVR >= 193 and SVR <= 253) needs to handle it by client
return svr;
NvU8 svr = pExt861->svr_vfpdb[i];
// Reserved
if (svr == 0 || svr == 128 || (svr >= 176 && svr <= 192) || svr == 255)
continue;
if (svr >= 129 && svr <= 144) return svr - 128; // Interpret as the Kth 18-byte DTD in both base0 and CTA block (for N = 1 to 16)
else if (svr >= 145 && svr <= 160) return svr - 144; // Interpret as the Nth 20-byte DTD or 6- or 7-byte CVT-based descriptor. (for N = 1 to 16)
else if (svr >= 161 && svr <= 175) return svr - 160; // Interpret as the video format indicated by the first VFD of the first VFDB with Frame Rates of Rate Index N (for N = 1 to 15)
else if (svr == 254) return kth; // Interpret as the timing format indicated by the first code of the first T8VTDB (for N = 1)
else // assign corresponding CTA format's timing from pre-defined CE timing table, EIA861B
{
// ( SVR >= 1 and SVR <= 127) and (SVR >= 193 and SVR <= 253) needs to handle it by client
return svr;
}
}
return 0;
}

560
src/common/modeset/timing/nvt_edidext_861.c
View File

@@ -40,7 +40,6 @@ PUSH_SEGMENTS
{hv,0,hfp,hsw,ht,(hsp)=='-',vv,0,vfp,vsw,vt,(vsp)=='-',(ip)=='i' ? NVT_INTERLACED:NVT_PROGRESSIVE,\
0,{0,((rrx1k)+500)/1000,rrx1k,((1?aspect)<<16)|(0?aspect),rep,{0},{0},{0},{0},NVT_STATUS_EDID_861STn(format),"CEA-861B:#"#format""}}
#define NVT_TIMING(hv,hfp,hsw,ht,hsp,vv,vfp,vsw,vt,vsp,rrx1k,ip,aspect,rep,format,name) \
{hv,0,hfp,hsw,ht,(hsp)=='-',vv,0,vfp,vsw,vt,(vsp)=='-',(ip)=='i' ? NVT_INTERLACED:NVT_PROGRESSIVE,\
0,{0,((rrx1k)+500)/1000,rrx1k,((1?aspect)<<16)|(0?aspect),rep,{0},{0},{0},{0},NVT_TYPE_NV_PREDEFINEDn(format),name}}
@@ -49,6 +48,8 @@ PUSH_SEGMENTS
{hv,0,hfp,hsw,ht,(hsp)=='-',vv,0,vfp,vsw,vt,(vsp)=='-',(ip)=='i' ? NVT_INTERLACED:NVT_PROGRESSIVE,\
0,{0,((rrx1k)+500)/1000,rrx1k,((1?aspect)<<16)|(0?aspect),rep,{0},{0},{0},{0},NVT_STATUS_HDMI_EXTn(format),name}}
#define RID_MODE(hv, hsp, vv, vsp, ip, aspect, rid) \
{hv, (hsp)=='-', vv, (vsp)=='-',(ip)=='i'? NVT_INTERLACED:NVT_PROGRESSIVE,((1?aspect)<<16)|(0?aspect), rid}
DATA_SEGMENT(PAGE_DATA)
CONS_SEGMENT(PAGE_CONS)
@@ -280,7 +281,7 @@ static const NVT_TIMING EIA861B[]=
EIA_TIMING( 4096, 800, 88, 5280,'+',2160, 8,10,2250,'+',100000,'p',256:135,0x1,218),// 4096 x 2160p @100 (Format 218)
EIA_TIMING( 4096, 88, 88, 4400,'+',2160, 8,10,2250,'+',119880,'p',256:135,0x1,219),// 4096 x 2160p @119.88/120 (Format 219)
// 220-255 Reserved for the Future
// the end
// the end
EIA_TIMING(0,0,0,0,'-',0,0,0,0,'-',0,'p',4:3,0,0)
};
static NvU32 MAX_CEA861B_FORMAT = sizeof(EIA861B)/sizeof(EIA861B[0]) - 1;
@@ -338,6 +339,81 @@ static const NvU32 EIA861B_DUAL_ASPECT_VICS[][2] =
};
static NvU32 MAX_EIA861B_DUAL_ASPECT_VICS = sizeof(EIA861B_DUAL_ASPECT_VICS) / sizeof(EIA861B_DUAL_ASPECT_VICS[0]);
static const NVT_RID_CODES RID[] =
{
RID_MODE( 0, '+', 0, '+', 'p', 16:9 , 0), // No Resolution Identification Available
RID_MODE( 1280, '+', 720, '+', 'p', 16:9 , 1), // HD, 720p
RID_MODE( 1280, '+', 720, '+', 'p', 64:27, 2), // HD, 720p, 21:9 anamorphic
RID_MODE( 1680, '+', 720, '+', 'p', 64:27, 3), // 21:9 "1.5k"
RID_MODE( 1920, '+', 1080, '+', 'p', 16:9 , 4), // Full HD, 1080p
RID_MODE( 1929, '+', 1080, '+', 'p', 64:27, 5), // Full HD, 1080p, 21:9 anamorphic
RID_MODE( 2560, '+', 1080, '+', 'p', 64:27, 6), // 21:9 "2.5k"
RID_MODE( 3840, '+', 1080, '+', 'p', 32:9 , 7), // 32:9 "4K"
RID_MODE( 2560, '+', 1440, '+', 'p', 16:9 , 8), // QHD, 1440p
RID_MODE( 3440, '+', 1440, '+', 'p', 64:27, 9), // WQHD
RID_MODE( 5120, '+', 1440, '+', 'p', 32:9 ,10), // 32:9 5k
RID_MODE( 3840, '+', 2160, '+', 'p', 16:9 ,11), // HD "4K", 2160p
RID_MODE( 3840, '+', 2160, '+', 'p', 64:27,12), // UHD "4K", 2160p, 21:9 anamorphic
RID_MODE( 5120, '+', 2160, '+', 'p', 64:27,13), // 21:9 "5K"
RID_MODE( 7680, '+', 2160, '+', 'p', 32:9 ,14), // 32:9 "8K"
RID_MODE( 5120, '+', 2880, '+', 'p', 16:9 ,15), // 2880p
RID_MODE( 5120, '+', 2880, '+', 'p', 64:27,16), // 2880p, 21:9 anamorphic
RID_MODE( 6880, '+', 2880, '+', 'p', 64:27,17), // 21:9 "6K"
RID_MODE(10240, '+', 2880, '+', 'p', 32:9 ,18), // 32:9 "10K"
RID_MODE( 7680, '+', 4320, '+', 'p', 16:9 ,19), // UHD "8K", 4320p
RID_MODE( 7680, '+', 4320, '+', 'p', 64:27,20), // UHD "8K", 4320p, 21:9 anamorphic
RID_MODE(10240, '+', 4320, '+', 'p', 64:27,21), // 21:9 "10K"
RID_MODE(15360, '+', 4320, '+', 'p', 32:9 ,22), // 32:9 "15K"
RID_MODE(11520, '+', 6480, '+', 'p', 16:9 ,23), // UHD "12K", 6480p
RID_MODE(11520, '+', 6480, '+', 'p', 64:27,24), // UHD "12K", 6480p, 21:9 anamorphic
RID_MODE(15360, '+', 6480, '+', 'p', 64:27,25), // 21:9 "15K"
RID_MODE(15360, '+', 8640, '+', 'p', 16:9 ,26), // UHD "16K", 8640p
RID_MODE(15360, '+', 8640, '+', 'p', 64:27,27), // UHD "16K", 8640p, 21:9 anamorphic
RID_MODE(20480, '+', 8640, '+', 'p', 64:27,28) // 21:9 "20K"
// 29...63 Reserved for future
};
static NvU32 MAX_RID_CODES_COUNT = sizeof(RID) / sizeof(RID[0]) - 1;
// RID to VIC Mapping
static const NvU8 RID_VIC_MAP[][8] =
{
{ 0, 0, 0, 0, 0, 0, 0, 0 },
{ 60, 61, 62, 108, 19, 4, 41, 47 }, // RID 01
{ 65, 66, 67, 109, 68, 69, 70, 71 }, // RID 02
{ 79, 80, 81, 110, 82, 83, 84, 85 }, // RID 03
{ 32, 33, 34, 111, 31, 16, 64, 63 }, // RID 04
{ 72, 73, 74, 112, 75, 76, 77, 78 }, // RID 05
{ 86, 87, 88, 113, 89, 90, 91, 92 }, // RID 06
{ 0, 0, 0, 0, 0, 0, 0, 0 },
{ 0, 0, 0, 0, 0, 0, 0, 0 },
{ 0, 0, 0, 0, 0, 0, 0, 0 },
{ 0, 0, 0, 0, 0, 0, 0, 0 },
{ 93, 94, 95, 114, 96, 97, 117, 118 }, // RID 11
{ 103, 104, 105, 116, 106, 107, 119, 120 }, // RID 12
{ 121, 122, 123, 124, 125, 126, 127, 193 }, // RID 13
{ 0, 0, 0, 0, 0, 0, 0, 0 },
{ 0, 0, 0, 0, 0, 0, 0, 0 },
{ 0, 0, 0, 0, 0, 0, 0, 0 },
{ 0, 0, 0, 0, 0, 0, 0, 0 },
{ 0, 0, 0, 0, 0, 0, 0, 0 },
{ 194, 195, 196, 197, 198, 199, 200, 201 }, // RID 19
{ 202, 203, 204, 205, 206, 207, 208, 209 }, // RID 20
{ 210, 211, 212, 213, 214, 215, 216, 217 }, // RID 21
{ 0, 0, 0, 0, 0, 0, 0, 0 },
{ 0, 0, 0, 0, 0, 0, 0, 0 },
{ 0, 0, 0, 0, 0, 0, 0, 0 },
{ 0, 0, 0, 0, 0, 0, 0, 0 },
{ 0, 0, 0, 0, 0, 0, 0, 0 },
{ 0, 0, 0, 0, 0, 0, 0, 0 }
};
// All the frame rate supported in VF
static const NvU16 VF_FRAME_RATE[] =
{
0, 24, 25, 30, 48, 50, 60, 100, 120, 144, 200, 240, 300, 360, 400, 480
};
static NvU8 MAX_VF_FRAME_RATE_COUNT = sizeof(VF_FRAME_RATE) / sizeof (VF_FRAME_RATE[0])-1;
static const NVT_TIMING PSF_TIMING[]=
{
NVT_TIMING( 1920,600, 88,2750,'+', 540, 2,5,562,'+',47952,'i',16:9, 0x1, 1, "ITU-R BT.709-5:1080i/24Psf"),//1920x1080i @47.952Hz | 24/PsF | ITU-R BT.709-5
@@ -371,7 +447,7 @@ static const HDMI3DDETAILS HDMI_MANDATORY_3D_FORMATS[] =
{20, NVT_HDMI_3D_SUPPORTED_SIDEBYSIDEHALF_MASK, NVT_HDMI_VS_BYTE_OPT1_HDMI_3DEX_SSH} // 1920 x 1080i @ 50 Hz
};
static NvU32 MAX_HDMI_MANDATORY_3D_FORMAT = sizeof(HDMI_MANDATORY_3D_FORMATS) / sizeof(HDMI_MANDATORY_3D_FORMATS[0]);
static const NVT_VIDEO_INFOFRAME DEFAULT_VIDEO_INFOFRAME = {/*header*/2,2,13, /*byte1*/0, /*byte2*/0x8, /*byte3*/0, /*byte4*/0, /*byte5*/0, /*byte6~13*/0,0,0,0,0,0,0,0};
static const NVT_VIDEO_INFOFRAME DEFAULT_VIDEO_INFOFRAME = {/*header*/2,2,13, /*byte1*/0, /*byte2*/0x8, /*byte3*/0, /*byte4*/0, /*byte5*/0, /*byte6~13*/0,0,0,0,0,0,0,0, /*byte14~15*/0,0};
static const NVT_AUDIO_INFOFRAME DEFAULT_AUDIO_INFOFRAME = {/*header*/4,1,10, /*byte1*/0, /*byte2*/0, /*byte3*/0, /*byte*/0, /*byte5*/0, /*byte6~10*/0,0,0,0,0};
CODE_SEGMENT(PAGE_DD_CODE)
@@ -388,6 +464,7 @@ getExistedCTATimingSeqNumber(
case NVT_TYPE_CTA861_DID_T7:
case NVT_TYPE_CTA861_DID_T8:
case NVT_TYPE_CTA861_DID_T10:
case NVT_TYPE_EDID_861ST:
break;
default:
return count;
@@ -395,13 +472,79 @@ getExistedCTATimingSeqNumber(
for (i = 0; i< pInfo->total_timings; i++)
{
if (NVT_GET_TIMING_STATUS_TYPE(pInfo->timing[i].etc.status) == timingType)
if (timingType == NVT_TYPE_EDID_861ST)
{
if (NVT_TIMING_IS_OVT(pInfo->timing[i].etc.flag))
++count;
}
else if (NVT_GET_TIMING_STATUS_TYPE(pInfo->timing[i].etc.status) == timingType)
{
++count;
}
}
return count;
}
CODE_SEGMENT(PAGE_DD_CODE)
static NvBool isVFDRefreshRate(NvU8 vfdSize, NvU8 *vfd, NvU8 rateIdx)
{
NvU8 rid, factor, i;
NvU16 rr;
NvBool bFR24, bFR48, bBFR50, bBFR60, bFR144, bFRFactor;
// frame rate factor {0.5x, 1x, 2x, 4x, 6x, 8x} x 2
const NvU8 frame_rate_factors[6] = { 1, 2, 4, 8, 12, 16 };
rr = VF_FRAME_RATE[rateIdx];
factor = 0;
rid = ((const VFD_ONE_BYTE*)vfd)->rid;
if (rid == 0) return NV_FALSE;
bBFR50 = ((const VFD_ONE_BYTE*)vfd)->bfr50;
// frame rate factor
// If Byte 2 is not present in the VFD, flags 0.5X, 1X and BFR60 shall be considered set
bBFR60 = vfdSize > 1 ? ((const VFD_TWO_BYTE*)vfd)->bfr60 : 1;
bFRFactor = vfdSize > 1 ? ((const VFD_TWO_BYTE*)vfd)->frRate : 3;
// individual frame rate
bFR24 = ((const VFD_ONE_BYTE*)vfd)->fr24;
if (rr == 24) return bFR24;
// individual frame rate
bFR48 = vfdSize > 2 ? ((const VFD_THREE_BYTE*)vfd)->fr48 : 0;
if (rr == 48) return bFR48;
// individual frame rate
bFR144 = vfdSize > 1 ? ((const VFD_TWO_BYTE*)vfd)->fr144 : 0;
if (rr == 144) return bFR144;
if (rr % (50/2) == 0)
{
if (!bBFR50) return NV_FALSE;
factor = rr / 25;
}
else if (rr % (60/2) == 0)
{
if (!bBFR60) return NV_FALSE;
factor = rr / 30;
}
for (i = 0; i < COUNT(frame_rate_factors); i++)
{
if (frame_rate_factors[i] == factor)
{
if (bFRFactor & (1 << i))
return NV_TRUE;
else
break;
}
}
return NV_FALSE;
}
// parse the 861 detailed timing info
CODE_SEGMENT(PAGE_DD_CODE)
void parse861ExtDetailedTiming(NvU8 *pEdidExt,
@@ -485,7 +628,7 @@ void parse861bShortTiming(NVT_EDID_CEA861_INFO *pExt861,
for (i = 0; i < total_svd; i++)
{
vic = NVT_GET_CTA_8BIT_VIC(pVic[i]);
vic = NVT_GET_CTA_8BIT_VIC(pVic[i]);
if (vic == 0 || vic > MAX_CEA861B_FORMAT)
continue;
@@ -563,6 +706,120 @@ void parse861bShortTiming(NVT_EDID_CEA861_INFO *pExt861,
}
}
CODE_SEGMENT(PAGE_DD_CODE)
void parseCta861VideoFormatDataBlock(NVT_EDID_CEA861_INFO *pExt861, void *pRawInfo)
{
NvU8 i = 0;
NvU8 rateIdx = 0;
NvU8 vfdb_idx = 0;
NvU8 startSeqNum = 0;
NvU8 eachOfDescSize = 0;
NvU32 width = 0;
NvU32 height = 0;
const VFD_ONE_BYTE *pVFDOneByte = 0 ;
NVT_TIMING newTiming;
NVT_EDID_INFO *pInfo = (NVT_EDID_INFO *)pRawInfo;
for (vfdb_idx = 0; vfdb_idx < pExt861->total_vfdb; vfdb_idx++)
{
eachOfDescSize = pExt861->vfdb[vfdb_idx].info.vfd_len + 1;
if (eachOfDescSize == 0)
{
nvt_assert(0 && "Video Format Descriptor length is 0!\n");
return;
}
for (i = 0; i < pExt861->vfdb[vfdb_idx].total_vfd; i++)
{
// data block value sanity check:
if (eachOfDescSize > 2 && (((const VFD_THREE_BYTE*)&pExt861->vfdb[vfdb_idx].video_format_desc[i*eachOfDescSize])->f31_37 != 0))
nvt_assert(0 && "F31-F37 bits does not be 0 in Byte3!.\n");
if (eachOfDescSize > 3 && ((const VFD_FOUR_BYTE*)&pExt861->vfdb[vfdb_idx].video_format_desc[i*eachOfDescSize])->f40_47 !=0)
nvt_assert(0 && "It is not support yet in Byte4!");
pVFDOneByte = (const VFD_ONE_BYTE *)&pExt861->vfdb[vfdb_idx].video_format_desc[i*eachOfDescSize];
/*
* If any of the following is true, then the RID shall be set to 0:
* 1. If a Video Format not listed in "Table 12 - Resolution Identification (RID) is sent
* 2. if a Video Format with Frame Rates not listed in "Table 13 - AVI InfoFrame Video Format Frame Rate" is sent
* 3. if a Video Format listed in "Table 14 - RID To VIC Mapping" is sent.
*/
// For 1.
if ((pVFDOneByte->rid & NVT_CTA861_VF_RID_MASK) == 0 || pVFDOneByte->rid > MAX_RID_CODES_COUNT)
{
nvt_assert(0 && "shall have a non-zero RID value or RID code value larger than 28");
continue;
}
width = RID[pVFDOneByte->rid].HVisible;
height = RID[pVFDOneByte->rid].VVisible;
// If the Source is sending a Video Format that can be indicated by RID and FR,
// and is not listed in Table 14 (RID to VIC), then it shall set the RID and FR fields to the proper codes
for (rateIdx = 1; rateIdx <= MAX_VF_FRAME_RATE_COUNT; rateIdx++)
{
// For 2.
if (!isVFDRefreshRate(eachOfDescSize, &pExt861->vfdb[vfdb_idx].video_format_desc[i*eachOfDescSize], rateIdx))
{
continue;
}
// For 3.
if (VF_FRAME_RATE[rateIdx] < 144 && RID_VIC_MAP[pVFDOneByte->rid][rateIdx-1])
{
nvt_assert(0 && "RID not allowed since it maps to VIC!");
continue;
}
startSeqNum = getExistedCTATimingSeqNumber(pInfo, NVT_TYPE_EDID_861ST);
NVMISC_MEMSET(&newTiming, 0, sizeof(newTiming));
if (NvTiming_CalcOVT(width, height, VF_FRAME_RATE[rateIdx], &newTiming) == NVT_STATUS_SUCCESS)
{
if (pExt861->vfdb[vfdb_idx].info.y420 && newTiming.pclk > NVT_HDMI_YUV_420_PCLK_SUPPORTED_MIN)
{
UPDATE_BPC_FOR_COLORFORMAT(newTiming.etc.yuv420, 0, 1,
pInfo->hdmiForumInfo.dc_30bit_420,
pInfo->hdmiForumInfo.dc_36bit_420, 0,
pInfo->hdmiForumInfo.dc_48bit_420);
}
newTiming.etc.flag |= NVT_FLAG_CTA_OVT_TIMING;
if (pExt861->vfdb[vfdb_idx].info.ntsc)
{
newTiming.etc.flag |= NVT_FLAG_CTA_OVT_FRR_TIMING;
}
newTiming.etc.status = NVT_STATUS_EDID_861STn(++startSeqNum);
NVT_SNPRINTF((char *)newTiming.etc.name, sizeof(newTiming.etc.name), "CTA861-OVT%d:#%3d:%dx%dx%3d.%03dHz/%s",
(int)pVFDOneByte->rid,
(int)NVT_GET_TIMING_STATUS_SEQ(newTiming.etc.status),
(int)newTiming.HVisible,
(int)newTiming.VVisible,
(int)newTiming.etc.rrx1k/1000,
(int)newTiming.etc.rrx1k%1000,
(newTiming.interlaced ? "I":"P"));
newTiming.etc.name[sizeof(newTiming.etc.name) - 1] = '\0';
if (!assignNextAvailableTiming(pInfo, &newTiming))
{
continue;
}
}
else
{
continue;
}
}
}
}
}
// parse the 861B short Yuv420 timing descriptor
CODE_SEGMENT(PAGE_DD_CODE)
void parse861bShortYuv420Timing(NVT_EDID_CEA861_INFO *pExt861,
@@ -603,7 +860,6 @@ void parse861bShortYuv420Timing(NVT_EDID_CEA861_INFO *pExt861,
return;
}
for (i = 0; i < total_y420vdb; i++)
{
vic = NVT_GET_CTA_8BIT_VIC(pYuv420Vic[i]);
@@ -735,6 +991,7 @@ void parseCta861NativeOrPreferredTiming(NVT_EDID_CEA861_INFO *pExt861,
NvU8 extDTDCount = 0;
NvU8 DIDT7Count = 0;
NvU8 DIDT10Count = 0;
NvU8 OVTCount = 0;
if (flag == FROM_CTA861_EXTENSION || flag == FROM_DISPLAYID_13_DATA_BLOCK)
{
@@ -765,10 +1022,11 @@ void parseCta861NativeOrPreferredTiming(NVT_EDID_CEA861_INFO *pExt861,
else if (NVT_IS_EXT_DTD(pInfo->timing[j].etc.status)) extDTDCount++;
else if (NVT_IS_CTA861_DID_T7(pInfo->timing[j].etc.status)) DIDT7Count++;
else if (NVT_IS_CTA861_DID_T10(pInfo->timing[j].etc.status)) DIDT10Count++;
else if (NVT_TIMING_IS_OVT(pInfo->timing[j].etc.flag)) OVTCount++;
}
}
// this only handle single SVR right now
// this only handles single SVR
for (i = 0; i < totalSvr; i++)
{
NvU8 svr = 0;
@@ -804,17 +1062,12 @@ void parseCta861NativeOrPreferredTiming(NVT_EDID_CEA861_INFO *pExt861,
break;
}
}
if (pExt861->valid.NVRDB == 1)
pInfo->timing[j].etc.flag |= NVT_FLAG_CTA_NATIVE_TIMING;
else
pInfo->timing[j].etc.flag |= NVT_FLAG_CTA_PREFERRED_TIMING;
}
}
else if (svr >= 145 && svr <= 160)
{
// Interpret as the Nth 20-byte DTD or 6- or 7-byte CVT-based descriptor
// where N = SVR – 144 (for N = 1 to 16)
// where N = SVR - 144 (for N = 1 to 16)
kth = svr - 144;
if (flag == FROM_CTA861_EXTENSION)
@@ -833,18 +1086,24 @@ void parseCta861NativeOrPreferredTiming(NVT_EDID_CEA861_INFO *pExt861,
break;
}
}
if (pExt861->valid.NVRDB == 1)
pInfo->timing[j].etc.flag |= NVT_FLAG_CTA_NATIVE_TIMING;
else
pInfo->timing[j].etc.flag |= NVT_FLAG_CTA_PREFERRED_TIMING;
}
}
}
else if (svr >= 161 && svr <= 175)
{
// Interpret as the video format indicated by the first VFD of the first VFDB with Frame Rates of Rate Index N
// where N = SVR - 160 (for N = 1 to 15)
break;
kth = svr - 160;
if (flag == FROM_CTA861_EXTENSION)
{
for (j = 0; j < pInfo->total_timings; j++)
{
if (kth <= OVTCount)
{
if (NVT_IS_CTA861_OVT_Tn(pInfo->timing[j].etc.flag, pInfo->timing[j].etc.status, kth))
break;
}
}
}
}
else if (svr == 254)
{
@@ -855,15 +1114,11 @@ void parseCta861NativeOrPreferredTiming(NVT_EDID_CEA861_INFO *pExt861,
{
if (NVT_IS_CTA861_DID_T8_1(pInfo->timing[j].etc.status))
{
if (pExt861->valid.NVRDB == 1)
pInfo->timing[j].etc.flag |= NVT_FLAG_CTA_NATIVE_TIMING;
else
pInfo->timing[j].etc.flag |= NVT_FLAG_CTA_PREFERRED_TIMING;
kth = 1;
break;
}
}
}
break;
}
else // assign corresponding CEA format's timing from pre-defined CE timing table, EIA861B
{
@@ -877,13 +1132,7 @@ void parseCta861NativeOrPreferredTiming(NVT_EDID_CEA861_INFO *pExt861,
{
isMatch = NvTiming_IsTimingExactEqual(&pInfo->timing[j], &preferTiming);
if (isMatch && (NVT_GET_TIMING_STATUS_TYPE(pInfo->timing[j].etc.status) == NVT_TYPE_EDID_861ST))
{
if (pExt861->valid.NVRDB == 1)
pInfo->timing[j].etc.flag |= NVT_FLAG_CTA_NATIVE_TIMING;
else
pInfo->timing[j].etc.flag |= NVT_FLAG_CTA_PREFERRED_TIMING;
break;
}
}
}
else if (flag == FROM_DISPLAYID_20_DATA_BLOCK)
@@ -892,16 +1141,25 @@ void parseCta861NativeOrPreferredTiming(NVT_EDID_CEA861_INFO *pExt861,
{
isMatch = NvTiming_IsTimingExactEqual(&pDisplayID20->timing[j], &preferTiming);
if (isMatch && (NVT_GET_TIMING_STATUS_TYPE(pDisplayID20->timing[j].etc.status) == NVT_TYPE_EDID_861ST))
{
if (pExt861->valid.NVRDB == 1)
pDisplayID20->timing[j].etc.flag |= NVT_FLAG_CTA_NATIVE_TIMING | NVT_FLAG_DISPLAYID_2_0_TIMING;
else
pDisplayID20->timing[j].etc.flag |= NVT_FLAG_CTA_PREFERRED_TIMING | NVT_FLAG_DISPLAYID_2_0_TIMING;
break;
}
}
}
}
if (flag == FROM_CTA861_EXTENSION || flag == FROM_DISPLAYID_13_DATA_BLOCK)
{
if (pExt861->valid.NVRDB == 1)
pInfo->timing[j].etc.flag |= NVT_FLAG_CTA_NATIVE_TIMING;
else if (vic != 0 || kth != 0)
pInfo->timing[j].etc.flag |= NVT_FLAG_CTA_PREFERRED_TIMING;
}
else if (flag == FROM_DISPLAYID_20_DATA_BLOCK)
{
if (pExt861->valid.NVRDB == 1)
pDisplayID20->timing[j].etc.flag |= NVT_FLAG_CTA_NATIVE_TIMING | NVT_FLAG_DISPLAYID_2_0_TIMING;
else if (vic !=0 || kth != 0)
pDisplayID20->timing[j].etc.flag |= NVT_FLAG_CTA_PREFERRED_TIMING | NVT_FLAG_DISPLAYID_2_0_TIMING;
}
}
}
@@ -1423,6 +1681,7 @@ NVT_STATUS parseCta861DataBlockInfo(NvU8 *p,
NvU32 vsvdb_index = 0;
NvU32 yuv420vdb_index = 0;
NvU32 yuv420cmdb_index = 0;
NvU8 vfd_index = 0;
NvU8 didT7_index = 0;
NvU8 didT8_index = 0;
NvU8 didT10_index = 0;
@@ -1456,6 +1715,9 @@ NVT_STATUS parseCta861DataBlockInfo(NvU8 *p,
case NVT_CEA861_TAG_VESA_DTC:
case NVT_CEA861_TAG_RSVD:
break;
case NVT_CTA861_TAG_VIDEO_FORMAT:
if (payload < 2) return NVT_STATUS_ERR; // no VFD
break;
case NVT_CEA861_TAG_VENDOR:
if (payload < 3) return NVT_STATUS_ERR;
break;
@@ -1504,7 +1766,7 @@ NVT_STATUS parseCta861DataBlockInfo(NvU8 *p,
}
break;
default:
break;
break;
}
return NVT_STATUS_SUCCESS;
}
@@ -1592,6 +1854,22 @@ NVT_STATUS parseCta861DataBlockInfo(NvU8 *p,
vendor_index++;
}
}
else if (tag == NVT_CTA861_TAG_VIDEO_FORMAT)
{
p861info->vfdb[vfd_index].info.vfd_len = p[i] & 0x03;
p861info->vfdb[vfd_index].info.ntsc = (p[i] & 0x40) >> 6;
p861info->vfdb[vfd_index].info.y420 = (p[i] & 0x80) >> 7;
p861info->vfdb[vfd_index].total_vfd = (NvU8)(payload - 1) / (p861info->vfdb[vfd_index].info.vfd_len + 1);
i++; payload--;
for (j = 0; j < payload; j++, i++)
{
p861info->vfdb[vfd_index].video_format_desc[j] = p[i];
}
p861info->total_vfdb = ++vfd_index;
}
else if (tag == NVT_CEA861_TAG_EXTENDED_FLAG)
{
if (payload >= 1)
@@ -2025,6 +2303,7 @@ NVT_STATUS NvTiming_ConstructVideoInfoframeCtrl(const NVT_TIMING *pTiming, NVT_V
{
// Prior RFE 543088
if (pCtrl->video_format_id == 0 &&
!(NVT_FRR_TIMING_IS_OVT(pTiming->etc.flag) || NVT_TIMING_IS_OVT(pTiming->etc.flag)) &&
NVT_GET_TIMING_STATUS_TYPE(pTiming->etc.status) == NVT_TYPE_EDID_861ST)
{
pCtrl->video_format_id = (NvU8)NVT_GET_TIMING_STATUS_SEQ(pTiming->etc.status);
@@ -2040,6 +2319,129 @@ NVT_STATUS NvTiming_ConstructVideoInfoframeCtrl(const NVT_TIMING *pTiming, NVT_V
}
}
// setup RID code
if (pCtrl->rid == NVT_INFOFRAME_CTRL_DONTCARE)
{
if (NVT_TYPE_EDID_861ST == NVT_GET_TIMING_STATUS_TYPE(pTiming->etc.status) &&
NVT_TIMING_IS_OVT(pTiming->etc.flag))
{
NvU8 ridIdx = 0;
// get the correct rid from the name string = CTA861-OVT'%d':xxx
// %d value shall included two digital or one digital character
if (pTiming->etc.name[11] == ':')
{
ridIdx = pTiming->etc.name[10] - '0';
}
else
{
ridIdx = 10 * (pTiming->etc.name[10] - '0') + (pTiming->etc.name[11] - '0');
}
if (ridIdx > NVT_CTA861_RID_1280x720p_16x9 &&
ridIdx < NVT_CTA861_RID_20480x8640p_64x27)
{
pCtrl->rid = ridIdx;
}
else
{
pCtrl->rid = NVT_INFOFRAME_CTRL_DONTCARE;
}
}
}
// setup Video Format Frame Rate
if (pCtrl->rid != NVT_INFOFRAME_CTRL_DONTCARE)
{
switch (pTiming->etc.rr)
{
case 24:
pCtrl->frame_rate = NVT_CTA861_FR_2400;
if (NVT_FRR_TIMING_IS_OVT(pTiming->etc.flag))
{
pCtrl->frame_rate = NVT_CTA861_FR_2398;
}
break;
case 25:
pCtrl->frame_rate = NVT_CTA861_FR_2500;
break;
case 30:
pCtrl->frame_rate = NVT_CTA861_FR_3000;
if (NVT_FRR_TIMING_IS_OVT(pTiming->etc.flag))
{
pCtrl->frame_rate = NVT_CTA861_FR_2997;
}
break;
case 48:
pCtrl->frame_rate = NVT_CTA861_FR_48000;
if (NVT_FRR_TIMING_IS_OVT(pTiming->etc.flag))
{
pCtrl->frame_rate = NVT_CTA861_FR_4795;
}
break;
case 50:
pCtrl->frame_rate = NVT_CTA861_FR_5000;
break;
case 60:
pCtrl->frame_rate = NVT_CTA861_FR_6000;
if (NVT_FRR_TIMING_IS_OVT(pTiming->etc.flag))
{
pCtrl->frame_rate = NVT_CTA861_FR_5994;
}
break;
case 100:
pCtrl->frame_rate = NVT_CTA861_FR_10000;
break;
case 120:
pCtrl->frame_rate = NVT_CTA861_FR_12000;
if (NVT_FRR_TIMING_IS_OVT(pTiming->etc.flag))
{
pCtrl->frame_rate = NVT_CTA861_FR_11988;
}
break;
case 144:
pCtrl->frame_rate = NVT_CTA861_FR_14400;
if (NVT_FRR_TIMING_IS_OVT(pTiming->etc.flag))
{
pCtrl->frame_rate = NVT_CTA861_FR_14386;
}
break;
case 200:
pCtrl->frame_rate = NVT_CTA861_FR_20000;
break;
case 240:
pCtrl->frame_rate = NVT_CTA861_FR_24000;
if (NVT_FRR_TIMING_IS_OVT(pTiming->etc.flag))
{
pCtrl->frame_rate = NVT_CTA861_FR_23976;
}
break;
case 300:
pCtrl->frame_rate = NVT_CTA861_FR_30000;
break;
case 360:
pCtrl->frame_rate = NVT_CTA861_FR_36000;
if (NVT_FRR_TIMING_IS_OVT(pTiming->etc.flag))
{
pCtrl->frame_rate = NVT_CTA861_FR_35964;
}
break;
case 400:
pCtrl->frame_rate = NVT_CTA861_FR_40000;
break;
case 480:
pCtrl->frame_rate = NVT_CTA861_FR_48000;
if (NVT_FRR_TIMING_IS_OVT(pTiming->etc.flag))
{
pCtrl->frame_rate = NVT_CTA861_FR_47952;
}
break;
default:
pCtrl->frame_rate = NVT_INFOFRAME_CTRL_DONTCARE;
break;
}
}
// for HDMI_EXT timing, AVI VIC should be 0.
if (NVT_GET_TIMING_STATUS_TYPE(pTiming->etc.status) == NVT_TYPE_HDMI_EXT)
{
@@ -2125,47 +2527,42 @@ NVT_STATUS NvTiming_ConstructVideoInfoframe(NVT_EDID_INFO *pEdidInfo, NVT_VIDEO_
// init the header
pInfoFrame->type = NVT_INFOFRAME_TYPE_VIDEO;
// TODO : This is just to check the version, we still need to change lots of structure
// "NVT_VIDEO_INFOFRAME" / "VIDEO_INFOFRAME" / "DEFAULT_VIDEO_INFOFRAME" / "NVM_DISP_STATE" etc..
// to accept the new ACE0-3 bits supported in the future. Right now no any sink to support this.
//
// Based on the latest CTA-861-H.pdf file, we need to do following logic to get the correct CTA861 version
// When Y=7, the IDO defines the C, EC and ACE fields, it shall use AVI InfoFrame Version 4.
// When Y < 7, the following algorithm shall be used for AVI InfoFrame version selection:
// if (C=3 and EC=7)
// Sources shall use AVI InfoFrame Version 4.
// Else if (VIC>=128)
// Sources shall use AVI InfoFrame Version 3.
// Else
// Sources shall use AVI InfoFrame Version 2.
// End if
//
// see 6.4 Format of Version 2, 3, and 4 AVI InfoFrames in CTA861-I
if (pCtrl)
{
if (nvt_get_bits(pInfoFrame->byte1, NVT_VIDEO_INFOFRAME_BYTE1_Y2Y1Y0_MASK, NVT_VIDEO_INFOFRAME_BYTE1_Y2Y1Y0_SHIFT) == NVT_VIDEO_INFOFRAME_BYTE1_Y2Y1Y0_IDODEFINED)
{
pInfoFrame->version = NVT_VIDEO_INFOFRAME_VERSION_4;
}
else if (nvt_get_bits(pInfoFrame->byte1, NVT_VIDEO_INFOFRAME_BYTE1_Y2Y1Y0_MASK, NVT_VIDEO_INFOFRAME_BYTE1_Y2Y1Y0_SHIFT) < NVT_VIDEO_INFOFRAME_BYTE1_Y2Y1Y0_IDODEFINED)
if (nvt_get_bits(pInfoFrame->byte1, NVT_VIDEO_INFOFRAME_BYTE1_Y2Y1Y0_MASK, NVT_VIDEO_INFOFRAME_BYTE1_Y2Y1Y0_SHIFT) <= NVT_VIDEO_INFOFRAME_BYTE1_Y2Y1Y0_YCbCr420) // this shall be as 0 always.
{
if ((pCtrl->rid != NVT_CTA861_RID_NONE) || (pCtrl->frame_rate != NVT_CTA861_FR_NO_DATA))
{
pInfoFrame->version = NVT_VIDEO_INFOFRAME_VERSION_4; // just put the logic to get the correct version 4, but it shall not be used at currently stage.
pInfoFrame->length = sizeof(NVT_VIDEO_INFOFRAME) - sizeof(NVT_INFOFRAME_HEADER); // Length == 15
}
else
if ((nvt_get_bits(pInfoFrame->byte2, NVT_VIDEO_INFOFRAME_BYTE2_C1C0_MASK, NVT_VIDEO_INFOFRAME_BYTE2_C1C0_SHIFT) == NVT_VIDEO_INFOFRAME_BYTE2_C1C0_EXT_COLORIMETRY) &&
//EC2-0 is based on the 7.5.5 at CTA861-G which DCI-P3 bit defined or notat byte4
(nvt_get_bits(pInfoFrame->byte3, NVT_VIDEO_INFOFRAME_BYTE3_EC_MASK, NVT_VIDEO_INFOFRAME_BYTE3_EC_SHIFT) == NVT_VIDEO_INFOFRAME_BYTE3_EC_AdditionalColorExt))
{
pInfoFrame->version = NVT_VIDEO_INFOFRAME_VERSION_4; // just put the logic to get the correct version 4, but it shall not be used at currently stage.
pInfoFrame->version = NVT_VIDEO_INFOFRAME_VERSION_4; // just put the logic to get the correct version 4, but it shall not be used at currently stage.
pInfoFrame->length = 14;
}
else
{
pInfoFrame->version = (((pCtrl->video_format_id & NVT_VIDEO_INFOFRAME_BYTE4_VIC7) == NVT_VIDEO_INFOFRAME_BYTE4_VIC7) ? NVT_VIDEO_INFOFRAME_VERSION_3 :
pInfoFrame->version = (((pCtrl->video_format_id & NVT_VIDEO_INFOFRAME_BYTE4_VIC7) != 0) ? NVT_VIDEO_INFOFRAME_VERSION_3 :
((pEdidInfo->ext861.revision >= NVT_CEA861_REV_B) ? NVT_VIDEO_INFOFRAME_VERSION_2 : NVT_VIDEO_INFOFRAME_VERSION_1));
pInfoFrame->length = 13;
}
}
else // Y=7, the IDO defineds the C, EC, ACE fileds. In the case the Source shall set the AVI InforFrame Version filed to no less than 3
{
pInfoFrame->version = NVT_VIDEO_INFOFRAME_VERSION_4;
pInfoFrame->length = 14;
}
}
else
{
pInfoFrame->version = (pEdidInfo->ext861.revision >= NVT_CEA861_REV_B) ? NVT_VIDEO_INFOFRAME_VERSION_2 : NVT_VIDEO_INFOFRAME_VERSION_1;
pInfoFrame->length = 13;
}
pInfoFrame->length = sizeof(NVT_VIDEO_INFOFRAME) - sizeof(NVT_INFOFRAME_HEADER);
if (pInfoFrame->version < NVT_VIDEO_INFOFRAME_VERSION_3)
{
@@ -2287,6 +2684,34 @@ NVT_STATUS NvTiming_ConstructVideoInfoframe(NVT_EDID_INFO *pEdidInfo, NVT_VIDEO_
pInfoFrame->right_bar_low = (NvU8)(pCtrl->right_bar % 0x100);
pInfoFrame->right_bar_high = (NvU8)(pCtrl->right_bar / 0x100);
}
// byte 14-15
if (pInfoFrame->version >= NVT_VIDEO_INFOFRAME_VERSION_4)
{
if (pCtrl->addition_colorimetry_ext != NVT_INFOFRAME_CTRL_DONTCARE)
{
nvt_nvu8_set_bits(pInfoFrame->byte14, pCtrl->addition_colorimetry_ext, NVT_VIDEO_INFOFRAME_BYTE14_ACE0_3_MASK, NVT_VIDEO_INFOFRAME_BYTE14_ACE0_3_SHIFT);
}
if (pCtrl->frame_rate != NVT_INFOFRAME_CTRL_DONTCARE)
{
// Frame rate
nvt_nvu8_set_bits(pInfoFrame->byte14, pCtrl->frame_rate, NVT_VIDEO_INFOFRAME_BYTE14_FR0_FR3_MASK, NVT_VIDEO_INFOFRAME_BYTE14_FR0_FR3_SHIFT);
pInfoFrame->byte15 &= NVT_VIDEO_INFOFRAME_BYTE15_FR4_MASK^0xFFU;
pInfoFrame->byte15 |= ((pCtrl->frame_rate & NVT_VIDEO_INFOFRAME_BYTE14_FR4_ONE_BIT_MASK) << NVT_VIDEO_INFOFRAME_BYTE15_FR4_SHIFT) & NVT_VIDEO_INFOFRAME_BYTE15_FR4_MASK;
}
if (pCtrl->rid != NVT_INFOFRAME_CTRL_DONTCARE)
{
// RID
nvt_nvu8_set_bits(pInfoFrame->byte15, pCtrl->rid, NVT_VIDEO_INFOFRAME_BYTE15_RID_MASK, NVT_VIDEO_INFOFRAME_BYTE15_RID_SHIFT);
}
}
else // version 2 or 3
{
pInfoFrame->byte14 = 0;
pInfoFrame->byte15 = 0;
}
}
return NVT_STATUS_SUCCESS;
@@ -2602,7 +3027,7 @@ NVT_STATUS NvTiming_ConstructExtendedMetadataPacketInfoframe(
}
else if (pCtrl->EnableQMS)
{
nvt_nvu8_set_bits(pInfoFrame->Data.metadataBytes[0], 1,
nvt_nvu8_set_bits(pInfoFrame->Data.metadataBytes[0], pCtrl->MConst,
NVT_HDMI_EMP_BYTE8_MD0_M_CONST_MASK,
NVT_HDMI_EMP_BYTE8_MD0_M_CONST_SHIFT);
nvt_nvu8_set_bits(pInfoFrame->Data.metadataBytes[0],
@@ -2711,6 +3136,16 @@ void NvTiming_ConstructAdaptiveSyncSDP(
NVT_DP_ADAPTIVE_SYNC_SDP_DB4_TARGET_RR_DIVIDER_MASK,
NVT_DP_ADAPTIVE_SYNC_SDP_DB4_TARGET_RR_DIVIDER_SHIFT);
}
if (pCtrl->srCoastingVTotal)
{
nvt_nvu8_set_bits(pSdp->payload.db7, pCtrl->srCoastingVTotal & 0xff,
NVT_DP_ADAPTIVE_SYNC_SDP_DB7_PR_COASTING_VTOTAL_LSB_MASK,
NVT_DP_ADAPTIVE_SYNC_SDP_DB7_PR_COASTING_VTOTAL_LSB_SHIFT);
nvt_nvu8_set_bits(pSdp->payload.db8, (pCtrl->srCoastingVTotal & 0xff00) >> 8,
NVT_DP_ADAPTIVE_SYNC_SDP_DB8_PR_COASTING_VTOTAL_MSB_MASK,
NVT_DP_ADAPTIVE_SYNC_SDP_DB8_PR_COASTING_VTOTAL_MSB_SHIFT);
}
}
// Enumerate Psf Timing
@@ -3406,7 +3841,6 @@ void parseEdidHdmiForumVSDB(VSDB_DATA *pVsdb, NVT_HDMI_FORUM_INFO *pHdmiInfo)
default:
break;
}
}

263
src/common/modeset/timing/nvt_ovt.c
View File

@@ -28,3 +28,266 @@
//*****************************************************************************
#include "nvBinSegment.h"
#include "nvmisc.h"
#include "nvtiming_pvt.h"
PUSH_SEGMENTS
CONS_SEGMENT(PAGE_CONS)
const NvU32 NVT_OVT_PIXEL_CLOCK_GRANULARITY = 1000; // Resulting Pixel Clock will be a multiple of this
const NvU32 NVT_OVT_MIN_H_TOTAL_GRANULARITY = 8; // Resulting Htotal value will be a multiple of this
const NvU32 NVT_OVT_MIN_V_BLANK_MICROSEC = 460; // Minimum duration of Vblank (us)
const NvU32 NVT_OVT_MIN_V_SYNC_LEADING_EDGE = 400; // Minimum duration of Vsync + Vback (us)
const NvU32 NVT_OVT_MIN_CLOCK_RATE_420 = 590000000; // interface-specific minimum pixel rate for transport of 4:2:0 sample
const NvU32 NVT_OVT_PIXEL_FACTOR_420 = 2; // Worst case of two pixels per link character for pixel rates of MinClockRate420 or more
const NvU32 NVT_OVT_MIN_H_BLANK_444 = 80; // Minimum Hblank width for pixel rates below MinClockRate420
const NvU32 NVT_OVT_MIN_H_BLANK_420 = 128; // Minimum Hblank width for pixel rates of MinClockRate420 or more
const NvU32 NVT_OVT_MAX_CHUNK_RATE = 650000000; // Maximum rate of chunks of pixels with a power-of-two size
const NvU32 NVT_OVT_AUDIO_PACKET_RATE = 195000; // 192k sample packets + 3k auxiliary data packets
const NvU32 NVT_OVT_AUDIO_PACKET_SIZE = 32; // each packet carries 8 audio sample
const NvU32 NVT_OVT_LINE_OVERHEAD = 32; // interface-specific overhead: 32 pixels/line
const NvU32 NVT_OVT_H_SYNC_PIXELS = 32;
const NvU32 NVT_OVT_H_BACK_WIDTH = 32;
const NvU32 NVT_OVT_V_SYNC_WIDTH = 8;
CODE_SEGMENT(PAGE_DD_CODE)
static NvU32 nvFloorPow2_U32(NvU32 x)
{
return x & ~(x - 1);
}
CODE_SEGMENT(PAGE_DD_CODE)
static NvU32 computeGCD(NvU32 a, NvU32 b)
{
NvU32 temp;
while (b != 0)
{
temp = a % b;
if (temp == 0) return b;
a = b;
b = temp;
}
return a;
}
CODE_SEGMENT(PAGE_DD_CODE)
static NvU32 calculate_aspect_ratio(NVT_TIMING *pT)
{
NvU32 gcd = computeGCD(pT->HVisible, pT->VVisible);
if (gcd == 0)
{
pT->etc.aspect = (NvU32)0;
return 0;
}
return (pT->HVisible / gcd) << 16 | (pT->VVisible / gcd);
}
/**
* OVT Algorithm Calculations Formula
*
* @brief Sinks can indicate supported video formats with VFD in a VFDB that are not represented by a CTA VIC.
* The timing parameters of those Video Formats are determined by the Optimized Video Timing(OVT) algorithm
*
* @param width : resolution width from RID
* @param height : resolution height from RID
* @param refreshRate : refresh rate x fraction rate
* @param pT : output all the parameters in NVT_TIMING
*
* @return NVT_STATUS_SUCCESS
*
*/
CODE_SEGMENT(PAGE_DD_CODE)
NVT_STATUS NvTiming_CalcOVT(NvU32 width, NvU32 height, NvU32 refreshRate, NVT_TIMING *pT)
{
NvU32 hTotal = 0;
NvU32 vTotal = 0;
NvU32 maxVRate = refreshRate;
NvU32 vTotalGranularity = 1;
NvU32 resolutionGranularity = 0;
NvU32 minVBlank, minVTotal, minLineRate, minHBlank, minHTotal, vBlank, vSyncPosition;
NvU32 hTotalGranularityChunk, hTotalGranularity, maxAudioPacketsPerLine;
NvU64 minPixelClockRate = 0LL;
NvU64 pixelClockRate = 0LL;
NvU64 maxActiveTime = 0LL;
NvU64 minLineTime = 0LL;
NvU64 minResolution = 0LL;
NvU32 V = 0;
NvU32 H = 0;
NvU64 R = 0;
// parameter sanity check
if (width % 8 != 0)
return NVT_STATUS_ERR;
// ** Preparation **
// 1. Determine maximum Vrate of frame rate group (see Table 13) and V-Total granularity:
switch (refreshRate)
{
case 24: case 25: case 30:
maxVRate = 30;
vTotalGranularity = 20;
break;
case 48: case 50: case 60:
maxVRate = 60;
vTotalGranularity = 20;
break;
case 100: case 120:
maxVRate = 120;
vTotalGranularity = 5;
break;
case 144:
maxVRate = 144;
vTotalGranularity = 1;
break;
case 200: case 240:
maxVRate = 240;
vTotalGranularity = 5;
break;
case 300: case 360:
maxVRate = 360;
vTotalGranularity = 5;
break;
case 400: case 480:
maxVRate = 480;
vTotalGranularity = 5;
break;
default:
vTotalGranularity = 1;
maxVRate = refreshRate;
nvt_assert (0 && "invalid input refresh rate!");
}
// 2. Minimum Vtotal is found from highest frame rate of Vrate group, Vactive and the minimum Vblank time of 460 μSec:
// 2.1 the minimum number of determine the maximum active time. For the sake of precision, it is multiplied by 1,000,000.
maxActiveTime = ((NvU64)1000000000000 / (NvU64)maxVRate) - (NvU64)NVT_OVT_MIN_V_BLANK_MICROSEC * 1000000;
// 2.2 get the minimum line time
minLineTime = maxActiveTime / (NvU64)height;
// 2.3 get the minimum number of VBlank lines. The multiplicand 1000000 is for accuracy, because we multiply it at 2.1
minVBlank = (NvU32)(NV_UNSIGNED_DIV_CEIL((NvU64)NVT_OVT_MIN_V_BLANK_MICROSEC * (NvU64)1000000, (NvU64)minLineTime));
// 2.4 get the minimum total number of lines
minVTotal = height + minVBlank;
if (minVTotal % vTotalGranularity !=0)
minVTotal += (vTotalGranularity - (minVTotal % vTotalGranularity));
// 3. Find the audio packet rate and use it to determine the required audio packets per line:
// 3.1 determine a minimum line rate
minLineRate = maxVRate * minVTotal; // Hz
// 3.2 The maximum number of audio packets
maxAudioPacketsPerLine = NV_UNSIGNED_DIV_CEIL(NVT_OVT_AUDIO_PACKET_RATE, minLineRate);
// 4. Find initial minimum horizontal total size, based on audio requirements (1 pixel = 1 character):
minHBlank = NVT_OVT_LINE_OVERHEAD + NVT_OVT_AUDIO_PACKET_SIZE * maxAudioPacketsPerLine;
// 4.1 determine a minimum Horizontal Total pixel (MinHtotal)
minHTotal = width + NV_MAX(NVT_OVT_MIN_H_BLANK_444, minHBlank);
// 5. Find hTotal and vTotal so that the pixelClockRate is divisible by the pixelClockGranularity, and
// hTotal is divisible by an appropriate processing chunk size:
minPixelClockRate = (NvU64)maxVRate * (NvU64)minHTotal * (NvU64)minVTotal; // Hz
// 5.1 determinate new granularity and minHtotal based on the new granularity
hTotalGranularityChunk = nvNextPow2_U32((NvU32)NV_UNSIGNED_DIV_CEIL(minPixelClockRate, (NvU64)NVT_OVT_MAX_CHUNK_RATE));
// 5.2 If this value is greater than the 8, it becomes the new horizontal granularity
hTotalGranularity = NV_MAX((NvU64)NVT_OVT_MIN_H_TOTAL_GRANULARITY, hTotalGranularityChunk);
if (minHTotal % hTotalGranularity != 0)
{
minHTotal += (hTotalGranularity - (minHTotal % hTotalGranularity));
}
// 5.3 optimized by iterating on resolution totals without multiplying by the max refresh rate.
resolutionGranularity = NVT_OVT_PIXEL_CLOCK_GRANULARITY / computeGCD(NVT_OVT_PIXEL_CLOCK_GRANULARITY, maxVRate);
// ** OVT Timing Search **
// 5.4 it will repeat until the found pixel clock is greater than the divisible pixel clock of the search at hte previous vTotal value,
// the hTotal and vTotal values of that preceding search are chosen for the video timing
for(;;)
{
minResolution = 0;
V = minVTotal;
for(;;)
{
H = minHTotal;
R = (NvU64)H * (NvU64)V;
if (minResolution && R > minResolution)
break;
while (R % resolutionGranularity || maxVRate * R / nvFloorPow2_U32(H) > NVT_OVT_MAX_CHUNK_RATE)
{
H += hTotalGranularity;
R = (NvU64)H * (NvU64)V;
}
if (minResolution == 0 || R < minResolution)
{
hTotal = H;
vTotal = V;
minResolution = R;
}
V += vTotalGranularity;
}
pixelClockRate = maxVRate * minResolution;
// 6. Check if timing requires adjustments for 4:2:0:
// 6.a Re-calculate minHTotal, in pixels, adjusted for 4:2:0 requirements. (2 pixels = 1 character):
minHTotal = width + NV_MAX(NVT_OVT_MIN_H_BLANK_420, NVT_OVT_PIXEL_FACTOR_420 * minHBlank);
// 6.b If the resulting PixelClockRate allows for 4:2:0, assure that the new Hblank requirement is met, or repeat calculation with new MinHtotal:
if (pixelClockRate >= NVT_OVT_MIN_CLOCK_RATE_420 && hTotal < minHTotal)
{
continue;
}
break;
}
// ** post-processing **
// 7. Adjust Vtotal, in lines, to achieve (integer) target Vrate:
vTotal = vTotal * maxVRate / refreshRate;
// 8. Find Vsync leading edge:
vBlank = vTotal - height;
vSyncPosition = (NvU32)NV_UNSIGNED_DIV_CEIL(((NvU64)NVT_OVT_MIN_V_SYNC_LEADING_EDGE * (NvU64)pixelClockRate), ((NvU64)1000000 * (NvU64)hTotal));
// 10. fill in the essential timing info for output
pT->HVisible = (NvU16)width;
pT->HTotal = (NvU16)hTotal;
pT->HFrontPorch = (NvU16)(hTotal - width - NVT_OVT_H_SYNC_PIXELS - NVT_OVT_H_BACK_WIDTH);
pT->HSyncWidth = (NvU16)NVT_OVT_H_SYNC_PIXELS;
pT->VVisible = (NvU16)height;
pT->VTotal = (NvU16)vTotal;
pT->VSyncWidth = (NvU16)NVT_OVT_V_SYNC_WIDTH;
pT->VFrontPorch = (NvU16)(vBlank - vSyncPosition);
pT->pclk = (NvU32)(pixelClockRate /*Hz*/ / 1000 + 5) / 10; //convert to 10Khz
pT->HSyncPol = NVT_H_SYNC_POSITIVE;
pT->VSyncPol = NVT_V_SYNC_POSITIVE;
pT->HBorder = pT->VBorder = 0; // not supported
pT->interlaced = 0; // not supported
// fill in the extra timing info
pT->etc.flag = 0;
pT->etc.rr = (NvU16)refreshRate;
pT->etc.rrx1k = (NvU32)axb_div_c_64((NvU64)pT->pclk, (NvU64)10000 * (NvU64)1000, (NvU64)pT->HTotal*(NvU64)pT->VTotal);
pT->etc.aspect = calculate_aspect_ratio(pT);
pT->etc.rep = 0x1;
NVT_SNPRINTF((char *)pT->etc.name, 40, "CTA861-OVT:%dx%dx%dHz", width, height, refreshRate);
pT->etc.name[39] = '\0';
return NVT_STATUS_SUCCESS;
}
CODE_SEGMENT(PAGE_DD_CODE)
NvBool NvTiming_IsTimingOVT(const NVT_TIMING *pTiming)
{
// Check from the Timing Type
if (pTiming->etc.flag & NVT_FLAG_CTA_OVT_TIMING)
{
return NV_TRUE;
}
return NV_FALSE;
}
POP_SEGMENTS

219
src/common/modeset/timing/nvtiming.h
View File

@@ -114,6 +114,13 @@ typedef union tagNVT_COLORDEPTH
(_colorFormat).bpc.bpc8 ? NVT_EDID_VIDEOSIGNAL_BPC_8 : \
(_colorFormat).bpc.bpc6 ? NVT_EDID_VIDEOSIGNAL_BPC_6 : NVT_EDID_VIDEOSIGNAL_BPC_NOT_DEFINED
#define NVT_COLORDEPTH_LOWEREST_BPC(_colorFormat) \
(_colorFormat).bpc.bpc6 ? NVT_EDID_VIDEOSIGNAL_BPC_6 : \
(_colorFormat).bpc.bpc8 ? NVT_EDID_VIDEOSIGNAL_BPC_8 : \
(_colorFormat).bpc.bpc10 ? NVT_EDID_VIDEOSIGNAL_BPC_10 : \
(_colorFormat).bpc.bpc12 ? NVT_EDID_VIDEOSIGNAL_BPC_12 : \
(_colorFormat).bpc.bpc16 ? NVT_EDID_VIDEOSIGNAL_BPC_16 : NVT_EDID_VIDEOSIGNAL_BPC_NOT_DEFINED
typedef struct tagNVT_TIMINGEXT
{
NvU32 flag; // reserve for NV h/w based enhancement like double-scan.
@@ -430,6 +437,7 @@ typedef enum NVT_TV_FORMAT
#define NVT_STATUS_CTA861_DID_T7N(n) NVT_DEF_TIMING_STATUS(NVT_TYPE_CTA861_DID_T7, n)
#define NVT_STATUS_CTA861_DID_T8N(n) NVT_DEF_TIMING_STATUS(NVT_TYPE_CTA861_DID_T8, n)
#define NVT_STATUS_CTA861_DID_T10N(n) NVT_DEF_TIMING_STATUS(NVT_TYPE_CTA861_DID_T10, n)
#define NVT_STATUS_CTA861_OVT_Tn(n) NVT_DEF_TIMING_STATUS(NVT_TYPE_CTA861_OVT, n)
//********************************
// CEA/EIA 861 related EDID info
@@ -469,7 +477,7 @@ typedef enum NVT_TV_FORMAT
#define NVT_CEA861_TAG_VENDOR 3 // Vendor Specific Data Block
#define NVT_CEA861_TAG_SPEAKER_ALLOC 4 // Speaker Allocation Data Block
#define NVT_CEA861_TAG_VESA_DTC 5 // VESA DTC data block
#define NVT_CEA861_TAG_RSVD1 6 // reserved block
#define NVT_CTA861_TAG_VIDEO_FORMAT 6 // Video Format Data Block in CTA861.6
#define NVT_CEA861_TAG_EXTENDED_FLAG 7 // use Extended Tag
//
// the extended tag codes when NVT_CEA861_TAG_EXTENDED_FLAG
@@ -563,7 +571,7 @@ typedef enum NVT_TV_FORMAT
// information but where the vertical frequency is adjusted by a factor of
// 1000/1001 (i.e., 24/1.001, 30/1.001, 60/1.001, 120/1.001 or 240/1.001).
// Excluding ceaIndex 1 640x480 which is a PC Mode.
#define NVT_CEA861_TIMING_FRR(_VID_, _RR_) ((_VID_) > 1 && ((_RR_) % 6) == 0)
#define NVT_CTA861_TIMING_FRR(_VID_, _RR_) ((_VID_) > 1 && ((_RR_) % 6) == 0)
#define NVT_CEA861_640X480P_59940HZ_4X3 1 // Video Identification Code: format 1
#define NVT_CEA861_720X480P_59940HZ_4X3 2 // Video Identification Code: format 2
#define NVT_CEA861_720X480P_59940HZ_16X9 3 // Video Identification Code: format 3
@@ -734,6 +742,66 @@ typedef enum NVT_TV_FORMAT
// NVT_CEA861_1280X720P_100000HZ_16X9,
// NVT_CEA861_1280X720P_119880HZ_16X9
// According to CEA-861-I Spec.
// Table 11 - Resoution Identification (RID)
#define NVT_CTA861_OVT_TIMING_FRR(_FLAG_, _RR_) (((_FLAG_) & (NVT_FLAG_CTA_OVT_TIMING)) != 0 && ((_RR_) % 6) == 0 && (_RR_) != 300)
#define NVT_CTA861_RID_NONE NVT_INFOFRAME_CTRL_DONTCARE
#define NVT_CTA861_RID_1280x720p_16x9 1
#define NVT_CTA861_RID_1280x720p_64x27 2
#define NVT_CTA861_RID_1680x720p_64x27 3
#define NVT_CTA861_RID_1920x1080p_16x9 4
#define NVT_CTA861_RID_1920x1080p_64x27 5
#define NVT_CTA861_RID_2560x1080p_64x27 6
#define NVT_CTA861_RID_3840x1080p_32x9 7
#define NVT_CTA861_RID_2560x1440p_16x9 8
#define NVT_CTA861_RID_3440x1440p_64x27 9
#define NVT_CTA861_RID_5120x1440p_32x9 10
#define NVT_CTA861_RID_3840x2160p_16x9 11
#define NVT_CTA861_RID_3840x2160p_64x27 12
#define NVT_CTA861_RID_5120x2160p_64x27 13
#define NVT_CTA861_RID_7680x2160p_32x9 14
#define NVT_CTA861_RID_5120x2880p_16x9 15
#define NVT_CTA861_RID_5120x2880p_64x27 16
#define NVT_CTA861_RID_6880x2880p_64x27 17
#define NVT_CTA861_RID_10240x2880p_32x9 18
#define NVT_CTA861_RID_7680x4320p_16x9 19
#define NVT_CTA861_RID_7680x4320p_64x27 20
#define NVT_CTA861_RID_10240x4320p_64x27 21
#define NVT_CTA861_RID_15360x4320p_32x9 22
#define NVT_CTA861_RID_11520x6480p_16x9 23
#define NVT_CTA861_RID_11520x6480p_64x27 24
#define NVT_CTA861_RID_15360x6480p_64x27 25
#define NVT_CTA861_RID_15360x8640p_16x9 26
#define NVT_CTA861_RID_15360x8640p_64x27 27
#define NVT_CTA861_RID_20480x8640p_64x27 28
// Table 12 - AVI InfoFrame Video Format Frame Rate
#define NVT_CTA861_FR_NO_DATA NVT_INFOFRAME_CTRL_DONTCARE
#define NVT_CTA861_FR_2398 1
#define NVT_CTA861_FR_2400 2
#define NVT_CTA861_FR_2500 3
#define NVT_CTA861_FR_2997 4
#define NVT_CTA861_FR_3000 5
#define NVT_CTA861_FR_4795 6
#define NVT_CTA861_FR_4800 7
#define NVT_CTA861_FR_5000 8
#define NVT_CTA861_FR_5994 9
#define NVT_CTA861_FR_6000 10
#define NVT_CTA861_FR_10000 11
#define NVT_CTA861_FR_11988 12
#define NVT_CTA861_FR_12000 13
#define NVT_CTA861_FR_14386 14
#define NVT_CTA861_FR_14400 15
#define NVT_CTA861_FR_20000 16
#define NVT_CTA861_FR_23976 17
#define NVT_CTA861_FR_24000 18
#define NVT_CTA861_FR_30000 19
#define NVT_CTA861_FR_35964 20
#define NVT_CTA861_FR_36000 21
#define NVT_CTA861_FR_40000 22
#define NVT_CTA861_FR_47952 23
#define NVT_CTA861_FR_48000 24
//*************************
// short audio descriptor
//*************************
@@ -845,7 +913,68 @@ typedef struct VSVDB_DATA
NvU8 vendor_data[NVT_CEA861_VSVDB_PAYLOAD_MAX_LENGTH];
} VSVDB_DATA;
//*******************************
// Video Format Data Block (VFDB)
//*******************************
#define NVT_CTA861_VF_MAX_BLOCKS 4
#define NVT_CTA861_VF_MAX_DESCRIPTORS 30
#define NVT_CTA861_VF_RID_MASK 0x3F
typedef struct tagNVT_RID_CODES
{
NvU16 HVisible; // horizontal visible
NvU8 HSyncPol; // horizontal sync polarity: 1-negative, 0-positive
NvU16 VVisible; // vertical visible
NvU8 VSyncPol; // vertical sync polarity: 1-negative, 0-positive
NvU16 interlaced; // 1-interlaced, 0-progressive
NvU32 aspect; // the display aspect ratio Hi(aspect):horizontal-aspect, Low(aspect):vertical-aspect
NvU8 rid; // Resolution Identification (RID)
} NVT_RID_CODES;
#pragma pack(1)
typedef struct tagVFD_ONE_BYTE
{
NvU8 rid : 6;
NvU8 fr24 : 1;
NvU8 bfr50 : 1;
} VFD_ONE_BYTE;
typedef struct tagVFD_TWO_BYTE
{
VFD_ONE_BYTE in_onebyte;
NvU8 frRate : 6;
NvU8 fr144 : 1;
NvU8 bfr60 : 1;
} VFD_TWO_BYTE;
typedef struct tagVFD_THREE_BYTE
{
VFD_TWO_BYTE in_twobyte;
NvU8 fr48 : 1;
NvU8 f31_37 : 7;
} VFD_THREE_BYTE;
typedef struct tagVFD_FOUR_BYTE
{
VFD_THREE_BYTE in_threebyte;
NvU8 f40_47;
} VFD_FOUR_BYTE;
typedef struct tagVFDB_DATA
{
struct {
NvU8 vfd_len : 2;
NvU8 f22_25 : 4;
NvU8 ntsc : 1;
NvU8 y420 : 1;
} info;
NvU8 total_vfd;
NvU8 video_format_desc[NVT_CTA861_VF_MAX_DESCRIPTORS];
} VFDB_DATA;
typedef struct tagNVT_DV_STATIC_METADATA_TYPE0
{
// first byte
@@ -1290,6 +1419,10 @@ typedef struct tagEDID_CEA861_INFO
// vendor specific video data
NvU8 total_vsvdb;
VSVDB_DATA vsvdb[NVT_CEA861_VSVDB_MAX_BLOCKS];
// video format data
NvU8 total_vfdb;
VFDB_DATA vfdb[NVT_CTA861_VF_MAX_BLOCKS];
// indicates which of the extended data blocks below contain valid data excluding extended blocks with total count
NVT_VALID_EXTENDED_BLOCKS valid;
@@ -2858,6 +2991,7 @@ typedef enum
NVT_PROTOCOL_UNKNOWN = 0,
NVT_PROTOCOL_DP = 1,
NVT_PROTOCOL_HDMI = 2,
NVT_PROTOCOL_DVI = 3,
} NVT_PROTOCOL;
// the display interface/connector claimed by the EDID
@@ -2870,14 +3004,14 @@ typedef enum
// the EDID extension TAG
#define NVT_EDID_EXTENSION_CTA 0x02 // CTA 861 series extensions
#define NVT_EDID_EXTENSION_VTB 0x10 // video timing block extension
#define NVT_EDID_EXTENSION_DI 0x40 // display information extension
#define NVT_EDID_EXTENSION_LS 0x50 // localized string extension
#define NVT_EDID_EXTENSION_DPVL 0x60 // digital packet video link extension
#define NVT_EDID_EXTENSION_DISPLAYID 0x70 // display id
#define NVT_EDID_EXTENSION_BM 0xF0 // extension block map
#define NVT_EDID_EXTENSION_OEM 0xFF // extension defined by the display manufacturer
#define NVT_EDID_EXTENSION_CTA 0x02 // CTA 861 series extensions
#define NVT_EDID_EXTENSION_VTB 0x10 // video timing block extension
#define NVT_EDID_EXTENSION_DI 0x40 // display information extension
#define NVT_EDID_EXTENSION_LS 0x50 // localized string extension
#define NVT_EDID_EXTENSION_DPVL 0x60 // digital packet video link extension
#define NVT_EDID_EXTENSION_DISPLAYID 0x70 // display id
#define NVT_EDID_EXTENSION_BM 0xF0 // extension block map
#define NVT_EDID_EXTENSION_OEM 0xFF // extension defined by the display manufacturer
//************************************
// Audio and Video Infoframe Control
@@ -2906,6 +3040,9 @@ typedef struct tagNVT_VIDEO_INFOFRAME_CTRL
NvU16 bottom_bar;
NvU16 left_bar;
NvU16 right_bar;
NvU8 addition_colorimetry_ext;
NvU8 frame_rate;
NvU8 rid;
}NVT_VIDEO_INFOFRAME_CTRL;
//
@@ -2922,7 +3059,7 @@ typedef struct tagNVT_AUDIO_INFOFRAME_CTRL
typedef struct tagNVT_VENDOR_SPECIFIC_INFOFRAME_CTRL
{
NvU32 Enable;
NvU8 Enable;
NvU8 HDMIRevision;
NvU8 HDMIFormat;
NvU8 HDMI_VIC;
@@ -2950,12 +3087,14 @@ typedef struct tagNVT_EXTENDED_METADATA_PACKET_INFOFRAME_CTRL
NvU32 EnableQMS;
NvU32 NextTFR;
NvU32 Sync;
NvU32 MConst;
} NVT_EXTENDED_METADATA_PACKET_INFOFRAME_CTRL;
typedef struct tagNVT_ADAPTIVE_SYNC_SDP_CTRL
{
NvU32 minVTotal;
NvU32 targetRefreshRate;
NvU32 srCoastingVTotal;
NvBool bFixedVTotal;
NvBool bRefreshRateDivider;
}NVT_ADAPTIVE_SYNC_SDP_CTRL;
@@ -3032,6 +3171,10 @@ typedef struct tagNVT_VIDEO_INFOFRAME
NvU8 left_bar_high;
NvU8 right_bar_low;
NvU8 right_bar_high;
// byte 14~15
NvU8 byte14;
NvU8 byte15;
}NVT_VIDEO_INFOFRAME;
//
#define NVT_VIDEO_INFOFRAME_VERSION_1 1
@@ -3186,8 +3329,17 @@ typedef struct tagNVT_VIDEO_INFOFRAME
#define NVT_VIDEO_INFOFRAME_BYTE5_RESERVED_V1_MASK 0xFF
#define NVT_VIDEO_INFOFRAME_BYTE5_RESERVED_V1_SHIFT 0
//
#define NVT_VIDEO_INFOFRAME_BYTE14_RESERVED_MASK 0x0F
#define NVT_VIDEO_INFOFRAME_BYTE14_RESERVED_SHIFT 0
#define NVT_VIDEO_INFOFRAME_BYTE14_FR0_FR3_MASK 0x0F
#define NVT_VIDEO_INFOFRAME_BYTE14_FR0_FR3_SHIFT 0
#define NVT_VIDEO_INFOFRAME_BYTE14_FR0_FR3_NODATA 0
#define NVT_VIDEO_INFOFRAME_BYTE14_FR4_ONE_BIT_MASK 0x10
#define NVT_VIDEO_INFOFRAME_BYTE15_FR4_MASK 0x40
#define NVT_VIDEO_INFOFRAME_BYTE15_FR4_NODATA 0
#define NVT_VIDEO_INFOFRAME_BYTE15_FR4_SHIFT 2
//
#define NVT_VIDEO_INFOFRAME_BYTE15_RID_MASK 0x3F
#define NVT_VIDEO_INFOFRAME_BYTE15_RID_SHIFT 0
#define NVT_VIDEO_INFOFRAME_BYTE15_RID_NODATA 0
//
#define NVT_VIDEO_INFOFRAME_BYTE14_ACE0_3_MASK 0xF0
#define NVT_VIDEO_INFOFRAME_BYTE14_ACE0_3_SHIFT 4
@@ -3252,7 +3404,21 @@ typedef struct
NvU16 topBar;
NvU16 bottomBar;
NvU16 leftBar;
NvU16 rightBar;
NvU16 rightBar;
// byte 14~15
struct
{
NvU8 fr_low : 4;
NvU8 ace : 4;
} byte14;
struct
{
NvU8 rid : 6;
NvU8 fr_hi : 1;
NvU8 rsvd_bits_byte15 : 1;
}byte15;
} NVT_VIDEO_INFOFRAME_OVERRIDE;
#pragma pack()
@@ -3302,6 +3468,11 @@ typedef struct
#define NVT_VIDEO_INFOFRAME_OVERRIDE_BYTE5_PR_MASK 0xF // pixel repetitions
#define NVT_VIDEO_INFOFRAME_OVERRIDE_BYTE5_CN1CN0_MASK 0x3
#define NVT_VIDEO_INFOFRAME_OVERRIDE_BYTE5_YQ1YQ0_MASK 0x3 // YCC quantization
//
#define NVT_VIDEO_INFOFRAME_OVERRIDE_BYTE14_FR0FR3_MASK 0xF // Frame rate 0-3 bits in Byte14
#define NVT_VIDEO_INFOFRAME_OVERRIDE_BYTE14_ACE0ACE3_MASK 0xF // Additional Colorimetry Extension
#define NVT_VIDEO_INFOFRAME_OVERRIDE_BYTE15_RID0RID5_MASK 0x3F // Resolution Identification
#define NVT_VIDEO_INFOFRAME_OVERRIDE_BYTE15_FR4_MASK 0x1 // Frame rate 4th bit in Byte 15
// audio infoframe structure
typedef struct tagNVT_AUDIO_INFOFRAME
@@ -3778,9 +3949,9 @@ typedef struct tagNVT_EXTENDED_METADATA_PACKET_INFOFRAME
#define NVT_HDMI_EMP_BYTE8_MD0_VRR_EN_SHIFT 0
#define NVT_HDMI_EMP_BYTE8_MD0_VRR_EN_DISABLE 0
#define NVT_HDMI_EMP_BYTE8_MD0_VRR_EN_ENABLE 1
#define NVT_HDMI_EMP_BYTE8_MD0_M_CONST_MASK 0x01
#define NVT_HDMI_EMP_BYTE8_MD0_M_CONST_MASK 0x02
#define NVT_HDMI_EMP_BYTE8_MD0_M_CONST_SHIFT 1
#define NVT_HDMI_EMP_BYTE8_MD0_QMS_EN_MASK 0x01
#define NVT_HDMI_EMP_BYTE8_MD0_QMS_EN_MASK 0x04
#define NVT_HDMI_EMP_BYTE8_MD0_QMS_EN_SHIFT 2
#define NVT_HDMI_EMP_BYTE8_MD0_QMS_EN_DISABLE 0
#define NVT_HDMI_EMP_BYTE8_MD0_QMS_EN_ENABLE 1
@@ -3793,7 +3964,7 @@ typedef struct tagNVT_EXTENDED_METADATA_PACKET_INFOFRAME
#define NVT_HDMI_EMP_BYTE8_MD2_RB_DISABLE 0
#define NVT_HDMI_EMP_BYTE8_MD2_RB_ENABLE 1
#define NVT_HDMI_EMP_BYTE8_MD2_NEXT_TFR_MASK 0x1f
#define NVT_HDMI_EMP_BYTE8_MD2_NEXT_TFR_MASK 0xf8
#define NVT_HDMI_EMP_BYTE8_MD2_NEXT_TFR_SHIFT 3
#define NVT_HDMI_EMP_BYTE8_MD2_BASE_RR_MSB_MASK 0x03
@@ -4622,7 +4793,7 @@ typedef struct tagNVT_DPCD
#define NVT_DPCD_LANE_COUNT_8 8
// note: the values of NVT_COLOR_FORMAT_* are fixed in order to match the equivalent NV classes
typedef enum
typedef enum _NVT_COLOR_FORMAT
{
NVT_COLOR_FORMAT_RGB = 0,
NVT_COLOR_FORMAT_YCbCr422 = 1,
@@ -5617,6 +5788,8 @@ typedef enum
#define NVT_FLAG_DISPLAYID_2_0_TIMING 0x00800000 // this one for the CTA861 embedded in DID20
#define NVT_FLAG_DISPLAYID_T7_T8_EXPLICT_YUV420 0x01000000 // DID2 E7 spec. supported yuv420 indicated
#define NVT_FLAG_CTA_NATIVE_TIMING 0x02000000 // NVRDB defined
#define NVT_FLAG_CTA_OVT_TIMING 0x04000000 // CTA861 CTA OVT Timing
#define NVT_FLAG_CTA_OVT_FRR_TIMING 0x08000000 // CTA861 CTA OVT Timing supported ntsc
#define NVT_FLAG_INTERLACED_MASK (NVT_FLAG_INTERLACED_TIMING | NVT_FLAG_INTERLACED_TIMING2)
@@ -5655,6 +5828,10 @@ NVT_STATUS NvTiming_CalcCVT_RB2(NvU32 width, NvU32 height, NvU32 rr, NvBool is10
NVT_STATUS NvTiming_CalcCVT_RB3(NvU32 width, NvU32 height, NvU32 rr, NvU32 deltaHBlank, NvU32 vBlankMicroSec, NvBool isEarlyVSync, NVT_TIMING *pT);
NvBool NvTiming_IsTimingCVTRB(const NVT_TIMING *pTiming);
// OVT timing calculation
NVT_STATUS NvTiming_CalcOVT(NvU32 width, NvU32 height, NvU32 rr, NVT_TIMING *pT);
NvBool NvTiming_IsTimingOVT(const NVT_TIMING *pTiming);
// CEA/EIA/Psf timing
NVT_STATUS NvTiming_CalcCEA861bTiming(NvU32 width, NvU32 height, NvU32 rr, NvU32 flag, NvU32 pixelRepeatCount, NVT_TIMING *pT);
NVT_STATUS NvTiming_EnumCEA861bTiming(NvU32 ceaFormat, NVT_TIMING *pT);
@@ -5668,6 +5845,7 @@ NVT_STATUS NvTiming_EnumHdmiVsdbExtendedTiming(NvU32 hdmi_vic, NVT_TIMING *pT);
NVT_STATUS NvTiming_GetTvTiming(NvU32 width, NvU32 height, NvU32 rr, NvU32 flag, NvU32 tvFormat, NVT_TIMING *pT);
// Get EDID timing
NVT_STATUS NvTiming_GetEdidTimingExWithPclk(NvU32 width, NvU32 height, NvU32 rr, NvU32 flag, NVT_EDID_INFO *pEdidInfo, NVT_TIMING *pT, NvU32 rrx1k, NvU32 pclk);
NVT_STATUS NvTiming_GetEdidTimingEx(NvU32 width, NvU32 height, NvU32 rr, NvU32 flag, NVT_EDID_INFO *pEdidInfo, NVT_TIMING *pT, NvU32 rrx1k);
NVT_STATUS NvTiming_GetEdidTiming(NvU32 width, NvU32 height, NvU32 rr, NvU32 flag, NVT_EDID_INFO *pEdidInfo, NVT_TIMING *pT);
@@ -5679,7 +5857,6 @@ NVT_STATUS NvTiming_GetHDMIStereoMandatoryFormatDetail(const NvU8 vic, NvU16 *pS
// EDID based AspectRatio Timing
NVT_STATUS NvTiming_GetEDIDBasedASPRTiming(NvU16 width, NvU16 height, NvU16 rr, NVT_EDID_INFO *pEI, NVT_TIMING *ft);
// EDID or DISPLAYID2 version
NvU32 NvTiming_GetVESADisplayDescriptorVersion(NvU8 *rawData, NvU32 *pVer);
@@ -5738,11 +5915,15 @@ NVT_STATUS NvTiming_GetDTD1Timing (NVT_EDID_INFO * pEdidInfo, NVT_TIMING * pT);
#define NVT_IS_CTA861_DID_T8_1(d) ((NVT_IS_CTA861_DID_T8((d))) && (NVT_GET_TIMING_STATUS_SEQ((d)) == 1))
#define NVT_IS_CTA861_DID_T10n(d, n) ((NVT_IS_CTA861_DID_T10((d))) && (NVT_GET_TIMING_STATUS_SEQ((d)) == n))
#define NVT_IS_CTA861_OVT_Tn(flag, status, n) ((0 != (NVT_FLAG_CTA_OVT_TIMING & (flag))) && (NVT_GET_TIMING_STATUS_SEQ((status)) == n))
#define NVT_DID20_TIMING_IS_CTA861(flag, status) ((NVT_IS_CTA861((status))) && (0 != (NVT_FLAG_DISPLAYID_2_0_TIMING & (flag))))
#define NVT_PREFERRED_TIMING_IS_DTD1(flag, status) ((NVT_IS_DTD1((status))) && (0 != (NVT_FLAG_DTD1_PREFERRED_TIMING & (flag))))
#define NVT_PREFERRED_TIMING_IS_DISPLAYID(flag) (0 != (NVT_FLAG_DISPLAYID_DTD_PREFERRED_TIMING & flag))
#define NVT_PREFERRED_TIMING_IS_CTA(flag) (0 != (NVT_FLAG_CTA_PREFERRED_TIMING & flag))
#define NVT_NATIVE_TIMING_IS_CTA(flag) (0 != (NVT_FLAG_CTA_NATIVE_TIMING & flag))
#define NVT_TIMING_IS_OVT(flag) (0 != (NVT_FLAG_CTA_OVT_TIMING & flag))
#define NVT_FRR_TIMING_IS_OVT(flag) (0 != (NVT_FLAG_CTA_OVT_FRR_TIMING & flag))
#ifdef __cplusplus
}

3
src/common/modeset/timing/nvtiming_pvt.h
View File

@@ -72,6 +72,7 @@ NVT_STATUS parseCta861DataBlockInfo(NvU8 *pEdid, NvU32 size, NVT_EDID_CEA861_INF
void parse861ExtDetailedTiming(NvU8 *pEdidExt, NvU8 basicCaps, NVT_EDID_INFO *pInfo);
void parse861bShortTiming(NVT_EDID_CEA861_INFO *pExt861, void *pRawInfo, NVT_CTA861_ORIGIN flag);
void parse861bShortYuv420Timing(NVT_EDID_CEA861_INFO *pExt861, void *pRawInfo, NVT_CTA861_ORIGIN flag);
void parseCta861VideoFormatDataBlock(NVT_EDID_CEA861_INFO *pExt861, void *pRawInfo);
void parseCta861NativeOrPreferredTiming(NVT_EDID_CEA861_INFO *pExt861, void *pRawInfo, NVT_CTA861_ORIGIN flag);
void parseCta861VsdbBlocks(NVT_EDID_CEA861_INFO *pExt861, void *pRawInfo, NVT_CTA861_ORIGIN flag);
void parseCta861VsvdbBlocks(NVT_EDID_CEA861_INFO *pExt861, void *pRawInfo, NVT_CTA861_ORIGIN flag);
@@ -94,7 +95,7 @@ NvBool isMatchedStandardTiming(NVT_EDID_INFO *pInfo, NVT_TIMING *pT);
NvBool isMatchedEstablishedTiming(NVT_EDID_INFO *pInfo, NVT_TIMING *pT);
NvU32 isHdmi3DStereoType(NvU8 StereoStructureType);
NvU32 getCEA861TimingAspectRatio(NvU32 vic);
NvU8 getHighestPrioritySVRIdx(NvU8 svr);
NvU8 getHighestPrioritySVRIdx(const NVT_EDID_CEA861_INFO *pExt861);
void SetActiveSpaceForHDMI3DStereo(const NVT_TIMING *pTiming, NVT_EXT_TIMING *pExtTiming);
void AddModeToSupportMap(HDMI3DSUPPORTMAP * pMap, NvU8 vic, NvU8 structure, NvU8 Detail);
void getMonitorDescriptorString(NvU8 *pEdid, NvU8 tag, char *str, int onceOnly);

98
src/common/nvlink/inband/interface/nvlink_inband_msg.h
View File

@@ -37,7 +37,7 @@
* - Avoid conditional fields in the structs.
* - Avoid nested and complex structs. Keep them simple and flat for ease of encoding and decoding.
* - Avoid embedded pointers. Flexible arrays at the end of the struct are allowed.
* - Always use the packed struct to typecast inband messages. More details:
* - Always use the packed struct to typecast inband messages. More details:
* - Always have reserved flags or fields to CYA given the stable ABI conditions.
*/
@@ -50,17 +50,22 @@
#include "nvstatus.h"
#include "nvstatuscodes.h"
#define NVLINK_INBAND_MAX_MSG_SIZE 4096
#define NVLINK_INBAND_MAX_MSG_SIZE 5120
#define NVLINK_INBAND_MSG_MAGIC_ID_FM 0xadbc
/* Nvlink Inband messages types */
#define NVLINK_INBAND_MSG_TYPE_GPU_PROBE_REQ 0
#define NVLINK_INBAND_MSG_TYPE_GPU_PROBE_RSP 1
#define NVLINK_INBAND_MSG_TYPE_MC_TEAM_SETUP_REQ 2
#define NVLINK_INBAND_MSG_TYPE_MC_TEAM_SETUP_RSP 3
#define NVLINK_INBAND_MSG_TYPE_MC_TEAM_RELEASE_REQ 4
#define NVLINK_INBAND_MSG_TYPE_MC_TEAM_SETUP_REQ_V2 5
#define NVLINK_INBAND_MSG_TYPE_MAX 6
#define NVLINK_INBAND_MSG_TYPE_GPU_PROBE_REQ 0
#define NVLINK_INBAND_MSG_TYPE_GPU_PROBE_RSP 1
#define NVLINK_INBAND_MSG_TYPE_MC_TEAM_SETUP_REQ 2
#define NVLINK_INBAND_MSG_TYPE_MC_TEAM_SETUP_RSP 3
#define NVLINK_INBAND_MSG_TYPE_MC_TEAM_RELEASE_REQ 4
#define NVLINK_INBAND_MSG_TYPE_MC_TEAM_SETUP_REQ_V2 5
#define NVLINK_INBAND_MSG_TYPE_GPU_PROBE_UPDATE_REQ 6
#define NVLINK_INBAND_MSG_TYPE_GPU_PROBE_REPLAY_REQ 7
#define NVLINK_INBAND_MSG_TYPE_GPU_PROBE_REPLAY_RSP NVLINK_INBAND_MSG_TYPE_GPU_PROBE_RSP
#define NVLINK_INBAND_MSG_TYPE_MC_TEAM_SETUP_REPLAY_REQ 8
#define NVLINK_INBAND_MSG_TYPE_MC_TEAM_SETUP_REPLAY_RSP NVLINK_INBAND_MSG_TYPE_MC_TEAM_SETUP_RSP
#define NVLINK_INBAND_MSG_TYPE_MAX 9
/* Nvlink Inband message packet header */
typedef struct
@@ -74,6 +79,7 @@ typedef struct
} nvlink_inband_msg_header_t;
#define NVLINK_INBAND_GPU_PROBE_CAPS_SRIOV_ENABLED NVBIT(0)
#define NVLINK_INBAND_GPU_PROBE_CAPS_PROBE_UPDATE NVBIT(1)
/* Add more caps as need in the future */
@@ -109,6 +115,11 @@ typedef struct
#define NVLINK_INBAND_FM_CAPS_BW_MODE_3QUARTER NVBIT64(4)
#define NVLINK_INBAND_FM_CAPS_MC_TEAM_SETUP_V2 NVBIT64(5)
#define NVLINK_INBAND_FABRIC_HEALTH_MASK_DEGRADED_BW 1:0
#define NVLINK_INBAND_FABRIC_HEALTH_MASK_DEGRADED_BW_NOT_SUPPORTED 0
#define NVLINK_INBAND_FABRIC_HEALTH_MASK_DEGRADED_BW_TRUE 1
#define NVLINK_INBAND_FABRIC_HEALTH_MASK_DEGRADED_BW_FALSE 2
typedef struct
{
NvU64 gpuHandle; /* Unique handle assigned by initialization entity for this GPU */
@@ -122,7 +133,8 @@ typedef struct
NvU64 flaAddressRange; /* GPU FLA address range */
NvU32 linkMaskToBeReduced; /* bit mask of unused NVLink ports for P2P */
NvU32 cliqueId; /* Fabric Clique Id */
NvU8 reserved[24]; /* For future use. Must be initialized to zero */
NvU32 fabricHealthMask; /* Mask containing bits indicating various fabric health parameters */
NvU8 reserved[20]; /* For future use. Must be initialized to zero */
} nvlink_inband_gpu_probe_rsp_t;
typedef struct
@@ -131,6 +143,20 @@ typedef struct
nvlink_inband_gpu_probe_rsp_t probeRsp;
} nvlink_inband_gpu_probe_rsp_msg_t;
typedef struct
{
NvU64 gpuHandle; /* Unique handle assigned by initialization entity for this GPU */
NvU32 cliqueId; /* Fabric Clique Id*/
NvU32 fabricHealthMask; /* Mask containing bits indicating various fabric health parameters */
NvU8 reserved[32]; /* For future use. Must be initialized to zero */
} nvlink_inband_gpu_probe_update_req_t;
typedef struct
{
nvlink_inband_msg_header_t msgHdr;
nvlink_inband_gpu_probe_update_req_t probeUpdate;
} nvlink_inband_gpu_probe_update_req_msg_t;
typedef struct
{
NvU64 mcAllocSize; /* Multicast allocation size requested */
@@ -203,6 +229,58 @@ typedef struct
nvlink_inband_mc_team_release_req_t mcTeamReleaseReq;
} nvlink_inband_mc_team_release_req_msg_t;
typedef struct
{
/* Fields to be replayed */
NvU64 gpuHandle; /* Unique handle that was provided by FM pre-migration. */
/* Other fields from the request */
NvU64 pciInfo; /* Encoded as Domain(63:32):Bus(15:8):Device(0:7). (debug only) */
NvU8 moduleId; /* GPIO based physical/module ID of the GPU. (debug only) */
NvUuid gpuUuid; /* UUID of the GPU. (debug only) */
NvU64 discoveredLinkMask; /* GPU's discovered NVLink mask info. (debug only) */
NvU64 enabledLinkMask; /* GPU's currently enabled NvLink mask info. (debug only) */
NvU32 gpuCapMask; /* GPU capabilities, one of NVLINK_INBAND_GPU_PROBE_CAPS */
NvU8 bwMode; /* NVLink bandwidth mode, one of NVLINK_INBAND_BW_MODE */
NvU8 reserved[31]; /* For future use. Must be initialized to zero */
} nvlink_inband_gpu_probe_replay_req_t;
typedef struct
{
nvlink_inband_msg_header_t msgHdr;
nvlink_inband_gpu_probe_replay_req_t probeReplayReq;
} nvlink_inband_gpu_probe_replay_req_msg_t;
typedef nvlink_inband_gpu_probe_rsp_t nvlink_inband_gpu_probe_replay_rsp_t;
typedef nvlink_inband_gpu_probe_rsp_msg_t nvlink_inband_gpu_probe_replay_rsp_msg_t;
typedef struct
{
/* Fields to be replayed */
NvU64 mcTeamHandle; /* Unique handle assigned for this Multicast team */
NvU64 mcAddressBase; /* FLA starting address assigned for the Multicast slot */
NvU64 mcAddressSize; /* Size of FLA assigned to the Multicast slot */
/* Other fields from the request */
NvU64 mcAllocSize; /* Multicast allocation size requested */
NvU32 flags; /* For future use. Must be initialized to zero */
NvU8 reserved[8]; /* For future use. Must be initialized to zero */
NvU16 numGpuHandles; /* Number of GPUs in this team */
NvU16 numKeys; /* Number of keys (a.k.a request ID) used by FM to send response */
NvU64 gpuHandlesAndKeys[]; /* Array of probed handles and keys, should be last */
} nvlink_inband_mc_team_setup_replay_req_t;
typedef struct
{
nvlink_inband_msg_header_t msgHdr;
nvlink_inband_mc_team_setup_replay_req_t mcTeamSetupReplayReq;
} nvlink_inband_mc_team_setup_replay_req_msg_t;
typedef nvlink_inband_mc_team_setup_rsp_t nvlink_inband_mc_team_setup_replay_rsp_t;
typedef nvlink_inband_mc_team_setup_rsp_msg_t nvlink_inband_mc_team_setup_replay_rsp_msg_t;
#pragma pack(pop)
/********************* Don't add any message structs after this line ******************************/

47
src/common/nvlink/interface/nvlink.h
View File

@@ -1,24 +1,25 @@
/*******************************************************************************
Copyright (c) 2014-2023 NVidia Corporation
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to
deal in the Software without restriction, including without limitation the
rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
sell copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be
included in all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
DEALINGS IN THE SOFTWARE.
*******************************************************************************/
/*
* SPDX-FileCopyrightText: Copyright (c) 2014-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
//
// nvlink.h
@@ -233,6 +234,8 @@ struct nvlink_link
// Has INITNEGOTIATE received CONFIG_GOOD (NVL3.0+)
NvBool bInitnegotiateConfigGood;
NvBool bCciManaged;
// Power state transition status
enum
{
@@ -279,6 +282,7 @@ struct nvlink_link_handlers
NV_API_CALL NvlStatus (*read_discovery_token) (struct nvlink_link *link, NvU64 *token);
NV_API_CALL void (*training_complete) (struct nvlink_link *link);
NV_API_CALL void (*get_uphy_load) (struct nvlink_link *link, NvBool* bUnlocked);
NV_API_CALL NvlStatus (*get_cci_link_mode) (struct nvlink_link *link, NvU64 *mode);
NV_API_CALL NvlStatus (*ali_training) (struct nvlink_link *link);
};
@@ -352,6 +356,7 @@ typedef struct nvlink_inband_data nvlink_inband_data;
#define NVLINK_LINKSTATE_INITPHASE5 0x1B // INITPHASE5
#define NVLINK_LINKSTATE_ALI 0x1C // ALI
#define NVLINK_LINKSTATE_ACTIVE_PENDING 0x1D // Intermediate state for a link going to active
#define NVLINK_LINKSTATE_TRAINING_CCI 0x1E // Intermediate state for a link that is still training
#define NVLINK_LINKSTATE_INVALID 0xFF // Invalid state
// NVLINK TX SUBLINK states

47
src/common/nvlink/interface/nvlink_lib_ctrl.h
View File

@@ -1,28 +1,30 @@
/*******************************************************************************
Copyright (c) 2016-2023 NVidia Corporation
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to
deal in the Software without restriction, including without limitation the
rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
sell copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be
included in all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
DEALINGS IN THE SOFTWARE.
*******************************************************************************/
/*
* SPDX-FileCopyrightText: Copyright (c) 2016-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _NVLINK_LIB_CTRL_H_
#define _NVLINK_LIB_CTRL_H_
#include "nvtypes.h"
#include "nvlink_errors.h"
@@ -67,6 +69,8 @@
#define NVLINK_VERSION_STRING_LENGTH 64
#define NVLINK_CCI_TRAINING_TIMEOUT_SEC 30
/*
* NVLink version consists of,
* major - no compatibility.
@@ -155,6 +159,7 @@ typedef enum
nvlink_link_mode_disable_pm,
nvlink_link_mode_traffic_setup,
nvlink_link_mode_contain,
nvlink_link_mode_training_cci
} nvlink_link_mode;
/* sublink tx modes */

40
src/common/nvlink/interface/nvlink_lock.h
View File

@@ -1,21 +1,25 @@
/*******************************************************************************
Copyright (c) 2020 NVidia Corporation
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to
deal in the Software without restriction, including without limitation the
rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
sell copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be
included in all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
DEALINGS IN THE SOFTWARE.
*******************************************************************************/
/*
* SPDX-FileCopyrightText: Copyright (c) 2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _NVLINK_LOCK_H_

43
src/common/nvlink/kernel/nvlink/core/nvlink_conn_mgmt.c
View File

@@ -1,24 +1,25 @@
/*******************************************************************************
Copyright (c) 2019-2022 NVidia Corporation
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to
deal in the Software without restriction, including without limitation the
rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
sell copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be
included in all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
DEALINGS IN THE SOFTWARE.
*******************************************************************************/
/*
* SPDX-FileCopyrightText: Copyright (c) 2019-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#include "nvlink.h"
#include "nvlink_export.h"

43
src/common/nvlink/kernel/nvlink/core/nvlink_discovery.c
View File

@@ -1,24 +1,25 @@
/*******************************************************************************
Copyright (c) 2019-2020 NVidia Corporation
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to
deal in the Software without restriction, including without limitation the
rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
sell copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be
included in all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
DEALINGS IN THE SOFTWARE.
*******************************************************************************/
/*
* SPDX-FileCopyrightText: Copyright (c) 2019-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#include "nvlink.h"
#include "nvlink_export.h"

43
src/common/nvlink/kernel/nvlink/core/nvlink_initialize.c
View File

@@ -1,24 +1,25 @@
/*******************************************************************************
Copyright (c) 2019-2021 NVidia Corporation
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to
deal in the Software without restriction, including without limitation the
rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
sell copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be
included in all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
DEALINGS IN THE SOFTWARE.
*******************************************************************************/
/*
* SPDX-FileCopyrightText: Copyright (c) 2019-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#include "nvlink.h"
#include "nvlink_export.h"

51
src/common/nvlink/kernel/nvlink/core/nvlink_ioctl.c
View File

@@ -1,24 +1,25 @@
/*******************************************************************************
Copyright (c) 2017-2023 NVidia Corporation
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to
deal in the Software without restriction, including without limitation the
rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
sell copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be
included in all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
DEALINGS IN THE SOFTWARE.
*******************************************************************************/
/*
* SPDX-FileCopyrightText: Copyright (c) 2017-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#include "nvlink.h"
#include "nvVer.h"
@@ -297,6 +298,7 @@ nvlink_core_get_endpoint_state
NvU64 state = NVLINK_LINKSTATE_INVALID;
NvU64 dlState = NVLINK_LINKSTATE_INVALID;
NvU64 tlState = NVLINK_LINKSTATE_INVALID;
NvU64 cciState = NVLINK_LINKSTATE_INVALID;
if ((link == NULL) || (linkState == NULL))
{
return;
@@ -317,6 +319,13 @@ nvlink_core_get_endpoint_state
linkState->linkMode = _nvlink_core_map_link_state(dlState, tlState);
// CCI link training in progress
link->link_handlers->get_cci_link_mode(link, &cciState);
if (cciState == NVLINK_LINKSTATE_TRAINING_CCI)
{
linkState->linkMode = nvlink_link_mode_training_cci;
}
status = link->link_handlers->get_tx_mode(link,
&state,
&txSubLinkSubstate);

43
src/common/nvlink/kernel/nvlink/core/nvlink_link_mgmt.c
View File

@@ -1,24 +1,25 @@
/*******************************************************************************
Copyright (c) 2019-2020 NVidia Corporation
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to
deal in the Software without restriction, including without limitation the
rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
sell copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be
included in all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
DEALINGS IN THE SOFTWARE.
*******************************************************************************/
/*
* SPDX-FileCopyrightText: Copyright (c) 2019-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#include "nvlink.h"
#include "nvlink_export.h"

43
src/common/nvlink/kernel/nvlink/core/nvlink_logger.c
View File

@@ -1,24 +1,25 @@
/*******************************************************************************
Copyright (c) 2019-2020 NVidia Corporation
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to
deal in the Software without restriction, including without limitation the
rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
sell copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be
included in all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
DEALINGS IN THE SOFTWARE.
*******************************************************************************/
/*
* SPDX-FileCopyrightText: Copyright (c) 2019-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#include "nvlink.h"
#include "nvlink_export.h"

85
src/common/nvlink/kernel/nvlink/core/nvlink_shutdown.c
View File

@@ -1,24 +1,25 @@
/*******************************************************************************
Copyright (c) 2019-2022 NVidia Corporation
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to
deal in the Software without restriction, including without limitation the
rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
sell copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be
included in all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
DEALINGS IN THE SOFTWARE.
*******************************************************************************/
/*
* SPDX-FileCopyrightText: Copyright (c) 2019-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#include "nvlink.h"
#include "nvlink_export.h"
@@ -434,6 +435,12 @@ nvlink_core_powerdown_intranode_conns_from_active_to_off
if (conns[i] == NULL)
continue;
if (conns[i]->end0->bCciManaged ||
conns[i]->end1->bCciManaged)
{
continue;
}
// Disable Power Management before moving link out of Active
conns[i]->end0->link_handlers->set_dl_link_mode(conns[i]->end0,
NVLINK_LINKSTATE_DISABLE_PM,
@@ -463,6 +470,12 @@ nvlink_core_powerdown_intranode_conns_from_active_to_off
if (conns[i] == NULL)
continue;
if (conns[i]->end0->bCciManaged ||
conns[i]->end1->bCciManaged)
{
continue;
}
// Wait for the end0 to go to SWCFG
status = nvlink_core_poll_link_state(conns[i]->end0,
NVLINK_LINKSTATE_SAFE,
@@ -521,6 +534,12 @@ nvlink_core_powerdown_intranode_conns_from_active_to_off
if (conns[i] == NULL)
continue;
if (conns[i]->end0->bCciManaged ||
conns[i]->end1->bCciManaged)
{
continue;
}
// Wait for sublinks to go to SAFE
if(conns[i]->end0->inSWCFG == NV_TRUE)
{
@@ -674,6 +693,12 @@ nvlink_core_powerdown_intranode_conns_from_active_to_swcfg
if (conns[i] == NULL)
continue;
if (conns[i]->end0->bCciManaged ||
conns[i]->end1->bCciManaged)
{
continue;
}
// Disable Power Management before moving link out of Active
conns[i]->end0->link_handlers->set_dl_link_mode(conns[i]->end0,
NVLINK_LINKSTATE_DISABLE_PM,
@@ -705,6 +730,12 @@ nvlink_core_powerdown_intranode_conns_from_active_to_swcfg
if (conns[i] == NULL)
continue;
if (conns[i]->end0->bCciManaged ||
conns[i]->end1->bCciManaged)
{
continue;
}
// Wait for the end0 to go to SWCFG
status = nvlink_core_poll_link_state(conns[i]->end0,
NVLINK_LINKSTATE_SAFE,
@@ -751,6 +782,12 @@ nvlink_core_powerdown_intranode_conns_from_active_to_swcfg
if (conns[i] == NULL)
continue;
if (conns[i]->end0->bCciManaged ||
conns[i]->end1->bCciManaged)
{
continue;
}
status = nvlink_core_poll_sublink_state(conns[i]->end0,
NVLINK_SUBLINK_STATE_TX_SAFE,
NVLINK_SUBLINK_SUBSTATE_TX_STABLE,
@@ -842,6 +879,12 @@ nvlink_core_reset_intranode_conns
if (conns[i] == NULL)
continue;
if (conns[i]->end0->bCciManaged ||
conns[i]->end1->bCciManaged)
{
continue;
}
//
// Reset both ends of this connection.
// This path should enable/init those link endpoints as well.

Some files were not shown because too many files have changed in this diff Show More