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550.40.07

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This commit is contained in:
Bernhard Stoeckner
2024-01-24 17:51:53 +01:00
parent bb2dac1f20
commit 91676d6628
1411 changed files with 261367 additions and 145959 deletions
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5
src/common/inc/displayport/displayport.h
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@@ -23,6 +23,7 @@
#ifndef _DISPLAYPORT_H_
#define _DISPLAYPORT_H_
#include "nvcfg_sdk.h"
#include "nvmisc.h"
#include "dpcd.h"
@@ -161,7 +162,7 @@ typedef enum
trainingPattern_1 = 0x1,
trainingPattern_2 = 0x2,
trainingPattern_3 = 0x3,
trainingPattern_4 = 0xB
trainingPattern_4 = 0xB,
} DP_TRAININGPATTERN;
typedef enum
@@ -245,6 +246,8 @@ typedef struct DscCaps
{
NvBool bDSCSupported;
NvBool bDSCDecompressionSupported;
NvBool bDynamicPPSSupported;
NvBool bDynamicDscToggleSupported;
NvBool bDSCPassThroughSupported;
unsigned versionMajor, versionMinor;
unsigned rcBufferBlockSize;

8
src/common/inc/displayport/dpcd.h
View File

@@ -697,6 +697,14 @@ number of Downstream ports will be limited to 32.
#define NV_DPCD_ADJUST_REQ_POST_CURSOR2_LANE6 5:4 /* R-XUF */
#define NV_DPCD_ADJUST_REQ_POST_CURSOR2_LANE7 7:6 /* R-XUF */
#define NV_DPCD_EDP_LINK_CONFIG_STATUS (0x0000020c) /* RWXUR */
#define NV_DPCD_EDP_LINK_CONFIG_STATUS_SET 0:0 /* R-XUF */
#define NV_DPCD_EDP_LINK_CONFIG_STATUS_SET_LINK_BW (0x00000000) /* R-XUV */
#define NV_DPCD_EDP_LINK_CONFIG_STATUS_SET_LINK_RATE (0x00000001) /* R-XUV */
#define NV_DPCD_EDP_LINK_CONFIG_STATUS_VALID 1:1 /* R-XUF */
#define NV_DPCD_EDP_LINK_CONFIG_STATUS_VALID_NO (0x00000000) /* R-XUV */
#define NV_DPCD_EDP_LINK_CONFIG_STATUS_VALID_YES (0x00000001) /* R-XUV */
// 0020Fh: RESERVED. Read all 0s
#define NV_DPCD_SYMBOL_ERROR_COUNT_LANEX_BYTE0(i) (0x00000210+(i)*2) /* R--1A */

96
src/common/inc/displayport/dpcd14.h
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@@ -43,9 +43,9 @@
#define NV_DPCD14_TRAINING_AUX_RD_INTERVAL_EXTENDED_RX_CAP_YES (0x00000001) /* R-XUV */
#define NV_DPCD14_DSC_SUPPORT (0x00000060) /* R-XUR */
#define NV_DPCD14_DSC_SUPPORT_DSC_SUPPORT 0:0 /* R-XUF */
#define NV_DPCD14_DSC_SUPPORT_DSC_SUPPORT_NO (0x00000000) /* R-XUV */
#define NV_DPCD14_DSC_SUPPORT_DSC_SUPPORT_YES (0x00000001) /* R-XUV */
#define NV_DPCD14_DSC_SUPPORT_DECOMPRESSION 0:0 /* R-XUF */
#define NV_DPCD14_DSC_SUPPORT_DECOMPRESSION_NO (0x00000000) /* R-XUV */
#define NV_DPCD14_DSC_SUPPORT_DECOMPRESSION_YES (0x00000001) /* R-XUV */
#define NV_DPCD14_DSC_ALGORITHM_REVISION (0x00000061) /* R-XUR */
#define NV_DPCD14_DSC_ALGORITHM_REVISION_MAJOR 3:0 /* R-XUF */
@@ -190,9 +190,9 @@
#define NV_DPCD14_DSC_BITS_PER_PIXEL_INCREMENT_SUPPORTED_1 (0x00000004) /* R-XUV */
#define NV_DPCD14_DSC_ENABLE (0x00000160) /* R-XUR */
#define NV_DPCD14_DSC_ENABLE_SINK 0:0 /* R-XUF */
#define NV_DPCD14_DSC_ENABLE_SINK_NO (0x00000000) /* R-XUV */
#define NV_DPCD14_DSC_ENABLE_SINK_YES (0x00000001) /* R-XUV */
#define NV_DPCD14_DSC_ENABLE_DECOMPRESSION 0:0 /* R-XUF */
#define NV_DPCD14_DSC_ENABLE_DECOMPRESSION_NO (0x00000000) /* R-XUV */
#define NV_DPCD14_DSC_ENABLE_DECOMPRESSION_YES (0x00000001) /* R-XUV */
#define NV_DPCD14_FEC_CAPABILITY (0x00000090) /* R-XUR */
#define NV_DPCD14_FEC_CAPABILITY_FEC_CAPABLE 0:0 /* R-XUF */
@@ -213,7 +213,9 @@
#define NV_DPCD14_FEC_CAPABILITY_PARITY_ERROR_COUNT_CAPABLE 5:5 /* R-XUF */
#define NV_DPCD14_FEC_CAPABILITY_PARITY_ERROR_COUNT_CAPABLE_NO (0x00000000) /* R-XUV */
#define NV_DPCD14_FEC_CAPABILITY_PARITY_ERROR_COUNT_CAPABLE_YES (0x00000001) /* R-XUV */
// Bit 6 : RESERVED. Read 0
#define NV_DPCD14_FEC_CAPABILITY_FEC_RUNNING_INDICATOR_SUPPORT 6:6 /* R-XUF */
#define NV_DPCD14_FEC_CAPABILITY_FEC_RUNNING_INDICATOR_SUPPORT_NO (0x00000000) /* R-XUV */
#define NV_DPCD14_FEC_CAPABILITY_FEC_RUNNING_INDICATOR_SUPPORT_YES (0x00000001) /* R-XUV */
#define NV_DPCD14_FEC_CAPABILITY_FEC_ERROR_REPORTING_POLICY_SUPPORTED 7:7 /* R-XUF */
#define NV_DPCD14_FEC_CAPABILITY_FEC_ERROR_REPORTING_POLICY_SUPPORTED_NO (0x00000000) /* R-XUV */
#define NV_DPCD14_FEC_CAPABILITY_FEC_ERROR_REPORTING_POLICY_SUPPORTED_YES (0x00000001) /* R-XUV */
@@ -629,36 +631,6 @@
#define NV_DPCD14_PHY_REPEATER_EXTENDED_WAKE_TIMEOUT_REQ 6:0 /* R-XUF */
#define NV_DPCD14_PHY_REPEATER_EXTENDED_WAKE_TIMEOUT_GRANT 7:7 /* RWXUF */
#define NV_DPCD14_PHY_REPEATER_EQ_DONE (0x000F0008) /* R-XUR */
#define NV_DPCD14_PHY_REPEATER_EQ_DONE_LTTPR(i) (i):(i) /* R-XUF */
#define NV_DPCD14_PHY_REPEATER_EQ_DONE_LTTPR_NO (0x00000000) /* R-XUF */
#define NV_DPCD14_PHY_REPEATER_EQ_DONE_LTTPR_YES (0x00000001) /* R-XUF */
#define NV_DPCD14_PHY_REPEATER_EQ_DONE_LTTPR_0 0:0 /* R-XUF */
#define NV_DPCD14_PHY_REPEATER_EQ_DONE_LTTPR_0_NO (0x00000000) /* R-XUF */
#define NV_DPCD14_PHY_REPEATER_EQ_DONE_LTTPR_0_YES (0x00000001) /* R-XUF */
#define NV_DPCD14_PHY_REPEATER_EQ_DONE_LTTPR_1 1:1 /* R-XUF */
#define NV_DPCD14_PHY_REPEATER_EQ_DONE_LTTPR_1_NO (0x00000000) /* R-XUF */
#define NV_DPCD14_PHY_REPEATER_EQ_DONE_LTTPR_1_YES (0x00000001) /* R-XUF */
#define NV_DPCD14_PHY_REPEATER_EQ_DONE_LTTPR_2 2:2 /* R-XUF */
#define NV_DPCD14_PHY_REPEATER_EQ_DONE_LTTPR_2_NO (0x00000000) /* R-XUF */
#define NV_DPCD14_PHY_REPEATER_EQ_DONE_LTTPR_2_YES (0x00000001) /* R-XUF */
#define NV_DPCD14_PHY_REPEATER_EQ_DONE_LTTPR_3 3:3 /* R-XUF */
#define NV_DPCD14_PHY_REPEATER_EQ_DONE_LTTPR_3_NO (0x00000000) /* R-XUF */
#define NV_DPCD14_PHY_REPEATER_EQ_DONE_LTTPR_3_YES (0x00000001) /* R-XUF */
#define NV_DPCD14_PHY_REPEATER_EQ_DONE_LTTPR_4 4:4 /* R-XUF */
#define NV_DPCD14_PHY_REPEATER_EQ_DONE_LTTPR_4_NO (0x00000000) /* R-XUF */
#define NV_DPCD14_PHY_REPEATER_EQ_DONE_LTTPR_4_YES (0x00000001) /* R-XUF */
#define NV_DPCD14_PHY_REPEATER_EQ_DONE_LTTPR_5 5:5 /* R-XUF */
#define NV_DPCD14_PHY_REPEATER_EQ_DONE_LTTPR_5_NO (0x00000000) /* R-XUF */
#define NV_DPCD14_PHY_REPEATER_EQ_DONE_LTTPR_5_YES (0x00000001) /* R-XUF */
#define NV_DPCD14_PHY_REPEATER_EQ_DONE_LTTPR_6 6:6 /* R-XUF */
#define NV_DPCD14_PHY_REPEATER_EQ_DONE_LTTPR_6_NO (0x00000000) /* R-XUF */
#define NV_DPCD14_PHY_REPEATER_EQ_DONE_LTTPR_6_YES (0x00000001) /* R-XUF */
#define NV_DPCD14_PHY_REPEATER_EQ_DONE_LTTPR_7 7:7 /* R-XUF */
#define NV_DPCD14_PHY_REPEATER_EQ_DONE_LTTPR_7_NO (0x00000000) /* R-XUF */
#define NV_DPCD14_PHY_REPEATER_EQ_DONE_LTTPR_7_YES (0x00000001) /* R-XUF */
#define NV_DPCD14_PHY_REPEATER_START(i) (0x000F0010+(i)*0x50) /* RW-1A */
#define NV_DPCD14_PHY_REPEATER_START__SIZE 8 /* R---S */
// Following defines are offsets
@@ -689,6 +661,56 @@
#define NV_DPCD14_ADJUST_REQUEST_LANE0_1_PHY_REPEATER (0x00000023) /* R-XUR */
#define NV_DPCD14_ADJUST_REQUEST_LANE2_3_PHY_REPEATER (0x00000024) /* R-XUR */
#define NV_DPCD14_PHY_REPEATER_FEC__SIZE NV_DPCD14_PHY_REPEATER_CNT_MAX /* R---S */
#define NV_DPCD14_PHY_REPEATER_FEC_STATUS(i) (0x000F0290+(i)*8) /* R--1A */
#define NV_DPCD14_PHY_REPEATER_FEC_STATUS_FEC_DECODE_EN_DETECTED 0:0 /* R-XUF */
#define NV_DPCD14_PHY_REPEATER_FEC_STATUS_FEC_DECODE_EN_DETECTED_NO (0x00000000) /* R-XUV */
#define NV_DPCD14_PHY_REPEATER_FEC_STATUS_FEC_DECODE_EN_DETECTED_YES (0x00000001) /* R-XUV */
#define NV_DPCD14_PHY_REPEATER_FEC_STATUS_FEC_DECODE_DIS_DETECTED 1:1 /* R-XUF */
#define NV_DPCD14_PHY_REPEATER_FEC_STATUS_FEC_DECODE_DIS_DETECTED_NO (0x00000000) /* R-XUV */
#define NV_DPCD14_PHY_REPEATER_FEC_STATUS_FEC_DECODE_DIS_DETECTED_YES (0x00000001) /* R-XUV */
#define NV_DPCD14_PHY_REPEATER_FEC_STATUS_FEC_RUNNING_INDICATOR 2:2 /* R-XUF */
#define NV_DPCD14_PHY_REPEATER_FEC_STATUS_FEC_RUNNING_INDICATOR_NO (0x00000000) /* R-XUV */
#define NV_DPCD14_PHY_REPEATER_FEC_STATUS_FEC_RUNNING_INDICATOR_YES (0x00000001) /* R-XUV */
#define NV_DPCD14_PHY_REPEATER_FEC_ERR_COUNT(i) (0x000F0291+(i)*8) /* R--2A */
#define NV_DPCD14_PHY_REPEATER_FEC_ERR_COUNT_LOW_BYTE(i) (NV_DPCD14_PHY_REPEATER_FEC_ERR_COUNT(i))
#define NV_DPCD14_PHY_REPEATER_FEC_ERR_COUNT_HIGH_BYTE(i) ((0x000F0292+(i)*8)) /* R-XUR */
#define NV_DPCD14_PHY_REPEATER_FEC_ERR_COUNT_VALID 7:7 /* R-XUF */
#define NV_DPCD14_PHY_REPEATER_FEC_ERR_COUNT_VALID_NO (0x00000000) /* R-XUV */
#define NV_DPCD14_PHY_REPEATER_FEC_ERR_COUNT_VALID_YES (0x00000001) /* R-XUV */
#define NV_DPCD14_PHY_REPEATER_FEC_CAP_0(i) (0x000F0294+(i)*8) /* R--1A */
#define NV_DPCD14_PHY_REPEATER_FEC_CAP_0_FEC_CAPABLE 0:0 /* R-XUF */
#define NV_DPCD14_PHY_REPEATER_FEC_CAP_0_FEC_CAPABLE_NO (0x00000000) /* R-XUV */
#define NV_DPCD14_PHY_REPEATER_FEC_CAP_0_FEC_CAPABLE_YES (0x00000001) /* R-XUV */
#define NV_DPCD14_PHY_REPEATER_FEC_CAP_0_UNCORRECTED_BLOCK_ERROR_COUNT_CAPABLE 1:1 /* R-XUF */
#define NV_DPCD14_PHY_REPEATER_FEC_CAP_0_UNCORRECTED_BLOCK_ERROR_COUNT_CAPABLE_NO (0x00000000) /* R-XUV */
#define NV_DPCD14_PHY_REPEATER_FEC_CAP_0_UNCORRECTED_BLOCK_ERROR_COUNT_CAPABLE_YES (0x00000001) /* R-XUV */
#define NV_DPCD14_PHY_REPEATER_FEC_CAP_0_CORRECTED_BLOCK_ERROR_COUNT_CAPABLE 2:2 /* R-XUF */
#define NV_DPCD14_PHY_REPEATER_FEC_CAP_0CORRECTED_BLOCK_ERROR_COUNT_CAPABLE_NO (0x00000000) /* R-XUV */
#define NV_DPCD14_PHY_REPEATER_FEC_CAP_0_CORRECTED_BLOCK_ERROR_COUNT_CAPABLE_YES (0x00000001) /* R-XUV */
#define NV_DPCD14_PHY_REPEATER_FEC_CAP_0_BIT_ERROR_COUNT_CAPABLE 3:3 /* R-XUF */
#define NV_DPCD14_PHY_REPEATER_FEC_CAP_0_BIT_ERROR_COUNT_CAPABLE_NO (0x00000000) /* R-XUV */
#define NV_DPCD14_PHY_REPEATER_FEC_CAP_0_BIT_ERROR_COUNT_CAPABLE_YES (0x00000001) /* R-XUV */
#define NV_DPCD14_PHY_REPEATER_FEC_CAP_0_PARITY_BLOCK_ERROR_COUNT_CAPABLE 4:4 /* R-XUF */
#define NV_DPCD14_PHY_REPEATER_FEC_CAP_0_PARITY_BLOCK_ERROR_COUNT_CAPABLE_NO (0x00000000) /* R-XUV */
#define NV_DPCD14_PHY_REPEATER_FEC_CAP_0_PARITY_BLOCK_ERROR_COUNT_CAPABLE_YES (0x00000001) /* R-XUV */
#define NV_DPCD14_PHY_REPEATER_FEC_CAP_0_PARITY_ERROR_COUNT_CAPABLE 5:5 /* R-XUF */
#define NV_DPCD14_PHY_REPEATER_FEC_CAP_0_PARITY_ERROR_COUNT_CAPABLE_NO (0x00000000) /* R-XUV */
#define NV_DPCD14_PHY_REPEATER_FEC_CAP_0_PARITY_ERROR_COUNT_CAPABLE_YES (0x00000001) /* R-XUV */
#define NV_DPCD14_PHY_REPEATER_FEC_CAP_0_FEC_RUNNING_INDICATOR_SUPPORT 6:6 /* R-XUF */
#define NV_DPCD14_PHY_REPEATER_FEC_CAP_0_FEC_RUNNING_INDICATOR_SUPPORT_NO (0x00000000) /* R-XUV */
#define NV_DPCD14_PHY_REPEATER_FEC_CAP_0_FEC_RUNNING_INDICATOR_SUPPORT_YES (0x00000001) /* R-XUV */
#define NV_DPCD14_PHY_REPEATER_FEC_CAP_0_FEC_ERROR_REPORTING_POLICY_SUPPORTED 7:7 /* R-XUF */
#define NV_DPCD14_PHY_REPEATER_FEC_CAP_0_FEC_ERROR_REPORTING_POLICY_SUPPORTED_NO (0x00000000) /* R-XUV */
#define NV_DPCD14_PHY_REPEATER_FEC_CAP_0_FEC_ERROR_REPORTING_POLICY_SUPPORTED_YES (0x00000001) /* R-XUV */
#define NV_DPCD14_PHY_REPEATER_FEC_CAP_1(i) (0x000F0295+(i)*8) /* R--1A */
#define NV_DPCD14_PHY_REPEATER_FEC_CAP_1_AGGREGATE_ERR_COUNT_CAPABLE 0:0 /* R-XUF */
#define NV_DPCD14_PHY_REPEATER_FEC_CAP_1_AGGREGATE_ERR_COUNT_CAPABLE_CAPABLE_N (0x00000000) /* R-XUV */
#define NV_DPCD14_PHY_REPEATER_FEC_CAP_1_AGGREGATE_ERR_COUNT_CAPABLE_CAPABLE_YES (0x00000001) /* R-XUV */
// BRANCH SPECIFIC DSC CAPS
#define NV_DPCD14_BRANCH_DSC_OVERALL_THROUGHPUT_MODE_0 (0x000000A0)
#define NV_DPCD14_BRANCH_DSC_OVERALL_THROUGHPUT_MODE_0_VALUE 7:0

16
src/common/inc/displayport/dpcd20.h
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@@ -25,14 +25,24 @@
#include "nvcfg_sdk.h"
// DSC Pass Through related DPCD. New bits in DPCD 0x0060h defined in DPCD2.0.
#define NV_DPCD20_DSC_SUPPORT_PASS_THROUGH_SUPPORT 1:1 /* R-XUF */
#define NV_DPCD20_DSC_SUPPORT_PASS_THROUGH_SUPPORT_NO (0x00000000) /* R-XUV */
#define NV_DPCD20_DSC_SUPPORT_PASS_THROUGH_SUPPORT_YES (0x00000001) /* R-XUV */
#define NV_DPCD20_DSC_SUPPORT_PASS_THROUGH 1:1 /* R-XUF */
#define NV_DPCD20_DSC_SUPPORT_PASS_THROUGH_NO (0x00000000) /* R-XUV */
#define NV_DPCD20_DSC_SUPPORT_PASS_THROUGH_YES (0x00000001) /* R-XUV */
// DSC Pass Through related DPCD. New bits in DPCD 0x0160h defined in DPCD2.0.
#define NV_DPCD20_DSC_ENABLE_PASS_THROUGH 1:1 /* R-XUF */
#define NV_DPCD20_DSC_ENABLE_PASS_THROUGH_NO (0x00000000) /* R-XUV */
#define NV_DPCD20_DSC_ENABLE_PASS_THROUGH_YES (0x00000001) /* R-XUV */
// DSC Dynamic PPS related DPCD. New bits in DPCD 0x0060h defined in DPCD2.0.
#define NV_DPCD20_DSC_SUPPORT_DYNAMIC_PPS_COMPRESSED_TO_COMPRESSED 2:2
#define NV_DPCD20_DSC_SUPPORT_DYNAMIC_PPS_COMPRESSED_TO_COMPRESSED_NO (0x00000000)
#define NV_DPCD20_DSC_SUPPORT_DYNAMIC_PPS_COMPRESSED_TO_COMPRESSED_YES (0x00000001)
// DSC Dynamic PPS related DPCD. New bits in DPCD 0x0060h defined in DPCD2.0.
#define NV_DPCD20_DSC_SUPPORT_DYNAMIC_PPS_UNCOMPRESSED_TO_FROM_COMPRESSED 3:3
#define NV_DPCD20_DSC_SUPPORT_DYNAMIC_PPS_UNCOMPRESSED_TO_FROM_COMPRESSED_NO (0x00000000)
#define NV_DPCD20_DSC_SUPPORT_DYNAMIC_PPS_UNCOMPRESSED_TO_FROM_COMPRESSED_YES (0x00000001)
// PANEL REPLAY RELATED DPCD
#define NV_DPCD20_PANEL_REPLAY_CAPABILITY (0x000000B0)
#define NV_DPCD20_PANEL_REPLAY_CAPABILITY_SUPPORTED 0:0

22
src/common/inc/nvBldVer.h
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@@ -36,26 +36,26 @@
// and then checked back in. You cannot make changes to these sections without
// corresponding changes to the buildmeister script
#ifndef NV_BUILD_BRANCH
#define NV_BUILD_BRANCH r545_96
#define NV_BUILD_BRANCH r551_06
#endif
#ifndef NV_PUBLIC_BRANCH
#define NV_PUBLIC_BRANCH r545_96
#define NV_PUBLIC_BRANCH r551_06
#endif
#if defined(NV_LINUX) || defined(NV_BSD) || defined(NV_SUNOS)
#define NV_BUILD_BRANCH_VERSION "rel/gpu_drv/r545/r545_96-124"
#define NV_BUILD_CHANGELIST_NUM (33538619)
#define NV_BUILD_BRANCH_VERSION "rel/gpu_drv/r550/r551_06-132"
#define NV_BUILD_CHANGELIST_NUM (33773930)
#define NV_BUILD_TYPE "Official"
#define NV_BUILD_NAME "rel/gpu_drv/r545/r545_96-124"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (33538619)
#define NV_BUILD_NAME "rel/gpu_drv/r550/r551_06-132"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (33773930)
#else /* Windows builds */
#define NV_BUILD_BRANCH_VERSION "r545_96-8"
#define NV_BUILD_CHANGELIST_NUM (33517029)
#define NV_BUILD_BRANCH_VERSION "r551_06-14"
#define NV_BUILD_CHANGELIST_NUM (33773930)
#define NV_BUILD_TYPE "Official"
#define NV_BUILD_NAME "546.17"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (33517029)
#define NV_BUILD_BRANCH_BASE_VERSION R545
#define NV_BUILD_NAME "551.23"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (33773930)
#define NV_BUILD_BRANCH_BASE_VERSION R550
#endif
// End buildmeister python edited section

2
src/common/inc/nvPNPVendorIds.h
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@@ -157,6 +157,7 @@ static const PNPVendorId PNPVendorIds[] =
{ "CRS", _VENDOR_NAME_ENTRY("Cisco") },
{ "CSE", _VENDOR_NAME_ENTRY("Compu Shack") },
{ "CSI", _VENDOR_NAME_ENTRY("Cabletron") },
{ "CSO", _VENDOR_NAME_ENTRY("California institute of Technology")},
{ "CSS", _VENDOR_NAME_ENTRY("CSS Laboratories") },
{ "CSW", _VENDOR_NAME_ENTRY("China Star Optoelectronics Technology Co., Ltd") },
{ "CTN", _VENDOR_NAME_ENTRY("Computone") },
@@ -294,6 +295,7 @@ static const PNPVendorId PNPVendorIds[] =
{ "ITK", _VENDOR_NAME_ENTRY("NTI Group") },
{ "IVK", _VENDOR_NAME_ENTRY("Iiyama") },
{ "IVM", _VENDOR_NAME_ENTRY("Idek Iiyama") },
{ "IVO", _VENDOR_NAME_ENTRY("InfoVision OptoElectronics Co., Ltd")},
{ "IVR", _VENDOR_NAME_ENTRY("Inlife-Handnet Co., Ltd.") },
{ "IWR", _VENDOR_NAME_ENTRY("Icuiti Corporation") },

2
src/common/inc/nvUnixVersion.h
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@@ -4,7 +4,7 @@
#if defined(NV_LINUX) || defined(NV_BSD) || defined(NV_SUNOS) || defined(NV_VMWARE) || defined(NV_QNX) || defined(NV_INTEGRITY) || \
(defined(RMCFG_FEATURE_PLATFORM_GSP) && RMCFG_FEATURE_PLATFORM_GSP == 1)
#define NV_VERSION_STRING "545.29.06"
#define NV_VERSION_STRING "550.40.07"
#else

2
src/common/inc/nvVer.h
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@@ -3,7 +3,7 @@
#define NV_COMPANY_NAME_STRING_SHORT "NVIDIA"
#define NV_COMPANY_NAME_STRING_FULL "NVIDIA Corporation"
#define NV_COMPANY_NAME_STRING NV_COMPANY_NAME_STRING_FULL
#define NV_COPYRIGHT_YEAR "2023"
#define NV_COPYRIGHT_YEAR "2024"
#define NV_COPYRIGHT "(C) " NV_COPYRIGHT_YEAR " NVIDIA Corporation. All rights reserved." // Please do not use the non-ascii copyright symbol for (C).
#if defined(NV_LINUX) || defined(NV_BSD) || defined(NV_SUNOS) || defined(NV_VMWARE) || defined(NV_QNX) || defined(NV_INTEGRITY) || \

217
src/common/inc/nveGPUConfig.h
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@@ -1,217 +0,0 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2018-2019 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _NVEGPUCONFIG_H_
#define _NVEGPUCONFIG_H_
#include <nvtypes.h>
#ifdef __cplusplus
extern "C" {
#endif
#ifdef __cplusplus
#define EGPU_INLINE NV_FORCEINLINE
#else //!__cplusplus
#if defined(NV_UNIX) || defined(NVCPU_RISCV64) || defined(NV_MODS)
#define EGPU_INLINE static NV_INLINE
#else //NV_UNIX
#define EGPU_INLINE NV_INLINE
#endif //NV_UNIX
#endif //!__cplusplus
// Surprise removal capable TB3 and TB2 BUS Device ID
#define BUS_DEVICE_ID_TB3_ALPINE_RIDGE_01 0x1578
#define BUS_DEVICE_ID_TB3_02 0x1576
#define BUS_DEVICE_ID_TB3_03 0x15C0
#define BUS_DEVICE_ID_TB3_04 0x15D3
#define BUS_DEVICE_ID_TB3_05 0x15DA
#define BUS_DEVICE_ID_TB3_06 0x15EA
#define BUS_DEVICE_ID_TB3_07 0x15E7
#define BUS_DEVICE_ID_TB3_08 0x15EF
#define BUS_DEVICE_ID_TB3_09 0x1133
#define BUS_DEVICE_ID_TB3_10 0x1136
// IceLake-U TB3 device ids. Below TB3 would be integrated to CPU.
#define BUS_DEVICE_ID_ICELAKE_TB3_01 0x8A1D
#define BUS_DEVICE_ID_ICELAKE_TB3_02 0x8A1F
#define BUS_DEVICE_ID_ICELAKE_TB3_03 0x8A21
#define BUS_DEVICE_ID_ICELAKE_TB3_04 0x8A23
#define BUS_DEVICE_ID_ICELAKE_TB3_05 0x8A0D
#define BUS_DEVICE_ID_ICELAKE_TB3_06 0x8A17
// TigerLake Thunderbolt device ids.
#define BUS_DEVICE_ID_TIGERLAKE_TB3_01 0x9A1B
#define BUS_DEVICE_ID_TIGERLAKE_TB3_02 0x9A1D
#define BUS_DEVICE_ID_TIGERLAKE_TB3_03 0x9A1F
#define BUS_DEVICE_ID_TIGERLAKE_TB3_04 0x9A21
#define BUS_DEVICE_ID_TIGERLAKE_TB3_05 0x9A23
#define BUS_DEVICE_ID_TIGERLAKE_TB3_06 0x9A25
#define BUS_DEVICE_ID_TIGERLAKE_TB3_07 0x9A27
#define BUS_DEVICE_ID_TIGERLAKE_TB3_08 0x9A29
#define BUS_DEVICE_ID_TIGERLAKE_TB3_09 0x9A2B
#define BUS_DEVICE_ID_TIGERLAKE_TB3_10 0x9A2D
// Meteor Lake ThunderBolt Device IDs
#define BUS_DEVICE_ID_METEOR_TB3_01 0x7EB2
#define BUS_DEVICE_ID_METEOR_TB3_02 0x7EC2
#define BUS_DEVICE_ID_METEOR_TB3_03 0x7EC3
#define BUS_DEVICE_ID_METEOR_TB3_04 0x7EB4
#define BUS_DEVICE_ID_METEOR_TB3_05 0x7EC4
#define BUS_DEVICE_ID_METEOR_TB3_06 0x7EB5
#define BUS_DEVICE_ID_METEOR_TB3_07 0x7EC5
#define BUS_DEVICE_ID_METEOR_TB3_08 0x7EC6
#define BUS_DEVICE_ID_METEOR_TB3_09 0x7EC7
// Raptor Lake ThunderBolt Device IDs
#define BUS_DEVICE_ID_RAPTOR_TB3_01 0xA73E
#define BUS_DEVICE_ID_RAPTOR_TB3_02 0xA76D
#define BUS_DEVICE_ID_RAPTOR_TB3_03 0x466E
#define BUS_DEVICE_ID_RAPTOR_TB3_04 0x463F
#define BUS_DEVICE_ID_RAPTOR_TB3_05 0x462F
#define BUS_DEVICE_ID_RAPTOR_TB3_06 0x461F
//#define BUS_DEVICE_ID_TB2_FALCON_RIDGE_DSL5520_01 0X156C // obsolete
#define BUS_DEVICE_ID_TB2_FALCON_RIDGE_DSL5520_02 0X156D
#define BUS_DEVICE_ID_TB2_03 0x157E
#define BUS_DEVICE_ID_TB2_04 0x156B
#define BUS_DEVICE_ID_TB2_05 0x1567
#define BUS_DEVICE_ID_TB2_06 0x1569
//#define BUS_DEVICE_ID_TB2_07 0x1548 // obsolete
#define BUS_DEVICE_ID_TB2_08 0x151B
#define BUS_DEVICE_ID_TB2_09 0x1549
#define BUS_DEVICE_ID_TB2_10 0x1513
//*****************************************************************************
// Function: isTB3DeviceID
//
// Routine Description:
//
// Function to match the specified Device ID with the known TB3 BUS's
// device IDs.
//
// Arguments:
//
// deviceID[IN]: Device ID to match with the TB3 Bus
//
// Return Value:
//
// true: When the passed Dev ID match with TB3's BUS Device ID
// false: When the passed Dev ID is not matching with known TB3's
// BUS Device ID
//*****************************************************************************
EGPU_INLINE NvBool isTB3DeviceID(NvU16 deviceID)
{
NvU32 index;
NvU16 tb3DeviceIDList[]={ BUS_DEVICE_ID_TB3_ALPINE_RIDGE_01,
BUS_DEVICE_ID_TB3_02,
BUS_DEVICE_ID_TB3_03,
BUS_DEVICE_ID_TB3_04,
BUS_DEVICE_ID_TB3_05,
BUS_DEVICE_ID_TB3_06,
BUS_DEVICE_ID_TB3_07,
BUS_DEVICE_ID_TB3_08,
BUS_DEVICE_ID_TB3_09,
BUS_DEVICE_ID_TB3_10,
BUS_DEVICE_ID_ICELAKE_TB3_01,
BUS_DEVICE_ID_ICELAKE_TB3_02,
BUS_DEVICE_ID_ICELAKE_TB3_03,
BUS_DEVICE_ID_ICELAKE_TB3_04,
BUS_DEVICE_ID_ICELAKE_TB3_05,
BUS_DEVICE_ID_ICELAKE_TB3_06,
BUS_DEVICE_ID_TIGERLAKE_TB3_01,
BUS_DEVICE_ID_TIGERLAKE_TB3_02,
BUS_DEVICE_ID_TIGERLAKE_TB3_03,
BUS_DEVICE_ID_TIGERLAKE_TB3_04,
BUS_DEVICE_ID_TIGERLAKE_TB3_05,
BUS_DEVICE_ID_TIGERLAKE_TB3_06,
BUS_DEVICE_ID_TIGERLAKE_TB3_07,
BUS_DEVICE_ID_TIGERLAKE_TB3_08,
BUS_DEVICE_ID_TIGERLAKE_TB3_09,
BUS_DEVICE_ID_TIGERLAKE_TB3_10,
BUS_DEVICE_ID_METEOR_TB3_01,
BUS_DEVICE_ID_METEOR_TB3_02,
BUS_DEVICE_ID_METEOR_TB3_03,
BUS_DEVICE_ID_METEOR_TB3_04,
BUS_DEVICE_ID_METEOR_TB3_05,
BUS_DEVICE_ID_METEOR_TB3_06,
BUS_DEVICE_ID_METEOR_TB3_07,
BUS_DEVICE_ID_METEOR_TB3_08,
BUS_DEVICE_ID_METEOR_TB3_09,
BUS_DEVICE_ID_RAPTOR_TB3_01,
BUS_DEVICE_ID_RAPTOR_TB3_02,
BUS_DEVICE_ID_RAPTOR_TB3_03,
BUS_DEVICE_ID_RAPTOR_TB3_04,
BUS_DEVICE_ID_RAPTOR_TB3_05,
BUS_DEVICE_ID_RAPTOR_TB3_06
};
for (index = 0; index < (sizeof(tb3DeviceIDList)/sizeof(NvU16)); index++)
{
if (deviceID == tb3DeviceIDList[index])
{
return NV_TRUE;
}
}
return NV_FALSE;
} // isTB3DeviceID
//*****************************************************************************
// Function: isTB2DeviceID
//
// Routine Description:
//
// Function to match the specified Device ID with the known TB2 BUS's
// device IDs.
//
// Arguments:
//
// deviceID[IN]: Device ID to match with the TB2 Bus
//
// Return Value:
//
// true: When the passed Dev ID match with TB2's BUS Device ID
// false: When the passed Dev ID is not matching with known TB2's
// BUS Device ID
//*****************************************************************************
EGPU_INLINE NvBool isTB2DeviceID(NvU16 deviceID)
{
NvU32 index;
NvU16 tb2DeviceIDList[]={ BUS_DEVICE_ID_TB2_FALCON_RIDGE_DSL5520_02,
BUS_DEVICE_ID_TB2_03, BUS_DEVICE_ID_TB2_04,
BUS_DEVICE_ID_TB2_05, BUS_DEVICE_ID_TB2_06,
BUS_DEVICE_ID_TB2_08, BUS_DEVICE_ID_TB2_09,
BUS_DEVICE_ID_TB2_10
};
for (index = 0; index < (sizeof(tb2DeviceIDList)/sizeof(NvU16)); index++)
{
if (deviceID == tb2DeviceIDList[index])
{
return NV_TRUE;
}
}
return NV_FALSE;
} // isTB2DeviceID
#ifdef __cplusplus
}
#endif
#endif //_NVEGPUCONFIG_H_

33
src/common/inc/nvhybridacpi.h
View File

@@ -68,6 +68,39 @@ extern "C"
#define NVHG_ERROR_UNSUPPORTED 0x80000002 // FunctionCode or SubFunctionCode not supported by this system
#define NVHG_ERROR_PARM_INVALID 0x80000003 // Parameter is invalid (i.e. start page beyond end of buffer)
// ****************************************************
// For MXDS Display Output Mux Control Method
// ****************************************************
#define MXDS_METHOD_GET_MUX_STATE 0x00000000
#define MXDS_METHOD_SET_DISP_MUX_TO_THISGPU 0x00000001
#define MXDS_METHOD_SET_BACKLIGHT_MUX_TO_THISGPU 0x00000002
#define MXDS_METHOD_SET_DISP_AND_BACKLIGHT_MUX_TO_THISGPU 0x00000003
// return buffer definitions
#define MXDS_METHOD_MUX_STATE_NOT_MUXED 0x00000000
#define MXDS_METHOD_MUX_STATE_IS_MUXED 0x00000001
//
// ACPI _MXDS (Switch DispMux state) specific defines
// These defines are as per the ACPI spec from Bug 2297713
//
#define MXDS_METHOD_MUX_OP 3:0
#define MXDS_METHOD_MUX_OP_GET 0x00000000
#define MXDS_METHOD_MUX_OP_SET 0x00000001
#define MXDS_METHOD_MUX_SET_MODE 4:4
#define MXDS_METHOD_MUX_SET_MODE_IGPU 0x00000000
#define MXDS_METHOD_MUX_SET_MODE_DGPU 0x00000001
//
// ACPI _LRST (LCD VDD force reset) specific defines
// These defines are as per the ACPI spec from NVIDIA
// DDS Partner Guidelines For Notebook (OEM Doc)
//
#define LRST_METHOD_FORCE_RESET_OP 2:0
#define LRST_METHOD_FORCE_RESET_OP_GET 0x00000000
#define LRST_METHOD_FORCE_RESET_OP_SET_LOW 0x00000001
#define LRST_METHOD_FORCE_RESET_OP_SET_HIGH 0x00000002
#if defined(__cplusplus)
} // extern "C"
#endif // defined(__cplusplus)

6
src/common/inc/nvlog_defs.h
View File

@@ -103,14 +103,8 @@ struct _NVLOG_BUFFER
#define NVLOG_MAX_BUFFERS_v11 16
#define NVLOG_MAX_BUFFERS_v12 256
#if NVOS_IS_UNIX
#define NVLOG_MAX_BUFFERS NVLOG_MAX_BUFFERS_v12
#define NVLOG_LOGGER_VERSION 12 // v1.2
#else
#define NVLOG_MAX_BUFFERS NVLOG_MAX_BUFFERS_v11
#define NVLOG_LOGGER_VERSION 11 // v1.1
#endif // NVOS_IS_UNIX
// Due to this file's peculiar location, NvPort may or may not be includable
typedef struct PORT_SPINLOCK PORT_SPINLOCK;

14
src/common/inc/swref/published/ada/ad102/dev_bus.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2022-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -28,6 +28,18 @@
#define NV_PBUS_SW_SCRATCH__SIZE_1 64 /* */
#define NV_PBUS_SW_SCRATCH_FIELD 31:0 /* RWIVF */
#define NV_PBUS_SW_SCRATCH_FIELD_INIT 0x00000000 /* RWI-V */
#define NV_PBUS_BAR1_BLOCK 0x00001704 /* RW-4R */
#define NV_PBUS_BAR1_BLOCK_MAP 29:0 /* */
#define NV_PBUS_BAR1_BLOCK_PTR 27:0 /* RWIUF */
#define NV_PBUS_BAR1_BLOCK_PTR_0 0x00000000 /* RWI-V */
#define NV_PBUS_BAR1_BLOCK_TARGET 29:28 /* RWIUF */
#define NV_PBUS_BAR1_BLOCK_TARGET_VID_MEM 0x00000000 /* RWI-V */
#define NV_PBUS_BAR1_BLOCK_TARGET_SYS_MEM_COHERENT 0x00000002 /* RW--V */
#define NV_PBUS_BAR1_BLOCK_TARGET_SYS_MEM_NONCOHERENT 0x00000003 /* RW--V */
#define NV_PBUS_BAR1_BLOCK_MODE 31:31 /* RWIUF */
#define NV_PBUS_BAR1_BLOCK_MODE_PHYSICAL 0x00000000 /* RWI-V */
#define NV_PBUS_BAR1_BLOCK_MODE_VIRTUAL 0x00000001 /* RW--V */
#define NV_PBUS_BAR1_BLOCK_PTR_SHIFT 12 /* */
#endif // ad102_dev_nv_bus_h

63
src/common/inc/swref/published/ada/ad102/dev_fault.h Normal file
View File

@@ -0,0 +1,63 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2023 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __ad102_dev_fault_h__
#define __ad102_dev_fault_h__
#define NV_PFAULT_MMU_ENG_ID_DISPLAY 1 /* */
#define NV_PFAULT_MMU_ENG_ID_IFB 9 /* */
#define NV_PFAULT_MMU_ENG_ID_FLA 4 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1 128 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2 192 /* */
#define NV_PFAULT_MMU_ENG_ID_SEC 14 /* */
#define NV_PFAULT_MMU_ENG_ID_PERF 8 /* */
#define NV_PFAULT_MMU_ENG_ID_NVDEC 25 /* */
#define NV_PFAULT_MMU_ENG_ID_NVDEC0 25 /* */
#define NV_PFAULT_MMU_ENG_ID_NVDEC1 26 /* */
#define NV_PFAULT_MMU_ENG_ID_NVDEC2 27 /* */
#define NV_PFAULT_MMU_ENG_ID_NVDEC3 28 /* */
#define NV_PFAULT_MMU_ENG_ID_NVDEC4 29 /* */
#define NV_PFAULT_MMU_ENG_ID_NVJPG0 21 /* */
#define NV_PFAULT_MMU_ENG_ID_NVJPG1 22 /* */
#define NV_PFAULT_MMU_ENG_ID_NVJPG2 23 /* */
#define NV_PFAULT_MMU_ENG_ID_NVJPG3 24 /* */
#define NV_PFAULT_MMU_ENG_ID_GRCOPY 15 /* */
#define NV_PFAULT_MMU_ENG_ID_CE0 15 /* */
#define NV_PFAULT_MMU_ENG_ID_CE1 16 /* */
#define NV_PFAULT_MMU_ENG_ID_CE2 17 /* */
#define NV_PFAULT_MMU_ENG_ID_CE3 18 /* */
#define NV_PFAULT_MMU_ENG_ID_CE4 19 /* */
#define NV_PFAULT_MMU_ENG_ID_CE5 20 /* */
#define NV_PFAULT_MMU_ENG_ID_PWR_PMU 6 /* */
#define NV_PFAULT_MMU_ENG_ID_PTP 3 /* */
#define NV_PFAULT_MMU_ENG_ID_NVENC0 11 /* */
#define NV_PFAULT_MMU_ENG_ID_NVENC1 12 /* */
#define NV_PFAULT_MMU_ENG_ID_NVENC2 13 /* */
#define NV_PFAULT_MMU_ENG_ID_OFA0 10 /* */
#define NV_PFAULT_MMU_ENG_ID_PHYSICAL 31 /* */
#define NV_PFAULT_CLIENT_HUB_NVJPG1 0x00000072 /* */
#define NV_PFAULT_CLIENT_HUB_NVJPG2 0x00000073 /* */
#define NV_PFAULT_CLIENT_HUB_NVJPG3 0x00000074 /* */
#endif // __ad102_dev_fault_h__

8
src/common/inc/swref/published/ampere/ga100/dev_boot.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES
* SPDX-FileCopyrightText: Copyright (c) 2003-2023 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -33,6 +33,12 @@
#define NV_PMC_ENABLE_NVDEC 15:15 /* */
#define NV_PMC_ENABLE_NVDEC_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_NVDEC_ENABLED 0x00000001 /* */
#define NV_PMC_ENABLE_PERFMON 28:28 /* RWIVF */
#define NV_PMC_ENABLE_PERFMON_DISABLED 0x00000000 /* RWI-V */
#define NV_PMC_ENABLE_PERFMON_ENABLED 0x00000001 /* RW--V */
#define NV_PMC_ENABLE_PDISP 30:30 /* RWIVF */
#define NV_PMC_ENABLE_PDISP_DISABLED 0x00000000 /* RW--V */
#define NV_PMC_ENABLE_PDISP_ENABLED 0x00000001 /* RWI-V */
#define NV_PMC_DEVICE_ENABLE(i) (0x000000600+(i)*4) /* RW-4A */
#define NV_PMC_DEVICE_ENABLE__SIZE_1 1 /* */
#define NV_PMC_DEVICE_ENABLE__PRIV_LEVEL_MASK 0x00000084 /* */

14
src/common/inc/swref/published/ampere/ga100/dev_bus.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES
* SPDX-FileCopyrightText: Copyright (c) 2022-2023 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -28,5 +28,17 @@
#define NV_PBUS_SW_SCRATCH__SIZE_1 64 /* */
#define NV_PBUS_SW_SCRATCH_FIELD 31:0 /* RWIVF */
#define NV_PBUS_SW_SCRATCH_FIELD_INIT 0x00000000 /* RWI-V */
#define NV_PBUS_BAR1_BLOCK 0x00001704 /* RW-4R */
#define NV_PBUS_BAR1_BLOCK_MAP 29:0 /* */
#define NV_PBUS_BAR1_BLOCK_PTR 27:0 /* RWIUF */
#define NV_PBUS_BAR1_BLOCK_PTR_0 0x00000000 /* RWI-V */
#define NV_PBUS_BAR1_BLOCK_TARGET 29:28 /* RWIUF */
#define NV_PBUS_BAR1_BLOCK_TARGET_VID_MEM 0x00000000 /* RWI-V */
#define NV_PBUS_BAR1_BLOCK_TARGET_SYS_MEM_COHERENT 0x00000002 /* RW--V */
#define NV_PBUS_BAR1_BLOCK_TARGET_SYS_MEM_NONCOHERENT 0x00000003 /* RW--V */
#define NV_PBUS_BAR1_BLOCK_MODE 31:31 /* RWIUF */
#define NV_PBUS_BAR1_BLOCK_MODE_PHYSICAL 0x00000000 /* RWI-V */
#define NV_PBUS_BAR1_BLOCK_MODE_VIRTUAL 0x00000001 /* RW--V */
#define NV_PBUS_BAR1_BLOCK_PTR_SHIFT 12 /* */
#endif // ga100_dev_nv_bus_h

206
src/common/inc/swref/published/ampere/ga100/dev_fault.h Normal file
View File

@@ -0,0 +1,206 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2023 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __ga100_dev_fault_h__
#define __ga100_dev_fault_h__
#define NV_PFAULT_MMU_ENG_ID_DISPLAY 1 /* */
#define NV_PFAULT_MMU_ENG_ID_IFB 9 /* */
#define NV_PFAULT_MMU_ENG_ID_FLA 4 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1 128 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2 192 /* */
#define NV_PFAULT_MMU_ENG_ID_SEC 14 /* */
#define NV_PFAULT_MMU_ENG_ID_PERF 8 /* */
#define NV_PFAULT_MMU_ENG_ID_NVDEC 25 /* */
#define NV_PFAULT_MMU_ENG_ID_NVDEC0 25 /* */
#define NV_PFAULT_MMU_ENG_ID_NVDEC1 26 /* */
#define NV_PFAULT_MMU_ENG_ID_NVDEC2 27 /* */
#define NV_PFAULT_MMU_ENG_ID_NVDEC3 28 /* */
#define NV_PFAULT_MMU_ENG_ID_NVDEC4 29 /* */
#define NV_PFAULT_MMU_ENG_ID_NVJPG0 30 /* */
#define NV_PFAULT_MMU_ENG_ID_GRCOPY 15 /* */
#define NV_PFAULT_MMU_ENG_ID_CE0 15 /* */
#define NV_PFAULT_MMU_ENG_ID_CE1 16 /* */
#define NV_PFAULT_MMU_ENG_ID_CE2 17 /* */
#define NV_PFAULT_MMU_ENG_ID_CE3 18 /* */
#define NV_PFAULT_MMU_ENG_ID_CE4 19 /* */
#define NV_PFAULT_MMU_ENG_ID_CE5 20 /* */
#define NV_PFAULT_MMU_ENG_ID_CE6 21 /* */
#define NV_PFAULT_MMU_ENG_ID_CE7 22 /* */
#define NV_PFAULT_MMU_ENG_ID_CE8 23 /* */
#define NV_PFAULT_MMU_ENG_ID_CE9 24 /* */
#define NV_PFAULT_MMU_ENG_ID_PWR_PMU 6 /* */
#define NV_PFAULT_MMU_ENG_ID_PTP 3 /* */
#define NV_PFAULT_MMU_ENG_ID_NVENC0 11 /* */
#define NV_PFAULT_MMU_ENG_ID_NVENC1 12 /* */
#define NV_PFAULT_MMU_ENG_ID_NVENC2 13 /* */
#define NV_PFAULT_MMU_ENG_ID_OFA0 10 /* */
#define NV_PFAULT_MMU_ENG_ID_PHYSICAL 31 /* */
#define NV_PFAULT_FAULT_TYPE_UNBOUND_INST_BLOCK 0x00000004 /* */
#define NV_PFAULT_CLIENT_GPC_T1_0 0x00000000 /* */
#define NV_PFAULT_CLIENT_GPC_T1_1 0x00000001 /* */
#define NV_PFAULT_CLIENT_GPC_T1_2 0x00000002 /* */
#define NV_PFAULT_CLIENT_GPC_T1_3 0x00000003 /* */
#define NV_PFAULT_CLIENT_GPC_T1_4 0x00000004 /* */
#define NV_PFAULT_CLIENT_GPC_T1_5 0x00000005 /* */
#define NV_PFAULT_CLIENT_GPC_T1_6 0x00000006 /* */
#define NV_PFAULT_CLIENT_GPC_T1_7 0x00000007 /* */
#define NV_PFAULT_CLIENT_GPC_PE_0 0x00000008 /* */
#define NV_PFAULT_CLIENT_GPC_PE_1 0x00000009 /* */
#define NV_PFAULT_CLIENT_GPC_PE_2 0x0000000A /* */
#define NV_PFAULT_CLIENT_GPC_PE_3 0x0000000B /* */
#define NV_PFAULT_CLIENT_GPC_PE_4 0x0000000C /* */
#define NV_PFAULT_CLIENT_GPC_PE_5 0x0000000D /* */
#define NV_PFAULT_CLIENT_GPC_PE_6 0x0000000E /* */
#define NV_PFAULT_CLIENT_GPC_PE_7 0x0000000F /* */
#define NV_PFAULT_CLIENT_GPC_RAST 0x00000010 /* */
#define NV_PFAULT_CLIENT_GPC_GCC 0x00000011 /* */
#define NV_PFAULT_CLIENT_GPC_GPCCS 0x00000012 /* */
#define NV_PFAULT_CLIENT_GPC_PROP_0 0x00000013 /* */
#define NV_PFAULT_CLIENT_GPC_PROP_1 0x00000014 /* */
#define NV_PFAULT_CLIENT_GPC_T1_8 0x00000021 /* */
#define NV_PFAULT_CLIENT_GPC_T1_9 0x00000022 /* */
#define NV_PFAULT_CLIENT_GPC_T1_10 0x00000023 /* */
#define NV_PFAULT_CLIENT_GPC_T1_11 0x00000024 /* */
#define NV_PFAULT_CLIENT_GPC_T1_12 0x00000025 /* */
#define NV_PFAULT_CLIENT_GPC_T1_13 0x00000026 /* */
#define NV_PFAULT_CLIENT_GPC_T1_14 0x00000027 /* */
#define NV_PFAULT_CLIENT_GPC_T1_15 0x00000028 /* */
#define NV_PFAULT_CLIENT_GPC_TPCCS_0 0x00000029 /* */
#define NV_PFAULT_CLIENT_GPC_TPCCS_1 0x0000002A /* */
#define NV_PFAULT_CLIENT_GPC_TPCCS_2 0x0000002B /* */
#define NV_PFAULT_CLIENT_GPC_TPCCS_3 0x0000002C /* */
#define NV_PFAULT_CLIENT_GPC_TPCCS_4 0x0000002D /* */
#define NV_PFAULT_CLIENT_GPC_TPCCS_5 0x0000002E /* */
#define NV_PFAULT_CLIENT_GPC_TPCCS_6 0x0000002F /* */
#define NV_PFAULT_CLIENT_GPC_TPCCS_7 0x00000030 /* */
#define NV_PFAULT_CLIENT_GPC_PE_8 0x00000031 /* */
#define NV_PFAULT_CLIENT_GPC_TPCCS_8 0x00000033 /* */
#define NV_PFAULT_CLIENT_GPC_T1_16 0x00000035 /* */
#define NV_PFAULT_CLIENT_GPC_T1_17 0x00000036 /* */
#define NV_PFAULT_CLIENT_GPC_ROP_0 0x00000070 /* */
#define NV_PFAULT_CLIENT_GPC_ROP_1 0x00000071 /* */
#define NV_PFAULT_CLIENT_GPC_GPM 0x00000017 /* */
#define NV_PFAULT_CLIENT_HUB_VIP 0x00000000 /* */
#define NV_PFAULT_CLIENT_HUB_CE0 0x00000001 /* */
#define NV_PFAULT_CLIENT_HUB_CE1 0x00000002 /* */
#define NV_PFAULT_CLIENT_HUB_DNISO 0x00000003 /* */
#define NV_PFAULT_CLIENT_HUB_DISPNISO 0x00000003 /* */
#define NV_PFAULT_CLIENT_HUB_FE0 0x00000004 /* */
#define NV_PFAULT_CLIENT_HUB_FE 0x00000004 /* */
#define NV_PFAULT_CLIENT_HUB_FECS0 0x00000005 /* */
#define NV_PFAULT_CLIENT_HUB_FECS 0x00000005 /* */
#define NV_PFAULT_CLIENT_HUB_HOST 0x00000006 /* */
#define NV_PFAULT_CLIENT_HUB_HOST_CPU 0x00000007 /* */
#define NV_PFAULT_CLIENT_HUB_HOST_CPU_NB 0x00000008 /* */
#define NV_PFAULT_CLIENT_HUB_ISO 0x00000009 /* */
#define NV_PFAULT_CLIENT_HUB_MMU 0x0000000A /* */
#define NV_PFAULT_CLIENT_HUB_NVDEC0 0x0000000B /* */
#define NV_PFAULT_CLIENT_HUB_NVDEC 0x0000000B /* */
#define NV_PFAULT_CLIENT_HUB_NVENC1 0x0000000D /* */
#define NV_PFAULT_CLIENT_HUB_NISO 0x0000000E /* */
#define NV_PFAULT_CLIENT_HUB_ACTRS 0x0000000E /* */
#define NV_PFAULT_CLIENT_HUB_P2P 0x0000000F /* */
#define NV_PFAULT_CLIENT_HUB_PD 0x00000010 /* */
#define NV_PFAULT_CLIENT_HUB_PERF0 0x00000011 /* */
#define NV_PFAULT_CLIENT_HUB_PERF 0x00000011 /* */
#define NV_PFAULT_CLIENT_HUB_PMU 0x00000012 /* */
#define NV_PFAULT_CLIENT_HUB_RASTERTWOD 0x00000013 /* */
#define NV_PFAULT_CLIENT_HUB_SCC 0x00000014 /* */
#define NV_PFAULT_CLIENT_HUB_SCC_NB 0x00000015 /* */
#define NV_PFAULT_CLIENT_HUB_SEC 0x00000016 /* */
#define NV_PFAULT_CLIENT_HUB_SSYNC 0x00000017 /* */
#define NV_PFAULT_CLIENT_HUB_GRCOPY 0x00000018 /* */
#define NV_PFAULT_CLIENT_HUB_CE2 0x00000018 /* */
#define NV_PFAULT_CLIENT_HUB_XV 0x00000019 /* */
#define NV_PFAULT_CLIENT_HUB_MMU_NB 0x0000001A /* */
#define NV_PFAULT_CLIENT_HUB_NVENC0 0x0000001B /* */
#define NV_PFAULT_CLIENT_HUB_NVENC 0x0000001B /* */
#define NV_PFAULT_CLIENT_HUB_DFALCON 0x0000001C /* */
#define NV_PFAULT_CLIENT_HUB_SKED0 0x0000001D /* */
#define NV_PFAULT_CLIENT_HUB_SKED 0x0000001D /* */
#define NV_PFAULT_CLIENT_HUB_AFALCON 0x0000001E /* */
#define NV_PFAULT_CLIENT_HUB_DONT_CARE 0x0000001F /* */
#define NV_PFAULT_CLIENT_HUB_HSCE0 0x00000020 /* */
#define NV_PFAULT_CLIENT_HUB_HSCE1 0x00000021 /* */
#define NV_PFAULT_CLIENT_HUB_HSCE2 0x00000022 /* */
#define NV_PFAULT_CLIENT_HUB_HSCE3 0x00000023 /* */
#define NV_PFAULT_CLIENT_HUB_HSCE4 0x00000024 /* */
#define NV_PFAULT_CLIENT_HUB_HSCE5 0x00000025 /* */
#define NV_PFAULT_CLIENT_HUB_HSCE6 0x00000026 /* */
#define NV_PFAULT_CLIENT_HUB_HSCE7 0x00000027 /* */
#define NV_PFAULT_CLIENT_HUB_HSCE8 0x00000028 /* */
#define NV_PFAULT_CLIENT_HUB_HSCE9 0x00000029 /* */
#define NV_PFAULT_CLIENT_HUB_HSHUB 0x0000002A /* */
#define NV_PFAULT_CLIENT_HUB_PTP_X0 0x0000002B /* */
#define NV_PFAULT_CLIENT_HUB_PTP_X1 0x0000002C /* */
#define NV_PFAULT_CLIENT_HUB_PTP_X2 0x0000002D /* */
#define NV_PFAULT_CLIENT_HUB_PTP_X3 0x0000002E /* */
#define NV_PFAULT_CLIENT_HUB_PTP_X4 0x0000002F /* */
#define NV_PFAULT_CLIENT_HUB_PTP_X5 0x00000030 /* */
#define NV_PFAULT_CLIENT_HUB_NVENC2 0x00000033 /* */
#define NV_PFAULT_CLIENT_HUB_VPR_SCRUBBER0 0x00000034 /* */
#define NV_PFAULT_CLIENT_HUB_VPR_SCRUBBER1 0x00000035 /* */
#define NV_PFAULT_CLIENT_HUB_DWBIF 0x00000036 /* */
#define NV_PFAULT_CLIENT_HUB_FBFALCON 0x00000037 /* */
#define NV_PFAULT_CLIENT_HUB_CE_SHIM 0x00000038 /* */
#define NV_PFAULT_CLIENT_HUB_GSP 0x00000039 /* */
#define NV_PFAULT_CLIENT_HUB_NVDEC1 0x0000003A /* */
#define NV_PFAULT_CLIENT_HUB_NVDEC2 0x0000003B /* */
#define NV_PFAULT_CLIENT_HUB_NVJPG0 0x0000003C /* */
#define NV_PFAULT_CLIENT_HUB_NVDEC3 0x0000003D /* */
#define NV_PFAULT_CLIENT_HUB_NVDEC4 0x0000003E /* */
#define NV_PFAULT_CLIENT_HUB_OFA0 0x0000003F /* */
#define NV_PFAULT_CLIENT_HUB_HSCE10 0x00000040 /* */
#define NV_PFAULT_CLIENT_HUB_HSCE11 0x00000041 /* */
#define NV_PFAULT_CLIENT_HUB_HSCE12 0x00000042 /* */
#define NV_PFAULT_CLIENT_HUB_HSCE13 0x00000043 /* */
#define NV_PFAULT_CLIENT_HUB_HSCE14 0x00000044 /* */
#define NV_PFAULT_CLIENT_HUB_HSCE15 0x00000045 /* */
#define NV_PFAULT_CLIENT_HUB_FE1 0x0000004E /* */
#define NV_PFAULT_CLIENT_HUB_FE2 0x0000004F /* */
#define NV_PFAULT_CLIENT_HUB_FE3 0x00000050 /* */
#define NV_PFAULT_CLIENT_HUB_FE4 0x00000051 /* */
#define NV_PFAULT_CLIENT_HUB_FE5 0x00000052 /* */
#define NV_PFAULT_CLIENT_HUB_FE6 0x00000053 /* */
#define NV_PFAULT_CLIENT_HUB_FE7 0x00000054 /* */
#define NV_PFAULT_CLIENT_HUB_FECS1 0x00000055 /* */
#define NV_PFAULT_CLIENT_HUB_FECS2 0x00000056 /* */
#define NV_PFAULT_CLIENT_HUB_FECS3 0x00000057 /* */
#define NV_PFAULT_CLIENT_HUB_FECS4 0x00000058 /* */
#define NV_PFAULT_CLIENT_HUB_FECS5 0x00000059 /* */
#define NV_PFAULT_CLIENT_HUB_FECS6 0x0000005A /* */
#define NV_PFAULT_CLIENT_HUB_FECS7 0x0000005B /* */
#define NV_PFAULT_CLIENT_HUB_SKED1 0x0000005C /* */
#define NV_PFAULT_CLIENT_HUB_SKED2 0x0000005D /* */
#define NV_PFAULT_CLIENT_HUB_SKED3 0x0000005E /* */
#define NV_PFAULT_CLIENT_HUB_SKED4 0x0000005F /* */
#define NV_PFAULT_CLIENT_HUB_SKED5 0x00000060 /* */
#define NV_PFAULT_CLIENT_HUB_SKED6 0x00000061 /* */
#define NV_PFAULT_CLIENT_HUB_SKED7 0x00000062 /* */
#define NV_PFAULT_CLIENT_HUB_ESC 0x00000063 /* */
#endif // __ga100_dev_fault_h__

28
src/common/inc/swref/published/ampere/ga100/hwproject.h Normal file
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@@ -0,0 +1,28 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __ga100_hwproject_h__
#define __ga100_hwproject_h__
#define NV_SCAL_LITTER_NUM_FBPAS 24
#endif // __ga100_hwproject_h__

1
src/common/inc/swref/published/ampere/ga102/dev_vm.h
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@@ -61,4 +61,5 @@
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF_TRIGGER 0x00001640 /* -W-4R */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF_TRIGGER_VECTOR 11:0 /* -WXVF */
#define NV_VIRTUAL_FUNCTION_PRIV_DOORBELL 0x2200 /* -W-4R */
#define NV_VIRTUAL_FUNCTION_PRIV_MAILBOX_SCRATCH(i) (0x2100+(i)*4) /* RW-4A */
#endif // __ga102_dev_vm_h__

32
src/common/inc/swref/published/hopper/gh100/dev_bus.h Normal file
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@@ -0,0 +1,32 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef gh100_dev_nv_bus_h
#define gh100_dev_nv_bus_h
#define NV_PBUS_SW_SCRATCH(i) (0x00001400+(i)*4) /* RW-4A */
#define NV_PBUS_SW_SCRATCH__SIZE_1 64 /* */
#define NV_PBUS_SW_SCRATCH_FIELD 31:0 /* RWIVF */
#define NV_PBUS_SW_SCRATCH_FIELD_INIT 0x00000000 /* RWI-V */
#endif // gh100_dev_nv_bus_h

47
src/common/inc/swref/published/hopper/gh100/dev_bus_addendum.h Normal file
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@@ -0,0 +1,47 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef gh100_dev_nv_bus_addendum_h
#define gh100_dev_nv_bus_addendum_h
/*!
* @defgroup FRTS_INSECURE_SCRATCH_REGISTERS
*
* Used to communicate the location/size of insecure FRTS
*
* @{
*/
#define NV_PBUS_SW_FRTS_INSECURE_ADDR_LO32 NV_PBUS_SW_SCRATCH(0x3D)
#define NV_PBUS_SW_FRTS_INSECURE_ADDR_HI32 NV_PBUS_SW_SCRATCH(0x3E)
#define NV_PBUS_SW_FRTS_INSECURE_CONFIG NV_PBUS_SW_SCRATCH(0x3F)
#define NV_PBUS_SW_FRTS_INSECURE_CONFIG_SIZE_4K 15U:0U
#define NV_PBUS_SW_FRTS_INSECURE_CONFIG_SIZE_4K_INVALID 0x0000
#define NV_PBUS_SW_FRTS_INSECURE_CONFIG_SIZE_4K_SHIFT 12U
#define NV_PBUS_SW_FRTS_INSECURE_CONFIG_MEDIA_TYPE 16U:16U
#define NV_PBUS_SW_FRTS_INSECURE_CONFIG_MEDIA_TYPE_FB 0U
#define NV_PBUS_SW_FRTS_INSECURE_CONFIG_MEDIA_TYPE_SYSMEM 1U
/*!@}*/
#endif // gh100_dev_nv_bus_addendum_h

181
src/common/inc/swref/published/hopper/gh100/dev_fault.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES
* SPDX-FileCopyrightText: Copyright (c) 2003-2023 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -24,6 +24,183 @@
#ifndef __gh100_dev_fault_h__
#define __gh100_dev_fault_h__
#define NV_PFAULT_MMU_ENG_ID_GRAPHICS 384 /* */
#define NV_PFAULT_MMU_ENG_ID_GRAPHICS 384 /* */
#define NV_PFAULT_MMU_ENG_ID_DISPLAY 1 /* */
#define NV_PFAULT_MMU_ENG_ID_GSP 2 /* */
#define NV_PFAULT_MMU_ENG_ID_FLA 4 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1 256 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2 320 /* */
#define NV_PFAULT_MMU_ENG_ID_FSP 7 /* */
#define NV_PFAULT_MMU_ENG_ID_PERF 10 /* */
#define NV_PFAULT_MMU_ENG_ID_PERF0 10 /* */
#define NV_PFAULT_MMU_ENG_ID_PWR_PMU 5 /* */
#define NV_PFAULT_MMU_ENG_ID_PTP 3 /* */
#define NV_PFAULT_MMU_ENG_ID_PHYSICAL 56 /* */
#define NV_PFAULT_MMU_ENG_ID_CE0 43 /* */
#define NV_PFAULT_MMU_ENG_ID_CE1 44 /* */
#define NV_PFAULT_MMU_ENG_ID_CE2 45 /* */
#define NV_PFAULT_MMU_ENG_ID_CE3 46 /* */
#define NV_PFAULT_MMU_ENG_ID_CE4 47 /* */
#define NV_PFAULT_MMU_ENG_ID_CE5 48 /* */
#define NV_PFAULT_MMU_ENG_ID_CE6 49 /* */
#define NV_PFAULT_MMU_ENG_ID_CE7 50 /* */
#define NV_PFAULT_MMU_ENG_ID_CE8 51 /* */
#define NV_PFAULT_MMU_ENG_ID_CE9 52 /* */
#define NV_PFAULT_CLIENT_GPC_T1_0 0x00000000 /* */
#define NV_PFAULT_CLIENT_GPC_T1_1 0x00000001 /* */
#define NV_PFAULT_CLIENT_GPC_T1_2 0x00000002 /* */
#define NV_PFAULT_CLIENT_GPC_T1_3 0x00000003 /* */
#define NV_PFAULT_CLIENT_GPC_T1_4 0x00000004 /* */
#define NV_PFAULT_CLIENT_GPC_T1_5 0x00000005 /* */
#define NV_PFAULT_CLIENT_GPC_T1_6 0x00000006 /* */
#define NV_PFAULT_CLIENT_GPC_T1_7 0x00000007 /* */
#define NV_PFAULT_CLIENT_GPC_PE_0 0x00000008 /* */
#define NV_PFAULT_CLIENT_GPC_PE_1 0x00000009 /* */
#define NV_PFAULT_CLIENT_GPC_PE_2 0x0000000A /* */
#define NV_PFAULT_CLIENT_GPC_PE_3 0x0000000B /* */
#define NV_PFAULT_CLIENT_GPC_PE_4 0x0000000C /* */
#define NV_PFAULT_CLIENT_GPC_PE_5 0x0000000D /* */
#define NV_PFAULT_CLIENT_GPC_PE_6 0x0000000E /* */
#define NV_PFAULT_CLIENT_GPC_PE_7 0x0000000F /* */
#define NV_PFAULT_CLIENT_GPC_RAST 0x00000010 /* */
#define NV_PFAULT_CLIENT_GPC_GCC 0x00000011 /* */
#define NV_PFAULT_CLIENT_GPC_GPCCS 0x00000012 /* */
#define NV_PFAULT_CLIENT_GPC_PROP_0 0x00000013 /* */
#define NV_PFAULT_CLIENT_GPC_PROP_1 0x00000014 /* */
#define NV_PFAULT_CLIENT_GPC_T1_8 0x00000021 /* */
#define NV_PFAULT_CLIENT_GPC_T1_9 0x00000022 /* */
#define NV_PFAULT_CLIENT_GPC_T1_10 0x00000023 /* */
#define NV_PFAULT_CLIENT_GPC_T1_11 0x00000024 /* */
#define NV_PFAULT_CLIENT_GPC_T1_12 0x00000025 /* */
#define NV_PFAULT_CLIENT_GPC_T1_13 0x00000026 /* */
#define NV_PFAULT_CLIENT_GPC_T1_14 0x00000027 /* */
#define NV_PFAULT_CLIENT_GPC_T1_15 0x00000028 /* */
#define NV_PFAULT_CLIENT_GPC_TPCCS_0 0x00000029 /* */
#define NV_PFAULT_CLIENT_GPC_TPCCS_1 0x0000002A /* */
#define NV_PFAULT_CLIENT_GPC_TPCCS_2 0x0000002B /* */
#define NV_PFAULT_CLIENT_GPC_TPCCS_3 0x0000002C /* */
#define NV_PFAULT_CLIENT_GPC_TPCCS_4 0x0000002D /* */
#define NV_PFAULT_CLIENT_GPC_TPCCS_5 0x0000002E /* */
#define NV_PFAULT_CLIENT_GPC_TPCCS_6 0x0000002F /* */
#define NV_PFAULT_CLIENT_GPC_TPCCS_7 0x00000030 /* */
#define NV_PFAULT_CLIENT_GPC_PE_8 0x00000031 /* */
#define NV_PFAULT_CLIENT_GPC_TPCCS_8 0x00000033 /* */
#define NV_PFAULT_CLIENT_GPC_T1_16 0x00000035 /* */
#define NV_PFAULT_CLIENT_GPC_T1_17 0x00000036 /* */
#define NV_PFAULT_CLIENT_GPC_ROP_0 0x00000070 /* */
#define NV_PFAULT_CLIENT_GPC_ROP_1 0x00000071 /* */
#define NV_PFAULT_CLIENT_GPC_GPM 0x00000017 /* */
#define NV_PFAULT_CLIENT_HUB_VIP 0x00000000 /* */
#define NV_PFAULT_CLIENT_HUB_CE0 0x00000001 /* */
#define NV_PFAULT_CLIENT_HUB_CE1 0x00000002 /* */
#define NV_PFAULT_CLIENT_HUB_DNISO 0x00000003 /* */
#define NV_PFAULT_CLIENT_HUB_DISPNISO 0x00000003 /* */
#define NV_PFAULT_CLIENT_HUB_FE0 0x00000004 /* */
#define NV_PFAULT_CLIENT_HUB_FE 0x00000004 /* */
#define NV_PFAULT_CLIENT_HUB_FECS0 0x00000005 /* */
#define NV_PFAULT_CLIENT_HUB_FECS 0x00000005 /* */
#define NV_PFAULT_CLIENT_HUB_HOST 0x00000006 /* */
#define NV_PFAULT_CLIENT_HUB_HOST_CPU 0x00000007 /* */
#define NV_PFAULT_CLIENT_HUB_HOST_CPU_NB 0x00000008 /* */
#define NV_PFAULT_CLIENT_HUB_ISO 0x00000009 /* */
#define NV_PFAULT_CLIENT_HUB_MMU 0x0000000A /* */
#define NV_PFAULT_CLIENT_HUB_NVDEC0 0x0000000B /* */
#define NV_PFAULT_CLIENT_HUB_NVDEC 0x0000000B /* */
#define NV_PFAULT_CLIENT_HUB_CE3 0x0000000C /* */
#define NV_PFAULT_CLIENT_HUB_NVENC1 0x0000000D /* */
#define NV_PFAULT_CLIENT_HUB_NISO 0x0000000E /* */
#define NV_PFAULT_CLIENT_HUB_ACTRS 0x0000000E /* */
#define NV_PFAULT_CLIENT_HUB_P2P 0x0000000F /* */
#define NV_PFAULT_CLIENT_HUB_PD 0x00000010 /* */
#define NV_PFAULT_CLIENT_HUB_PERF0 0x00000011 /* */
#define NV_PFAULT_CLIENT_HUB_PERF 0x00000011 /* */
#define NV_PFAULT_CLIENT_HUB_PMU 0x00000012 /* */
#define NV_PFAULT_CLIENT_HUB_RASTERTWOD 0x00000013 /* */
#define NV_PFAULT_CLIENT_HUB_SCC 0x00000014 /* */
#define NV_PFAULT_CLIENT_HUB_SCC_NB 0x00000015 /* */
#define NV_PFAULT_CLIENT_HUB_SEC 0x00000016 /* */
#define NV_PFAULT_CLIENT_HUB_SSYNC 0x00000017 /* */
#define NV_PFAULT_CLIENT_HUB_GRCOPY 0x00000018 /* */
#define NV_PFAULT_CLIENT_HUB_CE2 0x00000018 /* */
#define NV_PFAULT_CLIENT_HUB_XV 0x00000019 /* */
#define NV_PFAULT_CLIENT_HUB_MMU_NB 0x0000001A /* */
#define NV_PFAULT_CLIENT_HUB_NVENC0 0x0000001B /* */
#define NV_PFAULT_CLIENT_HUB_NVENC 0x0000001B /* */
#define NV_PFAULT_CLIENT_HUB_DFALCON 0x0000001C /* */
#define NV_PFAULT_CLIENT_HUB_SKED0 0x0000001D /* */
#define NV_PFAULT_CLIENT_HUB_SKED 0x0000001D /* */
#define NV_PFAULT_CLIENT_HUB_AFALCON 0x0000001E /* */
#define NV_PFAULT_CLIENT_HUB_DONT_CARE 0x0000001F /* */
#define NV_PFAULT_CLIENT_HUB_HSCE0 0x00000020 /* */
#define NV_PFAULT_CLIENT_HUB_HSCE1 0x00000021 /* */
#define NV_PFAULT_CLIENT_HUB_HSCE2 0x00000022 /* */
#define NV_PFAULT_CLIENT_HUB_HSCE3 0x00000023 /* */
#define NV_PFAULT_CLIENT_HUB_HSCE4 0x00000024 /* */
#define NV_PFAULT_CLIENT_HUB_HSCE5 0x00000025 /* */
#define NV_PFAULT_CLIENT_HUB_HSCE6 0x00000026 /* */
#define NV_PFAULT_CLIENT_HUB_HSCE7 0x00000027 /* */
#define NV_PFAULT_CLIENT_HUB_HSCE8 0x00000028 /* */
#define NV_PFAULT_CLIENT_HUB_HSCE9 0x00000029 /* */
#define NV_PFAULT_CLIENT_HUB_HSHUB 0x0000002A /* */
#define NV_PFAULT_CLIENT_HUB_PTP_X0 0x0000002B /* */
#define NV_PFAULT_CLIENT_HUB_PTP_X1 0x0000002C /* */
#define NV_PFAULT_CLIENT_HUB_PTP_X2 0x0000002D /* */
#define NV_PFAULT_CLIENT_HUB_PTP_X3 0x0000002E /* */
#define NV_PFAULT_CLIENT_HUB_PTP_X4 0x0000002F /* */
#define NV_PFAULT_CLIENT_HUB_PTP_X5 0x00000030 /* */
#define NV_PFAULT_CLIENT_HUB_NVENC2 0x00000033 /* */
#define NV_PFAULT_CLIENT_HUB_VPR_SCRUBBER0 0x00000034 /* */
#define NV_PFAULT_CLIENT_HUB_VPR_SCRUBBER1 0x00000035 /* */
#define NV_PFAULT_CLIENT_HUB_DWBIF 0x00000036 /* */
#define NV_PFAULT_CLIENT_HUB_FBFALCON 0x00000037 /* */
#define NV_PFAULT_CLIENT_HUB_CE_SHIM 0x00000038 /* */
#define NV_PFAULT_CLIENT_HUB_GSP 0x00000039 /* */
#define NV_PFAULT_CLIENT_HUB_NVDEC1 0x0000003A /* */
#define NV_PFAULT_CLIENT_HUB_NVDEC2 0x0000003B /* */
#define NV_PFAULT_CLIENT_HUB_NVJPG0 0x0000003C /* */
#define NV_PFAULT_CLIENT_HUB_NVDEC3 0x0000003D /* */
#define NV_PFAULT_CLIENT_HUB_NVDEC4 0x0000003E /* */
#define NV_PFAULT_CLIENT_HUB_OFA0 0x0000003F /* */
#define NV_PFAULT_CLIENT_HUB_HSCE10 0x00000040 /* */
#define NV_PFAULT_CLIENT_HUB_HSCE11 0x00000041 /* */
#define NV_PFAULT_CLIENT_HUB_HSCE12 0x00000042 /* */
#define NV_PFAULT_CLIENT_HUB_HSCE13 0x00000043 /* */
#define NV_PFAULT_CLIENT_HUB_HSCE14 0x00000044 /* */
#define NV_PFAULT_CLIENT_HUB_HSCE15 0x00000045 /* */
#define NV_PFAULT_CLIENT_HUB_FE1 0x0000004E /* */
#define NV_PFAULT_CLIENT_HUB_FE2 0x0000004F /* */
#define NV_PFAULT_CLIENT_HUB_FE3 0x00000050 /* */
#define NV_PFAULT_CLIENT_HUB_FE4 0x00000051 /* */
#define NV_PFAULT_CLIENT_HUB_FE5 0x00000052 /* */
#define NV_PFAULT_CLIENT_HUB_FE6 0x00000053 /* */
#define NV_PFAULT_CLIENT_HUB_FE7 0x00000054 /* */
#define NV_PFAULT_CLIENT_HUB_FECS1 0x00000055 /* */
#define NV_PFAULT_CLIENT_HUB_FECS2 0x00000056 /* */
#define NV_PFAULT_CLIENT_HUB_FECS3 0x00000057 /* */
#define NV_PFAULT_CLIENT_HUB_FECS4 0x00000058 /* */
#define NV_PFAULT_CLIENT_HUB_FECS5 0x00000059 /* */
#define NV_PFAULT_CLIENT_HUB_FECS6 0x0000005A /* */
#define NV_PFAULT_CLIENT_HUB_FECS7 0x0000005B /* */
#define NV_PFAULT_CLIENT_HUB_SKED1 0x0000005C /* */
#define NV_PFAULT_CLIENT_HUB_SKED2 0x0000005D /* */
#define NV_PFAULT_CLIENT_HUB_SKED3 0x0000005E /* */
#define NV_PFAULT_CLIENT_HUB_SKED4 0x0000005F /* */
#define NV_PFAULT_CLIENT_HUB_SKED5 0x00000060 /* */
#define NV_PFAULT_CLIENT_HUB_SKED6 0x00000061 /* */
#define NV_PFAULT_CLIENT_HUB_SKED7 0x00000062 /* */
#define NV_PFAULT_CLIENT_HUB_ESC 0x00000063 /* */
#define NV_PFAULT_CLIENT_HUB_NVDEC5 0x0000006F /* */
#define NV_PFAULT_CLIENT_HUB_NVDEC6 0x00000070 /* */
#define NV_PFAULT_CLIENT_HUB_NVDEC7 0x00000071 /* */
#define NV_PFAULT_CLIENT_HUB_NVJPG1 0x00000072 /* */
#define NV_PFAULT_CLIENT_HUB_NVJPG2 0x00000073 /* */
#define NV_PFAULT_CLIENT_HUB_NVJPG3 0x00000074 /* */
#define NV_PFAULT_CLIENT_HUB_NVJPG4 0x00000075 /* */
#define NV_PFAULT_CLIENT_HUB_NVJPG5 0x00000076 /* */
#define NV_PFAULT_CLIENT_HUB_NVJPG6 0x00000077 /* */
#define NV_PFAULT_CLIENT_HUB_NVJPG7 0x00000078 /* */
#define NV_PFAULT_CLIENT_HUB_FSP 0x00000079 /* */
#endif // __gh100_dev_fault_h__

20
src/common/inc/swref/published/hopper/gh100/dev_fb.h
View File

@@ -30,24 +30,4 @@
#define NV_PFB_FBHUB_PCIE_FLUSH_SYSMEM_ADDR_HI_ADR 31:0 /* RWIVF */
#define NV_PFB_FBHUB_PCIE_FLUSH_SYSMEM_ADDR_HI_ADR_MASK 0x000FFFFF /* ----V */
#define NV_PFB_PRI_MMU_L2TLB_ECC_UNCORRECTED_ERR_COUNT 0x00100E78 /* RW-4R */
#define NV_PFB_PRI_MMU_L2TLB_ECC_UNCORRECTED_ERR_COUNT 0x00100E78 /* RW-4R */
#define NV_PFB_PRI_MMU_L2TLB_ECC_UNCORRECTED_ERR_COUNT_TOTAL 15:0 /* RWEVF */
#define NV_PFB_PRI_MMU_L2TLB_ECC_UNCORRECTED_ERR_COUNT_TOTAL_INIT 0 /* RWE-V */
#define NV_PFB_PRI_MMU_L2TLB_ECC_UNCORRECTED_ERR_COUNT_UNIQUE 31:16 /* RWEVF */
#define NV_PFB_PRI_MMU_L2TLB_ECC_UNCORRECTED_ERR_COUNT_UNIQUE_INIT 0 /* RWE-V */
#define NV_PFB_PRI_MMU_HUBTLB_ECC_UNCORRECTED_ERR_COUNT 0x00100E8C /* RW-4R */
#define NV_PFB_PRI_MMU_HUBTLB_ECC_UNCORRECTED_ERR_COUNT 0x00100E8C /* RW-4R */
#define NV_PFB_PRI_MMU_HUBTLB_ECC_UNCORRECTED_ERR_COUNT_TOTAL 15:0 /* RWEVF */
#define NV_PFB_PRI_MMU_HUBTLB_ECC_UNCORRECTED_ERR_COUNT_TOTAL_INIT 0 /* RWE-V */
#define NV_PFB_PRI_MMU_HUBTLB_ECC_UNCORRECTED_ERR_COUNT_UNIQUE 31:16 /* RWEVF */
#define NV_PFB_PRI_MMU_HUBTLB_ECC_UNCORRECTED_ERR_COUNT_UNIQUE_INIT 0 /* RWE-V */
#define NV_PFB_PRI_MMU_FILLUNIT_ECC_UNCORRECTED_ERR_COUNT 0x00100EA0 /* RW-4R */
#define NV_PFB_PRI_MMU_FILLUNIT_ECC_UNCORRECTED_ERR_COUNT 0x00100EA0 /* RW-4R */
#define NV_PFB_PRI_MMU_FILLUNIT_ECC_UNCORRECTED_ERR_COUNT_TOTAL 15:0 /* RWEVF */
#define NV_PFB_PRI_MMU_FILLUNIT_ECC_UNCORRECTED_ERR_COUNT_TOTAL_INIT 0 /* RWE-V */
#define NV_PFB_PRI_MMU_FILLUNIT_ECC_UNCORRECTED_ERR_COUNT_UNIQUE 31:16 /* RWEVF */
#define NV_PFB_PRI_MMU_FILLUNIT_ECC_UNCORRECTED_ERR_COUNT_UNIQUE_INIT 0 /* RWE-V */
#endif // __gh100_dev_fb_h_

18
src/common/inc/swref/published/hopper/gh100/dev_gsp.h
View File

@@ -31,4 +31,22 @@
#define NV_PGSP_FALCON_ENGINE_RESET_STATUS_ASSERTED 0x00000000 /* R-E-V */
#define NV_PGSP_FALCON_ENGINE_RESET_STATUS_DEASSERTED 0x00000002 /* R---V */
#define NV_PGSP_MAILBOX(i) (0x110804+(i)*4) /* RW-4A */
#define NV_PGSP_EMEMC(i) (0x110ac0+(i)*8) /* RW-4A */
#define NV_PGSP_EMEMC__SIZE_1 8 /* */
#define NV_PGSP_EMEMC_OFFS 7:2 /* RWIVF */
#define NV_PGSP_EMEMC_OFFS_INIT 0x00000000 /* RWI-V */
#define NV_PGSP_EMEMC_BLK 15:8 /* RWIVF */
#define NV_PGSP_EMEMC_BLK_INIT 0x00000000 /* RWI-V */
#define NV_PGSP_EMEMC_AINCW 24:24 /* RWIVF */
#define NV_PGSP_EMEMC_AINCW_INIT 0x00000000 /* RWI-V */
#define NV_PGSP_EMEMC_AINCW_TRUE 0x00000001 /* RW--V */
#define NV_PGSP_EMEMC_AINCW_FALSE 0x00000000 /* RW--V */
#define NV_PGSP_EMEMC_AINCR 25:25 /* RWIVF */
#define NV_PGSP_EMEMC_AINCR_INIT 0x00000000 /* RWI-V */
#define NV_PGSP_EMEMC_AINCR_TRUE 0x00000001 /* RW--V */
#define NV_PGSP_EMEMC_AINCR_FALSE 0x00000000 /* RW--V */
#define NV_PGSP_EMEMD(i) (0x110ac4+(i)*8) /* RW-4A */
#define NV_PGSP_EMEMD__SIZE_1 8 /* */
#define NV_PGSP_EMEMD_DATA 31:0 /* RWXVF */
#endif // __gh100_dev_gsp_h__

29
src/common/inc/swref/published/hopper/gh100/dev_perf.h Normal file
View File

@@ -0,0 +1,29 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gh100_dev_perf_h__
#define __gh100_dev_perf_h__
#define NV_PERF_PMMSYSROUTER_NUM_USER_STREAMING_CHANNELS 9 /* */
#endif // __gh100_dev_perf_h__

44
src/common/inc/swref/published/hopper/gh100/dev_vm.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2022-23 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2022-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -65,4 +65,46 @@
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF_EN_CLEAR_VALUE 31:0 /* RWIVF */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF_EN_CLEAR_VALUE_INIT 0x00000000 /* R-I-V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_PAGE_FAULT_CTRL 0x00003070 /* RW-4R */
#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR1_BLOCK_LOW_ADDR 0x00000F60 /* RW-4R */
#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR1_BLOCK_LOW_ADDR_MAP 31:10 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR1_BLOCK_LOW_ADDR_BAR1_PENDING 0:0 /* R-IUF */
#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR1_BLOCK_LOW_ADDR_BAR1_PENDING_EMPTY 0x00000000 /* R-I-V */
#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR1_BLOCK_LOW_ADDR_BAR1_PENDING_BUSY 0x00000001 /* R---V */
#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR1_BLOCK_LOW_ADDR_BAR1_OUTSTANDING 1:1 /* R-IUF */
#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR1_BLOCK_LOW_ADDR_BAR1_OUTSTANDING_FALSE 0x00000000 /* R-I-V */
#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR1_BLOCK_LOW_ADDR_BAR1_OUTSTANDING_TRUE 0x00000001 /* R---V */
#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR1_BLOCK_LOW_ADDR_MODE 9:9 /* RWIUF */
#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR1_BLOCK_LOW_ADDR_MODE_PHYSICAL 0x00000000 /* RWI-V */
#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR1_BLOCK_LOW_ADDR_MODE_VIRTUAL 0x00000001 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR1_BLOCK_LOW_ADDR_TARGET 11:10 /* RWIUF */
#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR1_BLOCK_LOW_ADDR_TARGET_VID_MEM 0x00000000 /* RWI-V */
#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR1_BLOCK_LOW_ADDR_TARGET_SYS_MEM_COHERENT 0x00000002 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR1_BLOCK_LOW_ADDR_TARGET_SYS_MEM_NONCOHERENT 0x00000003 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR1_BLOCK_LOW_ADDR_PTR 31:12 /* RWIUF */
#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR1_BLOCK_LOW_ADDR_PTR_0 0x00000000 /* RWI-V */
#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR1_BLOCK_HIGH_ADDR 0x00000F64 /* RW-4R */
#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR1_BLOCK_HIGH_ADDR_PTR 31:0 /* RWIUF */
#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR1_BLOCK_HIGH_ADDR_PTR_0 0x00000000 /* RWI-V */
#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR1_BLOCK_PTR_SHIFT 12 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR2_BLOCK_LOW_ADDR 0x00000F70 /* RW-4R */
#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR2_BLOCK_LOW_ADDR_MAP 31:10 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR2_BLOCK_LOW_ADDR_BAR2_PENDING 0:0 /* R-IUF */
#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR2_BLOCK_LOW_ADDR_BAR2_PENDING_EMPTY 0x00000000 /* R-I-V */
#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR2_BLOCK_LOW_ADDR_BAR2_PENDING_BUSY 0x00000001 /* R---V */
#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR2_BLOCK_LOW_ADDR_BAR2_OUTSTANDING 1:1 /* R-IUF */
#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR2_BLOCK_LOW_ADDR_BAR2_OUTSTANDING_FALSE 0x00000000 /* R-I-V */
#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR2_BLOCK_LOW_ADDR_BAR2_OUTSTANDING_TRUE 0x00000001 /* R---V */
#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR2_BLOCK_LOW_ADDR_MODE 9:9 /* RWIUF */
#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR2_BLOCK_LOW_ADDR_MODE_PHYSICAL 0x00000000 /* RWI-V */
#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR2_BLOCK_LOW_ADDR_MODE_VIRTUAL 0x00000001 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR2_BLOCK_LOW_ADDR_TARGET 11:10 /* RWIUF */
#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR2_BLOCK_LOW_ADDR_TARGET_VID_MEM 0x00000000 /* RWI-V */
#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR2_BLOCK_LOW_ADDR_TARGET_SYS_MEM_COHERENT 0x00000002 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR2_BLOCK_LOW_ADDR_TARGET_SYS_MEM_NONCOHERENT 0x00000003 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR2_BLOCK_LOW_ADDR_PTR 31:12 /* RWIUF */
#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR2_BLOCK_LOW_ADDR_PTR_0 0x00000000 /* RWI-V */
#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR2_BLOCK_HIGH_ADDR 0x00000F74 /* RW-4R */
#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR2_BLOCK_HIGH_ADDR_PTR (52-33):0 /* RWIUF */
#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR2_BLOCK_HIGH_ADDR_PTR_0 0x00000000 /* RWI-V */
#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR2_BLOCK_PTR_SHIFT 12 /* */
#endif // __gh100_dev_vm_h__

3
src/common/inc/swref/published/hopper/gh100/dev_xtl_ep_pcfg_gpu.h
View File

@@ -24,6 +24,8 @@
#ifndef __gh100_dev_xtl_ep_pcfg_gpu_h__
#define __gh100_dev_xtl_ep_pcfg_gpu_h__
#define NV_EP_PCFG_GPU_ID 0x00000000 /* R--4R */
#define NV_EP_PCFG_GPU_ID_VENDOR 15:0 /* R-EVF */
#define NV_EP_PCFG_GPU_ID_VENDOR_NVIDIA 0x000010DE /* R-E-V */
#define NV_EP_PCFG_GPU_CTRL_CMD_AND_STATUS 0x00000004 /* RW-4R */
#define NV_EP_PCFG_GPU_CTRL_CMD_AND_STATUS_CMD_IO_SPACE 0:0 /* RWIVF */
#define NV_EP_PCFG_GPU_CTRL_CMD_AND_STATUS_CMD_IO_SPACE_ENABLE 0x00000001 /* RW--V */
@@ -114,4 +116,5 @@
#define NV_EP_PCFG_GPU_VSEC_DEBUG_SEC_FAULT_WDG 14:14 /* R-CVF */
#define NV_EP_PCFG_GPU_VSEC_DEBUG_SEC_FAULT_BOOTFSM 15:15 /* R-CVF */
#define NV_EP_PCFG_GPU_VSEC_DEBUG_SEC_IFF_POS 22:16 /* R-CVF */
#define NV_EP_PCFG_GPU_L1_PM_SS_CONTROL_1_REGISTER 0x00000298 /* RW-4R */
#endif // __gh100_dev_xtl_ep_pcfg_gpu_h__

5
src/common/inc/swref/published/hopper/gh100/hwproject.h
View File

@@ -21,9 +21,6 @@
* DEALINGS IN THE SOFTWARE.
*/
#define NV_CHIP_EXTENDED_SYSTEM_PHYSICAL_ADDRESS_BITS 52
#define NV_LTC_PRI_STRIDE 8192
#define NV_LTS_PRI_STRIDE 512
#define NV_FBPA_PRI_STRIDE 16384
#define NV_SCAL_LITTER_NUM_FBPAS 24
#define NV_XPL_BASE_ADDRESS 540672
#define NV_XTL_BASE_ADDRESS 593920
#define NV_FBPA_PRI_STRIDE 16384

5
src/common/inc/swref/published/maxwell/gm107/dev_boot.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2021 NVIDIA CORPORATION & AFFILIATES
* SPDX-FileCopyrightText: Copyright (c) 2003-2023 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -40,4 +40,7 @@
#define NV_PMC_ENABLE_DEVICE__SIZE_1 32 /* */
#define NV_PMC_ENABLE_DEVICE_DISABLE 0x00000000 /* */
#define NV_PMC_ENABLE_DEVICE_ENABLE 0x00000001 /* */
#define NV_PMC_ENABLE_PDISP 30:30 /* RWIVF */
#define NV_PMC_ENABLE_PDISP_DISABLED 0x00000000 /* RW--V */
#define NV_PMC_ENABLE_PDISP_ENABLED 0x00000001 /* RWI-V */
#endif // __gm107_dev_boot_h__

33
src/common/inc/swref/published/maxwell/gm107/dev_bus.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES
* SPDX-FileCopyrightText: Copyright (c) 2003-2023 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -48,6 +48,18 @@
#define NV_PBUS_BAR0_WINDOW_TARGET_SYS_MEM_COHERENT 0x00000002 /* RW--V */
#define NV_PBUS_BAR0_WINDOW_TARGET_SYS_MEM_NONCOHERENT 0x00000003 /* RW--V */
#define NV_PBUS_BAR0_WINDOW_BASE_SHIFT 16 /* */
#define NV_PBUS_BAR1_BLOCK 0x00001704 /* RW-4R */
#define NV_PBUS_BAR1_BLOCK_MAP 29:0 /* RWXUF */
#define NV_PBUS_BAR1_BLOCK_PTR 27:0 /* RWIUF */
#define NV_PBUS_BAR1_BLOCK_PTR_0 0x00000000 /* RWI-V */
#define NV_PBUS_BAR1_BLOCK_TARGET 29:28 /* RWIUF */
#define NV_PBUS_BAR1_BLOCK_TARGET_VID_MEM 0x00000000 /* RWI-V */
#define NV_PBUS_BAR1_BLOCK_TARGET_SYS_MEM_COHERENT 0x00000002 /* RW--V */
#define NV_PBUS_BAR1_BLOCK_TARGET_SYS_MEM_NONCOHERENT 0x00000003 /* RW--V */
#define NV_PBUS_BAR1_BLOCK_MODE 31:31 /* RWIUF */
#define NV_PBUS_BAR1_BLOCK_MODE_PHYSICAL 0x00000000 /* RWI-V */
#define NV_PBUS_BAR1_BLOCK_MODE_VIRTUAL 0x00000001 /* RW--V */
#define NV_PBUS_BAR1_BLOCK_PTR_SHIFT 12 /* */
#define NV_PBUS_BAR2_BLOCK 0x00001714 /* RW-4R */
#define NV_PBUS_BAR2_BLOCK_MAP 29:0 /* RWXUF */
#define NV_PBUS_BAR2_BLOCK_PTR 27:0 /* RWIUF */
@@ -64,4 +76,23 @@
#define NV_PBUS_BAR2_BLOCK_MODE_PHYSICAL 0x00000000 /* RWI-V */
#define NV_PBUS_BAR2_BLOCK_MODE_VIRTUAL 0x00000001 /* RW--V */
#define NV_PBUS_BAR2_BLOCK_PTR_SHIFT 12 /* */
#define NV_PBUS_BIND_STATUS 0x00001710 /* R--4R */
#define NV_PBUS_BIND_STATUS_BAR1_PENDING 0:0 /* R-IUF */
#define NV_PBUS_BIND_STATUS_BAR1_PENDING_EMPTY 0x00000000 /* R-I-V */
#define NV_PBUS_BIND_STATUS_BAR1_PENDING_BUSY 0x00000001 /* R---V */
#define NV_PBUS_BIND_STATUS_BAR1_OUTSTANDING 1:1 /* R-IUF */
#define NV_PBUS_BIND_STATUS_BAR1_OUTSTANDING_FALSE 0x00000000 /* R-I-V */
#define NV_PBUS_BIND_STATUS_BAR1_OUTSTANDING_TRUE 0x00000001 /* R---V */
#define NV_PBUS_BIND_STATUS_BAR2_PENDING 2:2 /* R-IUF */
#define NV_PBUS_BIND_STATUS_BAR2_PENDING_EMPTY 0x00000000 /* R-I-V */
#define NV_PBUS_BIND_STATUS_BAR2_PENDING_BUSY 0x00000001 /* R---V */
#define NV_PBUS_BIND_STATUS_BAR2_OUTSTANDING 3:3 /* R-IUF */
#define NV_PBUS_BIND_STATUS_BAR2_OUTSTANDING_FALSE 0x00000000 /* R-I-V */
#define NV_PBUS_BIND_STATUS_BAR2_OUTSTANDING_TRUE 0x00000001 /* R---V */
#define NV_PBUS_BIND_STATUS_IFB_PENDING 4:4 /* R-IUF */
#define NV_PBUS_BIND_STATUS_IFB_PENDING_EMPTY 0x00000000 /* R-I-V */
#define NV_PBUS_BIND_STATUS_IFB_PENDING_BUSY 0x00000001 /* R---V */
#define NV_PBUS_BIND_STATUS_IFB_OUTSTANDING 5:5 /* R-IUF */
#define NV_PBUS_BIND_STATUS_IFB_OUTSTANDING_FALSE 0x00000000 /* R-I-V */
#define NV_PBUS_BIND_STATUS_IFB_OUTSTANDING_TRUE 0x00000001 /* R---V */
#endif // __gm107_dev_bus_h__

33
src/common/inc/swref/published/maxwell/gm107/dev_fifo.h Normal file
View File

@@ -0,0 +1,33 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gm107_dev_fifo_h__
#define __gm107_dev_fifo_h__
#define NV_PFIFO_FB_IFACE 0x000026f0 /* RW-4R */
#define NV_PFIFO_FB_IFACE_CONTROL 0:0 /* RWIUF */
#define NV_PFIFO_FB_IFACE_CONTROL_DISABLE 0x00000000 /* RW--V */
#define NV_PFIFO_FB_IFACE_CONTROL_ENABLE 0x00000001 /* RWI-V */
#define NV_PFIFO_FB_IFACE_STATUS 4:4 /* R-IUF */
#define NV_PFIFO_FB_IFACE_STATUS_DISABLED 0x00000000 /* R---V */
#define NV_PFIFO_FB_IFACE_STATUS_ENABLED 0x00000001 /* R-I-V */
#endif // __gm107_dev_fifo_h__

4
src/common/inc/swref/published/maxwell/gm107/dev_nv_xve.h
View File

@@ -160,5 +160,7 @@
#define NV_XVE_AER_CORR_ERR_ADVISORY_NONFATAL_NOT_ACTIVE 0x00000000 /* R-C-V */
#define NV_XVE_AER_CORR_ERR_ADVISORY_NONFATAL_ACTIVE 0x00000001 /* R---V */
#define NV_XVE_AER_CORR_ERR_ADVISORY_NONFATAL_CLEAR 0x00000001 /* -W--C */
#define NV_XVE_CYA_2 0x00000704 /* RW-4R */
#define NV_XVE_CYA_2 0x00000704 /* RW-4R */
#define NV_XVE_DEVICE_CONTROL_STATUS_2 0x000000A0 /* RWI4R */
#define NV_XVE_L1_PM_SUBSTATES_CTRL1 0x00000260 /* RW-4R */
#endif // __gm107_dev_nv_xve_h__

44
src/common/inc/swref/published/maxwell/gm107/dev_pri_ringstation_sys.h Normal file
View File

@@ -0,0 +1,44 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gm107_dev_pri_ringstation_sys_h__
#define __gm107_dev_pri_ringstation_sys_h__
#define NV_PPRIV_SYS_PRI_ERROR_CODE 31:8 /* --XVF */
#define NV_PPRIV_SYS_PRI_ERROR_CODE_HOST_FECS_ERR 0xBAD00F /* ----V */
#define NV_PPRIV_SYS_PRI_ERROR_CODE_HOST_PRI_TIMEOUT 0xBAD001 /* ----V */
#define NV_PPRIV_SYS_PRI_ERROR_CODE_HOST_FB_ACK_TIMEOUT 0xBAD0B0 /* ----V */
#define NV_PPRIV_SYS_PRI_ERROR_CODE_FECS_PRI_TIMEOUT 0xBADF10 /* ----V */
#define NV_PPRIV_SYS_PRI_ERROR_CODE_FECS_PRI_DECODE 0xBADF11 /* ----V */
#define NV_PPRIV_SYS_PRI_ERROR_CODE_FECS_PRI_RESET 0xBADF12 /* ----V */
#define NV_PPRIV_SYS_PRI_ERROR_CODE_FECS_PRI_FLOORSWEEP 0xBADF13 /* ----V */
#define NV_PPRIV_SYS_PRI_ERROR_CODE_FECS_PRI_STUCK_ACK 0xBADF14 /* ----V */
#define NV_PPRIV_SYS_PRI_ERROR_CODE_FECS_PRI_0_EXPECTED_ACK 0xBADF15 /* ----V */
#define NV_PPRIV_SYS_PRI_ERROR_CODE_FECS_PRI_FENCE_ERROR 0xBADF16 /* ----V */
#define NV_PPRIV_SYS_PRI_ERROR_CODE_FECS_PRI_SUBID_ERROR 0xBADF17 /* ----V */
#define NV_PPRIV_SYS_PRI_ERROR_CODE_FECS_PRI_ORPHAN 0xBADF20 /* ----V */
#define NV_PPRIV_SYS_PRI_ERROR_CODE_FECS_DEAD_RING 0xBADF30 /* ----V */
#define NV_PPRIV_SYS_PRI_ERROR_CODE_FECS_TRAP 0xBADF40 /* ----V */
#define NV_PPRIV_SYS_PRI_ERROR_CODE_FECS_PRI_CLIENT_ERR 0xBADF50 /* ----V */
#endif // __gm107_dev_pri_ringstation_sys_h__

13
src/common/inc/swref/published/maxwell/gm107/dev_ram.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2021 NVIDIA CORPORATION & AFFILIATES
* SPDX-FileCopyrightText: Copyright (c) 2003-2023 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -55,4 +55,15 @@
#define NV_RAMRL_ENTRY_TIMESLICE_TIMEOUT_128 0x00000080 /* RWI-V */
#define NV_RAMRL_ENTRY_SIZE 8 /* */
#define NV_RAMRL_ENTRY_TSG_LENGTH_MAX 0x00000020 /* RW--V */
#define NV_RAMIN_PAGE_DIR_BASE_TARGET (128*32+1):(128*32+0) /* RWXUF */
#define NV_RAMIN_PAGE_DIR_BASE_TARGET_VID_MEM 0x00000000 /* RW--V */
#define NV_RAMIN_PAGE_DIR_BASE_TARGET_SYS_MEM_COHERENT 0x00000002 /* RW--V */
#define NV_RAMIN_PAGE_DIR_BASE_TARGET_SYS_MEM_NONCOHERENT 0x00000003 /* RW--V */
#define NV_RAMIN_PAGE_DIR_BASE_VOL (128*32+2):(128*32+2) /* RWXUF */
#define NV_RAMIN_PAGE_DIR_BASE_VOL_TRUE 0x00000001 /* RW--V */
#define NV_RAMIN_PAGE_DIR_BASE_VOL_FALSE 0x00000000 /* RW--V */
#define NV_RAMIN_PAGE_DIR_BASE_LO (128*32+31):(128*32+12) /* RWXUF */
#define NV_RAMIN_PAGE_DIR_BASE_HI (129*32+7):(129*32+0) /* RWXUF */
#define NV_RAMIN_ADR_LIMIT_LO (130*32+31):(130*32+12) /* RWXUF */
#define NV_RAMIN_ADR_LIMIT_HI (131*32+7):(131*32+0) /* RWXUF */
#endif // __gm107_dev_ram_h__

63
src/common/inc/swref/published/maxwell/gm200/dev_boot.h Normal file
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@@ -0,0 +1,63 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2021 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gm200_dev_boot_h__
#define __gm200_dev_boot_h__
#define NV_PMC_ENABLE 0x00000200 /* RW-4R */
#define NV_PMC_ENABLE_PMEDIA 4:4 /* */
#define NV_PMC_ENABLE_PMEDIA_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_PMEDIA_ENABLED 0x00000001 /* */
#define NV_PMC_ENABLE_PFIFO 8:8 /* RWIVF */
#define NV_PMC_ENABLE_PFIFO_DISABLED 0x00000000 /* RWI-V */
#define NV_PMC_ENABLE_PFIFO_ENABLED 0x00000001 /* RW--V */
#define NV_PMC_ENABLE_PWR 13:13 /* */
#define NV_PMC_ENABLE_PWR_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_PWR_ENABLED 0x00000001 /* */
#define NV_PMC_ENABLE_PGRAPH 12:12 /* */
#define NV_PMC_ENABLE_PGRAPH_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_PGRAPH_ENABLED 0x00000001 /* */
#define NV_PMC_ENABLE_SEC 14:14 /* */
#define NV_PMC_ENABLE_SEC_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_SEC_ENABLED 0x00000001 /* */
#define NV_PMC_ENABLE_CE0 6:6 /* */
#define NV_PMC_ENABLE_CE0_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_CE0_ENABLED 0x00000001 /* */
#define NV_PMC_ENABLE_CE1 7:7 /* */
#define NV_PMC_ENABLE_CE1_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_CE1_ENABLED 0x00000001 /* */
#define NV_PMC_ENABLE_CE2 21:21 /* */
#define NV_PMC_ENABLE_CE2_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_CE2_ENABLED 0x00000001 /* */
#define NV_PMC_ENABLE_NVDEC 15:15 /* */
#define NV_PMC_ENABLE_NVDEC_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_NVDEC_ENABLED 0x00000001 /* */
#define NV_PMC_ENABLE_PDISP 30:30 /* RWIVF */
#define NV_PMC_ENABLE_PDISP_DISABLED 0x00000000 /* RW--V */
#define NV_PMC_ENABLE_PDISP_ENABLED 0x00000001 /* RWI-V */
#define NV_PMC_ENABLE_NVENC0 18:18 /* */
#define NV_PMC_ENABLE_NVENC0_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_NVENC0_ENABLED 0x00000001 /* */
#define NV_PMC_ENABLE_NVENC1 19:19 /* */
#define NV_PMC_ENABLE_NVENC1_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_NVENC1_ENABLED 0x00000001 /* */
#endif // __gm200_dev_boot_h__

28
src/common/inc/swref/published/maxwell/gm200/dev_fifo.h Normal file
View File

@@ -0,0 +1,28 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gm200_dev_fifo_h__
#define __gm200_dev_fifo_h__
#define NV_PFIFO_CFG0 0x00002004 /* R--4R */
#define NV_PFIFO_CFG0_NUM_PBDMA 7:0 /* R-IUF */
#endif // __gm200_dev_fifo_h__

8
src/common/inc/swref/published/nv_arch.h
View File

@@ -47,7 +47,6 @@
#define GPU_ARCHITECTURE_TURING GPU_ARCHITECTURE(_CLASSIC, 0x0160)
#define GPU_ARCHITECTURE_AMPERE GPU_ARCHITECTURE(_CLASSIC, 0x0170)
#define GPU_ARCHITECTURE_HOPPER GPU_ARCHITECTURE(_CLASSIC, 0x0180)
#define GPU_ARCHITECTURE_ADA GPU_ARCHITECTURE(_CLASSIC, 0x0190)
#define GPU_ARCHITECTURE_T12X GPU_ARCHITECTURE(_TEGRA, 0x0040)
@@ -93,18 +92,11 @@
#define GPU_IMPLEMENTATION_GA106 0x06
#define GPU_IMPLEMENTATION_GA107 0x07
#define GPU_IMPLEMENTATION_GA102F 0x0F
#define GPU_IMPLEMENTATION_GH100 0x00
#define GPU_IMPLEMENTATION_AD102 0x02
#define GPU_IMPLEMENTATION_AD103 0x03
#define GPU_IMPLEMENTATION_AD104 0x04
#define GPU_IMPLEMENTATION_AD106 0x06
#define GPU_IMPLEMENTATION_AD107 0x07
#define GPU_IMPLEMENTATION_T124 0x00

2
src/common/inc/swref/published/nv_ref.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 1993-2021 NVIDIA CORPORATION & AFFILIATES
* SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a

19
src/common/inc/swref/published/nvswitch/ls10/dev_fsp_pri.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2003-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -30,4 +30,21 @@
#define NV_PFSP_FALCON_COMMON_SCRATCH_GROUP_2__DEVICE_MAP 0x00000016 /* */
#define NV_PFSP_FALCON_COMMON_SCRATCH_GROUP_2_VAL 31:0 /* RWIVF */
#define NV_PFSP_FALCON_COMMON_SCRATCH_GROUP_2_VAL_INIT 0x00000000 /* RWI-V */
#define NV_PFSP_QUEUE_HEAD(i) (0x008F2c00+(i)*8) /* RW-4A */
#define NV_PFSP_QUEUE_TAIL(i) (0x008F2c04+(i)*8) /* RW-4A */
#define NV_PFSP_MSGQ_HEAD(i) (0x008F2c80+(i)*8) /* RW-4A */
#define NV_PFSP_MSGQ_TAIL(i) (0x008F2c84+(i)*8) /* RW-4A */
#define NV_PFSP_EMEMC(i) (0x008F2ac0+(i)*8) /* RW-4A */
#define NV_PFSP_EMEMC_OFFS 7:2 /* RWIVF */
#define NV_PFSP_EMEMC_BLK 15:8 /* RWIVF */
#define NV_PFSP_EMEMC_AINCW 24:24 /* RWIVF */
#define NV_PFSP_EMEMC_AINCW_TRUE 0x00000001 /* RW--V */
#define NV_PFSP_EMEMC_AINCR 25:25 /* RWIVF */
#define NV_PFSP_EMEMC_AINCR_TRUE 0x00000001 /* RW--V */
#define NV_PFSP_EMEMD(i) (0x008F2ac4+(i)*8) /* RW-4A */
#endif // __ls10_dev_fsp_pri_h__

47
src/common/inc/swref/published/nvswitch/ls10/dev_nvldl_ip.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2003-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -300,6 +300,51 @@
#define NV_NVLDL_TX_ERROR_COUNT_CTRL_CLEAR_R4_RETRY_CLEAR 0x00000001 /* -W--V */
#define NV_NVLDL_TX_ERROR_COUNT_CTRL_CLEAR_REPLAY 8:8 /* -WXVF */
#define NV_NVLDL_TX_ERROR_COUNT_CTRL_CLEAR_REPLAY_CLEAR 0x00000001 /* -W--V */
#define NV_NVLDL_TXIOBIST_SKIPCOMINSERTERGEN_0 0x00002e00 /* RW-4R */
#define NV_NVLDL_TXIOBIST_SKIPCOMINSERTERGEN_0__PRIV_LEVEL_MASK 0x00002ff4 /* */
#define NV_NVLDL_TXIOBIST_SKIPCOMINSERTERGEN_0_COM_SYMBOL_0 31:0 /* RWEUF */
#define NV_NVLDL_TXIOBIST_SKIPCOMINSERTERGEN_0_COM_SYMBOL_0_INIT 0x00000000 /* RWE-V */
#define NV_NVLDL_TXIOBIST_SKIPCOMINSERTERGEN_1 0x00002e04 /* RW-4R */
#define NV_NVLDL_TXIOBIST_SKIPCOMINSERTERGEN_1__PRIV_LEVEL_MASK 0x00002ff4 /* */
#define NV_NVLDL_TXIOBIST_SKIPCOMINSERTERGEN_1_COM_SYMBOL_1 31:0 /* RWEUF */
#define NV_NVLDL_TXIOBIST_SKIPCOMINSERTERGEN_1_COM_SYMBOL_1_INIT 0x00000000 /* RWE-V */
#define NV_NVLDL_TXIOBIST_SKIPCOMINSERTERGEN_2 0x00002e08 /* RW-4R */
#define NV_NVLDL_TXIOBIST_SKIPCOMINSERTERGEN_2__PRIV_LEVEL_MASK 0x00002ff4 /* */
#define NV_NVLDL_TXIOBIST_SKIPCOMINSERTERGEN_2_SKIP_SYMBOL_0 31:0 /* RWEUF */
#define NV_NVLDL_TXIOBIST_SKIPCOMINSERTERGEN_2_SKIP_SYMBOL_0_INIT 0x00000000 /* RWE-V */
#define NV_NVLDL_TXIOBIST_SKIPCOMINSERTERGEN_3 0x00002e0c /* RW-4R */
#define NV_NVLDL_TXIOBIST_SKIPCOMINSERTERGEN_3__PRIV_LEVEL_MASK 0x00002ff4 /* */
#define NV_NVLDL_TXIOBIST_SKIPCOMINSERTERGEN_3_SKIP_SYMBOL_1 31:0 /* RWEUF */
#define NV_NVLDL_TXIOBIST_SKIPCOMINSERTERGEN_3_SKIP_SYMBOL_1_INIT 0x00000000 /* RWE-V */
#define NV_NVLDL_TXIOBIST_SKIPCOMINSERTERGEN_4 0x00002e10 /* RW-4R */
#define NV_NVLDL_TXIOBIST_SKIPCOMINSERTERGEN_4__PRIV_LEVEL_MASK 0x00002ff4 /* */
#define NV_NVLDL_TXIOBIST_SKIPCOMINSERTERGEN_4_MASK_COM_OUT 0:0 /* RWEUF */
#define NV_NVLDL_TXIOBIST_SKIPCOMINSERTERGEN_4_MASK_COM_OUT_INIT 0x00000001 /* RWE-V */
#define NV_NVLDL_TXIOBIST_SKIPCOMINSERTERGEN_4_MASK_SKIP_OUT 1:1 /* RWEUF */
#define NV_NVLDL_TXIOBIST_SKIPCOMINSERTERGEN_4_MASK_SKIP_OUT_INIT 0x00000001 /* RWE-V */
#define NV_NVLDL_TXIOBIST_SKIPCOMINSERTERGEN_4_SEND_DATA_OUT 2:2 /* RWEUF */
#define NV_NVLDL_TXIOBIST_SKIPCOMINSERTERGEN_4_SEND_DATA_OUT_INIT 0x00000001 /* RWE-V */
#define NV_NVLDL_TXIOBIST_SKIPCOMINSERTERGEN_4_RESET_WORD_CNT_OUT 11:3 /* RWEUF */
#define NV_NVLDL_TXIOBIST_SKIPCOMINSERTERGEN_4_RESET_WORD_CNT_OUT_INIT 0x00000100 /* RWE-V */
#define NV_NVLDL_TXIOBIST_CONFIG 0x00002e14 /* RW-4R */
#define NV_NVLDL_TXIOBIST_CONFIG__PRIV_LEVEL_MASK 0x00002ff0 /* */
#define NV_NVLDL_TXIOBIST_CONFIG_STARTTEST 0:0 /* RWEUF */
#define NV_NVLDL_TXIOBIST_CONFIG_STARTTEST_INIT 0x00000000 /* RWE-V */
#define NV_NVLDL_TXIOBIST_CONFIG_CFGCLKGATEEN 1:1 /* RWEUF */
#define NV_NVLDL_TXIOBIST_CONFIG_CFGCLKGATEEN_INIT 0x00000000 /* RWE-V */
#define NV_NVLDL_TXIOBIST_CONFIG_DPG_PRBSSEEDLD 2:2 /* RWEUF */
#define NV_NVLDL_TXIOBIST_CONFIG_DPG_PRBSSEEDLD_INIT 0x00000000 /* RWE-V */
#define NV_NVLDL_TXIOBIST_CONFIG_PRBSALT 3:3 /* RWEUF */
#define NV_NVLDL_TXIOBIST_CONFIG_PRBSALT_NRZ 0x00000000 /* RWE-V */
#define NV_NVLDL_TXIOBIST_CONFIG_PRBSALT_PAM4 0x00000001 /* RW--V */
#define NV_NVLDL_TXIOBIST_CONFIGREG 0x00002e18 /* RW-4R */
#define NV_NVLDL_TXIOBIST_CONFIGREG__PRIV_LEVEL_MASK 0x00002ff0 /* */
#define NV_NVLDL_TXIOBIST_CONFIGREG_TX_BIST_EN_IN 2:2 /* RWEUF */
#define NV_NVLDL_TXIOBIST_CONFIGREG_TX_BIST_EN_IN_INIT 0x00000000 /* RWE-V */
#define NV_NVLDL_TXIOBIST_CONFIGREG_DISABLE_WIRED_ENABLE_IN 3:3 /* RWEUF */
#define NV_NVLDL_TXIOBIST_CONFIGREG_DISABLE_WIRED_ENABLE_IN_INIT 0x00000000 /* RWE-V */
#define NV_NVLDL_TXIOBIST_CONFIGREG_IO_BIST_MODE_IN 17:17 /* RWEUF */
#define NV_NVLDL_TXIOBIST_CONFIGREG_IO_BIST_MODE_IN_INIT 0x00000000 /* RWE-V */
#define NV_NVLDL_RX_SLSM_STATUS_RX 0x00003014 /* R--4R */
#define NV_NVLDL_RX_SLSM_STATUS_RX_SUBSTATE 3:0 /* R-EVF */
#define NV_NVLDL_RX_SLSM_STATUS_RX_SUBSTATE_STABLE 0x00000000 /* R-E-V */

14
src/common/inc/swref/published/nvswitch/ls10/dev_nvldl_ip_addendum.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2003-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -24,6 +24,18 @@
#ifndef __ls10_dev_nvldl_ip_addendum_h__
#define __ls10_dev_nvldl_ip_addendum_h__
#define NV_NVLDL_TXIOBIST_CONFIG_CFGCLKGATEEN_ENABLE 0x00000001 /* RWI-V */
#define NV_NVLDL_TXIOBIST_SKIPCOMINSERTERGEN_2_SKIP_SYMBOL_0_SYMBOL 0x7845bdcd /* RWIUF */
#define NV_NVLDL_TXIOBIST_SKIPCOMINSERTERGEN_3_SKIP_SYMBOL_1_SYMBOL 0x124507ff /* RWIUF */
#define NV_NVLDL_TXIOBIST_SKIPCOMINSERTERGEN_0_COM_SYMBOL_0_SYMBOL 0xad3d6c5b /* RWIUF */
#define NV_NVLDL_TXIOBIST_SKIPCOMINSERTERGEN_1_COM_SYMBOL_1_SYMBOL 0xbe35879e /* RWIUF */
#define NV_NVLDL_TXIOBIST_SKIPCOMINSERTERGEN_4_RESET_WORD_CNT_OUT_COUNT 0x000000bd /* RWI-V */
#define NV_NVLDL_TXIOBIST_CONFIGREG_TX_BIST_EN_IN_ENABLE 0x00000001 /* RWI-V */
#define NV_NVLDL_TXIOBIST_CONFIGREG_DISABLE_WIRED_ENABLE_IN_ENABLE 0x00000001 /* RWI-V */
#define NV_NVLDL_TXIOBIST_CONFIGREG_IO_BIST_MODE_IN_ENABLE 0x00000001 /* RWI-V */
#define NV_NVLDL_TXIOBIST_CONFIG_STARTTEST_ENABLE 0x00000001 /* RWI-V */
#define NV_NVLDL_TXIOBIST_CONFIG_DPG_PRBSSEEDLD_ENABLE 0x00000001 /* RWI-V */
#define NV_NVLDL_CRC_BIT_ERROR_RATE_SHORT_THRESHOLD_MAN 2:0
#define NV_NVLDL_CRC_BIT_ERROR_RATE_SHORT_THRESHOLD_MAN_DEFAULT 0x00000003
#define NV_NVLDL_CRC_BIT_ERROR_RATE_SHORT_THRESHOLD_EXP 3:3

9
src/common/inc/swref/published/nvswitch/ls10/dev_nvlipt_lnk_ip.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2003-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -635,4 +635,11 @@
#define NV_NVLIPT_LNK_CTRL_CAP_LOCAL_LINK_CHANNEL_ALI_SUPPORT 28:28 /* RWIVF */
#define NV_NVLIPT_LNK_CTRL_CAP_LOCAL_LINK_CHANNEL_ALI_SUPPORT_SUPPORTED 0x00000001 /* RWI-V */
#define NV_NVLIPT_LNK_CTRL_CAP_LOCAL_LINK_CHANNEL_ALI_SUPPORT_NOT_SUPPORTED 0x00000000 /* RW--V */
#define NV_NVLIPT_LNK_CTRL_CAP_LOCAL_LINK_AN1 0x00000688 /* RW-4R */
#define NV_NVLIPT_LNK_CTRL_CAP_LOCAL_LINK_AN1_PWRM_L1_SUPPORT 1:1 /* RWIVF */
#define NV_NVLIPT_LNK_CTRL_CAP_LOCAL_LINK_AN1_PWRM_L1_SUPPORT_SUPPORTED 0x00000001 /* RWI-V */
#define NV_NVLIPT_LNK_CTRL_CAP_LOCAL_LINK_AN1_PWRM_L1_SUPPORT_NOT_SUPPORTED 0x00000000 /* RW--V */
#define NV_NVLIPT_LNK_SCRATCH_WARM 0x000007c0 /* RW-4R */
#define NV_NVLIPT_LNK_SCRATCH_WARM_DATA 31:0 /* RWEVF */
#define NV_NVLIPT_LNK_SCRATCH_WARM_DATA_INIT 0xdeadbaad /* RWE-V */
#endif // __ls10_dev_nvlipt_lnk_ip_h__

16
src/common/inc/swref/published/nvswitch/ls10/dev_pmgr.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2003-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -82,4 +82,18 @@
#define NV_PMGR_GPIO_INPUT_CNTL_BYPASS_FILTER 10:10 /* */
#define NV_PMGR_GPIO_INPUT_CNTL_BYPASS_FILTER_NO 0x00000000 /* */
#define NV_PMGR_GPIO_INPUT_CNTL_BYPASS_FILTER_YES 0x00000001 /* */
#define NV_GPIO_OUTPUT_CNTL(i) (0x00021200 +((i) * 0x4)) /* RW-4A */
#define NV_GPIO_OUTPUT_CNTL_IO_OUTPUT 12:12 /* RWIVF */
#define NV_GPIO_OUTPUT_CNTL_IO_OUTPUT_INIT 0x00000000 /* R-I-V */
#define NV_GPIO_OUTPUT_CNTL_IO_OUTPUT_0 0x00000000 /* RW--V */
#define NV_GPIO_OUTPUT_CNTL_IO_OUTPUT_1 0x00000001 /* RW--V */
#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_1 0x00021644 /* RWI4R */
#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_1_GPIO15_RISING 15:15 /* RWIVF */
#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_1_GPIO15_RISING_INIT 0x00000001 /* RWI-V */
#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_1_GPIO15_RISING_DISABLED 0x00000000 /* RW--V */
#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_1_GPIO15_RISING_ENABLED 0x00000001 /* RW--V */
#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_1_GPIO15_FALLING 31:31 /* RWIVF */
#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_1_GPIO15_FALLING_INIT 0x00000001 /* RWI-V */
#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_1_GPIO15_FALLING_DISABLED 0x00000000 /* RW--V */
#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_1_GPIO15_FALLING_ENABLED 0x00000001 /* RW--V */
#endif // __ls10_dev_pmgr_h__

10
src/common/inc/swref/published/nvswitch/ls10/dev_timer_ip.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2003-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -24,14 +24,18 @@
#ifndef __ls10_dev_timer_ip_h__
#define __ls10_dev_timer_ip_h__
/* This file is autogenerated. Do not edit */
#define NV_PTIMER 0x00000FFF:0x00000000 /* RW--D */
#define NV_PTIMER 0x00000FFF:0x00000000 /* RW--D */
#define NV_PTIMER_PRI_TMR_CG1 0x00000600 /* RW-4R */
#define NV_PTIMER_PRI_TMR_CG1_MONITOR_CG_EN 0:0 /* RWIVF */
#define NV_PTIMER_PRI_TMR_CG1_MONITOR_CG_EN_ENABLED 0x00000001 /* RW--V */
#define NV_PTIMER_PRI_TMR_CG1_MONITOR_CG_EN_DISABLED 0x00000000 /* RWI-V */
#define NV_PTIMER_PRI_TMR_CG1_MONITOR_CG_EN__PROD 0x00000000 /* RW--V */
#define NV_PTIMER_PRI_TMR_CG1_SLCG 1:1 /* RWIVF */
#define NV_PTIMER_PRI_TMR_CG1_SLCG 1:1 /* RWIVF */
#define NV_PTIMER_PRI_TMR_CG1_SLCG_ENABLED 0x00000000 /* RW--V */
#define NV_PTIMER_PRI_TMR_CG1_SLCG_DISABLED 0x00000001 /* RWI-V */
#define NV_PTIMER_PRI_TMR_CG1_SLCG__PROD 0x00000000 /* RW--V */
#define NV_PTIMER_TIME_0 0x00000400 /* R--4R */
#define NV_PTIMER_TIME_0_NSEC 31:5 /* R-XUF */
#define NV_PTIMER_TIME_1 0x00000410 /* R--4R */
#define NV_PTIMER_TIME_1_NSEC 28:0 /* R-XUF */
#endif // __ls10_dev_timer_ip_h__

28
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@@ -0,0 +1,28 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the Software),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __ls10_ptop_discovery_ip_h__
#define __ls10_ptop_discovery_ip_h__
/* This file is autogenerated. Do not edit */
#define NV_PTOP_UNICAST_SW_DEVICE_BASE_SAW_0 0x00028000 /* */
#endif // __ls10_ptop_discovery_ip_h__

51
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2021 NVIDIA CORPORATION & AFFILIATES
* SPDX-FileCopyrightText: Copyright (c) 2003-2023 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -44,4 +44,53 @@
#define NV_PMC_INTR_EN_CLEAR_DEVICE__SIZE_1 32 /* */
#define NV_PMC_INTR_EN_CLEAR_DEVICE_SET 0x00000001 /* */
#define NV_PMC_INTR_EN_CLEAR_VALUE 31:0 /* -W-VF */
#define NV_PMC_ENABLE 0x00000200 /* RW-4R */
#define NV_PMC_ENABLE_PMEDIA 4:4 /* */
#define NV_PMC_ENABLE_PMEDIA_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_PMEDIA_ENABLED 0x00000001 /* */
#define NV_PMC_ENABLE_PFIFO 8:8 /* RWIVF */
#define NV_PMC_ENABLE_PFIFO_DISABLED 0x00000000 /* RWI-V */
#define NV_PMC_ENABLE_PFIFO_ENABLED 0x00000001 /* RW--V */
#define NV_PMC_ENABLE_PWR 13:13 /* */
#define NV_PMC_ENABLE_PWR_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_PWR_ENABLED 0x00000001 /* */
#define NV_PMC_ENABLE_PGRAPH 12:12 /* */
#define NV_PMC_ENABLE_PGRAPH_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_PGRAPH_ENABLED 0x00000001 /* */
#define NV_PMC_ENABLE_SEC 14:14 /* */
#define NV_PMC_ENABLE_SEC_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_SEC_ENABLED 0x00000001 /* */
#define NV_PMC_ENABLE_CE0 6:6 /* */
#define NV_PMC_ENABLE_CE0_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_CE0_ENABLED 0x00000001 /* */
#define NV_PMC_ENABLE_CE1 7:7 /* */
#define NV_PMC_ENABLE_CE1_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_CE1_ENABLED 0x00000001 /* */
#define NV_PMC_ENABLE_CE2 21:21 /* */
#define NV_PMC_ENABLE_CE2_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_CE2_ENABLED 0x00000001 /* */
#define NV_PMC_ENABLE_CE3 22:22 /* */
#define NV_PMC_ENABLE_CE3_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_CE3_ENABLED 0x00000001 /* */
#define NV_PMC_ENABLE_CE4 23:23 /* */
#define NV_PMC_ENABLE_CE4_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_CE4_ENABLED 0x00000001 /* */
#define NV_PMC_ENABLE_CE5 24:24 /* */
#define NV_PMC_ENABLE_CE5_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_CE5_ENABLED 0x00000001 /* */
#define NV_PMC_ENABLE_NVDEC 15:15 /* */
#define NV_PMC_ENABLE_NVDEC_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_NVDEC_ENABLED 0x00000001 /* */
#define NV_PMC_ENABLE_PDISP 30:30 /* RWIVF */
#define NV_PMC_ENABLE_PDISP_DISABLED 0x00000000 /* RW--V */
#define NV_PMC_ENABLE_PDISP_ENABLED 0x00000001 /* RWI-V */
#define NV_PMC_ENABLE_NVENC0 18:18 /* */
#define NV_PMC_ENABLE_NVENC0_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_NVENC0_ENABLED 0x00000001 /* */
#define NV_PMC_ENABLE_NVENC1 19:19 /* */
#define NV_PMC_ENABLE_NVENC1_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_NVENC1_ENABLED 0x00000001 /* */
#define NV_PMC_ENABLE_NVENC2 4:4 /* */
#define NV_PMC_ENABLE_NVENC2_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_NVENC2_ENABLED 0x00000001 /* */
#endif // __gp100_dev_boot_h__

69
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@@ -0,0 +1,69 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2023 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gp100_dev_fb_h__
#define __gp100_dev_fb_h__
#define NV_PFB_PRI_MMU_INVALIDATE_ALL_VA 0:0 /* RWXVF */
#define NV_PFB_PRI_MMU_INVALIDATE_ALL_VA_FALSE 0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_INVALIDATE_ALL_VA_TRUE 0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_INVALIDATE_ALL_PDB 1:1 /* RWXVF */
#define NV_PFB_PRI_MMU_INVALIDATE_ALL_PDB_FALSE 0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_INVALIDATE_ALL_PDB_TRUE 0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_INVALIDATE_HUBTLB_ONLY 2:2 /* RWXVF */
#define NV_PFB_PRI_MMU_INVALIDATE_HUBTLB_ONLY_FALSE 0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_INVALIDATE_HUBTLB_ONLY_TRUE 0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_INVALIDATE_REPLAY 5:3 /* RWXVF */
#define NV_PFB_PRI_MMU_INVALIDATE_REPLAY_NONE 0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_INVALIDATE_REPLAY_START 0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_INVALIDATE_REPLAY_START_ACK_ALL 0x00000002 /* RW--V */
#define NV_PFB_PRI_MMU_INVALIDATE_REPLAY_CANCEL_TARGETED 0x00000003 /* RW--V */
#define NV_PFB_PRI_MMU_INVALIDATE_REPLAY_CANCEL_GLOBAL 0x00000004 /* RW--V */
#define NV_PFB_PRI_MMU_INVALIDATE_REPLAY_CANCEL 0x00000004 /* */
#define NV_PFB_PRI_MMU_INVALIDATE_SYS_MEMBAR 6:6 /* RWXVF */
#define NV_PFB_PRI_MMU_INVALIDATE_SYS_MEMBAR_FALSE 0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_INVALIDATE_SYS_MEMBAR_TRUE 0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_INVALIDATE_ACK 8:7 /* RWXVF */
#define NV_PFB_PRI_MMU_INVALIDATE_ACK_NONE_REQUIRED 0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_INVALIDATE_ACK_INTRANODE 0x00000002 /* RW--V */
#define NV_PFB_PRI_MMU_INVALIDATE_ACK_GLOBALLY 0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_INVALIDATE_CANCEL_CLIENT_ID 14:9 /* RWXVF */
#define NV_PFB_PRI_MMU_INVALIDATE_CANCEL_GPC_ID 19:15 /* RWXVF */
#define NV_PFB_PRI_MMU_INVALIDATE_CANCEL_CLIENT_TYPE 20:20 /* RWXVF */
#define NV_PFB_PRI_MMU_INVALIDATE_CANCEL_CLIENT_TYPE_GPC 0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_INVALIDATE_CANCEL_CLIENT_TYPE_HUB 0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_INVALIDATE_CACHE_LEVEL 26:24 /* RWXVF */
#define NV_PFB_PRI_MMU_INVALIDATE_CACHE_LEVEL_ALL 0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_INVALIDATE_CACHE_LEVEL_PTE_ONLY 0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_INVALIDATE_CACHE_LEVEL_UP_TO_PDE0 0x00000002 /* RW--V */
#define NV_PFB_PRI_MMU_INVALIDATE_CACHE_LEVEL_UP_TO_PDE1 0x00000003 /* RW--V */
#define NV_PFB_PRI_MMU_INVALIDATE_CACHE_LEVEL_UP_TO_PDE2 0x00000004 /* RW--V */
#define NV_PFB_PRI_MMU_INVALIDATE_CACHE_LEVEL_UP_TO_PDE3 0x00000005 /* RW--V */
#define NV_PFB_PRI_MMU_INVALIDATE_CACHE_LEVEL_UP_TO_PDE4 0x00000006 /* RW--V */
#define NV_PFB_PRI_MMU_INVALIDATE_CACHE_LEVEL_UP_TO_PDE5 0x00000007 /* RW--V */
#define NV_PFB_PRI_MMU_INVALIDATE_TRIGGER 31:31 /* -WEVF */
#define NV_PFB_PRI_MMU_INVALIDATE_TRIGGER_FALSE 0x00000000 /* -WE-V */
#define NV_PFB_PRI_MMU_INVALIDATE_TRIGGER_TRUE 0x00000001 /* -W--T */
#endif // __gv100_dev_fb_h__

75
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@@ -0,0 +1,75 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2021 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gp102_dev_boot_h__
#define __gp102_dev_boot_h__
#define NV_PMC_ENABLE 0x00000200 /* RW-4R */
#define NV_PMC_ENABLE_PMEDIA 4:4 /* */
#define NV_PMC_ENABLE_PMEDIA_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_PMEDIA_ENABLED 0x00000001 /* */
#define NV_PMC_ENABLE_PFIFO 8:8 /* RWIVF */
#define NV_PMC_ENABLE_PFIFO_DISABLED 0x00000000 /* RWI-V */
#define NV_PMC_ENABLE_PFIFO_ENABLED 0x00000001 /* RW--V */
#define NV_PMC_ENABLE_PWR 13:13 /* */
#define NV_PMC_ENABLE_PWR_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_PWR_ENABLED 0x00000001 /* */
#define NV_PMC_ENABLE_PGRAPH 12:12 /* */
#define NV_PMC_ENABLE_PGRAPH_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_PGRAPH_ENABLED 0x00000001 /* */
#define NV_PMC_ENABLE_SEC 14:14 /* */
#define NV_PMC_ENABLE_SEC_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_SEC_ENABLED 0x00000001 /* */
#define NV_PMC_ENABLE_CE0 6:6 /* */
#define NV_PMC_ENABLE_CE0_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_CE0_ENABLED 0x00000001 /* */
#define NV_PMC_ENABLE_CE1 7:7 /* */
#define NV_PMC_ENABLE_CE1_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_CE1_ENABLED 0x00000001 /* */
#define NV_PMC_ENABLE_CE2 21:21 /* */
#define NV_PMC_ENABLE_CE2_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_CE2_ENABLED 0x00000001 /* */
#define NV_PMC_ENABLE_CE3 22:22 /* */
#define NV_PMC_ENABLE_CE3_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_CE3_ENABLED 0x00000001 /* */
#define NV_PMC_ENABLE_CE4 23:23 /* */
#define NV_PMC_ENABLE_CE4_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_CE4_ENABLED 0x00000001 /* */
#define NV_PMC_ENABLE_CE5 24:24 /* */
#define NV_PMC_ENABLE_CE5_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_CE5_ENABLED 0x00000001 /* */
#define NV_PMC_ENABLE_NVDEC 15:15 /* */
#define NV_PMC_ENABLE_NVDEC_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_NVDEC_ENABLED 0x00000001 /* */
#define NV_PMC_ENABLE_PDISP 30:30 /* RWIVF */
#define NV_PMC_ENABLE_PDISP_DISABLED 0x00000000 /* RW--V */
#define NV_PMC_ENABLE_PDISP_ENABLED 0x00000001 /* RWI-V */
#define NV_PMC_ENABLE_NVENC0 18:18 /* */
#define NV_PMC_ENABLE_NVENC0_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_NVENC0_ENABLED 0x00000001 /* */
#define NV_PMC_ENABLE_NVENC1 19:19 /* */
#define NV_PMC_ENABLE_NVENC1_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_NVENC1_ENABLED 0x00000001 /* */
#define NV_PMC_ENABLE_NVENC2 4:4 /* */
#define NV_PMC_ENABLE_NVENC2_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_NVENC2_ENABLED 0x00000001 /* */
#endif // __gp102_dev_boot_h__

69
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES
* SPDX-FileCopyrightText: Copyright (c) 2003-2023 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -49,7 +49,74 @@
#define NV_PMC_ENABLE_DEVICE__SIZE_1 32 /* */
#define NV_PMC_ENABLE_DEVICE_DISABLE 0x00000000 /* */
#define NV_PMC_ENABLE_DEVICE_ENABLE 0x00000001 /* */
#define NV_PMC_ENABLE_PMEDIA 4:4 /* */
#define NV_PMC_ENABLE_PMEDIA_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_PMEDIA_ENABLED 0x00000001 /* */
#define NV_PMC_ENABLE_PFIFO 8:8 /* RWIVF */
#define NV_PMC_ENABLE_PFIFO_DISABLED 0x00000000 /* RWI-V */
#define NV_PMC_ENABLE_PFIFO_ENABLED 0x00000001 /* RW--V */
#define NV_PMC_ENABLE_PWR 13:13 /* */
#define NV_PMC_ENABLE_PWR_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_PWR_ENABLED 0x00000001 /* */
#define NV_PMC_ENABLE_CE0 6:6 /* */
#define NV_PMC_ENABLE_CE0_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_CE0_ENABLED 0x00000001 /* */
#define NV_PMC_ENABLE_CE1 7:7 /* */
#define NV_PMC_ENABLE_CE1_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_CE1_ENABLED 0x00000001 /* */
#define NV_PMC_ENABLE_CE2 21:21 /* */
#define NV_PMC_ENABLE_CE2_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_CE2_ENABLED 0x00000001 /* */
#define NV_PMC_ENABLE_CE3 22:22 /* */
#define NV_PMC_ENABLE_CE3_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_CE3_ENABLED 0x00000001 /* */
#define NV_PMC_ENABLE_CE4 23:23 /* */
#define NV_PMC_ENABLE_CE4_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_CE4_ENABLED 0x00000001 /* */
#define NV_PMC_ENABLE_CE5 24:24 /* */
#define NV_PMC_ENABLE_CE5_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_CE5_ENABLED 0x00000001 /* */
#define NV_PMC_ENABLE_CE6 9:9 /* */
#define NV_PMC_ENABLE_CE6_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_CE6_ENABLED 0x00000001 /* */
#define NV_PMC_ENABLE_CE7 10:10 /* */
#define NV_PMC_ENABLE_CE7_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_CE7_ENABLED 0x00000001 /* */
#define NV_PMC_ENABLE_CE8 11:11 /* */
#define NV_PMC_ENABLE_CE8_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_CE8_ENABLED 0x00000001 /* */
#define NV_PMC_ENABLE_PGRAPH 12:12 /* */
#define NV_PMC_ENABLE_PGRAPH_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_PGRAPH_ENABLED 0x00000001 /* */
#define NV_PMC_ENABLE_SEC 14:14 /* */
#define NV_PMC_ENABLE_SEC_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_SEC_ENABLED 0x00000001 /* */
#define NV_PMC_ENABLE_NVDEC 15:15 /* */
#define NV_PMC_ENABLE_NVDEC_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_NVDEC_ENABLED 0x00000001 /* */
#define NV_PMC_ENABLE_NVDEC0 15:15 /* */
#define NV_PMC_ENABLE_NVDEC0_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_NVDEC0_ENABLED 0x00000001 /* */
#define NV_PMC_ENABLE_NVDEC1 16:16 /* */
#define NV_PMC_ENABLE_NVDEC1_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_NVDEC1_ENABLED 0x00000001 /* */
#define NV_PMC_ENABLE_NVDEC2 20:20 /* */
#define NV_PMC_ENABLE_NVENC0 18:18 /* */
#define NV_PMC_ENABLE_NVENC0_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_NVENC0_ENABLED 0x00000001 /* */
#define NV_PMC_ENABLE_NVENC1 19:19 /* */
#define NV_PMC_ENABLE_NVENC1_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_NVENC1_ENABLED 0x00000001 /* */
#define NV_PMC_ENABLE_NVDEC2 20:20 /* */
#define NV_PMC_ENABLE_NVDEC2_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_NVDEC2_ENABLED 0x00000001 /* */
#define NV_PMC_ENABLE_PERFMON 28:28 /* RWIVF */
#define NV_PMC_ENABLE_PERFMON_DISABLED 0x00000000 /* RWI-V */
#define NV_PMC_ENABLE_PERFMON_ENABLED 0x00000001 /* RW--V */
#define NV_PMC_ENABLE_PDISP 30:30 /* RWIVF */
#define NV_PMC_ENABLE_PDISP_DISABLED 0x00000000 /* RW--V */
#define NV_PMC_ENABLE_PDISP_ENABLED 0x00000001 /* RWI-V */
#define NV_PMC_ENABLE_NVJPG0 31:31 /* */
#define NV_PMC_ENABLE_NVJPG0_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_NVJPG0_ENABLED 0x00000001 /* */
#endif // __tu102_dev_boot_h__

45
src/common/inc/swref/published/turing/tu102/dev_bus.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES
* SPDX-FileCopyrightText: Copyright (c) 2003-2023 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -35,4 +35,47 @@
#define NV_PBUS_IFR_FMT_FIXED2 0x00000008 /* */
#define NV_PBUS_IFR_FMT_FIXED2_TOTAL_DATA_SIZE 19:0 /* */
#define NV_PBUS_BAR1_BLOCK 0x00001704 /* RW-4R */
#define NV_PBUS_BAR1_BLOCK_MAP 29:0 /* */
#define NV_PBUS_BAR1_BLOCK_PTR 27:0 /* RWIUF */
#define NV_PBUS_BAR1_BLOCK_PTR_0 0x00000000 /* RWI-V */
#define NV_PBUS_BAR1_BLOCK_TARGET 29:28 /* RWIUF */
#define NV_PBUS_BAR1_BLOCK_TARGET_VID_MEM 0x00000000 /* RWI-V */
#define NV_PBUS_BAR1_BLOCK_TARGET_SYS_MEM_COHERENT 0x00000002 /* RW--V */
#define NV_PBUS_BAR1_BLOCK_TARGET_SYS_MEM_NONCOHERENT 0x00000003 /* RW--V */
#define NV_PBUS_BAR1_BLOCK_MODE 31:31 /* RWIUF */
#define NV_PBUS_BAR1_BLOCK_MODE_PHYSICAL 0x00000000 /* RWI-V */
#define NV_PBUS_BAR1_BLOCK_MODE_VIRTUAL 0x00000001 /* RW--V */
#define NV_PBUS_BAR1_BLOCK_PTR_SHIFT 12 /* */
#define NV_PBUS_BAR2_BLOCK 0x00001714 /* RW-4R */
#define NV_PBUS_BAR2_BLOCK_MAP 29:0 /* */
#define NV_PBUS_BAR2_BLOCK_PTR 27:0 /* RWIUF */
#define NV_PBUS_BAR2_BLOCK_PTR_0 0x00000000 /* RWI-V */
#define NV_PBUS_BAR2_BLOCK_TARGET 29:28 /* RWIUF */
#define NV_PBUS_BAR2_BLOCK_TARGET_VID_MEM 0x00000000 /* RWI-V */
#define NV_PBUS_BAR2_BLOCK_TARGET_SYS_MEM_COHERENT 0x00000002 /* RW--V */
#define NV_PBUS_BAR2_BLOCK_TARGET_SYS_MEM_NONCOHERENT 0x00000003 /* RW--V */
#define NV_PBUS_BAR2_BLOCK_DEBUG_CYA 30:30 /* RWIUF */
#define NV_PBUS_BAR2_BLOCK_DEBUG_CYA_OFF 0x00000001 /* RW--V */
#define NV_PBUS_BAR2_BLOCK_DEBUG_CYA_ON 0x00000000 /* RW--V */
#define NV_PBUS_BAR2_BLOCK_DEBUG_CYA_INIT 0x00000001 /* RWI-V */
#define NV_PBUS_BAR2_BLOCK_MODE 31:31 /* RWIUF */
#define NV_PBUS_BAR2_BLOCK_MODE_PHYSICAL 0x00000000 /* RWI-V */
#define NV_PBUS_BAR2_BLOCK_MODE_VIRTUAL 0x00000001 /* RW--V */
#define NV_PBUS_BAR2_BLOCK_PTR_SHIFT 12 /* */
#define NV_PBUS_BAR2_BLOCK_RESERVED 30:30 /* */
#define NV_PBUS_BAR2_BLOCK_RESERVED_DEFAULT 0x00000001 /* */
#define NV_PBUS_BIND_STATUS_BAR1_PENDING 0:0 /* R-IUF */
#define NV_PBUS_BIND_STATUS_BAR1_PENDING_EMPTY 0x00000000 /* R-I-V */
#define NV_PBUS_BIND_STATUS_BAR1_PENDING_BUSY 0x00000001 /* R---V */
#define NV_PBUS_BIND_STATUS_BAR1_OUTSTANDING 1:1 /* R-IUF */
#define NV_PBUS_BIND_STATUS_BAR1_OUTSTANDING_FALSE 0x00000000 /* R-I-V */
#define NV_PBUS_BIND_STATUS_BAR1_OUTSTANDING_TRUE 0x00000001 /* R---V */
#define NV_PBUS_BIND_STATUS_BAR2_PENDING 2:2 /* R-IUF */
#define NV_PBUS_BIND_STATUS_BAR2_PENDING_EMPTY 0x00000000 /* R-I-V */
#define NV_PBUS_BIND_STATUS_BAR2_PENDING_BUSY 0x00000001 /* R---V */
#define NV_PBUS_BIND_STATUS_BAR2_OUTSTANDING 3:3 /* R-IUF */
#define NV_PBUS_BIND_STATUS_BAR2_OUTSTANDING_FALSE 0x00000000 /* R-I-V */
#define NV_PBUS_BIND_STATUS_BAR2_OUTSTANDING_TRUE 0x00000001 /* R---V */
#endif // __tu102_dev_bus_h__

149
src/common/inc/swref/published/turing/tu102/dev_fault.h Normal file
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@@ -0,0 +1,149 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2023 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __ad102_dev_fault_h__
#define __ad102_dev_fault_h__
#define NV_PFAULT_MMU_ENG_ID_DISPLAY 1 /* */
#define NV_PFAULT_MMU_ENG_ID_IFB 9 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1 128 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2 192 /* */
#define NV_PFAULT_MMU_ENG_ID_SEC 14 /* */
#define NV_PFAULT_MMU_ENG_ID_PERF 8 /* */
#define NV_PFAULT_MMU_ENG_ID_NVDEC 10 /* */
#define NV_PFAULT_MMU_ENG_ID_NVDEC0 10 /* */
#define NV_PFAULT_MMU_ENG_ID_NVDEC1 25 /* */
#define NV_PFAULT_MMU_ENG_ID_NVDEC2 26 /* */
#define NV_PFAULT_MMU_ENG_ID_NVJPG0 24 /* */
#define NV_PFAULT_MMU_ENG_ID_GRCOPY 15 /* */
#define NV_PFAULT_MMU_ENG_ID_CE0 15 /* */
#define NV_PFAULT_MMU_ENG_ID_CE1 16 /* */
#define NV_PFAULT_MMU_ENG_ID_CE2 17 /* */
#define NV_PFAULT_MMU_ENG_ID_CE3 18 /* */
#define NV_PFAULT_MMU_ENG_ID_CE4 19 /* */
#define NV_PFAULT_MMU_ENG_ID_CE5 20 /* */
#define NV_PFAULT_MMU_ENG_ID_CE6 21 /* */
#define NV_PFAULT_MMU_ENG_ID_CE7 22 /* */
#define NV_PFAULT_MMU_ENG_ID_CE8 23 /* */
#define NV_PFAULT_MMU_ENG_ID_PWR_PMU 6 /* */
#define NV_PFAULT_MMU_ENG_ID_PTP 3 /* */
#define NV_PFAULT_MMU_ENG_ID_NVENC0 11 /* */
#define NV_PFAULT_MMU_ENG_ID_NVENC1 12 /* */
#define NV_PFAULT_MMU_ENG_ID_NVENC2 13 /* */
#define NV_PFAULT_MMU_ENG_ID_PHYSICAL 31 /* */
#define NV_PFAULT_CLIENT_GPC_T1_0 0x00000000 /* */
#define NV_PFAULT_CLIENT_GPC_T1_1 0x00000001 /* */
#define NV_PFAULT_CLIENT_GPC_T1_2 0x00000002 /* */
#define NV_PFAULT_CLIENT_GPC_T1_3 0x00000003 /* */
#define NV_PFAULT_CLIENT_GPC_T1_4 0x00000004 /* */
#define NV_PFAULT_CLIENT_GPC_T1_5 0x00000005 /* */
#define NV_PFAULT_CLIENT_GPC_T1_6 0x00000006 /* */
#define NV_PFAULT_CLIENT_GPC_T1_7 0x00000007 /* */
#define NV_PFAULT_CLIENT_GPC_PE_0 0x00000008 /* */
#define NV_PFAULT_CLIENT_GPC_PE_1 0x00000009 /* */
#define NV_PFAULT_CLIENT_GPC_PE_2 0x0000000A /* */
#define NV_PFAULT_CLIENT_GPC_PE_3 0x0000000B /* */
#define NV_PFAULT_CLIENT_GPC_PE_4 0x0000000C /* */
#define NV_PFAULT_CLIENT_GPC_PE_5 0x0000000D /* */
#define NV_PFAULT_CLIENT_GPC_PE_6 0x0000000E /* */
#define NV_PFAULT_CLIENT_GPC_PE_7 0x0000000F /* */
#define NV_PFAULT_CLIENT_GPC_RAST 0x00000010 /* */
#define NV_PFAULT_CLIENT_GPC_GCC 0x00000011 /* */
#define NV_PFAULT_CLIENT_GPC_GPCCS 0x00000012 /* */
#define NV_PFAULT_CLIENT_GPC_PROP_0 0x00000013 /* */
#define NV_PFAULT_CLIENT_GPC_PROP_1 0x00000014 /* */
#define NV_PFAULT_CLIENT_GPC_T1_8 0x00000021 /* */
#define NV_PFAULT_CLIENT_GPC_T1_9 0x00000022 /* */
#define NV_PFAULT_CLIENT_GPC_T1_10 0x00000023 /* */
#define NV_PFAULT_CLIENT_GPC_T1_11 0x00000024 /* */
#define NV_PFAULT_CLIENT_GPC_T1_12 0x00000025 /* */
#define NV_PFAULT_CLIENT_GPC_T1_13 0x00000026 /* */
#define NV_PFAULT_CLIENT_GPC_T1_14 0x00000027 /* */
#define NV_PFAULT_CLIENT_GPC_T1_15 0x00000028 /* */
#define NV_PFAULT_CLIENT_GPC_TPCCS_0 0x00000029 /* */
#define NV_PFAULT_CLIENT_GPC_TPCCS_1 0x0000002A /* */
#define NV_PFAULT_CLIENT_GPC_TPCCS_2 0x0000002B /* */
#define NV_PFAULT_CLIENT_GPC_TPCCS_3 0x0000002C /* */
#define NV_PFAULT_CLIENT_GPC_TPCCS_4 0x0000002D /* */
#define NV_PFAULT_CLIENT_GPC_TPCCS_5 0x0000002E /* */
#define NV_PFAULT_CLIENT_GPC_TPCCS_6 0x0000002F /* */
#define NV_PFAULT_CLIENT_GPC_TPCCS_7 0x00000030 /* */
#define NV_PFAULT_CLIENT_GPC_PE_8 0x00000031 /* */
#define NV_PFAULT_CLIENT_GPC_TPCCS_8 0x00000033 /* */
#define NV_PFAULT_CLIENT_GPC_T1_16 0x00000035 /* */
#define NV_PFAULT_CLIENT_GPC_T1_17 0x00000036 /* */
#define NV_PFAULT_CLIENT_HUB_CE0 0x00000001 /* */
#define NV_PFAULT_CLIENT_HUB_CE1 0x00000002 /* */
#define NV_PFAULT_CLIENT_HUB_DNISO 0x00000003 /* */
#define NV_PFAULT_CLIENT_HUB_FE 0x00000004 /* */
#define NV_PFAULT_CLIENT_HUB_FECS 0x00000005 /* */
#define NV_PFAULT_CLIENT_HUB_HOST 0x00000006 /* */
#define NV_PFAULT_CLIENT_HUB_HOST_CPU 0x00000007 /* */
#define NV_PFAULT_CLIENT_HUB_HOST_CPU_NB 0x00000008 /* */
#define NV_PFAULT_CLIENT_HUB_ISO 0x00000009 /* */
#define NV_PFAULT_CLIENT_HUB_MMU 0x0000000A /* */
#define NV_PFAULT_CLIENT_HUB_NVDEC 0x0000000B /* */
#define NV_PFAULT_CLIENT_HUB_NVDEC0 0x0000000B /* */
#define NV_PFAULT_CLIENT_HUB_NVENC1 0x0000000D /* */
#define NV_PFAULT_CLIENT_HUB_NVENC2 0x00000033 /* */
#define NV_PFAULT_CLIENT_HUB_NISO 0x0000000E /* */
#define NV_PFAULT_CLIENT_HUB_P2P 0x0000000F /* */
#define NV_PFAULT_CLIENT_HUB_PD 0x00000010 /* */
#define NV_PFAULT_CLIENT_HUB_PERF 0x00000011 /* */
#define NV_PFAULT_CLIENT_HUB_PMU 0x00000012 /* */
#define NV_PFAULT_CLIENT_HUB_RASTERTWOD 0x00000013 /* */
#define NV_PFAULT_CLIENT_HUB_SCC 0x00000014 /* */
#define NV_PFAULT_CLIENT_HUB_SCC_NB 0x00000015 /* */
#define NV_PFAULT_CLIENT_HUB_SEC 0x00000016 /* */
#define NV_PFAULT_CLIENT_HUB_SSYNC 0x00000017 /* */
#define NV_PFAULT_CLIENT_HUB_NVDEC1 0x0000003A /* */
#define NV_PFAULT_CLIENT_HUB_NVDEC2 0x0000003B /* */
#define NV_PFAULT_CLIENT_HUB_NVJPG0 0x0000003C /* */
#define NV_PFAULT_CLIENT_HUB_VIP 0x00000000 /* */
#define NV_PFAULT_CLIENT_HUB_GRCOPY 0x00000018 /* */
#define NV_PFAULT_CLIENT_HUB_CE2 0x00000018 /* */
#define NV_PFAULT_CLIENT_HUB_XV 0x00000019 /* */
#define NV_PFAULT_CLIENT_HUB_MMU_NB 0x0000001A /* */
#define NV_PFAULT_CLIENT_HUB_NVENC 0x0000001B /* */
#define NV_PFAULT_CLIENT_HUB_NVENC0 0x0000001B /* */
#define NV_PFAULT_CLIENT_HUB_DFALCON 0x0000001C /* */
#define NV_PFAULT_CLIENT_HUB_SKED 0x0000001D /* */
#define NV_PFAULT_CLIENT_HUB_AFALCON 0x0000001E /* */
#define NV_PFAULT_CLIENT_HUB_HSCE0 0x00000020 /* */
#define NV_PFAULT_CLIENT_HUB_HSCE1 0x00000021 /* */
#define NV_PFAULT_CLIENT_HUB_HSCE2 0x00000022 /* */
#define NV_PFAULT_CLIENT_HUB_HSCE3 0x00000023 /* */
#define NV_PFAULT_CLIENT_HUB_HSCE4 0x00000024 /* */
#define NV_PFAULT_CLIENT_HUB_HSCE5 0x00000025 /* */
#define NV_PFAULT_CLIENT_HUB_HSCE6 0x00000026 /* */
#define NV_PFAULT_CLIENT_HUB_HSCE7 0x00000027 /* */
#define NV_PFAULT_CLIENT_HUB_HSCE8 0x00000028 /* */
#define NV_PFAULT_CLIENT_HUB_HSCE9 0x00000029 /* */
#define NV_PFAULT_CLIENT_HUB_DWBIF 0x00000036 /* */
#define NV_PFAULT_CLIENT_HUB_FBFALCON 0x00000037 /* */
#define NV_PFAULT_CLIENT_HUB_GSP 0x00000039 /* */
#define NV_PFAULT_CLIENT_HUB_DONT_CARE 0x0000001F /* */
#endif // _ad102_dev_fault_h__

33
src/common/inc/swref/published/turing/tu102/dev_fb.h
View File

@@ -38,4 +38,37 @@
#define NV_PFB_PRI_MMU_WPR2_ADDR_HI_VAL 31:4 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR2_ADDR_HI_ALIGNMENT 0x0000000c /* */
#define NV_PFB_PRI_MMU_FAULT_BUFFER_SIZE_VAL 19:0 /* RWEVF */
#define NV_PFB_PRI_MMU_FAULT_BUFFER_SIZE_VAL_RESET 0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FAULT_BUFFER_SIZE_OVERFLOW_INTR 29:29 /* RWEVF */
#define NV_PFB_PRI_MMU_FAULT_BUFFER_SIZE_OVERFLOW_INTR_DISABLE 0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FAULT_BUFFER_SIZE_OVERFLOW_INTR_ENABLE 0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_FAULT_BUFFER_SIZE_SET_DEFAULT 30:30 /* RWEVF */
#define NV_PFB_PRI_MMU_FAULT_BUFFER_SIZE_SET_DEFAULT_NO 0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FAULT_BUFFER_SIZE_SET_DEFAULT_YES 0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_FAULT_BUFFER_SIZE_ENABLE 31:31 /* RWEVF */
#define NV_PFB_PRI_MMU_FAULT_BUFFER_SIZE_ENABLE_FALSE 0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FAULT_BUFFER_SIZE_ENABLE_TRUE 0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_L2TLB_ECC_UNCORRECTED_ERR_COUNT 0x00100E78 /* RW-4R */
#define NV_PFB_PRI_MMU_L2TLB_ECC_UNCORRECTED_ERR_COUNT 0x00100E78 /* RW-4R */
#define NV_PFB_PRI_MMU_L2TLB_ECC_UNCORRECTED_ERR_COUNT_TOTAL 15:0 /* RWEVF */
#define NV_PFB_PRI_MMU_L2TLB_ECC_UNCORRECTED_ERR_COUNT_TOTAL_INIT 0 /* RWE-V */
#define NV_PFB_PRI_MMU_L2TLB_ECC_UNCORRECTED_ERR_COUNT_UNIQUE 31:16 /* RWEVF */
#define NV_PFB_PRI_MMU_L2TLB_ECC_UNCORRECTED_ERR_COUNT_UNIQUE_INIT 0 /* RWE-V */
#define NV_PFB_PRI_MMU_HUBTLB_ECC_UNCORRECTED_ERR_COUNT 0x00100E8C /* RW-4R */
#define NV_PFB_PRI_MMU_HUBTLB_ECC_UNCORRECTED_ERR_COUNT 0x00100E8C /* RW-4R */
#define NV_PFB_PRI_MMU_HUBTLB_ECC_UNCORRECTED_ERR_COUNT_TOTAL 15:0 /* RWEVF */
#define NV_PFB_PRI_MMU_HUBTLB_ECC_UNCORRECTED_ERR_COUNT_TOTAL_INIT 0 /* RWE-V */
#define NV_PFB_PRI_MMU_HUBTLB_ECC_UNCORRECTED_ERR_COUNT_UNIQUE 31:16 /* RWEVF */
#define NV_PFB_PRI_MMU_HUBTLB_ECC_UNCORRECTED_ERR_COUNT_UNIQUE_INIT 0 /* RWE-V */
#define NV_PFB_PRI_MMU_FILLUNIT_ECC_UNCORRECTED_ERR_COUNT 0x00100EA0 /* RW-4R */
#define NV_PFB_PRI_MMU_FILLUNIT_ECC_UNCORRECTED_ERR_COUNT 0x00100EA0 /* RW-4R */
#define NV_PFB_PRI_MMU_FILLUNIT_ECC_UNCORRECTED_ERR_COUNT_TOTAL 15:0 /* RWEVF */
#define NV_PFB_PRI_MMU_FILLUNIT_ECC_UNCORRECTED_ERR_COUNT_TOTAL_INIT 0 /* RWE-V */
#define NV_PFB_PRI_MMU_FILLUNIT_ECC_UNCORRECTED_ERR_COUNT_UNIQUE 31:16 /* RWEVF */
#define NV_PFB_PRI_MMU_FILLUNIT_ECC_UNCORRECTED_ERR_COUNT_UNIQUE_INIT 0 /* RWE-V */
#endif // __tu102_dev_fb_h__

29
src/common/inc/swref/published/turing/tu102/dev_fbpa.h Normal file
View File

@@ -0,0 +1,29 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __tu102_dev_fbpa_h_
#define __tu102_dev_fbpa_h_
#define NV_PFB_FBPA_0_ECC_DED_COUNT__SIZE_1 2 /* */
#define NV_PFB_FBPA_0_ECC_DED_COUNT(i) (0x00900488+(i)*4) /* RW-4A */
#endif // __tu102_dev_fbpa_h_

1
src/common/inc/swref/published/turing/tu102/dev_gc6_island.h
View File

@@ -24,6 +24,7 @@
#ifndef __tu102_dev_gc6_island_h__
#define __tu102_dev_gc6_island_h__
#define NV_PGC6 0x118fff:0x118000 /* RW--D */
#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_PRIV_LEVEL_MASK 0x00118128 /* RW-4R */
#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */

17
src/common/inc/swref/published/turing/tu102/dev_gsp.h
View File

@@ -38,5 +38,22 @@
#define NV_PGSP_QUEUE_HEAD(i) (0x110c00+(i)*8) /* RW-4A */
#define NV_PGSP_QUEUE_HEAD__SIZE_1 8 /* */
#define NV_PGSP_QUEUE_HEAD_ADDRESS 31:0 /* RWIVF */
#define NV_PGSP_EMEMC(i) (0x110ac0+(i)*8) /* RW-4A */
#define NV_PGSP_EMEMC__SIZE_1 4 /* */
#define NV_PGSP_EMEMC_OFFS 7:2 /* RWIVF */
#define NV_PGSP_EMEMC_OFFS_INIT 0x00000000 /* RWI-V */
#define NV_PGSP_EMEMC_BLK 15:8 /* RWIVF */
#define NV_PGSP_EMEMC_BLK_INIT 0x00000000 /* RWI-V */
#define NV_PGSP_EMEMC_AINCW 24:24 /* RWIVF */
#define NV_PGSP_EMEMC_AINCW_INIT 0x00000000 /* RWI-V */
#define NV_PGSP_EMEMC_AINCW_TRUE 0x00000001 /* RW--V */
#define NV_PGSP_EMEMC_AINCW_FALSE 0x00000000 /* RW--V */
#define NV_PGSP_EMEMC_AINCR 25:25 /* RWIVF */
#define NV_PGSP_EMEMC_AINCR_INIT 0x00000000 /* RWI-V */
#define NV_PGSP_EMEMC_AINCR_TRUE 0x00000001 /* RW--V */
#define NV_PGSP_EMEMC_AINCR_FALSE 0x00000000 /* RW--V */
#define NV_PGSP_EMEMD(i) (0x110ac4+(i)*8) /* RW-4A */
#define NV_PGSP_EMEMD__SIZE_1 4 /* */
#define NV_PGSP_EMEMD_DATA 31:0 /* RW-VF */
#endif // __tu102_dev_gsp_h__

6
src/common/inc/swref/published/hopper/gh100/dev_ltc.h → src/common/inc/swref/published/turing/tu102/dev_ltc.h
View File

@@ -21,8 +21,8 @@
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gh100_dev_ltc_h_
#define __gh100_dev_ltc_h_
#ifndef __tu102_dev_ltc_h_
#define __tu102_dev_ltc_h_
#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_UNCORRECTED_ERR_COUNT 0x001404f8 /* RW-4R */
#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_UNCORRECTED_ERR_COUNT_TOTAL 15:0 /* RWIVF */
@@ -30,4 +30,4 @@
#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_UNCORRECTED_ERR_COUNT_UNIQUE 31:16 /* RWIVF */
#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_UNCORRECTED_ERR_COUNT_UNIQUE_INIT 0x0000 /* RWI-V */
#endif // __gh100_dev_ltc_h_
#endif // __tu102_dev_ltc_h_

8
src/common/inc/swref/published/turing/tu102/dev_nv_xve.h
View File

@@ -24,6 +24,10 @@
#ifndef __tu102_dev_nv_xve_h__
#define __tu102_dev_nv_xve_h__
#define NV_PCFG 0x00088FFF:0x00088000 /* RW--D */
#define NV_XVE_ID 0x00000000 /* R--4R */
#define NV_XVE_ID_VENDOR 15:0 /* C--VF */
#define NV_XVE_ID_VENDOR_NVIDIA 0x000010DE /* C---V */
#define NV_XVE_SW_RESET 0x00000718 /* RW-4R */
#define NV_XVE_DEVICE_CAPABILITY 0x0000007C /* R--4R */
#define NV_XVE_DEVICE_CAPABILITY_FUNCTION_LEVEL_RESET 28:28 /* R-XVF */
#define NV_XVE_DEVICE_CAPABILITY_FUNCTION_LEVEL_RESET_NOT_SUPPORTED 0x00000000 /* R---V */
@@ -35,6 +39,10 @@
#define NV_XVE_MSIX_CAP_HDR_ENABLE 31:31 /* RWIVF */
#define NV_XVE_MSIX_CAP_HDR_ENABLE_ENABLED 0x00000001 /* RW--V */
#define NV_XVE_MSIX_CAP_HDR_ENABLE_DISABLED 0x00000000 /* RWI-V */
#define NV_XVE_PRIV_MISC_1 0x0000041C /* RW-4R */
#define NV_XVE_PRIV_MISC_1_CYA_HIDE_MSIX_CAP 29:29 /* RWCVF */
#define NV_XVE_PRIV_MISC_1_CYA_HIDE_MSIX_CAP_TRUE 0x00000001 /* RW--V */
#define NV_XVE_PRIV_MISC_1_CYA_HIDE_MSIX_CAP_FALSE 0x00000000 /* RWC-V */
#define NV_XVE_SRIOV_CAP_HDR3 0x00000BD8 /* R--4R */
#define NV_XVE_SRIOV_CAP_HDR3_TOTAL_VFS 31:16 /* R-EVF */
#define NV_XVE_SRIOV_CAP_HDR5 0x00000BE0 /* R--4R */

68
src/common/inc/swref/published/turing/tu102/dev_vm.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES
* SPDX-FileCopyrightText: Copyright (c) 2003-2023 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -23,6 +23,8 @@
#ifndef __tu102_dev_vm_h__
#define __tu102_dev_vm_h__
#define NV_VIRTUAL_FUNCTION_PRIV 0x0002FFFF:0x00000000 /* RW--D */
#define NV_VIRTUAL_FUNCTION 0x0003FFFF:0x00030000 /* RW--D */
#define NV_VIRTUAL_FUNCTION_FULL_PHYS_OFFSET 0x00BBFFFF:0x00B80000 /* RW--D */
#define NV_VIRTUAL_FUNCTION_PRIV_L2_SYSMEM_INVALIDATE 0x00000F00 /* RW-4R */
#define NV_VIRTUAL_FUNCTION_PRIV_L2_PEERMEM_INVALIDATE 0x00000F04 /* RW-4R */
@@ -97,7 +99,23 @@
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_PUT_OVERFLOW_YES 0x00000001 /* R---V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_SIZE(i) (0x00003010+(i)*32) /* RW-4A */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_SIZE__SIZE_1 2 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_SIZE_VAL 19:0 /* RWEVF */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_SIZE_VAL_RESET 0x00000000 /* RWE-V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_SIZE_OVERFLOW_INTR 29:29 /* RWEVF */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_SIZE_OVERFLOW_INTR_DISABLE 0x00000000 /* RWE-V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_SIZE_OVERFLOW_INTR_ENABLE 0x00000001 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_SIZE_SET_DEFAULT 30:30 /* RWEVF */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_SIZE_SET_DEFAULT_NO 0x00000000 /* RWE-V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_SIZE_SET_DEFAULT_YES 0x00000001 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_SIZE_ENABLE 31:31 /* RWEVF */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_SIZE_ENABLE_FALSE 0x00000000 /* RWE-V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_SIZE_ENABLE_TRUE 0x00000001 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_PAGE_FAULT_CTRL 0x00003070 /* RW-4R */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_ADDR_LO 0x00003080 /* R--4R */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_ADDR_HI 0x00003084 /* R--4R */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_INST_LO 0x00003088 /* R--4R */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_INST_HI 0x0000308C /* R--4R */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_INFO 0x00003090 /* R--4R */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_STATUS 0x00003094 /* RW-4R */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_PDB 0x000030A0 /* RW-4R */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_PDB_APERTURE 1:1 /* RWEVF */
@@ -210,5 +228,51 @@
#define NV_VIRTUAL_FUNCTION_PRIV_DOORBELL 0x2200 /* -W-4R */
#define NV_VIRTUAL_FUNCTION_DOORBELL 0x30090 /* -W-4R */
#define NV_VIRTUAL_FUNCTION_ERR_CONT 0x30094 /* R--4R */
#define NV_VIRTUAL_FUNCTION_PRIV_MSIX_TABLE_VECTOR_CONTROL__SIZE_1 6 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_BAR1_BLOCK 0x00000F40 /* RW-4R */
#define NV_VIRTUAL_FUNCTION_PRIV_BAR1_BLOCK__VFALIAS NV_VBUS_VF_BAR1_BLOCK(f) /* */
#define NV_VIRTUAL_FUNCTION_PRIV_BAR1_BLOCK_MAP 29:0 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_BAR1_BLOCK_PTR 27:0 /* RWIUF */
#define NV_VIRTUAL_FUNCTION_PRIV_BAR1_BLOCK_PTR_0 0x00000000 /* RWI-V */
#define NV_VIRTUAL_FUNCTION_PRIV_BAR1_BLOCK_TARGET 29:28 /* RWIUF */
#define NV_VIRTUAL_FUNCTION_PRIV_BAR1_BLOCK_TARGET_VID_MEM 0x00000000 /* RWI-V */
#define NV_VIRTUAL_FUNCTION_PRIV_BAR1_BLOCK_TARGET_SYS_MEM_COHERENT 0x00000002 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_BAR1_BLOCK_TARGET_SYS_MEM_NONCOHERENT 0x00000003 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_BAR1_BLOCK_MODE 31:31 /* RWIUF */
#define NV_VIRTUAL_FUNCTION_PRIV_BAR1_BLOCK_MODE_PHYSICAL 0x00000000 /* RWI-V */
#define NV_VIRTUAL_FUNCTION_PRIV_BAR1_BLOCK_MODE_VIRTUAL 0x00000001 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_BAR2_BLOCK 0x00000F48 /* RW-4R */
#define NV_VIRTUAL_FUNCTION_PRIV_BAR2_BLOCK__VFALIAS NV_VBUS_VF_BAR2_BLOCK(f) /* */
#define NV_VIRTUAL_FUNCTION_PRIV_BAR2_BLOCK_MAP 29:0 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_BAR2_BLOCK_PTR 27:0 /* RWIUF */
#define NV_VIRTUAL_FUNCTION_PRIV_BAR2_BLOCK_PTR_0 0x00000000 /* RWI-V */
#define NV_VIRTUAL_FUNCTION_PRIV_BAR2_BLOCK_TARGET 29:28 /* RWIUF */
#define NV_VIRTUAL_FUNCTION_PRIV_BAR2_BLOCK_TARGET_VID_MEM 0x00000000 /* RWI-V */
#define NV_VIRTUAL_FUNCTION_PRIV_BAR2_BLOCK_TARGET_SYS_MEM_COHERENT 0x00000002 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_BAR2_BLOCK_TARGET_SYS_MEM_NONCOHERENT 0x00000003 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_BAR2_BLOCK_DEBUG_CYA 30:30 /* RWIUF */
#define NV_VIRTUAL_FUNCTION_PRIV_BAR2_BLOCK_DEBUG_CYA_OFF 0x00000001 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_BAR2_BLOCK_DEBUG_CYA_ON 0x00000000 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_BAR2_BLOCK_DEBUG_CYA_INIT 0x00000001 /* RWI-V */
#define NV_VIRTUAL_FUNCTION_PRIV_BAR2_BLOCK_MODE 31:31 /* RWIUF */
#define NV_VIRTUAL_FUNCTION_PRIV_BAR2_BLOCK_MODE_PHYSICAL 0x00000000 /* RWI-V */
#define NV_VIRTUAL_FUNCTION_PRIV_BAR2_BLOCK_MODE_VIRTUAL 0x00000001 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_BIND_STATUS 0x00000F50 /* R--4R */
#define NV_VIRTUAL_FUNCTION_PRIV_BIND_STATUS__VFALIAS NV_VBUS_VF_BIND_STATUS(f) /* */
#define NV_VIRTUAL_FUNCTION_PRIV_BIND_STATUS_BAR1_PENDING 0:0 /* R-IUF */
#define NV_VIRTUAL_FUNCTION_PRIV_BIND_STATUS_BAR1_PENDING_EMPTY 0x00000000 /* R-I-V */
#define NV_VIRTUAL_FUNCTION_PRIV_BIND_STATUS_BAR1_PENDING_BUSY 0x00000001 /* R---V */
#define NV_VIRTUAL_FUNCTION_PRIV_BIND_STATUS_BAR1_OUTSTANDING 1:1 /* R-IUF */
#define NV_VIRTUAL_FUNCTION_PRIV_BIND_STATUS_BAR1_OUTSTANDING_FALSE 0x00000000 /* R-I-V */
#define NV_VIRTUAL_FUNCTION_PRIV_BIND_STATUS_BAR1_OUTSTANDING_TRUE 0x00000001 /* R---V */
#define NV_VIRTUAL_FUNCTION_PRIV_BIND_STATUS_BAR2_PENDING 2:2 /* R-IUF */
#define NV_VIRTUAL_FUNCTION_PRIV_BIND_STATUS_BAR2_PENDING_EMPTY 0x00000000 /* R-I-V */
#define NV_VIRTUAL_FUNCTION_PRIV_BIND_STATUS_BAR2_PENDING_BUSY 0x00000001 /* R---V */
#define NV_VIRTUAL_FUNCTION_PRIV_BIND_STATUS_BAR2_OUTSTANDING 3:3 /* R-IUF */
#define NV_VIRTUAL_FUNCTION_PRIV_BIND_STATUS_BAR2_OUTSTANDING_FALSE 0x00000000 /* R-I-V */
#define NV_VIRTUAL_FUNCTION_PRIV_BIND_STATUS_BAR2_OUTSTANDING_TRUE 0x00000001 /* R---V */
#define NV_VIRTUAL_FUNCTION_PRIV_MSIX_TABLE_VECTOR_CONTROL(i) (0x0001000C+(i)*16) /* RW-4A */
#define NV_VIRTUAL_FUNCTION_PRIV_MSIX_TABLE_VECTOR_CONTROL__SIZE_1 6 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_MSIX_TABLE_VECTOR_CONTROL_MASK_BIT 0:0 /* RWIVF */
#define NV_VIRTUAL_FUNCTION_PRIV_MSIX_TABLE_VECTOR_CONTROL_MASK_BIT_UNMASKED 0x00000000 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_MSIX_TABLE_VECTOR_CONTROL_MASK_BIT_MASKED 0x00000001 /* RWI-V */
#endif // __tu102_dev_vm_h__

7
src/common/inc/swref/published/turing/tu102/hwproject.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2021-2021 NVIDIA CORPORATION & AFFILIATES
* SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -25,5 +25,10 @@
#define __tu102_hwproject_h__
#define NV_CHIP_EXTENDED_SYSTEM_PHYSICAL_ADDRESS_BITS 47
#define NV_HOST_NUM_PBDMA 12
#define NV_SCAL_LITTER_NUM_FBPAS 16
#define NV_FBPA_PRI_STRIDE 16384
#define NV_LTC_PRI_STRIDE 8192
#define NV_LTS_PRI_STRIDE 512
#endif // __tu102_hwproject_h__

60
src/common/inc/swref/published/volta/gv100/dev_boot.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2021 NVIDIA CORPORATION & AFFILIATES
* SPDX-FileCopyrightText: Copyright (c) 2003-2023 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -44,4 +44,62 @@
#define NV_PMC_INTR_EN_CLEAR_DEVICE__SIZE_1 32 /* */
#define NV_PMC_INTR_EN_CLEAR_DEVICE_SET 0x00000001 /* */
#define NV_PMC_INTR_EN_CLEAR_VALUE 31:0 /* -W-VF */
#define NV_PMC_ENABLE 0x00000200 /* RW-4R */
#define NV_PMC_ENABLE_PMEDIA 4:4 /* */
#define NV_PMC_ENABLE_PMEDIA_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_PMEDIA_ENABLED 0x00000001 /* */
#define NV_PMC_ENABLE_PFIFO 8:8 /* RWIVF */
#define NV_PMC_ENABLE_PFIFO_DISABLED 0x00000000 /* RWI-V */
#define NV_PMC_ENABLE_PFIFO_ENABLED 0x00000001 /* RW--V */
#define NV_PMC_ENABLE_PWR 13:13 /* */
#define NV_PMC_ENABLE_PWR_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_PWR_ENABLED 0x00000001 /* */
#define NV_PMC_ENABLE_PGRAPH 12:12 /* */
#define NV_PMC_ENABLE_PGRAPH_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_PGRAPH_ENABLED 0x00000001 /* */
#define NV_PMC_ENABLE_SEC 14:14 /* */
#define NV_PMC_ENABLE_SEC_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_SEC_ENABLED 0x00000001 /* */
#define NV_PMC_ENABLE_CE0 6:6 /* */
#define NV_PMC_ENABLE_CE0_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_CE0_ENABLED 0x00000001 /* */
#define NV_PMC_ENABLE_CE1 7:7 /* */
#define NV_PMC_ENABLE_CE1_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_CE1_ENABLED 0x00000001 /* */
#define NV_PMC_ENABLE_CE2 21:21 /* */
#define NV_PMC_ENABLE_CE2_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_CE2_ENABLED 0x00000001 /* */
#define NV_PMC_ENABLE_CE3 22:22 /* */
#define NV_PMC_ENABLE_CE3_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_CE3_ENABLED 0x00000001 /* */
#define NV_PMC_ENABLE_CE4 23:23 /* */
#define NV_PMC_ENABLE_CE4_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_CE4_ENABLED 0x00000001 /* */
#define NV_PMC_ENABLE_CE5 24:24 /* */
#define NV_PMC_ENABLE_CE5_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_CE5_ENABLED 0x00000001 /* */
#define NV_PMC_ENABLE_CE6 9:9 /* */
#define NV_PMC_ENABLE_CE6_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_CE6_ENABLED 0x00000001 /* */
#define NV_PMC_ENABLE_CE7 10:10 /* */
#define NV_PMC_ENABLE_CE7_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_CE7_ENABLED 0x00000001 /* */
#define NV_PMC_ENABLE_CE8 11:11 /* */
#define NV_PMC_ENABLE_CE8_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_CE8_ENABLED 0x00000001 /* */
#define NV_PMC_ENABLE_NVDEC 15:15 /* */
#define NV_PMC_ENABLE_NVDEC_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_NVDEC_ENABLED 0x00000001 /* */
#define NV_PMC_ENABLE_PDISP 30:30 /* RWIVF */
#define NV_PMC_ENABLE_PDISP_DISABLED 0x00000000 /* RW--V */
#define NV_PMC_ENABLE_PDISP_ENABLED 0x00000001 /* RWI-V */
#define NV_PMC_ENABLE_NVENC0 18:18 /* */
#define NV_PMC_ENABLE_NVENC0_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_NVENC0_ENABLED 0x00000001 /* */
#define NV_PMC_ENABLE_NVENC1 19:19 /* */
#define NV_PMC_ENABLE_NVENC1_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_NVENC1_ENABLED 0x00000001 /* */
#define NV_PMC_ENABLE_NVENC2 4:4 /* */
#define NV_PMC_ENABLE_NVENC2_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_NVENC2_ENABLED 0x00000001 /* */
#endif // __gv100_dev_boot_h__

40
src/common/inc/swref/published/volta/gv100/dev_fault.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2021 NVIDIA CORPORATION & AFFILIATES
* SPDX-FileCopyrightText: Copyright (c) 2003-2023 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -24,4 +24,42 @@
#ifndef __gv100_dev_fault_h__
#define __gv100_dev_fault_h__
#define NV_PFAULT_MMU_ENG_ID_GRAPHICS 64 /* */
#define NV_PFAULT_MMU_ENG_ID_PHYSICAL 31 /* */
#define NV_PFAULT_ACCESS_TYPE_VIRT_READ 0x00000000 /* */
#define NV_PFAULT_ACCESS_TYPE_VIRT_WRITE 0x00000001 /* */
#define NV_PFAULT_ACCESS_TYPE_VIRT_ATOMIC 0x00000002 /* */
#define NV_PFAULT_ACCESS_TYPE_VIRT_ATOMIC_STRONG 0x00000002 /* */
#define NV_PFAULT_ACCESS_TYPE_VIRT_PREFETCH 0x00000003 /* */
#define NV_PFAULT_ACCESS_TYPE_VIRT_ATOMIC_WEAK 0x00000004 /* */
#define NV_PFAULT_ACCESS_TYPE_PHYS_READ 0x00000008 /* */
#define NV_PFAULT_ACCESS_TYPE_PHYS_WRITE 0x00000009 /* */
#define NV_PFAULT_ACCESS_TYPE_PHYS_ATOMIC 0x0000000a /* */
#define NV_PFAULT_ACCESS_TYPE_PHYS_PREFETCH 0x0000000b /* */
#define NV_PFAULT_MMU_ENG_ID_CE0 15 /* */
#define NV_PFAULT_MMU_ENG_ID_CE1 16 /* */
#define NV_PFAULT_MMU_ENG_ID_CE2 17 /* */
#define NV_PFAULT_MMU_ENG_ID_CE3 18 /* */
#define NV_PFAULT_MMU_ENG_ID_CE4 19 /* */
#define NV_PFAULT_MMU_ENG_ID_CE5 20 /* */
#define NV_PFAULT_MMU_ENG_ID_CE6 21 /* */
#define NV_PFAULT_MMU_ENG_ID_CE7 22 /* */
#define NV_PFAULT_MMU_ENG_ID_CE8 23 /* */
#define NV_PFAULT_FAULT_TYPE_PDE 0x00000000 /* */
#define NV_PFAULT_FAULT_TYPE_PDE_SIZE 0x00000001 /* */
#define NV_PFAULT_FAULT_TYPE_PTE 0x00000002 /* */
#define NV_PFAULT_FAULT_TYPE_VA_LIMIT_VIOLATION 0x00000003 /* */
#define NV_PFAULT_FAULT_TYPE_UNBOUND_INST_BLOCK 0x00000004 /* */
#define NV_PFAULT_FAULT_TYPE_PRIV_VIOLATION 0x00000005 /* */
#define NV_PFAULT_FAULT_TYPE_RO_VIOLATION 0x00000006 /* */
#define NV_PFAULT_FAULT_TYPE_WO_VIOLATION 0x00000007 /* */
#define NV_PFAULT_FAULT_TYPE_PITCH_MASK_VIOLATION 0x00000008 /* */
#define NV_PFAULT_FAULT_TYPE_WORK_CREATION 0x00000009 /* */
#define NV_PFAULT_FAULT_TYPE_UNSUPPORTED_APERTURE 0x0000000a /* */
#define NV_PFAULT_FAULT_TYPE_COMPRESSION_FAILURE 0x0000000b /* */
#define NV_PFAULT_FAULT_TYPE_UNSUPPORTED_KIND 0x0000000c /* */
#define NV_PFAULT_FAULT_TYPE_REGION_VIOLATION 0x0000000d /* */
#define NV_PFAULT_FAULT_TYPE_POISONED 0x0000000e /* */
#define NV_PFAULT_FAULT_TYPE_ATOMIC_VIOLATION 0x0000000f /* */
#define NV_PFAULT_MMU_CLIENT_TYPE_GPC 0x00000000 /* */
#define NV_PFAULT_MMU_CLIENT_TYPE_HUB 0x00000001 /* */
#endif // __gv100_dev_fault_h__

51
src/common/inc/swref/published/volta/gv100/dev_fb.h
View File

@@ -73,6 +73,8 @@
#define NV_PFB_NISO_ACCESS_COUNTER_NOTIFY_BUFFER_CLR_WRITE_NACK 31:31 /* -WIVF */
#define NV_PFB_NISO_ACCESS_COUNTER_NOTIFY_BUFFER_CLR_WRITE_NACK_INIT 0x0 /* -WI-V */
#define NV_PFB_NISO_ACCESS_COUNTER_NOTIFY_BUFFER_CLR_WRITE_NACK_CLR 0x1 /* -W--V */
#define NV_PFB_PRI_MMU_NON_REPLAY_FAULT_BUFFER 0
#define NV_PFB_PRI_MMU_REPLAY_FAULT_BUFFER 1
#define NV_PFB_PRI_MMU_FAULT_BUFFER_GET(i) (0x00100E2C+(i)*20) /* RW-4A */
#define NV_PFB_PRI_MMU_FAULT_BUFFER_GET__SIZE_1 2 /* */
#define NV_PFB_PRI_MMU_FAULT_BUFFER_GET_PTR 19:0 /* RWEVF */
@@ -95,6 +97,44 @@
#define NV_PFB_PRI_MMU_FAULT_BUFFER_PUT_OVERFLOW 31:31 /* R-EVF */
#define NV_PFB_PRI_MMU_FAULT_BUFFER_PUT_OVERFLOW_NO 0x00000000 /* R-E-V */
#define NV_PFB_PRI_MMU_FAULT_BUFFER_PUT_OVERFLOW_YES 0x00000001 /* R---V */
#define NV_PFB_PRI_MMU_FAULT_ADDR_LO_ADDR 31:12 /* R-EVF */
#define NV_PFB_PRI_MMU_FAULT_ADDR_HI_ADDR 31:0 /* R-EVF */
#define NV_PFB_PRI_MMU_FAULT_INST_LO_ENGINE_ID 8:0 /* R-EVF */
#define NV_PFB_PRI_MMU_FAULT_INST_LO_APERTURE 11:10 /* R-EVF */
#define NV_PFB_PRI_MMU_FAULT_INST_LO_ADDR 31:12 /* R-EVF */
#define NV_PFB_PRI_MMU_FAULT_INST_HI_ADDR 31:0 /* R-EVF */
#define NV_PFB_PRI_MMU_FAULT_INFO_FAULT_TYPE 4:0 /* R-EVF */
#define NV_PFB_PRI_MMU_FAULT_INFO_FAULT_TYPE_RESET 0x00000000 /* R-E-V */
#define NV_PFB_PRI_MMU_FAULT_INFO_REPLAYABLE_FAULT 7:7 /* R-EVF */
#define NV_PFB_PRI_MMU_FAULT_INFO_REPLAYABLE_FAULT_RESET 0x00000000 /* R-E-V */
#define NV_PFB_PRI_MMU_FAULT_INFO_CLIENT 14:8 /* R-EVF */
#define NV_PFB_PRI_MMU_FAULT_INFO_CLIENT_RESET 0x00000000 /* R-E-V */
#define NV_PFB_PRI_MMU_FAULT_INFO_ACCESS_TYPE 19:16 /* R-EVF */
#define NV_PFB_PRI_MMU_FAULT_INFO_ACCESS_TYPE_READ 0x00000000 /* R---V */
#define NV_PFB_PRI_MMU_FAULT_INFO_ACCESS_TYPE_WRITE 0x00000001 /* R---V */
#define NV_PFB_PRI_MMU_FAULT_INFO_ACCESS_TYPE_ATOMIC 0x00000002 /* R---V */
#define NV_PFB_PRI_MMU_FAULT_INFO_ACCESS_TYPE_PREFETCH 0x00000003 /* R---V */
#define NV_PFB_PRI_MMU_FAULT_INFO_ACCESS_TYPE_VIRT_READ 0x00000000 /* R---V */
#define NV_PFB_PRI_MMU_FAULT_INFO_ACCESS_TYPE_VIRT_WRITE 0x00000001 /* R---V */
#define NV_PFB_PRI_MMU_FAULT_INFO_ACCESS_TYPE_VIRT_ATOMIC 0x00000002 /* R---V */
#define NV_PFB_PRI_MMU_FAULT_INFO_ACCESS_TYPE_VIRT_ATOMIC_STRONG 0x00000002 /* R---V */
#define NV_PFB_PRI_MMU_FAULT_INFO_ACCESS_TYPE_VIRT_PREFETCH 0x00000003 /* R---V */
#define NV_PFB_PRI_MMU_FAULT_INFO_ACCESS_TYPE_VIRT_ATOMIC_WEAK 0x00000004 /* R---V */
#define NV_PFB_PRI_MMU_FAULT_INFO_ACCESS_TYPE_PHYS_READ 0x00000008 /* R---V */
#define NV_PFB_PRI_MMU_FAULT_INFO_ACCESS_TYPE_PHYS_WRITE 0x00000009 /* R---V */
#define NV_PFB_PRI_MMU_FAULT_INFO_ACCESS_TYPE_PHYS_ATOMIC 0x0000000a /* R---V */
#define NV_PFB_PRI_MMU_FAULT_INFO_ACCESS_TYPE_PHYS_PREFETCH 0x0000000b /* R---V */
#define NV_PFB_PRI_MMU_FAULT_INFO_ACCESS_TYPE_RESET 0x00000000 /* R-E-V */
#define NV_PFB_PRI_MMU_FAULT_INFO_CLIENT_TYPE 20:20 /* R-EVF */
#define NV_PFB_PRI_MMU_FAULT_INFO_CLIENT_TYPE_RESET 0x00000000 /* R-E-V */
#define NV_PFB_PRI_MMU_FAULT_INFO_GPC_ID 28:24 /* R-EVF */
#define NV_PFB_PRI_MMU_FAULT_INFO_GPC_ID_RESET 0x00000000 /* R-E-V */
#define NV_PFB_PRI_MMU_FAULT_INFO_PROTECTED_MODE 29:29 /* R-EVF */
#define NV_PFB_PRI_MMU_FAULT_INFO_PROTECTED_MODE_RESET 0x00000000 /* R-E-V */
#define NV_PFB_PRI_MMU_FAULT_INFO_REPLAYABLE_FAULT_EN 30:30 /* R-EVF */
#define NV_PFB_PRI_MMU_FAULT_INFO_REPLAYABLE_FAULT_EN_RESET 0x00000000 /* R-E-V */
#define NV_PFB_PRI_MMU_FAULT_INFO_VALID 31:31 /* R-EVF */
#define NV_PFB_PRI_MMU_FAULT_INFO_VALID_RESET 0x00000000 /* R-E-V */
#define NV_PFB_PRI_MMU_FAULT_STATUS 0x00100E60 /* RW-4R */
#define NV_PFB_PRI_MMU_FAULT_STATUS_DROPPED_BAR1_PHYS 0:0 /* RWEVF */
#define NV_PFB_PRI_MMU_FAULT_STATUS_DROPPED_BAR1_PHYS_RESET 0x00000000 /* RWE-V */
@@ -159,4 +199,15 @@
#define NV_PFB_PRI_MMU_FAULT_STATUS_VALID_RESET 0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FAULT_STATUS_VALID_CLEAR 0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_FAULT_STATUS_VALID_SET 0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_FAULT_BUFFER_SIZE_VAL 19:0 /* RWEVF */
#define NV_PFB_PRI_MMU_FAULT_BUFFER_SIZE_VAL_RESET 0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FAULT_BUFFER_SIZE_OVERFLOW_INTR 29:29 /* RWEVF */
#define NV_PFB_PRI_MMU_FAULT_BUFFER_SIZE_OVERFLOW_INTR_DISABLE 0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FAULT_BUFFER_SIZE_OVERFLOW_INTR_ENABLE 0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_FAULT_BUFFER_SIZE_SET_DEFAULT 30:30 /* RWEVF */
#define NV_PFB_PRI_MMU_FAULT_BUFFER_SIZE_SET_DEFAULT_NO 0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FAULT_BUFFER_SIZE_SET_DEFAULT_YES 0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_FAULT_BUFFER_SIZE_ENABLE 31:31 /* RWEVF */
#define NV_PFB_PRI_MMU_FAULT_BUFFER_SIZE_ENABLE_FALSE 0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FAULT_BUFFER_SIZE_ENABLE_TRUE 0x00000001 /* RW--V */
#endif // __gv100_dev_fb_h__

66
src/common/inc/swref/published/volta/gv11b/dev_boot.h Normal file
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@@ -0,0 +1,66 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2021 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gv11b_dev_boot_h__
#define __gv11b_dev_boot_h__
#define NV_PMC_ENABLE 0x00000200 /* RW-4R */
#define NV_PMC_ENABLE_PMEDIA 4:4 /* */
#define NV_PMC_ENABLE_PMEDIA_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_PMEDIA_ENABLED 0x00000001 /* */
#define NV_PMC_ENABLE_PFIFO 8:8 /* RWIVF */
#define NV_PMC_ENABLE_PFIFO_DISABLED 0x00000000 /* RWI-V */
#define NV_PMC_ENABLE_PFIFO_ENABLED 0x00000001 /* RW--V */
#define NV_PMC_ENABLE_PWR 13:13 /* */
#define NV_PMC_ENABLE_PWR_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_PWR_ENABLED 0x00000001 /* */
#define NV_PMC_ENABLE_PGRAPH 12:12 /* */
#define NV_PMC_ENABLE_PGRAPH_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_PGRAPH_ENABLED 0x00000001 /* */
#define NV_PMC_ENABLE_SEC 14:14 /* */
#define NV_PMC_ENABLE_SEC_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_SEC_ENABLED 0x00000001 /* */
#define NV_PMC_ENABLE_CE0 6:6 /* */
#define NV_PMC_ENABLE_CE0_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_CE0_ENABLED 0x00000001 /* */
#define NV_PMC_ENABLE_CE1 7:7 /* */
#define NV_PMC_ENABLE_CE1_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_CE1_ENABLED 0x00000001 /* */
#define NV_PMC_ENABLE_CE2 21:21 /* */
#define NV_PMC_ENABLE_CE2_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_CE2_ENABLED 0x00000001 /* */
#define NV_PMC_ENABLE_NVDEC 15:15 /* */
#define NV_PMC_ENABLE_NVDEC_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_NVDEC_ENABLED 0x00000001 /* */
#define NV_PMC_ENABLE_PDISP 30:30 /* RWIVF */
#define NV_PMC_ENABLE_PDISP_DISABLED 0x00000000 /* RW--V */
#define NV_PMC_ENABLE_PDISP_ENABLED 0x00000001 /* RWI-V */
#define NV_PMC_ENABLE_NVENC0 18:18 /* */
#define NV_PMC_ENABLE_NVENC0_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_NVENC0_ENABLED 0x00000001 /* */
#define NV_PMC_ENABLE_NVENC1 19:19 /* */
#define NV_PMC_ENABLE_NVENC1_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_NVENC1_ENABLED 0x00000001 /* */
#define NV_PMC_ENABLE_NVENC2 4:4 /* */
#define NV_PMC_ENABLE_NVENC2_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_NVENC2_ENABLED 0x00000001 /* */
#endif // __gv11b_dev_boot_h__