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This commit is contained in:
Bernhard Stoeckner
2024-01-24 17:51:53 +01:00
parent bb2dac1f20
commit 91676d6628
1411 changed files with 261367 additions and 145959 deletions
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69
src/common/inc/swref/published/turing/tu102/dev_boot.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES
* SPDX-FileCopyrightText: Copyright (c) 2003-2023 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -49,7 +49,74 @@
#define NV_PMC_ENABLE_DEVICE__SIZE_1 32 /* */
#define NV_PMC_ENABLE_DEVICE_DISABLE 0x00000000 /* */
#define NV_PMC_ENABLE_DEVICE_ENABLE 0x00000001 /* */
#define NV_PMC_ENABLE_PMEDIA 4:4 /* */
#define NV_PMC_ENABLE_PMEDIA_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_PMEDIA_ENABLED 0x00000001 /* */
#define NV_PMC_ENABLE_PFIFO 8:8 /* RWIVF */
#define NV_PMC_ENABLE_PFIFO_DISABLED 0x00000000 /* RWI-V */
#define NV_PMC_ENABLE_PFIFO_ENABLED 0x00000001 /* RW--V */
#define NV_PMC_ENABLE_PWR 13:13 /* */
#define NV_PMC_ENABLE_PWR_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_PWR_ENABLED 0x00000001 /* */
#define NV_PMC_ENABLE_CE0 6:6 /* */
#define NV_PMC_ENABLE_CE0_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_CE0_ENABLED 0x00000001 /* */
#define NV_PMC_ENABLE_CE1 7:7 /* */
#define NV_PMC_ENABLE_CE1_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_CE1_ENABLED 0x00000001 /* */
#define NV_PMC_ENABLE_CE2 21:21 /* */
#define NV_PMC_ENABLE_CE2_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_CE2_ENABLED 0x00000001 /* */
#define NV_PMC_ENABLE_CE3 22:22 /* */
#define NV_PMC_ENABLE_CE3_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_CE3_ENABLED 0x00000001 /* */
#define NV_PMC_ENABLE_CE4 23:23 /* */
#define NV_PMC_ENABLE_CE4_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_CE4_ENABLED 0x00000001 /* */
#define NV_PMC_ENABLE_CE5 24:24 /* */
#define NV_PMC_ENABLE_CE5_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_CE5_ENABLED 0x00000001 /* */
#define NV_PMC_ENABLE_CE6 9:9 /* */
#define NV_PMC_ENABLE_CE6_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_CE6_ENABLED 0x00000001 /* */
#define NV_PMC_ENABLE_CE7 10:10 /* */
#define NV_PMC_ENABLE_CE7_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_CE7_ENABLED 0x00000001 /* */
#define NV_PMC_ENABLE_CE8 11:11 /* */
#define NV_PMC_ENABLE_CE8_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_CE8_ENABLED 0x00000001 /* */
#define NV_PMC_ENABLE_PGRAPH 12:12 /* */
#define NV_PMC_ENABLE_PGRAPH_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_PGRAPH_ENABLED 0x00000001 /* */
#define NV_PMC_ENABLE_SEC 14:14 /* */
#define NV_PMC_ENABLE_SEC_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_SEC_ENABLED 0x00000001 /* */
#define NV_PMC_ENABLE_NVDEC 15:15 /* */
#define NV_PMC_ENABLE_NVDEC_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_NVDEC_ENABLED 0x00000001 /* */
#define NV_PMC_ENABLE_NVDEC0 15:15 /* */
#define NV_PMC_ENABLE_NVDEC0_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_NVDEC0_ENABLED 0x00000001 /* */
#define NV_PMC_ENABLE_NVDEC1 16:16 /* */
#define NV_PMC_ENABLE_NVDEC1_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_NVDEC1_ENABLED 0x00000001 /* */
#define NV_PMC_ENABLE_NVDEC2 20:20 /* */
#define NV_PMC_ENABLE_NVENC0 18:18 /* */
#define NV_PMC_ENABLE_NVENC0_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_NVENC0_ENABLED 0x00000001 /* */
#define NV_PMC_ENABLE_NVENC1 19:19 /* */
#define NV_PMC_ENABLE_NVENC1_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_NVENC1_ENABLED 0x00000001 /* */
#define NV_PMC_ENABLE_NVDEC2 20:20 /* */
#define NV_PMC_ENABLE_NVDEC2_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_NVDEC2_ENABLED 0x00000001 /* */
#define NV_PMC_ENABLE_PERFMON 28:28 /* RWIVF */
#define NV_PMC_ENABLE_PERFMON_DISABLED 0x00000000 /* RWI-V */
#define NV_PMC_ENABLE_PERFMON_ENABLED 0x00000001 /* RW--V */
#define NV_PMC_ENABLE_PDISP 30:30 /* RWIVF */
#define NV_PMC_ENABLE_PDISP_DISABLED 0x00000000 /* RW--V */
#define NV_PMC_ENABLE_PDISP_ENABLED 0x00000001 /* RWI-V */
#define NV_PMC_ENABLE_NVJPG0 31:31 /* */
#define NV_PMC_ENABLE_NVJPG0_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_NVJPG0_ENABLED 0x00000001 /* */
#endif // __tu102_dev_boot_h__

45
src/common/inc/swref/published/turing/tu102/dev_bus.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES
* SPDX-FileCopyrightText: Copyright (c) 2003-2023 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -35,4 +35,47 @@
#define NV_PBUS_IFR_FMT_FIXED2 0x00000008 /* */
#define NV_PBUS_IFR_FMT_FIXED2_TOTAL_DATA_SIZE 19:0 /* */
#define NV_PBUS_BAR1_BLOCK 0x00001704 /* RW-4R */
#define NV_PBUS_BAR1_BLOCK_MAP 29:0 /* */
#define NV_PBUS_BAR1_BLOCK_PTR 27:0 /* RWIUF */
#define NV_PBUS_BAR1_BLOCK_PTR_0 0x00000000 /* RWI-V */
#define NV_PBUS_BAR1_BLOCK_TARGET 29:28 /* RWIUF */
#define NV_PBUS_BAR1_BLOCK_TARGET_VID_MEM 0x00000000 /* RWI-V */
#define NV_PBUS_BAR1_BLOCK_TARGET_SYS_MEM_COHERENT 0x00000002 /* RW--V */
#define NV_PBUS_BAR1_BLOCK_TARGET_SYS_MEM_NONCOHERENT 0x00000003 /* RW--V */
#define NV_PBUS_BAR1_BLOCK_MODE 31:31 /* RWIUF */
#define NV_PBUS_BAR1_BLOCK_MODE_PHYSICAL 0x00000000 /* RWI-V */
#define NV_PBUS_BAR1_BLOCK_MODE_VIRTUAL 0x00000001 /* RW--V */
#define NV_PBUS_BAR1_BLOCK_PTR_SHIFT 12 /* */
#define NV_PBUS_BAR2_BLOCK 0x00001714 /* RW-4R */
#define NV_PBUS_BAR2_BLOCK_MAP 29:0 /* */
#define NV_PBUS_BAR2_BLOCK_PTR 27:0 /* RWIUF */
#define NV_PBUS_BAR2_BLOCK_PTR_0 0x00000000 /* RWI-V */
#define NV_PBUS_BAR2_BLOCK_TARGET 29:28 /* RWIUF */
#define NV_PBUS_BAR2_BLOCK_TARGET_VID_MEM 0x00000000 /* RWI-V */
#define NV_PBUS_BAR2_BLOCK_TARGET_SYS_MEM_COHERENT 0x00000002 /* RW--V */
#define NV_PBUS_BAR2_BLOCK_TARGET_SYS_MEM_NONCOHERENT 0x00000003 /* RW--V */
#define NV_PBUS_BAR2_BLOCK_DEBUG_CYA 30:30 /* RWIUF */
#define NV_PBUS_BAR2_BLOCK_DEBUG_CYA_OFF 0x00000001 /* RW--V */
#define NV_PBUS_BAR2_BLOCK_DEBUG_CYA_ON 0x00000000 /* RW--V */
#define NV_PBUS_BAR2_BLOCK_DEBUG_CYA_INIT 0x00000001 /* RWI-V */
#define NV_PBUS_BAR2_BLOCK_MODE 31:31 /* RWIUF */
#define NV_PBUS_BAR2_BLOCK_MODE_PHYSICAL 0x00000000 /* RWI-V */
#define NV_PBUS_BAR2_BLOCK_MODE_VIRTUAL 0x00000001 /* RW--V */
#define NV_PBUS_BAR2_BLOCK_PTR_SHIFT 12 /* */
#define NV_PBUS_BAR2_BLOCK_RESERVED 30:30 /* */
#define NV_PBUS_BAR2_BLOCK_RESERVED_DEFAULT 0x00000001 /* */
#define NV_PBUS_BIND_STATUS_BAR1_PENDING 0:0 /* R-IUF */
#define NV_PBUS_BIND_STATUS_BAR1_PENDING_EMPTY 0x00000000 /* R-I-V */
#define NV_PBUS_BIND_STATUS_BAR1_PENDING_BUSY 0x00000001 /* R---V */
#define NV_PBUS_BIND_STATUS_BAR1_OUTSTANDING 1:1 /* R-IUF */
#define NV_PBUS_BIND_STATUS_BAR1_OUTSTANDING_FALSE 0x00000000 /* R-I-V */
#define NV_PBUS_BIND_STATUS_BAR1_OUTSTANDING_TRUE 0x00000001 /* R---V */
#define NV_PBUS_BIND_STATUS_BAR2_PENDING 2:2 /* R-IUF */
#define NV_PBUS_BIND_STATUS_BAR2_PENDING_EMPTY 0x00000000 /* R-I-V */
#define NV_PBUS_BIND_STATUS_BAR2_PENDING_BUSY 0x00000001 /* R---V */
#define NV_PBUS_BIND_STATUS_BAR2_OUTSTANDING 3:3 /* R-IUF */
#define NV_PBUS_BIND_STATUS_BAR2_OUTSTANDING_FALSE 0x00000000 /* R-I-V */
#define NV_PBUS_BIND_STATUS_BAR2_OUTSTANDING_TRUE 0x00000001 /* R---V */
#endif // __tu102_dev_bus_h__

149
src/common/inc/swref/published/turing/tu102/dev_fault.h Normal file
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@@ -0,0 +1,149 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2023 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __ad102_dev_fault_h__
#define __ad102_dev_fault_h__
#define NV_PFAULT_MMU_ENG_ID_DISPLAY 1 /* */
#define NV_PFAULT_MMU_ENG_ID_IFB 9 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1 128 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2 192 /* */
#define NV_PFAULT_MMU_ENG_ID_SEC 14 /* */
#define NV_PFAULT_MMU_ENG_ID_PERF 8 /* */
#define NV_PFAULT_MMU_ENG_ID_NVDEC 10 /* */
#define NV_PFAULT_MMU_ENG_ID_NVDEC0 10 /* */
#define NV_PFAULT_MMU_ENG_ID_NVDEC1 25 /* */
#define NV_PFAULT_MMU_ENG_ID_NVDEC2 26 /* */
#define NV_PFAULT_MMU_ENG_ID_NVJPG0 24 /* */
#define NV_PFAULT_MMU_ENG_ID_GRCOPY 15 /* */
#define NV_PFAULT_MMU_ENG_ID_CE0 15 /* */
#define NV_PFAULT_MMU_ENG_ID_CE1 16 /* */
#define NV_PFAULT_MMU_ENG_ID_CE2 17 /* */
#define NV_PFAULT_MMU_ENG_ID_CE3 18 /* */
#define NV_PFAULT_MMU_ENG_ID_CE4 19 /* */
#define NV_PFAULT_MMU_ENG_ID_CE5 20 /* */
#define NV_PFAULT_MMU_ENG_ID_CE6 21 /* */
#define NV_PFAULT_MMU_ENG_ID_CE7 22 /* */
#define NV_PFAULT_MMU_ENG_ID_CE8 23 /* */
#define NV_PFAULT_MMU_ENG_ID_PWR_PMU 6 /* */
#define NV_PFAULT_MMU_ENG_ID_PTP 3 /* */
#define NV_PFAULT_MMU_ENG_ID_NVENC0 11 /* */
#define NV_PFAULT_MMU_ENG_ID_NVENC1 12 /* */
#define NV_PFAULT_MMU_ENG_ID_NVENC2 13 /* */
#define NV_PFAULT_MMU_ENG_ID_PHYSICAL 31 /* */
#define NV_PFAULT_CLIENT_GPC_T1_0 0x00000000 /* */
#define NV_PFAULT_CLIENT_GPC_T1_1 0x00000001 /* */
#define NV_PFAULT_CLIENT_GPC_T1_2 0x00000002 /* */
#define NV_PFAULT_CLIENT_GPC_T1_3 0x00000003 /* */
#define NV_PFAULT_CLIENT_GPC_T1_4 0x00000004 /* */
#define NV_PFAULT_CLIENT_GPC_T1_5 0x00000005 /* */
#define NV_PFAULT_CLIENT_GPC_T1_6 0x00000006 /* */
#define NV_PFAULT_CLIENT_GPC_T1_7 0x00000007 /* */
#define NV_PFAULT_CLIENT_GPC_PE_0 0x00000008 /* */
#define NV_PFAULT_CLIENT_GPC_PE_1 0x00000009 /* */
#define NV_PFAULT_CLIENT_GPC_PE_2 0x0000000A /* */
#define NV_PFAULT_CLIENT_GPC_PE_3 0x0000000B /* */
#define NV_PFAULT_CLIENT_GPC_PE_4 0x0000000C /* */
#define NV_PFAULT_CLIENT_GPC_PE_5 0x0000000D /* */
#define NV_PFAULT_CLIENT_GPC_PE_6 0x0000000E /* */
#define NV_PFAULT_CLIENT_GPC_PE_7 0x0000000F /* */
#define NV_PFAULT_CLIENT_GPC_RAST 0x00000010 /* */
#define NV_PFAULT_CLIENT_GPC_GCC 0x00000011 /* */
#define NV_PFAULT_CLIENT_GPC_GPCCS 0x00000012 /* */
#define NV_PFAULT_CLIENT_GPC_PROP_0 0x00000013 /* */
#define NV_PFAULT_CLIENT_GPC_PROP_1 0x00000014 /* */
#define NV_PFAULT_CLIENT_GPC_T1_8 0x00000021 /* */
#define NV_PFAULT_CLIENT_GPC_T1_9 0x00000022 /* */
#define NV_PFAULT_CLIENT_GPC_T1_10 0x00000023 /* */
#define NV_PFAULT_CLIENT_GPC_T1_11 0x00000024 /* */
#define NV_PFAULT_CLIENT_GPC_T1_12 0x00000025 /* */
#define NV_PFAULT_CLIENT_GPC_T1_13 0x00000026 /* */
#define NV_PFAULT_CLIENT_GPC_T1_14 0x00000027 /* */
#define NV_PFAULT_CLIENT_GPC_T1_15 0x00000028 /* */
#define NV_PFAULT_CLIENT_GPC_TPCCS_0 0x00000029 /* */
#define NV_PFAULT_CLIENT_GPC_TPCCS_1 0x0000002A /* */
#define NV_PFAULT_CLIENT_GPC_TPCCS_2 0x0000002B /* */
#define NV_PFAULT_CLIENT_GPC_TPCCS_3 0x0000002C /* */
#define NV_PFAULT_CLIENT_GPC_TPCCS_4 0x0000002D /* */
#define NV_PFAULT_CLIENT_GPC_TPCCS_5 0x0000002E /* */
#define NV_PFAULT_CLIENT_GPC_TPCCS_6 0x0000002F /* */
#define NV_PFAULT_CLIENT_GPC_TPCCS_7 0x00000030 /* */
#define NV_PFAULT_CLIENT_GPC_PE_8 0x00000031 /* */
#define NV_PFAULT_CLIENT_GPC_TPCCS_8 0x00000033 /* */
#define NV_PFAULT_CLIENT_GPC_T1_16 0x00000035 /* */
#define NV_PFAULT_CLIENT_GPC_T1_17 0x00000036 /* */
#define NV_PFAULT_CLIENT_HUB_CE0 0x00000001 /* */
#define NV_PFAULT_CLIENT_HUB_CE1 0x00000002 /* */
#define NV_PFAULT_CLIENT_HUB_DNISO 0x00000003 /* */
#define NV_PFAULT_CLIENT_HUB_FE 0x00000004 /* */
#define NV_PFAULT_CLIENT_HUB_FECS 0x00000005 /* */
#define NV_PFAULT_CLIENT_HUB_HOST 0x00000006 /* */
#define NV_PFAULT_CLIENT_HUB_HOST_CPU 0x00000007 /* */
#define NV_PFAULT_CLIENT_HUB_HOST_CPU_NB 0x00000008 /* */
#define NV_PFAULT_CLIENT_HUB_ISO 0x00000009 /* */
#define NV_PFAULT_CLIENT_HUB_MMU 0x0000000A /* */
#define NV_PFAULT_CLIENT_HUB_NVDEC 0x0000000B /* */
#define NV_PFAULT_CLIENT_HUB_NVDEC0 0x0000000B /* */
#define NV_PFAULT_CLIENT_HUB_NVENC1 0x0000000D /* */
#define NV_PFAULT_CLIENT_HUB_NVENC2 0x00000033 /* */
#define NV_PFAULT_CLIENT_HUB_NISO 0x0000000E /* */
#define NV_PFAULT_CLIENT_HUB_P2P 0x0000000F /* */
#define NV_PFAULT_CLIENT_HUB_PD 0x00000010 /* */
#define NV_PFAULT_CLIENT_HUB_PERF 0x00000011 /* */
#define NV_PFAULT_CLIENT_HUB_PMU 0x00000012 /* */
#define NV_PFAULT_CLIENT_HUB_RASTERTWOD 0x00000013 /* */
#define NV_PFAULT_CLIENT_HUB_SCC 0x00000014 /* */
#define NV_PFAULT_CLIENT_HUB_SCC_NB 0x00000015 /* */
#define NV_PFAULT_CLIENT_HUB_SEC 0x00000016 /* */
#define NV_PFAULT_CLIENT_HUB_SSYNC 0x00000017 /* */
#define NV_PFAULT_CLIENT_HUB_NVDEC1 0x0000003A /* */
#define NV_PFAULT_CLIENT_HUB_NVDEC2 0x0000003B /* */
#define NV_PFAULT_CLIENT_HUB_NVJPG0 0x0000003C /* */
#define NV_PFAULT_CLIENT_HUB_VIP 0x00000000 /* */
#define NV_PFAULT_CLIENT_HUB_GRCOPY 0x00000018 /* */
#define NV_PFAULT_CLIENT_HUB_CE2 0x00000018 /* */
#define NV_PFAULT_CLIENT_HUB_XV 0x00000019 /* */
#define NV_PFAULT_CLIENT_HUB_MMU_NB 0x0000001A /* */
#define NV_PFAULT_CLIENT_HUB_NVENC 0x0000001B /* */
#define NV_PFAULT_CLIENT_HUB_NVENC0 0x0000001B /* */
#define NV_PFAULT_CLIENT_HUB_DFALCON 0x0000001C /* */
#define NV_PFAULT_CLIENT_HUB_SKED 0x0000001D /* */
#define NV_PFAULT_CLIENT_HUB_AFALCON 0x0000001E /* */
#define NV_PFAULT_CLIENT_HUB_HSCE0 0x00000020 /* */
#define NV_PFAULT_CLIENT_HUB_HSCE1 0x00000021 /* */
#define NV_PFAULT_CLIENT_HUB_HSCE2 0x00000022 /* */
#define NV_PFAULT_CLIENT_HUB_HSCE3 0x00000023 /* */
#define NV_PFAULT_CLIENT_HUB_HSCE4 0x00000024 /* */
#define NV_PFAULT_CLIENT_HUB_HSCE5 0x00000025 /* */
#define NV_PFAULT_CLIENT_HUB_HSCE6 0x00000026 /* */
#define NV_PFAULT_CLIENT_HUB_HSCE7 0x00000027 /* */
#define NV_PFAULT_CLIENT_HUB_HSCE8 0x00000028 /* */
#define NV_PFAULT_CLIENT_HUB_HSCE9 0x00000029 /* */
#define NV_PFAULT_CLIENT_HUB_DWBIF 0x00000036 /* */
#define NV_PFAULT_CLIENT_HUB_FBFALCON 0x00000037 /* */
#define NV_PFAULT_CLIENT_HUB_GSP 0x00000039 /* */
#define NV_PFAULT_CLIENT_HUB_DONT_CARE 0x0000001F /* */
#endif // _ad102_dev_fault_h__

33
src/common/inc/swref/published/turing/tu102/dev_fb.h
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@@ -38,4 +38,37 @@
#define NV_PFB_PRI_MMU_WPR2_ADDR_HI_VAL 31:4 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR2_ADDR_HI_ALIGNMENT 0x0000000c /* */
#define NV_PFB_PRI_MMU_FAULT_BUFFER_SIZE_VAL 19:0 /* RWEVF */
#define NV_PFB_PRI_MMU_FAULT_BUFFER_SIZE_VAL_RESET 0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FAULT_BUFFER_SIZE_OVERFLOW_INTR 29:29 /* RWEVF */
#define NV_PFB_PRI_MMU_FAULT_BUFFER_SIZE_OVERFLOW_INTR_DISABLE 0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FAULT_BUFFER_SIZE_OVERFLOW_INTR_ENABLE 0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_FAULT_BUFFER_SIZE_SET_DEFAULT 30:30 /* RWEVF */
#define NV_PFB_PRI_MMU_FAULT_BUFFER_SIZE_SET_DEFAULT_NO 0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FAULT_BUFFER_SIZE_SET_DEFAULT_YES 0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_FAULT_BUFFER_SIZE_ENABLE 31:31 /* RWEVF */
#define NV_PFB_PRI_MMU_FAULT_BUFFER_SIZE_ENABLE_FALSE 0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FAULT_BUFFER_SIZE_ENABLE_TRUE 0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_L2TLB_ECC_UNCORRECTED_ERR_COUNT 0x00100E78 /* RW-4R */
#define NV_PFB_PRI_MMU_L2TLB_ECC_UNCORRECTED_ERR_COUNT 0x00100E78 /* RW-4R */
#define NV_PFB_PRI_MMU_L2TLB_ECC_UNCORRECTED_ERR_COUNT_TOTAL 15:0 /* RWEVF */
#define NV_PFB_PRI_MMU_L2TLB_ECC_UNCORRECTED_ERR_COUNT_TOTAL_INIT 0 /* RWE-V */
#define NV_PFB_PRI_MMU_L2TLB_ECC_UNCORRECTED_ERR_COUNT_UNIQUE 31:16 /* RWEVF */
#define NV_PFB_PRI_MMU_L2TLB_ECC_UNCORRECTED_ERR_COUNT_UNIQUE_INIT 0 /* RWE-V */
#define NV_PFB_PRI_MMU_HUBTLB_ECC_UNCORRECTED_ERR_COUNT 0x00100E8C /* RW-4R */
#define NV_PFB_PRI_MMU_HUBTLB_ECC_UNCORRECTED_ERR_COUNT 0x00100E8C /* RW-4R */
#define NV_PFB_PRI_MMU_HUBTLB_ECC_UNCORRECTED_ERR_COUNT_TOTAL 15:0 /* RWEVF */
#define NV_PFB_PRI_MMU_HUBTLB_ECC_UNCORRECTED_ERR_COUNT_TOTAL_INIT 0 /* RWE-V */
#define NV_PFB_PRI_MMU_HUBTLB_ECC_UNCORRECTED_ERR_COUNT_UNIQUE 31:16 /* RWEVF */
#define NV_PFB_PRI_MMU_HUBTLB_ECC_UNCORRECTED_ERR_COUNT_UNIQUE_INIT 0 /* RWE-V */
#define NV_PFB_PRI_MMU_FILLUNIT_ECC_UNCORRECTED_ERR_COUNT 0x00100EA0 /* RW-4R */
#define NV_PFB_PRI_MMU_FILLUNIT_ECC_UNCORRECTED_ERR_COUNT 0x00100EA0 /* RW-4R */
#define NV_PFB_PRI_MMU_FILLUNIT_ECC_UNCORRECTED_ERR_COUNT_TOTAL 15:0 /* RWEVF */
#define NV_PFB_PRI_MMU_FILLUNIT_ECC_UNCORRECTED_ERR_COUNT_TOTAL_INIT 0 /* RWE-V */
#define NV_PFB_PRI_MMU_FILLUNIT_ECC_UNCORRECTED_ERR_COUNT_UNIQUE 31:16 /* RWEVF */
#define NV_PFB_PRI_MMU_FILLUNIT_ECC_UNCORRECTED_ERR_COUNT_UNIQUE_INIT 0 /* RWE-V */
#endif // __tu102_dev_fb_h__

29
src/common/inc/swref/published/turing/tu102/dev_fbpa.h Normal file
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@@ -0,0 +1,29 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __tu102_dev_fbpa_h_
#define __tu102_dev_fbpa_h_
#define NV_PFB_FBPA_0_ECC_DED_COUNT__SIZE_1 2 /* */
#define NV_PFB_FBPA_0_ECC_DED_COUNT(i) (0x00900488+(i)*4) /* RW-4A */
#endif // __tu102_dev_fbpa_h_

1
src/common/inc/swref/published/turing/tu102/dev_gc6_island.h
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@@ -24,6 +24,7 @@
#ifndef __tu102_dev_gc6_island_h__
#define __tu102_dev_gc6_island_h__
#define NV_PGC6 0x118fff:0x118000 /* RW--D */
#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_PRIV_LEVEL_MASK 0x00118128 /* RW-4R */
#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */

17
src/common/inc/swref/published/turing/tu102/dev_gsp.h
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@@ -38,5 +38,22 @@
#define NV_PGSP_QUEUE_HEAD(i) (0x110c00+(i)*8) /* RW-4A */
#define NV_PGSP_QUEUE_HEAD__SIZE_1 8 /* */
#define NV_PGSP_QUEUE_HEAD_ADDRESS 31:0 /* RWIVF */
#define NV_PGSP_EMEMC(i) (0x110ac0+(i)*8) /* RW-4A */
#define NV_PGSP_EMEMC__SIZE_1 4 /* */
#define NV_PGSP_EMEMC_OFFS 7:2 /* RWIVF */
#define NV_PGSP_EMEMC_OFFS_INIT 0x00000000 /* RWI-V */
#define NV_PGSP_EMEMC_BLK 15:8 /* RWIVF */
#define NV_PGSP_EMEMC_BLK_INIT 0x00000000 /* RWI-V */
#define NV_PGSP_EMEMC_AINCW 24:24 /* RWIVF */
#define NV_PGSP_EMEMC_AINCW_INIT 0x00000000 /* RWI-V */
#define NV_PGSP_EMEMC_AINCW_TRUE 0x00000001 /* RW--V */
#define NV_PGSP_EMEMC_AINCW_FALSE 0x00000000 /* RW--V */
#define NV_PGSP_EMEMC_AINCR 25:25 /* RWIVF */
#define NV_PGSP_EMEMC_AINCR_INIT 0x00000000 /* RWI-V */
#define NV_PGSP_EMEMC_AINCR_TRUE 0x00000001 /* RW--V */
#define NV_PGSP_EMEMC_AINCR_FALSE 0x00000000 /* RW--V */
#define NV_PGSP_EMEMD(i) (0x110ac4+(i)*8) /* RW-4A */
#define NV_PGSP_EMEMD__SIZE_1 4 /* */
#define NV_PGSP_EMEMD_DATA 31:0 /* RW-VF */
#endif // __tu102_dev_gsp_h__

33
src/common/inc/swref/published/turing/tu102/dev_ltc.h Normal file
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@@ -0,0 +1,33 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __tu102_dev_ltc_h_
#define __tu102_dev_ltc_h_
#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_UNCORRECTED_ERR_COUNT 0x001404f8 /* RW-4R */
#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_UNCORRECTED_ERR_COUNT_TOTAL 15:0 /* RWIVF */
#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_UNCORRECTED_ERR_COUNT_TOTAL_INIT 0x0000 /* RWI-V */
#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_UNCORRECTED_ERR_COUNT_UNIQUE 31:16 /* RWIVF */
#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_UNCORRECTED_ERR_COUNT_UNIQUE_INIT 0x0000 /* RWI-V */
#endif // __tu102_dev_ltc_h_

8
src/common/inc/swref/published/turing/tu102/dev_nv_xve.h
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@@ -24,6 +24,10 @@
#ifndef __tu102_dev_nv_xve_h__
#define __tu102_dev_nv_xve_h__
#define NV_PCFG 0x00088FFF:0x00088000 /* RW--D */
#define NV_XVE_ID 0x00000000 /* R--4R */
#define NV_XVE_ID_VENDOR 15:0 /* C--VF */
#define NV_XVE_ID_VENDOR_NVIDIA 0x000010DE /* C---V */
#define NV_XVE_SW_RESET 0x00000718 /* RW-4R */
#define NV_XVE_DEVICE_CAPABILITY 0x0000007C /* R--4R */
#define NV_XVE_DEVICE_CAPABILITY_FUNCTION_LEVEL_RESET 28:28 /* R-XVF */
#define NV_XVE_DEVICE_CAPABILITY_FUNCTION_LEVEL_RESET_NOT_SUPPORTED 0x00000000 /* R---V */
@@ -35,6 +39,10 @@
#define NV_XVE_MSIX_CAP_HDR_ENABLE 31:31 /* RWIVF */
#define NV_XVE_MSIX_CAP_HDR_ENABLE_ENABLED 0x00000001 /* RW--V */
#define NV_XVE_MSIX_CAP_HDR_ENABLE_DISABLED 0x00000000 /* RWI-V */
#define NV_XVE_PRIV_MISC_1 0x0000041C /* RW-4R */
#define NV_XVE_PRIV_MISC_1_CYA_HIDE_MSIX_CAP 29:29 /* RWCVF */
#define NV_XVE_PRIV_MISC_1_CYA_HIDE_MSIX_CAP_TRUE 0x00000001 /* RW--V */
#define NV_XVE_PRIV_MISC_1_CYA_HIDE_MSIX_CAP_FALSE 0x00000000 /* RWC-V */
#define NV_XVE_SRIOV_CAP_HDR3 0x00000BD8 /* R--4R */
#define NV_XVE_SRIOV_CAP_HDR3_TOTAL_VFS 31:16 /* R-EVF */
#define NV_XVE_SRIOV_CAP_HDR5 0x00000BE0 /* R--4R */

68
src/common/inc/swref/published/turing/tu102/dev_vm.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES
* SPDX-FileCopyrightText: Copyright (c) 2003-2023 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -23,6 +23,8 @@
#ifndef __tu102_dev_vm_h__
#define __tu102_dev_vm_h__
#define NV_VIRTUAL_FUNCTION_PRIV 0x0002FFFF:0x00000000 /* RW--D */
#define NV_VIRTUAL_FUNCTION 0x0003FFFF:0x00030000 /* RW--D */
#define NV_VIRTUAL_FUNCTION_FULL_PHYS_OFFSET 0x00BBFFFF:0x00B80000 /* RW--D */
#define NV_VIRTUAL_FUNCTION_PRIV_L2_SYSMEM_INVALIDATE 0x00000F00 /* RW-4R */
#define NV_VIRTUAL_FUNCTION_PRIV_L2_PEERMEM_INVALIDATE 0x00000F04 /* RW-4R */
@@ -97,7 +99,23 @@
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_PUT_OVERFLOW_YES 0x00000001 /* R---V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_SIZE(i) (0x00003010+(i)*32) /* RW-4A */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_SIZE__SIZE_1 2 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_SIZE_VAL 19:0 /* RWEVF */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_SIZE_VAL_RESET 0x00000000 /* RWE-V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_SIZE_OVERFLOW_INTR 29:29 /* RWEVF */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_SIZE_OVERFLOW_INTR_DISABLE 0x00000000 /* RWE-V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_SIZE_OVERFLOW_INTR_ENABLE 0x00000001 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_SIZE_SET_DEFAULT 30:30 /* RWEVF */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_SIZE_SET_DEFAULT_NO 0x00000000 /* RWE-V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_SIZE_SET_DEFAULT_YES 0x00000001 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_SIZE_ENABLE 31:31 /* RWEVF */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_SIZE_ENABLE_FALSE 0x00000000 /* RWE-V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_SIZE_ENABLE_TRUE 0x00000001 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_PAGE_FAULT_CTRL 0x00003070 /* RW-4R */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_ADDR_LO 0x00003080 /* R--4R */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_ADDR_HI 0x00003084 /* R--4R */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_INST_LO 0x00003088 /* R--4R */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_INST_HI 0x0000308C /* R--4R */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_INFO 0x00003090 /* R--4R */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_STATUS 0x00003094 /* RW-4R */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_PDB 0x000030A0 /* RW-4R */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_PDB_APERTURE 1:1 /* RWEVF */
@@ -210,5 +228,51 @@
#define NV_VIRTUAL_FUNCTION_PRIV_DOORBELL 0x2200 /* -W-4R */
#define NV_VIRTUAL_FUNCTION_DOORBELL 0x30090 /* -W-4R */
#define NV_VIRTUAL_FUNCTION_ERR_CONT 0x30094 /* R--4R */
#define NV_VIRTUAL_FUNCTION_PRIV_MSIX_TABLE_VECTOR_CONTROL__SIZE_1 6 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_BAR1_BLOCK 0x00000F40 /* RW-4R */
#define NV_VIRTUAL_FUNCTION_PRIV_BAR1_BLOCK__VFALIAS NV_VBUS_VF_BAR1_BLOCK(f) /* */
#define NV_VIRTUAL_FUNCTION_PRIV_BAR1_BLOCK_MAP 29:0 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_BAR1_BLOCK_PTR 27:0 /* RWIUF */
#define NV_VIRTUAL_FUNCTION_PRIV_BAR1_BLOCK_PTR_0 0x00000000 /* RWI-V */
#define NV_VIRTUAL_FUNCTION_PRIV_BAR1_BLOCK_TARGET 29:28 /* RWIUF */
#define NV_VIRTUAL_FUNCTION_PRIV_BAR1_BLOCK_TARGET_VID_MEM 0x00000000 /* RWI-V */
#define NV_VIRTUAL_FUNCTION_PRIV_BAR1_BLOCK_TARGET_SYS_MEM_COHERENT 0x00000002 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_BAR1_BLOCK_TARGET_SYS_MEM_NONCOHERENT 0x00000003 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_BAR1_BLOCK_MODE 31:31 /* RWIUF */
#define NV_VIRTUAL_FUNCTION_PRIV_BAR1_BLOCK_MODE_PHYSICAL 0x00000000 /* RWI-V */
#define NV_VIRTUAL_FUNCTION_PRIV_BAR1_BLOCK_MODE_VIRTUAL 0x00000001 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_BAR2_BLOCK 0x00000F48 /* RW-4R */
#define NV_VIRTUAL_FUNCTION_PRIV_BAR2_BLOCK__VFALIAS NV_VBUS_VF_BAR2_BLOCK(f) /* */
#define NV_VIRTUAL_FUNCTION_PRIV_BAR2_BLOCK_MAP 29:0 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_BAR2_BLOCK_PTR 27:0 /* RWIUF */
#define NV_VIRTUAL_FUNCTION_PRIV_BAR2_BLOCK_PTR_0 0x00000000 /* RWI-V */
#define NV_VIRTUAL_FUNCTION_PRIV_BAR2_BLOCK_TARGET 29:28 /* RWIUF */
#define NV_VIRTUAL_FUNCTION_PRIV_BAR2_BLOCK_TARGET_VID_MEM 0x00000000 /* RWI-V */
#define NV_VIRTUAL_FUNCTION_PRIV_BAR2_BLOCK_TARGET_SYS_MEM_COHERENT 0x00000002 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_BAR2_BLOCK_TARGET_SYS_MEM_NONCOHERENT 0x00000003 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_BAR2_BLOCK_DEBUG_CYA 30:30 /* RWIUF */
#define NV_VIRTUAL_FUNCTION_PRIV_BAR2_BLOCK_DEBUG_CYA_OFF 0x00000001 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_BAR2_BLOCK_DEBUG_CYA_ON 0x00000000 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_BAR2_BLOCK_DEBUG_CYA_INIT 0x00000001 /* RWI-V */
#define NV_VIRTUAL_FUNCTION_PRIV_BAR2_BLOCK_MODE 31:31 /* RWIUF */
#define NV_VIRTUAL_FUNCTION_PRIV_BAR2_BLOCK_MODE_PHYSICAL 0x00000000 /* RWI-V */
#define NV_VIRTUAL_FUNCTION_PRIV_BAR2_BLOCK_MODE_VIRTUAL 0x00000001 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_BIND_STATUS 0x00000F50 /* R--4R */
#define NV_VIRTUAL_FUNCTION_PRIV_BIND_STATUS__VFALIAS NV_VBUS_VF_BIND_STATUS(f) /* */
#define NV_VIRTUAL_FUNCTION_PRIV_BIND_STATUS_BAR1_PENDING 0:0 /* R-IUF */
#define NV_VIRTUAL_FUNCTION_PRIV_BIND_STATUS_BAR1_PENDING_EMPTY 0x00000000 /* R-I-V */
#define NV_VIRTUAL_FUNCTION_PRIV_BIND_STATUS_BAR1_PENDING_BUSY 0x00000001 /* R---V */
#define NV_VIRTUAL_FUNCTION_PRIV_BIND_STATUS_BAR1_OUTSTANDING 1:1 /* R-IUF */
#define NV_VIRTUAL_FUNCTION_PRIV_BIND_STATUS_BAR1_OUTSTANDING_FALSE 0x00000000 /* R-I-V */
#define NV_VIRTUAL_FUNCTION_PRIV_BIND_STATUS_BAR1_OUTSTANDING_TRUE 0x00000001 /* R---V */
#define NV_VIRTUAL_FUNCTION_PRIV_BIND_STATUS_BAR2_PENDING 2:2 /* R-IUF */
#define NV_VIRTUAL_FUNCTION_PRIV_BIND_STATUS_BAR2_PENDING_EMPTY 0x00000000 /* R-I-V */
#define NV_VIRTUAL_FUNCTION_PRIV_BIND_STATUS_BAR2_PENDING_BUSY 0x00000001 /* R---V */
#define NV_VIRTUAL_FUNCTION_PRIV_BIND_STATUS_BAR2_OUTSTANDING 3:3 /* R-IUF */
#define NV_VIRTUAL_FUNCTION_PRIV_BIND_STATUS_BAR2_OUTSTANDING_FALSE 0x00000000 /* R-I-V */
#define NV_VIRTUAL_FUNCTION_PRIV_BIND_STATUS_BAR2_OUTSTANDING_TRUE 0x00000001 /* R---V */
#define NV_VIRTUAL_FUNCTION_PRIV_MSIX_TABLE_VECTOR_CONTROL(i) (0x0001000C+(i)*16) /* RW-4A */
#define NV_VIRTUAL_FUNCTION_PRIV_MSIX_TABLE_VECTOR_CONTROL__SIZE_1 6 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_MSIX_TABLE_VECTOR_CONTROL_MASK_BIT 0:0 /* RWIVF */
#define NV_VIRTUAL_FUNCTION_PRIV_MSIX_TABLE_VECTOR_CONTROL_MASK_BIT_UNMASKED 0x00000000 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_MSIX_TABLE_VECTOR_CONTROL_MASK_BIT_MASKED 0x00000001 /* RWI-V */
#endif // __tu102_dev_vm_h__

7
src/common/inc/swref/published/turing/tu102/hwproject.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2021-2021 NVIDIA CORPORATION & AFFILIATES
* SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -25,5 +25,10 @@
#define __tu102_hwproject_h__
#define NV_CHIP_EXTENDED_SYSTEM_PHYSICAL_ADDRESS_BITS 47
#define NV_HOST_NUM_PBDMA 12
#define NV_SCAL_LITTER_NUM_FBPAS 16
#define NV_FBPA_PRI_STRIDE 16384
#define NV_LTC_PRI_STRIDE 8192
#define NV_LTS_PRI_STRIDE 512
#endif // __tu102_hwproject_h__