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This commit is contained in:
Bernhard Stoeckner
2024-01-24 17:51:53 +01:00
parent bb2dac1f20
commit 91676d6628
1411 changed files with 261367 additions and 145959 deletions
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19
src/common/sdk/nvidia/inc/cc_drv.h
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@@ -55,6 +55,17 @@ typedef enum ROTATE_IV_TYPE {
ROTATE_IV_ALL_VALID = 3, // Rotate the IV for all valid bundles in the KMB
} ROTATE_IV_TYPE;
// Status value written into NvNotification.Info16
typedef enum KEY_ROTATION_STATUS {
KEY_ROTATION_STATUS_IDLE = 0, // Key rotation complete/not in progress
KEY_ROTATION_STATUS_PENDING = 1, // RM is waiting for clients to report their channels are idle for key rotation
KEY_ROTATION_STATUS_IN_PROGRESS = 2, // Key rotation is in progress
KEY_ROTATION_STATUS_FAILED_TIMEOUT = 3, // Key rotation timeout failure, RM will RC non-idle channels
KEY_ROTATION_STATUS_FAILED_THRESHOLD = 4, // Key rotation failed because upper threshold was crossed, RM will RC non-idle channels
KEY_ROTATION_STATUS_FAILED_ROTATION = 5, // Internal RM failure while rotating keys for a certain channel, RM will RC the channel.
KEY_ROTATION_STATUS_MAX_COUNT = 6,
} KEY_ROTATION_STATUS;
typedef struct CC_AES_CRYPTOBUNDLE {
NvU32 iv[CC_AES_256_GCM_IV_SIZE_DWORD];
NvU32 key[CC_AES_256_GCM_KEY_SIZE_DWORD];
@@ -79,3 +90,11 @@ typedef struct CC_KMB {
} CC_KMB;
typedef struct CC_KMB *PCC_KMB;
typedef struct CC_CRYPTOBUNDLE_STATS {
NV_DECLARE_ALIGNED(NvU64 numEncryptionsH2D, 8);
NV_DECLARE_ALIGNED(NvU64 numEncryptionsD2H, 8);
NV_DECLARE_ALIGNED(NvU64 bytesEncryptedH2D, 8);
NV_DECLARE_ALIGNED(NvU64 bytesDecryptedD2H, 8);
} CC_CRYPTOBUNDLE_STATS;
typedef struct CC_CRYPTOBUNDLE_STATS *PCC_CRYPTOBUNDLE_STATS;

2
src/common/sdk/nvidia/inc/class/cl00de.h
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@@ -36,6 +36,8 @@ extern "C" {
#define RUSD_TIMESTAMP_WRITE_IN_PROGRESS (NV_U64_MAX)
#define RUSD_TIMESTAMP_INVALID 0
#define RUSD_SEQ_DATA_VALID(x) ((((NvU32)(x)) & 0x1U) == 0)
enum {
RUSD_CLK_PUBLIC_DOMAIN_GRAPHICS = 0,
RUSD_CLK_PUBLIC_DOMAIN_MEMORY,

52
src/common/sdk/nvidia/inc/class/cl00e0.h
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@@ -30,10 +30,16 @@
// Source file: class/cl00e0.finn
//
#include "nvcfg_sdk.h"
#include "cl0080.h"
/*
* Class definition for exporting memory handles to a different RM client on the
* same or another node (OS).
*
* No memory is allocated or mapped using this class.
* Parented by hClient.
* NvRmDupObject() is not supported. Use NV_MEM_EXPORT_FLAGS_DUP_BY_UUID instead.
*/
#define NV_MEMORY_EXPORT (0xe0U) /* finn: Evaluated from "NV00E0_ALLOCATION_PARAMETERS_MESSAGE_ID" */
@@ -49,7 +55,47 @@ typedef struct NV_EXPORT_MEM_PACKET {
#define NV_MEM_EXPORT_FLAGS_DEFAULT 0x00000000
#define NV_MEM_EXPORT_FLAGS_DUP_BY_UUID 0x00000001
/*
* imexChannel [IN]
* Used to associated export object with an IMEX channel.
* When duping,
* - If the caller is not the privileged IMEX daemon, validate the caller
* is subscribed to the channel.
* - Validate that the imexChannel matches with that of the export object being
* duped.
*
* packet [IN/OUT]
* Bag of bits which uniquely identifies this object universally.
* - When a new object is allocated, "packet" is returned as output.
* - If NV_MEM_EXPORT_FLAGS_DUP_BY_UUID is provided, "packet" is used as
* input to duplicate the existing object.
*
* numMaxHandles [IN/OUT]
* Max number of memory handles to be attached to the export object.
* - Input when a new object is allocated.
* - Output When duplicating.
*
* flags [IN/OUT]
* One of NV_MEM_EXPORT_FLAGS_*
* - Input when a new object is allocated or duplicated.
* - Output when duplicating. The flags at the time of allocation are
* returned.
*
* metadata [IN/OUT]
* Private data about the export object (opaque to kernel mode)
* - Input when a new object is allocated.
* - Output When duplicating.
*
* deviceInstanceMask [OUT]
* Attached device instance mask
*
* giIdMasks [OUT]
* Attached GPU instance ID mask (MIG is currently not supported)
* Must be indexed using deviceInstanceMask.
*
* numCurHandles [OUT]
* Number of memory handles currently attached to the export object.
*/
#define NV00E0_ALLOCATION_PARAMETERS_MESSAGE_ID (0x00e0U)

64
src/common/sdk/nvidia/inc/class/cl00f1.h Normal file
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@@ -0,0 +1,64 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2022-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: class/cl00f1.finn
//
#define NV_IMEX_SESSION (0xf1U) /* finn: Evaluated from "NV00F1_ALLOCATION_PARAMETERS_MESSAGE_ID" */
#define NV00F1_ALLOC_FLAGS_DEFAULT 0
//
// Disables channel recovery on IMEX shutdown. This can lead to security
// issues. The flag is intended to be used for testing purpose only.
//
#define NV00F1_ALLOC_DISABLE_CHANNEL_RECOVERY NVBIT(0)
#define NV00F1_ALLOCATION_PARAMETERS_MESSAGE_ID (0x00f1U)
typedef struct NV00F1_ALLOCATION_PARAMETERS {
//
// capDescriptor is a file descriptor for UNIX RM clients, but a void
// pointer for windows RM clients.
//
// capDescriptor is transparent to RM clients i.e. RM's user-mode shim
// populates this field on behalf of clients.
//
NV_DECLARE_ALIGNED(NvU64 capDescriptor, 8);
// See NV00F1_ALLOC_FLAGS_xxx
NvU32 flags;
// OS event handle created with NvRmAllocOsEvent().
NV_DECLARE_ALIGNED(NvP64 pOsEvent, 8);
// Node ID which represent this OS/RM instance
NvU16 nodeId;
} NV00F1_ALLOCATION_PARAMETERS;

82
src/common/sdk/nvidia/inc/class/cl00f9.h Normal file
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@@ -0,0 +1,82 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: class/cl00f9.finn
//
#include "cl00e0.h"
/*
* Class definition for importing memory handles from a different RM client on
* the same or another node (OS).
*/
#define NV_MEMORY_FABRIC_IMPORT_V2 (0xf9U) /* finn: Evaluated from "NV00F9_ALLOCATION_PARAMETERS_MESSAGE_ID" */
/*
* imexChannel [IN]
* IMEX channel to be used for import. (Currently ignored, driver picks the
* appropriate channel)
*
* packet [DEPRECATED, use expPacket instead]
* Fabric packet which uniquely identifies this object universally.
*
* expPacket [IN]
* Export object (see cl00e0.h) identifier from which memory will be imported.
*
* index [IN]
* Index into the FLA handle array associated with the export UUID.
*
* flags [IN]
* For future use.
* Set to zero for default behavior.
*
* pOsEvent [IN]
* Optional OS event handle created with NvRmAllocOsEvent().
*
* id [IN]
* A 48-bit ID for this import call. The caller has freedom to uniqueness
* of the ID. RM would track the object uniquely using
* <packet.uuid + index + ID>.
*/
#define NV00F9_IMPORT_ID_MAX (NVBIT64(48) - 1)
#define NV00F9_IMPORT_ID_SHIFT 16
#define NV00F9_ALLOCATION_PARAMETERS_MESSAGE_ID (0x00f9U)
typedef struct NV00F9_ALLOCATION_PARAMETERS {
NvU32 imexChannel;
NV_EXPORT_MEM_PACKET expPacket;
NvU16 index;
NvU32 flags;
NV_DECLARE_ALIGNED(NvP64 pOsEvent, 8);
NV_DECLARE_ALIGNED(NvU64 id, 8);
} NV00F9_ALLOCATION_PARAMETERS;

71
src/common/sdk/nvidia/inc/class/cl00fb.h Normal file
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@@ -0,0 +1,71 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: class/cl00fb.finn
//
#include "cl00e0.h"
/*
* Class definition for referencing the imported fabric memory,
* NV_MEMORY_FABRIC_IMPORT_V2, using the export object UUID.
*
* A privileged fabric manager only class, parented by client.
*
* No fabric events will be generated during creation or destruction of
* this class.
*/
#define NV_MEMORY_FABRIC_IMPORTED_REF (0xfbU) /* finn: Evaluated from "NV00FB_ALLOCATION_PARAMETERS_MESSAGE_ID" */
/*
* exportUuid [IN]
* Universally unique identifier of the export object. This is extracted
* from a fabric packet.
*
* index [IN]
* Index of the export object to which the memory object is attached.
*
* flags [IN]
* Currently unused. Must be zero for now.
*
* id [IN]
* Import ID. An import request is uniquely identified using,
* <packet.uuid + index + ID>.
*/
#define NV00FB_ALLOCATION_PARAMETERS_MESSAGE_ID (0x00fbU)
typedef struct NV00FB_ALLOCATION_PARAMETERS {
NvU8 exportUuid[NV_MEM_EXPORT_UUID_LEN];
NvU16 index;
NvU32 flags;
NV_DECLARE_ALIGNED(NvU64 id, 8);
} NV00FB_ALLOCATION_PARAMETERS;

19
src/common/sdk/nvidia/inc/class/cl00fd.h
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@@ -36,8 +36,18 @@
#include "cl00e0.h"
#define NV_MEMORY_MULTICAST_FABRIC (0xfdU) /* finn: Evaluated from "NV00FD_ALLOCATION_PARAMETERS_MESSAGE_ID" */
/*
* expPacket [IN]
* Export object (see cl00e0.h) identifier from which memory will be imported.
*
* index [IN]
* Index of the export object to which the memory object is attached.
*/
/*
* alignment [IN]
@@ -62,6 +72,13 @@
#define NV_MEMORY_MULTICAST_FABRIC_PAGE_SIZE_512M 0x20000000
/*
* This flag must be passed if the object is created using export packet. Note
* when this flag is provided, the input params: alignment, allocSize,
* numGpus, pageSize won't be honored.
*/
#define NV_MEMORY_MULTICAST_FABRIC_ALLOC_FLAGS_USE_EXPORT_PACKET 0x00000001
#define NV00FD_ALLOCATION_PARAMETERS_MESSAGE_ID (0x00fdU)
@@ -69,6 +86,8 @@
typedef struct NV00FD_ALLOCATION_PARAMETERS {
NV_EXPORT_MEM_PACKET expPacket;
NvU16 index;
NV_DECLARE_ALIGNED(NvU64 alignment, 8);
NV_DECLARE_ALIGNED(NvU64 allocSize, 8);
NvU32 pageSize;

3
src/common/sdk/nvidia/inc/class/cl00fe.h
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@@ -41,6 +41,7 @@
#define NV_MEMORY_MAPPER_ALLOCATION_PARAMS_MESSAGE_ID (0x00FEU)
typedef struct NV_MEMORY_MAPPER_ALLOCATION_PARAMS {
NvBool unused;
NvHandle hSemaphoreSurface;
NvU32 maxQueueSize;
} NV_MEMORY_MAPPER_ALLOCATION_PARAMS;

15
src/common/sdk/nvidia/inc/class/cl2080_notification.h
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@@ -221,7 +221,11 @@ extern "C" {
#define NV2080_NOTIFIERS_RESERVED180 (180)
#define NV2080_NOTIFIERS_AUX_POWER_EVENT (181)
#define NV2080_NOTIFIERS_AUX_POWER_STATE_CHANGE (182)
#define NV2080_NOTIFIERS_MAXCOUNT (183)
#define NV2080_NOTIFIERS_RESERVED_183 (183) // Unused
#define NV2080_NOTIFIERS_GSP_PERF_TRACE (184)
#define NV2080_NOTIFIERS_INBAND_RESPONSE (185)
#define NV2080_NOTIFIERS_RESERVED_186 (186) // Unused
#define NV2080_NOTIFIERS_MAXCOUNT (187)
// Indexed GR notifier reference
#define NV2080_NOTIFIERS_GR(x) ((x == 0) ? (NV2080_NOTIFIERS_GR0) : (NV2080_NOTIFIERS_GR1 + (x - 1)))
@@ -330,7 +334,8 @@ extern "C" {
#define NV2080_ENGINE_TYPE_RESERVED3c (0x0000003c)
#define NV2080_ENGINE_TYPE_RESERVED3d (0x0000003d)
#define NV2080_ENGINE_TYPE_RESERVED3e (0x0000003e)
#define NV2080_ENGINE_TYPE_LAST (0x0000003f)
#define NV2080_ENGINE_TYPE_RESERVED3f (0x0000003f)
#define NV2080_ENGINE_TYPE_LAST (0x00000040)
#define NV2080_ENGINE_TYPE_ALLENGINES (0xffffffff)
//
@@ -507,7 +512,7 @@ typedef struct Nv2080HdmiFrlRequestNotificationRec {
NvU32 displayId;
} Nv2080HdmiFrlRequestNotification;
/*
/*
* Platform Power Mode event information
*/
typedef struct _NV2080_PLATFORM_POWER_MODE_CHANGE_STATUS {
@@ -516,8 +521,8 @@ typedef struct _NV2080_PLATFORM_POWER_MODE_CHANGE_STATUS {
NvU8 eventReason;
} NV2080_PLATFORM_POWER_MODE_CHANGE_STATUS;
#define NV2080_PLATFORM_POWER_MODE_CHANGE_INFO_INDEX 7:0
#define NV2080_PLATFORM_POWER_MODE_CHANGE_INFO_MASK 15:8
#define NV2080_PLATFORM_POWER_MODE_CHANGE_INFO_INDEX 7:0
#define NV2080_PLATFORM_POWER_MODE_CHANGE_INFO_MASK 15:8
#define NV2080_PLATFORM_POWER_MODE_CHANGE_INFO_REASON 23:16
/*

2
src/common/sdk/nvidia/inc/class/cl90cdtypes.h
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@@ -36,9 +36,11 @@ extern "C" {
#define NV_EVENT_BUFFER_RECORD_TYPE_VIDEO_TRACE (1)
#define NV_EVENT_BUFFER_RECORD_TYPE_FECS_CTX_SWITCH_V2 (2)
#define NV_EVENT_BUFFER_RECORD_TYPE_NVTELEMETRY_REPORT_EVENT_SYSTEM (4)
#define NV_EVENT_BUFFER_RECORD_TYPE_RATS_GSP_TRACE (8)
#define NV_EVENT_BUFFER_RECORD_TYPE_NVTELEMETRY_REPORT_EVENT_SUBDEVICE (132)
#define NV_EVENT_BUFFER_RECORD_TYPE_FECS_CTX_SWITCH (134)
#ifdef __cplusplus
}; /* extern "C" */
#endif

32
src/common/sdk/nvidia/inc/class/cla080.h Normal file
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@@ -0,0 +1,32 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2012-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: class/cla080.finn
//
#define KEPLER_DEVICE_VGPU 0x0000a080U

5
src/common/sdk/nvidia/inc/class/cla084.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -46,6 +46,8 @@
* swizzId [IN] -> Used only when MIG mode is enabled otherwise set
* to NV2080_CTRL_GPU_PARTITION_ID_INVALID.
* numChannels -> Used only when SRIOV is enabled. Must be a power of 2.
* placementId [IN] -> Used to provide placement ID of with heterogeneous timesliced vGPUs.
* Otherwise set to NVA081_PLACEMENT_ID_INVALID.
* bDisableDefaultSmcExecPartRestore - If set to true, SMC default execution partition
* save/restore will not be done in host-RM
* vgpuDeviceInstanceId -> Specifies the vGPU device instance per VM to be used
@@ -67,6 +69,7 @@ typedef struct NVA084_ALLOC_PARAMETERS {
NvU32 vmPid;
NvU32 numChannels;
NvU32 numPluginChannels;
NvU16 placementId;
VM_ID_TYPE vmIdType;
NV_DECLARE_ALIGNED(VM_ID guestVmId, 8);
NvBool bDisableDefaultSmcExecPartRestore;

209
src/common/sdk/nvidia/inc/class/cla0bc.h Normal file
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@@ -0,0 +1,209 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2012-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: class/cla0bc.finn
//
#define NVENC_SW_SESSION (0xa0bcU) /* finn: Evaluated from "NVA0BC_ALLOC_PARAMETERS_MESSAGE_ID" */
/*
* NVENC_SESSION_INFO_REGION_MAX_COUNT_V1
* Number of regions.
* Currently we have two regions.
* +---------+ <== Region 1 Start
* | Entry 1 |
* | Entry 2 |
* | ... |
* | Entry N |
* +---------+ <== Region 1 End, Region 2 Start.
* | Entry 1 |
* | Entry 2 |
* | ... |
* | Entry N |
* +---------+ <== Region 2 End
* Region 1 : Contains GPU timestamp of each frame when frame was submitted
* to encode by UMD.
* Region 2 : Two entries in this region for each frame. Start and end GPU
* timestamps of when GPU started and ended encoding a frame.
*/
#define NVENC_SESSION_INFO_REGION_MAX_COUNT_V1 2
/*
* NVENC_SESSION_INFO_ENTRY_V1
* This structure represents a single timestamp entry for a frame.
* frameId
* Frame id of the frame being submitted for encoding by UMD.
* reserved
* This is a reserved field. Unused.
* timestamp
* GPU timestamp.
*/
typedef struct NVENC_SESSION_INFO_ENTRY_V1 {
NvU32 frameId;
NvU32 reserved;
NV_DECLARE_ALIGNED(NvU64 timestamp, 8);
} NVENC_SESSION_INFO_ENTRY_V1;
/*
* NVENC_SESSION_INFO_REGION_1_ENTRY_V1
* This structure represents an entry in Region 1.
* submissionTSEntry
* Frame id and GPU timestamp of the time when the frame was submitted to
* encode by UMD.
*
* NVENC_SESSION_INFO_REGION_1_ENTRY_SIZE_V1
* Size of each entry in region 1.
*
* NVENC_SESSION_INFO_REGION_1_MAX_ENTRIES_COUNT_V1
* No of entries in region 1.
*
* NVENC_SESSION_INFO_REGION_1_V1
* This structure represents Region 1.
*
* NVENC_SESSION_INFO_REGION_1_SIZE_V1
* Size of region 1.
*
* NVENC_SESSION_INFO_REGION_1_OFFSET_V1
* First region, so offset is 0.
*/
typedef struct NVENC_SESSION_INFO_REGION_1_ENTRY_V1 {
NV_DECLARE_ALIGNED(NVENC_SESSION_INFO_ENTRY_V1 submissionTSEntry, 8);
} NVENC_SESSION_INFO_REGION_1_ENTRY_V1;
#define NVENC_SESSION_INFO_REGION_1_ENTRY_SIZE_V1 sizeof(NVENC_SESSION_INFO_REGION_1_ENTRY_V1)
#define NVENC_SESSION_INFO_REGION_1_MAX_ENTRIES_COUNT_V1 256
typedef struct NVENC_SESSION_INFO_REGION_1_V1 {
NV_DECLARE_ALIGNED(NVENC_SESSION_INFO_REGION_1_ENTRY_V1 frameInfo[NVENC_SESSION_INFO_REGION_1_MAX_ENTRIES_COUNT_V1], 8);
} NVENC_SESSION_INFO_REGION_1_V1;
#define NVENC_SESSION_INFO_REGION_1_SIZE_V1 sizeof(NVENC_SESSION_INFO_REGION_1_V1)
#define NVENC_SESSION_INFO_REGION_1_OFFSET_V1 0
/*
* NVENC_SESSION_INFO_REGION_2_ENTRY_V1
* This structure represents a complete entry in Region 2.
* startTSEntry
* Frame id and GPU timestamp of the time when frame encoding started.
* endTSEntry
* Frame id and GPU timestamp of the time when frame encoding ended.
*
* NVENC_SESSION_INFO_REGION_2_ENTRY_SIZE_V1
* Size of each entry in region 2.
*
* NVENC_SESSION_INFO_REGION_2_MAX_ENTRIES_COUNT_V1
* No of entries in region 2.
*
* NVENC_SESSION_INFO_REGION_2_V1
* This structure represents Region 2.
*
* NVENC_SESSION_INFO_REGION_2_SIZE_V1
* Size of region 2.
*
* NVENC_SESSION_INFO_REGION_2_OFFSET_V1
* Offset of region 2 from base.
*/
typedef struct NVENC_SESSION_INFO_REGION_2_ENTRY_V1 {
NV_DECLARE_ALIGNED(NVENC_SESSION_INFO_ENTRY_V1 startTSEntry, 8);
NV_DECLARE_ALIGNED(NVENC_SESSION_INFO_ENTRY_V1 endTSEntry, 8);
} NVENC_SESSION_INFO_REGION_2_ENTRY_V1;
#define NVENC_SESSION_INFO_REGION_2_ENTRY_SIZE_V1 sizeof(NVENC_SESSION_INFO_REGION_2_ENTRY_V1)
#define NVENC_SESSION_INFO_REGION_2_MAX_ENTRIES_COUNT_V1 NVENC_SESSION_INFO_REGION_1_MAX_ENTRIES_COUNT_V1
typedef struct NVENC_SESSION_INFO_REGION_2_V1 {
NV_DECLARE_ALIGNED(NVENC_SESSION_INFO_REGION_2_ENTRY_V1 frameInfo[NVENC_SESSION_INFO_REGION_2_MAX_ENTRIES_COUNT_V1], 8);
} NVENC_SESSION_INFO_REGION_2_V1;
#define NVENC_SESSION_INFO_REGION_2_SIZE_V1 sizeof(NVENC_SESSION_INFO_REGION_2_V1)
#define NVENC_SESSION_INFO_REGION_2_OFFSET_V1 (NVENC_SESSION_INFO_REGION_1_OFFSET_V1 + \
NVENC_SESSION_INFO_REGION_1_SIZE_V1)
/*
* NVENC_SESSION_INFO_V1
* This structure represents the complete memory allocated to store the per
* frame submission-start-end timestamps data.
*
* NVENC_SESSION_INFO_SIZE_V1
* Size of complete memory.
*/
typedef struct NVENC_SESSION_INFO_V1 {
NV_DECLARE_ALIGNED(NVENC_SESSION_INFO_REGION_1_V1 region1, 8);
NV_DECLARE_ALIGNED(NVENC_SESSION_INFO_REGION_2_V1 region2, 8);
} NVENC_SESSION_INFO_V1;
#define NVENC_SESSION_INFO_SIZE_V1 sizeof(NVENC_SESSION_INFO_V1)
/*
* NVA0BC_ALLOC_PARAMETERS
*
* This structure represents NVENC SW session allocation parameters.
*
* codecType
* Codec type to be used to do the encoding.
* hResolution
* Width of frames to be encoded.
* vResolution
* Height of frames to be encoded.
* version
* Adding version to handle any future changes to struct.
* In future we can extend this struct to notify RM that UMD needs to send
* other data. Versioning will help in identifying the difference in structs.
* Values are defined by NVA0BC_ALLOC_PARAMS_VER_xxx.
* hMem
* Handle to the system memory allocated by UMD.
* RM needs to access the memory to get the raw timestamp data and process it.
*/
#define NVA0BC_ALLOC_PARAMETERS_MESSAGE_ID (0xa0bcU)
typedef struct NVA0BC_ALLOC_PARAMETERS {
NvU32 codecType;
NvU32 hResolution;
NvU32 vResolution;
NvU32 version;
NvHandle hMem;
} NVA0BC_ALLOC_PARAMETERS;
#define NVA0BC_ALLOC_PARAMS_VER_0 0x00000000
#define NVA0BC_ALLOC_PARAMS_VER_1 0x00000001
#define NVA0BC_NVENC_SESSION_CODEC_TYPE_H264 0x000000
#define NVA0BC_NVENC_SESSION_CODEC_TYPE_HEVC 0x000001
#define NVA0BC_NVENC_SESSION_CODEC_TYPE_AV1 0x000002
#define NVA0BC_NVENC_SESSION_CODEC_TYPE_UNKNOWN 0x0000FF

81
src/common/sdk/nvidia/inc/class/cla0bd.h Normal file
View File

@@ -0,0 +1,81 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2012-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: class/cla0bd.finn
//
#define NVFBC_SW_SESSION (0xa0bdU) /* finn: Evaluated from "NVA0BD_ALLOC_PARAMETERS_MESSAGE_ID" */
/*
* NVA0BD_ALLOC_PARAMETERS
*
* displayOrdinal
* This parameter specifies the display identifier.
* sessionType
* This parameter NVFBC session type. Possible values are specified
* by NVA0BD_NVFBC_SESSION_TYPE_* macros.
* sessionFlags
* This parameter returns various flags values of the NVFBC session.
* Valid flag values include:
* NVA0BD_NVFBC_SESSION_FLAG_DIFFMAP_ENABLED
* When true this flag indicates there are user has enabled
* diff map feature for the session.
* NVA0BD_NVFBC_SESSION_FLAG_CLASSIFICATIONMAP_ENABLED
* When true this flag indicates there are user has enabled
* diff map feature for the session.
* hMaxResolution
* This parameter returns the max horizontal resolution supported by
* the NvFBC session.
* vMaxResolution
* This parameter returns the max vertical resolution supported by
* the NvFBC session.
*/
#define NVA0BD_ALLOC_PARAMETERS_MESSAGE_ID (0xa0bdU)
typedef struct NVA0BD_ALLOC_PARAMETERS {
NvU32 displayOrdinal;
NvU32 sessionType;
NvU32 sessionFlags;
NvU32 hMaxResolution;
NvU32 vMaxResolution;
} NVA0BD_ALLOC_PARAMETERS;
#define NVA0BD_NVFBC_SESSION_TYPE_UNKNOWN 0x000000
#define NVA0BD_NVFBC_SESSION_TYPE_TOSYS 0x000001
#define NVA0BD_NVFBC_SESSION_TYPE_CUDA 0x000002
#define NVA0BD_NVFBC_SESSION_TYPE_VID 0x000003
#define NVA0BD_NVFBC_SESSION_TYPE_HWENC 0x000004
#define NVA0BD_NVFBC_SESSION_FLAG_DIFFMAP_ENABLED 0:0
#define NVA0BD_NVFBC_SESSION_FLAG_DIFFMAP_ENABLED_FALSE (0x00000000)
#define NVA0BD_NVFBC_SESSION_FLAG_DIFFMAP_ENABLED_TRUE (0x00000001)
#define NVA0BD_NVFBC_SESSION_FLAG_CLASSIFICATIONMAP_ENABLED 1:1
#define NVA0BD_NVFBC_SESSION_FLAG_CLASSIFICATIONMAP_ENABLED_FALSE (0x00000000)
#define NVA0BD_NVFBC_SESSION_FLAG_CLASSIFICATIONMAP_ENABLED_TRUE (0x00000001)

1
src/common/sdk/nvidia/inc/class/clc86f.h
View File

@@ -52,6 +52,7 @@ typedef volatile struct Nvc86fControl_struct {
#define NVC86F_SEM_PAYLOAD_HI (0x00000068)
#define NVC86F_SEM_EXECUTE (0x0000006c)
#define NVC86F_SEM_EXECUTE_OPERATION 2:0
#define NVC86F_SEM_EXECUTE_OPERATION_ACQUIRE 0x00000000
#define NVC86F_SEM_EXECUTE_OPERATION_RELEASE 0x00000001
#define NVC86F_SEM_EXECUTE_RELEASE_WFI 20:20
#define NVC86F_SEM_EXECUTE_RELEASE_WFI_DIS 0x00000000

3
src/common/sdk/nvidia/inc/class/clc86fsw.h
View File

@@ -35,7 +35,8 @@
#define NVC86F_NOTIFIERS_SW (6)
#define NVC86F_NOTIFIERS_GR_DEBUG_INTR (7)
#define NVC86F_NOTIFIERS_REPLAYABLE_FAULT (8)
#define NVC86F_NOTIFIERS_MAXCOUNT (9)
#define NVC86F_NOTIFIERS_KEY_ROTATION (9)
#define NVC86F_NOTIFIERS_MAXCOUNT (10)
/* NvNotification[] fields and values */
#define NVC86F_NOTIFICATION_STATUS_ERROR_BAD_ARGUMENT (0x2000)

2
src/common/sdk/nvidia/inc/class/clcba2.h
View File

@@ -118,6 +118,7 @@ typedef volatile struct _clcba2_tag0 {
// Class definitions
#define NVCBA2_DECRYPT_COPY_SIZE_MAX_BYTES (2*1024*1024)
#define NVCBA2_DECRYPT_SCRUB_SIZE_MAX_BYTES (1024*1024*1024)
// Errors
#define NVCBA2_ERROR_NONE (0x00000000)
@@ -149,6 +150,7 @@ typedef volatile struct _clcba2_tag0 {
#define NVCBA2_ERROR_SCRUBBER_INVALD_ADDRESS (0x0000001a)
#define NVCBA2_ERROR_SCRUBBER_INSUFFICIENT_PERMISSIONS (0x0000001b)
#define NVCBA2_ERROR_SCRUBBER_MUTEX_ACQUIRE_FAILURE (0x0000001c)
#define NVCBA2_ERROR_SCRUB_SIZE_MAX_EXCEEDED (0x0000001d)
#ifdef __cplusplus
}; /* extern "C" */

24
src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000client.h
View File

@@ -179,6 +179,30 @@ typedef struct NV0000_CTRL_CLIENT_OBJECTS_ARE_DUPLICATES_PARAMS {
NvBool bDuplicates; /* [out] - Returns true if duplicates */
} NV0000_CTRL_CLIENT_OBJECTS_ARE_DUPLICATES_PARAMS;
/*
* NV0000_CTRL_CMD_CLIENT_SUBSCRIBE_TO_IMEX_CHANNEL:
*
* Subscribes to the first accessible or provided channel.
* Subscription is valid throughout the lifetime of a client.
*
* devDescriptor [OPAQUE IN]
* devDescriptor is an IMEX file descriptor for UNIX RM clients, but a void
* pointer for windows RM clients. It is transparent to RM clients i.e. RM's
* user-mode shim populates this field on behalf of clients.
*
* channel [IN/OUT]
* Channel number to which the client is subscribed
* If -1 is passed, RM picks the first accessible channel.
*/
#define NV0000_CTRL_CMD_CLIENT_SUBSCRIBE_TO_IMEX_CHANNEL (0xd08) /* finn: Evaluated from "(FINN_NV01_ROOT_CLIENT_INTERFACE_ID << 8) | NV0000_CTRL_CLIENT_SUBSCRIBE_TO_IMEX_CHANNEL_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_CLIENT_SUBSCRIBE_TO_IMEX_CHANNEL_PARAMS_MESSAGE_ID (0x8U)
typedef struct NV0000_CTRL_CLIENT_SUBSCRIBE_TO_IMEX_CHANNEL_PARAMS {
NV_DECLARE_ALIGNED(NvU64 devDescriptor, 8);
NvU32 channel;
} NV0000_CTRL_CLIENT_SUBSCRIBE_TO_IMEX_CHANNEL_PARAMS;
/* _ctrl0000client_h_ */

68
src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000gpu.h
View File

@@ -1027,5 +1027,73 @@ typedef struct NV0000_CTRL_GPU_GET_ACTIVE_DEVICE_IDS_PARAMS {
NV0000_CTRL_GPU_ACTIVE_DEVICE devices[NV0000_CTRL_GPU_MAX_ACTIVE_DEVICES];
} NV0000_CTRL_GPU_GET_ACTIVE_DEVICE_IDS_PARAMS;
/*
* NV0000_CTRL_CMD_GPU_ASYNC_ATTACH_ID
*
* This command attaches the GPU with the given gpuId, similar to
* NV0000_CTRL_CMD_GPU_ATTACH_IDS. However, this command instructs the RM
* to perform the attach in the background.
*
* After calling this command, clients are expected to call
* NV0000_CTRL_CMD_GPU_WAIT_ATTACH_ID before performing any operation that
* depends on the GPU being attached.
*
* If the gpuId fails to attach, either this command or the subsequent
* NV0000_CTRL_CMD_GPU_WAIT_ATTACH_ID command may fail.
*
* If clients from multiple processes use this command or the
* NV0000_CTRL_CMD_GPU_ATTACH_IDS command to attach a gpuId, the RM ensures
* that the gpuId won't be detached until all processes have issued a call to
* NV0000_CTRL_CMD_GPU_DETACH_IDS to detach the gpuId (or have terminated).
*
* Possible status values returned are:
* NV_OK
* NV_ERR_OPERATING_SYSTEM
* NV_ERR_INVALID_PARAM_STRUCT
* NV_ERR_INVALID_ARGUMENT
*/
#define NV0000_CTRL_CMD_GPU_ASYNC_ATTACH_ID (0x289U) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_ASYNC_ATTACH_ID_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_GPU_ASYNC_ATTACH_ID_PARAMS_MESSAGE_ID (0x89U)
typedef struct NV0000_CTRL_GPU_ASYNC_ATTACH_ID_PARAMS {
NvU32 gpuId;
} NV0000_CTRL_GPU_ASYNC_ATTACH_ID_PARAMS;
/*
* NV0000_CTRL_CMD_GPU_WAIT_ATTACH_ID
*
* This command waits for and returns the status of a background attach
* operation started by NV0000_CTRL_CMD_GPU_ASYNC_ATTACH_ID.
*
* Clients are expected to call this command after calling
* NV0000_CTRL_CMD_GPU_ASYNC_ATTACH_ID before performing any operation that
* depends on the GPU being attached.
*
* If the gpuId fails to attach, either this command or the previous
* NV0000_CTRL_CMD_GPU_ASYNC_ATTACH_ID command may fail.
*
* Calling this command for a gpuId that is already attached (for example,
* after a successful NV0000_CTRL_CMD_GPU_ATTACH_IDS) is a no-op.
*
* Calling this command for a gpuId that is neither attached nor has a
* background attach operation will result in NV_ERR_INVALID_ARGUMENT.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_OPERATING_SYSTEM
* NV_ERR_INVALID_PARAM_STRUCT
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_IRQ_EDGE_TRIGGERED
* NV_ERR_IRQ_NOT_FIRING
*/
#define NV0000_CTRL_CMD_GPU_WAIT_ATTACH_ID (0x290U) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_WAIT_ATTACH_ID_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_GPU_WAIT_ATTACH_ID_PARAMS_MESSAGE_ID (0x90U)
typedef struct NV0000_CTRL_GPU_WAIT_ATTACH_ID_PARAMS {
NvU32 gpuId;
} NV0000_CTRL_GPU_WAIT_ATTACH_ID_PARAMS;
/* _ctrl0000gpu_h_ */

39
src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000system.h
View File

@@ -202,8 +202,8 @@ typedef struct NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_PARAMS {
* Vendor defined Model and Extended Model combined
* stepping
* Silicon stepping
* bSEVEnabled
* Secure Encrypted Virtualization enabled/disabled state
* bCCEnabled
* Confidentail compute enabled/disabled state
*
* Possible status values returned are:
* NV_OK
@@ -227,7 +227,7 @@ typedef struct NV0000_CTRL_SYSTEM_GET_CPU_INFO_PARAMS {
NvU32 model; /* Vendor defined Model and Extended Model combined */
NvU8 stepping; /* Silicon stepping */
NvU32 coresOnDie; /* cpu cores per die */
NvBool bSEVEnabled; /* SEV enabled on cpu */
NvBool bCCEnabled; /* CC enabled on cpu */
} NV0000_CTRL_SYSTEM_GET_CPU_INFO_PARAMS;
// Macros for CPU family information
@@ -418,28 +418,6 @@ typedef struct NV0000_CTRL_SYSTEM_GET_CHIPSET_INFO_PARAMS {
/*
* NV0000_CTRL_CMD_SYSTEM_SET_MEMORY_SIZE
*
* This command is used to set the system memory size in pages.
*
* memorySize
* This parameter specifies the system memory size in pages. All values
* are considered legal.
*
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_PARAM_STRUCT
*/
#define NV0000_CTRL_CMD_SYSTEM_SET_MEMORY_SIZE (0x107U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_SET_MEMORY_SIZE_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_SYSTEM_SET_MEMORY_SIZE_PARAMS_MESSAGE_ID (0x7U)
typedef struct NV0000_CTRL_SYSTEM_SET_MEMORY_SIZE_PARAMS {
NvU32 memorySize;
} NV0000_CTRL_SYSTEM_SET_MEMORY_SIZE_PARAMS;
/*
* NV0000_CTRL_CMD_SYSTEM_GET_LOCK_TIMES
*
@@ -467,7 +445,7 @@ typedef struct NV0000_CTRL_SYSTEM_SET_MEMORY_SIZE_PARAMS {
* NV_ERR_NOT_SUPPORTED
*/
#define NV0000_CTRL_CMD_SYSTEM_GET_LOCK_TIMES (0x109U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_LOCK_TIMES_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_CMD_SYSTEM_GET_LOCK_TIMES (0x109U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_LOCK_TIMES_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_SYSTEM_GET_LOCK_TIMES_PARAMS_MESSAGE_ID (0x9U)
@@ -1092,6 +1070,7 @@ typedef struct NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PARAMS {
NvU32 p2pOptimalWriteCEs;
NvU8 p2pCapsStatus[NV0000_CTRL_P2P_CAPS_INDEX_TABLE_SIZE];
NV_DECLARE_ALIGNED(NvP64 busPeerIds, 8);
NV_DECLARE_ALIGNED(NvP64 busEgmPeerIds, 8);
} NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PARAMS;
/* valid p2pCaps values */
@@ -1225,6 +1204,11 @@ typedef struct NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PARAMS {
* busPeerIds[X * gpuCount + Y] maps from index X to index Y in
* the gpuIds[] table. For invalid or non-existent peer busPeerIds[]
* has the value NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INVALID_PEER.
* [out] busEgmPeerIds
* EGM Peer ID matrix. It is a one-dimentional array.
* busEgmPeerIds[X * gpuCount + Y] maps from index X to index Y in
* the gpuIds[] table. For invalid or non-existent peer busEgmPeerIds[]
* has the value NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INVALID_PEER.
*
* Possible status values returned are:
* NV_OK
@@ -1246,6 +1230,7 @@ typedef struct NV0000_CTRL_SYSTEM_GET_P2P_CAPS_V2_PARAMS {
NvU32 p2pOptimalWriteCEs;
NvU8 p2pCapsStatus[NV0000_CTRL_P2P_CAPS_INDEX_TABLE_SIZE];
NvU32 busPeerIds[NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS_SQUARED];
NvU32 busEgmPeerIds[NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS_SQUARED];
} NV0000_CTRL_SYSTEM_GET_P2P_CAPS_V2_PARAMS;
/*
@@ -2178,8 +2163,6 @@ typedef struct NV0000_CTRL_CMD_SYSTEM_NVPCF_GET_POWER_MODE_INFO_PARAMS {
#define CONTROLLER_FILTER_TYPE_MOVING_MAX 1U
/* Valid NVPCF subfunction case */
#define NVPCF0100_CTRL_CONFIG_DSM_1X_FUNC_GET_SUPPORTED_CASE 0U
#define NVPCF0100_CTRL_CONFIG_DSM_1X_FUNC_GET_DYNAMIC_CASE 1U
#define NVPCF0100_CTRL_CONFIG_DSM_2X_FUNC_GET_SUPPORTED_CASE 2U
#define NVPCF0100_CTRL_CONFIG_DSM_2X_FUNC_GET_DYNAMIC_CASE 3U

50
src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073common.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2022-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -68,4 +68,52 @@ typedef struct NV0073_CTRL_CMD_DSC_CAP_PARAMS {
NvU32 maxNumHztSlices;
NvU32 lineBufferBitDepth;
} NV0073_CTRL_CMD_DSC_CAP_PARAMS;
/*
* NV0073_CTRL_CMD_FRL_CONFIG_MACRO_PAD
*
* subDeviceInstance
* This parameter specifies the subdevice instance within the
* NV04_DISPLAY_COMMON parent device to which the operation should be
* directed. This parameter must specify a value between zero and the
* total number of subdevices within the parent device. This parameter
* should be set to zero for default behavior
* cmd
* This parameter is an input to this command.
* Here are the current defined fields:
* NV0073_CTRL_CMD_FRL_CONFIG_MACRO_PAD_CMD_POWER
* Set to specify what operation to run.
* NV0073_CTRL_CMD_FRL_CONFIG_MACRO_PAD_CMD_POWER_UP
* Request to power up pad.
* NV0073_CTRL_CMD_FRL_CONFIG_MACRO_PAD_CMD_POWER_DOWN
* Request to power down the pad.
* linkBw
* This parameter is used to pass in the link bandwidth required to run the
* power up sequence. Refer enum DM_FRL_LINK_RATE_GBPS for valid values.
* laneCount
* This parameter is used to pass the lanecount.
* sorIndex
* This parameter is used to pass the SOR index.
* padlinkIndex
* This parameter is used to pass the padlink index for primary link.
* Please refer enum DFPPADLINK for valid index values for Link A~F.
*/
#define NV0073_CTRL_CMD_FRL_CONFIG_MACRO_PAD (0x730502U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_COMMON_INTERFACE_ID << 8) | NV0073_CTRL_CMD_FRL_CONFIG_MACRO_PAD_PARAMS_MESSAGE_ID" */
#define NV0073_CTRL_CMD_FRL_CONFIG_MACRO_PAD_PARAMS_MESSAGE_ID (0x2U)
typedef struct NV0073_CTRL_CMD_FRL_CONFIG_MACRO_PAD_PARAMS {
NvU32 subDeviceInstance;
NvU32 cmd;
NvU32 linkBw;
NvU32 laneCount;
NvU32 sorIndex;
NvU32 padlinkIndex;
} NV0073_CTRL_CMD_FRL_CONFIG_MACRO_PAD_PARAMS;
#define NV0073_CTRL_CMD_FRL_CONFIG_MACRO_PAD_CMD_POWER 0:0
#define NV0073_CTRL_CMD_FRL_CONFIG_MACRO_PAD_CMD_POWER_UP (0x00000000U)
#define NV0073_CTRL_CMD_FRL_CONFIG_MACRO_PAD_CMD_POWER_DOWN (0x00000001U)
/* _ctrl0073common_h_ */

30
src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073dfp.h
View File

@@ -946,7 +946,6 @@ typedef struct NV0073_CTRL_CMD_DFP_RUN_PRE_DISP_MUX_OPERATIONS_PARAMS {
#define NV0073_CTRL_DFP_DISP_MUX_FLAGS_SKIP_BACKLIGHT_ENABLE_NO 0x00000000U
#define NV0073_CTRL_DFP_DISP_MUX_FLAGS_SKIP_BACKLIGHT_ENABLE_YES 0x00000001U
#define NV0073_CTRL_DISP_MUX_BACKLIGHT_BRIGHTNESS_MIN 0U
#define NV0073_CTRL_DISP_MUX_BACKLIGHT_BRIGHTNESS_MAX 100U
@@ -1288,4 +1287,33 @@ typedef struct NV0073_CTRL_DFP_GET_FIXED_MODE_TIMING_PARAMS {
/*
* NV0073_CTRL_CMD_DFP_EDP_DRIVER_UNLOAD
*
* This command is called when we want to inform RM of driver
* unload.
*
* subDeviceInstance (in)
* This parameter specifies the subdevice instance within the
* NV04_DISPLAY_COMMON parent device to which the operation
* should be directed.
* displayId (in)
* This parameter inputs the displayId of the active display. A value
* of zero indicates no display is active.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_PARAM_STRUCT
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_NOT_SUPPORTED
*/
#define NV0073_CTRL_CMD_DFP_EDP_DRIVER_UNLOAD (0x731174U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DFP_INTERFACE_ID << 8) | NV0073_CTRL_DFP_EDP_DRIVER_UNLOAD_PARAMS_MESSAGE_ID" */
#define NV0073_CTRL_DFP_EDP_DRIVER_UNLOAD_PARAMS_MESSAGE_ID (0x74U)
typedef struct NV0073_CTRL_DFP_EDP_DRIVER_UNLOAD_PARAMS {
NvU32 subDeviceInstance;
NvU32 displayId;
} NV0073_CTRL_DFP_EDP_DRIVER_UNLOAD_PARAMS;
/* _ctrl0073dfp_h_ */

311
src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073dp.h
View File

@@ -771,41 +771,51 @@ typedef NV0073_CTRL_DP_LANE_DATA_PARAMS NV0073_CTRL_DP_SET_LANE_DATA_PARAMS;
/*
* NV0073_CTRL_DP_CSTM
*
* This structure specifies the 80 bit DP CSTM Test Pattern data
* The fields of this structure are to be specified as follows:
* lower takes bits 31:0
* middle takes bits 63:32
* upper takes bits 79:64
*
* This structure specifies -
* A) 80 bit DP CSTM Test Pattern data for DP1.x (HBR2 + 8b/10b channel coding)
* The fields of this structure are to be specified as follows:
* field_31_0 takes bits 31:0
* field_63_32 takes bits 63:32
* field_95_64 takes bits 79:64
* B) 264 bit DP CSTM Test Pattern data for DP2.x (128b/132b channel coding)
* The fields of this structure are to be specified as follows:
* field_31_0 contains bits 31:0
* field_63_32 contains bits 63:32
* field_95_64 contains bits 95:64
* field_127_95 contains bits 127:95
* field_159_128 contains bits 159:128
* field_191_160 contains bits 191:160
* field_223_192 contains bits 223:192
* field_255_224 contains bits 255:224
* field_263_256 contains bits 263:256
*/
typedef struct NV0073_CTRL_DP_CSTM {
NvU32 lower;
NvU32 middle;
NvU32 upper;
NvU32 field_31_0;
NvU32 field_63_32;
NvU32 field_95_64;
NvU32 field_127_95;
NvU32 field_159_128;
NvU32 field_191_160;
NvU32 field_223_192;
NvU32 field_255_224;
NvU32 field_263_256;
} NV0073_CTRL_DP_CSTM;
#define NV0073_CTRL_DP_SET_TESTPATTERN_PARAMS_CSTM2 15:0
#define NV0073_CTRL_DP_SET_TESTPATTERN_PARAMS_CSTM8 7:0
/*
* NV0073_CTRL_DP_TESTPATTERN
*
* This structure specifies the possible test patterns available in
* display port. The field testPattern can be one of the following
* values.
* NV0073_CTRL_DP_SET_TESTPATTERN_DATA_NONE
* No test pattern on the main link
* NV0073_CTRL_DP_SET_TESTPATTERN_DATA_D10_2
* D10.2 pattern on the main link
* NV0073_CTRL_DP_SET_TESTPATTERN_DATA_SERMP
* SERMP pattern on main link
* NV0073_CTRL_DP_SET_TESTPATTERN_DATA_PRBS_7
* PRBS7 pattern on the main link
*
* This structure specifies the possible test patterns available in display port.
*/
typedef struct NV0073_CTRL_DP_TESTPATTERN {
NvU32 testPattern;
} NV0073_CTRL_DP_TESTPATTERN;
#define NV0073_CTRL_DP_TESTPATTERN_DATA 2:0
#define NV0073_CTRL_DP_TESTPATTERN_DATA 4:0
#define NV0073_CTRL_DP_TESTPATTERN_DATA_NONE (0x00000000U)
#define NV0073_CTRL_DP_TESTPATTERN_DATA_D10_2 (0x00000001U)
#define NV0073_CTRL_DP_TESTPATTERN_DATA_SERMP (0x00000002U)
@@ -813,6 +823,20 @@ typedef struct NV0073_CTRL_DP_TESTPATTERN {
#define NV0073_CTRL_DP_TESTPATTERN_DATA_CSTM (0x00000004U)
#define NV0073_CTRL_DP_TESTPATTERN_DATA_HBR2COMPLIANCE (0x00000005U)
#define NV0073_CTRL_DP_TESTPATTERN_DATA_CP2520PAT3 (0x00000006U)
#define NV0073_CTRL_DP_TESTPATTERN_DATA_TRAINING1 (0x00000007U)
#define NV0073_CTRL_DP_TESTPATTERN_DATA_TRAINING2 (0x00000008U)
#define NV0073_CTRL_DP_TESTPATTERN_DATA_TRAINING3 (0x00000009U)
#define NV0073_CTRL_DP_TESTPATTERN_DATA_TRAINING4 (0x0000000AU)
#define NV0073_CTRL_DP_TESTPATTERN_DATA_CP2520PAT1 (0x0000000BU)
#define NV0073_CTRL_DP_TESTPATTERN_DATA_128B132B_TPS1 (0x0000000CU)
#define NV0073_CTRL_DP_TESTPATTERN_DATA_128B132B_TPS2 (0x0000000DU)
#define NV0073_CTRL_DP_TESTPATTERN_DATA_PRBS_9 (0x0000000EU)
#define NV0073_CTRL_DP_TESTPATTERN_DATA_PRBS_11 (0x0000000FU)
#define NV0073_CTRL_DP_TESTPATTERN_DATA_PRBS_15 (0x00000010U)
#define NV0073_CTRL_DP_TESTPATTERN_DATA_PRBS_23 (0x00000011U)
#define NV0073_CTRL_DP_TESTPATTERN_DATA_PRBS_31 (0x00000012U)
#define NV0073_CTRL_DP_TESTPATTERN_DATA_SQNUM (0x00000013U)
#define NV0073_CTRL_DP_TESTPATTERN_DATA_CSTM_264 (0x00000014U)
/*
* NV0073_CTRL_CMD_DP_SET_TESTPATTERN
@@ -880,10 +904,6 @@ typedef struct NV0073_CTRL_DP_SET_TESTPATTERN_PARAMS {
#define NV0073_CTRL_CMD_DP_SET_TESTPATTERN (0x731347U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_DP_SET_TESTPATTERN_PARAMS_MESSAGE_ID" */
#define NV0073_CTRL_DP_SET_TESTPATTERN_PARAMS_CSTM0 31:0
#define NV0073_CTRL_DP_SET_TESTPATTERN_PARAMS_CSTM1 63:32
#define NV0073_CTRL_DP_SET_TESTPATTERN_PARAMS_CSTM2 15:0
/*
* NV0073_CTRL_CMD_GET_DP_TESTPATTERN
*
@@ -2816,244 +2836,5 @@ typedef struct NV0073_CTRL_DP_EXECUTE_OVERDRIVE_POLICY_PARAMS {
NvU16 prodId;
} NV0073_CTRL_DP_EXECUTE_OVERDRIVE_POLICY_PARAMS;
/*
* NV0073_CTRL_CMD_DP2X_LINK_TRAINING_CTRL
*
* This command is used to trigger link training on DP2.x device with 128b132b channel encoding.
*
* subDeviceInstance
* This parameter specifies the subdevice instance within the
* NV04_DISPLAY_COMMON parent device to which the operation should be
* directed. This parameter must specify a value between zero and the
* total number of subdevices within the parent device. This parameter
* should be set to zero for default behavior.
*
* displayId
* This parameter specifies the ID of the display for which the dfp
* caps should be returned. The display ID must a dfp display.
* If more than one displayId bit is set or the displayId is not a dfp,
* this call will return NV_ERR_INVALID_ARGUMENT.
*
* cmd
* This parameter is an input to this command.
* Here are the current defined fields:
* 1.Ask RM to enter specific stage
* NV0073_CTRL_DP2X_CMD_LINK_TRAINING_SETTING
* NV0073_CTRL_DP2X_CMD_LINK_TRAINING_SET_CHNL_EQ
* _CDS
* _SET_* only valid if _SETTING_TRUE
*
* 2.Ask RM to check the completion of specific stage
* NV0073_CTRL_DP2X_CMD_LINK_TRAINING_POLLING
* NV0073_CTRL_DP2X_CMD_LINK_TRAINING_POLL_CHNL_EQ_DONE
* _CHNL_EQ_INTERLANE_ALIGN
* _CDS
* _POLL_* only valid if _POLLING_TRUE
*
* _SETTING_TRUE and _POLLING_TRUE are mutual exclusive.
* RM will return NV_ERR_INVALID_ARGUMENT if both bit are set.
*
* 3.Downspread configuration
* NV0073_CTRL_DP2X_CMD_FORCED_DOWNSPREAD
* Specifies whether RM should be forced to enable or disable the DP
* Downspread setting. This can be used along with the Fake link
* training option so that we can configure the GPU to enable/disable
* spread when a real display is not connected.
*
* NV0073_CTRL_DP2X_CMD_FORCED_DOWNSPREAD_NO (default behavior)
* RM will enable Downspread when the display supports it.
* NV0073_CTRL_DP2X_CMD_FORCED_DOWNSPREAD_YES
* RM will enable/disable Downspread according to _SET_DOWNSPREAD field.
*
* NV0073_CTRL_DP2X_CMD_SET_DOWNSPREAD
* Specifies if RM should enable or disable downspread.
* Only valid when _FORCED_DOWNSPREAD is set to _YES
*
* NV0073_CTRL_DP2X_CMD_SET_DOWNSPREAD_ENABLE
* RM will enable Downspread even if the display does not support it.
* NV0073_CTRL_DP2X_CMD_SET_DOWNSPREAD_DISABLE
* RM will not enable Downspread even if the display does support it.
*
* 4.NV0073_CTRL_DP2X_CMD_FAKE_LINK_TRAINING
* This field specifies if fake link training is to be done. This will
* program enough of the hardware to avoid any hardware hangs and
* depending upon option chosen by the client, OR will be enabled for
* transmisssion.
*
* NV0073_CTRL_DP2X_CMD_FAKE_LINK_TRAINING_NO
* No Fake LT will be performed
* NV0073_CTRL_DP2X_CMD_FAKE_LINK_TRAINING_DONOT_TOGGLE_TRANSMISSION
* SOR will be not powered up during Fake LT
* NV0073_CTRL_DP2X_CMD_FAKE_LINK_TRAINING_TOGGLE_TRANSMISSION_ON
* SOR will be powered up during Fake LT
*
* 5.NV0073_CTRL_DP2X_CMD_FALLBACK_CONFIG
*
* 6.NV0073_CTRL_DP2X_CMD_SKIP_HW_PROGRAMMING
* Specifies whether RM should skip HW training of the link.
* If this is the case then RM only updates its SW state without actually
* touching any HW registers. Clients should use this ONLY if it has determined -
* a. link is trained and not lost
* b. desired link config is same as current trained link config
* c. link is not in D3 (should be in D0)
*
* NV0073_CTRL_DP2X_CMD_SKIP_HW_PROGRAMMING_NO
* RM doesn't skip HW LT as the current Link Config is not the same as the
* requested Link Config.
* NV0073_CTRL_DP2X_CMD_SKIP_HW_PROGRAMMING_YES
* RM skips HW LT and only updates its SW state as client has determined that
* the current state of the link and the requested Link Config is the same.
* data
* This parameter is an input and output to this command.
* Here are the current defined fields:
* NV0073_CTRL_DP2X_DATA_LANE_COUNT
* Valid values: 0, 1, 2, 4
* NV0073_CTRL_DP2X_DATA_LINK_BW
* Valid values: all standard link rates defined in DP2.x and ILRs defined in eDP spec.
*
* pollingInfo
* This parameter is an output to this command.
* Here are the current defined fields:
*
* NV0073_CTRL_DP2X_POLLING_INFO_CHNL_EQ_INTERVAL
* For Channel equalization, the polling interval is defined in DPCD 0x2216.
* RM report to DPLib when _SET_STAGE is set to _CHNL_EQ.
* (For CDS stage, the polling interval is fixed at 3ms.)
*
* NV0073_CTRL_DP2X_POLLING_INFO_RESULT
* _DONE: if the specified stage is done.
* _PENDING: if the specified stage is still pending.
*
* err
* This parameter specifies provides info regarding the outcome
* of this calling control call. If zero, no errors were found.
* Otherwise, this parameter will specify the error detected.
* The valid parameter is broken down as follows:
* NV0073_CTRL_DP2X_ERR_CHANNEL_EQ_DONE
* If set to _ERR, link training failed at channel equalization phase.
* NV0073_CTRL_DP2X_ERR_CDS_DONE
* If set to _ERR, link training failed at CDS phase.
* NV0073_CTRL_DP2X_ERR_TIMEOUT
* If set to _ERR, link training failed because of timeout.
* NV0073_CTRL_DP2X_ERR_LT_FAILED
* If set to _ERR, link training failed.
* NV0073_CTRL_DP2X_ERR_INVALID_PARAMETER
* If set to _ERR, link configuration or displayID is invalid.
* NV0073_CTRL_DP2X_ERR_SET_LANE_COUNT
* If set to _ERR, link training failed when setting lane count.
* NV0073_CTRL_DP2X_ERR_SET_LINK_BW
* If set to _ERR, link training failed when setting link rate.
* NV0073_CTRL_DP2X_ERR_ENABLE_FEC
* If set to _ERR, link training failed when enabling FEC.
* NV0073_CTRL_DP2X_ERR_CONFIG_LTTPR
* If set to _ERR, link training failed when setting LTTPR.
* NV0073_CTRL_DP2X_ERR_PRE_LT
* If set to _ERR, link training failed before link training start.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
* NVOS_STATUS_ERROR
*/
#define NV0073_CTRL_CMD_DP2X_LINK_TRAINING_CTRL (0x731383U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_DP2X_LINK_TRAINING_CTRL_PARAMS_MESSAGE_ID" */
#define NV0073_CTRL_CMD_DP2X_LINK_TRAINING_CTRL_PARAMS_MESSAGE_ID (0x83U)
typedef struct NV0073_CTRL_CMD_DP2X_LINK_TRAINING_CTRL_PARAMS {
NvU32 subDeviceInstance;
NvU32 displayId;
NvU32 cmd;
NvU32 data;
NvU32 pollingInfo;
NvU32 err;
} NV0073_CTRL_CMD_DP2X_LINK_TRAINING_CTRL_PARAMS;
#define NV0073_CTRL_DP2X_CMD_LINK_TRAINING_SETTING 0:0
#define NV0073_CTRL_DP2X_CMD_LINK_TRAINING_SETTING_FALSE (0x00000000U)
#define NV0073_CTRL_DP2X_CMD_LINK_TRAINING_SETTING_TRUE (0x00000001U)
#define NV0073_CTRL_DP2X_CMD_LINK_TRAINING_SET 1:1
#define NV0073_CTRL_DP2X_CMD_LINK_TRAINING_SET_CHNL_EQ (0x00000000U)
#define NV0073_CTRL_DP2X_CMD_LINK_TRAINING_SET_CDS (0x00000001U)
#define NV0073_CTRL_DP2X_CMD_LINK_TRAINING_POLLING 8:8
#define NV0073_CTRL_DP2X_CMD_LINK_TRAINING_POLLING_FALSE (0x00000000U)
#define NV0073_CTRL_DP2X_CMD_LINK_TRAINING_POLLING_TRUE (0x00000001U)
#define NV0073_CTRL_DP2X_CMD_LINK_TRAINING_POLL 10:9
#define NV0073_CTRL_DP2X_CMD_LINK_TRAINING_POLL_CHNL_EQ_DONE (0x00000000U)
#define NV0073_CTRL_DP2X_CMD_LINK_TRAINING_POLL_CHNL_EQ_INTERLANE_ALIGN (0x00000001U)
#define NV0073_CTRL_DP2X_CMD_LINK_TRAINING_POLL_CDS (0x00000002U)
// Flags for link training.
#define NV0073_CTRL_DP2X_CMD_FORCED_DOWNSPREAD 16:16
#define NV0073_CTRL_DP2X_CMD_FORCED_DOWNSPREAD_NO (0x00000000U)
#define NV0073_CTRL_DP2X_CMD_FORCED_DOWNSPREAD_YES (0x00000001U)
#define NV0073_CTRL_DP2X_CMD_SET_DOWNSPREAD 17:17
#define NV0073_CTRL_DP2X_CMD_SET_DOWNSPREAD_DISABLE (0x00000000U)
#define NV0073_CTRL_DP2X_CMD_SET_DOWNSPREAD_ENABLE (0x00000001U)
#define NV0073_CTRL_DP2X_CMD_SKIP_HW_PROGRAMMING 18:18
#define NV0073_CTRL_DP2X_CMD_SKIP_HW_PROGRAMMING_NO (0x00000000U)
#define NV0073_CTRL_DP2X_CMD_SKIP_HW_PROGRAMMING_YES (0x00000001U)
#define NV0073_CTRL_DP2X_CMD_FAKE_LINK_TRAINING 20:19
#define NV0073_CTRL_DP2X_CMD_FAKE_LINK_TRAINING_NO (0x00000000U)
#define NV0073_CTRL_DP2X_CMD_FAKE_LINK_TRAINING_DONOT_TOGGLE_TRANSMISSION (0x00000001U)
#define NV0073_CTRL_DP2X_CMD_FAKE_LINK_TRAINING_TOGGLE_TRANSMISSION_ON (0x00000002U)
#define NV0073_CTRL_DP2X_CMD_FALLBACK_CONFIG 21:21
#define NV0073_CTRL_DP2X_CMD_FALLBACK_CONFIG_FALSE (0x00000000U)
#define NV0073_CTRL_DP2X_CMD_FALLBACK_CONFIG_TRUE (0x00000001U)
// Basic Data for Link training: Lane count and bandwidth.
#define NV0073_CTRL_DP2X_DATA_LANE_COUNT 3:0
#define NV0073_CTRL_DP2X_DATA_LANE_COUNT_0 (0x00000000U)
#define NV0073_CTRL_DP2X_DATA_LANE_COUNT_1 (0x00000001U)
#define NV0073_CTRL_DP2X_DATA_LANE_COUNT_2 (0x00000002U)
#define NV0073_CTRL_DP2X_DATA_LANE_COUNT_4 (0x00000004U)
#define NV0073_CTRL_DP2X_DATA_LINK_BW 7:4
#define NV0073_CTRL_DP2X_DATA_LINK_BW_1_62GBPS (0x00000001U)
#define NV0073_CTRL_DP2X_DATA_LINK_BW_2_16GBPS (0x00000002U)
#define NV0073_CTRL_DP2X_DATA_LINK_BW_2_43GBPS (0x00000003U)
#define NV0073_CTRL_DP2X_DATA_LINK_BW_2_70GBPS (0x00000004U)
#define NV0073_CTRL_DP2X_DATA_LINK_BW_3_24GBPS (0x00000005U)
#define NV0073_CTRL_DP2X_DATA_LINK_BW_4_32GBPS (0x00000006U)
#define NV0073_CTRL_DP2X_DATA_LINK_BW_5_40GBPS (0x00000007U)
#define NV0073_CTRL_DP2X_DATA_LINK_BW_6_75GBPS (0x00000008U)
#define NV0073_CTRL_DP2X_DATA_LINK_BW_8_10GBPS (0x00000009U)
#define NV0073_CTRL_DP2X_DATA_LINK_BW_UHBR10_0 (0x0000000AU)
#define NV0073_CTRL_DP2X_DATA_LINK_BW_UHBR13_5 (0x0000000BU)
#define NV0073_CTRL_DP2X_DATA_LINK_BW_UHBR20_0 (0x0000000CU)
#define NV0073_CTRL_DP2X_ERR_CHANNEL_EQ 0:0
#define NV0073_CTRL_DP2X_ERR_CHANNEL_EQ_DONE (0x00000000U)
#define NV0073_CTRL_DP2X_ERR_CHANNEL_EQ_FAILED (0x00000001U)
#define NV0073_CTRL_DP2X_ERR_CDS 1:1
#define NV0073_CTRL_DP2X_ERR_CDS_DONE (0x00000000U)
#define NV0073_CTRL_DP2X_ERR_CDS_FAILED (0x00000001U)
#define NV0073_CTRL_DP2X_ERR_TIMEOUT 2:2
#define NV0073_CTRL_DP2X_ERR_TIMEOUT_NO (0x00000000U)
#define NV0073_CTRL_DP2X_ERR_TIMEOUT_YES (0x00000001U)
#define NV0073_CTRL_DP2X_ERR_LT_FAILED 3:3
#define NV0073_CTRL_DP2X_ERR_LT_FAILED_NO (0x00000000U)
#define NV0073_CTRL_DP2X_ERR_LT_FAILED_YES (0x00000001U)
#define NV0073_CTRL_DP2X_ERR_INVALID_PARAMETER 4:4
#define NV0073_CTRL_DP2X_ERR_INVALID_PARAMETER_NOERR (0x00000000U)
#define NV0073_CTRL_DP2X_ERR_INVALID_PARAMETER_ERR (0x00000001U)
#define NV0073_CTRL_DP2X_ERR_SET_LANE_COUNT 5:5
#define NV0073_CTRL_DP2X_ERR_SET_LANE_COUNT_NOERR (0x00000000U)
#define NV0073_CTRL_DP2X_ERR_SET_LANE_COUNT_ERR (0x00000001U)
#define NV0073_CTRL_DP2X_ERR_SET_LINK_BW 6:6
#define NV0073_CTRL_DP2X_ERR_SET_LINK_BW_NOERR (0x00000000U)
#define NV0073_CTRL_DP2X_ERR_SET_LINK_BW_ERR (0x00000001U)
#define NV0073_CTRL_DP2X_ERR_ENABLE_FEC 7:7
#define NV0073_CTRL_DP2X_ERR_ENABLE_FEC_NOERR (0x00000000U)
#define NV0073_CTRL_DP2X_ERR_ENABLE_FEC_ERR (0x00000001U)
#define NV0073_CTRL_DP2X_ERR_CONFIG_LTTPR 8:8
#define NV0073_CTRL_DP2X_ERR_CONFIG_LTTPR_NOERR (0x00000000U)
#define NV0073_CTRL_DP2X_ERR_CONFIG_LTTPR_ERR (0x00000001U)
#define NV0073_CTRL_DP2X_ERR_PRE_LT 9:9
#define NV0073_CTRL_DP2X_ERR_PRE_LT_NOERR (0x00000000U)
#define NV0073_CTRL_DP2X_ERR_PRE_LT_ERR (0x00000001U)
#define NV0073_CTRL_DP2X_POLLING_INFO_CHNL_EQ_INTERVAL 7:0
#define NV0073_CTRL_DP2X_POLLING_INFO_RESULT 31:31
#define NV0073_CTRL_DP2X_POLLING_INFO_RESULT_PENDING (0x00000001U)
#define NV0073_CTRL_DP2X_POLLING_INFO_RESULT_DONE (0x00000000U)
/* _ctrl0073dp_h_ */

19
src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073internal.h
View File

@@ -30,6 +30,7 @@
#include "ctrl/ctrl0073/ctrl0073base.h"
#include "ctrl/ctrl0073/ctrl0073system.h"
#include "ctrl/ctrl0073/ctrl0073dfp.h"
#define NV0073_CTRL_CMD_INTERNAL_GET_HOTPLUG_UNPLUG_STATE (0x730401U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_INTERNAL_INTERFACE_ID << 8) | NV0073_CTRL_INTERNAL_GET_HOTPLUG_UNPLUG_STATE_PARAMS_MESSAGE_ID" */
@@ -43,4 +44,22 @@ typedef NV0073_CTRL_SYSTEM_GET_HOTPLUG_UNPLUG_STATE_PARAMS NV0073_CTRL_INTERNAL_
typedef NV0073_CTRL_CMD_SYSTEM_VRR_SET_RGLINE_ACTIVE_PARAMS NV0073_CTRL_CMD_INTERNAL_VRR_SET_RGLINE_ACTIVE_PARAMS;
#define NV0073_CTRL_CMD_INTERNAL_DFP_SWITCH_DISP_MUX (0x730460U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_INTERNAL_INTERFACE_ID << 8) | NV0073_CTRL_CMD_DFP_SWITCH_DISP_MUX_PARAMS_MESSAGE_ID" */
#define NV0073_CTRL_CMD_INTERNAL_DFP_SWITCH_DISP_MUX_PARAMS_MESSAGE_ID (0x3U)
typedef NV0073_CTRL_CMD_DFP_SWITCH_DISP_MUX_PARAMS NV0073_CTRL_CMD_INTERNAL_DFP_SWITCH_DISP_MUX_PARAMS;
#define NV0073_CTRL_CMD_INTERNAL_DFP_GET_DISP_MUX_STATUS (0x730404U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_INTERNAL_INTERFACE_ID << 8) | NV0073_CTRL_CMD_INTERNAL_DFP_GET_DISP_MUX_STATUS_PARAMS_MESSAGE_ID" */
#define NV0073_CTRL_CMD_INTERNAL_DFP_GET_DISP_MUX_STATUS_PARAMS_MESSAGE_ID (0x4U)
typedef NV0073_CTRL_CMD_DFP_GET_DISP_MUX_STATUS_PARAMS NV0073_CTRL_CMD_INTERNAL_DFP_GET_DISP_MUX_STATUS_PARAMS;
#define NV0073_CTRL_CMD_INTERNAL_VBLANK_SEM_CONTROL (0x730405U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_INTERNAL_INTERFACE_ID << 8) | NV0073_CTRL_CMD_INTERNAL_VBLANK_SEM_CONTROL_PARAMS_MESSAGE_ID" */
#define NV0073_CTRL_CMD_INTERNAL_VBLANK_SEM_CONTROL_PARAMS_MESSAGE_ID (0x5U)
typedef NV0073_CTRL_CMD_SYSTEM_VBLANK_SEM_CONTROL_PARAMS NV0073_CTRL_CMD_INTERNAL_VBLANK_SEM_CONTROL_PARAMS;
/* ctrl0073internal_h */

130
src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073specific.h
View File

@@ -126,8 +126,8 @@ typedef struct NV0073_CTRL_SPECIFIC_GET_TYPE_PARAMS {
* Perform the read and return an unadulterated EDID.
* NV0073_CTRL_SPECIFIC_GET_EDID_FLAGS_DISPMUX_READ_MODE
* A client uses this field to indicate whether to read EDID
* from SBIOS using ACPI sub function for display dynamic switching
* feature. This flag should only be set on internal display with
* from SBIOS using ACPI sub function for display dynamic switching
* feature. This flag should only be set on internal display with
* dynamic switching feature enabled.
* Possible values are:
* NV0073_CTRL_SPECIFIC_GET_EDID_FLAGS_DISPMUX_READ_MODE_ACPI
@@ -789,10 +789,10 @@ typedef struct NV0073_CTRL_SPECIFIC_GET_ALL_HEAD_MASK_PARAMS {
* It is temporal and will be deprecated soon.
* packetSize
* packet size of packets in pPacket to send, including header and payload.
* targetHead
* Specifies the target head number for which SDP needs to be updated.
* targetHead
* Specifies the target head number for which SDP needs to be updated.
* bUsePsrHeadforSdp
* Indicates use targetHead field for setting SDP or infoframe packet instead
* Indicates use targetHead field for setting SDP or infoframe packet instead
* of deriving the active head from displayID.
* pPacket
* pPacket points to the packets to send.
@@ -1346,7 +1346,7 @@ typedef struct NV0073_CTRL_SPECIFIC_SET_MONITOR_POWER_PARAMS {
* For FRL 4-lane configuration and 10 Gbps bandwidth per lane.
* NV0073_CTRL_HDMI_FRL_DATA_SET_FRL_RATE_4LANES_12G
* For FRL 4-lane configuration and 12 Gbps bandwidth per lane.
* On return, the link bandwidth setting is returned which may be
* On return, the link bandwidth setting is returned which may be
* different from the requested input setting.
* bFakeLt
* This flag as input to this command.
@@ -1406,7 +1406,7 @@ typedef struct NV0073_CTRL_CMD_SPECIFIC_GET_REGIONAL_CRCS_PARAMS {
* NV0073_CTRL_CMD_SPECIFIC_GET_REGIONAL_CRCS
*
* This command is used to capture the active viewport region CRCs
*
*
* [in]subDeviceInstance
* This parameter specifies the subdevice instance within the
* NV04_DISPLAY_COMMON parent device to which the operation should be
@@ -1502,13 +1502,13 @@ typedef struct NV0073_CTRL_SPECIFIC_GET_HDMI_GPU_CAPS_PARAMS {
/*
* NV0073_CTRL_CMD_SPECIFIC_DISPLAY_CHANGE
*
*
* Notifies the system that a display change is about to begin/end.
* Also performs the necessary synchronizations for the same.
*
*
* The command takes a NV0073_CTRL_SPECIFIC_DISPLAY_CHANGE_PARAMS structure as an
* argument with appropriate subDeviceInstance.
*
*
* [in]subDeviceInstance
* The sub-device instance
* [in]newDevices
@@ -1555,7 +1555,7 @@ typedef struct NV0073_CTRL_SPECIFIC_DISPLAY_CHANGE_PARAMS {
* NV04_DISPLAY_COMMON parent device to which the operation should be
* directed.
* displayId
* This parameter specifies the displayId of HDMI sink.
* This parameter specifies the displayId of HDMI sink.
* offset
* This parameter specifies the SCDC offset which the read operation
* should be used.
@@ -1639,7 +1639,7 @@ typedef struct NV0073_CTRL_SPECIFIC_IS_DIRECTMODE_DISPLAY_PARAMS {
* This parameter specifies the command for the HDMI FRL capacity computation.
* [in] input
* This parameter specifies the input data for the HDMI FRL capacity
* computation.
* computation.
* [out] result
* This indicates the computation result of HDMI FRL capacity computation.
* [in/out] preCalc
@@ -1727,7 +1727,7 @@ typedef struct NV0073_CTRL_SPECIFIC_GET_HDMI_FRL_CAPACITY_COMPUTATION_PARAMS {
* This generic packets can be used for both HDMI and DP.
* HW has added 6 new generic packets for each head because some usecases have
* requirement to send infoframe in particular location (vsync, vblank, loadV).
*
*
* Note: 1. Client first needs to reserve or acquire a free infoframe index
* using NV0073_CTRL_CMD_SPECIFIC_ACQUIRE_SHARED_GENERIC_PACKET.
* 2. Client needs to update the SDP index for head through control call
@@ -1753,7 +1753,7 @@ typedef struct NV0073_CTRL_SPECIFIC_GET_HDMI_FRL_CAPACITY_COMPUTATION_PARAMS {
* Set to _YES will cause new infoframe to be transmitted exactly once.
* Set to _NO will cause new infoframe to be transmitted every frame.
* NV0073_CTRL_SPECIFIC_SHARED_GENERIC_CTRL_LOC
* SDP can be sent in 3 different locations:
* SDP can be sent in 3 different locations:
* VBLANK - new infoframe will be sent at Vblank.
* VSYNC - new infoframe will be sent at Vsync.
* LOADV - new infoframe will be triggered by LOADV, and sent at Vsync
@@ -1765,9 +1765,9 @@ typedef struct NV0073_CTRL_SPECIFIC_GET_HDMI_FRL_CAPACITY_COMPUTATION_PARAMS {
* _DISABLE: do not override shared generic infoframe subpacker DB1 bit3.
* [in]packetSize
* size of packets in Packet array to send, including header and payload.
* [in]infoframeIndex
* [in]infoframeIndex
* Specifies the target head number for which SDP needs to be updated.
* [in]infoframeIndex
* [in]infoframeIndex
* Specifies the index of infoframe.
* [in]packet
* pPacket points to the packets to send.
@@ -1823,9 +1823,9 @@ typedef struct NV0073_CTRL_SPECIFIC_SET_SHARED_GENERIC_PACKET_PARAMS {
/*
* NV0073_CTRL_CMD_SPECIFIC_ACQUIRE_SHARED_GENERIC_PACKET
*
* This command is used to reserve the infoframe for head and RM would assign
* This command is used to reserve the infoframe for head and RM would assign
* free infoframe index and return the index of infoframe. Later client needs
* to call control call NV0073_CTRL_CMD_SPECIFIC_RELEASE_SHARED_GENERIC_PACKET
* to call control call NV0073_CTRL_CMD_SPECIFIC_RELEASE_SHARED_GENERIC_PACKET
* to release the index.
*
* [in]subDeviceInstance
@@ -1871,7 +1871,7 @@ typedef struct NV0073_CTRL_SPECIFIC_ACQUIRE_SHARED_GENERIC_PACKET_PARAMS {
* of subdevices within the parent device. This parameter should be set
* to zero for default behavior.
* [in]targetHeadIndex
* Specifies the target head number for which SDP needs to be updated.
* Specifies the target head number for which SDP needs to be updated.
* [in]infoframeIndex
* Infoframe index for the target head
* Possible status values returned are:
@@ -1994,4 +1994,96 @@ typedef struct NV0073_CTRL_SPECIFIC_DEFAULT_ADAPTIVESYNC_DISPLAY_PARAMS {
NvBool bDefaultAdaptivesync;
} NV0073_CTRL_SPECIFIC_DEFAULT_ADAPTIVESYNC_DISPLAY_PARAMS;
/*
* NV0073_CTRL_CMD_SPECIFIC_GET_DISPLAY_BRIGHTNESS_LTM
* NV0073_CTRL_CMD_SPECIFIC_SET_DISPLAY_BRIGHTNESS_LTM
* These commands retrieve and set the brightness level and Local Tone Mapping (LTM) settings for
* the specified display.
*
* subDeviceInstance
* This parameter specifies the subdevice instance within the
* NV04_DISPLAY_COMMON parent device to which the operation should be
* directed.
*
* displayId
* Display for which brightness/LTM settings is to be retrieved or set.
*
* brightnessMilliNits
* the display brightness in the millinits units in the [0,10000000] range, inclusive.
*
* transitionTimeMs
* the transition time for display brightness to transition from current brightness level to the brightnessMilliNits
*
* bUncalibrated
* if true the parameter indicates brightnessMilliNits has to be interpreted as brightness % value, in 0.001% units
*
* bAdaptiveBrightness
* if true the brightnessMilliNits is set by the OS in the response to the ambient light sensor (ALS) input (if present on the system)
*
* bBoostRange
* if true the brightnessMilliNits value is set by the OS in the response to the ambient light sensor (ALS) input (if present on the system)
* Indicating very bright ambient light environment
*
* ambientIlluminance
* if bAdaptiveBrightness = true, ambientIlluminance represents an ambient illuminance value reported by the ALS sensor, in 0.001 Lux units
*
* ambientChromaticityX
* if bAdaptiveBrightness = true, ambientChromaticityX represents X chromaticity value reported by ALS sensor, in 0.001 units of [0,1] range
*
* ambientChromaticityY
* if bAdaptiveBrightness = true, ambientChromaticityY represents Y chromaticity value reported by ALS sensor, in 0.001 units of [0,1] range
*
* bLtmEnable
* if set to true, enable LTM functionality in GPU display HW. Set to true by default.
*
* bEnhanceContrast
* if bLtmEnable = true, and if set to true, enhance local contrast via LTM regardless of any other contrast enhancement driver policies. Set to false by default.
*
* contrastGain
* if bLtmEnable = true, this is used to how gain we need to apply on the contrast.
*
* detailGain
* if bLtmEnable = true, how much details needs to be boosted is indicated by this parameter.
*
* bContentAdaptiveBrightness
* if bLtmEnable = true, and if set to true, modify display backlight level and adjust pixel values dynamically on per-frame basis to perform content adaptive brightness control to reduce display power. Set to false by default.
*
* bDynamicHdrTonemapping
* if bLtmEnable = true, and if set to true, and output is HDR, enable dynamic per frame HDR tonemapping. Set to false by default.
*
* Possible status values returned include:
* NV_OK
* NV_ERR_NOT_SUPPORTED
*/
typedef struct NV0073_CTRL_SPECIFIC_DISPLAY_BRIGHTNESS_LTM_PARAMS {
NvU32 subDeviceInstance;
NvU32 displayId;
NvU32 brightnessMilliNits;
NvU32 transitionTimeMs;
NvBool bUncalibrated;
NvBool bAdaptiveBrightness;
NvBool bBoostRange;
NvU32 ambientIlluminance;
NvU32 ambientChromaticityX;
NvU32 ambientChromaticityY;
NvBool bEnhanceContrast;
NvU16 contrastGain;
NvU16 detailGain;
NvBool bContentAdaptiveBrightness;
NvBool bDynamicHdrTonemapping;
} NV0073_CTRL_SPECIFIC_DISPLAY_BRIGHTNESS_LTM_PARAMS;
#define NV0073_CTRL_SPECIFIC_GET_DISPLAY_BRIGHTNESS_LTM_PARAMS_MESSAGE_ID (0xAFU)
typedef NV0073_CTRL_SPECIFIC_DISPLAY_BRIGHTNESS_LTM_PARAMS NV0073_CTRL_SPECIFIC_GET_DISPLAY_BRIGHTNESS_LTM_PARAMS;
#define NV0073_CTRL_CMD_SPECIFIC_GET_DISPLAY_BRIGHTNESS_LTM (0x7302afU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_SPECIFIC_GET_DISPLAY_BRIGHTNESS_LTM_PARAMS_MESSAGE_ID" */
#define NV0073_CTRL_SPECIFIC_SET_DISPLAY_BRIGHTNESS_LTM_PARAMS_MESSAGE_ID (0xB0U)
typedef NV0073_CTRL_SPECIFIC_DISPLAY_BRIGHTNESS_LTM_PARAMS NV0073_CTRL_SPECIFIC_SET_DISPLAY_BRIGHTNESS_LTM_PARAMS;
#define NV0073_CTRL_CMD_SPECIFIC_SET_DISPLAY_BRIGHTNESS_LTM (0x7302b0U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_SPECIFIC_SET_DISPLAY_BRIGHTNESS_LTM_PARAMS_MESSAGE_ID" */
/* _ctrl0073specific_h_ */

158
src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073system.h
View File

@@ -1468,8 +1468,8 @@ typedef struct NV0073_CTRL_SYSTEM_ARM_LIGHTWEIGHT_SUPERVISOR_PARAMS {
*
* bVrrDirty
* When set to NV_TRUE, indicates that vrr configuration has been changed
* When set to NV_FALSE, this will indicate transitions from One shot mode to
* Continuous mode and vice versa
* When set to NV_FALSE, this will indicate transitions from One shot mode to
* Continuous mode and vice versa
*
* bVrrEnabled
* When set to NV_TRUE, indicates that vrr has been enabled, i.e. vBp extended by 2 lines
@@ -1541,7 +1541,7 @@ typedef struct NV0073_CTRL_CMD_SYSTEM_QUERY_DISPLAY_IDS_WITH_MUX_PARAMS {
* because it exceeds the total bandwidth available to the system, or because
* too much bandwidth is already allocated to other clients), the call will
* fail and NV_ERR_INSUFFICIENT_RESOURCES will be returned.
*
*
* If bandwidth has already been allocated via a prior call, and a new
* allocation is requested, the new allocation will replace the old one. (If
* the new allocation fails, the old allocation remains in effect.)
@@ -1718,7 +1718,7 @@ typedef struct NV0073_CTRL_CMD_SYSTEM_CHECK_SIDEBAND_I2C_SUPPORT_PARAMS {
* This parameter inputs the displayId of the active display. A value
* of zero indicates no display is active.
* bIsSidebandSrSupported
* If it is true, it means that sideband is supported and not PSR API.
* If it is true, it means that sideband is supported and not PSR API.
*
* Possible status values returned are:
* NV_OK
@@ -1755,7 +1755,7 @@ typedef struct NV0073_CTRL_CMD_SYSTEM_CHECK_SIDEBAND_SR_SUPPORT_PARAMS {
* NV_ERR_GENERIC
*/
/*
/*
* This is the shared structure that will be used to communicate between
* Physical RM and clients. As of now the access relies on single source of
* truth operation, i.e. only Physical RM writes into the shared location
@@ -1791,5 +1791,153 @@ typedef struct NV0073_CTRL_CMD_SYSTEM_VRR_SET_RGLINE_ACTIVE_PARAMS {
NvHandle hMemory;
} NV0073_CTRL_CMD_SYSTEM_VRR_SET_RGLINE_ACTIVE_PARAMS;
/*
* NV0073_CTRL_CMD_SYSTEM_VBLANK_SEM_CONTROL
*
* The VBlank Semaphore Control API ("VBlank Sem Control") allows clients to
* register for a semaphore release to be performed on the specified memory.
*
* One or more clients may register a memory allocation + offset by specifying
* _PARAMS::bEnabled = NV_TRUE and describing a video memory object with
* _PARAMS::hMemory and an offset within that memory object
* (_PARAMS::memoryOffset). Until the hMemory + memoryOffset combination is
* disabled by a subsequent call with bEnabled = NV_FALSE, during each vblank on
* the specified head, RM will interpret the specified memory location as an
* NV0073_CTRL_CMD_SYSTEM_VBLANK_SEM_CONTROL_DATA data structure.
*
* _PARAMS::memoryOffset must be a multiple of 8, so that GPU semaphore releases
* and GSP can write to 8-byte fields within
* NV0073_CTRL_CMD_SYSTEM_VBLANK_SEM_CONTROL_DATA with natural alignment.
*
* During vblank, the _CONTROL_DATA::control field will be read, and the
* following pseudocode will be performed:
*
* swapInterval = DRF_VAL(data->flags)
* useMinimumGpuTime = DRV_VAL(data->flags)
*
* if (data->requestCounter == prevRequestCounter)
* return
*
* if (currentVblankCount < (prevVBlankCount + swapInterval))
* return
*
* if (useMinimumGpuTime && (data->minimumGpuTime < currentGpuTime))
* return
*
* data->vblankCount = currentVblankCount
* data->releaseGpuTime = currentGpuTime
* data->semaphore = data->requestCounter
*
* prevRequestCounter = data->requestCounter
* previousVblankCount = currentVblankCount
*
* I.e., if the client-described conditions are met, the RM will write
* _CONTROL_DATA::semaphore to the client-requested 'requestCounter' along with
* several informational fields (vblankCount, releaseGpuTime).
*
* The intent is for clients to use semaphore releases to write:
*
* _CONTROL_DATA::minimumGpuTime (if desired)
* _CONTROL_DATA::swapInterval
* _CONTROL_DATA::requestCounter
*
* and then perform a semaphore acquire on _CONTROL_DATA::semaphore >=
* requestCounter (using the ACQ_GEQ semaphore operation). This will block any
* following methods in the client's channel (e.g., a blit) until the requested
* conditions are met. Note the ::requestCounter should be written last,
* because the change in value of ::requestCounter is what causes RM, during a
* vblank callback, to inspect the other fields.
*
* Additionally, clients should use the CPU (not semaphore releases in their
* channel) to write the field _CONTROL_DATA::requestCounterAccel at the same
* time that they enqueue the semaphore release to write to
* _CONTROL_DATA::requestCounter. ::requestCounterAccel will be used by resman
* to "accelerate" the vblank sem control by copying the value from
* ::requestCounterAccel to ::semaphore. This will be done when the vblank sem
* control is disabled, and when a client calls
* NV0073_CTRL_CMD_SYSTEM_ACCEL_VBLANK_SEM_CONTROLS. It is important for resman
* to have access to the value in ::requestCounterAccel, and not just
* ::requestCounter. The latter is only the last value released so far by the
* client's channel (further releases to ::requestCounter may still be inflight,
* perhaps blocked on pending semaphore acquires). The former should be the
* most recent value enqueued in the channel. This is also why it is important
* for clients to acquire with ACQ_GEQ (greater-than-or-equal-to), rather than
* just ACQUIRE.
*
* The same hMemory (with difference memoryOffsets) may be used by multiple
* VBlank Sem Controls.
*/
/* Fields within NV0073_CTRL_CMD_SYSTEM_VBLANK_SEM_CONTROL_DATA::flags */
#define NV0073_CTRL_CMD_SYSTEM_VBLANK_SEM_CONTROL_SWAP_INTERVAL 15:0
#define NV0073_CTRL_CMD_SYSTEM_VBLANK_SEM_CONTROL_USE_MINIMUM_GPU_TIME 16:16
typedef struct NV0073_CTRL_CMD_SYSTEM_VBLANK_SEM_CONTROL_DATA {
NvU32 requestCounterAccel;
NvU32 requestCounter;
NvU32 flags;
NV_DECLARE_ALIGNED(NvU64 minimumGpuTime, 8);
NvU32 semaphore;
NV_DECLARE_ALIGNED(NvU64 vblankCount, 8);
NV_DECLARE_ALIGNED(NvU64 releaseGpuTime, 8);
} NV0073_CTRL_CMD_SYSTEM_VBLANK_SEM_CONTROL_DATA;
#define NV0073_CTRL_CMD_SYSTEM_VBLANK_SEM_CONTROL (0x73019fU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_CMD_SYSTEM_VBLANK_SEM_CONTROL_PARAMS_MESSAGE_ID" */
#define NV0073_CTRL_CMD_SYSTEM_VBLANK_SEM_CONTROL_PARAMS_MESSAGE_ID (0x9FU)
typedef struct NV0073_CTRL_CMD_SYSTEM_VBLANK_SEM_CONTROL_PARAMS {
NvU32 subDeviceInstance;
NvBool bEnable;
NvU32 head;
NvHandle hMemory;
NV_DECLARE_ALIGNED(NvU64 memoryOffset, 8);
} NV0073_CTRL_CMD_SYSTEM_VBLANK_SEM_CONTROL_PARAMS;
/*
* Accelerate all VBlank Sem Controls on the specified heads.
*
* For all enabled vblank sem controls on the specified heads, immediate set
* their pending ::semaphore fields to the value in their ::requestCounterAccel
* field.
*/
#define NV0073_CTRL_CMD_SYSTEM_ACCEL_VBLANK_SEM_CONTROLS (0x7301a2U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_CMD_SYSTEM_ACCEL_VBLANK_SEM_CONTROLS_PARAMS_MESSAGE_ID" */
#define NV0073_CTRL_CMD_SYSTEM_ACCEL_VBLANK_SEM_CONTROLS_PARAMS_MESSAGE_ID (0xA2U)
typedef struct NV0073_CTRL_CMD_SYSTEM_ACCEL_VBLANK_SEM_CONTROLS_PARAMS {
NvU32 subDeviceInstance;
NvU32 headMask;
} NV0073_CTRL_CMD_SYSTEM_ACCEL_VBLANK_SEM_CONTROLS_PARAMS;
/*
* Maps the memory allocated in Kernel RM into Physical RM using the
* memory descriptor information provided.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_NOT_SUPPORTED
*/
typedef struct NV0073_CTRL_SHARED_MEMDESC_INFO {
NV_DECLARE_ALIGNED(NvU64 base, 8);
NV_DECLARE_ALIGNED(NvU64 size, 8);
NV_DECLARE_ALIGNED(NvU64 alignment, 8);
NvU32 addressSpace;
NvU32 cpuCacheAttrib;
} NV0073_CTRL_SHARED_MEMDESC_INFO;
#define NV0073_CTRL_CMD_SYSTEM_MAP_SHARED_DATA (0x7301a3U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_CMD_SYSTEM_MAP_SHARED_DATA_PARAMS_MESSAGE_ID" */
#define NV0073_CTRL_CMD_SYSTEM_MAP_SHARED_DATA_PARAMS_MESSAGE_ID (0xA3U)
typedef struct NV0073_CTRL_CMD_SYSTEM_MAP_SHARED_DATA_PARAMS {
NV_DECLARE_ALIGNED(NV0073_CTRL_SHARED_MEMDESC_INFO memDescInfo, 8);
NvU32 subDeviceInstance;
NvBool bMap;
} NV0073_CTRL_CMD_SYSTEM_MAP_SHARED_DATA_PARAMS;
/* _ctrl0073system_h_ */

4
src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080bif.h
View File

@@ -62,7 +62,8 @@ typedef struct NV0080_CTRL_BIF_RESET_PARAMS {
NvU32 flags;
} NV0080_CTRL_BIF_RESET_PARAMS;
#define NV0080_CTRL_BIF_RESET_FLAGS_TYPE 3:0
#define NV0080_CTRL_BIF_RESET_FLAGS_TYPE 4:0
#define NV0080_CTRL_BIF_RESET_FLAGS_TYPE_SW_RESET 0x1
#define NV0080_CTRL_BIF_RESET_FLAGS_TYPE_SBR 0x2
#define NV0080_CTRL_BIF_RESET_FLAGS_TYPE_FUNDAMENTAL 0x3
@@ -70,6 +71,7 @@ typedef struct NV0080_CTRL_BIF_RESET_PARAMS {
#define NV0080_CTRL_BIF_RESET_FLAGS_TYPE_BOOT_DEVICE 0x5
#define NV0080_CTRL_BIF_RESET_FLAGS_TYPE_PEX 0x6
#define NV0080_CTRL_BIF_RESET_FLAGS_TYPE_OOBHUB_TRIGGER 0x7
#define NV0080_CTRL_BIF_RESET_FLAGS_TYPE_BASE 0x8
/*
* NV0080_CTRL_BIF_GET_DMA_BASE_SYSMEM_ADDR

29
src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080fb.h
View File

@@ -228,7 +228,36 @@ typedef struct NV0080_CTRL_FB_GET_CAPS_V2_PARAMS {
NvU8 capsTbl[NV0080_CTRL_FB_CAPS_TBL_SIZE];
} NV0080_CTRL_FB_GET_CAPS_V2_PARAMS;
/**
* NV0080_CTRL_CMD_FB_SET_DEFAULT_VIDMEM_PHYSICALITY
*
* When clients allocate video memory specifying _DEFAULT (0) for
* NVOS32_ATTR_PHYSICALITY, RM will usually allocate contiguous memory.
* Clients can change that behavior with this command so that _DEFAULT maps to
* another value.
*
* The expectation is that clients currently implicitly rely on the default,
* but can be incrementally updated to explicitly specify _CONTIGUOUS where
* necessary and change the default for their allocations to _NONCONTIGUOUS or
* _ALLOW_NONCONTIGUOUS.
*
* In the future RM may be updated to globally default to _NONCONTIGUOUS or
* _ALLOW_NONCONTIGUOUS, and at that point this can be removed.
*/
#define NV0080_CTRL_CMD_FB_SET_DEFAULT_VIDMEM_PHYSICALITY (0x801308) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_FB_INTERFACE_ID << 8) | NV0080_CTRL_FB_SET_DEFAULT_VIDMEM_PHYSICALITY_PARAMS_MESSAGE_ID" */
#define NV0080_CTRL_FB_SET_DEFAULT_VIDMEM_PHYSICALITY_PARAMS_MESSAGE_ID (0x8U)
typedef struct NV0080_CTRL_FB_SET_DEFAULT_VIDMEM_PHYSICALITY_PARAMS {
NvU32 value;
} NV0080_CTRL_FB_SET_DEFAULT_VIDMEM_PHYSICALITY_PARAMS;
typedef enum NV0080_CTRL_FB_DEFAULT_VIDMEM_PHYSICALITY {
NV0080_CTRL_FB_DEFAULT_VIDMEM_PHYSICALITY_DEFAULT = 0,
NV0080_CTRL_FB_DEFAULT_VIDMEM_PHYSICALITY_NONCONTIGUOUS = 1,
NV0080_CTRL_FB_DEFAULT_VIDMEM_PHYSICALITY_CONTIGUOUS = 2,
NV0080_CTRL_FB_DEFAULT_VIDMEM_PHYSICALITY_ALLOW_NONCONTIGUOUS = 3,
} NV0080_CTRL_FB_DEFAULT_VIDMEM_PHYSICALITY;
/* _ctrl0080fb_h_ */

3
src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080fifo.h
View File

@@ -190,7 +190,8 @@ typedef struct NV0080_CTRL_FIFO_START_SELECTED_CHANNELS_PARAMS {
#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_GFXP_CTRL_BLK (0x00000016)
#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_FECS_EVENT (0x00000017)
#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_PRIV_ACCESS_MAP (0x00000018)
#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_COUNT (0x00000019)
#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_SETUP (0x00000019)
#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_COUNT (0x0000001a)
#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_PARAMS_MESSAGE_ID (0x7U)
typedef struct NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_PARAMS {

100
src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080gpu.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2004-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2004-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -468,6 +468,9 @@ typedef struct NV0080_CTRL_GPU_GET_VGX_CAPS_PARAMS {
* bNonPowerOf2ChannelCountSupported
* Flag for whether non power of 2 VF channels are supported.
*
* bVfResizableBAR1Supported
* Flag for whether Resizable VF BAR1 capability is supported.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_NOT_SUPPORTED
@@ -494,11 +497,12 @@ typedef struct NV0080_CTRL_GPU_GET_SRIOV_CAPS_PARAMS {
NvBool bEmulateVFBar0TlbInvalidationRegister;
NvBool bClientRmAllocatedCtxBuffer;
NvBool bNonPowerOf2ChannelCountSupported;
NvBool bVfResizableBAR1Supported;
} NV0080_CTRL_GPU_GET_SRIOV_CAPS_PARAMS;
// Update this macro if new HW exceeds GPU Classlist MAX_SIZE
#define NV0080_CTRL_GPU_CLASSLIST_MAX_SIZE 160
#define NV0080_CTRL_GPU_CLASSLIST_MAX_SIZE 174
#define NV0080_CTRL_CMD_GPU_GET_CLASSLIST_V2 (0x800292) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GPU_INTERFACE_ID << 8) | NV0080_CTRL_GPU_GET_CLASSLIST_V2_PARAMS_MESSAGE_ID" */
@@ -550,32 +554,32 @@ typedef struct NV0080_CTRL_GPU_GET_BRAND_CAPS_PARAMS {
/*
* These are the per-VF BAR1 sizes that we support in MB.
* They are used with the NV0080_CTRL_GPU_SET_VGPU_VF_BAR1_SIZE control call and
* should match the NV_XVE_BAR1_CONFIG_SIZE register defines.
*/
#define NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_64M 64
#define NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_128M 128
#define NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_256M 256
#define NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_512M 512
#define NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_1G 1024
#define NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_2G 2048
#define NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_4G 4096
#define NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_8G 8192
#define NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_16G 16384
#define NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_32G 32768
#define NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_64G 65536
#define NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_128G 131072
#define NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_64M (1 << 6)
#define NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_128M (1 << 7)
#define NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_256M (1 << 8)
#define NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_512M (1 << 9)
#define NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_1G (1 << 10)
#define NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_2G (1 << 11)
#define NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_4G (1 << 12)
#define NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_8G (1 << 13)
#define NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_16G (1 << 14)
#define NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_32G (1 << 15)
#define NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_64G (1 << 16)
#define NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_128G (1 << 17)
#define NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_256G (1 << 18)
#define NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_MIN NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_64M
#define NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_MAX NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_128G
#define NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_MAX NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_256G
#define NV0080_CTRL_GPU_VGPU_NUM_VFS_INVALID NV_U32_MAX
#define NV0080_CTRL_GPU_VGPU_NUM_VFS_INVALID 0x0
/*
* NV0080_CTRL_GPU_SET_VGPU_VF_BAR1_SIZE
*
* @brief Resize BAR1 per-VF on the given GPU
* vfBar1SizeMB[in] size of per-VF BAR1 size in MB
* numVfs[out] number of VFs that can be created given the new BAR1 size
* vfBar1SizeMB[in] Requested VF BAR1 size in MB
* numVfs[out] Number of VFs that can be created
* given the requested BAR1 size
*/
#define NV0080_CTRL_GPU_SET_VGPU_VF_BAR1_SIZE (0x800296) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GPU_INTERFACE_ID << 8) | NV0080_CTRL_GPU_SET_VGPU_VF_BAR1_SIZE_PARAMS_MESSAGE_ID" */
@@ -586,4 +590,60 @@ typedef struct NV0080_CTRL_GPU_SET_VGPU_VF_BAR1_SIZE_PARAMS {
NvU32 numVfs;
} NV0080_CTRL_GPU_SET_VGPU_VF_BAR1_SIZE_PARAMS;
/*
* NV0080_CTRL_CMD_GPU_SET_VGPU_HETEROGENEOUS_MODE
*
* This command set a value indicating vGPU heterogeneous mode.
* vGPU heterogeneous mode on a GPU can only be set when the command
* is running in a vGPU host device.
*
* bHeterogeneousMode
* This parameter set the vGPU heterogeneous mode of the device.
* Possible values are:
* NV_TRUE
* This value indicates that the device will be associated with vGPU heterogeneous mode.
* NV_FALSE
* This value indicates that the device will be removed from vGPU heterogeneous mode.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_IN_USE
* NV_ERR_NOT_SUPPORTED
*/
#define NV0080_CTRL_CMD_GPU_SET_VGPU_HETEROGENEOUS_MODE (0x800297) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GPU_INTERFACE_ID << 8) | NV0080_CTRL_GPU_SET_VGPU_HETEROGENEOUS_MODE_PARAMS_MESSAGE_ID" */
#define NV0080_CTRL_GPU_SET_VGPU_HETEROGENEOUS_MODE_PARAMS_MESSAGE_ID (0x97U)
typedef struct NV0080_CTRL_GPU_SET_VGPU_HETEROGENEOUS_MODE_PARAMS {
NvBool bHeterogeneousMode;
} NV0080_CTRL_GPU_SET_VGPU_HETEROGENEOUS_MODE_PARAMS;
/**
* NV0080_CTRL_CMD_GPU_GET_VGPU_HETEROGENEOUS_MODE
*
* This command returns a value indicating vGPU heterogeneous mode of
* the GPU.
*
* bHeterogeneousMode
* This parameter returns the vGPU heterogeneous mode of the device.
* Possible values are:
* NV_TRUE
* This value indicates that the device is associated with vGPU heterogeneous mode.
* NV_FALSE
* This value indicates that the device is not in vGPU heterogeneous mode.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
*/
#define NV0080_CTRL_CMD_GPU_GET_VGPU_HETEROGENEOUS_MODE (0x800298) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GPU_INTERFACE_ID << 8) | NV0080_CTRL_GPU_GET_VGPU_HETEROGENEOUS_MODE_PARAMS_MESSAGE_ID" */
#define NV0080_CTRL_GPU_GET_VGPU_HETEROGENEOUS_MODE_PARAMS_MESSAGE_ID (0x98U)
typedef struct NV0080_CTRL_GPU_GET_VGPU_HETEROGENEOUS_MODE_PARAMS {
NvBool bHeterogeneousMode;
} NV0080_CTRL_GPU_GET_VGPU_HETEROGENEOUS_MODE_PARAMS;
/* _ctrl0080gpu_h_ */

2
src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080gr.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2004-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2004-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a

13
src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080internal.h
View File

@@ -30,7 +30,6 @@
// Source file: ctrl/ctrl0080/ctrl0080internal.finn
//
#include "nvlimits.h"
#include "ctrl0080gr.h"
#include "ctrl0080fifo.h"
#include "ctrl/ctrl0080/ctrl0080base.h"
@@ -89,18 +88,6 @@ typedef struct NV0080_CTRL_CMD_INTERNAL_GR_SET_TPC_PARTITION_MODE_FINN_PARAMS {
/*!
* @ref NV0080_CTRL_CMD_INTERNAL_PERF_GET_UNDERPOWERED_GPU_COUNT
*/
#define NV0080_CTRL_CMD_INTERNAL_PERF_GET_UNDERPOWERED_GPU_COUNT (0x802006) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV0080_CTRL_INTERNAL_PERF_GET_UNDERPOWERED_GPU_COUNT_PARAMS_MESSAGE_ID" */
#define NV0080_CTRL_INTERNAL_PERF_GET_UNDERPOWERED_GPU_COUNT_PARAMS_MESSAGE_ID (0x6U)
typedef struct NV0080_CTRL_INTERNAL_PERF_GET_UNDERPOWERED_GPU_COUNT_PARAMS {
NvU8 powerDisconnectedGpuBus[NV_MAX_DEVICES];
NvU8 powerDisconnectedGpuCount;
} NV0080_CTRL_INTERNAL_PERF_GET_UNDERPOWERED_GPU_COUNT_PARAMS;
/*
* NV0080_CTRL_CMD_INTERNAL_FIFO_RC_AND_PERMANENTLY_DISABLE_CHANNELS
*

19
src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080msenc.h
View File

@@ -68,6 +68,23 @@ typedef struct NV0080_CTRL_MSENC_GET_CAPS_PARAMS {
/* size in bytes of MSENC caps table */
#define NV0080_CTRL_MSENC_CAPS_TBL_SIZE 4
#define NV0080_CTRL_MSENC_CAPS_TBL_SIZE 4
/*
* NV0080_CTRL_CMD_MSENC_GET_CAPS_V2
*
* This command is a version of NV0080_CTRL_CMD_MSENC_GET_CAPS with caps passed inline in capsTbl.
*
* For consistency with other video caps controls, it adds `instanceId` parameter. Currently it is
* ignored.
*/
#define NV0080_CTRL_CMD_MSENC_GET_CAPS_V2 (0x801b02) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_MSENC_INTERFACE_ID << 8) | NV0080_CTRL_MSENC_GET_CAPS_V2_PARAMS_MESSAGE_ID" */
#define NV0080_CTRL_MSENC_GET_CAPS_V2_PARAMS_MESSAGE_ID (0x2U)
typedef struct NV0080_CTRL_MSENC_GET_CAPS_V2_PARAMS {
NvU8 capsTbl[NV0080_CTRL_MSENC_CAPS_TBL_SIZE];
NvU32 instanceId; // ignored
} NV0080_CTRL_MSENC_GET_CAPS_V2_PARAMS;
/* _ctrl0080msenc_h_ */

17
src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080perf.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2004-2019 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2004-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -43,6 +43,21 @@ typedef struct NV0080_CTRL_PERF_CUDA_LIMIT_CONTROL_PARAMS {
} NV0080_CTRL_PERF_CUDA_LIMIT_CONTROL_PARAMS;
/*
* This command sets the control information pertaining to Cuda limit.
*
* bCudaLimit
* When set to TRUE, clocks will be limited based on Cuda.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_INVALID_REQUEST
* NV_ERR_INVALID_STATE
*/
#define NV0080_CTRL_CMD_PERF_CUDA_LIMIT_SET_CONTROL (0x801909) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_PERF_INTERFACE_ID << 8) | NV0080_CTRL_PERF_CUDA_LIMIT_CONTROL_PARAMS_MESSAGE_ID" */
/* _ctrl0080perf_h_ */

158
src/common/sdk/nvidia/inc/ctrl/ctrl00e0.h Normal file
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@@ -0,0 +1,158 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl00e0.finn
//
#include "ctrl/ctrlxxxx.h"
#include "class/cl00e0.h"
#define NV00E0_CTRL_CMD(cat,idx) NVXXXX_CTRL_CMD(0x00E0, NV00E0_CTRL_##cat, idx)
/* NV00E0 command categories (6bits) */
#define NV00E0_CTRL_RESERVED (0x00U)
#define NV00E0_CTRL_MEMORY_EXPORT (0x01U)
/*
* NV00E0_CTRL_CMD_NULL
*
* This command does nothing.
* This command does not take any parameters.
*
* Possible status values returned are:
* NV_OK
*/
#define NV00E0_CTRL_CMD_NULL (0xe00000U) /* finn: Evaluated from "(FINN_NV_MEMORY_EXPORT_RESERVED_INTERFACE_ID << 8) | 0x0" */
/*
* NV00E0_CTRL_CMD_EXPORT_MEM
*
* Attaches memory handles to the export object.
*
* index [IN]
* Index into the export object at which to start attaching the provided
* memory handles.
*
* hParent [IN]
* Parent of memory handles to be attached (client or device or subdevice)
* If device or subdevice is used as parent, the related GPU is ref-counted
* by populating devDescriptor on behalf of the caller.
*
* handles [IN]
* Memory handles to be attached.
*
* numHandles [IN]
* Number of memory handles to be attached.
*
* devDescriptor [OPAQUE]
* devDescriptor is a file descriptor for unix RM clients, but a void
* pointer for windows RM clients. It is transparent to RM clients i.e. RM's
* user-mode shim populates this field on behalf of clients.
*
* Notes:
* - Imported fabric memory handles not supported.
* - No MIG support.
* - If 'numHandles' and 'index' overlap with a prior call, the newer call's
* RM handles will overwrite the attached handles from the previous call.
* This overlapping behavior can also be used to detach a handle by setting
* the appropriate object in 'handles' to 0.
*/
#define NV00E0_CTRL_CMD_EXPORT_MEM (0xe00101) /* finn: Evaluated from "(FINN_NV_MEMORY_EXPORT_INTERFACE_ID << 8) | NV00E0_CTRL_EXPORT_MEM_PARAMS_MESSAGE_ID" */
#define NV00E0_MAX_EXPORT_HANDLES 256
#define NV00E0_CTRL_EXPORT_MEM_PARAMS_MESSAGE_ID (0x1U)
typedef struct NV00E0_CTRL_EXPORT_MEM_PARAMS {
NvU16 index;
NvHandle hParent;
NvHandle handles[NV00E0_MAX_EXPORT_HANDLES];
NvU16 numHandles;
NV_DECLARE_ALIGNED(NvU64 devDescriptor, 8);
} NV00E0_CTRL_EXPORT_MEM_PARAMS;
/*
* NV00E0_CTRL_CMD_IMPORT_MEM
*
* Imports attached objects into the caller's RM client.
*
* index [IN]
* Index into the export object from which start importing.
*
* numHandles [IN]
* Number of memory handles to be imported.
*
* handles [IN]
* Handles to be used for importing.
*
* memInfos [OUT]
* Information of the imported objects
*/
#define NV00E0_CTRL_CMD_IMPORT_MEM (0xe00102) /* finn: Evaluated from "(FINN_NV_MEMORY_EXPORT_INTERFACE_ID << 8) | NV00E0_CTRL_IMPORT_MEM_PARAMS_MESSAGE_ID" */
#define NV00E0_MAX_IMPORT_HANDLES 128
#define NV00E0_ADDR_SPACE_TYPE_SYSMEM 0x1
#define NV00E0_ADDR_SPACE_TYPE_VIDMEM 0x2
#define NV00E0_ADDR_SPACE_TYPE_FABRIC 0x3
#define NV00E0_ADDR_SPACE_TYPE_FABRIC_MC 0x4
typedef struct NV_IMPORT_MEM_INFO {
NvHandle hParent;
NvU8 addrSpace;
} NV_IMPORT_MEM_INFO;
#define NV00E0_CTRL_IMPORT_MEM_PARAMS_MESSAGE_ID (0x2U)
typedef struct NV00E0_CTRL_IMPORT_MEM_PARAMS {
NvU16 index;
NvU16 numHandles;
NvHandle handles[NV00E0_MAX_IMPORT_HANDLES];
NV_IMPORT_MEM_INFO memInfos[NV00E0_MAX_IMPORT_HANDLES];
} NV00E0_CTRL_IMPORT_MEM_PARAMS;
/*
* NV00E0_CTRL_CMD_GET_INFO
*
* Returns object information
*
* info [OUT]
* Same as NV00E0_ALLOCATION_PARAMETERS, see cl00e0.h for details.
*/
#define NV00E0_CTRL_CMD_GET_INFO (0xe00103) /* finn: Evaluated from "(FINN_NV_MEMORY_EXPORT_INTERFACE_ID << 8) | NV00E0_CTRL_GET_INFO_PARAMS_MESSAGE_ID" */
#define NV00E0_CTRL_GET_INFO_PARAMS_MESSAGE_ID (0x3U)
typedef struct NV00E0_CTRL_GET_INFO_PARAMS {
NV00E0_ALLOCATION_PARAMETERS info;
} NV00E0_CTRL_GET_INFO_PARAMS;
/* _ctrl00e0_h_ */

233
src/common/sdk/nvidia/inc/ctrl/ctrl00f1.h Normal file
View File

@@ -0,0 +1,233 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2022-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl00f1.finn
//
#include "ctrl/ctrlxxxx.h"
#include "class/cl00e0.h"
/*
* NV00F1_CTRL_CMD_GET_FABRIC_EVENTS
*
* Queries the fabric object for events.
*
* eventArray [OUT]
* An array of import lifetime events.
*
* numEvents [OUT]
* The number of valid events in eventArray.
*
* bMoreEvents [OUT]
* Whether there are any remaining events to be queried.
*
* Possible status values returned are:
* NV_ERR_NOT_SUPPORTED
* NV_OK
*/
#define NV00F1_CTRL_CMD_GET_FABRIC_EVENTS (0xf10001U) /* finn: Evaluated from "(FINN_IMEX_SESSION_INTERFACE_ID << 8) | NV00F1_CTRL_GET_FABRIC_EVENTS_PARAMS_MESSAGE_ID" */
/* Event types */
#define NV00F1_CTRL_FABRIC_EVENT_TYPE_MEM_IMPORT 0U
#define NV00F1_CTRL_FABRIC_EVENT_TYPE_MEM_UNIMPORT 1U
#define NV00F1_CTRL_FABRIC_EVENT_TYPE_REMOTE_GPU_ATTACH 2U
#define NV00F1_CTRL_FABRIC_EVENT_TYPE_CLIQUE_ID_CHANGE 3U
/*
* id
* Import ID. An import request can be uniquely identified using,
* <packet.uuid + index + ID>.
*
* index
* Index of the export object to which the memory object is attached.
*
* exportNodeId
* ID of the exporter node where memory will be imported.
*
* exportUuid
* Universally unique identifier of the export object. This is extracted
* from a fabric packet.
*
*/
typedef struct NV00F1_CTRL_FABRIC_MEM_IMPORT_EVENT_DATA {
NV_DECLARE_ALIGNED(NvU64 id, 8);
NvU16 index;
NvU16 exportNodeId;
NvU8 exportUuid[NV_MEM_EXPORT_UUID_LEN];
} NV00F1_CTRL_FABRIC_MEM_IMPORT_EVENT_DATA;
/*
* importEventId
* ID of the corresponding import event.
*
* exportNodeId
* ID of the exporter node where memory will be unimported.
*/
typedef struct NV00F1_CTRL_FABRIC_MEM_UNIMPORT_EVENT_DATA {
NV_DECLARE_ALIGNED(NvU64 importEventId, 8);
NvU16 exportNodeId;
} NV00F1_CTRL_FABRIC_MEM_UNIMPORT_EVENT_DATA;
/*
* gpuFabricProbeHandle [IN]
* Fabric probe handle of the remote GPU
*
* key [IN]
* Key is used by the GFM in the MCFLA team response as an ID to allow the
* RM to correlate it with the MCFLA team request.
*
* cliqueId [IN]
* Clique ID of the remote GPU being attached.
*
* index
* Index of the export object to which the memory object is attached.
*
* exportNodeId
* ID of the exporter node where memory will be imported.
*
* exportUuid
* Universally unique identifier of the export object. This is extracted
* from a fabric packet.
*/
typedef struct NV00F1_CTRL_ATTACH_REMOTE_GPU_EVENT_DATA {
NV_DECLARE_ALIGNED(NvU64 gpuFabricProbeHandle, 8);
NV_DECLARE_ALIGNED(NvU64 key, 8);
NvU32 cliqueId;
NvU16 index;
NvU16 exportNodeId;
NvU8 exportUuid[NV_MEM_EXPORT_UUID_LEN];
} NV00F1_CTRL_ATTACH_REMOTE_GPU_EVENT_DATA;
/*
* gpuId
* GPU ID of the GPU whose cliqueID has changed.
*
* cliqueId
* Clique ID of the GPU.
*/
typedef struct NV00F1_CTRL_CLIQUE_ID_CHANGE_GPU_EVENT_DATA {
NvU32 gpuId;
NvU32 cliqueId;
} NV00F1_CTRL_CLIQUE_ID_CHANGE_GPU_EVENT_DATA;
/*
* type
* Event type, one of NV00F1_CTRL_FABRIC_EVENT_TYPE_*.
*
* id
* A monotonically increasing event ID.
*
* imexChannel
* imex channel subscribed by the caller.
*
* data
* Event data
*/
typedef struct NV00F1_CTRL_FABRIC_EVENT {
NvU8 type;
NV_DECLARE_ALIGNED(NvU64 id, 8);
NvU32 imexChannel;
union {
NV_DECLARE_ALIGNED(NV00F1_CTRL_FABRIC_MEM_IMPORT_EVENT_DATA import, 8);
NV_DECLARE_ALIGNED(NV00F1_CTRL_FABRIC_MEM_UNIMPORT_EVENT_DATA unimport, 8);
NV_DECLARE_ALIGNED(NV00F1_CTRL_ATTACH_REMOTE_GPU_EVENT_DATA attach, 8);
NV00F1_CTRL_CLIQUE_ID_CHANGE_GPU_EVENT_DATA cliqueIdChange;
} data;
} NV00F1_CTRL_FABRIC_EVENT;
#define NV00F1_CTRL_GET_FABRIC_EVENTS_ARRAY_SIZE 128U
#define NV00F1_CTRL_GET_FABRIC_EVENTS_PARAMS_MESSAGE_ID (0x1U)
typedef struct NV00F1_CTRL_GET_FABRIC_EVENTS_PARAMS {
NV_DECLARE_ALIGNED(NV00F1_CTRL_FABRIC_EVENT eventArray[NV00F1_CTRL_GET_FABRIC_EVENTS_ARRAY_SIZE], 8);
NvU32 numEvents;
NvBool bMoreEvents;
} NV00F1_CTRL_GET_FABRIC_EVENTS_PARAMS;
/*
* NV00F1_CTRL_CMD_FINISH_MEM_UNIMPORT
*
* Notifies the unimport sequence is finished.
*
* tokenArray [IN]
* An array of tokens that finished the unimport sequence.
*
* numTokens [IN]
* The number of valid tokens in the tokenArray.
*
* Possible status values returned are:
* NV_ERR_OBJECT_NOT_FOUND
* NV_ERR_NOT_SUPPORTED
* NV_OK
*/
#define NV00F1_CTRL_CMD_FINISH_MEM_UNIMPORT (0xf10002U) /* finn: Evaluated from "(FINN_IMEX_SESSION_INTERFACE_ID << 8) | NV00F1_CTRL_FINISH_MEM_UNIMPORT_PARAMS_MESSAGE_ID" */
/*
* unimportEventId
* ID of the unimport event.
*/
typedef struct NV00F1_CTRL_FABRIC_UNIMPORT_TOKEN {
NV_DECLARE_ALIGNED(NvU64 unimportEventId, 8);
} NV00F1_CTRL_FABRIC_UNIMPORT_TOKEN;
#define NV00F1_CTRL_FINISH_MEM_UNIMPORT_ARRAY_SIZE 256U
#define NV00F1_CTRL_FINISH_MEM_UNIMPORT_PARAMS_MESSAGE_ID (0x2U)
typedef struct NV00F1_CTRL_FINISH_MEM_UNIMPORT_PARAMS {
NV_DECLARE_ALIGNED(NV00F1_CTRL_FABRIC_UNIMPORT_TOKEN tokenArray[NV00F1_CTRL_FINISH_MEM_UNIMPORT_ARRAY_SIZE], 8);
NvU32 numTokens;
} NV00F1_CTRL_FINISH_MEM_UNIMPORT_PARAMS;
/*
* NV00F1_CTRL_CMD_DISABLE_IMPORTERS
*
* Disables clients which imported memory from the given nodeId. Channel
* recovery (disablement) sequence is also invoked to halt fabric traffic
* from these clients.
*
* nodeId [IN]
* An array of tokens that finished the unimport sequence.
*
* Possible status values returned are:
* NV_ERR_NOT_SUPPORTED
* NV_OK
*/
#define NV00F1_CTRL_CMD_DISABLE_IMPORTERS (0xf10003U) /* finn: Evaluated from "(FINN_IMEX_SESSION_INTERFACE_ID << 8) | NV00F1_CTRL_DISABLE_IMPORTERS_PARAMS_MESSAGE_ID" */
#define NV00F1_CTRL_DISABLE_IMPORTERS_PARAMS_MESSAGE_ID (0x3U)
typedef struct NV00F1_CTRL_DISABLE_IMPORTERS_PARAMS {
NvU16 nodeId;
} NV00F1_CTRL_DISABLE_IMPORTERS_PARAMS;
/* _ctrl00f1.h_ */

3
src/common/sdk/nvidia/inc/ctrl/ctrl00f8.h
View File

@@ -205,7 +205,8 @@ typedef struct NV00F8_CTRL_ATTACH_MEM_INFO {
*
* Restrictions:
* a. Physical memory with 2MB pagesize is allowed
* b. Only vidmem physical memory handle can be attached
* b. vidmem and sysmem with fixed node ID can be attached.
* sysmem with fixed node ID is supported only if EGM is enabled.
* c. Supported only for flexible fabric objects.
*/
#define NV00F8_CTRL_CMD_ATTACH_MEM (0xf80103) /* finn: Evaluated from "(FINN_NV_MEMORY_FABRIC_FABRIC_INTERFACE_ID << 8) | NV00F8_CTRL_ATTACH_MEM_PARAMS_MESSAGE_ID" */

87
src/common/sdk/nvidia/inc/ctrl/ctrl00f9.h Normal file
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@@ -0,0 +1,87 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2021-22 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl00f9.finn
//
#include "ctrl/ctrlxxxx.h"
#include "ctrl/ctrl00f8.h"
#define NV00F9_CTRL_CMD(cat,idx) NVXXXX_CTRL_CMD(0x00f9, NV00F9_CTRL_##cat, idx)
/* NV00F9 command categories (6bits) */
#define NV00F9_CTRL_RESERVED (0x00U)
#define NV00F9_CTRL_IMPORT (0x01U)
/*
* NV00F9_CTRL_CMD_NULL
*
* This command does nothing.
* This command does not take any parameters.
*
* Possible status values returned are:
* NV_OK
*/
#define NV00F9_CTRL_CMD_NULL (0xf90000U) /* finn: Evaluated from "(FINN_NV_MEMORY_FABRIC_IMPORT_V2_RESERVED_INTERFACE_ID << 8) | 0x0" */
/*
* NV00F9_CTRL_CMD_GET_INFO
*
* Queries memory allocation attributes.
*
* size [OUT]
* Size of the allocation.
*
* pageSize [OUT]
* Page size of the allocation
*
* memFlags [OUT]
* Flags associated with memory allocation.
*
* physAttrs [OUT]
* Physical attributes associated with memory allocation.
* For flexible mappings, it is not possible to retrieve this information,
* behavior is undefined (returns all zeros).
*/
#define NV00F9_CTRL_CMD_GET_INFO (0xf90101U) /* finn: Evaluated from "(FINN_NV_MEMORY_FABRIC_IMPORT_V2_IMPORT_INTERFACE_ID << 8) | NV00F9_CTRL_GET_INFO_PARAMS_MESSAGE_ID" */
#define NV00F9_CTRL_GET_INFO_PARAMS_MESSAGE_ID (0x1U)
typedef struct NV00F9_CTRL_GET_INFO_PARAMS {
NV_DECLARE_ALIGNED(NvU64 size, 8);
NV_DECLARE_ALIGNED(NvU64 pageSize, 8);
NvU32 memFlags;
NV_PHYSICAL_MEMORY_ATTRS physAttrs;
} NV00F9_CTRL_GET_INFO_PARAMS;
/* _ctrl00f9_h_ */

114
src/common/sdk/nvidia/inc/ctrl/ctrl00fb.h Normal file
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@@ -0,0 +1,114 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2021-22 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl00fb.finn
//
#include "nvtypes.h"
#include "ctrl/ctrlxxxx.h"
#include "ctrl/ctrl00f8.h"
#define NV00FB_CTRL_CMD(cat, idx) \
NVXXXX_CTRL_CMD(0x00fb, NV00FB_CTRL_##cat, idx)
/* NV00FB command categories (6bits) */
#define NV00FB_CTRL_RESERVED (0x00U)
#define NV00FB_CTRL_IMPORT_REF (0x01U)
/*
* NV00FB_CTRL_CMD_NULL
*
* This command does nothing.
* This command does not take any parameters.
*
* Possible status values returned are:
* NV_OK
*/
#define NV00FB_CTRL_CMD_NULL (0xfb0000U) /* finn: Evaluated from "(FINN_NV_MEMORY_FABRIC_IMPORTED_REF_RESERVED_INTERFACE_ID << 8) | 0x0" */
/*
* NV00FB_CTRL_CMD_VALIDATE
*
* Populate the imported memory, making it ready to map locally.
*
* attrs [IN]
* Attributes associated with memory allocation.
*
* physAttrs [IN]
* Physical attributes associated with memory allocation.
* For flexible mappings, it is not possible to retrieve this information,
* behavior is undefined (returns all zeros).
*
* offset [IN]
* Offset into memory allocation to query physical addresses for.
*
* totalPfns [IN]
* Number of PFNs in memory allocation.
*
* pfnArray [IN]
* Array of PFNs in memory allocation (2MB page size shifted).
*
* numPfns [IN]
* Number of valid entries in pfnArray.
*
* memFlags [IN]
* Flags associated with memory allocation.
*
* flags [IN]
* Flags to notify RM about errors during import.
*
* bDone [out]
* Whether the RM is expecting additional calls to _VALIDATE.
*/
#define NV00FB_CTRL_CMD_VALIDATE (0xfb0101U) /* finn: Evaluated from "(FINN_NV_MEMORY_FABRIC_IMPORTED_REF_IMPORT_REF_INTERFACE_ID << 8) | NV00FB_CTRL_VALIDATE_PARAMS_MESSAGE_ID" */
#define NV00FB_CTRL_VALIDATE_PFN_ARRAY_SIZE 512U
#define NV00FB_CTRL_FLAGS_NONE 0U
#define NV00FB_CTRL_FLAGS_IMPORT_FAILED 1U
#define NV00FB_CTRL_VALIDATE_PARAMS_MESSAGE_ID (0x1U)
typedef struct NV00FB_CTRL_VALIDATE_PARAMS {
NV_DECLARE_ALIGNED(NV_FABRIC_MEMORY_ATTRS attrs, 8);
NV_PHYSICAL_MEMORY_ATTRS physAttrs;
NV_DECLARE_ALIGNED(NvU64 offset, 8);
NV_DECLARE_ALIGNED(NvU64 totalPfns, 8);
NvU32 pfnArray[NV00FB_CTRL_VALIDATE_PFN_ARRAY_SIZE];
NvU32 numPfns;
NvU32 memFlags;
NvU32 flags;
NvBool bDone;
} NV00FB_CTRL_VALIDATE_PARAMS;
/* _ctrl00fb_h_ */

47
src/common/sdk/nvidia/inc/ctrl/ctrl00fd.h
View File

@@ -202,6 +202,53 @@ typedef struct NV00FD_CTRL_DETACH_MEM_PARAMS {
NvU32 flags;
} NV00FD_CTRL_DETACH_MEM_PARAMS;
/*
* NV00FD_CTRL_CMD_ATTACH_REMOTE_GPU
*
* Attaches a remote GPU to the Multicast FLA object. This control call is
* restricted to the privileged clients like IMEX daemon.
*
* gpuFabricProbeHandle [IN]
* Fabric probe handle of the remote GPU
*
* key [IN]
* Key is used by the GFM in the MCFLA team response as an ID to allow the
* RM to correlate it with the MCFLA team request.
*
* cliqueId [IN]
* Clique ID of the remote GPU being attached.
*
* nodeId [IN]
* nodeID from which the remote GPU is being attached.
*/
#define NV00FD_CTRL_CMD_ATTACH_REMOTE_GPU (0xfd0106) /* finn: Evaluated from "(FINN_NV_MEMORY_MULTICAST_FABRIC_FABRIC_INTERFACE_ID << 8) | NV00FD_CTRL_ATTACH_REMOTE_GPU_PARAMS_MESSAGE_ID" */
#define NV00FD_CTRL_ATTACH_REMOTE_GPU_PARAMS_MESSAGE_ID (0x6U)
typedef struct NV00FD_CTRL_ATTACH_REMOTE_GPU_PARAMS {
NV_DECLARE_ALIGNED(NvU64 gpuFabricProbeHandle, 8);
NV_DECLARE_ALIGNED(NvU64 key, 8);
NvU32 cliqueId;
NvU16 nodeId;
} NV00FD_CTRL_ATTACH_REMOTE_GPU_PARAMS;
/*
* NV00FD_CTRL_CMD_SET_FAILURE
*
* Marks the MCLFA object allocation with a failure. This control call is
* restricted to the privileged client like IMEX daemon.
*
* status [IN]
* Failure status, shouldn't be NV_OK.
*/
#define NV00FD_CTRL_CMD_SET_FAILURE (0xfd0107) /* finn: Evaluated from "(FINN_NV_MEMORY_MULTICAST_FABRIC_FABRIC_INTERFACE_ID << 8) | NV00FD_CTRL_SET_FAILURE_PARAMS_MESSAGE_ID" */
#define NV00FD_CTRL_SET_FAILURE_PARAMS_MESSAGE_ID (0x7U)
typedef struct NV00FD_CTRL_SET_FAILURE_PARAMS {
NV_STATUS status;
} NV00FD_CTRL_SET_FAILURE_PARAMS;
/* _ctrl00fd_h_ */

57
src/common/sdk/nvidia/inc/ctrl/ctrl00fe.h
View File

@@ -30,35 +30,62 @@
// Source file: ctrl/ctrl00fe.finn
//
#define NV00FE_CTRL_SUBMIT_PAGING_OPERATIONS_FLAG_PAGE_KIND_SOURCE_ALLOCATION 0:0
#define NV00FE_CTRL_SUBMIT_PAGING_OPERATIONS_FLAG_PAGE_KIND_SOURCE_ALLOCATION_PHYSICAL (0x00000000U)
#define NV00FE_CTRL_SUBMIT_PAGING_OPERATIONS_FLAG_PAGE_KIND_SOURCE_ALLOCATION_VIRTUAL (0x00000001U)
typedef enum NV00FE_CTRL_OPERATION_TYPE {
NV00FE_CTRL_OPERATION_TYPE_NOP = 0, // operation is ignored, used internally
NV00FE_CTRL_OPERATION_TYPE_MAP = 1,
NV00FE_CTRL_OPERATION_TYPE_UNMAP = 2,
NV00FE_CTRL_OPERATION_TYPE_SEMAPHORE_WAIT = 3,
NV00FE_CTRL_OPERATION_TYPE_SEMAPHORE_SIGNAL = 4,
} NV00FE_CTRL_OPERATION_TYPE;
typedef struct NV00FE_CTRL_PAGING_OPERATION {
typedef struct NV00FE_CTRL_OPERATION_MAP {
NvHandle hVirtualMemory;
NV_DECLARE_ALIGNED(NvU64 virtualOffset, 8);
NvHandle hPhysicalMemory;
NV_DECLARE_ALIGNED(NvU64 physicalOffset, 8);
NV_DECLARE_ALIGNED(NvU64 size, 8);
NvU32 flags;
} NV00FE_CTRL_PAGING_OPERATION;
NvU32 dmaFlags; // NVOS46_FLAGS
} NV00FE_CTRL_OPERATION_MAP;
typedef struct NV00FE_CTRL_OPERATION_UNMAP {
NvHandle hVirtualMemory;
NV_DECLARE_ALIGNED(NvU64 virtualOffset, 8);
NV_DECLARE_ALIGNED(NvU64 size, 8);
NvU32 dmaFlags; // NVOS47_FLAGS
} NV00FE_CTRL_OPERATION_UNMAP;
typedef struct NV00FE_CTRL_OPERATION_SEMAPHORE {
NvU32 index;
NV_DECLARE_ALIGNED(NvU64 value, 8);
} NV00FE_CTRL_OPERATION_SEMAPHORE;
typedef struct NV00FE_CTRL_OPERATION {
NV00FE_CTRL_OPERATION_TYPE type;
union {
NV_DECLARE_ALIGNED(NV00FE_CTRL_OPERATION_MAP map, 8);
NV_DECLARE_ALIGNED(NV00FE_CTRL_OPERATION_UNMAP unmap, 8);
NV_DECLARE_ALIGNED(NV00FE_CTRL_OPERATION_SEMAPHORE semaphore, 8);
} data;
} NV00FE_CTRL_OPERATION;
/*
* NV00FE_CTRL_CMD_SUBMIT_PAGING_OPERATIONS
* NV00FE_CTRL_CMD_SUBMIT_OPERATIONS
*
* Execute a list of paging operations
* Execute a list of mapping/semaphore operations
* Page size is determined by the virtual allocation
* Offsets/sizes must respect the page size
*
*/
#define NV00FE_CTRL_CMD_SUBMIT_PAGING_OPERATIONS (0xfe0002U) /* finn: Evaluated from "(FINN_NV_MEMORY_MAPPER_INTERFACE_ID << 8) | NV00FE_CTRL_SUBMIT_PAGING_OPERATIONS_PARAMS_MESSAGE_ID" */
#define NV00FE_CTRL_CMD_SUBMIT_OPERATIONS (0xfe0101U) /* finn: Evaluated from "(FINN_NV_MEMORY_MAPPER_INTERFACE_ID << 8) | NV00FE_CTRL_SUBMIT_OPERATIONS_PARAMS_MESSAGE_ID" */
#define NV00FE_CTRL_SUBMIT_PAGING_OPERATIONS_MAX_COUNT (0x00010000U)
#define NV00FE_MAX_OPERATIONS_COUNT (0x00001000U)
#define NV00FE_CTRL_SUBMIT_PAGING_OPERATIONS_PARAMS_MESSAGE_ID (0x2U)
#define NV00FE_CTRL_SUBMIT_OPERATIONS_PARAMS_MESSAGE_ID (0x1U)
typedef struct NV00FE_CTRL_SUBMIT_PAGING_OPERATIONS_PARAMS {
NvU32 pagingOpsCount;
NV_DECLARE_ALIGNED(NvP64 pagingOps, 8);
} NV00FE_CTRL_SUBMIT_PAGING_OPERATIONS_PARAMS;
typedef struct NV00FE_CTRL_SUBMIT_OPERATIONS_PARAMS {
NvU32 operationsCount;
NV_DECLARE_ALIGNED(NV00FE_CTRL_OPERATION pOperations[NV00FE_MAX_OPERATIONS_COUNT], 8);
NvU32 operationsProcessedCount;
} NV00FE_CTRL_SUBMIT_OPERATIONS_PARAMS;

12
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080bios.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2005-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2005-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -353,6 +353,8 @@ typedef struct NV2080_CTRL_BIOS_GET_NBSI_OBJ_PARAMS {
* This field returns the sku for the current chip.
* chipSKUMod
* This field returns the SKU modifier.
* skuConfigVersion
* Version number for the SKU configuration detailing pstate, thermal, VF curve and so on.
* project
* This field returns the Project (Board) number.
* projectSKU
@@ -369,15 +371,13 @@ typedef struct NV2080_CTRL_BIOS_GET_NBSI_OBJ_PARAMS {
*/
#define NV2080_CTRL_CMD_BIOS_GET_SKU_INFO (0x20800808) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BIOS_INTERFACE_ID << 8) | NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS_MESSAGE_ID" */
/* maximum length of parameter strings */
#define NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS_MESSAGE_ID (0x8U)
typedef struct NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS {
NvU32 BoardID;
char chipSKU[4];
char chipSKUMod[2];
char chipSKU[9];
char chipSKUMod[5];
NvU32 skuConfigVersion;
char project[5];
char projectSKU[5];
char CDP[6];

78
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080ecc.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2017-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2017-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -60,4 +60,80 @@ typedef struct NV2080_CTRL_ECC_GET_CLIENT_EXPOSED_COUNTERS_PARAMS {
NV_DECLARE_ALIGNED(NvU64 dramCorrectedTotalCounts, 8);
NV_DECLARE_ALIGNED(NvU64 dramUncorrectedTotalCounts, 8);
} NV2080_CTRL_ECC_GET_CLIENT_EXPOSED_COUNTERS_PARAMS;
#define NV2080_CTRL_CMD_ECC_GET_ECI_COUNTERS (0x20803401U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_ECC_INTERFACE_ID << 8) | NV2080_CTRL_ECC_GET_ECI_COUNTERS_PARAMS_MESSAGE_ID" */
/*
* NV2080_CTRL_ECC_GET_ECI_COUNTERS_PARAMS
*
* sramParityUncorrectedUnique [out]
* sramSecDedUncorrectedUnique [out]
* sramCorrectedTotal [out]
* dramUncorrectedTotal [out]
* dramCorrectedTotal [out]
* Aggregate error counts for SRAM and DRAM.
*
* lastClearedTimestamp [out]
* unix-epoch based timestamp. These fields indicate when the error counters
* were last cleared by the user.
*
* sramBucketL2 [out]
* sramBucketSM [out]
* sramBucketPcie [out]
* sramBucketFirmware [out]
* sramBucketOther [out]
* Aggregate unique uncorrctable error counts for SRAM buckets.
*
* sramErrorThresholdExceeded [out]
* Boolean flag which is set if SRAM error threshold was exceeded
*/
#define NV2080_CTRL_ECC_GET_ECI_COUNTERS_PARAMS_MESSAGE_ID (0x1U)
typedef struct NV2080_CTRL_ECC_GET_ECI_COUNTERS_PARAMS {
NV_DECLARE_ALIGNED(NvU64 sramParityUncorrectedUnique, 8);
NV_DECLARE_ALIGNED(NvU64 sramSecDedUncorrectedUnique, 8);
NV_DECLARE_ALIGNED(NvU64 sramCorrectedTotal, 8);
NV_DECLARE_ALIGNED(NvU64 dramUncorrectedTotal, 8);
NV_DECLARE_ALIGNED(NvU64 dramCorrectedTotal, 8);
NvU32 lastClearedTimestamp;
NV_DECLARE_ALIGNED(NvU64 sramBucketL2, 8);
NV_DECLARE_ALIGNED(NvU64 sramBucketSM, 8);
NV_DECLARE_ALIGNED(NvU64 sramBucketPcie, 8);
NV_DECLARE_ALIGNED(NvU64 sramBucketFirmware, 8);
NV_DECLARE_ALIGNED(NvU64 sramBucketOther, 8);
NvBool sramErrorThresholdExceeded;
} NV2080_CTRL_ECC_GET_ECI_COUNTERS_PARAMS;
/*
* NV2080_CTRL_ECC_GET_VOLATILE_COUNTS_PARAMS
*
* Reports count of volatile errors
*
* sramCorUni [out]:
* Unique correctable SRAM error count
* sramUncParityUni [out]:
* Unique uncorrectable SRAM parity error count
* sramUncSecDedUni [out]:
* Unique uncorrectable SRAM SEC-DED error count
* dramCorTot [out]:
* Total correctable DRAM error count
* dramUncTot [out]:
* total uncorrectable DRAM error count
*/
#define NV2080_CTRL_CMD_ECC_GET_VOLATILE_COUNTS (0x20803402U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_ECC_INTERFACE_ID << 8) | NV2080_CTRL_ECC_GET_VOLATILE_COUNTS_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_ECC_GET_VOLATILE_COUNTS_PARAMS_MESSAGE_ID (0x2U)
typedef struct NV2080_CTRL_ECC_GET_VOLATILE_COUNTS_PARAMS {
NV_DECLARE_ALIGNED(NvU64 sramCorUni, 8);
NV_DECLARE_ALIGNED(NvU64 sramUncParityUni, 8);
NV_DECLARE_ALIGNED(NvU64 sramUncSecDedUni, 8);
NV_DECLARE_ALIGNED(NvU64 dramCorTot, 8);
NV_DECLARE_ALIGNED(NvU64 dramUncTot, 8);
} NV2080_CTRL_ECC_GET_VOLATILE_COUNTS_PARAMS;
/* _ctrl2080ecc_h_ */

35
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080event.h
View File

@@ -335,4 +335,39 @@ typedef struct NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_PARAMS {
NvBool bAllUsers;
} NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_PARAMS;
/*
* NV2080_CTRL_CMD_EVENT_RATS_GSP_TRACE_BIND_EVTBUF_FOR_UID
*
* This command is used to create a RATS tracing bindpoint to eventbuffer.
*
* hEventBuffer[IN]
* The event buffer to bind to
*
* tracepointMask[IN]
* Bitmask for selecting tracepoints
*
* gspLoggingBufferSize[IN]
* User defined size of GSP owned event logging buffer
*
* gspLoggingBufferWatermark[IN]
* User defined watermark that triggers RPC to kernel of traces
* HINT: set higher for more frequent trace updates
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_NOT_SUPPORTED
*/
#define NV2080_CTRL_CMD_EVENT_RATS_GSP_TRACE_BIND_EVTBUF (0x2080030a) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_EVENT_INTERFACE_ID << 8) | NV2080_CTRL_EVENT_RATS_GSP_TRACE_BIND_EVTBUF_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_EVENT_RATS_GSP_TRACE_BIND_EVTBUF_PARAMS_MESSAGE_ID (0xAU)
typedef struct NV2080_CTRL_EVENT_RATS_GSP_TRACE_BIND_EVTBUF_PARAMS {
NvHandle hEventBuffer;
NV_DECLARE_ALIGNED(NvU64 tracepointMask, 8);
NvU32 gspLoggingBufferSize;
NvU32 gspLoggingBufferWatermark;
} NV2080_CTRL_EVENT_RATS_GSP_TRACE_BIND_EVTBUF_PARAMS;
/* _ctrl2080event_h_ */

95
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080fb.h
View File

@@ -35,6 +35,7 @@
/* NV20_SUBDEVICE_XX fb control commands and parameters */
#include "nvlimits.h"
#include "nvcfg_sdk.h"
/*
* NV2080_CTRL_FB_INFO
@@ -360,6 +361,8 @@ typedef NVXXXX_CTRL_XXX_INFO NV2080_CTRL_FB_INFO;
#define NV2080_CTRL_FB_INFO_RAM_TYPE_LPDDR5 (0x00000013U) /* LPDDR (Low Power SDDR) used on T23x and later.*/
#define NV2080_CTRL_FB_INFO_RAM_TYPE_HBM3 (0x00000014U) /* HBM3 (High Bandwidth Memory) v3 */
/* valid RAM LOCATION types */
#define NV2080_CTRL_FB_INFO_RAM_LOCATION_GPU_DEDICATED (0x00000000U)
#define NV2080_CTRL_FB_INFO_RAM_LOCATION_SYS_SHARED (0x00000001U)
@@ -519,8 +522,60 @@ typedef struct NV2080_CTRL_FB_GET_CALIBRATION_LOCK_FAILED_PARAMS {
} NV2080_CTRL_FB_GET_CALIBRATION_LOCK_FAILED_PARAMS;
/* valid flags parameter values */
#define NV2080_CTRL_CMD_FB_GET_CAL_FLAG_NONE (0x00000000U)
#define NV2080_CTRL_CMD_FB_GET_CAL_FLAG_RESET (0x00000001U)
#define NV2080_CTRL_CMD_FB_GET_CAL_FLAG_NONE (0x00000000U)
#define NV2080_CTRL_CMD_FB_GET_CAL_FLAG_RESET (0x00000001U)
/*
* NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE_IRQL
*
* If supported by hardware and the OS, this command implements a streamlined version of
* NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE which can be called at high IRQL and Bypass the
* RM Lock.
*
* Requires the following NVOS54_PARAMETERS to be set for raised IRQ / Lock Bypass operation:
* NVOS54_FLAGS_IRQL_RAISED
* NVOS54_FLAGS_LOCK_BYPASS
*
* flags
* Contains flags to control various aspects of the flush. Valid values
* are defined in NV2080_CTRL_CTRL_CMD_FB_FLUSH_GPU_CACHE_IRQL_FLAGS*.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_NOT_SUPPORTED
* NV_ERR_INVALID_STATE
* NV_ERR_INVALID_ARGUMENT
*
* See Also:
* NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE
* This is the more generalized version which is not intended to be called at raised IRQ level
* NV0080_CTRL_CMD_DMA_FLUSH
* Performs flush operations in broadcast for the GPU cache and other hardware
* engines. Use this call if you want to flush all GPU caches in a
* broadcast device.
* NV0041_CTRL_CMD_SURFACE_FLUSH_GPU_CACHE
* Flushes memory associated with a single allocation if the hardware
* supports it. Use this call if you want to flush a single allocation and
* you have a memory object describing the physical memory.
*/
#define NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE_IRQL (0x2080130dU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE_IRQL_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE_IRQL_PARAMS_MESSAGE_ID (0xDU)
typedef struct NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE_IRQL_PARAMS {
NvU32 flags;
} NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE_IRQL_PARAMS;
/* valid fields and values for flags */
#define NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE_IRQL_FLAGS_WRITE_BACK 0:0
#define NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE_IRQL_FLAGS_WRITE_BACK_NO (0x00000000U)
#define NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE_IRQL_FLAGS_WRITE_BACK_YES (0x00000001U)
#define NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE_IRQL_FLAGS_INVALIDATE 1:1
#define NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE_IRQL_FLAGS_INVALIDATE_NO (0x00000000U)
#define NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE_IRQL_FLAGS_INVALIDATE_YES (0x00000001U)
#define NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE_IRQL_FLAGS_FB_FLUSH 2:2
#define NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE_IRQL_FLAGS_FB_FLUSH_NO (0x00000000U)
#define NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE_IRQL_FLAGS_FB_FLUSH_YES (0x00000001U)
/*
* NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE
@@ -565,9 +620,9 @@ typedef struct NV2080_CTRL_FB_GET_CALIBRATION_LOCK_FAILED_PARAMS {
* supports it. Use this call if you want to flush a single allocation and
* you have a memory object describing the physical memory.
*/
#define NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE (0x2080130eU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_FLUSH_GPU_CACHE_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE (0x2080130eU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_FLUSH_GPU_CACHE_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_FB_FLUSH_GPU_CACHE_MAX_ADDRESSES 500U
#define NV2080_CTRL_FB_FLUSH_GPU_CACHE_MAX_ADDRESSES 500U
#define NV2080_CTRL_FB_FLUSH_GPU_CACHE_PARAMS_MESSAGE_ID (0xEU)
@@ -2294,6 +2349,34 @@ typedef struct NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_SUBP_MASK_PARAMS {
NV_DECLARE_ALIGNED(NvU64 fbpaSubpEnMask, 8);
} NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_SUBP_MASK_PARAMS;
/*!
* Structure holding the in/out params for NV2080_CTRL_SYSL2_FS_INFO_SYSLTC_MASK.
*/
typedef struct NV2080_CTRL_SYSL2_FS_INFO_SYSLTC_MASK_PARAMS {
/*!
* [IN]: physical/local sys Id.
*/
NvU32 sysIdx;
/*!
* [OUT]: physical/local sysltc mask.
*/
NvU32 sysl2LtcEnMask;
} NV2080_CTRL_SYSL2_FS_INFO_SYSLTC_MASK_PARAMS;
/*!
* Structure holding the in/out params for NV2080_CTRL_FB_FS_INFO_PAC_MASK.
*/
typedef struct NV2080_CTRL_FB_FS_INFO_PAC_MASK_PARAMS {
/*!
* [IN]: physical/local FB partition index.
*/
NvU32 fbpIndex;
/*!
* [OUT]: physical/local PAC mask.
*/
NvU32 pacEnMask;
} NV2080_CTRL_FB_FS_INFO_PAC_MASK_PARAMS;
// Possible values for queryType
#define NV2080_CTRL_FB_FS_INFO_INVALID_QUERY 0x0U
#define NV2080_CTRL_FB_FS_INFO_FBP_MASK 0x1U
@@ -2308,6 +2391,8 @@ typedef struct NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_SUBP_MASK_PARAMS {
#define NV2080_CTRL_FB_FS_INFO_FBPA_SUBP_MASK 0xAU
#define NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_SUBP_MASK 0xBU
#define NV2080_CTRL_FB_FS_INFO_FBP_LOGICAL_MAP 0xCU
#define NV2080_CTRL_SYSL2_FS_INFO_SYSLTC_MASK 0xDU
#define NV2080_CTRL_FB_FS_INFO_PAC_MASK 0xEU
typedef struct NV2080_CTRL_FB_FS_INFO_QUERY {
NvU16 queryType;
@@ -2327,6 +2412,8 @@ typedef struct NV2080_CTRL_FB_FS_INFO_QUERY {
NV_DECLARE_ALIGNED(NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_SUBP_MASK_PARAMS dmFbpaSubp, 8);
NV2080_CTRL_FB_FS_INFO_FBPA_SUBP_MASK_PARAMS fbpaSubp;
NV2080_CTRL_FB_FS_INFO_FBP_LOGICAL_MAP_PARAMS fbpLogicalMap;
NV2080_CTRL_SYSL2_FS_INFO_SYSLTC_MASK_PARAMS sysl2Ltc;
NV2080_CTRL_FB_FS_INFO_PAC_MASK_PARAMS pac;
} queryParams;
} NV2080_CTRL_FB_FS_INFO_QUERY;

272
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080fifo.h
View File

@@ -30,6 +30,7 @@
// Source file: ctrl/ctrl2080/ctrl2080fifo.finn
//
#include "nvcfg_sdk.h"
#include "ctrl/ctrl2080/ctrl2080base.h"
/*
@@ -466,6 +467,94 @@ typedef struct NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION_PARAMS {
#define NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION_ATTRIBUTE_WRITECOMBINED 0X00000002
#define NV2080_CTRL_CMD_VGPU_SCHEDULER_POLICY_UNKNOWN 0
#define NV2080_CTRL_CMD_VGPU_SCHEDULER_POLICY_OTHER 1
#define NV2080_CTRL_CMD_VGPU_SCHEDULER_POLICY_BEST_EFFORT 2
#define NV2080_CTRL_CMD_VGPU_SCHEDULER_POLICY_EQUAL_SHARE 3
#define NV2080_CTRL_CMD_VGPU_SCHEDULER_POLICY_FIXED_SHARE 4
// Count of the supported vGPU scheduler policies
#define NV2080_CTRL_CMD_SUPPORTED_VGPU_SCHEDULER_POLICY_COUNT 3
#define NV2080_CTRL_CMD_VGPU_SCHEDULER_ARR_DEFAULT 0
#define NV2080_CTRL_CMD_VGPU_SCHEDULER_ARR_DISABLE 1
#define NV2080_CTRL_CMD_VGPU_SCHEDULER_ARR_ENABLE 2
/*
* NV2080_CTRL_CMD_FIFO_OBJSCHED_SW_GET_LOG
*
* This command returns the OBJSCHED_SW log enties.
*
* engineId
* This field specifies the NV2080_ENGINE_TYPE_* engine whose SW runlist log
* entries are to be fetched.
*
* count
* This field returns the count of log entries fetched.
*
* entry
* The array of SW runlist log entries.
*
* timestampNs
* Timestamp in ns when this SW runlist was preeempted.
*
* timeRunTotalNs
* Total time in ns this SW runlist has run as compared to others.
*
* timeRunNs
* Time in ns this SW runlist ran before preemption.
*
* swrlId
* SW runlist Id.
*
* schedPolicy
* This field returns the runlist scheduling policy. It specifies the
* NV2080_CTRL_CMD_VGPU_SCHEDULER_POLICY_* scheduling policy.
*
* arrEnabled
* This field returns if Adaptive round robin scheduler
* is enabled/disabled.
*
* arrAvgFactor
* This field returns the average factor to be used in compensating the timeslice
* for Adaptive scheduler mode.
*
* targetTimesliceNs
* This field returns the target timeslice duration in ns for each SW runlist
* as configured by the user or the default value otherwise.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
*/
#define NV2080_CTRL_CMD_FIFO_OBJSCHED_SW_GET_LOG (0x2080110e) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FIFO_INTERFACE_ID << 8) | NV2080_CTRL_FIFO_OBJSCHED_SW_GET_LOG_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_FIFO_OBJSCHED_SW_COUNT 32
#define NV2080_CTRL_FIFO_OBJSCHED_SW_NCOUNTERS 8
#define NV2080_CTRL_FIFO_OBJSCHED_SW_GET_LOG_ENTRIES 200
#define NV2080_CTRL_FIFO_OBJSCHED_SW_GET_LOG_PARAMS_MESSAGE_ID (0xEU)
typedef struct NV2080_CTRL_FIFO_OBJSCHED_SW_GET_LOG_PARAMS {
NvU32 engineId;
NvU32 count;
struct {
NV_DECLARE_ALIGNED(NvU64 timestampNs, 8);
NV_DECLARE_ALIGNED(NvS64 timeRunTotalNs, 8);
NvU32 timeRunNs;
NvU32 swrlId;
NvU32 targetTimeSlice;
NV_DECLARE_ALIGNED(NvU64 cumulativePreemptionTime, 8);
NV_DECLARE_ALIGNED(NvU64 counters[NV2080_CTRL_FIFO_OBJSCHED_SW_NCOUNTERS], 8);
} entry[NV2080_CTRL_FIFO_OBJSCHED_SW_GET_LOG_ENTRIES];
NvU32 schedPolicy;
NvU32 arrEnabled;
NvU32 arrAvgFactor;
NvU32 targetTimesliceNs;
} NV2080_CTRL_FIFO_OBJSCHED_SW_GET_LOG_PARAMS;
/*
* NV2080_CTRL_CMD_FIFO_GET_DEVICE_INFO_TABLE
@@ -783,6 +872,189 @@ typedef struct NV2080_CTRL_FIFO_GET_ALLOCATED_CHANNELS_PARAMS {
NvU32 bitMask[NV2080_CTRL_FIFO_GET_ALLOCATED_CHANNELS_MAX_CHANNELS / 32];
} NV2080_CTRL_FIFO_GET_ALLOCATED_CHANNELS_PARAMS;
/*
* NV2080_CTRL_CMD_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION
*
* This command will disable and preempt channels described in the
* list provided and mark them ready for key rotation.
* hClient <-> hChannel pairs should use the same index in the arrays.
*
* numChannels
* The number of valid entries in hChannelList array.
* hClientList
* An array of NvHandle listing the client handles
* hChannelList
* An array of NvHandle listing the channel handles
* to be stopped.
* bEnableAfterKeyRotation
* This determines if channel is enabled by RM after it completes key rotation.
* Possible status values returned are:
* NV_OK
* NVOS_INVALID_STATE
*/
#define NV2080_CTRL_CMD_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION (0x2080111a) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FIFO_INTERFACE_ID << 8) | NV2080_CTRL_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_MAX_ENTRIES (64)
#define NV2080_CTRL_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_PARAMS_MESSAGE_ID (0x1AU)
typedef struct NV2080_CTRL_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_PARAMS {
NvU32 numChannels;
NvHandle hClientList[NV2080_CTRL_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_MAX_ENTRIES];
NvHandle hChannelList[NV2080_CTRL_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_MAX_ENTRIES];
NvBool bEnableAfterKeyRotation;
} NV2080_CTRL_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_PARAMS;
/*
* NV2080_CTRL_CMD_FIFO_OBJSCHED_GET_STATE
*
* This command returns the vGPU schedular state.
*
* engineId
* This field specifies the NV2080_ENGINE_TYPE_* engine whose SW runlist log
* entries are to be fetched.
*
* schedPolicy
* This field returns the runlist scheduling policy. It specifies the
* NV2080_CTRL_CMD_VGPU_SCHEDULER_POLICY_* scheduling policy.
*
* arrEnabled
* This field returns if Adaptive round robin scheduler
* is enabled/disabled.
*
* targetTimesliceNs
* This field returns the target timeslice duration in ns for each SW runlist
* as configured by the user or the default value otherwise.
*
* arrAvgFactor
* This field returns the average factor to be used in compensating the timeslice
* for Adaptive scheduler mode.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
*/
#define NV2080_CTRL_CMD_FIFO_OBJSCHED_GET_STATE (0x20801120) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FIFO_INTERFACE_ID << 8) | NV2080_CTRL_FIFO_OBJSCHED_GET_STATE_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_FIFO_OBJSCHED_GET_STATE_PARAMS_MESSAGE_ID (0x20U)
typedef struct NV2080_CTRL_FIFO_OBJSCHED_GET_STATE_PARAMS {
NvU32 engineId;
NvU32 schedPolicy;
NvU32 arrEnabled;
NvU32 targetTimesliceNs;
NvU32 arrAvgFactor;
} NV2080_CTRL_FIFO_OBJSCHED_GET_STATE_PARAMS;
/*
* NV2080_CTRL_CMD_FIFO_OBJSCHED_SET_STATE
*
* This command set the vGPU schedular state.
*
* engineId
* This field specifies the NV2080_ENGINE_TYPE_* engine.
*
* schedPolicy
* This field sets the runlist scheduling policy. It specifies the
* NV2080_CTRL_CMD_VGPU_SCHEDULER_POLICY_* scheduling policy.
*
* enableArr
* This field sets the Adaptive round robin scheduler
* is enabled/disabled.
*
* timesliceTargetNs
* This field sets the time slice target time in ns.
*
* frequencyForARR
* This field sets the scheduling frequency for Adaptive round robin scheduler mode.
*
* avgFactorForARR
* This field sets the average factor to be used in compensating the timeslice
* for Adaptive scheduler mode.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_DEVICE
* NV_ERR_INVALID_STATE
* NV_ERR_NOT_SUPPORTED
* NV_ERR_INSUFFICIENT_PERMISSIONS
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_INVALID_PARAM_STRUCT
*/
#define NV2080_CTRL_CMD_FIFO_OBJSCHED_SET_STATE (0x20801121) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FIFO_INTERFACE_ID << 8) | NV2080_CTRL_FIFO_OBJSCHED_SET_STATE_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_FIFO_OBJSCHED_SET_STATE_PARAMS_MESSAGE_ID (0x21U)
typedef struct NV2080_CTRL_FIFO_OBJSCHED_SET_STATE_PARAMS {
NvU32 engineId;
NvU32 schedPolicy;
NvU32 enableArr;
NvU32 timesliceTargetNs;
NvU32 frequencyForARR;
NvU32 avgFactorForARR;
} NV2080_CTRL_FIFO_OBJSCHED_SET_STATE_PARAMS;
/*
* NV2080_CTRL_CMD_FIFO_OBJSCHED_GET_CAPS
*
* This command returns the vGPU schedular capabilities.
*
* engineId [in]
* This field specifies the NV2080_ENGINE_TYPE_* engine whose SW runlist log
* entries are to be fetched.
*
* supportedSchedulers [out]
* This field returns the supported runlist scheduling policies on the device.
* It specifies the NV2080_CTRL_CMD_VGPU_SCHEDULER_POLICY_* scheduling policy.
*
* bIsArrModeSupported [out]
* This field returns if Adaptive scheduler mode is enabled/disabled.
*
* maxTimesliceNs [out]
* This field returns the maximum time slice value in ns.
*
* minTimesliceNs [out]
* This field returns the minimum time slice value in ns.
*
* maxFrequencyForARR [out]
* This field returns the maximum scheduling frequency for
* Adaptive round robin scheduler mode.
*
* minFrequencyForARR [out]
* This field returns the minimum scheduling frequency for
* Adaptive round robin scheduler mode.
*
* maxAvgFactorForARR [out]
* This field returns the maximum average factor in compensating
* the timeslice for Adaptive scheduler mode.
*
* minAvgFactorForARR [out]
* This field returns the minimum average factor in compensating
* the timeslice for Adaptive scheduler mode.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
*/
#define NV2080_CTRL_CMD_FIFO_OBJSCHED_GET_CAPS (0x20801122) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FIFO_INTERFACE_ID << 8) | NV2080_CTRL_FIFO_OBJSCHED_GET_CAPS_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_FIFO_OBJSCHED_GET_CAPS_PARAMS_MESSAGE_ID (0x22U)
typedef struct NV2080_CTRL_FIFO_OBJSCHED_GET_CAPS_PARAMS {
NvU32 engineId;
NvU32 supportedSchedulers[NV2080_CTRL_CMD_SUPPORTED_VGPU_SCHEDULER_POLICY_COUNT];
NvBool bIsArrModeSupported;
NvU32 maxTimesliceNs;
NvU32 minTimesliceNs;
NvU32 maxFrequencyForARR;
NvU32 minFrequencyForARR;
NvU32 maxAvgFactorForARR;
NvU32 minAvgFactorForARR;
} NV2080_CTRL_FIFO_OBJSCHED_GET_CAPS_PARAMS;
/* _ctrl2080fifo_h_ */

1
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080flcn.h
View File

@@ -148,6 +148,7 @@ typedef struct NV2080_CTRL_FLCN_GET_ENGINE_ARCH_PARAMS {
#define NV2080_CTRL_FLCN_GET_ENGINE_ARCH_DEFAULT 0x0
#define NV2080_CTRL_FLCN_GET_ENGINE_ARCH_FALCON 0x1
#define NV2080_CTRL_FLCN_GET_ENGINE_ARCH_RISCV 0x2
#define NV2080_CTRL_FLCN_GET_ENGINE_ARCH_RISCV_EB 0x3
/*!@}*/

57
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080gpu.h
View File

@@ -748,7 +748,7 @@ typedef struct NV2080_CTRL_GPU_GET_ENGINES_PARAMS {
#define NV2080_CTRL_CMD_GPU_GET_ENGINES_V2 (0x20800170U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_ENGINES_V2_PARAMS_MESSAGE_ID" */
/* Must match NV2080_ENGINE_TYPE_LAST from cl2080.h */
#define NV2080_GPU_MAX_ENGINES_LIST_SIZE 0x3FU
#define NV2080_GPU_MAX_ENGINES_LIST_SIZE 0x40U
#define NV2080_CTRL_GPU_GET_ENGINES_V2_PARAMS_MESSAGE_ID (0x70U)
@@ -2518,6 +2518,8 @@ typedef struct NV2080_CTRL_GPU_PARTITION_SPAN {
NV_DECLARE_ALIGNED(NvU64 hi, 8);
} NV2080_CTRL_GPU_PARTITION_SPAN;
#define NV_GI_UUID_LEN 16U
/*
* NV2080_CTRL_GPU_SET_PARTITION_INFO
*
@@ -2538,6 +2540,9 @@ typedef struct NV2080_CTRL_GPU_PARTITION_SPAN {
* - PartitionID associated with a newly created partition. Input in case
* of partition invalidation.
*
* uuid[OUT]
* - Uuid of a newly created partition.
*
* partitionFlag[IN]
* - Flags to determine if GPU is requested to be partitioned in FULL,
* HALF, QUARTER or ONE_EIGHTHED and whether the partition requires
@@ -2566,6 +2571,7 @@ typedef struct NV2080_CTRL_GPU_PARTITION_SPAN {
*/
typedef struct NV2080_CTRL_GPU_SET_PARTITION_INFO {
NvU32 swizzId;
NvU8 uuid[NV_GI_UUID_LEN];
NvU32 partitionFlag;
NvBool bValid;
NV_DECLARE_ALIGNED(NV2080_CTRL_GPU_PARTITION_SPAN placement, 8);
@@ -3824,7 +3830,7 @@ typedef struct NV2080_CTRL_GPU_SET_EGM_GPA_FABRIC_BASE_ADDR_PARAMS {
*/
#define NV2080_CTRL_CMD_GPU_GET_ENGINE_LOAD_TIMES (0x2080019bU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_ENGINE_LOAD_TIMES_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_GPU_MAX_ENGINE_OBJECTS 0xC0U
#define NV2080_CTRL_GPU_MAX_ENGINE_OBJECTS 0xC8U
#define NV2080_CTRL_GPU_GET_ENGINE_LOAD_TIMES_PARAMS_MESSAGE_ID (0x9BU)
@@ -4038,8 +4044,15 @@ typedef struct NV2080_CTRL_GPU_GET_COMPUTE_PROFILES_PARAMS {
#define NV2080_CTRL_GPU_FABRIC_PROBE_CAP_MC_SUPPORTED NVBIT64(0)
#define NV2080_CTRL_GPU_FABRIC_PROBE_CAP_MC_MUTLINODE_SUPPORTED NVBIT64(1)
#define NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_DEGRADED_BW 1:0
#define NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_DEGRADED_BW_NOT_SUPPORTED 0
#define NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_DEGRADED_BW_TRUE 1
#define NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_DEGRADED_BW_FALSE 2
/*!
* NV2080_CTRL_CMD_GET_GPU_FABRIC_PROBE_INFO_PARAMS
*
@@ -4068,7 +4081,9 @@ typedef struct NV2080_CTRL_GPU_GET_COMPUTE_PROFILES_PARAMS {
* Possible values are
* NV2080_CTRL_GPU_FABRIC_PROBE_CAP_*
* fabricCliqueId[OUT]
* - Unique ID of a set of GPUs within a fabric partition that can perform P2P
* - Unique ID of a set of GPUs within a fabric partition that can perform P2P
* fabricHealthMask[OUT]
* - Mask where bits indicate different status about the health of the fabric
*/
#define NV2080_CTRL_CMD_GET_GPU_FABRIC_PROBE_INFO_PARAMS_MESSAGE_ID (0xA3U)
@@ -4079,6 +4094,7 @@ typedef struct NV2080_CTRL_CMD_GET_GPU_FABRIC_PROBE_INFO_PARAMS {
NvU16 fabricPartitionId;
NV_DECLARE_ALIGNED(NvU64 fabricCaps, 8);
NvU32 fabricCliqueId;
NvU32 fabricHealthMask;
} NV2080_CTRL_CMD_GET_GPU_FABRIC_PROBE_INFO_PARAMS;
#define NV2080_CTRL_CMD_GET_GPU_FABRIC_PROBE_INFO (0x208001a3) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_CMD_GET_GPU_FABRIC_PROBE_INFO_PARAMS_MESSAGE_ID" */
@@ -4284,4 +4300,39 @@ typedef struct NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO_V2_PARAMS {
#define NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO_V2 (0x208001afU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO_V2_PARAMS_MESSAGE_ID" */
typedef struct NV2080_CTRL_GPU_CONSTRUCTED_FALCON_INFO {
NvU32 engDesc;
NvU32 ctxAttr;
NvU32 ctxBufferSize;
NvU32 addrSpaceList;
NvU32 registerBase;
} NV2080_CTRL_GPU_CONSTRUCTED_FALCON_INFO;
#define NV2080_CTRL_GPU_MAX_CONSTRUCTED_FALCONS 0x40
#define NV2080_CTRL_CMD_GPU_GET_CONSTRUCTED_FALCON_INFO (0x208001b0) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_CONSTRUCTED_FALCON_INFO_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_GPU_GET_CONSTRUCTED_FALCON_INFO_PARAMS_MESSAGE_ID (0xB0U)
typedef struct NV2080_CTRL_GPU_GET_CONSTRUCTED_FALCON_INFO_PARAMS {
NvU32 numConstructedFalcons;
NV2080_CTRL_GPU_CONSTRUCTED_FALCON_INFO constructedFalconsTable[NV2080_CTRL_GPU_MAX_CONSTRUCTED_FALCONS];
} NV2080_CTRL_GPU_GET_CONSTRUCTED_FALCON_INFO_PARAMS;
/*
* NV2080_CTRL_GPU_GET_FIPS_STATUS
*
* @brief get FIPS status (enabled/disabled) from GSP-RM
*
*
* @return NV_OK on success
* @return NV_ERR_ otherwise
*/
#define NV2080_CTRL_GPU_GET_FIPS_STATUS_PARAMS_MESSAGE_ID (0xe4U)
typedef struct NV2080_CTRL_GPU_GET_FIPS_STATUS_PARAMS {
NvBool bFipsEnabled;
} NV2080_CTRL_GPU_GET_FIPS_STATUS_PARAMS;
#define NV2080_CTRL_GPU_GET_FIPS_STATUS (0x208001e4) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_FIPS_STATUS_PARAMS_MESSAGE_ID" */
/* _ctrl2080gpu_h_ */

37
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080gr.h
View File

@@ -622,6 +622,35 @@ typedef struct NV2080_CTRL_GR_CTXSW_PM_BIND_PARAMS {
} NV2080_CTRL_GR_CTXSW_PM_BIND_PARAMS;
/* valid pmMode values same as above NV2080_CTRL_CTXSW_PM_MODE */
/*
* NV2080_CTRL_CMD_GR_CTXSW_SETUP_BIND
*
* This command is used to set the Setup context switch mode and virtual address
* for the specified channel. A value of NV_ERR_NOT_SUPPORTED is
* returned if the target channel does not support setup context switch mode
* changes.
*
* hClient
* This parameter specifies the client handle of
* that owns the Setup context buffer. This field must match
* the hClient used in the control call for non-kernel clients.
* hChannel
* This parameter specifies the channel handle of
* the channel that is to have its Setup context switch mode changed.
* vMemPtr
* This parameter specifies the 64 bit virtual address
* for the allocated Setup context buffer.
*/
#define NV2080_CTRL_CMD_GR_CTXSW_SETUP_BIND (0x2080123aU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_CTXSW_SETUP_BIND_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_GR_CTXSW_SETUP_BIND_PARAMS_MESSAGE_ID (0x3AU)
typedef struct NV2080_CTRL_GR_CTXSW_SETUP_BIND_PARAMS {
NvHandle hClient;
NvHandle hChannel;
NV_DECLARE_ALIGNED(NvU64 vMemPtr, 8);
} NV2080_CTRL_GR_CTXSW_SETUP_BIND_PARAMS;
/*
* NV2080_CTRL_CMD_GR_SET_GPC_TILE_MAP
*
@@ -1067,10 +1096,10 @@ typedef struct NV2080_CTRL_GR_GET_CTX_BUFFER_INFO_PARAMS {
NV_DECLARE_ALIGNED(NV2080_CTRL_GR_CTX_BUFFER_INFO ctxBufferInfo[NV2080_CTRL_GR_MAX_CTX_BUFFER_COUNT], 8);
} NV2080_CTRL_GR_GET_CTX_BUFFER_INFO_PARAMS;
// Aperture flags
#define NV2080_CTRL_GR_CTX_BUFFER_INFO_APERTURE_UNKNWON ADDR_UNKNOWN
#define NV2080_CTRL_GR_CTX_BUFFER_INFO_APERTURE_SYSMEM ADDR_SYSMEM
#define NV2080_CTRL_GR_CTX_BUFFER_INFO_APERTURE_FBMEM ADDR_FBMEM
// Aperture flags. The defines should match the defines in mem_desc.h
#define NV2080_CTRL_GR_CTX_BUFFER_INFO_APERTURE_UNKNOWN 0
#define NV2080_CTRL_GR_CTX_BUFFER_INFO_APERTURE_SYSMEM 1
#define NV2080_CTRL_GR_CTX_BUFFER_INFO_APERTURE_FBMEM 2
/*
* NV2080_CTRL_CMD_GR_GET_GLOBAL_SM_ORDER

241
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080internal.h
View File

@@ -76,6 +76,9 @@ typedef struct NV2080_CTRL_INTERNAL_DISPLAY_GET_STATIC_INFO_PARAMS {
NvBool bPrimaryVga;
NvU32 i2cPort;
NvU32 internalDispActiveMask;
NvU32 embeddedDisplayPortMask;
NvBool bExternalMuxSupported;
NvBool bInternalMuxSupported;
} NV2080_CTRL_INTERNAL_DISPLAY_GET_STATIC_INFO_PARAMS;
@@ -112,8 +115,6 @@ typedef struct NV2080_CTRL_INTERNAL_MEMSYS_GET_STATIC_CONFIG_PARAMS {
/*! L2 cache size */
NV_DECLARE_ALIGNED(NvU64 l2CacheSize, 8);
NvBool bReservedMemAtBottom;
/*! Indicate whether fpba is present or not */
NvBool bFbpaPresent;
@@ -123,9 +124,6 @@ typedef struct NV2080_CTRL_INTERNAL_MEMSYS_GET_STATIC_CONFIG_PARAMS {
/*! log32(comprPageSize) */
NvU32 comprPageShift;
/*! Maximum number of pages that can be dynamaically blacklisted */
NvU16 maximumBlacklistPages;
/*! RAM type */
NvU32 ramType;
@@ -134,12 +132,6 @@ typedef struct NV2080_CTRL_INTERNAL_MEMSYS_GET_STATIC_CONFIG_PARAMS {
/*! LTS per LTC count */
NvU32 ltsPerLtcCount;
/*! Ampere PLC bug */
NvBool bDisablePlcForCertainOffsetsBug3046774;
/*! FB override Start KB */
NV_DECLARE_ALIGNED(NvU64 fbOverrideStartKb, 8);
} NV2080_CTRL_INTERNAL_MEMSYS_GET_STATIC_CONFIG_PARAMS;
/*!
@@ -294,7 +286,7 @@ typedef struct NV2080_CTRL_INTERNAL_BSP_GET_CAPS_PARAMS {
*/
#define NV2080_CTRL_CMD_INTERNAL_MSENC_GET_CAPS (0x20800a25) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MSENC_GET_CAPS_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_CMD_INTERNAL_MAX_MSENCS 3
#define NV2080_CTRL_CMD_INTERNAL_MAX_MSENCS 8
typedef struct NV2080_CTRL_INTERNAL_MSENC_CAPS {
NvU8 capsTbl[NV0080_CTRL_MSENC_CAPS_TBL_SIZE];
@@ -558,7 +550,7 @@ typedef NV2080_CTRL_INTERNAL_STATIC_GR_GET_PPC_MASKS_PARAMS NV2080_CTRL_INTERNAL
#define NV2080_CTRL_INTERNAL_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_COUNT 0x19
#define NV2080_CTRL_INTERNAL_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_COUNT 0x1a
typedef struct NV2080_CTRL_INTERNAL_ENGINE_CONTEXT_BUFFER_INFO {
NvU32 size;
@@ -631,7 +623,6 @@ typedef struct NV2080_CTRL_INTERNAL_GPU_GET_CHIP_INFO_PARAMS {
NvU8 chipSubRev;
NvU32 emulationRev1;
NvBool isCmpSku;
NvU32 bar1Size;
NvU32 pciDeviceId;
NvU32 pciSubDeviceId;
NvU32 pciRevisionId;
@@ -805,7 +796,7 @@ typedef struct NV2080_CTRL_INTERNAL_DEVICE_INFO {
NvU32 runlistPriBase;
NvU32 groupId;
} NV2080_CTRL_INTERNAL_DEVICE_INFO;
#define NV2080_CTRL_CMD_INTERNAL_DEVICE_INFO_MAX_ENTRIES 88
#define NV2080_CTRL_CMD_INTERNAL_DEVICE_INFO_MAX_ENTRIES 256
#define NV2080_CTRL_CMD_INTERNAL_GET_DEVICE_INFO_TABLE (0x20800a40) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GET_DEVICE_INFO_TABLE_PARAMS_MESSAGE_ID" */
@@ -831,24 +822,6 @@ typedef struct NV2080_CTRL_INTERNAL_GPU_GET_USER_REGISTER_ACCESS_MAP_PARAMS {
NvU8 profilingRanges[NV2080_CTRL_INTERNAL_GPU_USER_REGISTER_ACCESS_MAP_MAX_PROFILING_RANGES];
} NV2080_CTRL_INTERNAL_GPU_GET_USER_REGISTER_ACCESS_MAP_PARAMS;
typedef struct NV2080_CTRL_INTERNAL_CONSTRUCTED_FALCON_INFO {
NvU32 engDesc;
NvU32 ctxAttr;
NvU32 ctxBufferSize;
NvU32 addrSpaceList;
NvU32 registerBase;
} NV2080_CTRL_INTERNAL_CONSTRUCTED_FALCON_INFO;
#define NV2080_CTRL_CMD_INTERNAL_MAX_CONSTRUCTED_FALCONS 0x40
#define NV2080_CTRL_CMD_INTERNAL_GET_CONSTRUCTED_FALCON_INFO (0x20800a42) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GET_CONSTRUCTED_FALCON_INFO_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_INTERNAL_GET_CONSTRUCTED_FALCON_INFO_PARAMS_MESSAGE_ID (0x42U)
typedef struct NV2080_CTRL_INTERNAL_GET_CONSTRUCTED_FALCON_INFO_PARAMS {
NvU32 numConstructedFalcons;
NV2080_CTRL_INTERNAL_CONSTRUCTED_FALCON_INFO constructedFalconsTable[NV2080_CTRL_CMD_INTERNAL_MAX_CONSTRUCTED_FALCONS];
} NV2080_CTRL_INTERNAL_GET_CONSTRUCTED_FALCON_INFO_PARAMS;
/**
* Get GR PDB properties synchronized between Kernel and Physical
*
@@ -858,6 +831,37 @@ typedef struct NV2080_CTRL_INTERNAL_GET_CONSTRUCTED_FALCON_INFO_PARAMS {
typedef struct NV2080_CTRL_INTERNAL_NV_RANGE {
NV_DECLARE_ALIGNED(NvU64 lo, 8);
NV_DECLARE_ALIGNED(NvU64 hi, 8);
} NV2080_CTRL_INTERNAL_NV_RANGE;
/*!
* NV2080_CTRL_INTERNAL_MIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS
*
* This structure specifies a target swizz-id and mem_range to update
*
* swizzId[IN]
* - Targeted swizz-id for which the memRange is being set
*
* memAddrRange[IN]
* - Memory Range for given GPU instance
*/
#define NV2080_CTRL_INTERNAL_MIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS_MESSAGE_ID (0x43U)
typedef struct NV2080_CTRL_INTERNAL_MIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS {
NvU32 swizzId;
NV_DECLARE_ALIGNED(NV2080_CTRL_INTERNAL_NV_RANGE memAddrRange, 8);
} NV2080_CTRL_INTERNAL_MIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS;
#define NV2080_CTRL_CMD_INTERNAL_KMIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE (0x20800a44) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_KMIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_INTERNAL_KMIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS_MESSAGE_ID (0x44U)
typedef NV2080_CTRL_INTERNAL_MIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS NV2080_CTRL_INTERNAL_KMIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS;
#define NV2080_CTRL_CMD_INTERNAL_MIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE (0x20800a43) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS_MESSAGE_ID" */
typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_PDB_PROPERTIES {
NvBool bPerSubCtxheaderSupported;
} NV2080_CTRL_INTERNAL_STATIC_GR_PDB_PROPERTIES;
@@ -1029,7 +1033,7 @@ typedef struct NV2080_CTRL_INTERNAL_DISPLAY_SETUP_RG_LINE_INTR_PARAMS {
* validGfxCTSIdMask [OUT]
* # mask of CTS IDs that contain Gfx capable Grs which can be assigned under this profile
*/
#define NV2080_CTRL_INTERNAL_GRMGR_PARTITION_MAX_TYPES 20
#define NV2080_CTRL_INTERNAL_GRMGR_PARTITION_MAX_TYPES 60
@@ -1104,10 +1108,12 @@ typedef struct NV2080_CTRL_INTERNAL_MEMSYS_SET_PARTITIONABLE_MEM_PARAMS {
#define NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PARTITIONABLE_ENGINES_MAX_ENGINES_MASK_SIZE 4
#define NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PARTITIONABLE_ENGINES_PARAMS_MESSAGE_ID (0x52U)
typedef struct NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PARTITIONABLE_ENGINES_PARAMS {
NV_DECLARE_ALIGNED(NvU64 engineMask, 8);
NV_DECLARE_ALIGNED(NvU64 engineMask[NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PARTITIONABLE_ENGINES_MAX_ENGINES_MASK_SIZE], 8);
} NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PARTITIONABLE_ENGINES_PARAMS;
#define NV2080_CTRL_INTERNAL_FIFO_MAX_RUNLIST_BUFFERS 2
@@ -1142,6 +1148,23 @@ typedef struct NV2080_CTRL_INTERNAL_DISPLAY_SET_IMP_INIT_INFO_PARAMS {
TEGRA_IMP_IMPORT_DATA tegraImpImportData;
} NV2080_CTRL_INTERNAL_DISPLAY_SET_IMP_INIT_INFO_PARAMS;
#define NV2080_CTRL_CMD_INTERNAL_GET_EGPU_BRIDGE_INFO (0x20800a55) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GET_EGPU_BRIDGE_INFO_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_INTERNAL_GET_EGPU_BRIDGE_INFO_PARAMS_MESSAGE_ID (0x55U)
typedef struct NV2080_CTRL_INTERNAL_GET_EGPU_BRIDGE_INFO_PARAMS {
NvU16 pciDeviceId;
NvU16 pciSubDeviceId;
NvBool iseGPUBridge;
NvU8 approvedBusType;
} NV2080_CTRL_INTERNAL_GET_EGPU_BRIDGE_INFO_PARAMS;
#define NV2080_CTRL_INTERNAL_EGPU_BUS_TYPE_NONE (0x00000000)
#define NV2080_CTRL_INTERNAL_EGPU_BUS_TYPE_CUSTOM (0x00000001)
#define NV2080_CTRL_INTERNAL_EGPU_BUS_TYPE_TB2 (0x00000002)
#define NV2080_CTRL_INTERNAL_EGPU_BUS_TYPE_TB3 (0x00000003)
/*!
* NV2080_CTRL_CMD_INTERNAL_BUS_FLUSH_WITH_SYSMEMBAR
*
@@ -1357,6 +1380,9 @@ typedef struct NV2080_CTRL_INTERNAL_VMMU_GET_SPA_FOR_GPA_ENTRIES_PARAMS {
* valid [IN]
* This bit indicates whether pushbuffer parameters are valid or not
*
* pbTargetAperture [IN]
* Indicates the PushBuffer Target Aperture type (IOVA, PCI, PCI_COHERENT or NVM)
*
*/
#define NV2080_CTRL_CMD_INTERNAL_DISPLAY_CHANNEL_PUSHBUFFER (0x20800a58) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_DISPLAY_CHANNEL_PUSHBUFFER_PARAMS_MESSAGE_ID" */
@@ -1370,6 +1396,7 @@ typedef struct NV2080_CTRL_INTERNAL_DISPLAY_CHANNEL_PUSHBUFFER_PARAMS {
NvU32 hclass;
NvU32 channelInstance;
NvBool valid;
NvU32 pbTargetAperture;
} NV2080_CTRL_INTERNAL_DISPLAY_CHANNEL_PUSHBUFFER_PARAMS;
/*!
@@ -1556,11 +1583,6 @@ typedef struct NV2080_CTRL_INTERNAL_DISPLAY_GET_ACTIVE_DISPLAY_DEVICES_PARAMS {
#define NV2080_CTRL_INTERNAL_MAX_SWIZZ_ID 15
typedef struct NV2080_CTRL_INTERNAL_NV_RANGE {
NV_DECLARE_ALIGNED(NvU64 lo, 8);
NV_DECLARE_ALIGNED(NvU64 hi, 8);
} NV2080_CTRL_INTERNAL_NV_RANGE;
#define NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES_PARAMS_MESSAGE_ID (0x60U)
typedef struct NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES_PARAMS {
@@ -2127,6 +2149,7 @@ typedef struct NV2080_CTRL_INTERNAL_KMIGMGR_EXPORTED_GPU_INSTANCE_INFO {
typedef struct NV2080_CTRL_INTERNAL_KMIGMGR_IMPORT_EXPORT_GPU_INSTANCE_PARAMS {
NvU32 swizzId;
NvU8 uuid[NV_GI_UUID_LEN];
NV_DECLARE_ALIGNED(NV2080_CTRL_INTERNAL_KMIGMGR_EXPORTED_GPU_INSTANCE_INFO info, 8);
} NV2080_CTRL_INTERNAL_KMIGMGR_IMPORT_EXPORT_GPU_INSTANCE_PARAMS;
@@ -2610,54 +2633,55 @@ typedef struct NV2080_CTRL_INTERNAL_BIF_SET_PCIE_RO_PARAMS {
} NV2080_CTRL_INTERNAL_BIF_SET_PCIE_RO_PARAMS;
/*
* NV2080_CTRL_CMD_INTERNAL_DISPLAY_UNIX_CONSOLE
* NV2080_CTRL_CMD_INTERNAL_DISPLAY_PRE_UNIX_CONSOLE
*
* An internal call to invoke the sequence VGA register reads & writes to
* perform save and restore of VGA
*
* [in] saveOrRestore
* [in] bSave
* To indicate whether save or restore needs to be performed.
* [in] useVbios
* [in] bUseVbios
* Primary VGA indication from OS.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_GENERIC
* NV_ERR_INVALID_OPERATION
* NV_ERR_NOT_SUPPORTED
*/
#define NV2080_CTRL_CMD_INTERNAL_DISPLAY_UNIX_CONSOLE (0x20800a76) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_DISPLAY_UNIX_CONSOLE_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_CMD_INTERNAL_DISPLAY_PRE_UNIX_CONSOLE (0x20800a76) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_DISPLAY_PRE_UNIX_CONSOLE_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_CMD_INTERNAL_DISPLAY_UNIX_CONSOLE_PARAMS_MESSAGE_ID (0x76U)
#define NV2080_CTRL_CMD_INTERNAL_DISPLAY_PRE_UNIX_CONSOLE_PARAMS_MESSAGE_ID (0x76U)
typedef struct NV2080_CTRL_CMD_INTERNAL_DISPLAY_UNIX_CONSOLE_PARAMS {
NvBool bSaveOrRestore;
typedef struct NV2080_CTRL_CMD_INTERNAL_DISPLAY_PRE_UNIX_CONSOLE_PARAMS {
NvBool bSave;
NvBool bUseVbios;
} NV2080_CTRL_CMD_INTERNAL_DISPLAY_UNIX_CONSOLE_PARAMS;
} NV2080_CTRL_CMD_INTERNAL_DISPLAY_PRE_UNIX_CONSOLE_PARAMS;
/*!
* NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_RESTORE
* NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_UNIX_CONSOLE
*
* To perform restore operation from saved fonts.
* To perform save or restore operation from/to saved fonts.
*
* [in] saveOrRestore
* [in] bSave
* To indicate whether save or restore needs to be performed.
* [in] useVbios
* [in] bUseVbios
* Primary VGA indication from OS.
* [in] bVbiosCallSuccessful
* Indicates if vbios invocation was successful or not.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_GENERIC
* NV_ERR_NOT_SUPPORTED
*/
#define NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_RESTORE (0x20800a77) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_RESTORE_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_UNIX_CONSOLE (0x20800a77) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_UNIX_CONSOLE_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_RESTORE_PARAMS_MESSAGE_ID (0x77U)
#define NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_UNIX_CONSOLE_PARAMS_MESSAGE_ID (0x77U)
typedef struct NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_RESTORE_PARAMS {
NvBool bWriteCr;
} NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_RESTORE_PARAMS;
typedef struct NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_UNIX_CONSOLE_PARAMS {
NvBool bSave;
NvBool bUseVbios;
NvBool bVbiosCallSuccessful;
} NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_UNIX_CONSOLE_PARAMS;
/*!
* @ref NV2080_CTRL_CMD_INTERNAL_STATIC_MIGMGR_GET_COMPUTE_PROFILES
@@ -3683,22 +3707,6 @@ typedef struct NV2080_CTRL_INTERNAL_CONF_COMPUTE_GET_STATIC_INFO_PARAMS {
NvBool bIsPcieTrusted;
} NV2080_CTRL_INTERNAL_CONF_COMPUTE_GET_STATIC_INFO_PARAMS;
/*!
* NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_ENCRYPTION_CONTROL
*
* This command is used to trigger the initialization / suspension of encrypted RPCs for Confidential Compute.
* bEncryptionControl : [IN]
* NV_TRUE indicates initialization.
* NV_FALSE indicates suspension.
*/
#define NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_ENCRYPTION_CONTROL (0x208001b2) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_ENCRYPTION_CONTROL_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_ENCRYPTION_CONTROL_PARAMS_MESSAGE_ID (0xB2U)
typedef struct NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_ENCRYPTION_CONTROL_PARAMS {
NvBool bEncryptionControl;
} NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_ENCRYPTION_CONTROL_PARAMS;
/*!
* NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_DERIVE_SWL_KEYS
*
@@ -3749,6 +3757,25 @@ typedef struct NV2080_CTRL_INTERNAL_CONF_COMPUTE_DERIVE_LCE_KEYS_PARAMS {
NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK ivMaskSet[NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK_LCE_COUNT];
} NV2080_CTRL_INTERNAL_CONF_COMPUTE_DERIVE_LCE_KEYS_PARAMS;
/*!
* NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_SET_GPU_STATE
*
* This control call can be used to set gpu state on GSP to accept client requests
* or to block client requests.
* This is a internal command sent from Kernel RM to Physical RM.
*
* bAcceptClientRequest:[IN]
* NV_TRUE : set gpu state to accept client work requests
* NV_FALSE: set gpu state to block client work requests
*
*/
#define NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_SET_GPU_STATE (0x20800ae7) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_SET_GPU_STATE_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_SET_GPU_STATE_PARAMS_MESSAGE_ID (0xE7U)
typedef struct NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_SET_GPU_STATE_PARAMS {
NvBool bAcceptClientRequest;
} NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_SET_GPU_STATE_PARAMS;
/*
@@ -3960,4 +3987,64 @@ typedef struct NV2080_CTRL_INTERNAL_USER_SHARED_DATA_SET_DATA_POLL_PARAMS {
} NV2080_CTRL_INTERNAL_USER_SHARED_DATA_SET_DATA_POLL_PARAMS;
#define NV2080_CTRL_CMD_INTERNAL_USER_SHARED_DATA_SET_DATA_POLL (0x20800aff) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_USER_SHARED_DATA_SET_DATA_POLL_PARAMS_MESSAGE_ID" */
/*!
* NV2080_CTRL_CMD_INTERNAL_GSP_START_TRACE_INFO_PARAMS
*
* This structure provides the params for starting GPU Fabric Probe
*
* tracepointMask[IN]
* - tracepoint selection filter
* bufferSize[IN]
* - size of gsp side logging buffer
* bufferWatermark[IN]
* - entry threshold for GSP to issue RPC of logged entries to kernel RM
* bStart[IN]
* - if true, start tracing. if false, stop tracing.
*/
#define NV2080_CTRL_CMD_INTERNAL_GSP_START_TRACE_INFO_PARAMS_MESSAGE_ID (0xE3U)
typedef struct NV2080_CTRL_CMD_INTERNAL_GSP_START_TRACE_INFO_PARAMS {
NV_DECLARE_ALIGNED(NvU64 tracepointMask, 8);
NvU32 bufferSize;
NvU32 bufferWatermark;
NvBool bStart;
} NV2080_CTRL_CMD_INTERNAL_GSP_START_TRACE_INFO_PARAMS;
/*
* NV2080_CTRL_CMD_INTERNAL_GSP_START_TRACE
*
* This command is used to start GSP-RM trace tool.
* This command accepts NV2080_CTRL_CMD_INTERNAL_GSP_START_TRACE_INFO_PARAMS
*
*/
#define NV2080_CTRL_CMD_INTERNAL_GSP_START_TRACE (0x208001e3) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_GSP_START_TRACE_INFO_PARAMS_MESSAGE_ID" */
/*
* NV2080_CTRL_CMD_INTERNAL_GET_ENABLED_SEC2_CLASSES
*
* @brief get state (enabled/disabled) of SEC2 classes
*
*
* @return NV_OK on success
* @return NV_ERR_ otherwise
*/
#define NV2080_CTRL_CMD_INTERNAL_GET_ENABLED_SEC2_CLASSES_PARAMS_MESSAGE_ID (0xAFU)
typedef struct NV2080_CTRL_CMD_INTERNAL_GET_ENABLED_SEC2_CLASSES_PARAMS {
NvBool bMaxwellSec2Enabled;
NvBool bNv95A1TsecEnabled;
NvBool bHopperSec2WorkLaunchAEnabled;
} NV2080_CTRL_CMD_INTERNAL_GET_ENABLED_SEC2_CLASSES_PARAMS;
#define NV2080_CTRL_CMD_INTERNAL_GET_ENABLED_SEC2_CLASSES (0x20800aaf) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_GET_ENABLED_SEC2_CLASSES_PARAMS_MESSAGE_ID" */
/*!
* @ref NV2080_CTRL_CMD_INTERNAL_GR_CTXSW_SETUP_BIND
*/
#define NV2080_CTRL_CMD_INTERNAL_GR_CTXSW_SETUP_BIND (0x20800ae4) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GR_CTXSW_SETUP_BIND_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_INTERNAL_GR_CTXSW_SETUP_BIND_PARAMS_MESSAGE_ID (0xE4U)
typedef NV2080_CTRL_GR_CTXSW_SETUP_BIND_PARAMS NV2080_CTRL_INTERNAL_GR_CTXSW_SETUP_BIND_PARAMS;
/* ctrl2080internal_h */

152
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080nvd.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2004-2015 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2004-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -209,44 +209,61 @@ typedef struct NV2080_NOCAT_JOURNAL_RECORD {
// NOCAT activity counter indexes
// collection activity
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_COLLECT_REQ_IDX 0
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_ALLOCATED_IDX 1
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_COLLECTED_IDX 2
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_ALLOC_FAILED_IDX 3
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_COLLECT_FAILED_IDX 4
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_COLLECT_REQ_DROPPED_IDX 5
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_COLLECT_REQ_IDX 0
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_GRANDFATHERED_RECORD_IDX 1
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_ALLOCATED_IDX 2
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_COLLECTED_IDX 3
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_NOTIFICATIONS_IDX 4
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_ALLOC_FAILED_IDX 5
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_COLLECT_FAILED_IDX 6
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_COLLECT_LOCKED_OUT_IDX 7
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_CTRL_INSERT_RECORDS_IDX 8
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_RPC_INSERT_RECORDS_IDX 9
// Journal Lock activity
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_JOURNAL_LOCKED_IDX 10
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_JOURNAL_LOCK_UPDATED_IDX 11
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_JOURNAL_UNLOCKED_IDX 12
// lookup activity
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_NO_RECORDS_IDX 13
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_BAD_BUFFER_IDX 14
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_MATCH_FOUND_IDX 15
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_NO_MATCH_IDX 16
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_CLOSEST_FOUND_IDX 17
// reporting activity
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_REQUESTED_IDX 6
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_REPORTED_IDX 7
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_DROPPED_IDX 8
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_MISSED_IDX 9
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_REQUESTED_IDX 18
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_REPORTED_IDX 19
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_DROPPED_IDX 20
// update activity
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_UPDATE_REQ_IDX 10
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_UPDATED_IDX 11
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_UPDATE_FAILED_IDX 12
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_UPDATE_REQ_IDX 21
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_UPDATED_IDX 22
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_UPDATE_FAILED_IDX 23
// general errors
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_BUSY_IDX 13
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_BAD_PARAM_IDX 14
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_BAD_TYPE_IDX 15
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_BUSY_IDX 24
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_BAD_PARAM_IDX 25
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_BAD_TYPE_IDX 26
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_RES1_IDX 16
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_RES2_IDX 17
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_CACHE_UPDATE_IDX 18
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_INSERT_RECORDS_IDX 19
// reserved entries for temporary use.
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_RES5_IDX 27
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_RES4_IDX 28
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_RES3_IDX 29
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_RES2_IDX 30
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_RES1_IDX 31
// this should be relative to the highest counter index
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_COUNTER_COUNT (0x14) /* finn: Evaluated from "NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_INSERT_RECORDS_IDX + 1" */
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_COUNTER_COUNT (0x20) /* finn: Evaluated from "NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_RES1_IDX + 1" */
#define NV2080_CTRL_NOCAT_GET_COUNTERS_ONLY 0:0
#define NV2080_CTRL_NOCAT_GET_COUNTERS_ONLY_YES 1
#define NV2080_CTRL_NOCAT_GET_COUNTERS_ONLY_NO 0
#define NV2080_CTRL_NOCAT_GET_COUNTERS_ONLY_YES 1
#define NV2080_CTRL_NOCAT_GET_COUNTERS_ONLY_NO 0
#define NV2080_CTRL_NOCAT_GET_RESET_COUNTERS 1:1
#define NV2080_CTRL_NOCAT_GET_RESET_COUNTERS_YES 1
#define NV2080_CTRL_NOCAT_GET_RESET_COUNTERS_NO 0
#define NV2080_CTRL_NOCAT_GET_RESET_COUNTERS_YES 1
#define NV2080_CTRL_NOCAT_GET_RESET_COUNTERS_NO 0
#define NV2080_CTRL_NVD_GET_NOCAT_JOURNAL_PARAMS_MESSAGE_ID (0x9U)
@@ -266,7 +283,7 @@ typedef struct NV2080_CTRL_NVD_GET_NOCAT_JOURNAL_PARAMS {
* This command reports the TDR data collected by KMD to be added to the
* nocat record
*
* dataType:
* dataType
* [IN] specifies the type of data provided.
* targetRecordType
* [IN] specifies record type the data is intended for.
@@ -274,23 +291,22 @@ typedef struct NV2080_CTRL_NVD_GET_NOCAT_JOURNAL_PARAMS {
* [IN] specifies the data to be added.
*/
#define NV2080_CTRL_CMD_NVD_SET_NOCAT_JOURNAL_DATA (0x2080240b) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVD_INTERFACE_ID << 8) | NV2080_CTRL_NVD_SET_NOCAT_JOURNAL_DATA_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_CMD_NVD_SET_NOCAT_JOURNAL_DATA (0x2080240b) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVD_INTERFACE_ID << 8) | NV2080_CTRL_NVD_SET_NOCAT_JOURNAL_DATA_PARAMS_MESSAGE_ID" */
// data types & structures
#define NV2080_CTRL_NOCAT_JOURNAL_DATA_TYPE_EMPTY 0
#define NV2080_CTRL_NOCAT_JOURNAL_DATA_TYPE_TDR_REASON 1
#define NV2080_CTRL_NOCAT_JOURNAL_DATA_TYPE_INSERT_RECORD 2
#define NV2080_CTRL_NOCAT_JOURNAL_DATA_TYPE_SET_TAG 3
#define NV2080_CTRL_NOCAT_JOURNAL_DATA_TYPE_RCLOG 4
#define NV2080_CTRL_NOCAT_JOURNAL_DATA_TYPE_EMPTY 0
#define NV2080_CTRL_NOCAT_JOURNAL_DATA_TYPE_TDR_REASON 1
#define NV2080_CTRL_NOCAT_JOURNAL_DATA_TYPE_SET_TAG 2
#define NV2080_CTRL_NOCAT_JOURNAL_DATA_TYPE_RCLOG 3
#define NV2080_CTRL_NOCAT_TDR_TYPE_NONE 0
#define NV2080_CTRL_NOCAT_TDR_TYPE_LEGACY 1
#define NV2080_CTRL_NOCAT_TDR_TYPE_FULLCHIP 2
#define NV2080_CTRL_NOCAT_TDR_TYPE_BUSRESET 3
#define NV2080_CTRL_NOCAT_TDR_TYPE_GC6_RESET 4
#define NV2080_CTRL_NOCAT_TDR_TYPE_SURPRISE_REMOVAL 5
#define NV2080_CTRL_NOCAT_TDR_TYPE_UCODE_RESET 6
#define NV2080_CTRL_NOCAT_TDR_TYPE_TEST 7
#define NV2080_CTRL_NOCAT_TDR_TYPE_NONE 0
#define NV2080_CTRL_NOCAT_TDR_TYPE_LEGACY 1
#define NV2080_CTRL_NOCAT_TDR_TYPE_FULLCHIP 2
#define NV2080_CTRL_NOCAT_TDR_TYPE_BUSRESET 3
#define NV2080_CTRL_NOCAT_TDR_TYPE_GC6_RESET 4
#define NV2080_CTRL_NOCAT_TDR_TYPE_SURPRISE_REMOVAL 5
#define NV2080_CTRL_NOCAT_TDR_TYPE_UCODE_RESET 6
#define NV2080_CTRL_NOCAT_TDR_TYPE_TEST 7
typedef struct NV2080CtrlNocatJournalDataTdrReason {
NvU32 flags;
@@ -300,23 +316,6 @@ typedef struct NV2080CtrlNocatJournalDataTdrReason {
NvU32 reasonCode;
} NV2080CtrlNocatJournalDataTdrReason;
#define NV2080_CTRL_NOCAT_INSERT_ALLOW_NULL_STR 0:0
#define NV2080_CTRL_NOCAT_INSERT_ALLOW_NULL_STR_YES 1
#define NV2080_CTRL_NOCAT_INSERT_ALLOW_NULL_STR_NO 0
#define NV2080_CTRL_NOCAT_INSERT_ALLOW_0_LEN_BUFFER 1:1
#define NV2080_CTRL_NOCAT_INSERT_ALLOW_0_LEN_BUFFER_YES 1
#define NV2080_CTRL_NOCAT_INSERT_ALLOW_0_LEN_BUFFER_NO 0
typedef struct NV2080CtrlNocatJournalInsertRecord {
NvU32 flags;
NvU8 recType;
NvU32 bugcheck;
NvU8 source[NV2080_NOCAT_JOURNAL_MAX_STR_LEN];
NvU32 subsystem;
NV_DECLARE_ALIGNED(NvU64 errorCode, 8);
NvU8 faultingEngine[NV2080_NOCAT_JOURNAL_MAX_STR_LEN];
NvU32 tdrReason;
} NV2080CtrlNocatJournalInsertRecord;
#define NV2080_CTRL_NOCAT_TAG_CLEAR 0:0
#define NV2080_CTRL_NOCAT_TAG_CLEAR_YES 1
#define NV2080_CTRL_NOCAT_TAG_CLEAR_NO 0
@@ -342,9 +341,44 @@ typedef struct NV2080_CTRL_NVD_SET_NOCAT_JOURNAL_DATA_PARAMS {
NvU32 targetRecordType;
union {
NV_DECLARE_ALIGNED(NV2080CtrlNocatJournalDataTdrReason tdrReason, 8);
NV_DECLARE_ALIGNED(NV2080CtrlNocatJournalInsertRecord insertData, 8);
NV2080CtrlNocatJournalSetTag tagData;
NV2080CtrlNocatJournalRclog rclog;
} nocatJournalData;
} NV2080_CTRL_NVD_SET_NOCAT_JOURNAL_DATA_PARAMS;
/*
* NV2080_CTRL_CMD_NVD_INSERT_NOCAT_JOURNAL_RECORD
*
* This command Inserts a NOCAT Journal record from an outside component.
*
* nocatJournalData
* [IN] specifies the data to be added.
*/
#define NV2080_CTRL_CMD_NVD_INSERT_NOCAT_JOURNAL_RECORD (0x2080240c) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVD_INTERFACE_ID << 8) | NV2080_CTRL_CMD_NVD_INSERT_NOCAT_JOURNAL_RECORD_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_NOCAT_INSERT_ALLOW_NULL_STR 0:0
#define NV2080_CTRL_NOCAT_INSERT_ALLOW_NULL_STR_YES 1
#define NV2080_CTRL_NOCAT_INSERT_ALLOW_NULL_STR_NO 0
#define NV2080_CTRL_NOCAT_INSERT_ALLOW_0_LEN_BUFFER 1:1
#define NV2080_CTRL_NOCAT_INSERT_ALLOW_0_LEN_BUFFER_YES 1
#define NV2080_CTRL_NOCAT_INSERT_ALLOW_0_LEN_BUFFER_NO 0
typedef struct NV2080CtrlNocatJournalInsertRecord {
NvU32 flags;
NV_DECLARE_ALIGNED(NvU64 timestamp, 8);
NvU8 recType;
NvU32 bugcheck;
char source[NV2080_NOCAT_JOURNAL_MAX_STR_LEN];
NvU32 subsystem;
NV_DECLARE_ALIGNED(NvU64 errorCode, 8);
char faultingEngine[NV2080_NOCAT_JOURNAL_MAX_STR_LEN];
NvU32 tdrReason;
NvU32 diagBufferLen;
NvU8 diagBuffer[NV2080_NOCAT_JOURNAL_MAX_DIAG_BUFFER];
} NV2080CtrlNocatJournalInsertRecord;
#define NV2080_CTRL_CMD_NVD_INSERT_NOCAT_JOURNAL_RECORD_PARAMS_MESSAGE_ID (0xCU)
typedef struct NV2080_CTRL_CMD_NVD_INSERT_NOCAT_JOURNAL_RECORD_PARAMS {
NV_DECLARE_ALIGNED(NV2080CtrlNocatJournalInsertRecord nocatJournalRecord, 8);
} NV2080_CTRL_CMD_NVD_INSERT_NOCAT_JOURNAL_RECORD_PARAMS;
/* _ctr2080nvd_h_ */

67
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080nvlink.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2014-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2014-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -31,6 +31,7 @@
//
#include "ctrl/ctrl2080/ctrl2080base.h"
#include "nvcfg_sdk.h"
/* NV20_SUBDEVICE_XX bus control commands and parameters */
@@ -809,6 +810,8 @@ typedef struct NV2080_CTRL_NVLINK_CLEAR_COUNTERS_PARAMS {
NV_DECLARE_ALIGNED(NvU64 linkMask, 8);
} NV2080_CTRL_NVLINK_CLEAR_COUNTERS_PARAMS;
/*
* NV2080_CTRL_CMD_NVLINK_INJECT_ERROR
* This command causes all the same actions to occur as if the related
@@ -820,7 +823,7 @@ typedef struct NV2080_CTRL_NVLINK_CLEAR_COUNTERS_PARAMS {
* This parameter specifies that the error should be fatal.
*
*/
#define NV2080_CTRL_CMD_NVLINK_INJECT_ERROR (0x20803006U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_INJECT_ERROR_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_CMD_NVLINK_INJECT_ERROR (0x20803006U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_INJECT_ERROR_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_NVLINK_INJECT_ERROR_PARAMS_MESSAGE_ID (0x6U)
@@ -1655,13 +1658,23 @@ typedef struct NV2080_CTRL_NVLINK_ENABLE_NVLINK_PEER_PARAMS {
NvBool bEnable;
} NV2080_CTRL_NVLINK_ENABLE_NVLINK_PEER_PARAMS;
#define NV2080_CTRL_NVLINK_GET_LP_COUNTERS_COUNT_TX_NVHS 0U
#define NV2080_CTRL_NVLINK_GET_LP_COUNTERS_COUNT_TX_EIGHTH 1U
#define NV2080_CTRL_NVLINK_GET_LP_COUNTERS_COUNT_TX_OTHER 2U
#define NV2080_CTRL_NVLINK_GET_LP_COUNTERS_NUM_TX_LP_ENTER 3U
#define NV2080_CTRL_NVLINK_GET_LP_COUNTERS_NUM_TX_LP_EXIT 4U
#define NV2080_CTRL_NVLINK_GET_LP_COUNTERS_COUNT_TX_SLEEP 5U
#define NV2080_CTRL_NVLINK_GET_LP_COUNTERS_MAX_COUNTERS 6U
#define NV2080_CTRL_NVLINK_GET_LP_COUNTERS_COUNT_TX_NVHS 0U
#define NV2080_CTRL_NVLINK_GET_LP_COUNTERS_COUNT_TX_EIGHTH 1U
#define NV2080_CTRL_NVLINK_GET_LP_COUNTERS_COUNT_TX_OTHER 2U
#define NV2080_CTRL_NVLINK_GET_LP_COUNTERS_NUM_TX_LP_ENTER 3U
#define NV2080_CTRL_NVLINK_GET_LP_COUNTERS_NUM_TX_LP_EXIT 4U
#define NV2080_CTRL_NVLINK_GET_LP_COUNTERS_COUNT_TX_SLEEP 5U
#define NV2080_CTRL_NVLINK_GET_LP_COUNTERS_HS_TIME 6U
#define NV2080_CTRL_NVLINK_GET_LP_COUNTERS_LOCAL_FULL_BW_EXIT_TIME 7U
#define NV2080_CTRL_NVLINK_GET_LP_COUNTERS_LOCAL_LP_ENTRY_TIME 8U
#define NV2080_CTRL_NVLINK_GET_LP_COUNTERS_LOCAL_LP_EXIT_TIME 9U
#define NV2080_CTRL_NVLINK_GET_LP_COUNTERS_LOCAL_FULL_BW_ENTRY_TIME 10U
#define NV2080_CTRL_NVLINK_GET_LP_COUNTERS_REMOTE_FULL_BW_EXIT_TIME 11U
#define NV2080_CTRL_NVLINK_GET_LP_COUNTERS_REMOTE_LP_ENTRY_TIME 12U
#define NV2080_CTRL_NVLINK_GET_LP_COUNTERS_REMOTE_LP_EXIT_TIME 13U
#define NV2080_CTRL_NVLINK_GET_LP_COUNTERS_REMOTE_FULL_BW_ENTRY_TIME 14U
#define NV2080_CTRL_NVLINK_GET_LP_COUNTERS_OTHER_STATE_TIME 15U
#define NV2080_CTRL_NVLINK_GET_LP_COUNTERS_MAX_COUNTERS 16U
/*
* NV2080_CTRL_CMD_NVLINK_GET_LP_COUNTERS
@@ -1694,6 +1707,8 @@ typedef struct NV2080_CTRL_NVLINK_GET_LP_COUNTERS_PARAMS {
#define NV2080_CTRL_CMD_NVLINK_GET_LP_COUNTERS (0x20803018U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_GET_LP_COUNTERS_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_CMD_NVLINK_CLEAR_LP_COUNTERS (0x20803052U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8 | 0x52)" */
/*
* NVLINK Link states
* These should ALWAYS match the nvlink core library defines in nvlink.h
@@ -2830,6 +2845,7 @@ typedef struct NV2080_CTRL_NVLINK_PROCESS_INIT_DISABLED_LINKS_PARAMS {
* cmd [IN] enum identifying the EOM related command for the driver to process
* link [IN] linkId
* params [IN] NvU32 word that is written into NV_PMINION_SCRATCH_SWRW_0 before calling CONFIGEOM dlcmd
* measurements [OUT] output of EOM
*
* Params Packing is specified in Minion IAS
*/
@@ -2841,27 +2857,37 @@ typedef enum NV2080_CTRL_CMD_NVLINK_EOM_CONTROL_PARAMS_COMMAND {
NVLINK_EOM_CONTROL_FULL_EOM_SEQUENCE = 3,
} NV2080_CTRL_CMD_NVLINK_EOM_CONTROL_PARAMS_COMMAND;
typedef struct NV2080_CTRL_NVLINK_EOM_MEASUREMENT {
NvU8 upper;
NvU8 middle;
NvU8 lower;
NvU8 composite;
} NV2080_CTRL_NVLINK_EOM_MEASUREMENT;
#define NV2080_CTRL_NVLINK_EOM_CONTROL_PARAMS_MESSAGE_ID (0x3cU)
typedef struct NV2080_CTRL_NVLINK_EOM_CONTROL_PARAMS {
NV2080_CTRL_CMD_NVLINK_EOM_CONTROL_PARAMS_COMMAND cmd;
NvU32 linkId;
NvU32 params;
NV2080_CTRL_NVLINK_EOM_MEASUREMENT measurements[NV2080_CTRL_NVLINK_MAX_LANES];
} NV2080_CTRL_NVLINK_EOM_CONTROL_PARAMS;
#define NV2080_CTRL_CMD_NVLINK_EOM_CONTROL (0x2080303c) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_EOM_CONTROL_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_CMD_NVLINK_EOM_CONTROL (0x2080303c) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_EOM_CONTROL_PARAMS_MESSAGE_ID" */
/*!
* Inband Recieved Data
* Inband Received Data
*/
#define NV2080_CTRL_NVLINK_INBAND_MAX_MSG_SIZE 4096
#define NV2080_CTRL_NVLINK_INBAND_MAX_DATA_SIZE 5120
#define NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_PARAMS_MESSAGE_ID (0x3dU)
typedef struct NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_PARAMS {
NvU8 data[NV2080_CTRL_NVLINK_INBAND_MAX_MSG_SIZE];
NvU8 data[NV2080_CTRL_NVLINK_INBAND_MAX_DATA_SIZE];
NvU32 dataSize;
} NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_PARAMS;
#define NV2080_CTRL_CMD_READ_NVLINK_INBAND_RESPONSE (0x2080303d) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_PARAMS_MESSAGE_ID" */
/*
* NV2080_CTRL_CMD_NVLINK_SET_L1_THRESHOLD
*
@@ -2909,7 +2935,7 @@ typedef struct NV2080_CTRL_NVLINK_GET_L1_THRESHOLD_PARAMS {
#define NV2080_CTRL_NVLINK_INBAND_SEND_DATA_PARAMS_MESSAGE_ID (0x40U)
typedef struct NV2080_CTRL_NVLINK_INBAND_SEND_DATA_PARAMS {
NvU8 buffer[NV2080_CTRL_NVLINK_INBAND_MAX_MSG_SIZE];
NvU8 buffer[NV2080_CTRL_NVLINK_INBAND_MAX_DATA_SIZE];
NvU32 dataSize;
} NV2080_CTRL_NVLINK_INBAND_SEND_DATA_PARAMS;
@@ -3074,5 +3100,18 @@ typedef struct NV2080_CTRL_NVLINK_IS_REDUCED_CONFIG_PARAMS {
#define NV2080_CTRL_CMD_NVLINK_IS_REDUCED_CONFIG (0x20803046U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_IS_REDUCED_CONFIG_PARAMS_MESSAGE_ID" */
/*!
*
* NV2080_CTRL_CMD_NVLINK_ENABLE_LINKS
*
* Nvlink Fatal Error Recovery
* This command accepts no parameters.
*
*/
#define NV2080_CTRL_CMD_NVLINK_FATAL_ERROR_RECOVERY (0x20803048U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | 0x48" */
/* _ctrl2080nvlink_h_ */

252
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080perf.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2005-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2005-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -444,6 +444,14 @@ typedef struct NV2080_CTRL_PERF_GPUMON_PERFMON_UTIL_SAMPLE {
* NV DECODER utilization sample.
*/
NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE nvdec;
/*!
* NV JPEG utilization sample.
*/
NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE nvjpg;
/*!
* NV OFA utilization sample.
*/
NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE nvofa;
} NV2080_CTRL_PERF_GPUMON_PERFMON_UTIL_SAMPLE;
/*!
@@ -582,5 +590,247 @@ typedef struct NV2080_CTRL_PERF_AGGRESSIVE_PSTATE_NOTIFY_PARAMS {
} NV2080_CTRL_PERF_AGGRESSIVE_PSTATE_NOTIFY_PARAMS;
typedef struct NV2080_CTRL_PERF_GET_CLK_INFO {
NvU32 flags;
NvU32 domain;
NvU32 currentFreq;
NvU32 defaultFreq;
NvU32 minFreq;
NvU32 maxFreq;
} NV2080_CTRL_PERF_GET_CLK_INFO;
#define NV2080_CTRL_PERF_CLK_MAX_DOMAINS 32U
#define NV2080_CTRL_CMD_PERF_GET_LEVEL_INFO (0x20802002) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_PERF_INTERFACE_ID << 8) | NV2080_CTRL_PERF_GET_LEVEL_INFO_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_PERF_GET_LEVEL_INFO_PARAMS_MESSAGE_ID (0x2U)
typedef struct NV2080_CTRL_PERF_GET_LEVEL_INFO_PARAMS {
NvU32 level;
NvU32 flags;
NV_DECLARE_ALIGNED(NvP64 perfGetClkInfoList, 8);
NvU32 perfGetClkInfoListSize;
} NV2080_CTRL_PERF_GET_LEVEL_INFO_PARAMS;
#define NV2080_CTRL_CMD_PERF_GET_LEVEL_INFO_V2 (0x2080200b) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_PERF_INTERFACE_ID << 8) | NV2080_CTRL_PERF_GET_LEVEL_INFO_V2_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_PERF_GET_LEVEL_INFO_V2_PARAMS_MESSAGE_ID (0xBU)
typedef struct NV2080_CTRL_PERF_GET_LEVEL_INFO_V2_PARAMS {
NvU32 level;
NvU32 flags;
NV2080_CTRL_PERF_GET_CLK_INFO perfGetClkInfoList[NV2080_CTRL_PERF_CLK_MAX_DOMAINS];
NvU32 perfGetClkInfoListSize;
} NV2080_CTRL_PERF_GET_LEVEL_INFO_V2_PARAMS;
#define NV2080_CTRL_PERF_GET_LEVEL_INFO_FLAGS_TYPE 0:0
#define NV2080_CTRL_PERF_GET_LEVEL_INFO_FLAGS_TYPE_DEFAULT (0x00000000)
#define NV2080_CTRL_PERF_GET_LEVEL_INFO_FLAGS_TYPE_OVERCLOCK (0x00000001)
#define NV2080_CTRL_PERF_GET_LEVEL_INFO_FLAGS_MODE 2:1
#define NV2080_CTRL_PERF_GET_LEVEL_INFO_FLAGS_MODE_NONE (0x00000000)
#define NV2080_CTRL_PERF_GET_LEVEL_INFO_FLAGS_MODE_DESKTOP (0x00000001)
#define NV2080_CTRL_PERF_GET_LEVEL_INFO_FLAGS_MODE_MAXPERF (0x00000002)
/*
* NV2080_CTRL_CMD_PERF_GET_VID_ENG_PERFMON_SAMPLE
*
* This command can be used to obtain video decoder utilization of
* the associated subdevice.
* This command is not supported with SMC enabled.
*
* engineType
* This parameter will allow clients to set type of video
* engine in question. It can be NVENC or NVDEC.
* clkPercentBusy
* This parameter contains the percentage during the sample that
* the clock remains busy.
* samplingPeriodUs
* This field returns the sampling period in microseconds.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_PARAM_STRUCT
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_NOT_SUPPORTED
*/
#define NV2080_CTRL_CMD_PERF_GET_VID_ENG_PERFMON_SAMPLE (0x20802087) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_PERF_INTERFACE_ID << 8) | NV2080_CTRL_PERF_GET_VID_ENG_PERFMON_SAMPLE_PARAMS_MESSAGE_ID" */
typedef enum NV2080_CTRL_CMD_PERF_VID_ENG {
/*!
* GPU Video encoder engine.
*/
NV2080_CTRL_CMD_PERF_VID_ENG_NVENC = 1,
/*!
* GPU video decoder engine.
*/
NV2080_CTRL_CMD_PERF_VID_ENG_NVDEC = 2,
/*!
* GPU JPEG engine.
*/
NV2080_CTRL_CMD_PERF_VID_ENG_NVJPG = 3,
/*!
* GPU OFA engine.
*/
NV2080_CTRL_CMD_PERF_VID_ENG_NVOFA = 4,
} NV2080_CTRL_CMD_PERF_VID_ENG;
#define NV2080_CTRL_PERF_GET_VID_ENG_PERFMON_SAMPLE_PARAMS_MESSAGE_ID (0x87U)
typedef struct NV2080_CTRL_PERF_GET_VID_ENG_PERFMON_SAMPLE_PARAMS {
NV2080_CTRL_CMD_PERF_VID_ENG engineType;
NvU32 clkPercentBusy;
NvU32 samplingPeriodUs;
} NV2080_CTRL_PERF_GET_VID_ENG_PERFMON_SAMPLE_PARAMS;
/*
* NV2080_CTRL_CMD_PERF_GET_POWERSTATE
*
* This command can be used to find out whether the perf power state is AC/battery.
*
* powerStateInfo
* This parameter specifies the power source type.
*
* Possible status values returned are:
* NV_OK
*/
#define NV2080_CTRL_CMD_PERF_GET_POWERSTATE (0x2080205a) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_PERF_INTERFACE_ID << 8) | NV2080_CTRL_PERF_GET_POWERSTATE_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_PERF_GET_POWERSTATE_PARAMS_MESSAGE_ID (0x5AU)
typedef struct NV2080_CTRL_PERF_GET_POWERSTATE_PARAMS {
NV2080_CTRL_PERF_POWERSTATE_PARAMS powerStateInfo;
} NV2080_CTRL_PERF_GET_POWERSTATE_PARAMS;
/*
* NV2080_CTRL_CMD_PERF_NOTIFY_VIDEOEVENT
*
* This command can be used by video driver to notify RM concerning
* performance related events.
*
* videoEvent
* This parameter specifies the video event to notify.
* Legal values for this parameter include:
* NV2080_CTRL_PERF_VIDEOEVENT_STREAM_HD_START
* NV2080_CTRL_PERF_VIDEOEVENT_STREAM_HD_STOP
* These values indicate that a HD video stream (less than 4K)
* has started/stopped.
* NV2080_CTRL_PERF_VIDEOEVENT_STREAM_SD_START
* NV2080_CTRL_PERF_VIDEOEVENT_STREAM_SD_STOP
* These are now obsolete in new products as we no longer
* need to differentiate between SD and HD.
* NV2080_CTRL_PERF_VIDEOEVENT_STREAM_4K_START
* NV2080_CTRL_PERF_VIDEOEVENT_STREAM_4K_STOP
* These value indicates that a 4K video stream (3840x2160 pixels
* or higher) has started/stopped.
* NV2080_CTRL_PERF_VIDEOEVENT_OFA_START
* NV2080_CTRL_PERF_VIDEOEVENT_OFA_STOP
* These value indicates that Optical Flow Accelerator usage has
* started/stopped.
* The following flags may be or'd into the event value:
* NV2080_CTRL_PERF_VIDEOEVENT_FLAG_LINEAR_MODE
* The stream operates BSP/VP2 or MSVLD/MSPDEC communication in
* linear mode (default is ring mode).
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_STATE
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_INVALID_PARAM_STRUCT
*/
#define NV2080_CTRL_CMD_PERF_NOTIFY_VIDEOEVENT (0x2080205d) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_PERF_INTERFACE_ID << 8) | NV2080_CTRL_PERF_NOTIFY_VIDEOEVENT_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_PERF_NOTIFY_VIDEOEVENT_PARAMS_MESSAGE_ID (0x5DU)
typedef struct NV2080_CTRL_PERF_NOTIFY_VIDEOEVENT_PARAMS {
NvU32 videoEvent;
} NV2080_CTRL_PERF_NOTIFY_VIDEOEVENT_PARAMS;
#define NV2080_CTRL_PERF_VIDEOEVENT_EVENT_MASK (0x0000ffff)
#define NV2080_CTRL_PERF_VIDEOEVENT_STREAM_HD_START (0x00000001)
#define NV2080_CTRL_PERF_VIDEOEVENT_STREAM_HD_STOP (0x00000002)
#define NV2080_CTRL_PERF_VIDEOEVENT_STREAM_START NV2080_CTRL_PERF_VIDEOEVENT_STREAM_HD_START
#define NV2080_CTRL_PERF_VIDEOEVENT_STREAM_STOP NV2080_CTRL_PERF_VIDEOEVENT_STREAM_HD_STOP
#define NV2080_CTRL_PERF_VIDEOEVENT_STREAM_SD_START (0x00000003)
#define NV2080_CTRL_PERF_VIDEOEVENT_STREAM_SD_STOP (0x00000004)
#define NV2080_CTRL_PERF_VIDEOEVENT_STREAM_4K_START (0x00000005)
#define NV2080_CTRL_PERF_VIDEOEVENT_STREAM_4K_STOP (0x00000006)
#define NV2080_CTRL_PERF_VIDEOEVENT_OFA_START (0x00000007)
#define NV2080_CTRL_PERF_VIDEOEVENT_OFA_STOP (0x00000008)
#define NV2080_CTRL_PERF_VIDEOEVENT_FLAG_LINEAR_MODE (0x00010000)
/*!
* @defgroup NV2080_CTRL_PERF_PSTATES
*
* These are definitions of performance states (P-states) values.
* P0 has the maximum performance capability and consumes maximum
* power. P1 has a lower perf and power than P0, and so on.
* For NVIDIA GPUs, the following definitions are made:
* P0 - maximum 3D performance
* P1 - original P0 when active clocked
* P2-P3 - balanced 3D performance-power
* P8 - basic HD video playback
* P10 - SD video playback
* P12 - minimum idle power
* P15 - max possible P-state under current scheme (currently not used)
* Not all P-states are available on a given system.
*
* @note The @ref NV2080_CTRL_PERF_PSTATES_ID was introduced after the
* original constants were added, so not all places that intend to use
* these values are using the type. They should be updated to do so.
* @{
*/
typedef NvU32 NV2080_CTRL_PERF_PSTATES_ID;
#define NV2080_CTRL_PERF_PSTATES_UNDEFINED (0x00000000U)
#define NV2080_CTRL_PERF_PSTATES_CLEAR_FORCED (0x00000000U)
#define NV2080_CTRL_PERF_PSTATES_MIN (0x00000001U)
#define NV2080_CTRL_PERF_PSTATES_P0 (0x00000001U)
#define NV2080_CTRL_PERF_PSTATES_P1 (0x00000002U)
#define NV2080_CTRL_PERF_PSTATES_P2 (0x00000004U)
#define NV2080_CTRL_PERF_PSTATES_P3 (0x00000008U)
#define NV2080_CTRL_PERF_PSTATES_P4 (0x00000010U)
#define NV2080_CTRL_PERF_PSTATES_P5 (0x00000020U)
#define NV2080_CTRL_PERF_PSTATES_P6 (0x00000040U)
#define NV2080_CTRL_PERF_PSTATES_P7 (0x00000080U)
#define NV2080_CTRL_PERF_PSTATES_P8 (0x00000100U)
#define NV2080_CTRL_PERF_PSTATES_P9 (0x00000200U)
#define NV2080_CTRL_PERF_PSTATES_P10 (0x00000400U)
#define NV2080_CTRL_PERF_PSTATES_P11 (0x00000800U)
#define NV2080_CTRL_PERF_PSTATES_P12 (0x00001000U)
#define NV2080_CTRL_PERF_PSTATES_P13 (0x00002000U)
#define NV2080_CTRL_PERF_PSTATES_P14 (0x00004000U)
#define NV2080_CTRL_PERF_PSTATES_P15 (0x00008000U)
#define NV2080_CTRL_PERF_PSTATES_MAX NV2080_CTRL_PERF_PSTATES_P15
#define NV2080_CTRL_PERF_PSTATES_SKIP_ENTRY (0x10000U) /* finn: Evaluated from "(NV2080_CTRL_PERF_PSTATES_MAX << 1)" */
#define NV2080_CTRL_PERF_PSTATES_ALL (0xffffU) /* finn: Evaluated from "(NV2080_CTRL_PERF_PSTATES_MAX | (NV2080_CTRL_PERF_PSTATES_MAX - 1))" */
/*!@}*/
/*
* NV2080_CTRL_CMD_PERF_GET_CURRENT_PSTATE
*
* This command returns the current performance state of the GPU.
*
* currPstate
* This parameter returns the current P-state, as defined in
* NV2080_CTRL_PERF_PSTATES values.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_PARAM_STRUCT
* NV_ERR_NOT_SUPPORTED
* NV_ERR_INVALID_STATE
*/
#define NV2080_CTRL_CMD_PERF_GET_CURRENT_PSTATE (0x20802068) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_PERF_INTERFACE_ID << 8) | NV2080_CTRL_PERF_GET_CURRENT_PSTATE_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_PERF_GET_CURRENT_PSTATE_PARAMS_MESSAGE_ID (0x68U)
typedef struct NV2080_CTRL_PERF_GET_CURRENT_PSTATE_PARAMS {
NvU32 currPstate;
} NV2080_CTRL_PERF_GET_CURRENT_PSTATE_PARAMS;
/* _ctrl2080perf_h_ */

5
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080pmu.h
View File

@@ -1,4 +1,3 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
@@ -24,6 +23,8 @@
#pragma once
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl2080/ctrl2080pmu.finn
@@ -31,8 +32,6 @@
#include "nvtypes.h"
/*!
* @file
*

111
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080spdm.h
View File

@@ -38,93 +38,45 @@
* @brief SPDM Command Types
*
*/
#define RM_GSP_SPDM_CMD_ID_CC_INIT (0x1)
#define RM_GSP_SPDM_CMD_ID_CC_DEINIT (0x2)
#define RM_GSP_SPDM_CMD_ID_CC_CTRL (0x3)
#define RM_GSP_SPDM_CMD_ID_CC_INIT_RM_DATA (0x4)
#define RM_GSP_SPDM_CMD_ID_CC_INIT (0x1)
#define RM_GSP_SPDM_CMD_ID_CC_DEINIT (0x2)
#define RM_GSP_SPDM_CMD_ID_CC_CTRL (0x3)
#define RM_GSP_SPDM_CMD_ID_CC_INIT_RM_DATA (0x4)
#define RM_GSP_SPDM_CMD_ID_CC_HEARTBEAT_CTRL (0x5)
#define RM_GSP_SPDM_CMD_ID_INVALID_COMMAND (0xFF)
#define RM_GSP_SPDM_CMD_ID_INVALID_COMMAND (0xFF)
#define RSVD7_SIZE 16
#define RSVD7_SIZE 16
#define RSVD8_SIZE 2
/*!
* Guest RM must send RM_GSP_SPDM_CMD_ID_CC_INIT to GSP-RM before SPDM session start
*/
typedef struct RM_GSP_SPDM_CC_INIT_CTX {
NvU32 guestId; // To indicate CC guest Id, VM0, VM1 ... etc
NvU64_ALIGN32 dmaAddr; // The address RM allocate in SYS memory or FB memory.
NvU32 rmBufferSizeInByte; // The memort size allocated by RM(exclude NV_SPDM_DESC_HEADER)
} RM_GSP_SPDM_CC_INIT_CTX;
typedef struct RM_GSP_SPDM_CC_INIT_CTX *PRM_GSP_SPDM_CC_INIT_CTX;
#define RSVD8_SIZE 2
/*!
* Guest RM provides INIT context
*/
typedef struct RM_GSP_SPDM_CMD_CC_INIT {
// Command must be first as this struct is the part of union
NvU8 cmdType;
RM_GSP_SPDM_CC_INIT_CTX ccInitCtx;
NvU8 cmdType;
} RM_GSP_SPDM_CMD_CC_INIT;
typedef struct RM_GSP_SPDM_CMD_CC_INIT *PRM_GSP_SPDM_CMD_CC_INIT;
#define DEINIT_FLAGS_FORCE_CLEAR (0x1)
/*!
* Guest RM must send RM_GSP_SPDM_CMD_ID_CC_DEINIT to GSP-RM to end a session
*/
typedef struct RM_GSP_SPDM_CC_DEINIT_CTX {
NvU32 guestId; // To indicate CC guest Id, VM0, VM1 ... etc
NvU32 endpointId; // To indicate SPDM endpoint Id
NvU32 flags;
} RM_GSP_SPDM_CC_DEINIT_CTX;
typedef struct RM_GSP_SPDM_CC_DEINIT_CTX *PRM_GSP_SPDM_CC_DEINIT_CTX;
/*!
* Guest RM provides INIT context
*/
typedef struct RM_GSP_SPDM_CMD_CC_DEINIT {
// Command must be first as this struct is the part of union
NvU8 cmdType;
RM_GSP_SPDM_CC_DEINIT_CTX ccDeinitCtx;
NvU8 cmdType;
} RM_GSP_SPDM_CMD_CC_DEINIT;
typedef struct RM_GSP_SPDM_CMD_CC_DEINIT *PRM_GSP_SPDM_CMD_CC_DEINIT;
/*!
* RM provides SPDM message request context, include header + corresponding payload
*/
typedef struct RM_GSP_SPDM_CC_CTRL_CTX {
NvU32 version;
NvU32 guestId; // To indicate CC client Id, VM0, VM1 ... etc
NvU32 endpointId; // To indicate SPDM endpoint Id
} RM_GSP_SPDM_CC_CTRL_CTX;
typedef struct RM_GSP_SPDM_CC_CTRL_CTX *PRM_GSP_SPDM_CC_CTRL_CTX;
/*!
* RM provides the SPDM request info to GSP
*/
typedef struct RM_GSP_SPDM_CMD_CC_CTRL {
// Command must be first as this struct is the part of union
NvU8 cmdType;
RM_GSP_SPDM_CC_CTRL_CTX ccCtrlCtx;
NvU8 cmdType;
} RM_GSP_SPDM_CMD_CC_CTRL;
typedef struct RM_GSP_SPDM_CMD_CC_CTRL *PRM_GSP_SPDM_CMD_CC_CTRL;
@@ -136,9 +88,9 @@ typedef struct RM_GSP_SPDM_CMD_CC_INIT_RM_DATA {
NvU32 rsvd1;
char rsvd2[4];
char rsvd2[9];
char rsvd3[2];
char rsvd3[5];
char rsvd4[5];
@@ -152,6 +104,15 @@ typedef struct RM_GSP_SPDM_CMD_CC_INIT_RM_DATA {
} RM_GSP_SPDM_CMD_CC_INIT_RM_DATA;
typedef struct RM_GSP_SPDM_CMD_CC_INIT_RM_DATA *PRM_GSP_SPDM_CMD_CC_INIT_RM_DATA;
typedef struct RM_GSP_SPDM_CMD_CC_HEARTBEAT_CTRL {
// Command must be first as this struct is the part of union
NvU8 cmdType;
// Whether to enable or disable heartbeats
NvBool bEnable;
} RM_GSP_SPDM_CMD_CC_HEARTBEAT_CTRL;
typedef struct RM_GSP_SPDM_CMD_CC_HEARTBEAT_CTRL *PRM_GSP_SPDM_CMD_CC_HEARTBEAT_CTRL;
/*!
* NOTE : Do not include structure members that have alignment requirement >= 8 to avoid alignment directives
@@ -164,11 +125,12 @@ typedef struct RM_GSP_SPDM_CMD_CC_INIT_RM_DATA *PRM_GSP_SPDM_CMD_CC_INIT_RM_DATA
* A union of all SPDM Commands.
*/
typedef union RM_GSP_SPDM_CMD {
NvU8 cmdType;
RM_GSP_SPDM_CMD_CC_INIT ccInit;
RM_GSP_SPDM_CMD_CC_DEINIT ccDeinit;
RM_GSP_SPDM_CMD_CC_CTRL ccCtrl;
RM_GSP_SPDM_CMD_CC_INIT_RM_DATA rmDataInitCmd;
NvU8 cmdType;
RM_GSP_SPDM_CMD_CC_INIT ccInit;
RM_GSP_SPDM_CMD_CC_DEINIT ccDeinit;
RM_GSP_SPDM_CMD_CC_CTRL ccCtrl;
RM_GSP_SPDM_CMD_CC_INIT_RM_DATA rmDataInitCmd;
RM_GSP_SPDM_CMD_CC_HEARTBEAT_CTRL ccHeartbeatCtrl;
} RM_GSP_SPDM_CMD;
typedef union RM_GSP_SPDM_CMD *PRM_GSP_SPDM_CMD;
@@ -182,17 +144,18 @@ typedef union RM_GSP_SPDM_CMD *PRM_GSP_SPDM_CMD;
/*!
* Returns the status for program CE keys to RM
*/
#define RM_GSP_SPDM_MSG_ID_CC_INIT (0x1)
#define RM_GSP_SPDM_MSG_ID_CC_DEINIT (0x2)
#define RM_GSP_SPDM_MSG_ID_CC_CTRL (0x3)
#define RM_GSP_SPDM_MSG_ID_CC_INIT_RM_DATA (0x4)
#define RM_GSP_SPDM_MSG_ID_CC_INIT (0x1)
#define RM_GSP_SPDM_MSG_ID_CC_DEINIT (0x2)
#define RM_GSP_SPDM_MSG_ID_CC_CTRL (0x3)
#define RM_GSP_SPDM_MSG_ID_CC_INIT_RM_DATA (0x4)
#define RM_GSP_SPDM_MSG_ID_CC_HEARTBEAT_CTRL (0x5)
/*!
* Returns the Error Status for Invalid Command
*/
#define RM_GSP_SPDM_MSG_ID_INVALID_COMMAND (0xFF)
#define RM_GSP_SPDM_MSG_ID_INVALID_COMMAND (0xFF)
/*!
* NOTE : Do not include structure members that have alignment requirement >= 8 to avoid alignment directives
@@ -207,12 +170,6 @@ typedef union RM_GSP_SPDM_CMD *PRM_GSP_SPDM_CMD;
typedef struct RM_GSP_SPDM_MSG {
NvU8 msgType;
NvU32 version;
NvU32 guestId;
NvU32 endpointId;
// status returned from GSP message infrastructure.
NvU32 status;

26
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080vgpumgrinternal.h
View File

@@ -61,7 +61,7 @@
#define NV2080_CTRL_MAX_VMMU_SEGMENTS 384
/* Must match NV2080_ENGINE_TYPE_LAST from cl2080.h */
#define NV2080_GPU_MAX_ENGINES 0x3f
#define NV2080_GPU_MAX_ENGINES 0x40
#define NV2080_CTRL_VGPU_MGR_INTERNAL_BOOTLOAD_GSP_VGPU_PLUGIN_TASK_PARAMS_MESSAGE_ID (0x1U)
@@ -412,4 +412,28 @@ typedef struct NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_MGR_CONFIG_PARAMS {
NvBool bSupportHeterogeneousTimeSlicedVgpuTypes;
} NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_MGR_CONFIG_PARAMS;
/*
* NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_GET_PGPU_MIGRATION_SUPPORT
*
* Reroutes NVA084_CTRL_CMD_KERNEL_HOST_VGPU_DEVICE_FREE_STATES to GSP RM to enable
* kernel clients to utilize NVA082_CTRL_CMD_HOST_VGPU_DEVICE_FREE_STATES.
*
* gfid [IN]
* This parameter specifies the gfid of vGPU assigned to VM.
* flags [IN]
* Specifies what component of HostVgpuDevice to free.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_STATE
*/
#define NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_FREE_STATES (0x2080400c) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_VGPU_MGR_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_VGPU_MGR_INTERNAL_FREE_STATES_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_VGPU_MGR_INTERNAL_FREE_STATES_PARAMS_MESSAGE_ID (0xCU)
typedef struct NV2080_CTRL_VGPU_MGR_INTERNAL_FREE_STATES_PARAMS {
NvU32 gfid;
NvU32 flags;
} NV2080_CTRL_VGPU_MGR_INTERNAL_FREE_STATES_PARAMS;
/* _ctrl2080vgpumgrinternal_h_ */

4
src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208fmmu.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2018-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2018-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -126,4 +126,6 @@ typedef struct NV208F_CTRL_MMU_GET_NUM_HSHUBMMUS_PARAMS {
NvU32 numHshubmmus;
} NV208F_CTRL_MMU_GET_NUM_HSHUBMMUS_PARAMS;
/* _ctrl208fmmu_h_ */

21
src/common/sdk/nvidia/inc/ctrl/ctrl506f.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2001-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2001-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -93,4 +93,21 @@
typedef struct NV506F_CTRL_CMD_RESET_ISOLATED_CHANNEL_PARAMS {
NvU32 exceptType;
NvU32 engineID;
} NV506F_CTRL_CMD_RESET_ISOLATED_CHANNEL_PARAMS;/* _ctrl506f.h_ */
} NV506F_CTRL_CMD_RESET_ISOLATED_CHANNEL_PARAMS;
/*
* NV506F_CTRL_CMD_INTERNAL_RESET_ISOLATED_CHANNEL
*
* This command is an internal command sent from Kernel RM to Physical RM
* to perform the channel reset operations in hardware on an isolated channel
*
* Please see description of NV506F_CTRL_CMD_RESET_ISOLATED_CHANNEL for more information.
*
*/
#define NV506F_CTRL_CMD_INTERNAL_RESET_ISOLATED_CHANNEL (0x506f0106) /* finn: Evaluated from "(FINN_NV50_CHANNEL_GPFIFO_GPFIFO_INTERFACE_ID << 8) | NV506F_CTRL_CMD_INTERNAL_RESET_ISOLATED_CHANNEL_PARAMS_MESSAGE_ID" */
#define NV506F_CTRL_CMD_INTERNAL_RESET_ISOLATED_CHANNEL_PARAMS_MESSAGE_ID (0x6U)
typedef NV506F_CTRL_CMD_RESET_ISOLATED_CHANNEL_PARAMS NV506F_CTRL_CMD_INTERNAL_RESET_ISOLATED_CHANNEL_PARAMS;
/* _ctrl506f.h_ */

2
src/common/sdk/nvidia/inc/ctrl/ctrl5070/ctrl5070verif.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2001-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2001-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a

12
src/common/sdk/nvidia/inc/ctrl/ctrl906f.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2007-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2007-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -119,6 +119,9 @@ typedef struct NV906F_CTRL_GET_CLASS_ENGINEID_PARAMS {
* resetReason
* Specifies reason to reset a channel.
*
* bIsRcPending
* Specifies if an RC is pending on the channel
*
* Possible status values returned are:
* NV_OK
*/
@@ -138,9 +141,10 @@ typedef struct NV906F_CTRL_GET_CLASS_ENGINEID_PARAMS {
#define NV906F_CTRL_CMD_RESET_CHANNEL_PARAMS_MESSAGE_ID (0x2U)
typedef struct NV906F_CTRL_CMD_RESET_CHANNEL_PARAMS {
NvU32 engineID;
NvU32 subdeviceInstance;
NvU32 resetReason;
NvU32 engineID;
NvU32 subdeviceInstance;
NvU32 resetReason;
NvBool bIsRcPending;
} NV906F_CTRL_CMD_RESET_CHANNEL_PARAMS;
/*

297
src/common/sdk/nvidia/inc/ctrl/ctrla080.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2012-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2012-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -21,7 +21,6 @@
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
#include <nvtypes.h>
@@ -31,6 +30,29 @@
// Source file: ctrl/ctrla080.finn
//
#include "ctrl/ctrlxxxx.h"
/* KEPLER_DEVICE_VGPU control commands and parameters */
#define NVA080_CTRL_CMD(cat,idx) NVXXXX_CTRL_CMD(0xA080, NVA080_CTRL_##cat, idx)
/* Command categories (6bits) */
#define NVA080_CTRL_RESERVED (0x00)
#define NVA080_CTRL_VGPU_DISPLAY (0x01)
#define NVA080_CTRL_VGPU_MEMORY (0x02)
#define NVA080_CTRL_VGPU_OTHERS (0x03)
/*
* NVA080_CTRL_CMD_NULL
*
* This command does nothing.
* This command does not take any parameters.
*
* Possible status values returned are:
* NV_OK
*/
#define NVA080_CTRL_CMD_NULL (0xa0800000) /* finn: Evaluated from "(FINN_KEPLER_DEVICE_VGPU_RESERVED_INTERFACE_ID << 8) | 0x0" */
@@ -181,142 +203,7 @@ typedef struct NVA080_CTRL_VGPU_DISPLAY_CLEANUP_SURFACE_PARAMS {
NvU32 blankingEnabled;
} NVA080_CTRL_VGPU_DISPLAY_CLEANUP_SURFACE_PARAMS;
/*
* NVA080_CTRL_CMD_VGPU_DISPLAY_GET_POINTER_ADDRESS
*
* This command returns CPU virtual address of the mouse pointer mapping for VGPU.
* The address returned by this command is the pointer address for the head 0.
* VGPU_POINTER_OFFSET_HEAD(i) should be added to this address to get the address of head i.
* VGPU mouse pointer is a 32 bit value, X location of the mouse pointer is stored in
* 15:0 and Y location is stored in 31:16 bits. X location value of the mouse pointer is
* negative if bit 15 is set. Similarly, Y location value is negative if bit 31 is set.
*
* Parameters:
* pPointerAddress
* CPU virtual address of the mouse pointer mapping for VGPU
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
* NVOS_STATUS_NOT_SUPPORTED
*/
#define NVA080_CTRL_CMD_VGPU_DISPLAY_GET_POINTER_ADDRESS (0xa0800105) /* finn: Evaluated from "(FINN_KEPLER_DEVICE_VGPU_VGPU_DISPLAY_INTERFACE_ID << 8) | NVA080_CTRL_VGPU_DISPLAY_GET_POINTER_ADDRESS_PARAMS_MESSAGE_ID" */
#define NVA080_CTRL_VGPU_DISPLAY_GET_POINTER_ADDRESS_PARAMS_MESSAGE_ID (0x5U)
typedef struct NVA080_CTRL_VGPU_DISPLAY_GET_POINTER_ADDRESS_PARAMS {
NV_DECLARE_ALIGNED(NvP64 pPointerAddress, 8);
} NVA080_CTRL_VGPU_DISPLAY_GET_POINTER_ADDRESS_PARAMS;
#define VGPU_POINTER_OFFSET_HEAD0_VALUE 0x00000000
#define VGPU_POINTER_OFFSET_HEAD0_FLAG 0x00000004
#define VGPU_POINTER_OFFSET_HEAD1_VALUE 0x00000008
#define VGPU_POINTER_OFFSET_HEAD1_FLAG 0x0000000c
#define VGPU_POINTER_OFFSET_HEAD2_VALUE 0x00000010
#define VGPU_POINTER_OFFSET_HEAD2_FLAG 0x00000014
#define VGPU_POINTER_OFFSET_HEAD3_VALUE 0x00000018
#define VGPU_POINTER_OFFSET_HEAD3_FLAG 0x0000001c
#define VGPU_POINTER_OFFSET_HEAD_VALUE(i) (i * 8)
#define VGPU_POINTER_OFFSET_HEAD_FLAG(i) (4 + i * 8)
#define VGPU_POINTER_OFFSET_HEAD_SIZE 4
/*
* NVA080_CTRL_CMD_GET_MAPPABLE_VIDEO_SIZE
*
* This command returns mappable video size to be used by each VM.
*
* Parameters:
* mappableVideoSize
* This parameter returns mappable video size in bytes.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
* NVOS_STATUS_NOT_SUPPORTED
*/
#define NV_VGPU_POINTER_X_LOCATION 15:0
#define NV_VGPU_POINTER_Y_LOCATION 31:16
#define NVA080_CTRL_CMD_GET_MAPPABLE_VIDEO_SIZE (0xa0800201) /* finn: Evaluated from "(FINN_KEPLER_DEVICE_VGPU_VGPU_MEMORY_INTERFACE_ID << 8) | NVA080_CTRL_GET_MAPPABLE_VIDEO_SIZE_PARAMS_MESSAGE_ID" */
#define NVA080_CTRL_GET_MAPPABLE_VIDEO_SIZE_PARAMS_MESSAGE_ID (0x1U)
typedef struct NVA080_CTRL_GET_MAPPABLE_VIDEO_SIZE_PARAMS {
NV_DECLARE_ALIGNED(NvU64 mappableVideoSize, 8);
} NVA080_CTRL_GET_MAPPABLE_VIDEO_SIZE_PARAMS;
/*
* NVA080_CTRL_CMD_MAP_SEMA_MEM
*
* This command returns GPU VA for the channel with 'hCtxDma' handle
* where per VM semaphore memory is mapped which is used for tracking
* non-stall interrupt of each VM.
*
* Parameters:
* hClient [in]
* This parameter specifies the handle to the NV01_ROOT object of
* the client. This object should be the parent of the object
* specified by hDevice.
* hDevice [in]
* This parameter specifies the handle of the NV01_DEVICE object
* representing the desired GPU.
* hMemory [in]
* This parameter specifies the handle for semaphore memory
* hCtxDma [in]
* This parameter specifies the handle of the NV01_CONTEXT_DMA
* object through which bufferId is written in semaphore memory for
* non-stall interrupt tracking.
* semaAddress [out]
* This parameter returns the GPU virtual address of the semaphore
* memory.
*
* Possible status values returned are:
* NV_OK
* NVOS_STATUS_INVALID_DATA
* NV_ERR_INVALID_CLIENT
* NV_ERR_INVALID_OBJECT_HANDLE
*
*/
#define NVA080_CTRL_CMD_MAP_SEMA_MEM (0xa0800202) /* finn: Evaluated from "(FINN_KEPLER_DEVICE_VGPU_VGPU_MEMORY_INTERFACE_ID << 8) | NVA080_CTRL_MAP_SEMA_MEM_PARAMS_MESSAGE_ID" */
typedef struct NVA080_CTRL_SEMA_MEM_PARAMS {
NvHandle hClient;
NvHandle hDevice;
NvHandle hMemory;
NvHandle hCtxDma;
NV_DECLARE_ALIGNED(NvU64 semaAddress, 8);
} NVA080_CTRL_SEMA_MEM_PARAMS;
#define NVA080_CTRL_MAP_SEMA_MEM_PARAMS_MESSAGE_ID (0x2U)
typedef NVA080_CTRL_SEMA_MEM_PARAMS NVA080_CTRL_MAP_SEMA_MEM_PARAMS;
/*
* NVA080_CTRL_CMD_UNMAP_SEMA_MEM
*
* This command unmaps per VM semaphore memory from GPU VA space, mapped by
* NVA080_CTRL_CMD_MAP_SEMA_MEM command.
*
* Parameters:
* Same as NVA080_CTRL_MAP_SEMA_MEM_PARAMS, except semaAddress is input
* parameter here.
*
* Possible status values returned are:
* NV_OK
* NVOS_STATUS_INVALID_DATA
* NV_ERR_INVALID_CLIENT
* NV_ERR_INVALID_OBJECT_HANDLE
*
*/
#define NVA080_CTRL_CMD_UNMAP_SEMA_MEM (0xa0800203) /* finn: Evaluated from "(FINN_KEPLER_DEVICE_VGPU_VGPU_MEMORY_INTERFACE_ID << 8) | NVA080_CTRL_UNMAP_SEMA_MEM_PARAMS_MESSAGE_ID" */
#define NVA080_CTRL_UNMAP_SEMA_MEM_PARAMS_MESSAGE_ID (0x3U)
typedef NVA080_CTRL_SEMA_MEM_PARAMS NVA080_CTRL_UNMAP_SEMA_MEM_PARAMS;
/*!
* NVA080_CTRL_CMD_SET_FB_USAGE
@@ -338,140 +225,6 @@ typedef struct NVA080_CTRL_SET_FB_USAGE_PARAMS {
NV_DECLARE_ALIGNED(NvU64 fbUsed, 8);
} NVA080_CTRL_SET_FB_USAGE_PARAMS;
/*!
* NVA080_CTRL_CMD_MAP_PER_ENGINE_SEMA_MEM
*
* This command allocates the per engine vGPU semaphore memory and map it to
* GPU/CPU VA.
*
* Calculate engine's semaphore GPU VA =
* semaAddress + semaStride * NV2080_ENGINE_TYPE_ of that engine
*
* Parameters:
* hClient [in]
* This parameter specifies the handle to the NV01_ROOT object of
* the client. This object should be the parent of the object
* specified by hDevice.
* hDevice [in]
* This parameter specifies the handle of the NV01_DEVICE object
* representing the desired GPU.
* hMemory [in]
* This parameter specifies the handle for semaphore memory
* hCtxDma [in]
* This parameter specifies the handle of the NV01_CONTEXT_DMA
* object through which bufferId is written in semaphore memory for
* non-stall interrupt tracking.
* semaAddress [out]
* This parameter returns the GPU VA of the per engine semaphore memory.
* semaStride [out]
* This parameter specifies the stride of each engine's semaphore offset within this memory.
*
* Possible status values returned are:
* NV_OK
*/
#define NVA080_CTRL_CMD_MAP_PER_ENGINE_SEMA_MEM (0xa0800205) /* finn: Evaluated from "(FINN_KEPLER_DEVICE_VGPU_VGPU_MEMORY_INTERFACE_ID << 8) | NVA080_CTRL_MAP_PER_ENGINE_SEMA_MEM_PARAMS_MESSAGE_ID" */
typedef struct NVA080_CTRL_PER_ENGINE_SEMA_MEM_PARAMS {
NvU32 hClient;
NvU32 hDevice;
NvHandle hMemory;
NvU32 hCtxDma;
NV_DECLARE_ALIGNED(NvU64 semaAddress, 8);
NvU32 semaStride;
} NVA080_CTRL_PER_ENGINE_SEMA_MEM_PARAMS;
#define NVA080_CTRL_MAP_PER_ENGINE_SEMA_MEM_PARAMS_MESSAGE_ID (0x5U)
typedef NVA080_CTRL_PER_ENGINE_SEMA_MEM_PARAMS NVA080_CTRL_MAP_PER_ENGINE_SEMA_MEM_PARAMS;
/*!
* NVA080_CTRL_CMD_UNMAP_PER_ENGINE_SEMA_MEM
*
* This command unmaps and frees the per engine vGPU semaphore memory.
*
* Parameters:
* Same as NVA080_CTRL_MAP_PER_ENGINE_SEMA_MEM_PARAMS, except semaAddress is input
* parameter here.
*
* Possible status values returned are:
* NV_OK
*/
#define NVA080_CTRL_CMD_UNMAP_PER_ENGINE_SEMA_MEM (0xa0800206) /* finn: Evaluated from "(FINN_KEPLER_DEVICE_VGPU_VGPU_MEMORY_INTERFACE_ID << 8) | NVA080_CTRL_UNMAP_PER_ENGINE_SEMA_MEM_PARAMS_MESSAGE_ID" */
#define NVA080_CTRL_UNMAP_PER_ENGINE_SEMA_MEM_PARAMS_MESSAGE_ID (0x6U)
typedef NVA080_CTRL_PER_ENGINE_SEMA_MEM_PARAMS NVA080_CTRL_UNMAP_PER_ENGINE_SEMA_MEM_PARAMS;
/*
* NVA080_CTRL_CMD_UPDATE_SYSMEM_BITMAP
*
* This command provides the guest RM with PFN information, so that it can
* update the shared memory with the plugin, which keeps track of guest sysmem.
*
* Parameters:
* destPhysAddr
* Start address of the segment to be tracked
*
* pageCount
* Number of pages in the segment
*
* pageSize
* Size of pages in the segment
*
* isValid:
* TRUE : Set bits corresponding to PFNs in bitmap and increase segment refcount
* FALSE: Decrease segment refcount and then unset bits if refcount is 0
*
* pfnList
* List of PFNs in the segment
*
* flags
* FLAGS_DST_PHYS_ADDR_BAR1_OFFSET
* Flag set to TRUE if pteMem is CPU VA pointing to BAR1 and
* dstPhysAddr contains BAR1 offset.
*
* Possible status values returned are:
* NVOS_STATUS_SUCCESS
*/
#define NVA080_CTRL_CMD_UPDATE_SYSMEM_BITMAP (0xa0800207) /* finn: Evaluated from "(FINN_KEPLER_DEVICE_VGPU_VGPU_MEMORY_INTERFACE_ID << 8) | NVA080_CTRL_UPDATE_SYSMEM_BITMAP_PARAMS_MESSAGE_ID" */
#define NVA080_CTRL_UPDATE_SYSMEM_BITMAP_PARAMS_FLAGS_DST_PHYS_ADDR_BAR1_OFFSET 0:0
#define NVA080_CTRL_UPDATE_SYSMEM_BITMAP_PARAMS_FLAGS_DST_PHYS_ADDR_BAR1_OFFSET_FALSE (0x00000000)
#define NVA080_CTRL_UPDATE_SYSMEM_BITMAP_PARAMS_FLAGS_DST_PHYS_ADDR_BAR1_OFFSET_TRUE (0x00000001)
#define NVA080_CTRL_UPDATE_SYSMEM_BITMAP_PARAMS_MESSAGE_ID (0x7U)
typedef struct NVA080_CTRL_UPDATE_SYSMEM_BITMAP_PARAMS {
NV_DECLARE_ALIGNED(NvU64 destPhysAddr, 8);
NvU32 pageCount;
NvU32 pageSize;
NvBool isValid;
NV_DECLARE_ALIGNED(NvP64 pfnList, 8);
NvU32 flags;
} NVA080_CTRL_UPDATE_SYSMEM_BITMAP_PARAMS;
/*
* Blit semaphore offset location
*/
#define VGPU_BLIT_RESTORE_SEMA_MEM_OFFSET 0x200
#define VGPU_BLIT_RESTORE_SEMA_MEM_ADDR(addr) (((NvU64)addr) + VGPU_BLIT_RESTORE_SEMA_MEM_OFFSET)
#define VGPU_BLIT_SEMA_MEM_OFFSET 0x400
#define VGPU_BLIT_SEMA_MEM_ADDR(addr) (((NvU64)addr) + VGPU_BLIT_SEMA_MEM_OFFSET)
#define VGPU_FBMEMCE_PUSH_SEMA_MEM_OFFSET 0x800
#define VGPU_FBMEMCE_PUSH_SEMA_MEM_ADDR(addr) (((NvU64)addr) + VGPU_FBMEMCE_PUSH_SEMA_MEM_OFFSET)
#define VGPU_FBMEMCE_SEMA_MEM_OFFSET 0x810
#define VGPU_FBMEMCE_SEMA_MEM_ADDR(addr) (((NvU64)addr) + VGPU_FBMEMCE_SEMA_MEM_OFFSET)
#define VGPU_FBMEMCE_PIPELINED_SEMA_MEM_LOWER_OFFSET 0x820
#define VGPU_FBMEMCE_PIPELINED_SEMA_MEM_LOWER_ADDR(addr) (((NvU64)addr) + VGPU_FBMEMCE_PIPELINED_SEMA_MEM_LOWER_OFFSET)
#define VGPU_FBMEMCE_PIPELINED_SEMA_MEM_UPPER_OFFSET 0x824
/*
* NVA080_CTRL_CMD_VGPU_GET_CONFIG
@@ -571,7 +324,7 @@ typedef struct NVA080_CTRL_UPDATE_SYSMEM_BITMAP_PARAMS {
* NV_ERR_INVALID_PARAM_STRUCT
* NV_ERR_INVALID_ARGUMENT
*/
#define VGPU_FBMEMCE_PIPELINED_SEMA_MEM_UPPER_ADDR(addr) (((NvU64)addr) + VGPU_FBMEMCE_PIPELINED_SEMA_MEM_UPPER_OFFSET)
#define NVA080_CTRL_CMD_VGPU_GET_CONFIG (0xa0800301) /* finn: Evaluated from "(FINN_KEPLER_DEVICE_VGPU_VGPU_OTHERS_INTERFACE_ID << 8) | NVA080_CTRL_VGPU_GET_CONFIG_PARAMS_MESSAGE_ID" */
#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_SW_VSYNC_ENABLED 0:0

140
src/common/sdk/nvidia/inc/ctrl/ctrla081.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2014-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2014-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -51,6 +51,7 @@
#define NVA081_PCI_CONFIG_SPACE_SIZE 0x100
#define NVA081_PGPU_METADATA_STRING_SIZE 256
#define NVA081_EXTRA_PARAMETERS_SIZE 1024
#define NVA081_PLACEMENT_ID_INVALID 0xFFFFU
/*
* NVA081_CTRL_CMD_VGPU_CONFIG_SET_INFO
@@ -118,6 +119,9 @@ typedef struct NVA081_CTRL_VGPU_INFO {
NvU32 exclusiveSize;
// used only by NVML
NvU32 gpuInstanceProfileId;
NvU32 placementSize;
NvU32 placementCount;
NvU32 placementIds[NVA081_MAX_VGPU_PER_PGPU];
} NVA081_CTRL_VGPU_INFO;
/*
@@ -231,6 +235,9 @@ typedef struct NVA081_GUEST_VM_INFO {
* This parameter specifies whether driver is loaded on this particular vGPU.
* swizzId [OUT]
* This param specifies the GPU Instance ID or Swizz ID
* placementId [OUT]
* This param specifies the placement ID of heterogeneous timesliced vGPU instance.
* Otherwise it is NVA081_PLACEMENT_ID_INVALID.
*
*/
typedef struct NVA081_HOST_VGPU_DEVICE {
@@ -244,6 +251,7 @@ typedef struct NVA081_HOST_VGPU_DEVICE {
NvU32 eccState;
NvBool bDriverLoaded;
NvU32 swizzId;
NvU32 placementId;
} NVA081_HOST_VGPU_DEVICE;
/* ECC state values */
@@ -463,11 +471,11 @@ typedef struct NVA081_CTRL_VGPU_CONFIG_NOTIFY_START_PARAMS {
} NVA081_CTRL_VGPU_CONFIG_NOTIFY_START_PARAMS;
/*
* NVA081_CTRL_CMD_VGPU_CONFIG_MDEV_REGISTER
* NVA081_CTRL_CMD_VGPU_CONFIG_UPDATE_PGPU_INFO
*
* This command register the GPU to Linux kernel's mdev module for vGPU on KVM.
*/
#define NVA081_CTRL_CMD_VGPU_CONFIG_MDEV_REGISTER (0xa0810109) /* finn: Evaluated from "(FINN_NVA081_VGPU_CONFIG_VGPU_CONFIG_INTERFACE_ID << 8) | 0x9" */
#define NVA081_CTRL_CMD_VGPU_CONFIG_UPDATE_PGPU_INFO (0xa0810109) /* finn: Evaluated from "(FINN_NVA081_VGPU_CONFIG_VGPU_CONFIG_INTERFACE_ID << 8) | 0x9" */
/*
* NVA081_CTRL_CMD_VGPU_CONFIG_SET_VGPU_INSTANCE_ENCODER_CAPACITY
@@ -747,4 +755,130 @@ typedef struct NVA081_CTRL_VGPU_CONFIG_VALIDATE_SWIZZID_PARAMS {
NvU32 swizzId;
} NVA081_CTRL_VGPU_CONFIG_VALIDATE_SWIZZID_PARAMS;
/*
* NVA081_CTRL_CMD_VGPU_CONFIG_UPDATE_HETEROGENEOUS_INFO
*
* This command is used to get a placement Id from RM for timesliced
* heterogeneous vGPUs.
*
* isHeterogeneousEnabled [OUT]
* This param specific whether timesliced heterogeneous vGPU is enabled
* for different FB sized profiles.
*
* vgpuTypeId [IN]
* This param specifies the Type ID for VGPU profile
*
* placementId [IN / OUT]
* This param specifies the input placement ID provided by hypervisor
* or output placement ID reserved by RM for vGPU type ID.
*
* TODO : This same RmCtrl will be also be used to provide GSP heap offset
* to CPU plugin when vGPU-GSP is enabled.
* (As guest fb and gsp heap is allocated before A084 object)
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_REQUEST
* NV_ERR_INVALID_STATE
* NV_ERR_INVALID_ARGUMENT
*/
#define NVA081_CTRL_CMD_VGPU_CONFIG_UPDATE_HETEROGENEOUS_INFO (0xa081011b) /* finn: Evaluated from "(FINN_NVA081_VGPU_CONFIG_VGPU_CONFIG_INTERFACE_ID << 8) | NVA081_CTRL_VGPU_CONFIG_UPDATE_HETEROGENEOUS_INFO_PARAMS_MESSAGE_ID" */
#define NVA081_CTRL_VGPU_CONFIG_UPDATE_HETEROGENEOUS_INFO_PARAMS_MESSAGE_ID (0x1bU)
typedef struct NVA081_CTRL_VGPU_CONFIG_UPDATE_HETEROGENEOUS_INFO_PARAMS {
NvBool isHeterogeneousEnabled;
NvU16 placementId;
NvU32 vgpuTypeId;
NV_DECLARE_ALIGNED(NvU64 guestFbLength, 8);
NV_DECLARE_ALIGNED(NvU64 guestFbOffset, 8);
NV_DECLARE_ALIGNED(NvU64 gspHeapOffset, 8);
} NVA081_CTRL_VGPU_CONFIG_UPDATE_HETEROGENEOUS_INFO_PARAMS;
/*
* NVA081_CTRL_CMD_VGPU_CONFIG_GET_CREATABLE_PLACEMENTS
*
* This command fetches count and list of creatable vGPU placements
*
* Parameters:
*
* vgpuTypeId [IN]
* The client provided vGPU type ID
*
* placementSize [OUT]
* The number of placement slots occupied by the vGPU type
*
* count [OUT]
* This parameter returns the number of placements supported for the vGPU
*
* placementIds [OUT]
* Array of creatable placement IDs
*
* Possible status values returned are:
* NV_OK
* NV_ERR_OBJECT_NOT_FOUND
* NV_ERR_NOT_SUPPORTED
*/
#define NVA081_CTRL_CMD_VGPU_CONFIG_GET_CREATABLE_PLACEMENTS (0xa081011c) /* finn: Evaluated from "(FINN_NVA081_VGPU_CONFIG_VGPU_CONFIG_INTERFACE_ID << 8) | NVA081_CTRL_VGPU_CONFIG_GET_CREATABLE_PLACEMENTS_PARAMS_MESSAGE_ID" */
#define NVA081_CTRL_VGPU_CONFIG_GET_CREATABLE_PLACEMENTS_PARAMS_MESSAGE_ID (0x1cU)
typedef struct NVA081_CTRL_VGPU_CONFIG_GET_CREATABLE_PLACEMENTS_PARAMS {
NvU32 vgpuTypeId;
NvU32 placementSize;
NvU32 count;
NvU32 placementIds[NVA081_MAX_VGPU_PER_PGPU];
} NVA081_CTRL_VGPU_CONFIG_GET_CREATABLE_PLACEMENTS_PARAMS;
/*
* NVA081_CTRL_CMD_PGPU_GET_VGPU_STREAMING_CAPABILITY
*
* This command is used to get streaming capability for the physical GPU.
*
* streamingCapability [OUT]
* This param specifies whether vGPU profiles on the GPU supports migration data streaming
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_REQUEST
* NV_ERR_INVALID_ARGUMENT
*/
#define NVA081_CTRL_CMD_PGPU_GET_VGPU_STREAMING_CAPABILITY (0xa081011d) /* finn: Evaluated from "(FINN_NVA081_VGPU_CONFIG_VGPU_CONFIG_INTERFACE_ID << 8) | NVA081_CTRL_PGPU_GET_VGPU_STREAMING_CAPABILITY_PARAMS_MESSAGE_ID" */
#define NVA081_CTRL_PGPU_GET_VGPU_STREAMING_CAPABILITY_PARAMS_MESSAGE_ID (0x1dU)
typedef struct NVA081_CTRL_PGPU_GET_VGPU_STREAMING_CAPABILITY_PARAMS {
NvBool streamingCapability;
} NVA081_CTRL_PGPU_GET_VGPU_STREAMING_CAPABILITY_PARAMS;
/* vGPU capabilities */
#define NVA081_CTRL_VGPU_CAPABILITY_MINI_QUARTER_GPU 0
/*
* NVA081_CTRL_CMD_VGPU_SET_CAPABILITY
*
* This command is used to set vGPU capability for the physical GPU.
*
* capability [IN]
* This param specifies the requested capabiity of the device that is to be set
* One of NVA081_CTRL_VGPU_CAPABILITY* values
*
* state [IN]
* This param specifies the state of the capability
*
* Possible status values returned are:
* NV_OK
* NV_ERR_OBJECT_NOT_FOUND
* NV_ERR_INVALID_ARGUMENT
*/
#define NVA081_CTRL_CMD_VGPU_SET_CAPABILITY (0xa081011e) /* finn: Evaluated from "(FINN_NVA081_VGPU_CONFIG_VGPU_CONFIG_INTERFACE_ID << 8) | NVA081_CTRL_VGPU_SET_CAPABILITY_PARAMS_MESSAGE_ID" */
#define NVA081_CTRL_VGPU_SET_CAPABILITY_PARAMS_MESSAGE_ID (0x1eU)
typedef struct NVA081_CTRL_VGPU_SET_CAPABILITY_PARAMS {
NvU32 capability;
NvBool state;
} NVA081_CTRL_VGPU_SET_CAPABILITY_PARAMS;
/* _ctrlA081vgpuconfig_h_ */

24
src/common/sdk/nvidia/inc/ctrl/ctrla084.h
View File

@@ -284,4 +284,28 @@ typedef struct NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_GET_BAR_MAPPING_RANGES_PARAMS
*/
#define NVA084_CTRL_CMD_KERNEL_HOST_VGPU_DEVICE_RESTORE_DEFAULT_EXEC_PARTITION (0xa084010b) /* finn: Evaluated from "(FINN_NVA084_KERNEL_HOST_VGPU_DEVICE_KERNEL_HOST_VGPU_DEVICE_INTERFACE_ID << 8) | 0xB" */
/*
* NVA084_CTRL_CMD_KERNEL_HOST_VGPU_DEVICE_FREE_STATES
*
* This command is a KernelHostVgpuDeviceApi counterpart of
* NVA082_CTRL_CMD_HOST_VGPU_DEVICE_FREE_STATES, that allows
* to clean up a VF state.
*
* Parameters:
*
* flags [IN]
* Specifies what states need to be freed, same as in NVA082_CTRL_CMD_HOST_VGPU_DEVICE_FREE_STATES
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_STATE
*/
#define NVA084_CTRL_CMD_KERNEL_HOST_VGPU_DEVICE_FREE_STATES (0xa084010c) /* finn: Evaluated from "(FINN_NVA084_KERNEL_HOST_VGPU_DEVICE_KERNEL_HOST_VGPU_DEVICE_INTERFACE_ID << 8) | NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_FREE_STATES_PARAMS_MESSAGE_ID" */
#define NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_FREE_STATES_PARAMS_MESSAGE_ID (0xCU)
typedef struct NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_FREE_STATES_PARAMS {
NvU32 flags;
} NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_FREE_STATES_PARAMS;
/* _ctrla084_h_ */

119
src/common/sdk/nvidia/inc/ctrl/ctrla0bc.h Normal file
View File

@@ -0,0 +1,119 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2007-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrla0bc.finn
//
#include "ctrl/ctrlxxxx.h"
/* NVENC_SW_SESSION control commands and parameters */
#define NVA0BC_CTRL_CMD(cat,idx) NVXXXX_CTRL_CMD(0xA0BC, NVA0BC_CTRL_##cat, idx)
/* Command categories (6bits) */
#define NVA0BC_CTRL_RESERVED (0x00)
#define NVA0BC_CTRL_NVENC_SW_SESSION (0x01)
#define NVA0BC_CTRL_CMD_NVENC_MAX_BUFFER_ENTRIES 60
/*
* NVA0BC_CTRL_CMD_NVENC_SW_SESSION_UPDATE_INFO
*
* This command is used to let RM know about runtime information about
* running NVENC session on given GPU.
* *
* hResolution
* This parameter specifies the current horizontal resolution of NVENC session.
* vResolution
* This parameter specifies the current vertical resolution of NVENC session.
* averageEncodeLatency
* This field specifies the average encode latency over last 1 second.
* averageEncodeFps
* This field specifies the average encode FPS over last 1 second.
* timestampBufferSize
* This field specifies the number of entries in the caller's timestampBuffer.
* It should not be greater than NVA0BC_CTRL_CMD_NVENC_MAX_BUFFER_ENTRIES.
* When this field is zero, RM will assume that client has calculated averageEncodeFps
* and averageEncodeLatency, thus ignore timestampBuffer.
* timestampBuffer
* This field specifies a pointer in the caller's address space
* to the buffer holding encode timestamps in microseconds.
* This buffer must be at least as big as timestampBufferSize multiplied
* by the size of the NVA0BC_CTRL_NVENC_TIMESTAMP structure.
* e.g. if there are 10 fps, buffer will contain only 10 entries and rest of
* entries should be 0x00. However if there are more than 60 fps, buffer will
* contain last/latest 60 entries of frame encoding start-end timestamps. Caller
* should make sure timestamps won't wrap around. RM assume that for each
* frame timestamp value endTime would be greater than startTime.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
*/
#define NVA0BC_CTRL_CMD_NVENC_SW_SESSION_UPDATE_INFO (0xa0bc0101) /* finn: Evaluated from "(FINN_NVENC_SW_SESSION_NVENC_SW_SESSION_INTERFACE_ID << 8) | NVA0BC_CTRL_NVENC_SW_SESSION_UPDATE_INFO_PARAMS_MESSAGE_ID" */
typedef struct NVA0BC_CTRL_NVENC_TIMESTAMP {
NV_DECLARE_ALIGNED(NvU64 startTime, 8);
NV_DECLARE_ALIGNED(NvU64 endTime, 8);
} NVA0BC_CTRL_NVENC_TIMESTAMP;
#define NVA0BC_CTRL_NVENC_SW_SESSION_UPDATE_INFO_PARAMS_MESSAGE_ID (0x1U)
typedef struct NVA0BC_CTRL_NVENC_SW_SESSION_UPDATE_INFO_PARAMS {
NvU32 hResolution;
NvU32 vResolution;
NvU32 averageEncodeLatency;
NvU32 averageEncodeFps;
NvU32 timestampBufferSize;
NV_DECLARE_ALIGNED(NvP64 timestampBuffer, 8);
} NVA0BC_CTRL_NVENC_SW_SESSION_UPDATE_INFO_PARAMS;
/*
* NVA0BC_CTRL_CMD_NVENC_SW_SESSION_UPDATE_INFO_V2
*
* This command updates the NVENC software sessions information for the associate GPU.
* This command is similar to NVA0BC_CTRL_CMD_NVENC_SW_SESSION_UPDATE_INFO but doesn't have
* embedded pointers.
*
* Check NVA0BC_CTRL_CMD_NVENC_SW_SESSION_UPDATE_INFO for detailed information.
*/
#define NVA0BC_CTRL_CMD_NVENC_SW_SESSION_UPDATE_INFO_V2 (0xa0bc0102) /* finn: Evaluated from "(FINN_NVENC_SW_SESSION_NVENC_SW_SESSION_INTERFACE_ID << 8) | NVA0BC_CTRL_NVENC_SW_SESSION_UPDATE_INFO_V2_PARAMS_MESSAGE_ID" */
#define NVA0BC_CTRL_NVENC_SW_SESSION_UPDATE_INFO_V2_PARAMS_MESSAGE_ID (0x2U)
typedef struct NVA0BC_CTRL_NVENC_SW_SESSION_UPDATE_INFO_V2_PARAMS {
NvU32 hResolution;
NvU32 vResolution;
NvU32 averageEncodeLatency;
NvU32 averageEncodeFps;
NvU32 timestampBufferSize;
NV_DECLARE_ALIGNED(NVA0BC_CTRL_NVENC_TIMESTAMP timestampBuffer[NVA0BC_CTRL_CMD_NVENC_MAX_BUFFER_ENTRIES], 8);
} NVA0BC_CTRL_NVENC_SW_SESSION_UPDATE_INFO_V2_PARAMS;
/* _ctrla0bc_h_ */

100
src/common/sdk/nvidia/inc/ctrl/ctrla0bd.h Normal file
View File

@@ -0,0 +1,100 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2007-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrla0bd.finn
//
#include "ctrl/ctrlxxxx.h"
/* NVFBC_SW_SESSION control commands and parameters */
#define NVA0BD_CTRL_CMD(cat,idx) NVXXXX_CTRL_CMD(0xA0BD, NVA0BD_CTRL_##cat, idx)
/* Command categories (6bits) */
#define NVA0BD_CTRL_RESERVED (0x00)
#define NVA0BD_CTRL_NVFBC_SW_SESSION (0x01)
#define NVA0BD_CTRL_CMD_NVFBC_MAX_TIMESTAMP_ENTRIES 60
/*
* NVA0BD_CTRL_CMD_NVFBC_SW_SESSION_UPDATE_INFO
*
* This command is used to let RM know about runtime information about
* NVFBC session on given GPU.
* *
* hResolution
* This parameter specifies the current horizontal resolution of NVFBC session.
* vResolution
* This parameter specifies the current vertical resolution of NVFBC session.
* captureCallFlags
* This field specifies the flags associated with the capture call and the session.
* One of the flags specifies whether the user made the capture with wait or not.
* totalGrabCalls
* This field specifies the total number of grab calls made by the user.
* averageLatency
* This field specifies the average capture latency over last 1 second.
* averageFPS
* This field specifies the average frames captured.
* timestampEntryCount
* This field specifies the number of entries in the timestampEntry array.
* It should not be greater than NVA0BD_CTRL_CMD_NVFBC_MAX_TIMESTAMP_ENTRIES.
* When this field is zero, RM will assume that client has calculated averageFBCFps
* and averageFBCLatency, thus ignore timestampEntry array.
* timestampEntry
* This field specifies a array holding capture timestamps in microseconds.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
*/
#define NVA0BD_CTRL_CMD_NVFBC_SW_SESSION_UPDATE_INFO (0xa0bd0101) /* finn: Evaluated from "(FINN_NVFBC_SW_SESSION_NVFBC_SW_SESSION_INTERFACE_ID << 8) | NVA0BD_CTRL_NVFBC_SW_SESSION_UPDATE_INFO_PARAMS_MESSAGE_ID" */
typedef struct NVA0BD_CTRL_NVFBC_TIMESTAMP {
NV_DECLARE_ALIGNED(NvU64 startTime, 8);
NV_DECLARE_ALIGNED(NvU64 endTime, 8);
} NVA0BD_CTRL_NVFBC_TIMESTAMP;
#define NVA0BD_CTRL_NVFBC_SW_SESSION_UPDATE_INFO_PARAMS_MESSAGE_ID (0x1U)
typedef struct NVA0BD_CTRL_NVFBC_SW_SESSION_UPDATE_INFO_PARAMS {
NvU32 hResolution;
NvU32 vResolution;
NvU32 captureCallFlags;
NvU32 totalGrabCalls;
NvU32 averageLatency;
NvU32 averageFPS;
NvU32 timestampEntryCount;
NV_DECLARE_ALIGNED(NVA0BD_CTRL_NVFBC_TIMESTAMP timestampEntry[NVA0BD_CTRL_CMD_NVFBC_MAX_TIMESTAMP_ENTRIES], 8);
} NVA0BD_CTRL_NVFBC_SW_SESSION_UPDATE_INFO_PARAMS;
#define NVA0BD_NVFBC_WITH_WAIT 1:0
#define NVA0BD_NVFBC_WITH_WAIT_FALSE (0x00000000)
#define NVA0BD_NVFBC_WITH_WAIT_INFINITE (0x00000001)
#define NVA0BD_NVFBC_WITH_WAIT_TIMEOUT (0x00000010)
/* _ctrla0bd_h_ */

64
src/common/sdk/nvidia/inc/ctrl/ctrlb0cc/ctrlb0ccinternal.h
View File

@@ -48,7 +48,71 @@ typedef struct NVB0CC_CTRL_CMD_INTERNAL_ALLOC_PMA_STREAM_FINN_PARAMS {
NV_DECLARE_ALIGNED(NVB0CC_CTRL_ALLOC_PMA_STREAM_PARAMS params, 8);
} NVB0CC_CTRL_CMD_INTERNAL_ALLOC_PMA_STREAM_FINN_PARAMS;
/*!
* NVB0CC_CTRL_CMD_INTERNAL_QUIESCE_PMA_CHANNEL
*
* This command is used to quiesce ongoing HWPM streamout and wait for PMA engine to
* become idle. After this point, no new PMA records would be generated and
* membytes streaming would be triggered if GR context is resident or HWPM ctxsw is disabled.
*/
#define NVB0CC_CTRL_CMD_INTERNAL_QUIESCE_PMA_CHANNEL (0xb0cc0201) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_INTERNAL_INTERFACE_ID << 8) | NVB0CC_CTRL_INTERNAL_QUIESCE_PMA_CHANNEL_PARAMS_MESSAGE_ID" */
#define NVB0CC_CTRL_INTERNAL_QUIESCE_PMA_CHANNEL_PARAMS_MESSAGE_ID (0x1U)
typedef struct NVB0CC_CTRL_INTERNAL_QUIESCE_PMA_CHANNEL_PARAMS {
/*!
* [in] The PMA Channel Index associated with a given PMA stream.
*/
NvU32 pmaChannelIdx;
/*!
* [out] Will return if membytes streaming was triggered, to decide if
* we need to poll membytes value on guest to complete streamout.
*/
NvBool bMembytesPollingRequired;
} NVB0CC_CTRL_INTERNAL_QUIESCE_PMA_CHANNEL_PARAMS;
/*!
* NVB0CC_CTRL_CMD_INTERNAL_SRIOV_PROMOTE_PMA_STREAM
*
* Currently only used in vGPU full SRIOV mode.
* This command is used to promote VAs and required info about the HWPM IB
* and PMA buffers from guest to host in full SRIOV mode.
*/
#define NVB0CC_CTRL_CMD_INTERNAL_SRIOV_PROMOTE_PMA_STREAM (0xb0cc0202) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_INTERNAL_INTERFACE_ID << 8) | NVB0CC_CTRL_INTERNAL_SRIOV_PROMOTE_PMA_STREAM_PARAMS_MESSAGE_ID" */
#define NVB0CC_CTRL_INTERNAL_SRIOV_PROMOTE_PMA_STREAM_PARAMS_MESSAGE_ID (0x2U)
typedef struct NVB0CC_CTRL_INTERNAL_SRIOV_PROMOTE_PMA_STREAM_PARAMS {
/*!
* [in] The PMA Channel Index associated with a given PMA stream.
*/
NvU32 pmaChannelIdx;
/*!
* [in] PMA records buffer VA.
*/
NV_DECLARE_ALIGNED(NvU64 pmaBufferVA, 8);
/*!
* [in] size of the PMA records buffer. This must be <= NVB0CC_PMA_BUFFER_SIZE_MAX.
*/
NV_DECLARE_ALIGNED(NvU64 pmaBufferSize, 8);
/*!
* [in] Membytes buffer VA.
*/
NV_DECLARE_ALIGNED(NvU64 membytesVA, 8);
/*!
* [in] HWPM PMA Instance Block PA
*/
NV_DECLARE_ALIGNED(NvU64 hwpmIBPA, 8);
/*!
* [in] HWPM PMA Instance Block aperture
*/
NvU8 hwpmIBAperture;
} NVB0CC_CTRL_INTERNAL_SRIOV_PROMOTE_PMA_STREAM_PARAMS;
/*!
* NVB0CC_CTRL_CMD_INTERNAL_PERMISSIONS_INIT

2
src/common/sdk/nvidia/inc/ctrl/ctrlb0cc/ctrlb0ccprofiler.h
View File

@@ -591,4 +591,6 @@ typedef struct NVB0CC_CTRL_GET_DYNAMIC_MMA_BOOST_STATUS_PARAMS {
NvBool enabled;
} NVB0CC_CTRL_GET_DYNAMIC_MMA_BOOST_STATUS_PARAMS;
/* _ctrlb0ccprofiler_h_ */

41
src/common/sdk/nvidia/inc/ctrl/ctrlc370/ctrlc370or.h Normal file
View File

@@ -0,0 +1,41 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2015-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrlc370/ctrlc370or.finn
//
#include "ctrl/ctrlc370/ctrlc370base.h"
/* C370 is partially derived from 5070 */
#include "ctrl/ctrl5070/ctrl5070or.h"
/* _ctrlc370or_h_ */

26
src/common/sdk/nvidia/inc/ctrl/ctrlc372/ctrlc372chnc.h
View File

@@ -147,16 +147,36 @@
* (On older post-Volta products, clients may set other
* NVC372_CTRL_IMP_LUT_USAGE_xxx values, but they map to
* NVC372_CTRL_IMP_LUT_USAGE_HW_MAX in RM-SW.)
*
* head.cursorSize32p
* This parameter specifies the width of the cursor, in units of 32 pixels.
* So, for example, "8" would mean 8 * 32 = 256, for a 256x256 cursor. Zero
* means the cursor is disabled.
*
* head.tileMask
* This parameter specifies the number of tiles which will be assigned to
* the head. Normally, this parameter is set to zero, allowing IMP to
* calculate the number of tiles, but the number of tiles may be specified
* explicitly for test or debug. If the mode is not possible with the
* specified number of tiles, IMP will report the result as such; the
* number of tiles will not be adjusted.
*
* If tiles are forced for only a subset of active heads, IMP will
* calculate the tiles for the remaining heads (if possible).
*
* If head.bEnableDsc is enabled, head.possibleDscSliceCountMask may
* optionally be used to force the number of DSC slices.
*
* head.bEnableDsc
* bEnableDsc indicates whether or not DSC is enabled
*
* head.dscTargetBppX16
* dscTargetBppX16 is the DSC encoder's target bits per pixel, multiplied
* by 16.
*
* This field is required only on systems that support tiling, and only if
* head.bEnableDsc is true.
*
* head.possibleDscSliceCountMask
* This is a bit mask indicating how many DSC slices are allowed in a
* scanline. If a bit n is set in the bit mask, it means that one possible
@@ -584,8 +604,12 @@ typedef struct NVC372_CTRL_IMP_HEAD {
NvU8 lut;
NvU8 cursorSize32p;
NvU8 tileMask;
NvBool bEnableDsc;
NvU16 dscTargetBppX16;
NvU32 possibleDscSliceCountMask;
NvU32 maxDscSliceWidth;

78
src/common/sdk/nvidia/inc/ctrl/ctrlc56f.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2018-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2018-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -162,12 +162,27 @@ typedef struct NVC56F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN_PARAMS {
NvU32 workSubmitToken;
} NVC56F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN_PARAMS;
/*
* NVC56F_CTRL_CMD_GET_KMB_STAT_ADDR
*
* This struct defines the addresses to log encryption statistics
* amountEncryptedAddr
* Amount of bytes encrypted
* numberEncryptedAddr
* Number of times data was encrypted.
*/
typedef struct NVC56F_CTRL_CMD_GET_KMB_STAT_ADDR {
NV_DECLARE_ALIGNED(NvP64 amountEncryptedAddr, 8);
NV_DECLARE_ALIGNED(NvP64 numberEncryptedAddr, 8);
} NVC56F_CTRL_CMD_GET_KMB_STAT_ADDR;
/*
* NVC56F_CTRL_CMD_GET_KMB
*
* This command returns the Key Material Bundle (KMB) for the current channel.
*
* kmb [OUT] The KMB for the channel.
*
* kmb [OUT] The KMB for the channel.
* hMemory [IN] Memory handle to the encryption statistics buffer for the channel.
*
* Possible status values returned are:
* NV_OK
@@ -180,7 +195,8 @@ typedef struct NVC56F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN_PARAMS {
#define NVC56F_CTRL_CMD_GET_KMB_PARAMS_MESSAGE_ID (0xBU)
typedef struct NVC56F_CTRL_CMD_GET_KMB_PARAMS {
CC_KMB kmb;
CC_KMB kmb;
NvHandle hMemory;
} NVC56F_CTRL_CMD_GET_KMB_PARAMS;
/*
@@ -206,6 +222,60 @@ typedef struct NVC56F_CTRL_ROTATE_SECURE_CHANNEL_IV_PARAMS {
CC_KMB updatedKmb;
} NVC56F_CTRL_ROTATE_SECURE_CHANNEL_IV_PARAMS;
/*
* NV_CONF_COMPUTE_CTRL_SET_SECURITY_POLICY
*
* This command sets the CC security policy.
* It can only be set before GpuReadyState is set.
* Is ignored after GpuReadyState is set.
*
* attackerAdvantage [IN]
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_OBJECT_HANDLE
* NV_ERR_INVALID_STATE
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_NOT_SUPPORTED
*/
/*
* The minimum and maximum values for attackerAdvantage.
* The probability of an attacker successfully guessing the contents of an encrypted packet go up ("attacker advantage").
*/
#define SET_SECURITY_POLICY_ATTACKER_ADVANTAGE_MIN (50)
#define SET_SECURITY_POLICY_ATTACKER_ADVANTAGE_MAX (75)
#define NV_CONF_COMPUTE_CTRL_SET_SECURITY_POLICY (0xc56f010d) /* finn: Evaluated from "(FINN_AMPERE_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | NV_CONF_COMPUTE_CTRL_SET_SECURITY_POLICY_PARAMS_MESSAGE_ID" */
#define NV_CONF_COMPUTE_CTRL_SET_SECURITY_POLICY_PARAMS_MESSAGE_ID (0xDU)
typedef struct NV_CONF_COMPUTE_CTRL_SET_SECURITY_POLICY_PARAMS {
NV_DECLARE_ALIGNED(NvU64 attackerAdvantage, 8);
} NV_CONF_COMPUTE_CTRL_SET_SECURITY_POLICY_PARAMS;
/*
* NV_CONF_COMPUTE_CTRL_GET_SECURITY_POLICY
*
* This command get the CC security policy.
*
* attackerAdvantage [OUT]
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_OBJECT_HANDLE
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_NOT_SUPPORTED
*/
#define NV_CONF_COMPUTE_CTRL_GET_SECURITY_POLICY (0xc56f010e) /* finn: Evaluated from "(FINN_AMPERE_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | NV_CONF_COMPUTE_CTRL_GET_SECURITY_POLICY_PARAMS_MESSAGE_ID" */
#define NV_CONF_COMPUTE_CTRL_GET_SECURITY_POLICY_PARAMS_MESSAGE_ID (0xEU)
typedef struct NV_CONF_COMPUTE_CTRL_GET_SECURITY_POLICY_PARAMS {
NV_DECLARE_ALIGNED(NvU64 attackerAdvantage, 8);
} NV_CONF_COMPUTE_CTRL_GET_SECURITY_POLICY_PARAMS;
/* _ctrlc56f.h_ */

13
src/common/sdk/nvidia/inc/ctrl/ctrlc637.h
View File

@@ -391,4 +391,17 @@ typedef struct NVC637_CTRL_EXEC_PARTITIONS_GET_PROFILE_CAPACITY_PARAMS {
NvU32 totalSpansCount;
} NVC637_CTRL_EXEC_PARTITIONS_GET_PROFILE_CAPACITY_PARAMS;
/*
* NVC637_CTRL_CMD_GET_UUID
*/
#define NVC637_CTRL_CMD_GET_UUID (0xc63701aaU) /* finn: Evaluated from "(FINN_AMPERE_SMC_PARTITION_REF_EXEC_PARTITIONS_INTERFACE_ID << 8) | NVC637_CTRL_GET_UUID_PARAMS_MESSAGE_ID" */
#define NVC637_CTRL_GET_UUID_PARAMS_MESSAGE_ID (0xAAU)
typedef struct NVC637_CTRL_GET_UUID_PARAMS {
NvU8 uuid[NVC637_UUID_LEN];
char uuidStr[NVC637_UUID_STR_LEN];
} NVC637_CTRL_GET_UUID_PARAMS;
// _ctrlc637_h_

36
src/common/sdk/nvidia/inc/ctrl/ctrlcb33.h
View File

@@ -89,6 +89,8 @@
* Dev tools mode is used for debugging/profiling
* Dev tools mode is set at system level and implies that all GPUs in
* the system have this mode enabled/disabled
* multiGpuMode: [OUT]
* Specifies the mode in which a multi gpu system is operating
*
* cpuCapability, gpusCapability & environment are determined by the
* driver and cannot be modified later on
@@ -101,26 +103,29 @@
* NV_ERR_INVALID_CLIENT
* NV_ERR_OBJECT_NOT_FOUND
*/
#define NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_GET_CAPABILITIES (0xcb330101) /* finn: Evaluated from "(FINN_NV_CONFIDENTIAL_COMPUTE_CONF_COMPUTE_INTERFACE_ID << 8) | 0x1" */
#define NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_GET_CAPABILITIES (0xcb330101) /* finn: Evaluated from "(FINN_NV_CONFIDENTIAL_COMPUTE_CONF_COMPUTE_INTERFACE_ID << 8) | 0x1" */
#define NV_CONF_COMPUTE_SYSTEM_CPU_CAPABILITY_NONE 0
#define NV_CONF_COMPUTE_SYSTEM_CPU_CAPABILITY_AMD_SEV 1
#define NV_CONF_COMPUTE_SYSTEM_CPU_CAPABILITY_INTEL_TDX 2
#define NV_CONF_COMPUTE_SYSTEM_CPU_CAPABILITY_NONE 0
#define NV_CONF_COMPUTE_SYSTEM_CPU_CAPABILITY_AMD_SEV 1
#define NV_CONF_COMPUTE_SYSTEM_CPU_CAPABILITY_INTEL_TDX 2
#define NV_CONF_COMPUTE_SYSTEM_GPUS_CAPABILITY_NONE 0
#define NV_CONF_COMPUTE_SYSTEM_GPUS_CAPABILITY_APM 1
#define NV_CONF_COMPUTE_SYSTEM_GPUS_CAPABILITY_HCC 2
#define NV_CONF_COMPUTE_SYSTEM_GPUS_CAPABILITY_NONE 0
#define NV_CONF_COMPUTE_SYSTEM_GPUS_CAPABILITY_APM 1
#define NV_CONF_COMPUTE_SYSTEM_GPUS_CAPABILITY_HCC 2
#define NV_CONF_COMPUTE_SYSTEM_ENVIRONMENT_UNAVAILABLE 0
#define NV_CONF_COMPUTE_SYSTEM_ENVIRONMENT_SIM 1
#define NV_CONF_COMPUTE_SYSTEM_ENVIRONMENT_PROD 2
#define NV_CONF_COMPUTE_SYSTEM_ENVIRONMENT_UNAVAILABLE 0
#define NV_CONF_COMPUTE_SYSTEM_ENVIRONMENT_SIM 1
#define NV_CONF_COMPUTE_SYSTEM_ENVIRONMENT_PROD 2
#define NV_CONF_COMPUTE_SYSTEM_FEATURE_DISABLED 0
#define NV_CONF_COMPUTE_SYSTEM_FEATURE_APM_ENABLED 1
#define NV_CONF_COMPUTE_SYSTEM_FEATURE_HCC_ENABLED 2
#define NV_CONF_COMPUTE_SYSTEM_FEATURE_DISABLED 0
#define NV_CONF_COMPUTE_SYSTEM_FEATURE_APM_ENABLED 1
#define NV_CONF_COMPUTE_SYSTEM_FEATURE_HCC_ENABLED 2
#define NV_CONF_COMPUTE_SYSTEM_DEVTOOLS_MODE_DISABLED 0
#define NV_CONF_COMPUTE_SYSTEM_DEVTOOLS_MODE_ENABLED 1
#define NV_CONF_COMPUTE_SYSTEM_DEVTOOLS_MODE_DISABLED 0
#define NV_CONF_COMPUTE_SYSTEM_DEVTOOLS_MODE_ENABLED 1
#define NV_CONF_COMPUTE_SYSTEM_MULTI_GPU_MODE_NONE 0
#define NV_CONF_COMPUTE_SYSTEM_MULTI_GPU_MODE_PROTECTED_PCIE 1
typedef struct NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_GET_CAPABILITIES_PARAMS {
NvU8 cpuCapability;
@@ -128,6 +133,7 @@ typedef struct NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_GET_CAPABILITIES_PARAMS {
NvU8 environment;
NvU8 ccFeature;
NvU8 devToolsMode;
NvU8 multiGpuMode;
} NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_GET_CAPABILITIES_PARAMS;
/*

29
src/common/sdk/nvidia/inc/g_finn_rm_api.h
View File

@@ -219,8 +219,6 @@ typedef FINN_RM_API FINN_NV01_TIMER_TMR;
typedef FINN_RM_API FINN_FABRIC_MANAGER_SESSION_RESERVED;
#define FINN_FABRIC_MANAGER_SESSION_FM_INTERFACE_ID (0xf01U)
typedef FINN_RM_API FINN_FABRIC_MANAGER_SESSION_FM;
#define FINN_FABRIC_MANAGER_SESSION_IMEX_INTERFACE_ID (0xf02U)
typedef FINN_RM_API FINN_FABRIC_MANAGER_SESSION_IMEX;
#define FINN_NV0020_GPU_MANAGEMENT_RESERVED_INTERFACE_ID (0x2000U)
typedef FINN_RM_API FINN_NV0020_GPU_MANAGEMENT_RESERVED;
#define FINN_NV0020_GPU_MANAGEMENT_GPU_MGMT_INTERFACE_ID (0x2001U)
@@ -302,18 +300,6 @@ typedef FINN_RM_API FINN_NV_MEMORY_EXPORT_RESERVED;
typedef FINN_RM_API FINN_NV_MEMORY_EXPORT;
#define FINN_IMEX_SESSION_INTERFACE_ID (0xf100U)
typedef FINN_RM_API FINN_IMEX_SESSION;
#define FINN_NV01_MEMORY_FABRIC_EXPORT_RESERVED_INTERFACE_ID (0xf400U)
typedef FINN_RM_API FINN_NV01_MEMORY_FABRIC_EXPORT_RESERVED;
#define FINN_NV01_MEMORY_FABRIC_EXPORT_EXPORT_INTERFACE_ID (0xf401U)
typedef FINN_RM_API FINN_NV01_MEMORY_FABRIC_EXPORT_EXPORT;
#define FINN_NV01_MEMORY_FABRIC_IMPORT_RESERVED_INTERFACE_ID (0xf500U)
typedef FINN_RM_API FINN_NV01_MEMORY_FABRIC_IMPORT_RESERVED;
#define FINN_NV01_MEMORY_FABRIC_IMPORT_IMPORT_INTERFACE_ID (0xf501U)
typedef FINN_RM_API FINN_NV01_MEMORY_FABRIC_IMPORT_IMPORT;
#define FINN_NV_MEMORY_FABRIC_EXPORT_RESERVED_INTERFACE_ID (0xf700U)
typedef FINN_RM_API FINN_NV_MEMORY_FABRIC_EXPORT_RESERVED;
#define FINN_NV_MEMORY_FABRIC_EXPORT_INTERFACE_ID (0xf701U)
typedef FINN_RM_API FINN_NV_MEMORY_FABRIC_EXPORT;
#define FINN_NV_MEMORY_FABRIC_RESERVED_INTERFACE_ID (0xf800U)
typedef FINN_RM_API FINN_NV_MEMORY_FABRIC_RESERVED;
#define FINN_NV_MEMORY_FABRIC_FABRIC_INTERFACE_ID (0xf801U)
@@ -322,10 +308,6 @@ typedef FINN_RM_API FINN_NV_MEMORY_FABRIC_FABRIC;
typedef FINN_RM_API FINN_NV_MEMORY_FABRIC_IMPORT_V2_RESERVED;
#define FINN_NV_MEMORY_FABRIC_IMPORT_V2_IMPORT_INTERFACE_ID (0xf901U)
typedef FINN_RM_API FINN_NV_MEMORY_FABRIC_IMPORT_V2_IMPORT;
#define FINN_NV_MEMORY_FABRIC_EXPORTED_REF_RESERVED_INTERFACE_ID (0xfa00U)
typedef FINN_RM_API FINN_NV_MEMORY_FABRIC_EXPORTED_REF_RESERVED;
#define FINN_NV_MEMORY_FABRIC_EXPORTED_REF_EXPORT_REF_INTERFACE_ID (0xfa01U)
typedef FINN_RM_API FINN_NV_MEMORY_FABRIC_EXPORTED_REF_EXPORT_REF;
#define FINN_NV_MEMORY_FABRIC_IMPORTED_REF_RESERVED_INTERFACE_ID (0xfb00U)
typedef FINN_RM_API FINN_NV_MEMORY_FABRIC_IMPORTED_REF_RESERVED;
#define FINN_NV_MEMORY_FABRIC_IMPORTED_REF_IMPORT_REF_INTERFACE_ID (0xfb01U)
@@ -334,7 +316,7 @@ typedef FINN_RM_API FINN_NV_MEMORY_FABRIC_IMPORTED_REF_IMPORT_REF;
typedef FINN_RM_API FINN_NV_MEMORY_MULTICAST_FABRIC_RESERVED;
#define FINN_NV_MEMORY_MULTICAST_FABRIC_FABRIC_INTERFACE_ID (0xfd01U)
typedef FINN_RM_API FINN_NV_MEMORY_MULTICAST_FABRIC_FABRIC;
#define FINN_NV_MEMORY_MAPPER_INTERFACE_ID (0x00FE00U)
#define FINN_NV_MEMORY_MAPPER_INTERFACE_ID (0xfe01U)
typedef FINN_RM_API FINN_NV_MEMORY_MAPPER;
#define FINN_NV20_SUBDEVICE_0_RESERVED_INTERFACE_ID (0x208000U)
@@ -587,7 +569,8 @@ typedef FINN_RM_API FINN_KEPLER_CHANNEL_GPFIFO_A_EVENT;
typedef FINN_RM_API FINN_KEPLER_CHANNEL_GPFIFO_A_GPFIFO;
#define FINN_KEPLER_CHANNEL_GPFIFO_A_INTERNAL_INTERFACE_ID (0xa06f03U)
typedef FINN_RM_API FINN_KEPLER_CHANNEL_GPFIFO_A_INTERNAL;
#define FINN_KEPLER_DEVICE_VGPU_RESERVED_INTERFACE_ID (0xa08000U)
typedef FINN_RM_API FINN_KEPLER_DEVICE_VGPU_RESERVED;
#define FINN_KEPLER_DEVICE_VGPU_VGPU_DISPLAY_INTERFACE_ID (0xa08001U)
typedef FINN_RM_API FINN_KEPLER_DEVICE_VGPU_VGPU_DISPLAY;
#define FINN_KEPLER_DEVICE_VGPU_VGPU_MEMORY_INTERFACE_ID (0xa08002U)
@@ -690,6 +673,8 @@ typedef FINN_RM_API FINN_NVC370_DISPLAY_RESERVED;
typedef FINN_RM_API FINN_NVC370_DISPLAY_CHNCTL;
#define FINN_NVC370_DISPLAY_EVENT_INTERFACE_ID (0xc37009U)
typedef FINN_RM_API FINN_NVC370_DISPLAY_EVENT;
#define FINN_NVC370_DISPLAY_OR_INTERFACE_ID (0xc37004U)
typedef FINN_RM_API FINN_NVC370_DISPLAY_OR;
#define FINN_NVC370_DISPLAY_RG_INTERFACE_ID (0xc37002U)
typedef FINN_RM_API FINN_NVC370_DISPLAY_RG;
#define FINN_NVC370_DISPLAY_VERIF_INTERFACE_ID (0xc37006U)
@@ -747,6 +732,10 @@ typedef FINN_RM_API FINN_NV_CONFIDENTIAL_COMPUTE_CONF_COMPUTE;
typedef FINN_RM_API FINN_NV_COUNTER_COLLECTION_UNIT_RESERVED;
#define FINN_NV_COUNTER_COLLECTION_UNIT_CCU_INTERFACE_ID (0xcbca01U)
typedef FINN_RM_API FINN_NV_COUNTER_COLLECTION_UNIT_CCU;
#define FINN_NV_SCHEDULER_RESERVED_INTERFACE_ID (0xcbcb00U)
typedef FINN_RM_API FINN_NV_SCHEDULER_RESERVED;
#define FINN_NV_SCHEDULER_SCHEDULER_INTERFACE_ID (0xcbcb01U)
typedef FINN_RM_API FINN_NV_SCHEDULER_SCHEDULER;
#define FINN_NVE2_SYNCPOINT_BASE_RESERVED_INTERFACE_ID (0xe2ad00U)
typedef FINN_RM_API FINN_NVE2_SYNCPOINT_BASE_RESERVED;
#define FINN_NVE2_SYNCPOINT_BASE_SYNCPOINT_BASE_INTERFACE_ID (0xe2ad01U)

6
src/common/sdk/nvidia/inc/nverror.h
View File

@@ -61,6 +61,7 @@
#define ROBUST_CHANNEL_PREEMPTIVE_REMOVAL (45)
#define ROBUST_CHANNEL_NVENC0_ERROR (47)
#define ROBUST_CHANNEL_GPU_ECC_DBE (48)
#define FB_MEMORY_ERROR (58)
#define PMU_ERROR (59)
#define ROBUST_CHANNEL_SEC2_ERROR (60)
#define PMU_BREAKPOINT (61)
@@ -108,6 +109,7 @@
#define ROBUST_CHANNEL_NVJPG5_ERROR (103)
#define ROBUST_CHANNEL_NVJPG6_ERROR (104)
#define ROBUST_CHANNEL_NVJPG7_ERROR (105)
#define DESTINATION_FLA_TRANSLATION_ERROR (108)
#define SEC_FAULT_ERROR (110)
#define GSP_RPC_TIMEOUT (119)
#define GSP_ERROR (120)
@@ -120,7 +122,9 @@
#define NVLINK_FLA_PRIV_ERR (137)
#define ROBUST_CHANNEL_DLA_ERROR (138)
#define UNRECOVERABLE_ECC_ERROR_ESCAPE (140)
#define ROBUST_CHANNEL_LAST_ERROR (UNRECOVERABLE_ECC_ERROR_ESCAPE)
#define ROBUST_CHANNEL_FAST_PATH_ERROR (141)
#define GPU_INIT_ERROR (143)
#define ROBUST_CHANNEL_LAST_ERROR (GPU_INIT_ERROR)
// Indexed CE reference

3
src/common/sdk/nvidia/inc/nvmisc.h
View File

@@ -919,6 +919,9 @@ static NV_FORCEINLINE void *NV_NVUPTR_TO_PTR(NvUPtr address)
//
#define NV_BIT_SET_128(b, lo, hi) { nvAssert( (b) < 128 ); if ( (b) < 64 ) (lo) |= NVBIT64(b); else (hi) |= NVBIT64( b & 0x3F ); }
// Get the number of elements the specified fixed-size array
#define NV_ARRAY_ELEMENTS(x) ((sizeof(x)/sizeof((x)[0])))
#ifdef __cplusplus
}
#endif //__cplusplus

25
src/common/sdk/nvidia/inc/nvos.h
View File

@@ -722,6 +722,7 @@ typedef struct
NvU64 rangeEnd NV_ALIGN_BYTES(8); // [IN] - from rangeBegin to rangeEnd, inclusive.
NvU32 attr2; // [IN/OUT] - surface attributes requested, and surface attributes allocated
NvU32 ctagOffset; // [IN] - comptag offset for this surface (see NVOS32_ALLOC_COMPTAG_OFFSET)
NvS32 numaNode; // [IN] - NUMA node from which memory should be allocated
} AllocSize;
// NVOS32_FUNCTION_ALLOC_TILED_PITCH_HEIGHT
@@ -748,6 +749,7 @@ typedef struct
NvU64 rangeEnd NV_ALIGN_BYTES(8); // [IN] - from rangeBegin to rangeEnd, inclusive.
NvU32 attr2; // [IN/OUT] - surface attributes requested, and surface attributes allocated
NvU32 ctagOffset; // [IN] - comptag offset for this surface (see NVOS32_ALLOC_COMPTAG_OFFSET)
NvS32 numaNode; // [IN] - NUMA node from which memory should be allocated
} AllocTiledPitchHeight;
// NVOS32_FUNCTION_FREE
@@ -823,6 +825,7 @@ typedef struct
NvP64 address NV_ALIGN_BYTES(8);// [OUT] - returned address
NvU32 attr2; // [IN/OUT] - surface attributes requested, and surface attributes allocated
NvU32 ctagOffset; // [IN] - comptag offset for this surface (see NVOS32_ALLOC_COMPTAG_OFFSET)
NvS32 numaNode; // [IN] - NUMA node from which memory should be allocated
} AllocSizeRange;
// additions for Longhorn
@@ -1300,6 +1303,11 @@ typedef struct
#define NVOS32_ATTR2_PROTECTION_DEVICE_READ_WRITE 0x00000000
#define NVOS32_ATTR2_PROTECTION_DEVICE_READ_ONLY 0x00000001
// Deprecated. To be deleted once client code has removed references.
#define NVOS32_ATTR2_USE_EGM 24:24
#define NVOS32_ATTR2_USE_EGM_FALSE 0x00000000
#define NVOS32_ATTR2_USE_EGM_TRUE 0x00000001
//
// Allow client allocations to go to protected/unprotected video/system memory.
// When Ampere Protected Model aka APM or Confidential Compute is enabled and
@@ -1834,6 +1842,18 @@ typedef struct
#define NVOS33_FLAGS_CACHING_TYPE_DEFAULT 6
#define NVOS33_FLAGS_CACHING_TYPE_UNCACHED_WEAK 7
//
// For use when Hopper Confidential Compute is operating in devtools mode
// BAR1 access to CPR vidmem is blocked to CPU-RM by default when HCC is
// enabled in both devtools and prod modes. However, certain mappings are
// allowed to go through successfully only in devtools mode. For example,
// CPU mappings made on behalf of devtools, event buffer mappings are allowed
// to happen in devtools mode
//
#define NVOS33_FLAGS_ALLOW_MAPPING_ON_HCC 26:26
#define NVOS33_FLAGS_ALLOW_MAPPING_ON_HCC_NO (0x00000000)
#define NVOS33_FLAGS_ALLOW_MAPPING_ON_HCC_YES (0x00000001)
/* parameters */
typedef struct
{
@@ -2159,6 +2179,7 @@ typedef struct
NvHandle hMemory; // [IN] memory handle for mapping
NvV32 flags; // [IN] flags
NvU64 dmaOffset NV_ALIGN_BYTES(8); // [IN] dma offset from NV04_MAP_MEMORY_DMA
NvU64 size NV_ALIGN_BYTES(8); // [IN] size to unmap, 0 to unmap entire mapping
NvV32 status; // [OUT] status
} NVOS47_PARAMETERS;
@@ -2423,7 +2444,8 @@ typedef struct {
#define NV_CHANNELGPFIFO_NOTIFICATION_TYPE_ERROR 0x00000000
#define NV_CHANNELGPFIFO_NOTIFICATION_TYPE_WORK_SUBMIT_TOKEN 0x00000001
#define NV_CHANNELGPFIFO_NOTIFICATION_TYPE__SIZE_1 2
#define NV_CHANNELGPFIFO_NOTIFICATION_TYPE_KEY_ROTATION_STATUS 0x00000002
#define NV_CHANNELGPFIFO_NOTIFICATION_TYPE__SIZE_1 3
#define NV_CHANNELGPFIFO_NOTIFICATION_STATUS_VALUE 14:0
#define NV_CHANNELGPFIFO_NOTIFICATION_STATUS_IN_PROGRESS 15:15
#define NV_CHANNELGPFIFO_NOTIFICATION_STATUS_IN_PROGRESS_TRUE 0x1
@@ -2727,6 +2749,7 @@ typedef struct
#define NV_VASPACE_ALLOCATION_FLAGS_SKIP_SCRUB_MEMPOOL BIT(10)
#define NV_VASPACE_ALLOCATION_FLAGS_OPTIMIZE_PTETABLE_MEMPOOL_USAGE BIT(11)
#define NV_VASPACE_ALLOCATION_FLAGS_REQUIRE_FIXED_OFFSET BIT(12)
#define NV_VASPACE_ALLOCATION_FLAGS_PTETABLE_HEAP_MANAGED BIT(13)
#define NV_VASPACE_ALLOCATION_INDEX_GPU_NEW 0x00 //<! Create new VASpace, by default
#define NV_VASPACE_ALLOCATION_INDEX_GPU_HOST 0x01 //<! Acquire reference to BAR1 VAS.

3
src/common/sdk/nvidia/inc/nvstatuscodes.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2014-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2014-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -150,6 +150,7 @@ NV_STATUS_CODE(NV_ERR_NVLINK_CONFIGURATION_ERROR, 0x00000078, "Nvlink Confi
NV_STATUS_CODE(NV_ERR_RISCV_ERROR, 0x00000079, "Generic RISC-V assert or halt")
NV_STATUS_CODE(NV_ERR_FABRIC_MANAGER_NOT_PRESENT, 0x0000007A, "Fabric Manager is not loaded")
NV_STATUS_CODE(NV_ERR_ALREADY_SIGNALLED, 0x0000007B, "Semaphore Surface value already >= requested wait value")
NV_STATUS_CODE(NV_ERR_QUEUE_TASK_SLOT_NOT_AVAILABLE, 0x0000007C, "PMU RPC error due to no queue slot available for this event")
// Warnings:
NV_STATUS_CODE(NV_WARN_HOT_SWITCH, 0x00010001, "WARNING Hot switch")

7
src/common/sdk/nvidia/inc/nvtypes.h
View File

@@ -141,7 +141,12 @@ typedef signed short NvS16; /* -32768 to 32767 */
#endif
// Macro to build an NvU32 from four bytes, listed from msb to lsb
#define NvU32_BUILD(a, b, c, d) (((a) << 24) | ((b) << 16) | ((c) << 8) | (d))
#define NvU32_BUILD(a, b, c, d) \
((NvU32)( \
(((NvU32)(a) & 0xff) << 24) | \
(((NvU32)(b) & 0xff) << 16) | \
(((NvU32)(c) & 0xff) << 8) | \
(((NvU32)(d) & 0xff))))
#if NVTYPES_USE_STDINT
typedef uint32_t NvV32; /* "void": enumerated or multiple fields */