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This commit is contained in:
Bernhard Stoeckner
2024-01-24 17:51:53 +01:00
parent bb2dac1f20
commit 91676d6628
1411 changed files with 261367 additions and 145959 deletions
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12
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080bios.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2005-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2005-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -353,6 +353,8 @@ typedef struct NV2080_CTRL_BIOS_GET_NBSI_OBJ_PARAMS {
* This field returns the sku for the current chip.
* chipSKUMod
* This field returns the SKU modifier.
* skuConfigVersion
* Version number for the SKU configuration detailing pstate, thermal, VF curve and so on.
* project
* This field returns the Project (Board) number.
* projectSKU
@@ -369,15 +371,13 @@ typedef struct NV2080_CTRL_BIOS_GET_NBSI_OBJ_PARAMS {
*/
#define NV2080_CTRL_CMD_BIOS_GET_SKU_INFO (0x20800808) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BIOS_INTERFACE_ID << 8) | NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS_MESSAGE_ID" */
/* maximum length of parameter strings */
#define NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS_MESSAGE_ID (0x8U)
typedef struct NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS {
NvU32 BoardID;
char chipSKU[4];
char chipSKUMod[2];
char chipSKU[9];
char chipSKUMod[5];
NvU32 skuConfigVersion;
char project[5];
char projectSKU[5];
char CDP[6];

78
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080ecc.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2017-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2017-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -60,4 +60,80 @@ typedef struct NV2080_CTRL_ECC_GET_CLIENT_EXPOSED_COUNTERS_PARAMS {
NV_DECLARE_ALIGNED(NvU64 dramCorrectedTotalCounts, 8);
NV_DECLARE_ALIGNED(NvU64 dramUncorrectedTotalCounts, 8);
} NV2080_CTRL_ECC_GET_CLIENT_EXPOSED_COUNTERS_PARAMS;
#define NV2080_CTRL_CMD_ECC_GET_ECI_COUNTERS (0x20803401U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_ECC_INTERFACE_ID << 8) | NV2080_CTRL_ECC_GET_ECI_COUNTERS_PARAMS_MESSAGE_ID" */
/*
* NV2080_CTRL_ECC_GET_ECI_COUNTERS_PARAMS
*
* sramParityUncorrectedUnique [out]
* sramSecDedUncorrectedUnique [out]
* sramCorrectedTotal [out]
* dramUncorrectedTotal [out]
* dramCorrectedTotal [out]
* Aggregate error counts for SRAM and DRAM.
*
* lastClearedTimestamp [out]
* unix-epoch based timestamp. These fields indicate when the error counters
* were last cleared by the user.
*
* sramBucketL2 [out]
* sramBucketSM [out]
* sramBucketPcie [out]
* sramBucketFirmware [out]
* sramBucketOther [out]
* Aggregate unique uncorrctable error counts for SRAM buckets.
*
* sramErrorThresholdExceeded [out]
* Boolean flag which is set if SRAM error threshold was exceeded
*/
#define NV2080_CTRL_ECC_GET_ECI_COUNTERS_PARAMS_MESSAGE_ID (0x1U)
typedef struct NV2080_CTRL_ECC_GET_ECI_COUNTERS_PARAMS {
NV_DECLARE_ALIGNED(NvU64 sramParityUncorrectedUnique, 8);
NV_DECLARE_ALIGNED(NvU64 sramSecDedUncorrectedUnique, 8);
NV_DECLARE_ALIGNED(NvU64 sramCorrectedTotal, 8);
NV_DECLARE_ALIGNED(NvU64 dramUncorrectedTotal, 8);
NV_DECLARE_ALIGNED(NvU64 dramCorrectedTotal, 8);
NvU32 lastClearedTimestamp;
NV_DECLARE_ALIGNED(NvU64 sramBucketL2, 8);
NV_DECLARE_ALIGNED(NvU64 sramBucketSM, 8);
NV_DECLARE_ALIGNED(NvU64 sramBucketPcie, 8);
NV_DECLARE_ALIGNED(NvU64 sramBucketFirmware, 8);
NV_DECLARE_ALIGNED(NvU64 sramBucketOther, 8);
NvBool sramErrorThresholdExceeded;
} NV2080_CTRL_ECC_GET_ECI_COUNTERS_PARAMS;
/*
* NV2080_CTRL_ECC_GET_VOLATILE_COUNTS_PARAMS
*
* Reports count of volatile errors
*
* sramCorUni [out]:
* Unique correctable SRAM error count
* sramUncParityUni [out]:
* Unique uncorrectable SRAM parity error count
* sramUncSecDedUni [out]:
* Unique uncorrectable SRAM SEC-DED error count
* dramCorTot [out]:
* Total correctable DRAM error count
* dramUncTot [out]:
* total uncorrectable DRAM error count
*/
#define NV2080_CTRL_CMD_ECC_GET_VOLATILE_COUNTS (0x20803402U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_ECC_INTERFACE_ID << 8) | NV2080_CTRL_ECC_GET_VOLATILE_COUNTS_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_ECC_GET_VOLATILE_COUNTS_PARAMS_MESSAGE_ID (0x2U)
typedef struct NV2080_CTRL_ECC_GET_VOLATILE_COUNTS_PARAMS {
NV_DECLARE_ALIGNED(NvU64 sramCorUni, 8);
NV_DECLARE_ALIGNED(NvU64 sramUncParityUni, 8);
NV_DECLARE_ALIGNED(NvU64 sramUncSecDedUni, 8);
NV_DECLARE_ALIGNED(NvU64 dramCorTot, 8);
NV_DECLARE_ALIGNED(NvU64 dramUncTot, 8);
} NV2080_CTRL_ECC_GET_VOLATILE_COUNTS_PARAMS;
/* _ctrl2080ecc_h_ */

35
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080event.h
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@@ -335,4 +335,39 @@ typedef struct NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_PARAMS {
NvBool bAllUsers;
} NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_PARAMS;
/*
* NV2080_CTRL_CMD_EVENT_RATS_GSP_TRACE_BIND_EVTBUF_FOR_UID
*
* This command is used to create a RATS tracing bindpoint to eventbuffer.
*
* hEventBuffer[IN]
* The event buffer to bind to
*
* tracepointMask[IN]
* Bitmask for selecting tracepoints
*
* gspLoggingBufferSize[IN]
* User defined size of GSP owned event logging buffer
*
* gspLoggingBufferWatermark[IN]
* User defined watermark that triggers RPC to kernel of traces
* HINT: set higher for more frequent trace updates
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_NOT_SUPPORTED
*/
#define NV2080_CTRL_CMD_EVENT_RATS_GSP_TRACE_BIND_EVTBUF (0x2080030a) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_EVENT_INTERFACE_ID << 8) | NV2080_CTRL_EVENT_RATS_GSP_TRACE_BIND_EVTBUF_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_EVENT_RATS_GSP_TRACE_BIND_EVTBUF_PARAMS_MESSAGE_ID (0xAU)
typedef struct NV2080_CTRL_EVENT_RATS_GSP_TRACE_BIND_EVTBUF_PARAMS {
NvHandle hEventBuffer;
NV_DECLARE_ALIGNED(NvU64 tracepointMask, 8);
NvU32 gspLoggingBufferSize;
NvU32 gspLoggingBufferWatermark;
} NV2080_CTRL_EVENT_RATS_GSP_TRACE_BIND_EVTBUF_PARAMS;
/* _ctrl2080event_h_ */

95
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080fb.h
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@@ -35,6 +35,7 @@
/* NV20_SUBDEVICE_XX fb control commands and parameters */
#include "nvlimits.h"
#include "nvcfg_sdk.h"
/*
* NV2080_CTRL_FB_INFO
@@ -360,6 +361,8 @@ typedef NVXXXX_CTRL_XXX_INFO NV2080_CTRL_FB_INFO;
#define NV2080_CTRL_FB_INFO_RAM_TYPE_LPDDR5 (0x00000013U) /* LPDDR (Low Power SDDR) used on T23x and later.*/
#define NV2080_CTRL_FB_INFO_RAM_TYPE_HBM3 (0x00000014U) /* HBM3 (High Bandwidth Memory) v3 */
/* valid RAM LOCATION types */
#define NV2080_CTRL_FB_INFO_RAM_LOCATION_GPU_DEDICATED (0x00000000U)
#define NV2080_CTRL_FB_INFO_RAM_LOCATION_SYS_SHARED (0x00000001U)
@@ -519,8 +522,60 @@ typedef struct NV2080_CTRL_FB_GET_CALIBRATION_LOCK_FAILED_PARAMS {
} NV2080_CTRL_FB_GET_CALIBRATION_LOCK_FAILED_PARAMS;
/* valid flags parameter values */
#define NV2080_CTRL_CMD_FB_GET_CAL_FLAG_NONE (0x00000000U)
#define NV2080_CTRL_CMD_FB_GET_CAL_FLAG_RESET (0x00000001U)
#define NV2080_CTRL_CMD_FB_GET_CAL_FLAG_NONE (0x00000000U)
#define NV2080_CTRL_CMD_FB_GET_CAL_FLAG_RESET (0x00000001U)
/*
* NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE_IRQL
*
* If supported by hardware and the OS, this command implements a streamlined version of
* NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE which can be called at high IRQL and Bypass the
* RM Lock.
*
* Requires the following NVOS54_PARAMETERS to be set for raised IRQ / Lock Bypass operation:
* NVOS54_FLAGS_IRQL_RAISED
* NVOS54_FLAGS_LOCK_BYPASS
*
* flags
* Contains flags to control various aspects of the flush. Valid values
* are defined in NV2080_CTRL_CTRL_CMD_FB_FLUSH_GPU_CACHE_IRQL_FLAGS*.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_NOT_SUPPORTED
* NV_ERR_INVALID_STATE
* NV_ERR_INVALID_ARGUMENT
*
* See Also:
* NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE
* This is the more generalized version which is not intended to be called at raised IRQ level
* NV0080_CTRL_CMD_DMA_FLUSH
* Performs flush operations in broadcast for the GPU cache and other hardware
* engines. Use this call if you want to flush all GPU caches in a
* broadcast device.
* NV0041_CTRL_CMD_SURFACE_FLUSH_GPU_CACHE
* Flushes memory associated with a single allocation if the hardware
* supports it. Use this call if you want to flush a single allocation and
* you have a memory object describing the physical memory.
*/
#define NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE_IRQL (0x2080130dU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE_IRQL_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE_IRQL_PARAMS_MESSAGE_ID (0xDU)
typedef struct NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE_IRQL_PARAMS {
NvU32 flags;
} NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE_IRQL_PARAMS;
/* valid fields and values for flags */
#define NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE_IRQL_FLAGS_WRITE_BACK 0:0
#define NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE_IRQL_FLAGS_WRITE_BACK_NO (0x00000000U)
#define NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE_IRQL_FLAGS_WRITE_BACK_YES (0x00000001U)
#define NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE_IRQL_FLAGS_INVALIDATE 1:1
#define NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE_IRQL_FLAGS_INVALIDATE_NO (0x00000000U)
#define NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE_IRQL_FLAGS_INVALIDATE_YES (0x00000001U)
#define NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE_IRQL_FLAGS_FB_FLUSH 2:2
#define NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE_IRQL_FLAGS_FB_FLUSH_NO (0x00000000U)
#define NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE_IRQL_FLAGS_FB_FLUSH_YES (0x00000001U)
/*
* NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE
@@ -565,9 +620,9 @@ typedef struct NV2080_CTRL_FB_GET_CALIBRATION_LOCK_FAILED_PARAMS {
* supports it. Use this call if you want to flush a single allocation and
* you have a memory object describing the physical memory.
*/
#define NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE (0x2080130eU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_FLUSH_GPU_CACHE_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE (0x2080130eU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_FLUSH_GPU_CACHE_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_FB_FLUSH_GPU_CACHE_MAX_ADDRESSES 500U
#define NV2080_CTRL_FB_FLUSH_GPU_CACHE_MAX_ADDRESSES 500U
#define NV2080_CTRL_FB_FLUSH_GPU_CACHE_PARAMS_MESSAGE_ID (0xEU)
@@ -2294,6 +2349,34 @@ typedef struct NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_SUBP_MASK_PARAMS {
NV_DECLARE_ALIGNED(NvU64 fbpaSubpEnMask, 8);
} NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_SUBP_MASK_PARAMS;
/*!
* Structure holding the in/out params for NV2080_CTRL_SYSL2_FS_INFO_SYSLTC_MASK.
*/
typedef struct NV2080_CTRL_SYSL2_FS_INFO_SYSLTC_MASK_PARAMS {
/*!
* [IN]: physical/local sys Id.
*/
NvU32 sysIdx;
/*!
* [OUT]: physical/local sysltc mask.
*/
NvU32 sysl2LtcEnMask;
} NV2080_CTRL_SYSL2_FS_INFO_SYSLTC_MASK_PARAMS;
/*!
* Structure holding the in/out params for NV2080_CTRL_FB_FS_INFO_PAC_MASK.
*/
typedef struct NV2080_CTRL_FB_FS_INFO_PAC_MASK_PARAMS {
/*!
* [IN]: physical/local FB partition index.
*/
NvU32 fbpIndex;
/*!
* [OUT]: physical/local PAC mask.
*/
NvU32 pacEnMask;
} NV2080_CTRL_FB_FS_INFO_PAC_MASK_PARAMS;
// Possible values for queryType
#define NV2080_CTRL_FB_FS_INFO_INVALID_QUERY 0x0U
#define NV2080_CTRL_FB_FS_INFO_FBP_MASK 0x1U
@@ -2308,6 +2391,8 @@ typedef struct NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_SUBP_MASK_PARAMS {
#define NV2080_CTRL_FB_FS_INFO_FBPA_SUBP_MASK 0xAU
#define NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_SUBP_MASK 0xBU
#define NV2080_CTRL_FB_FS_INFO_FBP_LOGICAL_MAP 0xCU
#define NV2080_CTRL_SYSL2_FS_INFO_SYSLTC_MASK 0xDU
#define NV2080_CTRL_FB_FS_INFO_PAC_MASK 0xEU
typedef struct NV2080_CTRL_FB_FS_INFO_QUERY {
NvU16 queryType;
@@ -2327,6 +2412,8 @@ typedef struct NV2080_CTRL_FB_FS_INFO_QUERY {
NV_DECLARE_ALIGNED(NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_SUBP_MASK_PARAMS dmFbpaSubp, 8);
NV2080_CTRL_FB_FS_INFO_FBPA_SUBP_MASK_PARAMS fbpaSubp;
NV2080_CTRL_FB_FS_INFO_FBP_LOGICAL_MAP_PARAMS fbpLogicalMap;
NV2080_CTRL_SYSL2_FS_INFO_SYSLTC_MASK_PARAMS sysl2Ltc;
NV2080_CTRL_FB_FS_INFO_PAC_MASK_PARAMS pac;
} queryParams;
} NV2080_CTRL_FB_FS_INFO_QUERY;

272
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080fifo.h
View File

@@ -30,6 +30,7 @@
// Source file: ctrl/ctrl2080/ctrl2080fifo.finn
//
#include "nvcfg_sdk.h"
#include "ctrl/ctrl2080/ctrl2080base.h"
/*
@@ -466,6 +467,94 @@ typedef struct NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION_PARAMS {
#define NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION_ATTRIBUTE_WRITECOMBINED 0X00000002
#define NV2080_CTRL_CMD_VGPU_SCHEDULER_POLICY_UNKNOWN 0
#define NV2080_CTRL_CMD_VGPU_SCHEDULER_POLICY_OTHER 1
#define NV2080_CTRL_CMD_VGPU_SCHEDULER_POLICY_BEST_EFFORT 2
#define NV2080_CTRL_CMD_VGPU_SCHEDULER_POLICY_EQUAL_SHARE 3
#define NV2080_CTRL_CMD_VGPU_SCHEDULER_POLICY_FIXED_SHARE 4
// Count of the supported vGPU scheduler policies
#define NV2080_CTRL_CMD_SUPPORTED_VGPU_SCHEDULER_POLICY_COUNT 3
#define NV2080_CTRL_CMD_VGPU_SCHEDULER_ARR_DEFAULT 0
#define NV2080_CTRL_CMD_VGPU_SCHEDULER_ARR_DISABLE 1
#define NV2080_CTRL_CMD_VGPU_SCHEDULER_ARR_ENABLE 2
/*
* NV2080_CTRL_CMD_FIFO_OBJSCHED_SW_GET_LOG
*
* This command returns the OBJSCHED_SW log enties.
*
* engineId
* This field specifies the NV2080_ENGINE_TYPE_* engine whose SW runlist log
* entries are to be fetched.
*
* count
* This field returns the count of log entries fetched.
*
* entry
* The array of SW runlist log entries.
*
* timestampNs
* Timestamp in ns when this SW runlist was preeempted.
*
* timeRunTotalNs
* Total time in ns this SW runlist has run as compared to others.
*
* timeRunNs
* Time in ns this SW runlist ran before preemption.
*
* swrlId
* SW runlist Id.
*
* schedPolicy
* This field returns the runlist scheduling policy. It specifies the
* NV2080_CTRL_CMD_VGPU_SCHEDULER_POLICY_* scheduling policy.
*
* arrEnabled
* This field returns if Adaptive round robin scheduler
* is enabled/disabled.
*
* arrAvgFactor
* This field returns the average factor to be used in compensating the timeslice
* for Adaptive scheduler mode.
*
* targetTimesliceNs
* This field returns the target timeslice duration in ns for each SW runlist
* as configured by the user or the default value otherwise.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
*/
#define NV2080_CTRL_CMD_FIFO_OBJSCHED_SW_GET_LOG (0x2080110e) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FIFO_INTERFACE_ID << 8) | NV2080_CTRL_FIFO_OBJSCHED_SW_GET_LOG_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_FIFO_OBJSCHED_SW_COUNT 32
#define NV2080_CTRL_FIFO_OBJSCHED_SW_NCOUNTERS 8
#define NV2080_CTRL_FIFO_OBJSCHED_SW_GET_LOG_ENTRIES 200
#define NV2080_CTRL_FIFO_OBJSCHED_SW_GET_LOG_PARAMS_MESSAGE_ID (0xEU)
typedef struct NV2080_CTRL_FIFO_OBJSCHED_SW_GET_LOG_PARAMS {
NvU32 engineId;
NvU32 count;
struct {
NV_DECLARE_ALIGNED(NvU64 timestampNs, 8);
NV_DECLARE_ALIGNED(NvS64 timeRunTotalNs, 8);
NvU32 timeRunNs;
NvU32 swrlId;
NvU32 targetTimeSlice;
NV_DECLARE_ALIGNED(NvU64 cumulativePreemptionTime, 8);
NV_DECLARE_ALIGNED(NvU64 counters[NV2080_CTRL_FIFO_OBJSCHED_SW_NCOUNTERS], 8);
} entry[NV2080_CTRL_FIFO_OBJSCHED_SW_GET_LOG_ENTRIES];
NvU32 schedPolicy;
NvU32 arrEnabled;
NvU32 arrAvgFactor;
NvU32 targetTimesliceNs;
} NV2080_CTRL_FIFO_OBJSCHED_SW_GET_LOG_PARAMS;
/*
* NV2080_CTRL_CMD_FIFO_GET_DEVICE_INFO_TABLE
@@ -783,6 +872,189 @@ typedef struct NV2080_CTRL_FIFO_GET_ALLOCATED_CHANNELS_PARAMS {
NvU32 bitMask[NV2080_CTRL_FIFO_GET_ALLOCATED_CHANNELS_MAX_CHANNELS / 32];
} NV2080_CTRL_FIFO_GET_ALLOCATED_CHANNELS_PARAMS;
/*
* NV2080_CTRL_CMD_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION
*
* This command will disable and preempt channels described in the
* list provided and mark them ready for key rotation.
* hClient <-> hChannel pairs should use the same index in the arrays.
*
* numChannels
* The number of valid entries in hChannelList array.
* hClientList
* An array of NvHandle listing the client handles
* hChannelList
* An array of NvHandle listing the channel handles
* to be stopped.
* bEnableAfterKeyRotation
* This determines if channel is enabled by RM after it completes key rotation.
* Possible status values returned are:
* NV_OK
* NVOS_INVALID_STATE
*/
#define NV2080_CTRL_CMD_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION (0x2080111a) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FIFO_INTERFACE_ID << 8) | NV2080_CTRL_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_MAX_ENTRIES (64)
#define NV2080_CTRL_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_PARAMS_MESSAGE_ID (0x1AU)
typedef struct NV2080_CTRL_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_PARAMS {
NvU32 numChannels;
NvHandle hClientList[NV2080_CTRL_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_MAX_ENTRIES];
NvHandle hChannelList[NV2080_CTRL_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_MAX_ENTRIES];
NvBool bEnableAfterKeyRotation;
} NV2080_CTRL_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_PARAMS;
/*
* NV2080_CTRL_CMD_FIFO_OBJSCHED_GET_STATE
*
* This command returns the vGPU schedular state.
*
* engineId
* This field specifies the NV2080_ENGINE_TYPE_* engine whose SW runlist log
* entries are to be fetched.
*
* schedPolicy
* This field returns the runlist scheduling policy. It specifies the
* NV2080_CTRL_CMD_VGPU_SCHEDULER_POLICY_* scheduling policy.
*
* arrEnabled
* This field returns if Adaptive round robin scheduler
* is enabled/disabled.
*
* targetTimesliceNs
* This field returns the target timeslice duration in ns for each SW runlist
* as configured by the user or the default value otherwise.
*
* arrAvgFactor
* This field returns the average factor to be used in compensating the timeslice
* for Adaptive scheduler mode.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
*/
#define NV2080_CTRL_CMD_FIFO_OBJSCHED_GET_STATE (0x20801120) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FIFO_INTERFACE_ID << 8) | NV2080_CTRL_FIFO_OBJSCHED_GET_STATE_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_FIFO_OBJSCHED_GET_STATE_PARAMS_MESSAGE_ID (0x20U)
typedef struct NV2080_CTRL_FIFO_OBJSCHED_GET_STATE_PARAMS {
NvU32 engineId;
NvU32 schedPolicy;
NvU32 arrEnabled;
NvU32 targetTimesliceNs;
NvU32 arrAvgFactor;
} NV2080_CTRL_FIFO_OBJSCHED_GET_STATE_PARAMS;
/*
* NV2080_CTRL_CMD_FIFO_OBJSCHED_SET_STATE
*
* This command set the vGPU schedular state.
*
* engineId
* This field specifies the NV2080_ENGINE_TYPE_* engine.
*
* schedPolicy
* This field sets the runlist scheduling policy. It specifies the
* NV2080_CTRL_CMD_VGPU_SCHEDULER_POLICY_* scheduling policy.
*
* enableArr
* This field sets the Adaptive round robin scheduler
* is enabled/disabled.
*
* timesliceTargetNs
* This field sets the time slice target time in ns.
*
* frequencyForARR
* This field sets the scheduling frequency for Adaptive round robin scheduler mode.
*
* avgFactorForARR
* This field sets the average factor to be used in compensating the timeslice
* for Adaptive scheduler mode.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_DEVICE
* NV_ERR_INVALID_STATE
* NV_ERR_NOT_SUPPORTED
* NV_ERR_INSUFFICIENT_PERMISSIONS
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_INVALID_PARAM_STRUCT
*/
#define NV2080_CTRL_CMD_FIFO_OBJSCHED_SET_STATE (0x20801121) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FIFO_INTERFACE_ID << 8) | NV2080_CTRL_FIFO_OBJSCHED_SET_STATE_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_FIFO_OBJSCHED_SET_STATE_PARAMS_MESSAGE_ID (0x21U)
typedef struct NV2080_CTRL_FIFO_OBJSCHED_SET_STATE_PARAMS {
NvU32 engineId;
NvU32 schedPolicy;
NvU32 enableArr;
NvU32 timesliceTargetNs;
NvU32 frequencyForARR;
NvU32 avgFactorForARR;
} NV2080_CTRL_FIFO_OBJSCHED_SET_STATE_PARAMS;
/*
* NV2080_CTRL_CMD_FIFO_OBJSCHED_GET_CAPS
*
* This command returns the vGPU schedular capabilities.
*
* engineId [in]
* This field specifies the NV2080_ENGINE_TYPE_* engine whose SW runlist log
* entries are to be fetched.
*
* supportedSchedulers [out]
* This field returns the supported runlist scheduling policies on the device.
* It specifies the NV2080_CTRL_CMD_VGPU_SCHEDULER_POLICY_* scheduling policy.
*
* bIsArrModeSupported [out]
* This field returns if Adaptive scheduler mode is enabled/disabled.
*
* maxTimesliceNs [out]
* This field returns the maximum time slice value in ns.
*
* minTimesliceNs [out]
* This field returns the minimum time slice value in ns.
*
* maxFrequencyForARR [out]
* This field returns the maximum scheduling frequency for
* Adaptive round robin scheduler mode.
*
* minFrequencyForARR [out]
* This field returns the minimum scheduling frequency for
* Adaptive round robin scheduler mode.
*
* maxAvgFactorForARR [out]
* This field returns the maximum average factor in compensating
* the timeslice for Adaptive scheduler mode.
*
* minAvgFactorForARR [out]
* This field returns the minimum average factor in compensating
* the timeslice for Adaptive scheduler mode.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
*/
#define NV2080_CTRL_CMD_FIFO_OBJSCHED_GET_CAPS (0x20801122) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FIFO_INTERFACE_ID << 8) | NV2080_CTRL_FIFO_OBJSCHED_GET_CAPS_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_FIFO_OBJSCHED_GET_CAPS_PARAMS_MESSAGE_ID (0x22U)
typedef struct NV2080_CTRL_FIFO_OBJSCHED_GET_CAPS_PARAMS {
NvU32 engineId;
NvU32 supportedSchedulers[NV2080_CTRL_CMD_SUPPORTED_VGPU_SCHEDULER_POLICY_COUNT];
NvBool bIsArrModeSupported;
NvU32 maxTimesliceNs;
NvU32 minTimesliceNs;
NvU32 maxFrequencyForARR;
NvU32 minFrequencyForARR;
NvU32 maxAvgFactorForARR;
NvU32 minAvgFactorForARR;
} NV2080_CTRL_FIFO_OBJSCHED_GET_CAPS_PARAMS;
/* _ctrl2080fifo_h_ */

1
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080flcn.h
View File

@@ -148,6 +148,7 @@ typedef struct NV2080_CTRL_FLCN_GET_ENGINE_ARCH_PARAMS {
#define NV2080_CTRL_FLCN_GET_ENGINE_ARCH_DEFAULT 0x0
#define NV2080_CTRL_FLCN_GET_ENGINE_ARCH_FALCON 0x1
#define NV2080_CTRL_FLCN_GET_ENGINE_ARCH_RISCV 0x2
#define NV2080_CTRL_FLCN_GET_ENGINE_ARCH_RISCV_EB 0x3
/*!@}*/

57
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080gpu.h
View File

@@ -748,7 +748,7 @@ typedef struct NV2080_CTRL_GPU_GET_ENGINES_PARAMS {
#define NV2080_CTRL_CMD_GPU_GET_ENGINES_V2 (0x20800170U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_ENGINES_V2_PARAMS_MESSAGE_ID" */
/* Must match NV2080_ENGINE_TYPE_LAST from cl2080.h */
#define NV2080_GPU_MAX_ENGINES_LIST_SIZE 0x3FU
#define NV2080_GPU_MAX_ENGINES_LIST_SIZE 0x40U
#define NV2080_CTRL_GPU_GET_ENGINES_V2_PARAMS_MESSAGE_ID (0x70U)
@@ -2518,6 +2518,8 @@ typedef struct NV2080_CTRL_GPU_PARTITION_SPAN {
NV_DECLARE_ALIGNED(NvU64 hi, 8);
} NV2080_CTRL_GPU_PARTITION_SPAN;
#define NV_GI_UUID_LEN 16U
/*
* NV2080_CTRL_GPU_SET_PARTITION_INFO
*
@@ -2538,6 +2540,9 @@ typedef struct NV2080_CTRL_GPU_PARTITION_SPAN {
* - PartitionID associated with a newly created partition. Input in case
* of partition invalidation.
*
* uuid[OUT]
* - Uuid of a newly created partition.
*
* partitionFlag[IN]
* - Flags to determine if GPU is requested to be partitioned in FULL,
* HALF, QUARTER or ONE_EIGHTHED and whether the partition requires
@@ -2566,6 +2571,7 @@ typedef struct NV2080_CTRL_GPU_PARTITION_SPAN {
*/
typedef struct NV2080_CTRL_GPU_SET_PARTITION_INFO {
NvU32 swizzId;
NvU8 uuid[NV_GI_UUID_LEN];
NvU32 partitionFlag;
NvBool bValid;
NV_DECLARE_ALIGNED(NV2080_CTRL_GPU_PARTITION_SPAN placement, 8);
@@ -3824,7 +3830,7 @@ typedef struct NV2080_CTRL_GPU_SET_EGM_GPA_FABRIC_BASE_ADDR_PARAMS {
*/
#define NV2080_CTRL_CMD_GPU_GET_ENGINE_LOAD_TIMES (0x2080019bU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_ENGINE_LOAD_TIMES_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_GPU_MAX_ENGINE_OBJECTS 0xC0U
#define NV2080_CTRL_GPU_MAX_ENGINE_OBJECTS 0xC8U
#define NV2080_CTRL_GPU_GET_ENGINE_LOAD_TIMES_PARAMS_MESSAGE_ID (0x9BU)
@@ -4038,8 +4044,15 @@ typedef struct NV2080_CTRL_GPU_GET_COMPUTE_PROFILES_PARAMS {
#define NV2080_CTRL_GPU_FABRIC_PROBE_CAP_MC_SUPPORTED NVBIT64(0)
#define NV2080_CTRL_GPU_FABRIC_PROBE_CAP_MC_MUTLINODE_SUPPORTED NVBIT64(1)
#define NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_DEGRADED_BW 1:0
#define NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_DEGRADED_BW_NOT_SUPPORTED 0
#define NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_DEGRADED_BW_TRUE 1
#define NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_DEGRADED_BW_FALSE 2
/*!
* NV2080_CTRL_CMD_GET_GPU_FABRIC_PROBE_INFO_PARAMS
*
@@ -4068,7 +4081,9 @@ typedef struct NV2080_CTRL_GPU_GET_COMPUTE_PROFILES_PARAMS {
* Possible values are
* NV2080_CTRL_GPU_FABRIC_PROBE_CAP_*
* fabricCliqueId[OUT]
* - Unique ID of a set of GPUs within a fabric partition that can perform P2P
* - Unique ID of a set of GPUs within a fabric partition that can perform P2P
* fabricHealthMask[OUT]
* - Mask where bits indicate different status about the health of the fabric
*/
#define NV2080_CTRL_CMD_GET_GPU_FABRIC_PROBE_INFO_PARAMS_MESSAGE_ID (0xA3U)
@@ -4079,6 +4094,7 @@ typedef struct NV2080_CTRL_CMD_GET_GPU_FABRIC_PROBE_INFO_PARAMS {
NvU16 fabricPartitionId;
NV_DECLARE_ALIGNED(NvU64 fabricCaps, 8);
NvU32 fabricCliqueId;
NvU32 fabricHealthMask;
} NV2080_CTRL_CMD_GET_GPU_FABRIC_PROBE_INFO_PARAMS;
#define NV2080_CTRL_CMD_GET_GPU_FABRIC_PROBE_INFO (0x208001a3) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_CMD_GET_GPU_FABRIC_PROBE_INFO_PARAMS_MESSAGE_ID" */
@@ -4284,4 +4300,39 @@ typedef struct NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO_V2_PARAMS {
#define NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO_V2 (0x208001afU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO_V2_PARAMS_MESSAGE_ID" */
typedef struct NV2080_CTRL_GPU_CONSTRUCTED_FALCON_INFO {
NvU32 engDesc;
NvU32 ctxAttr;
NvU32 ctxBufferSize;
NvU32 addrSpaceList;
NvU32 registerBase;
} NV2080_CTRL_GPU_CONSTRUCTED_FALCON_INFO;
#define NV2080_CTRL_GPU_MAX_CONSTRUCTED_FALCONS 0x40
#define NV2080_CTRL_CMD_GPU_GET_CONSTRUCTED_FALCON_INFO (0x208001b0) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_CONSTRUCTED_FALCON_INFO_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_GPU_GET_CONSTRUCTED_FALCON_INFO_PARAMS_MESSAGE_ID (0xB0U)
typedef struct NV2080_CTRL_GPU_GET_CONSTRUCTED_FALCON_INFO_PARAMS {
NvU32 numConstructedFalcons;
NV2080_CTRL_GPU_CONSTRUCTED_FALCON_INFO constructedFalconsTable[NV2080_CTRL_GPU_MAX_CONSTRUCTED_FALCONS];
} NV2080_CTRL_GPU_GET_CONSTRUCTED_FALCON_INFO_PARAMS;
/*
* NV2080_CTRL_GPU_GET_FIPS_STATUS
*
* @brief get FIPS status (enabled/disabled) from GSP-RM
*
*
* @return NV_OK on success
* @return NV_ERR_ otherwise
*/
#define NV2080_CTRL_GPU_GET_FIPS_STATUS_PARAMS_MESSAGE_ID (0xe4U)
typedef struct NV2080_CTRL_GPU_GET_FIPS_STATUS_PARAMS {
NvBool bFipsEnabled;
} NV2080_CTRL_GPU_GET_FIPS_STATUS_PARAMS;
#define NV2080_CTRL_GPU_GET_FIPS_STATUS (0x208001e4) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_FIPS_STATUS_PARAMS_MESSAGE_ID" */
/* _ctrl2080gpu_h_ */

37
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080gr.h
View File

@@ -622,6 +622,35 @@ typedef struct NV2080_CTRL_GR_CTXSW_PM_BIND_PARAMS {
} NV2080_CTRL_GR_CTXSW_PM_BIND_PARAMS;
/* valid pmMode values same as above NV2080_CTRL_CTXSW_PM_MODE */
/*
* NV2080_CTRL_CMD_GR_CTXSW_SETUP_BIND
*
* This command is used to set the Setup context switch mode and virtual address
* for the specified channel. A value of NV_ERR_NOT_SUPPORTED is
* returned if the target channel does not support setup context switch mode
* changes.
*
* hClient
* This parameter specifies the client handle of
* that owns the Setup context buffer. This field must match
* the hClient used in the control call for non-kernel clients.
* hChannel
* This parameter specifies the channel handle of
* the channel that is to have its Setup context switch mode changed.
* vMemPtr
* This parameter specifies the 64 bit virtual address
* for the allocated Setup context buffer.
*/
#define NV2080_CTRL_CMD_GR_CTXSW_SETUP_BIND (0x2080123aU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_CTXSW_SETUP_BIND_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_GR_CTXSW_SETUP_BIND_PARAMS_MESSAGE_ID (0x3AU)
typedef struct NV2080_CTRL_GR_CTXSW_SETUP_BIND_PARAMS {
NvHandle hClient;
NvHandle hChannel;
NV_DECLARE_ALIGNED(NvU64 vMemPtr, 8);
} NV2080_CTRL_GR_CTXSW_SETUP_BIND_PARAMS;
/*
* NV2080_CTRL_CMD_GR_SET_GPC_TILE_MAP
*
@@ -1067,10 +1096,10 @@ typedef struct NV2080_CTRL_GR_GET_CTX_BUFFER_INFO_PARAMS {
NV_DECLARE_ALIGNED(NV2080_CTRL_GR_CTX_BUFFER_INFO ctxBufferInfo[NV2080_CTRL_GR_MAX_CTX_BUFFER_COUNT], 8);
} NV2080_CTRL_GR_GET_CTX_BUFFER_INFO_PARAMS;
// Aperture flags
#define NV2080_CTRL_GR_CTX_BUFFER_INFO_APERTURE_UNKNWON ADDR_UNKNOWN
#define NV2080_CTRL_GR_CTX_BUFFER_INFO_APERTURE_SYSMEM ADDR_SYSMEM
#define NV2080_CTRL_GR_CTX_BUFFER_INFO_APERTURE_FBMEM ADDR_FBMEM
// Aperture flags. The defines should match the defines in mem_desc.h
#define NV2080_CTRL_GR_CTX_BUFFER_INFO_APERTURE_UNKNOWN 0
#define NV2080_CTRL_GR_CTX_BUFFER_INFO_APERTURE_SYSMEM 1
#define NV2080_CTRL_GR_CTX_BUFFER_INFO_APERTURE_FBMEM 2
/*
* NV2080_CTRL_CMD_GR_GET_GLOBAL_SM_ORDER

241
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080internal.h
View File

@@ -76,6 +76,9 @@ typedef struct NV2080_CTRL_INTERNAL_DISPLAY_GET_STATIC_INFO_PARAMS {
NvBool bPrimaryVga;
NvU32 i2cPort;
NvU32 internalDispActiveMask;
NvU32 embeddedDisplayPortMask;
NvBool bExternalMuxSupported;
NvBool bInternalMuxSupported;
} NV2080_CTRL_INTERNAL_DISPLAY_GET_STATIC_INFO_PARAMS;
@@ -112,8 +115,6 @@ typedef struct NV2080_CTRL_INTERNAL_MEMSYS_GET_STATIC_CONFIG_PARAMS {
/*! L2 cache size */
NV_DECLARE_ALIGNED(NvU64 l2CacheSize, 8);
NvBool bReservedMemAtBottom;
/*! Indicate whether fpba is present or not */
NvBool bFbpaPresent;
@@ -123,9 +124,6 @@ typedef struct NV2080_CTRL_INTERNAL_MEMSYS_GET_STATIC_CONFIG_PARAMS {
/*! log32(comprPageSize) */
NvU32 comprPageShift;
/*! Maximum number of pages that can be dynamaically blacklisted */
NvU16 maximumBlacklistPages;
/*! RAM type */
NvU32 ramType;
@@ -134,12 +132,6 @@ typedef struct NV2080_CTRL_INTERNAL_MEMSYS_GET_STATIC_CONFIG_PARAMS {
/*! LTS per LTC count */
NvU32 ltsPerLtcCount;
/*! Ampere PLC bug */
NvBool bDisablePlcForCertainOffsetsBug3046774;
/*! FB override Start KB */
NV_DECLARE_ALIGNED(NvU64 fbOverrideStartKb, 8);
} NV2080_CTRL_INTERNAL_MEMSYS_GET_STATIC_CONFIG_PARAMS;
/*!
@@ -294,7 +286,7 @@ typedef struct NV2080_CTRL_INTERNAL_BSP_GET_CAPS_PARAMS {
*/
#define NV2080_CTRL_CMD_INTERNAL_MSENC_GET_CAPS (0x20800a25) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MSENC_GET_CAPS_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_CMD_INTERNAL_MAX_MSENCS 3
#define NV2080_CTRL_CMD_INTERNAL_MAX_MSENCS 8
typedef struct NV2080_CTRL_INTERNAL_MSENC_CAPS {
NvU8 capsTbl[NV0080_CTRL_MSENC_CAPS_TBL_SIZE];
@@ -558,7 +550,7 @@ typedef NV2080_CTRL_INTERNAL_STATIC_GR_GET_PPC_MASKS_PARAMS NV2080_CTRL_INTERNAL
#define NV2080_CTRL_INTERNAL_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_COUNT 0x19
#define NV2080_CTRL_INTERNAL_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_COUNT 0x1a
typedef struct NV2080_CTRL_INTERNAL_ENGINE_CONTEXT_BUFFER_INFO {
NvU32 size;
@@ -631,7 +623,6 @@ typedef struct NV2080_CTRL_INTERNAL_GPU_GET_CHIP_INFO_PARAMS {
NvU8 chipSubRev;
NvU32 emulationRev1;
NvBool isCmpSku;
NvU32 bar1Size;
NvU32 pciDeviceId;
NvU32 pciSubDeviceId;
NvU32 pciRevisionId;
@@ -805,7 +796,7 @@ typedef struct NV2080_CTRL_INTERNAL_DEVICE_INFO {
NvU32 runlistPriBase;
NvU32 groupId;
} NV2080_CTRL_INTERNAL_DEVICE_INFO;
#define NV2080_CTRL_CMD_INTERNAL_DEVICE_INFO_MAX_ENTRIES 88
#define NV2080_CTRL_CMD_INTERNAL_DEVICE_INFO_MAX_ENTRIES 256
#define NV2080_CTRL_CMD_INTERNAL_GET_DEVICE_INFO_TABLE (0x20800a40) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GET_DEVICE_INFO_TABLE_PARAMS_MESSAGE_ID" */
@@ -831,24 +822,6 @@ typedef struct NV2080_CTRL_INTERNAL_GPU_GET_USER_REGISTER_ACCESS_MAP_PARAMS {
NvU8 profilingRanges[NV2080_CTRL_INTERNAL_GPU_USER_REGISTER_ACCESS_MAP_MAX_PROFILING_RANGES];
} NV2080_CTRL_INTERNAL_GPU_GET_USER_REGISTER_ACCESS_MAP_PARAMS;
typedef struct NV2080_CTRL_INTERNAL_CONSTRUCTED_FALCON_INFO {
NvU32 engDesc;
NvU32 ctxAttr;
NvU32 ctxBufferSize;
NvU32 addrSpaceList;
NvU32 registerBase;
} NV2080_CTRL_INTERNAL_CONSTRUCTED_FALCON_INFO;
#define NV2080_CTRL_CMD_INTERNAL_MAX_CONSTRUCTED_FALCONS 0x40
#define NV2080_CTRL_CMD_INTERNAL_GET_CONSTRUCTED_FALCON_INFO (0x20800a42) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GET_CONSTRUCTED_FALCON_INFO_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_INTERNAL_GET_CONSTRUCTED_FALCON_INFO_PARAMS_MESSAGE_ID (0x42U)
typedef struct NV2080_CTRL_INTERNAL_GET_CONSTRUCTED_FALCON_INFO_PARAMS {
NvU32 numConstructedFalcons;
NV2080_CTRL_INTERNAL_CONSTRUCTED_FALCON_INFO constructedFalconsTable[NV2080_CTRL_CMD_INTERNAL_MAX_CONSTRUCTED_FALCONS];
} NV2080_CTRL_INTERNAL_GET_CONSTRUCTED_FALCON_INFO_PARAMS;
/**
* Get GR PDB properties synchronized between Kernel and Physical
*
@@ -858,6 +831,37 @@ typedef struct NV2080_CTRL_INTERNAL_GET_CONSTRUCTED_FALCON_INFO_PARAMS {
typedef struct NV2080_CTRL_INTERNAL_NV_RANGE {
NV_DECLARE_ALIGNED(NvU64 lo, 8);
NV_DECLARE_ALIGNED(NvU64 hi, 8);
} NV2080_CTRL_INTERNAL_NV_RANGE;
/*!
* NV2080_CTRL_INTERNAL_MIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS
*
* This structure specifies a target swizz-id and mem_range to update
*
* swizzId[IN]
* - Targeted swizz-id for which the memRange is being set
*
* memAddrRange[IN]
* - Memory Range for given GPU instance
*/
#define NV2080_CTRL_INTERNAL_MIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS_MESSAGE_ID (0x43U)
typedef struct NV2080_CTRL_INTERNAL_MIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS {
NvU32 swizzId;
NV_DECLARE_ALIGNED(NV2080_CTRL_INTERNAL_NV_RANGE memAddrRange, 8);
} NV2080_CTRL_INTERNAL_MIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS;
#define NV2080_CTRL_CMD_INTERNAL_KMIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE (0x20800a44) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_KMIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_INTERNAL_KMIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS_MESSAGE_ID (0x44U)
typedef NV2080_CTRL_INTERNAL_MIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS NV2080_CTRL_INTERNAL_KMIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS;
#define NV2080_CTRL_CMD_INTERNAL_MIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE (0x20800a43) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS_MESSAGE_ID" */
typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_PDB_PROPERTIES {
NvBool bPerSubCtxheaderSupported;
} NV2080_CTRL_INTERNAL_STATIC_GR_PDB_PROPERTIES;
@@ -1029,7 +1033,7 @@ typedef struct NV2080_CTRL_INTERNAL_DISPLAY_SETUP_RG_LINE_INTR_PARAMS {
* validGfxCTSIdMask [OUT]
* # mask of CTS IDs that contain Gfx capable Grs which can be assigned under this profile
*/
#define NV2080_CTRL_INTERNAL_GRMGR_PARTITION_MAX_TYPES 20
#define NV2080_CTRL_INTERNAL_GRMGR_PARTITION_MAX_TYPES 60
@@ -1104,10 +1108,12 @@ typedef struct NV2080_CTRL_INTERNAL_MEMSYS_SET_PARTITIONABLE_MEM_PARAMS {
#define NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PARTITIONABLE_ENGINES_MAX_ENGINES_MASK_SIZE 4
#define NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PARTITIONABLE_ENGINES_PARAMS_MESSAGE_ID (0x52U)
typedef struct NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PARTITIONABLE_ENGINES_PARAMS {
NV_DECLARE_ALIGNED(NvU64 engineMask, 8);
NV_DECLARE_ALIGNED(NvU64 engineMask[NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PARTITIONABLE_ENGINES_MAX_ENGINES_MASK_SIZE], 8);
} NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PARTITIONABLE_ENGINES_PARAMS;
#define NV2080_CTRL_INTERNAL_FIFO_MAX_RUNLIST_BUFFERS 2
@@ -1142,6 +1148,23 @@ typedef struct NV2080_CTRL_INTERNAL_DISPLAY_SET_IMP_INIT_INFO_PARAMS {
TEGRA_IMP_IMPORT_DATA tegraImpImportData;
} NV2080_CTRL_INTERNAL_DISPLAY_SET_IMP_INIT_INFO_PARAMS;
#define NV2080_CTRL_CMD_INTERNAL_GET_EGPU_BRIDGE_INFO (0x20800a55) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GET_EGPU_BRIDGE_INFO_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_INTERNAL_GET_EGPU_BRIDGE_INFO_PARAMS_MESSAGE_ID (0x55U)
typedef struct NV2080_CTRL_INTERNAL_GET_EGPU_BRIDGE_INFO_PARAMS {
NvU16 pciDeviceId;
NvU16 pciSubDeviceId;
NvBool iseGPUBridge;
NvU8 approvedBusType;
} NV2080_CTRL_INTERNAL_GET_EGPU_BRIDGE_INFO_PARAMS;
#define NV2080_CTRL_INTERNAL_EGPU_BUS_TYPE_NONE (0x00000000)
#define NV2080_CTRL_INTERNAL_EGPU_BUS_TYPE_CUSTOM (0x00000001)
#define NV2080_CTRL_INTERNAL_EGPU_BUS_TYPE_TB2 (0x00000002)
#define NV2080_CTRL_INTERNAL_EGPU_BUS_TYPE_TB3 (0x00000003)
/*!
* NV2080_CTRL_CMD_INTERNAL_BUS_FLUSH_WITH_SYSMEMBAR
*
@@ -1357,6 +1380,9 @@ typedef struct NV2080_CTRL_INTERNAL_VMMU_GET_SPA_FOR_GPA_ENTRIES_PARAMS {
* valid [IN]
* This bit indicates whether pushbuffer parameters are valid or not
*
* pbTargetAperture [IN]
* Indicates the PushBuffer Target Aperture type (IOVA, PCI, PCI_COHERENT or NVM)
*
*/
#define NV2080_CTRL_CMD_INTERNAL_DISPLAY_CHANNEL_PUSHBUFFER (0x20800a58) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_DISPLAY_CHANNEL_PUSHBUFFER_PARAMS_MESSAGE_ID" */
@@ -1370,6 +1396,7 @@ typedef struct NV2080_CTRL_INTERNAL_DISPLAY_CHANNEL_PUSHBUFFER_PARAMS {
NvU32 hclass;
NvU32 channelInstance;
NvBool valid;
NvU32 pbTargetAperture;
} NV2080_CTRL_INTERNAL_DISPLAY_CHANNEL_PUSHBUFFER_PARAMS;
/*!
@@ -1556,11 +1583,6 @@ typedef struct NV2080_CTRL_INTERNAL_DISPLAY_GET_ACTIVE_DISPLAY_DEVICES_PARAMS {
#define NV2080_CTRL_INTERNAL_MAX_SWIZZ_ID 15
typedef struct NV2080_CTRL_INTERNAL_NV_RANGE {
NV_DECLARE_ALIGNED(NvU64 lo, 8);
NV_DECLARE_ALIGNED(NvU64 hi, 8);
} NV2080_CTRL_INTERNAL_NV_RANGE;
#define NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES_PARAMS_MESSAGE_ID (0x60U)
typedef struct NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES_PARAMS {
@@ -2127,6 +2149,7 @@ typedef struct NV2080_CTRL_INTERNAL_KMIGMGR_EXPORTED_GPU_INSTANCE_INFO {
typedef struct NV2080_CTRL_INTERNAL_KMIGMGR_IMPORT_EXPORT_GPU_INSTANCE_PARAMS {
NvU32 swizzId;
NvU8 uuid[NV_GI_UUID_LEN];
NV_DECLARE_ALIGNED(NV2080_CTRL_INTERNAL_KMIGMGR_EXPORTED_GPU_INSTANCE_INFO info, 8);
} NV2080_CTRL_INTERNAL_KMIGMGR_IMPORT_EXPORT_GPU_INSTANCE_PARAMS;
@@ -2610,54 +2633,55 @@ typedef struct NV2080_CTRL_INTERNAL_BIF_SET_PCIE_RO_PARAMS {
} NV2080_CTRL_INTERNAL_BIF_SET_PCIE_RO_PARAMS;
/*
* NV2080_CTRL_CMD_INTERNAL_DISPLAY_UNIX_CONSOLE
* NV2080_CTRL_CMD_INTERNAL_DISPLAY_PRE_UNIX_CONSOLE
*
* An internal call to invoke the sequence VGA register reads & writes to
* perform save and restore of VGA
*
* [in] saveOrRestore
* [in] bSave
* To indicate whether save or restore needs to be performed.
* [in] useVbios
* [in] bUseVbios
* Primary VGA indication from OS.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_GENERIC
* NV_ERR_INVALID_OPERATION
* NV_ERR_NOT_SUPPORTED
*/
#define NV2080_CTRL_CMD_INTERNAL_DISPLAY_UNIX_CONSOLE (0x20800a76) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_DISPLAY_UNIX_CONSOLE_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_CMD_INTERNAL_DISPLAY_PRE_UNIX_CONSOLE (0x20800a76) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_DISPLAY_PRE_UNIX_CONSOLE_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_CMD_INTERNAL_DISPLAY_UNIX_CONSOLE_PARAMS_MESSAGE_ID (0x76U)
#define NV2080_CTRL_CMD_INTERNAL_DISPLAY_PRE_UNIX_CONSOLE_PARAMS_MESSAGE_ID (0x76U)
typedef struct NV2080_CTRL_CMD_INTERNAL_DISPLAY_UNIX_CONSOLE_PARAMS {
NvBool bSaveOrRestore;
typedef struct NV2080_CTRL_CMD_INTERNAL_DISPLAY_PRE_UNIX_CONSOLE_PARAMS {
NvBool bSave;
NvBool bUseVbios;
} NV2080_CTRL_CMD_INTERNAL_DISPLAY_UNIX_CONSOLE_PARAMS;
} NV2080_CTRL_CMD_INTERNAL_DISPLAY_PRE_UNIX_CONSOLE_PARAMS;
/*!
* NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_RESTORE
* NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_UNIX_CONSOLE
*
* To perform restore operation from saved fonts.
* To perform save or restore operation from/to saved fonts.
*
* [in] saveOrRestore
* [in] bSave
* To indicate whether save or restore needs to be performed.
* [in] useVbios
* [in] bUseVbios
* Primary VGA indication from OS.
* [in] bVbiosCallSuccessful
* Indicates if vbios invocation was successful or not.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_GENERIC
* NV_ERR_NOT_SUPPORTED
*/
#define NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_RESTORE (0x20800a77) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_RESTORE_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_UNIX_CONSOLE (0x20800a77) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_UNIX_CONSOLE_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_RESTORE_PARAMS_MESSAGE_ID (0x77U)
#define NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_UNIX_CONSOLE_PARAMS_MESSAGE_ID (0x77U)
typedef struct NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_RESTORE_PARAMS {
NvBool bWriteCr;
} NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_RESTORE_PARAMS;
typedef struct NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_UNIX_CONSOLE_PARAMS {
NvBool bSave;
NvBool bUseVbios;
NvBool bVbiosCallSuccessful;
} NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_UNIX_CONSOLE_PARAMS;
/*!
* @ref NV2080_CTRL_CMD_INTERNAL_STATIC_MIGMGR_GET_COMPUTE_PROFILES
@@ -3683,22 +3707,6 @@ typedef struct NV2080_CTRL_INTERNAL_CONF_COMPUTE_GET_STATIC_INFO_PARAMS {
NvBool bIsPcieTrusted;
} NV2080_CTRL_INTERNAL_CONF_COMPUTE_GET_STATIC_INFO_PARAMS;
/*!
* NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_ENCRYPTION_CONTROL
*
* This command is used to trigger the initialization / suspension of encrypted RPCs for Confidential Compute.
* bEncryptionControl : [IN]
* NV_TRUE indicates initialization.
* NV_FALSE indicates suspension.
*/
#define NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_ENCRYPTION_CONTROL (0x208001b2) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_ENCRYPTION_CONTROL_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_ENCRYPTION_CONTROL_PARAMS_MESSAGE_ID (0xB2U)
typedef struct NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_ENCRYPTION_CONTROL_PARAMS {
NvBool bEncryptionControl;
} NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_ENCRYPTION_CONTROL_PARAMS;
/*!
* NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_DERIVE_SWL_KEYS
*
@@ -3749,6 +3757,25 @@ typedef struct NV2080_CTRL_INTERNAL_CONF_COMPUTE_DERIVE_LCE_KEYS_PARAMS {
NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK ivMaskSet[NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK_LCE_COUNT];
} NV2080_CTRL_INTERNAL_CONF_COMPUTE_DERIVE_LCE_KEYS_PARAMS;
/*!
* NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_SET_GPU_STATE
*
* This control call can be used to set gpu state on GSP to accept client requests
* or to block client requests.
* This is a internal command sent from Kernel RM to Physical RM.
*
* bAcceptClientRequest:[IN]
* NV_TRUE : set gpu state to accept client work requests
* NV_FALSE: set gpu state to block client work requests
*
*/
#define NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_SET_GPU_STATE (0x20800ae7) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_SET_GPU_STATE_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_SET_GPU_STATE_PARAMS_MESSAGE_ID (0xE7U)
typedef struct NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_SET_GPU_STATE_PARAMS {
NvBool bAcceptClientRequest;
} NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_SET_GPU_STATE_PARAMS;
/*
@@ -3960,4 +3987,64 @@ typedef struct NV2080_CTRL_INTERNAL_USER_SHARED_DATA_SET_DATA_POLL_PARAMS {
} NV2080_CTRL_INTERNAL_USER_SHARED_DATA_SET_DATA_POLL_PARAMS;
#define NV2080_CTRL_CMD_INTERNAL_USER_SHARED_DATA_SET_DATA_POLL (0x20800aff) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_USER_SHARED_DATA_SET_DATA_POLL_PARAMS_MESSAGE_ID" */
/*!
* NV2080_CTRL_CMD_INTERNAL_GSP_START_TRACE_INFO_PARAMS
*
* This structure provides the params for starting GPU Fabric Probe
*
* tracepointMask[IN]
* - tracepoint selection filter
* bufferSize[IN]
* - size of gsp side logging buffer
* bufferWatermark[IN]
* - entry threshold for GSP to issue RPC of logged entries to kernel RM
* bStart[IN]
* - if true, start tracing. if false, stop tracing.
*/
#define NV2080_CTRL_CMD_INTERNAL_GSP_START_TRACE_INFO_PARAMS_MESSAGE_ID (0xE3U)
typedef struct NV2080_CTRL_CMD_INTERNAL_GSP_START_TRACE_INFO_PARAMS {
NV_DECLARE_ALIGNED(NvU64 tracepointMask, 8);
NvU32 bufferSize;
NvU32 bufferWatermark;
NvBool bStart;
} NV2080_CTRL_CMD_INTERNAL_GSP_START_TRACE_INFO_PARAMS;
/*
* NV2080_CTRL_CMD_INTERNAL_GSP_START_TRACE
*
* This command is used to start GSP-RM trace tool.
* This command accepts NV2080_CTRL_CMD_INTERNAL_GSP_START_TRACE_INFO_PARAMS
*
*/
#define NV2080_CTRL_CMD_INTERNAL_GSP_START_TRACE (0x208001e3) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_GSP_START_TRACE_INFO_PARAMS_MESSAGE_ID" */
/*
* NV2080_CTRL_CMD_INTERNAL_GET_ENABLED_SEC2_CLASSES
*
* @brief get state (enabled/disabled) of SEC2 classes
*
*
* @return NV_OK on success
* @return NV_ERR_ otherwise
*/
#define NV2080_CTRL_CMD_INTERNAL_GET_ENABLED_SEC2_CLASSES_PARAMS_MESSAGE_ID (0xAFU)
typedef struct NV2080_CTRL_CMD_INTERNAL_GET_ENABLED_SEC2_CLASSES_PARAMS {
NvBool bMaxwellSec2Enabled;
NvBool bNv95A1TsecEnabled;
NvBool bHopperSec2WorkLaunchAEnabled;
} NV2080_CTRL_CMD_INTERNAL_GET_ENABLED_SEC2_CLASSES_PARAMS;
#define NV2080_CTRL_CMD_INTERNAL_GET_ENABLED_SEC2_CLASSES (0x20800aaf) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_GET_ENABLED_SEC2_CLASSES_PARAMS_MESSAGE_ID" */
/*!
* @ref NV2080_CTRL_CMD_INTERNAL_GR_CTXSW_SETUP_BIND
*/
#define NV2080_CTRL_CMD_INTERNAL_GR_CTXSW_SETUP_BIND (0x20800ae4) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GR_CTXSW_SETUP_BIND_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_INTERNAL_GR_CTXSW_SETUP_BIND_PARAMS_MESSAGE_ID (0xE4U)
typedef NV2080_CTRL_GR_CTXSW_SETUP_BIND_PARAMS NV2080_CTRL_INTERNAL_GR_CTXSW_SETUP_BIND_PARAMS;
/* ctrl2080internal_h */

152
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080nvd.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2004-2015 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2004-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -209,44 +209,61 @@ typedef struct NV2080_NOCAT_JOURNAL_RECORD {
// NOCAT activity counter indexes
// collection activity
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_COLLECT_REQ_IDX 0
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_ALLOCATED_IDX 1
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_COLLECTED_IDX 2
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_ALLOC_FAILED_IDX 3
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_COLLECT_FAILED_IDX 4
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_COLLECT_REQ_DROPPED_IDX 5
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_COLLECT_REQ_IDX 0
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_GRANDFATHERED_RECORD_IDX 1
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_ALLOCATED_IDX 2
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_COLLECTED_IDX 3
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_NOTIFICATIONS_IDX 4
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_ALLOC_FAILED_IDX 5
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_COLLECT_FAILED_IDX 6
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_COLLECT_LOCKED_OUT_IDX 7
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_CTRL_INSERT_RECORDS_IDX 8
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_RPC_INSERT_RECORDS_IDX 9
// Journal Lock activity
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_JOURNAL_LOCKED_IDX 10
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_JOURNAL_LOCK_UPDATED_IDX 11
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_JOURNAL_UNLOCKED_IDX 12
// lookup activity
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_NO_RECORDS_IDX 13
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_BAD_BUFFER_IDX 14
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_MATCH_FOUND_IDX 15
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_NO_MATCH_IDX 16
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_CLOSEST_FOUND_IDX 17
// reporting activity
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_REQUESTED_IDX 6
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_REPORTED_IDX 7
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_DROPPED_IDX 8
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_MISSED_IDX 9
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_REQUESTED_IDX 18
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_REPORTED_IDX 19
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_DROPPED_IDX 20
// update activity
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_UPDATE_REQ_IDX 10
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_UPDATED_IDX 11
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_UPDATE_FAILED_IDX 12
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_UPDATE_REQ_IDX 21
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_UPDATED_IDX 22
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_UPDATE_FAILED_IDX 23
// general errors
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_BUSY_IDX 13
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_BAD_PARAM_IDX 14
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_BAD_TYPE_IDX 15
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_BUSY_IDX 24
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_BAD_PARAM_IDX 25
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_BAD_TYPE_IDX 26
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_RES1_IDX 16
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_RES2_IDX 17
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_CACHE_UPDATE_IDX 18
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_INSERT_RECORDS_IDX 19
// reserved entries for temporary use.
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_RES5_IDX 27
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_RES4_IDX 28
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_RES3_IDX 29
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_RES2_IDX 30
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_RES1_IDX 31
// this should be relative to the highest counter index
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_COUNTER_COUNT (0x14) /* finn: Evaluated from "NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_INSERT_RECORDS_IDX + 1" */
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_COUNTER_COUNT (0x20) /* finn: Evaluated from "NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_RES1_IDX + 1" */
#define NV2080_CTRL_NOCAT_GET_COUNTERS_ONLY 0:0
#define NV2080_CTRL_NOCAT_GET_COUNTERS_ONLY_YES 1
#define NV2080_CTRL_NOCAT_GET_COUNTERS_ONLY_NO 0
#define NV2080_CTRL_NOCAT_GET_COUNTERS_ONLY_YES 1
#define NV2080_CTRL_NOCAT_GET_COUNTERS_ONLY_NO 0
#define NV2080_CTRL_NOCAT_GET_RESET_COUNTERS 1:1
#define NV2080_CTRL_NOCAT_GET_RESET_COUNTERS_YES 1
#define NV2080_CTRL_NOCAT_GET_RESET_COUNTERS_NO 0
#define NV2080_CTRL_NOCAT_GET_RESET_COUNTERS_YES 1
#define NV2080_CTRL_NOCAT_GET_RESET_COUNTERS_NO 0
#define NV2080_CTRL_NVD_GET_NOCAT_JOURNAL_PARAMS_MESSAGE_ID (0x9U)
@@ -266,7 +283,7 @@ typedef struct NV2080_CTRL_NVD_GET_NOCAT_JOURNAL_PARAMS {
* This command reports the TDR data collected by KMD to be added to the
* nocat record
*
* dataType:
* dataType
* [IN] specifies the type of data provided.
* targetRecordType
* [IN] specifies record type the data is intended for.
@@ -274,23 +291,22 @@ typedef struct NV2080_CTRL_NVD_GET_NOCAT_JOURNAL_PARAMS {
* [IN] specifies the data to be added.
*/
#define NV2080_CTRL_CMD_NVD_SET_NOCAT_JOURNAL_DATA (0x2080240b) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVD_INTERFACE_ID << 8) | NV2080_CTRL_NVD_SET_NOCAT_JOURNAL_DATA_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_CMD_NVD_SET_NOCAT_JOURNAL_DATA (0x2080240b) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVD_INTERFACE_ID << 8) | NV2080_CTRL_NVD_SET_NOCAT_JOURNAL_DATA_PARAMS_MESSAGE_ID" */
// data types & structures
#define NV2080_CTRL_NOCAT_JOURNAL_DATA_TYPE_EMPTY 0
#define NV2080_CTRL_NOCAT_JOURNAL_DATA_TYPE_TDR_REASON 1
#define NV2080_CTRL_NOCAT_JOURNAL_DATA_TYPE_INSERT_RECORD 2
#define NV2080_CTRL_NOCAT_JOURNAL_DATA_TYPE_SET_TAG 3
#define NV2080_CTRL_NOCAT_JOURNAL_DATA_TYPE_RCLOG 4
#define NV2080_CTRL_NOCAT_JOURNAL_DATA_TYPE_EMPTY 0
#define NV2080_CTRL_NOCAT_JOURNAL_DATA_TYPE_TDR_REASON 1
#define NV2080_CTRL_NOCAT_JOURNAL_DATA_TYPE_SET_TAG 2
#define NV2080_CTRL_NOCAT_JOURNAL_DATA_TYPE_RCLOG 3
#define NV2080_CTRL_NOCAT_TDR_TYPE_NONE 0
#define NV2080_CTRL_NOCAT_TDR_TYPE_LEGACY 1
#define NV2080_CTRL_NOCAT_TDR_TYPE_FULLCHIP 2
#define NV2080_CTRL_NOCAT_TDR_TYPE_BUSRESET 3
#define NV2080_CTRL_NOCAT_TDR_TYPE_GC6_RESET 4
#define NV2080_CTRL_NOCAT_TDR_TYPE_SURPRISE_REMOVAL 5
#define NV2080_CTRL_NOCAT_TDR_TYPE_UCODE_RESET 6
#define NV2080_CTRL_NOCAT_TDR_TYPE_TEST 7
#define NV2080_CTRL_NOCAT_TDR_TYPE_NONE 0
#define NV2080_CTRL_NOCAT_TDR_TYPE_LEGACY 1
#define NV2080_CTRL_NOCAT_TDR_TYPE_FULLCHIP 2
#define NV2080_CTRL_NOCAT_TDR_TYPE_BUSRESET 3
#define NV2080_CTRL_NOCAT_TDR_TYPE_GC6_RESET 4
#define NV2080_CTRL_NOCAT_TDR_TYPE_SURPRISE_REMOVAL 5
#define NV2080_CTRL_NOCAT_TDR_TYPE_UCODE_RESET 6
#define NV2080_CTRL_NOCAT_TDR_TYPE_TEST 7
typedef struct NV2080CtrlNocatJournalDataTdrReason {
NvU32 flags;
@@ -300,23 +316,6 @@ typedef struct NV2080CtrlNocatJournalDataTdrReason {
NvU32 reasonCode;
} NV2080CtrlNocatJournalDataTdrReason;
#define NV2080_CTRL_NOCAT_INSERT_ALLOW_NULL_STR 0:0
#define NV2080_CTRL_NOCAT_INSERT_ALLOW_NULL_STR_YES 1
#define NV2080_CTRL_NOCAT_INSERT_ALLOW_NULL_STR_NO 0
#define NV2080_CTRL_NOCAT_INSERT_ALLOW_0_LEN_BUFFER 1:1
#define NV2080_CTRL_NOCAT_INSERT_ALLOW_0_LEN_BUFFER_YES 1
#define NV2080_CTRL_NOCAT_INSERT_ALLOW_0_LEN_BUFFER_NO 0
typedef struct NV2080CtrlNocatJournalInsertRecord {
NvU32 flags;
NvU8 recType;
NvU32 bugcheck;
NvU8 source[NV2080_NOCAT_JOURNAL_MAX_STR_LEN];
NvU32 subsystem;
NV_DECLARE_ALIGNED(NvU64 errorCode, 8);
NvU8 faultingEngine[NV2080_NOCAT_JOURNAL_MAX_STR_LEN];
NvU32 tdrReason;
} NV2080CtrlNocatJournalInsertRecord;
#define NV2080_CTRL_NOCAT_TAG_CLEAR 0:0
#define NV2080_CTRL_NOCAT_TAG_CLEAR_YES 1
#define NV2080_CTRL_NOCAT_TAG_CLEAR_NO 0
@@ -342,9 +341,44 @@ typedef struct NV2080_CTRL_NVD_SET_NOCAT_JOURNAL_DATA_PARAMS {
NvU32 targetRecordType;
union {
NV_DECLARE_ALIGNED(NV2080CtrlNocatJournalDataTdrReason tdrReason, 8);
NV_DECLARE_ALIGNED(NV2080CtrlNocatJournalInsertRecord insertData, 8);
NV2080CtrlNocatJournalSetTag tagData;
NV2080CtrlNocatJournalRclog rclog;
} nocatJournalData;
} NV2080_CTRL_NVD_SET_NOCAT_JOURNAL_DATA_PARAMS;
/*
* NV2080_CTRL_CMD_NVD_INSERT_NOCAT_JOURNAL_RECORD
*
* This command Inserts a NOCAT Journal record from an outside component.
*
* nocatJournalData
* [IN] specifies the data to be added.
*/
#define NV2080_CTRL_CMD_NVD_INSERT_NOCAT_JOURNAL_RECORD (0x2080240c) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVD_INTERFACE_ID << 8) | NV2080_CTRL_CMD_NVD_INSERT_NOCAT_JOURNAL_RECORD_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_NOCAT_INSERT_ALLOW_NULL_STR 0:0
#define NV2080_CTRL_NOCAT_INSERT_ALLOW_NULL_STR_YES 1
#define NV2080_CTRL_NOCAT_INSERT_ALLOW_NULL_STR_NO 0
#define NV2080_CTRL_NOCAT_INSERT_ALLOW_0_LEN_BUFFER 1:1
#define NV2080_CTRL_NOCAT_INSERT_ALLOW_0_LEN_BUFFER_YES 1
#define NV2080_CTRL_NOCAT_INSERT_ALLOW_0_LEN_BUFFER_NO 0
typedef struct NV2080CtrlNocatJournalInsertRecord {
NvU32 flags;
NV_DECLARE_ALIGNED(NvU64 timestamp, 8);
NvU8 recType;
NvU32 bugcheck;
char source[NV2080_NOCAT_JOURNAL_MAX_STR_LEN];
NvU32 subsystem;
NV_DECLARE_ALIGNED(NvU64 errorCode, 8);
char faultingEngine[NV2080_NOCAT_JOURNAL_MAX_STR_LEN];
NvU32 tdrReason;
NvU32 diagBufferLen;
NvU8 diagBuffer[NV2080_NOCAT_JOURNAL_MAX_DIAG_BUFFER];
} NV2080CtrlNocatJournalInsertRecord;
#define NV2080_CTRL_CMD_NVD_INSERT_NOCAT_JOURNAL_RECORD_PARAMS_MESSAGE_ID (0xCU)
typedef struct NV2080_CTRL_CMD_NVD_INSERT_NOCAT_JOURNAL_RECORD_PARAMS {
NV_DECLARE_ALIGNED(NV2080CtrlNocatJournalInsertRecord nocatJournalRecord, 8);
} NV2080_CTRL_CMD_NVD_INSERT_NOCAT_JOURNAL_RECORD_PARAMS;
/* _ctr2080nvd_h_ */

67
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080nvlink.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2014-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2014-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -31,6 +31,7 @@
//
#include "ctrl/ctrl2080/ctrl2080base.h"
#include "nvcfg_sdk.h"
/* NV20_SUBDEVICE_XX bus control commands and parameters */
@@ -809,6 +810,8 @@ typedef struct NV2080_CTRL_NVLINK_CLEAR_COUNTERS_PARAMS {
NV_DECLARE_ALIGNED(NvU64 linkMask, 8);
} NV2080_CTRL_NVLINK_CLEAR_COUNTERS_PARAMS;
/*
* NV2080_CTRL_CMD_NVLINK_INJECT_ERROR
* This command causes all the same actions to occur as if the related
@@ -820,7 +823,7 @@ typedef struct NV2080_CTRL_NVLINK_CLEAR_COUNTERS_PARAMS {
* This parameter specifies that the error should be fatal.
*
*/
#define NV2080_CTRL_CMD_NVLINK_INJECT_ERROR (0x20803006U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_INJECT_ERROR_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_CMD_NVLINK_INJECT_ERROR (0x20803006U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_INJECT_ERROR_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_NVLINK_INJECT_ERROR_PARAMS_MESSAGE_ID (0x6U)
@@ -1655,13 +1658,23 @@ typedef struct NV2080_CTRL_NVLINK_ENABLE_NVLINK_PEER_PARAMS {
NvBool bEnable;
} NV2080_CTRL_NVLINK_ENABLE_NVLINK_PEER_PARAMS;
#define NV2080_CTRL_NVLINK_GET_LP_COUNTERS_COUNT_TX_NVHS 0U
#define NV2080_CTRL_NVLINK_GET_LP_COUNTERS_COUNT_TX_EIGHTH 1U
#define NV2080_CTRL_NVLINK_GET_LP_COUNTERS_COUNT_TX_OTHER 2U
#define NV2080_CTRL_NVLINK_GET_LP_COUNTERS_NUM_TX_LP_ENTER 3U
#define NV2080_CTRL_NVLINK_GET_LP_COUNTERS_NUM_TX_LP_EXIT 4U
#define NV2080_CTRL_NVLINK_GET_LP_COUNTERS_COUNT_TX_SLEEP 5U
#define NV2080_CTRL_NVLINK_GET_LP_COUNTERS_MAX_COUNTERS 6U
#define NV2080_CTRL_NVLINK_GET_LP_COUNTERS_COUNT_TX_NVHS 0U
#define NV2080_CTRL_NVLINK_GET_LP_COUNTERS_COUNT_TX_EIGHTH 1U
#define NV2080_CTRL_NVLINK_GET_LP_COUNTERS_COUNT_TX_OTHER 2U
#define NV2080_CTRL_NVLINK_GET_LP_COUNTERS_NUM_TX_LP_ENTER 3U
#define NV2080_CTRL_NVLINK_GET_LP_COUNTERS_NUM_TX_LP_EXIT 4U
#define NV2080_CTRL_NVLINK_GET_LP_COUNTERS_COUNT_TX_SLEEP 5U
#define NV2080_CTRL_NVLINK_GET_LP_COUNTERS_HS_TIME 6U
#define NV2080_CTRL_NVLINK_GET_LP_COUNTERS_LOCAL_FULL_BW_EXIT_TIME 7U
#define NV2080_CTRL_NVLINK_GET_LP_COUNTERS_LOCAL_LP_ENTRY_TIME 8U
#define NV2080_CTRL_NVLINK_GET_LP_COUNTERS_LOCAL_LP_EXIT_TIME 9U
#define NV2080_CTRL_NVLINK_GET_LP_COUNTERS_LOCAL_FULL_BW_ENTRY_TIME 10U
#define NV2080_CTRL_NVLINK_GET_LP_COUNTERS_REMOTE_FULL_BW_EXIT_TIME 11U
#define NV2080_CTRL_NVLINK_GET_LP_COUNTERS_REMOTE_LP_ENTRY_TIME 12U
#define NV2080_CTRL_NVLINK_GET_LP_COUNTERS_REMOTE_LP_EXIT_TIME 13U
#define NV2080_CTRL_NVLINK_GET_LP_COUNTERS_REMOTE_FULL_BW_ENTRY_TIME 14U
#define NV2080_CTRL_NVLINK_GET_LP_COUNTERS_OTHER_STATE_TIME 15U
#define NV2080_CTRL_NVLINK_GET_LP_COUNTERS_MAX_COUNTERS 16U
/*
* NV2080_CTRL_CMD_NVLINK_GET_LP_COUNTERS
@@ -1694,6 +1707,8 @@ typedef struct NV2080_CTRL_NVLINK_GET_LP_COUNTERS_PARAMS {
#define NV2080_CTRL_CMD_NVLINK_GET_LP_COUNTERS (0x20803018U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_GET_LP_COUNTERS_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_CMD_NVLINK_CLEAR_LP_COUNTERS (0x20803052U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8 | 0x52)" */
/*
* NVLINK Link states
* These should ALWAYS match the nvlink core library defines in nvlink.h
@@ -2830,6 +2845,7 @@ typedef struct NV2080_CTRL_NVLINK_PROCESS_INIT_DISABLED_LINKS_PARAMS {
* cmd [IN] enum identifying the EOM related command for the driver to process
* link [IN] linkId
* params [IN] NvU32 word that is written into NV_PMINION_SCRATCH_SWRW_0 before calling CONFIGEOM dlcmd
* measurements [OUT] output of EOM
*
* Params Packing is specified in Minion IAS
*/
@@ -2841,27 +2857,37 @@ typedef enum NV2080_CTRL_CMD_NVLINK_EOM_CONTROL_PARAMS_COMMAND {
NVLINK_EOM_CONTROL_FULL_EOM_SEQUENCE = 3,
} NV2080_CTRL_CMD_NVLINK_EOM_CONTROL_PARAMS_COMMAND;
typedef struct NV2080_CTRL_NVLINK_EOM_MEASUREMENT {
NvU8 upper;
NvU8 middle;
NvU8 lower;
NvU8 composite;
} NV2080_CTRL_NVLINK_EOM_MEASUREMENT;
#define NV2080_CTRL_NVLINK_EOM_CONTROL_PARAMS_MESSAGE_ID (0x3cU)
typedef struct NV2080_CTRL_NVLINK_EOM_CONTROL_PARAMS {
NV2080_CTRL_CMD_NVLINK_EOM_CONTROL_PARAMS_COMMAND cmd;
NvU32 linkId;
NvU32 params;
NV2080_CTRL_NVLINK_EOM_MEASUREMENT measurements[NV2080_CTRL_NVLINK_MAX_LANES];
} NV2080_CTRL_NVLINK_EOM_CONTROL_PARAMS;
#define NV2080_CTRL_CMD_NVLINK_EOM_CONTROL (0x2080303c) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_EOM_CONTROL_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_CMD_NVLINK_EOM_CONTROL (0x2080303c) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_EOM_CONTROL_PARAMS_MESSAGE_ID" */
/*!
* Inband Recieved Data
* Inband Received Data
*/
#define NV2080_CTRL_NVLINK_INBAND_MAX_MSG_SIZE 4096
#define NV2080_CTRL_NVLINK_INBAND_MAX_DATA_SIZE 5120
#define NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_PARAMS_MESSAGE_ID (0x3dU)
typedef struct NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_PARAMS {
NvU8 data[NV2080_CTRL_NVLINK_INBAND_MAX_MSG_SIZE];
NvU8 data[NV2080_CTRL_NVLINK_INBAND_MAX_DATA_SIZE];
NvU32 dataSize;
} NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_PARAMS;
#define NV2080_CTRL_CMD_READ_NVLINK_INBAND_RESPONSE (0x2080303d) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_PARAMS_MESSAGE_ID" */
/*
* NV2080_CTRL_CMD_NVLINK_SET_L1_THRESHOLD
*
@@ -2909,7 +2935,7 @@ typedef struct NV2080_CTRL_NVLINK_GET_L1_THRESHOLD_PARAMS {
#define NV2080_CTRL_NVLINK_INBAND_SEND_DATA_PARAMS_MESSAGE_ID (0x40U)
typedef struct NV2080_CTRL_NVLINK_INBAND_SEND_DATA_PARAMS {
NvU8 buffer[NV2080_CTRL_NVLINK_INBAND_MAX_MSG_SIZE];
NvU8 buffer[NV2080_CTRL_NVLINK_INBAND_MAX_DATA_SIZE];
NvU32 dataSize;
} NV2080_CTRL_NVLINK_INBAND_SEND_DATA_PARAMS;
@@ -3074,5 +3100,18 @@ typedef struct NV2080_CTRL_NVLINK_IS_REDUCED_CONFIG_PARAMS {
#define NV2080_CTRL_CMD_NVLINK_IS_REDUCED_CONFIG (0x20803046U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_IS_REDUCED_CONFIG_PARAMS_MESSAGE_ID" */
/*!
*
* NV2080_CTRL_CMD_NVLINK_ENABLE_LINKS
*
* Nvlink Fatal Error Recovery
* This command accepts no parameters.
*
*/
#define NV2080_CTRL_CMD_NVLINK_FATAL_ERROR_RECOVERY (0x20803048U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | 0x48" */
/* _ctrl2080nvlink_h_ */

252
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080perf.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2005-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2005-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -444,6 +444,14 @@ typedef struct NV2080_CTRL_PERF_GPUMON_PERFMON_UTIL_SAMPLE {
* NV DECODER utilization sample.
*/
NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE nvdec;
/*!
* NV JPEG utilization sample.
*/
NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE nvjpg;
/*!
* NV OFA utilization sample.
*/
NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE nvofa;
} NV2080_CTRL_PERF_GPUMON_PERFMON_UTIL_SAMPLE;
/*!
@@ -582,5 +590,247 @@ typedef struct NV2080_CTRL_PERF_AGGRESSIVE_PSTATE_NOTIFY_PARAMS {
} NV2080_CTRL_PERF_AGGRESSIVE_PSTATE_NOTIFY_PARAMS;
typedef struct NV2080_CTRL_PERF_GET_CLK_INFO {
NvU32 flags;
NvU32 domain;
NvU32 currentFreq;
NvU32 defaultFreq;
NvU32 minFreq;
NvU32 maxFreq;
} NV2080_CTRL_PERF_GET_CLK_INFO;
#define NV2080_CTRL_PERF_CLK_MAX_DOMAINS 32U
#define NV2080_CTRL_CMD_PERF_GET_LEVEL_INFO (0x20802002) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_PERF_INTERFACE_ID << 8) | NV2080_CTRL_PERF_GET_LEVEL_INFO_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_PERF_GET_LEVEL_INFO_PARAMS_MESSAGE_ID (0x2U)
typedef struct NV2080_CTRL_PERF_GET_LEVEL_INFO_PARAMS {
NvU32 level;
NvU32 flags;
NV_DECLARE_ALIGNED(NvP64 perfGetClkInfoList, 8);
NvU32 perfGetClkInfoListSize;
} NV2080_CTRL_PERF_GET_LEVEL_INFO_PARAMS;
#define NV2080_CTRL_CMD_PERF_GET_LEVEL_INFO_V2 (0x2080200b) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_PERF_INTERFACE_ID << 8) | NV2080_CTRL_PERF_GET_LEVEL_INFO_V2_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_PERF_GET_LEVEL_INFO_V2_PARAMS_MESSAGE_ID (0xBU)
typedef struct NV2080_CTRL_PERF_GET_LEVEL_INFO_V2_PARAMS {
NvU32 level;
NvU32 flags;
NV2080_CTRL_PERF_GET_CLK_INFO perfGetClkInfoList[NV2080_CTRL_PERF_CLK_MAX_DOMAINS];
NvU32 perfGetClkInfoListSize;
} NV2080_CTRL_PERF_GET_LEVEL_INFO_V2_PARAMS;
#define NV2080_CTRL_PERF_GET_LEVEL_INFO_FLAGS_TYPE 0:0
#define NV2080_CTRL_PERF_GET_LEVEL_INFO_FLAGS_TYPE_DEFAULT (0x00000000)
#define NV2080_CTRL_PERF_GET_LEVEL_INFO_FLAGS_TYPE_OVERCLOCK (0x00000001)
#define NV2080_CTRL_PERF_GET_LEVEL_INFO_FLAGS_MODE 2:1
#define NV2080_CTRL_PERF_GET_LEVEL_INFO_FLAGS_MODE_NONE (0x00000000)
#define NV2080_CTRL_PERF_GET_LEVEL_INFO_FLAGS_MODE_DESKTOP (0x00000001)
#define NV2080_CTRL_PERF_GET_LEVEL_INFO_FLAGS_MODE_MAXPERF (0x00000002)
/*
* NV2080_CTRL_CMD_PERF_GET_VID_ENG_PERFMON_SAMPLE
*
* This command can be used to obtain video decoder utilization of
* the associated subdevice.
* This command is not supported with SMC enabled.
*
* engineType
* This parameter will allow clients to set type of video
* engine in question. It can be NVENC or NVDEC.
* clkPercentBusy
* This parameter contains the percentage during the sample that
* the clock remains busy.
* samplingPeriodUs
* This field returns the sampling period in microseconds.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_PARAM_STRUCT
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_NOT_SUPPORTED
*/
#define NV2080_CTRL_CMD_PERF_GET_VID_ENG_PERFMON_SAMPLE (0x20802087) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_PERF_INTERFACE_ID << 8) | NV2080_CTRL_PERF_GET_VID_ENG_PERFMON_SAMPLE_PARAMS_MESSAGE_ID" */
typedef enum NV2080_CTRL_CMD_PERF_VID_ENG {
/*!
* GPU Video encoder engine.
*/
NV2080_CTRL_CMD_PERF_VID_ENG_NVENC = 1,
/*!
* GPU video decoder engine.
*/
NV2080_CTRL_CMD_PERF_VID_ENG_NVDEC = 2,
/*!
* GPU JPEG engine.
*/
NV2080_CTRL_CMD_PERF_VID_ENG_NVJPG = 3,
/*!
* GPU OFA engine.
*/
NV2080_CTRL_CMD_PERF_VID_ENG_NVOFA = 4,
} NV2080_CTRL_CMD_PERF_VID_ENG;
#define NV2080_CTRL_PERF_GET_VID_ENG_PERFMON_SAMPLE_PARAMS_MESSAGE_ID (0x87U)
typedef struct NV2080_CTRL_PERF_GET_VID_ENG_PERFMON_SAMPLE_PARAMS {
NV2080_CTRL_CMD_PERF_VID_ENG engineType;
NvU32 clkPercentBusy;
NvU32 samplingPeriodUs;
} NV2080_CTRL_PERF_GET_VID_ENG_PERFMON_SAMPLE_PARAMS;
/*
* NV2080_CTRL_CMD_PERF_GET_POWERSTATE
*
* This command can be used to find out whether the perf power state is AC/battery.
*
* powerStateInfo
* This parameter specifies the power source type.
*
* Possible status values returned are:
* NV_OK
*/
#define NV2080_CTRL_CMD_PERF_GET_POWERSTATE (0x2080205a) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_PERF_INTERFACE_ID << 8) | NV2080_CTRL_PERF_GET_POWERSTATE_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_PERF_GET_POWERSTATE_PARAMS_MESSAGE_ID (0x5AU)
typedef struct NV2080_CTRL_PERF_GET_POWERSTATE_PARAMS {
NV2080_CTRL_PERF_POWERSTATE_PARAMS powerStateInfo;
} NV2080_CTRL_PERF_GET_POWERSTATE_PARAMS;
/*
* NV2080_CTRL_CMD_PERF_NOTIFY_VIDEOEVENT
*
* This command can be used by video driver to notify RM concerning
* performance related events.
*
* videoEvent
* This parameter specifies the video event to notify.
* Legal values for this parameter include:
* NV2080_CTRL_PERF_VIDEOEVENT_STREAM_HD_START
* NV2080_CTRL_PERF_VIDEOEVENT_STREAM_HD_STOP
* These values indicate that a HD video stream (less than 4K)
* has started/stopped.
* NV2080_CTRL_PERF_VIDEOEVENT_STREAM_SD_START
* NV2080_CTRL_PERF_VIDEOEVENT_STREAM_SD_STOP
* These are now obsolete in new products as we no longer
* need to differentiate between SD and HD.
* NV2080_CTRL_PERF_VIDEOEVENT_STREAM_4K_START
* NV2080_CTRL_PERF_VIDEOEVENT_STREAM_4K_STOP
* These value indicates that a 4K video stream (3840x2160 pixels
* or higher) has started/stopped.
* NV2080_CTRL_PERF_VIDEOEVENT_OFA_START
* NV2080_CTRL_PERF_VIDEOEVENT_OFA_STOP
* These value indicates that Optical Flow Accelerator usage has
* started/stopped.
* The following flags may be or'd into the event value:
* NV2080_CTRL_PERF_VIDEOEVENT_FLAG_LINEAR_MODE
* The stream operates BSP/VP2 or MSVLD/MSPDEC communication in
* linear mode (default is ring mode).
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_STATE
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_INVALID_PARAM_STRUCT
*/
#define NV2080_CTRL_CMD_PERF_NOTIFY_VIDEOEVENT (0x2080205d) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_PERF_INTERFACE_ID << 8) | NV2080_CTRL_PERF_NOTIFY_VIDEOEVENT_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_PERF_NOTIFY_VIDEOEVENT_PARAMS_MESSAGE_ID (0x5DU)
typedef struct NV2080_CTRL_PERF_NOTIFY_VIDEOEVENT_PARAMS {
NvU32 videoEvent;
} NV2080_CTRL_PERF_NOTIFY_VIDEOEVENT_PARAMS;
#define NV2080_CTRL_PERF_VIDEOEVENT_EVENT_MASK (0x0000ffff)
#define NV2080_CTRL_PERF_VIDEOEVENT_STREAM_HD_START (0x00000001)
#define NV2080_CTRL_PERF_VIDEOEVENT_STREAM_HD_STOP (0x00000002)
#define NV2080_CTRL_PERF_VIDEOEVENT_STREAM_START NV2080_CTRL_PERF_VIDEOEVENT_STREAM_HD_START
#define NV2080_CTRL_PERF_VIDEOEVENT_STREAM_STOP NV2080_CTRL_PERF_VIDEOEVENT_STREAM_HD_STOP
#define NV2080_CTRL_PERF_VIDEOEVENT_STREAM_SD_START (0x00000003)
#define NV2080_CTRL_PERF_VIDEOEVENT_STREAM_SD_STOP (0x00000004)
#define NV2080_CTRL_PERF_VIDEOEVENT_STREAM_4K_START (0x00000005)
#define NV2080_CTRL_PERF_VIDEOEVENT_STREAM_4K_STOP (0x00000006)
#define NV2080_CTRL_PERF_VIDEOEVENT_OFA_START (0x00000007)
#define NV2080_CTRL_PERF_VIDEOEVENT_OFA_STOP (0x00000008)
#define NV2080_CTRL_PERF_VIDEOEVENT_FLAG_LINEAR_MODE (0x00010000)
/*!
* @defgroup NV2080_CTRL_PERF_PSTATES
*
* These are definitions of performance states (P-states) values.
* P0 has the maximum performance capability and consumes maximum
* power. P1 has a lower perf and power than P0, and so on.
* For NVIDIA GPUs, the following definitions are made:
* P0 - maximum 3D performance
* P1 - original P0 when active clocked
* P2-P3 - balanced 3D performance-power
* P8 - basic HD video playback
* P10 - SD video playback
* P12 - minimum idle power
* P15 - max possible P-state under current scheme (currently not used)
* Not all P-states are available on a given system.
*
* @note The @ref NV2080_CTRL_PERF_PSTATES_ID was introduced after the
* original constants were added, so not all places that intend to use
* these values are using the type. They should be updated to do so.
* @{
*/
typedef NvU32 NV2080_CTRL_PERF_PSTATES_ID;
#define NV2080_CTRL_PERF_PSTATES_UNDEFINED (0x00000000U)
#define NV2080_CTRL_PERF_PSTATES_CLEAR_FORCED (0x00000000U)
#define NV2080_CTRL_PERF_PSTATES_MIN (0x00000001U)
#define NV2080_CTRL_PERF_PSTATES_P0 (0x00000001U)
#define NV2080_CTRL_PERF_PSTATES_P1 (0x00000002U)
#define NV2080_CTRL_PERF_PSTATES_P2 (0x00000004U)
#define NV2080_CTRL_PERF_PSTATES_P3 (0x00000008U)
#define NV2080_CTRL_PERF_PSTATES_P4 (0x00000010U)
#define NV2080_CTRL_PERF_PSTATES_P5 (0x00000020U)
#define NV2080_CTRL_PERF_PSTATES_P6 (0x00000040U)
#define NV2080_CTRL_PERF_PSTATES_P7 (0x00000080U)
#define NV2080_CTRL_PERF_PSTATES_P8 (0x00000100U)
#define NV2080_CTRL_PERF_PSTATES_P9 (0x00000200U)
#define NV2080_CTRL_PERF_PSTATES_P10 (0x00000400U)
#define NV2080_CTRL_PERF_PSTATES_P11 (0x00000800U)
#define NV2080_CTRL_PERF_PSTATES_P12 (0x00001000U)
#define NV2080_CTRL_PERF_PSTATES_P13 (0x00002000U)
#define NV2080_CTRL_PERF_PSTATES_P14 (0x00004000U)
#define NV2080_CTRL_PERF_PSTATES_P15 (0x00008000U)
#define NV2080_CTRL_PERF_PSTATES_MAX NV2080_CTRL_PERF_PSTATES_P15
#define NV2080_CTRL_PERF_PSTATES_SKIP_ENTRY (0x10000U) /* finn: Evaluated from "(NV2080_CTRL_PERF_PSTATES_MAX << 1)" */
#define NV2080_CTRL_PERF_PSTATES_ALL (0xffffU) /* finn: Evaluated from "(NV2080_CTRL_PERF_PSTATES_MAX | (NV2080_CTRL_PERF_PSTATES_MAX - 1))" */
/*!@}*/
/*
* NV2080_CTRL_CMD_PERF_GET_CURRENT_PSTATE
*
* This command returns the current performance state of the GPU.
*
* currPstate
* This parameter returns the current P-state, as defined in
* NV2080_CTRL_PERF_PSTATES values.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_PARAM_STRUCT
* NV_ERR_NOT_SUPPORTED
* NV_ERR_INVALID_STATE
*/
#define NV2080_CTRL_CMD_PERF_GET_CURRENT_PSTATE (0x20802068) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_PERF_INTERFACE_ID << 8) | NV2080_CTRL_PERF_GET_CURRENT_PSTATE_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_PERF_GET_CURRENT_PSTATE_PARAMS_MESSAGE_ID (0x68U)
typedef struct NV2080_CTRL_PERF_GET_CURRENT_PSTATE_PARAMS {
NvU32 currPstate;
} NV2080_CTRL_PERF_GET_CURRENT_PSTATE_PARAMS;
/* _ctrl2080perf_h_ */

5
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080pmu.h
View File

@@ -1,4 +1,3 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
@@ -24,6 +23,8 @@
#pragma once
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl2080/ctrl2080pmu.finn
@@ -31,8 +32,6 @@
#include "nvtypes.h"
/*!
* @file
*

111
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080spdm.h
View File

@@ -38,93 +38,45 @@
* @brief SPDM Command Types
*
*/
#define RM_GSP_SPDM_CMD_ID_CC_INIT (0x1)
#define RM_GSP_SPDM_CMD_ID_CC_DEINIT (0x2)
#define RM_GSP_SPDM_CMD_ID_CC_CTRL (0x3)
#define RM_GSP_SPDM_CMD_ID_CC_INIT_RM_DATA (0x4)
#define RM_GSP_SPDM_CMD_ID_CC_INIT (0x1)
#define RM_GSP_SPDM_CMD_ID_CC_DEINIT (0x2)
#define RM_GSP_SPDM_CMD_ID_CC_CTRL (0x3)
#define RM_GSP_SPDM_CMD_ID_CC_INIT_RM_DATA (0x4)
#define RM_GSP_SPDM_CMD_ID_CC_HEARTBEAT_CTRL (0x5)
#define RM_GSP_SPDM_CMD_ID_INVALID_COMMAND (0xFF)
#define RM_GSP_SPDM_CMD_ID_INVALID_COMMAND (0xFF)
#define RSVD7_SIZE 16
#define RSVD7_SIZE 16
#define RSVD8_SIZE 2
/*!
* Guest RM must send RM_GSP_SPDM_CMD_ID_CC_INIT to GSP-RM before SPDM session start
*/
typedef struct RM_GSP_SPDM_CC_INIT_CTX {
NvU32 guestId; // To indicate CC guest Id, VM0, VM1 ... etc
NvU64_ALIGN32 dmaAddr; // The address RM allocate in SYS memory or FB memory.
NvU32 rmBufferSizeInByte; // The memort size allocated by RM(exclude NV_SPDM_DESC_HEADER)
} RM_GSP_SPDM_CC_INIT_CTX;
typedef struct RM_GSP_SPDM_CC_INIT_CTX *PRM_GSP_SPDM_CC_INIT_CTX;
#define RSVD8_SIZE 2
/*!
* Guest RM provides INIT context
*/
typedef struct RM_GSP_SPDM_CMD_CC_INIT {
// Command must be first as this struct is the part of union
NvU8 cmdType;
RM_GSP_SPDM_CC_INIT_CTX ccInitCtx;
NvU8 cmdType;
} RM_GSP_SPDM_CMD_CC_INIT;
typedef struct RM_GSP_SPDM_CMD_CC_INIT *PRM_GSP_SPDM_CMD_CC_INIT;
#define DEINIT_FLAGS_FORCE_CLEAR (0x1)
/*!
* Guest RM must send RM_GSP_SPDM_CMD_ID_CC_DEINIT to GSP-RM to end a session
*/
typedef struct RM_GSP_SPDM_CC_DEINIT_CTX {
NvU32 guestId; // To indicate CC guest Id, VM0, VM1 ... etc
NvU32 endpointId; // To indicate SPDM endpoint Id
NvU32 flags;
} RM_GSP_SPDM_CC_DEINIT_CTX;
typedef struct RM_GSP_SPDM_CC_DEINIT_CTX *PRM_GSP_SPDM_CC_DEINIT_CTX;
/*!
* Guest RM provides INIT context
*/
typedef struct RM_GSP_SPDM_CMD_CC_DEINIT {
// Command must be first as this struct is the part of union
NvU8 cmdType;
RM_GSP_SPDM_CC_DEINIT_CTX ccDeinitCtx;
NvU8 cmdType;
} RM_GSP_SPDM_CMD_CC_DEINIT;
typedef struct RM_GSP_SPDM_CMD_CC_DEINIT *PRM_GSP_SPDM_CMD_CC_DEINIT;
/*!
* RM provides SPDM message request context, include header + corresponding payload
*/
typedef struct RM_GSP_SPDM_CC_CTRL_CTX {
NvU32 version;
NvU32 guestId; // To indicate CC client Id, VM0, VM1 ... etc
NvU32 endpointId; // To indicate SPDM endpoint Id
} RM_GSP_SPDM_CC_CTRL_CTX;
typedef struct RM_GSP_SPDM_CC_CTRL_CTX *PRM_GSP_SPDM_CC_CTRL_CTX;
/*!
* RM provides the SPDM request info to GSP
*/
typedef struct RM_GSP_SPDM_CMD_CC_CTRL {
// Command must be first as this struct is the part of union
NvU8 cmdType;
RM_GSP_SPDM_CC_CTRL_CTX ccCtrlCtx;
NvU8 cmdType;
} RM_GSP_SPDM_CMD_CC_CTRL;
typedef struct RM_GSP_SPDM_CMD_CC_CTRL *PRM_GSP_SPDM_CMD_CC_CTRL;
@@ -136,9 +88,9 @@ typedef struct RM_GSP_SPDM_CMD_CC_INIT_RM_DATA {
NvU32 rsvd1;
char rsvd2[4];
char rsvd2[9];
char rsvd3[2];
char rsvd3[5];
char rsvd4[5];
@@ -152,6 +104,15 @@ typedef struct RM_GSP_SPDM_CMD_CC_INIT_RM_DATA {
} RM_GSP_SPDM_CMD_CC_INIT_RM_DATA;
typedef struct RM_GSP_SPDM_CMD_CC_INIT_RM_DATA *PRM_GSP_SPDM_CMD_CC_INIT_RM_DATA;
typedef struct RM_GSP_SPDM_CMD_CC_HEARTBEAT_CTRL {
// Command must be first as this struct is the part of union
NvU8 cmdType;
// Whether to enable or disable heartbeats
NvBool bEnable;
} RM_GSP_SPDM_CMD_CC_HEARTBEAT_CTRL;
typedef struct RM_GSP_SPDM_CMD_CC_HEARTBEAT_CTRL *PRM_GSP_SPDM_CMD_CC_HEARTBEAT_CTRL;
/*!
* NOTE : Do not include structure members that have alignment requirement >= 8 to avoid alignment directives
@@ -164,11 +125,12 @@ typedef struct RM_GSP_SPDM_CMD_CC_INIT_RM_DATA *PRM_GSP_SPDM_CMD_CC_INIT_RM_DATA
* A union of all SPDM Commands.
*/
typedef union RM_GSP_SPDM_CMD {
NvU8 cmdType;
RM_GSP_SPDM_CMD_CC_INIT ccInit;
RM_GSP_SPDM_CMD_CC_DEINIT ccDeinit;
RM_GSP_SPDM_CMD_CC_CTRL ccCtrl;
RM_GSP_SPDM_CMD_CC_INIT_RM_DATA rmDataInitCmd;
NvU8 cmdType;
RM_GSP_SPDM_CMD_CC_INIT ccInit;
RM_GSP_SPDM_CMD_CC_DEINIT ccDeinit;
RM_GSP_SPDM_CMD_CC_CTRL ccCtrl;
RM_GSP_SPDM_CMD_CC_INIT_RM_DATA rmDataInitCmd;
RM_GSP_SPDM_CMD_CC_HEARTBEAT_CTRL ccHeartbeatCtrl;
} RM_GSP_SPDM_CMD;
typedef union RM_GSP_SPDM_CMD *PRM_GSP_SPDM_CMD;
@@ -182,17 +144,18 @@ typedef union RM_GSP_SPDM_CMD *PRM_GSP_SPDM_CMD;
/*!
* Returns the status for program CE keys to RM
*/
#define RM_GSP_SPDM_MSG_ID_CC_INIT (0x1)
#define RM_GSP_SPDM_MSG_ID_CC_DEINIT (0x2)
#define RM_GSP_SPDM_MSG_ID_CC_CTRL (0x3)
#define RM_GSP_SPDM_MSG_ID_CC_INIT_RM_DATA (0x4)
#define RM_GSP_SPDM_MSG_ID_CC_INIT (0x1)
#define RM_GSP_SPDM_MSG_ID_CC_DEINIT (0x2)
#define RM_GSP_SPDM_MSG_ID_CC_CTRL (0x3)
#define RM_GSP_SPDM_MSG_ID_CC_INIT_RM_DATA (0x4)
#define RM_GSP_SPDM_MSG_ID_CC_HEARTBEAT_CTRL (0x5)
/*!
* Returns the Error Status for Invalid Command
*/
#define RM_GSP_SPDM_MSG_ID_INVALID_COMMAND (0xFF)
#define RM_GSP_SPDM_MSG_ID_INVALID_COMMAND (0xFF)
/*!
* NOTE : Do not include structure members that have alignment requirement >= 8 to avoid alignment directives
@@ -207,12 +170,6 @@ typedef union RM_GSP_SPDM_CMD *PRM_GSP_SPDM_CMD;
typedef struct RM_GSP_SPDM_MSG {
NvU8 msgType;
NvU32 version;
NvU32 guestId;
NvU32 endpointId;
// status returned from GSP message infrastructure.
NvU32 status;

26
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080vgpumgrinternal.h
View File

@@ -61,7 +61,7 @@
#define NV2080_CTRL_MAX_VMMU_SEGMENTS 384
/* Must match NV2080_ENGINE_TYPE_LAST from cl2080.h */
#define NV2080_GPU_MAX_ENGINES 0x3f
#define NV2080_GPU_MAX_ENGINES 0x40
#define NV2080_CTRL_VGPU_MGR_INTERNAL_BOOTLOAD_GSP_VGPU_PLUGIN_TASK_PARAMS_MESSAGE_ID (0x1U)
@@ -412,4 +412,28 @@ typedef struct NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_MGR_CONFIG_PARAMS {
NvBool bSupportHeterogeneousTimeSlicedVgpuTypes;
} NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_MGR_CONFIG_PARAMS;
/*
* NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_GET_PGPU_MIGRATION_SUPPORT
*
* Reroutes NVA084_CTRL_CMD_KERNEL_HOST_VGPU_DEVICE_FREE_STATES to GSP RM to enable
* kernel clients to utilize NVA082_CTRL_CMD_HOST_VGPU_DEVICE_FREE_STATES.
*
* gfid [IN]
* This parameter specifies the gfid of vGPU assigned to VM.
* flags [IN]
* Specifies what component of HostVgpuDevice to free.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_STATE
*/
#define NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_FREE_STATES (0x2080400c) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_VGPU_MGR_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_VGPU_MGR_INTERNAL_FREE_STATES_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_VGPU_MGR_INTERNAL_FREE_STATES_PARAMS_MESSAGE_ID (0xCU)
typedef struct NV2080_CTRL_VGPU_MGR_INTERNAL_FREE_STATES_PARAMS {
NvU32 gfid;
NvU32 flags;
} NV2080_CTRL_VGPU_MGR_INTERNAL_FREE_STATES_PARAMS;
/* _ctrl2080vgpumgrinternal_h_ */