550.40.07

This commit is contained in:
Bernhard Stoeckner
2024-01-24 17:51:53 +01:00
parent bb2dac1f20
commit 91676d6628
1411 changed files with 261367 additions and 145959 deletions

View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2005-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2005-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -444,6 +444,14 @@ typedef struct NV2080_CTRL_PERF_GPUMON_PERFMON_UTIL_SAMPLE {
* NV DECODER utilization sample.
*/
NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE nvdec;
/*!
* NV JPEG utilization sample.
*/
NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE nvjpg;
/*!
* NV OFA utilization sample.
*/
NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE nvofa;
} NV2080_CTRL_PERF_GPUMON_PERFMON_UTIL_SAMPLE;
/*!
@@ -582,5 +590,247 @@ typedef struct NV2080_CTRL_PERF_AGGRESSIVE_PSTATE_NOTIFY_PARAMS {
} NV2080_CTRL_PERF_AGGRESSIVE_PSTATE_NOTIFY_PARAMS;
typedef struct NV2080_CTRL_PERF_GET_CLK_INFO {
NvU32 flags;
NvU32 domain;
NvU32 currentFreq;
NvU32 defaultFreq;
NvU32 minFreq;
NvU32 maxFreq;
} NV2080_CTRL_PERF_GET_CLK_INFO;
#define NV2080_CTRL_PERF_CLK_MAX_DOMAINS 32U
#define NV2080_CTRL_CMD_PERF_GET_LEVEL_INFO (0x20802002) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_PERF_INTERFACE_ID << 8) | NV2080_CTRL_PERF_GET_LEVEL_INFO_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_PERF_GET_LEVEL_INFO_PARAMS_MESSAGE_ID (0x2U)
typedef struct NV2080_CTRL_PERF_GET_LEVEL_INFO_PARAMS {
NvU32 level;
NvU32 flags;
NV_DECLARE_ALIGNED(NvP64 perfGetClkInfoList, 8);
NvU32 perfGetClkInfoListSize;
} NV2080_CTRL_PERF_GET_LEVEL_INFO_PARAMS;
#define NV2080_CTRL_CMD_PERF_GET_LEVEL_INFO_V2 (0x2080200b) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_PERF_INTERFACE_ID << 8) | NV2080_CTRL_PERF_GET_LEVEL_INFO_V2_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_PERF_GET_LEVEL_INFO_V2_PARAMS_MESSAGE_ID (0xBU)
typedef struct NV2080_CTRL_PERF_GET_LEVEL_INFO_V2_PARAMS {
NvU32 level;
NvU32 flags;
NV2080_CTRL_PERF_GET_CLK_INFO perfGetClkInfoList[NV2080_CTRL_PERF_CLK_MAX_DOMAINS];
NvU32 perfGetClkInfoListSize;
} NV2080_CTRL_PERF_GET_LEVEL_INFO_V2_PARAMS;
#define NV2080_CTRL_PERF_GET_LEVEL_INFO_FLAGS_TYPE 0:0
#define NV2080_CTRL_PERF_GET_LEVEL_INFO_FLAGS_TYPE_DEFAULT (0x00000000)
#define NV2080_CTRL_PERF_GET_LEVEL_INFO_FLAGS_TYPE_OVERCLOCK (0x00000001)
#define NV2080_CTRL_PERF_GET_LEVEL_INFO_FLAGS_MODE 2:1
#define NV2080_CTRL_PERF_GET_LEVEL_INFO_FLAGS_MODE_NONE (0x00000000)
#define NV2080_CTRL_PERF_GET_LEVEL_INFO_FLAGS_MODE_DESKTOP (0x00000001)
#define NV2080_CTRL_PERF_GET_LEVEL_INFO_FLAGS_MODE_MAXPERF (0x00000002)
/*
* NV2080_CTRL_CMD_PERF_GET_VID_ENG_PERFMON_SAMPLE
*
* This command can be used to obtain video decoder utilization of
* the associated subdevice.
* This command is not supported with SMC enabled.
*
* engineType
* This parameter will allow clients to set type of video
* engine in question. It can be NVENC or NVDEC.
* clkPercentBusy
* This parameter contains the percentage during the sample that
* the clock remains busy.
* samplingPeriodUs
* This field returns the sampling period in microseconds.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_PARAM_STRUCT
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_NOT_SUPPORTED
*/
#define NV2080_CTRL_CMD_PERF_GET_VID_ENG_PERFMON_SAMPLE (0x20802087) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_PERF_INTERFACE_ID << 8) | NV2080_CTRL_PERF_GET_VID_ENG_PERFMON_SAMPLE_PARAMS_MESSAGE_ID" */
typedef enum NV2080_CTRL_CMD_PERF_VID_ENG {
/*!
* GPU Video encoder engine.
*/
NV2080_CTRL_CMD_PERF_VID_ENG_NVENC = 1,
/*!
* GPU video decoder engine.
*/
NV2080_CTRL_CMD_PERF_VID_ENG_NVDEC = 2,
/*!
* GPU JPEG engine.
*/
NV2080_CTRL_CMD_PERF_VID_ENG_NVJPG = 3,
/*!
* GPU OFA engine.
*/
NV2080_CTRL_CMD_PERF_VID_ENG_NVOFA = 4,
} NV2080_CTRL_CMD_PERF_VID_ENG;
#define NV2080_CTRL_PERF_GET_VID_ENG_PERFMON_SAMPLE_PARAMS_MESSAGE_ID (0x87U)
typedef struct NV2080_CTRL_PERF_GET_VID_ENG_PERFMON_SAMPLE_PARAMS {
NV2080_CTRL_CMD_PERF_VID_ENG engineType;
NvU32 clkPercentBusy;
NvU32 samplingPeriodUs;
} NV2080_CTRL_PERF_GET_VID_ENG_PERFMON_SAMPLE_PARAMS;
/*
* NV2080_CTRL_CMD_PERF_GET_POWERSTATE
*
* This command can be used to find out whether the perf power state is AC/battery.
*
* powerStateInfo
* This parameter specifies the power source type.
*
* Possible status values returned are:
* NV_OK
*/
#define NV2080_CTRL_CMD_PERF_GET_POWERSTATE (0x2080205a) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_PERF_INTERFACE_ID << 8) | NV2080_CTRL_PERF_GET_POWERSTATE_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_PERF_GET_POWERSTATE_PARAMS_MESSAGE_ID (0x5AU)
typedef struct NV2080_CTRL_PERF_GET_POWERSTATE_PARAMS {
NV2080_CTRL_PERF_POWERSTATE_PARAMS powerStateInfo;
} NV2080_CTRL_PERF_GET_POWERSTATE_PARAMS;
/*
* NV2080_CTRL_CMD_PERF_NOTIFY_VIDEOEVENT
*
* This command can be used by video driver to notify RM concerning
* performance related events.
*
* videoEvent
* This parameter specifies the video event to notify.
* Legal values for this parameter include:
* NV2080_CTRL_PERF_VIDEOEVENT_STREAM_HD_START
* NV2080_CTRL_PERF_VIDEOEVENT_STREAM_HD_STOP
* These values indicate that a HD video stream (less than 4K)
* has started/stopped.
* NV2080_CTRL_PERF_VIDEOEVENT_STREAM_SD_START
* NV2080_CTRL_PERF_VIDEOEVENT_STREAM_SD_STOP
* These are now obsolete in new products as we no longer
* need to differentiate between SD and HD.
* NV2080_CTRL_PERF_VIDEOEVENT_STREAM_4K_START
* NV2080_CTRL_PERF_VIDEOEVENT_STREAM_4K_STOP
* These value indicates that a 4K video stream (3840x2160 pixels
* or higher) has started/stopped.
* NV2080_CTRL_PERF_VIDEOEVENT_OFA_START
* NV2080_CTRL_PERF_VIDEOEVENT_OFA_STOP
* These value indicates that Optical Flow Accelerator usage has
* started/stopped.
* The following flags may be or'd into the event value:
* NV2080_CTRL_PERF_VIDEOEVENT_FLAG_LINEAR_MODE
* The stream operates BSP/VP2 or MSVLD/MSPDEC communication in
* linear mode (default is ring mode).
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_STATE
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_INVALID_PARAM_STRUCT
*/
#define NV2080_CTRL_CMD_PERF_NOTIFY_VIDEOEVENT (0x2080205d) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_PERF_INTERFACE_ID << 8) | NV2080_CTRL_PERF_NOTIFY_VIDEOEVENT_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_PERF_NOTIFY_VIDEOEVENT_PARAMS_MESSAGE_ID (0x5DU)
typedef struct NV2080_CTRL_PERF_NOTIFY_VIDEOEVENT_PARAMS {
NvU32 videoEvent;
} NV2080_CTRL_PERF_NOTIFY_VIDEOEVENT_PARAMS;
#define NV2080_CTRL_PERF_VIDEOEVENT_EVENT_MASK (0x0000ffff)
#define NV2080_CTRL_PERF_VIDEOEVENT_STREAM_HD_START (0x00000001)
#define NV2080_CTRL_PERF_VIDEOEVENT_STREAM_HD_STOP (0x00000002)
#define NV2080_CTRL_PERF_VIDEOEVENT_STREAM_START NV2080_CTRL_PERF_VIDEOEVENT_STREAM_HD_START
#define NV2080_CTRL_PERF_VIDEOEVENT_STREAM_STOP NV2080_CTRL_PERF_VIDEOEVENT_STREAM_HD_STOP
#define NV2080_CTRL_PERF_VIDEOEVENT_STREAM_SD_START (0x00000003)
#define NV2080_CTRL_PERF_VIDEOEVENT_STREAM_SD_STOP (0x00000004)
#define NV2080_CTRL_PERF_VIDEOEVENT_STREAM_4K_START (0x00000005)
#define NV2080_CTRL_PERF_VIDEOEVENT_STREAM_4K_STOP (0x00000006)
#define NV2080_CTRL_PERF_VIDEOEVENT_OFA_START (0x00000007)
#define NV2080_CTRL_PERF_VIDEOEVENT_OFA_STOP (0x00000008)
#define NV2080_CTRL_PERF_VIDEOEVENT_FLAG_LINEAR_MODE (0x00010000)
/*!
* @defgroup NV2080_CTRL_PERF_PSTATES
*
* These are definitions of performance states (P-states) values.
* P0 has the maximum performance capability and consumes maximum
* power. P1 has a lower perf and power than P0, and so on.
* For NVIDIA GPUs, the following definitions are made:
* P0 - maximum 3D performance
* P1 - original P0 when active clocked
* P2-P3 - balanced 3D performance-power
* P8 - basic HD video playback
* P10 - SD video playback
* P12 - minimum idle power
* P15 - max possible P-state under current scheme (currently not used)
* Not all P-states are available on a given system.
*
* @note The @ref NV2080_CTRL_PERF_PSTATES_ID was introduced after the
* original constants were added, so not all places that intend to use
* these values are using the type. They should be updated to do so.
* @{
*/
typedef NvU32 NV2080_CTRL_PERF_PSTATES_ID;
#define NV2080_CTRL_PERF_PSTATES_UNDEFINED (0x00000000U)
#define NV2080_CTRL_PERF_PSTATES_CLEAR_FORCED (0x00000000U)
#define NV2080_CTRL_PERF_PSTATES_MIN (0x00000001U)
#define NV2080_CTRL_PERF_PSTATES_P0 (0x00000001U)
#define NV2080_CTRL_PERF_PSTATES_P1 (0x00000002U)
#define NV2080_CTRL_PERF_PSTATES_P2 (0x00000004U)
#define NV2080_CTRL_PERF_PSTATES_P3 (0x00000008U)
#define NV2080_CTRL_PERF_PSTATES_P4 (0x00000010U)
#define NV2080_CTRL_PERF_PSTATES_P5 (0x00000020U)
#define NV2080_CTRL_PERF_PSTATES_P6 (0x00000040U)
#define NV2080_CTRL_PERF_PSTATES_P7 (0x00000080U)
#define NV2080_CTRL_PERF_PSTATES_P8 (0x00000100U)
#define NV2080_CTRL_PERF_PSTATES_P9 (0x00000200U)
#define NV2080_CTRL_PERF_PSTATES_P10 (0x00000400U)
#define NV2080_CTRL_PERF_PSTATES_P11 (0x00000800U)
#define NV2080_CTRL_PERF_PSTATES_P12 (0x00001000U)
#define NV2080_CTRL_PERF_PSTATES_P13 (0x00002000U)
#define NV2080_CTRL_PERF_PSTATES_P14 (0x00004000U)
#define NV2080_CTRL_PERF_PSTATES_P15 (0x00008000U)
#define NV2080_CTRL_PERF_PSTATES_MAX NV2080_CTRL_PERF_PSTATES_P15
#define NV2080_CTRL_PERF_PSTATES_SKIP_ENTRY (0x10000U) /* finn: Evaluated from "(NV2080_CTRL_PERF_PSTATES_MAX << 1)" */
#define NV2080_CTRL_PERF_PSTATES_ALL (0xffffU) /* finn: Evaluated from "(NV2080_CTRL_PERF_PSTATES_MAX | (NV2080_CTRL_PERF_PSTATES_MAX - 1))" */
/*!@}*/
/*
* NV2080_CTRL_CMD_PERF_GET_CURRENT_PSTATE
*
* This command returns the current performance state of the GPU.
*
* currPstate
* This parameter returns the current P-state, as defined in
* NV2080_CTRL_PERF_PSTATES values.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_PARAM_STRUCT
* NV_ERR_NOT_SUPPORTED
* NV_ERR_INVALID_STATE
*/
#define NV2080_CTRL_CMD_PERF_GET_CURRENT_PSTATE (0x20802068) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_PERF_INTERFACE_ID << 8) | NV2080_CTRL_PERF_GET_CURRENT_PSTATE_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_PERF_GET_CURRENT_PSTATE_PARAMS_MESSAGE_ID (0x68U)
typedef struct NV2080_CTRL_PERF_GET_CURRENT_PSTATE_PARAMS {
NvU32 currPstate;
} NV2080_CTRL_PERF_GET_CURRENT_PSTATE_PARAMS;
/* _ctrl2080perf_h_ */