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550.40.07
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@@ -1,5 +1,5 @@
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/*
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* SPDX-FileCopyrightText: Copyright (c) 2007-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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* SPDX-FileCopyrightText: Copyright (c) 2007-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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* SPDX-License-Identifier: MIT
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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@@ -119,6 +119,9 @@ typedef struct NV906F_CTRL_GET_CLASS_ENGINEID_PARAMS {
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* resetReason
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* Specifies reason to reset a channel.
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*
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* bIsRcPending
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* Specifies if an RC is pending on the channel
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*
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* Possible status values returned are:
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* NV_OK
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*/
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@@ -138,9 +141,10 @@ typedef struct NV906F_CTRL_GET_CLASS_ENGINEID_PARAMS {
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#define NV906F_CTRL_CMD_RESET_CHANNEL_PARAMS_MESSAGE_ID (0x2U)
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typedef struct NV906F_CTRL_CMD_RESET_CHANNEL_PARAMS {
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NvU32 engineID;
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NvU32 subdeviceInstance;
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NvU32 resetReason;
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NvU32 engineID;
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NvU32 subdeviceInstance;
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NvU32 resetReason;
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NvBool bIsRcPending;
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} NV906F_CTRL_CMD_RESET_CHANNEL_PARAMS;
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/*
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