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https://github.com/NVIDIA/open-gpu-kernel-modules.git
synced 2026-01-31 13:39:47 +00:00
550.40.07
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@@ -195,8 +195,8 @@ NvU32 nvGenerateUnixRmHandleInternal(NVUnixRmHandleAllocatorPtr pAllocator)
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/* Find free handle */
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handleId = 1;
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while (USED(pAllocator->bitmap, handleId) &&
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(handleId <= pAllocator->maxHandles)) {
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while ((handleId <= pAllocator->maxHandles) &&
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USED(pAllocator->bitmap, handleId)) {
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handleId++;
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}
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@@ -72,6 +72,18 @@ static inline void nvPushSetMethodDataU64(NvPushChannelPtr p, const NvU64 data)
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__nvPushSetMethodDataSegmentU64(&p->main, data);
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}
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/* Little-endian: least significant bits first. */
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static inline void __nvPushSetMethodDataSegmentU64LE(NvPushChannelSegmentPtr s, const NvU64 data)
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{
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__nvPushSetMethodDataSegment(s, NvU64_LO32(data));
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__nvPushSetMethodDataSegment(s, NvU64_HI32(data));
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}
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static inline void nvPushSetMethodDataU64LE(NvPushChannelPtr p, const NvU64 data)
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{
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__nvPushSetMethodDataSegmentU64LE(&p->main, data);
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}
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void __nvPushMoveDWORDS(NvU32* dst, const NvU32* src, int dwords);
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static inline void
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@@ -332,13 +332,7 @@ static void InsertProgressTracker(NvPushChannelPtr p, NvU32 putOffset,
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DRF_DEF(C36F, _SEM_EXECUTE, _RELEASE_WFI, _DIS));
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__nvPushStart(p, progressTracker, 0, NVC36F_SEM_ADDR_LO, 5, _INC_METHOD);
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/*
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* NVC36F_SEM_ADDR_{LO,HI} is backwards from most 64-bit
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* addresses spread over two methods, so we cannot use
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* __nvPushSetMethodDataSegmentU64().
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*/
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__nvPushSetMethodDataSegment(segment, NvU64_LO32(p->progressSemaphore.gpuVA));
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__nvPushSetMethodDataSegment(segment, NvU64_HI32(p->progressSemaphore.gpuVA));
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__nvPushSetMethodDataSegmentU64LE(segment, p->progressSemaphore.gpuVA);
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__nvPushSetMethodDataSegment(segment, payload);
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__nvPushSetMethodDataSegment(segment, 0);
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__nvPushSetMethodDataSegment(segment, semaphoreOperation);
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@@ -638,11 +632,16 @@ NvBool __nvPushTestPushBuffer(NvPushChannelPtr p)
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/*
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* Immediately after allocating the pushbuffer, push a channel NOP and
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* babysit the channel until it's consumed as a quick sanity check.
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* Note we use a full long timeout (10 seconds) when performing this
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* sanity test. In normal operation, idling will happen very quickly.
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* However, when the GPU is under heavy load in stress tests, it can
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* take much longer to idle the channel.
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*/
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WriteGetOffset(p, 0);
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ret = IdleChannel(p, FALSE /* progressTrackerWFI */,
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NV_PUSH_NOTIFIER_SHORT_TIMEOUT);
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NV_PUSH_NOTIFIER_LONG_TIMEOUT);
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if (!ret) {
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nvPushImportLogError(p->pDevice, "Failed to initialize DMA.");
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@@ -1047,10 +1046,8 @@ static void VoltaReleaseTimelineSemaphore(
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NvU64 val)
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{
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nvPushMethod(p, 0, NVC36F_SEM_ADDR_LO, 5);
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nvPushSetMethodData(p, NvU64_LO32(gpuAddress));
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nvPushSetMethodData(p, NvU64_HI32(gpuAddress)); // NVC36F_SEM_ADDR_HI
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nvPushSetMethodData(p, NvU64_LO32(val)); // NVC36F_SEM_PAYLOAD_LO
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nvPushSetMethodData(p, NvU64_HI32(val)); // NVC36F_SEM_PAYLOAD_HI
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nvPushSetMethodDataU64LE(p, gpuAddress); // NVC36F_SEM_ADDR_LO/HI
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nvPushSetMethodDataU64LE(p, val); // NVC36F_SEM_PAYLOAD_LO/HI
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nvPushSetMethodData(p, // NVC36F_SEM_EXECUTE
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DRF_DEF(C36F, _SEM_EXECUTE, _OPERATION, _RELEASE) |
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DRF_DEF(C36F, _SEM_EXECUTE, _RELEASE_WFI, _EN) |
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@@ -1067,10 +1064,8 @@ static void VoltaAcquireTimelineSemaphore(
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NvU64 val)
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{
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nvPushMethod(p, 0, NVC36F_SEM_ADDR_LO, 5);
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nvPushSetMethodData(p, NvU64_LO32(gpuAddress));
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nvPushSetMethodData(p, NvU64_HI32(gpuAddress)); // NVC36F_SEM_ADDR_HI
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nvPushSetMethodData(p, NvU64_LO32(val)); // NVC36F_SEM_PAYLOAD_LO
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nvPushSetMethodData(p, NvU64_HI32(val)); // NVC36F_SEM_PAYLOAD_HI
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nvPushSetMethodDataU64LE(p, gpuAddress); // NVC36F_SEM_ADDR_LO/HI
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nvPushSetMethodDataU64LE(p, val); // NVC36F_SEM_PAYLOAD_LO/HI
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nvPushSetMethodData(p, // NVC36F_SEM_EXECUTE
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DRF_DEF(C36F, _SEM_EXECUTE, _OPERATION, _ACQ_STRICT_GEQ) |
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DRF_DEF(C36F, _SEM_EXECUTE, _ACQUIRE_SWITCH_TSG, _EN) |
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