mirror of
https://github.com/NVIDIA/open-gpu-kernel-modules.git
synced 2026-02-25 09:23:59 +00:00
550.40.07
This commit is contained in:
Bernhard Stoeckner
@@ -64,33 +64,153 @@ typedef struct RPC_OBJ_IFACES {
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// Typedefs for RPC HAL interfaces.
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//
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typedef NV_STATUS RpcCtrlFifoSetupVfZombieSubctxPdb(POBJGPU, POBJRPC, NvHandle, NvHandle, void*);
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typedef NV_STATUS RpcVgpuPfRegRead32(POBJGPU, POBJRPC, NvU64, NvU32*, NvU32);
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typedef NV_STATUS RpcCtrlBusUnsetP2pMapping(POBJGPU, POBJRPC, NvHandle, NvHandle, void*);
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typedef NV_STATUS RpcDumpProtobufComponent(POBJGPU, POBJRPC, PRB_ENCODER *pPrbEnc, NVD_STATE *pNvDumpState, NVDUMP_COMPONENT component);
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typedef NV_STATUS RpcEccNotifierWriteAck(POBJGPU, POBJRPC);
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typedef NV_STATUS RpcAllocMemory(POBJGPU, POBJRPC, NvHandle, NvHandle, NvHandle,
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NvU32, NvU32, MEMORY_DESCRIPTOR*);
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typedef NV_STATUS RpcCtrlDbgReadSingleSmErrorState(POBJGPU, POBJRPC, NvHandle, NvHandle, void*);
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typedef NV_STATUS RpcDisableChannels(POBJGPU, POBJRPC, NvU32);
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typedef NV_STATUS RpcGpuExecRegOps(POBJGPU, POBJRPC, NvHandle, NvHandle,
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NV2080_CTRL_GPU_EXEC_REG_OPS_PARAMS*, NV2080_CTRL_GPU_REG_OP*);
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typedef NV_STATUS RpcRmfsInit(POBJGPU, POBJRPC, PMEMORY_DESCRIPTOR);
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typedef NV_STATUS RpcCtrlGpuPromoteCtx(POBJGPU, POBJRPC, NvHandle, NvHandle, void*);
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typedef NV_STATUS RpcCtrlDbgSetNextStopTriggerType(POBJGPU, POBJRPC, NvHandle, NvHandle, void*);
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typedef NV_STATUS RpcAllocShareDevice(POBJGPU, POBJRPC, NvHandle, NvHandle, NvHandle,
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NvHandle, NvHandle, NvU32, NvU32, NvU64, NvU32);
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typedef NV_STATUS RpcCtrlPreempt(POBJGPU, POBJRPC, NvHandle, NvHandle, void*);
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typedef NV_STATUS RpcCtrlGpuInitializeCtx(POBJGPU, POBJRPC, NvHandle, NvHandle, void*);
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typedef NV_STATUS RpcCtrlReservePmAreaSmpc(POBJGPU, POBJRPC, NvHandle, NvHandle, void*);
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typedef NV_STATUS RpcCtrlGpuMigratableOps(POBJGPU, POBJRPC, NvHandle, NvHandle, void*);
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typedef NV_STATUS RpcCtrlDbgSetModeErrbarDebug(POBJGPU, POBJRPC, NvHandle, NvHandle, void*);
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typedef NV_STATUS RpcCtrlPmaStreamUpdateGetPut(POBJGPU, POBJRPC, NvHandle, NvHandle, void*);
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typedef NV_STATUS RpcCtrlFabricMemoryDescribe(POBJGPU, POBJRPC, NvHandle, NvHandle, void*);
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typedef NV_STATUS RpcAllocChannelDma(POBJGPU, POBJRPC, NvHandle, NvHandle, NvHandle,
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NvU32, NV_CHANNEL_ALLOC_PARAMS*, NvU32*);
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typedef NV_STATUS RpcCtrlSetZbcDepthClear(POBJGPU, POBJRPC, NvHandle, NvHandle, void*);
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typedef NV_STATUS RpcCtrlResetIsolatedChannel(POBJGPU, POBJRPC, NvHandle, NvHandle, void*);
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typedef NV_STATUS RpcCtrlDmaSetDefaultVaspace(POBJGPU, POBJRPC, NvHandle, NvHandle, void*);
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typedef NV_STATUS RpcAllocSubdevice(POBJGPU, POBJRPC, NvHandle, NvHandle, NvHandle, NvU32, NvU32);
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typedef NV_STATUS RpcFree(POBJGPU, POBJRPC, NvHandle, NvHandle, NvHandle);
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typedef NV_STATUS RpcDmaControl(POBJGPU, POBJRPC, NvHandle, NvHandle, NvU32, void*, NvU32);
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typedef NV_STATUS RpcCtrlDbgClearSingleSmErrorState(POBJGPU, POBJRPC, NvHandle, NvHandle, void*);
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typedef NV_STATUS RpcUnsetPageDirectory(POBJGPU, POBJRPC, NvHandle, NvHandle,
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NV0080_CTRL_DMA_UNSET_PAGE_DIRECTORY_PARAMS*);
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typedef NV_STATUS RpcGetGspStaticInfo(POBJGPU, POBJRPC);
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typedef NV_STATUS RpcSaveHibernationData(POBJGPU, POBJRPC);
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typedef NV_STATUS RpcDupObject(POBJGPU, POBJRPC, NvHandle, NvHandle, NvHandle,
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NvHandle, NvHandle, NvU32);
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typedef NV_STATUS RpcGspSetSystemInfo(POBJGPU, POBJRPC);
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typedef NV_STATUS RpcRmfsCleanup(POBJGPU, POBJRPC);
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typedef NV_STATUS RpcCtrlPmAreaPcSampler(POBJGPU, POBJRPC, NvHandle, NvHandle, NvU32, void*);
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typedef NV_STATUS RpcCtrlDbgSetExceptionMask(POBJGPU, POBJRPC, NvHandle, NvHandle, void*);
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typedef NV_STATUS RpcCtrlVaspaceCopyServerReservedPdes(POBJGPU, POBJRPC, NvHandle, NvHandle, void*);
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typedef NV_STATUS RpcCtrlGrCtxswPreemptionBind(POBJGPU, POBJRPC, NvHandle, NvHandle, void*);
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typedef NV_STATUS RpcCtrlAllocPmaStream(POBJGPU, POBJRPC, NvHandle, NvHandle, void*);
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typedef NV_STATUS RpcCtrlReserveHwpmLegacy(POBJGPU, POBJRPC, NvHandle, NvHandle, void*);
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typedef NV_STATUS RpcCtrlInternalQuiescePmaChannel(POBJGPU, POBJRPC, NvHandle, NvHandle, void*);
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typedef NV_STATUS RpcCtrlPerfRatedTdpGetStatus(POBJGPU, POBJRPC, NvHandle, NvHandle, void*);
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typedef NV_STATUS RpcCtrlBusSetP2pMapping(POBJGPU, POBJRPC, NvHandle, NvHandle, void*);
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typedef NV_STATUS RpcCtrlGpuGetInfoV2(POBJGPU, POBJRPC, NvHandle, NvHandle, void*);
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typedef NV_STATUS RpcCtrlGetHsCredits(POBJGPU, POBJRPC, NvHandle, NvHandle, void*);
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typedef NV_STATUS RpcCtrlGrSetCtxswPreemptionMode(POBJGPU, POBJRPC, NvHandle, NvHandle, void*);
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typedef NV_STATUS RpcCtrlB0ccExecRegOps(POBJGPU, POBJRPC, NvHandle, NvHandle, void*);
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typedef NV_STATUS RpcCtrlGrmgrGetGrFsInfo(POBJGPU, POBJRPC, NvHandle, NvHandle, void*);
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typedef NV_STATUS RpcCtrlGetZbcClearTable(POBJGPU, POBJRPC, NvHandle, NvHandle, void*);
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typedef NV_STATUS RpcCleanupSurface(POBJGPU, POBJRPC,
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NVA080_CTRL_VGPU_DISPLAY_CLEANUP_SURFACE_PARAMS*);
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typedef NV_STATUS RpcCtrlSetTimeslice(POBJGPU, POBJRPC, NvHandle, NvHandle, void*);
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typedef NV_STATUS RpcCtrlGpuQueryEccStatus(POBJGPU, POBJRPC, NvHandle, NvHandle, void*);
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typedef NV_STATUS RpcCtrlDbgGetModeMmuDebug(POBJGPU, POBJRPC, NvHandle, NvHandle, void*);
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typedef NV_STATUS RpcCtrlDbgClearAllSmErrorStates(POBJGPU, POBJRPC, NvHandle, NvHandle, void*);
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typedef NV_STATUS RpcVgpuGspRingDoorbell(POBJGPU, NvU32);
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typedef NV_STATUS RpcCtrlGrSetTpcPartitionMode(POBJGPU, POBJRPC, NvHandle, NvHandle, void*);
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typedef NV_STATUS RpcCtrlGetTotalHsCredits(POBJGPU, POBJRPC, NvHandle, NvHandle, void*);
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typedef NV_STATUS RpcCtrlInternalPromoteFaultMethodBuffers(OBJGPU *, OBJRPC *, NvHandle, NvHandle, void *);
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typedef NV_STATUS RpcCtrlFbGetInfoV2(POBJGPU, POBJRPC, NvHandle, NvHandle, void*);
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typedef NV_STATUS RpcVgpuGspWriteScratchRegister(POBJGPU, NvU64);
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typedef NV_STATUS RpcSetPageDirectory(POBJGPU, POBJRPC, NvHandle, NvHandle,
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NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_PARAMS*);
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typedef NV_STATUS RpcCtrlGetP2pCapsV2(POBJGPU, POBJRPC, void*);
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typedef NV_STATUS RpcCtrlNvlinkGetInbandReceivedData(POBJGPU, POBJRPC, NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_PARAMS*, NvU16, NvBool*);
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typedef NV_STATUS RpcCtrlGetCePceMask(POBJGPU, POBJRPC, NvHandle, NvHandle, void*);
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typedef NV_STATUS RpcCtrlGetNvlinkPeerIdMask(POBJGPU, POBJRPC, NvHandle, NvHandle, void*);
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typedef NV_STATUS RpcCtrlGpuEvictCtx(POBJGPU, POBJRPC, NvHandle, NvHandle, void*);
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typedef NV_STATUS RpcCtrlGetMmuDebugMode(POBJGPU, POBJRPC, NvHandle, NvHandle, void*);
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typedef NV_STATUS RpcInvalidateTlb(POBJGPU, POBJRPC, NvU64, NvU32);
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typedef NV_STATUS RpcCtrlDbgSetSingleSmSingleStep(POBJGPU, POBJRPC, NvHandle, NvHandle, void*);
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typedef NV_STATUS RpcUnloadingGuestDriver(POBJGPU, POBJRPC, NvBool, NvBool, NvU32);
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typedef NV_STATUS RpcGetEngineUtilizationWrapper(POBJGPU, POBJRPC, NvHandle, NvHandle, NvU32, void*, NvU32);
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typedef NV_STATUS RpcGetConsolidatedGrStaticInfo(POBJGPU, POBJRPC);
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typedef NV_STATUS RpcSwitchToVga(POBJGPU, POBJRPC);
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typedef NV_STATUS RpcCtrlResetChannel(POBJGPU, POBJRPC, NvHandle, NvHandle, void*);
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typedef NV_STATUS RpcCtrlGpfifoSchedule(POBJGPU, POBJRPC, NvHandle, NvHandle, NvU32, void*);
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typedef NV_STATUS RpcSetRegistry(POBJGPU, POBJRPC);
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typedef NV_STATUS RpcRmfsCloseQueue(POBJGPU, POBJRPC);
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typedef NV_STATUS RpcGetStaticInfo(POBJGPU, POBJRPC);
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typedef NV_STATUS RpcCtrlGetNvlinkStatus(POBJGPU, POBJRPC, NvHandle, NvHandle, void*);
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typedef NV_STATUS RpcGetStaticData(POBJGPU, POBJRPC);
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typedef NV_STATUS RpcCtrlGrGetTpcPartitionMode(POBJGPU, POBJRPC, NvHandle, NvHandle, void*);
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typedef NV_STATUS RpcCtrlStopChannel(POBJGPU, POBJRPC, NvHandle, NvHandle, void*);
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typedef NV_STATUS RpcSetSurfaceProperties(POBJGPU, POBJRPC, NvHandle,
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NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES*,
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NvBool);
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typedef NV_STATUS RpcCtrlGpfifoSetWorkSubmitTokenNotifIndex(POBJGPU, POBJRPC, NvHandle, NvHandle, void*);
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typedef NV_STATUS RpcCtrlTimerSetGrTickFreq(POBJGPU, POBJRPC, NvHandle, NvHandle, void*);
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typedef NV_STATUS RpcAllocEvent(POBJGPU, POBJRPC, NvHandle, NvHandle, NvHandle,
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NvHandle, NvHandle, NvU32, NvU32);
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typedef NV_STATUS RpcCtrlGrPcSamplingMode(POBJGPU, POBJRPC, NvHandle, NvHandle, void*);
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typedef NV_STATUS RpcCtrlMcServiceInterrupts(POBJGPU, POBJRPC, NvHandle, NvHandle, void*);
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typedef NV_STATUS RpcCtrlDbgReadAllSmErrorStates(POBJGPU, POBJRPC, NvHandle, NvHandle, void*);
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typedef NV_STATUS RpcCtrlSetZbcColorClear(POBJGPU, POBJRPC, NvHandle, NvHandle, void*);
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typedef NV_STATUS RpcGetEncoderCapacity(POBJGPU, POBJRPC, NvHandle, NvHandle, NvU32*);
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typedef NV_STATUS RpcCtrlGetP2pCaps(POBJGPU, POBJRPC, NvHandle, NvHandle, void*);
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typedef NV_STATUS RpcPerfGetLevelInfo(POBJGPU, POBJRPC, NvHandle, NvHandle,
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NV2080_CTRL_PERF_GET_LEVEL_INFO_PARAMS*,
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NV2080_CTRL_PERF_GET_CLK_INFO*);
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typedef NV_STATUS RpcAllocObject(POBJGPU, POBJRPC, NvHandle, NvHandle, NvHandle, NvU32, void*);
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typedef NV_STATUS RpcCtrlGpuHandleVfPriFault(POBJGPU, POBJRPC, NvHandle, NvHandle, void*);
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typedef NV_STATUS RpcRmApiControl(POBJGPU, POBJRPC, NvHandle, NvHandle, NvU32, void*, NvU32);
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typedef NV_STATUS RpcCtrlFabricMemStats(POBJGPU, POBJRPC, NvHandle, NvHandle, void*);
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typedef NV_STATUS RpcCtrlGrCtxswZcullBind(POBJGPU, POBJRPC, NvHandle, NvHandle, void*);
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typedef NV_STATUS RpcCtrlInternalMemsysSetZbcReferenced(POBJGPU, POBJRPC, NvHandle, NvHandle, void*);
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typedef NV_STATUS RpcCtrlPerfRatedTdpSetControl(POBJGPU, POBJRPC, NvHandle, NvHandle, void*);
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typedef NV_STATUS RpcCtrlExecPartitionsCreate(POBJGPU, POBJRPC, NvHandle, NvHandle, void*);
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typedef NV_STATUS RpcCtrlGpfifoGetWorkSubmitToken(POBJGPU, POBJRPC, NvHandle, NvHandle, void*);
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typedef NV_STATUS RpcIdleChannels(OBJGPU *, OBJRPC *, NvHandle *phclients,
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NvHandle *phdevices, NvHandle *phchannels,
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NvU32 nentries, NvU32 flags, NvU32 timeout);
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typedef NV_STATUS RpcCtrlCmdInternalGpuStartFabricProbe(POBJGPU, POBJRPC, NV2080_CTRL_CMD_INTERNAL_START_GPU_FABRIC_PROBE_INFO_PARAMS*);
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typedef NV_STATUS RpcGetBrandCaps(POBJGPU, POBJRPC, NvHandle, NvHandle, NvU32, void*, NvU32);
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typedef NV_STATUS RpcRestoreHibernationData(POBJGPU, POBJRPC);
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typedef NV_STATUS RpcCtrlFlaSetupInstanceMemBlock(POBJGPU, POBJRPC, NvHandle, NvHandle, void*);
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typedef NV_STATUS RpcCtrlInternalSriovPromotePmaStream(POBJGPU, POBJRPC, NvHandle, NvHandle, void*);
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typedef NV_STATUS RpcCtrlFbGetFsInfo(POBJGPU, POBJRPC, NvHandle, NvHandle, void*);
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typedef NV_STATUS RpcCtrlSetChannelInterleaveLevel(POBJGPU, POBJRPC, NvHandle, NvHandle, void*);
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typedef NV_STATUS RpcCtrlDbgResumeContext(POBJGPU, POBJRPC, NvHandle, NvHandle);
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typedef NV_STATUS RpcAllocRoot(POBJGPU, POBJRPC, NvHandle);
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typedef NV_STATUS RpcCtrlFifoDisableChannels(POBJGPU, POBJRPC, NvHandle, NvHandle, void*);
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typedef NV_STATUS RpcCtrlSetHsCredits(POBJGPU, POBJRPC, NvHandle, NvHandle, void*);
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typedef NV_STATUS RpcGetEngineUtilization(POBJGPU, POBJRPC, NvHandle,
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NvHandle, NvU32, void*, NvU32);
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typedef NV_STATUS RpcCtrlGetZbcClearTableEntry(POBJGPU, POBJRPC, NvHandle, NvHandle, void*);
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typedef NV_STATUS RpcCtrlNvencSwSessionUpdateInfo(POBJGPU, POBJRPC, NvHandle, NvHandle, void*);
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typedef NV_STATUS RpcCtrlDbgSuspendContext(POBJGPU, POBJRPC, NvHandle, NvHandle, void*);
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typedef NV_STATUS RpcCtrlGetP2pCapsMatrix(POBJGPU, POBJRPC, NvHandle, NvHandle, void*);
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typedef NV_STATUS RpcCtrlDbgExecRegOps(POBJGPU, POBJRPC, NvHandle, NvHandle, void*);
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typedef NV_STATUS RpcCtrlFreePmaStream(POBJGPU, POBJRPC, NvHandle, NvHandle, void*);
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typedef NV_STATUS RpcCtrlSetTsgInterleaveLevel(POBJGPU, POBJRPC, NvHandle, NvHandle, void*);
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typedef NV_STATUS RpcCtrlMasterGetVirtualFunctionErrorContIntrMask(POBJGPU, POBJRPC, NvHandle, NvHandle, void*);
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typedef NV_STATUS RpcLog(POBJGPU, POBJRPC, const char*, NvU32);
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typedef NV_STATUS RpcCtrlExecPartitionsDelete(POBJGPU, POBJRPC, NvHandle, NvHandle, void*);
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typedef NV_STATUS RpcCtrlPerfBoost(POBJGPU, POBJRPC, NvHandle, NvHandle, void*);
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typedef NV_STATUS RpcCtrlDbgSetModeMmuDebug(POBJGPU, POBJRPC, NvHandle, NvHandle, void*);
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typedef NV_STATUS RpcCtrlFifoSetChannelProperties(POBJGPU, POBJRPC, NvHandle, NvHandle, void*);
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typedef NV_STATUS RpcCtrlSubdeviceGetP2pCaps(POBJGPU, POBJRPC, NvHandle, NvHandle, void*);
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typedef NV_STATUS RpcUpdateBarPde(POBJGPU, POBJRPC, NV_RPC_UPDATE_PDE_BAR_TYPE, NvU64, NvU64);
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typedef NV_STATUS RpcCtrlBindPmResources(POBJGPU, POBJRPC, NvHandle, NvHandle);
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typedef NV_STATUS RpcMapMemoryDma(POBJGPU, POBJRPC, NvHandle, NvHandle, NvHandle,
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NvHandle, NvU64, NvU64, NvU32, NvU64*);
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typedef NV_STATUS RpcUnmapMemoryDma(POBJGPU, POBJRPC, NvHandle, NvHandle, NvHandle, NvHandle, NvU32, NvU64);
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typedef NV_STATUS RpcRmfsTest(POBJGPU, POBJRPC, NvU32, NvU32, NvU32, NvU32);
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typedef NV_STATUS RpcSetGuestSystemInfoExt(POBJGPU, POBJRPC);
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typedef NV_STATUS Rpc_iGrp_ipVersions_getInfo(IGRP_IP_VERSIONS_TABLE_INFO *);
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@@ -99,26 +219,136 @@ typedef NV_STATUS Rpc_iGrp_ipVersions_getInfo(IGRP_IP_VERSIONS_TABLE_INFO *
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//
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typedef struct RPC_HAL_IFACES {
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RpcCtrlFifoSetupVfZombieSubctxPdb *rpcCtrlFifoSetupVfZombieSubctxPdb; /* CTRL_FIFO_SETUP_VF_ZOMBIE_SUBCTX_PDB */
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RpcVgpuPfRegRead32 *rpcVgpuPfRegRead32; /* Read reg value from plugin */
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RpcCtrlBusUnsetP2pMapping *rpcCtrlBusUnsetP2pMapping; /* CTRL_BUS_UNSET_P2P_MAPPING */
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RpcDumpProtobufComponent *rpcDumpProtobufComponent; /* Dump a GSP component into the protobuf. */
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RpcEccNotifierWriteAck *rpcEccNotifierWriteAck; /* ECC_NOTIFIER_WRITE_ACK */
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RpcAllocMemory *rpcAllocMemory; /* ALLOC_MEMORY */
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RpcCtrlDbgReadSingleSmErrorState *rpcCtrlDbgReadSingleSmErrorState; /* CTRL_DBG_READ_SINGLE_SM_ERROR_STATE */
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RpcDisableChannels *rpcDisableChannels; /* Disable channels */
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RpcGpuExecRegOps *rpcGpuExecRegOps; /* GPU_EXEC_REG_OPS */
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RpcRmfsInit *rpcRmfsInit; /* Resman File Streaming Init */
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RpcCtrlGpuPromoteCtx *rpcCtrlGpuPromoteCtx; /* GPU_PROMOTE_CTX */
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RpcCtrlDbgSetNextStopTriggerType *rpcCtrlDbgSetNextStopTriggerType; /* CTRL_DBG_SET_NEXT_STOP_TRIGGER_TYPE */
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RpcAllocShareDevice *rpcAllocShareDevice; /* ALLOC_SHARE_DEVICE */
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RpcCtrlPreempt *rpcCtrlPreempt; /* CTRL_PREEMPT */
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RpcCtrlGpuInitializeCtx *rpcCtrlGpuInitializeCtx; /* CTRL_GPU_INITIALIZE_CTX */
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RpcCtrlReservePmAreaSmpc *rpcCtrlReservePmAreaSmpc; /* CTRL_RESERVE_PM_AREA_SMPC */
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RpcCtrlGpuMigratableOps *rpcCtrlGpuMigratableOps; /* NV2080_CTRL_CMD_GPU_MIGRATABLE_OPS */
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RpcCtrlDbgSetModeErrbarDebug *rpcCtrlDbgSetModeErrbarDebug; /* CTRL_DBG_SET_MODE_ERRBAR_DEBUG */
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RpcCtrlPmaStreamUpdateGetPut *rpcCtrlPmaStreamUpdateGetPut; /* CTRL_HWPM_STREAMOUT_UPDATE_GET_PUT */
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RpcCtrlFabricMemoryDescribe *rpcCtrlFabricMemoryDescribe; /* CTRL_FABRIC_MEMORY_DESCRIBE */
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RpcAllocChannelDma *rpcAllocChannelDma; /* ALLOC_CHANNEL_DMA */
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RpcCtrlSetZbcDepthClear *rpcCtrlSetZbcDepthClear; /* CTRL_SET_ZBC_DEPTH_CLEAR */
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RpcCtrlResetIsolatedChannel *rpcCtrlResetIsolatedChannel; /* CTRL_RESET_ISOLATED_CHANNEL */
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RpcCtrlDmaSetDefaultVaspace *rpcCtrlDmaSetDefaultVaspace; /* CTRL_DMA_SET_DEFAULT_VASPACE */
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RpcAllocSubdevice *rpcAllocSubdevice; /* ALLOC_SUBDEVICE */
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RpcFree *rpcFree; /* FREE */
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RpcDmaControl *rpcDmaControl; /* DMA_CONTROL */
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RpcCtrlDbgClearSingleSmErrorState *rpcCtrlDbgClearSingleSmErrorState; /* CTRL_DBG_CLEAR_SINGLE_SM_ERROR_STATE */
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RpcUnsetPageDirectory *rpcUnsetPageDirectory; /* UNSET_PAGE_DIRECTORY */
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RpcGetGspStaticInfo *rpcGetGspStaticInfo; /* Get static info from GSP RM. */
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RpcSaveHibernationData *rpcSaveHibernationData; /* SAVE_HIBERNATION_DATA */
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RpcDupObject *rpcDupObject; /* DUP_OBJECT */
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RpcGspSetSystemInfo *rpcGspSetSystemInfo; /* Tells GSP-RM about the overall system environment */
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RpcRmfsCleanup *rpcRmfsCleanup; /* Resman File Cleanup */
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RpcCtrlPmAreaPcSampler *rpcCtrlPmAreaPcSampler; /* CTRL_PM_AREA_PC_SAMPLER */
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RpcCtrlDbgSetExceptionMask *rpcCtrlDbgSetExceptionMask; /* CTRL_DBG_SET_EXCEPTION_MASK */
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RpcCtrlVaspaceCopyServerReservedPdes *rpcCtrlVaspaceCopyServerReservedPdes; /* CTRL_VASPACE_COPY_SERVER_RESERVED_PDES */
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RpcCtrlGrCtxswPreemptionBind *rpcCtrlGrCtxswPreemptionBind; /* CTRL_GR_CTXSW_PREEMPTION_BIND */
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RpcCtrlAllocPmaStream *rpcCtrlAllocPmaStream; /* CTRL_ALLOC_PMA_STREAM */
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RpcCtrlReserveHwpmLegacy *rpcCtrlReserveHwpmLegacy; /* CTRL_RESERVE_HWPM_LEGACY */
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RpcCtrlInternalQuiescePmaChannel *rpcCtrlInternalQuiescePmaChannel; /* CTRL_INTERNAL_QUIESCE_PMA_CHANNEL */
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RpcCtrlPerfRatedTdpGetStatus *rpcCtrlPerfRatedTdpGetStatus; /* CTRL_PERF_RATED_TDP_GET_STATUS */
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RpcCtrlBusSetP2pMapping *rpcCtrlBusSetP2pMapping; /* CTRL_BUS_SET_P2P_MAPPING */
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RpcCtrlGpuGetInfoV2 *rpcCtrlGpuGetInfoV2; /* CTRL_GPU_GET_INFO_V2 */
|
||||
RpcCtrlGetHsCredits *rpcCtrlGetHsCredits; /* CTRL_GET_HS_CREDITS */
|
||||
RpcCtrlGrSetCtxswPreemptionMode *rpcCtrlGrSetCtxswPreemptionMode; /* CTRL_GR_SET_CTXSW_PREEMPTION_MODE */
|
||||
RpcCtrlB0ccExecRegOps *rpcCtrlB0ccExecRegOps; /* CTRL_B0CC_EXEC_REG_OPS */
|
||||
RpcCtrlGrmgrGetGrFsInfo *rpcCtrlGrmgrGetGrFsInfo; /* CTRL_GRMGR_GET_GR_FS_INFO */
|
||||
RpcCtrlGetZbcClearTable *rpcCtrlGetZbcClearTable; /* CTRL_GET_ZBC_CLEAR_TABLE */
|
||||
RpcCleanupSurface *rpcCleanupSurface; /* CLEANUP_SURFACE */
|
||||
RpcCtrlSetTimeslice *rpcCtrlSetTimeslice; /* CTRL_SET_TIMESLICE */
|
||||
RpcCtrlGpuQueryEccStatus *rpcCtrlGpuQueryEccStatus; /* CTRL_GPU_QUERY_ECC_STATUS */
|
||||
RpcCtrlDbgGetModeMmuDebug *rpcCtrlDbgGetModeMmuDebug; /* CTRL_DBG_GET_MODE_MMU_DEBUG */
|
||||
RpcCtrlDbgClearAllSmErrorStates *rpcCtrlDbgClearAllSmErrorStates; /* CTRL_DBG_CLEAR_ALL_SM_ERROR_STATES */
|
||||
RpcVgpuGspRingDoorbell *rpcVgpuGspRingDoorbell; /* Ring the doorbell register */
|
||||
RpcCtrlGrSetTpcPartitionMode *rpcCtrlGrSetTpcPartitionMode; /* CTRL_GR_SET_TPC_PARTITION_MODE */
|
||||
RpcCtrlGetTotalHsCredits *rpcCtrlGetTotalHsCredits; /* CTRL_GET_TOTAL_HS_CREDITS */
|
||||
RpcCtrlInternalPromoteFaultMethodBuffers *rpcCtrlInternalPromoteFaultMethodBuffers; /* CTRL_INTERNAL_PROMOTE_FAULT_METHOD_BUFFERS */
|
||||
RpcCtrlFbGetInfoV2 *rpcCtrlFbGetInfoV2; /* CTRL_FB_GET_INFO_V2 */
|
||||
RpcVgpuGspWriteScratchRegister *rpcVgpuGspWriteScratchRegister; /* Write the vGPU GSP scratch register */
|
||||
RpcSetPageDirectory *rpcSetPageDirectory; /* SET_PAGE_DIRECTORY */
|
||||
RpcCtrlGetP2pCapsV2 *rpcCtrlGetP2pCapsV2; /* CTRL_GET_P2P_CAPS_V2 */
|
||||
RpcCtrlNvlinkGetInbandReceivedData *rpcCtrlNvlinkGetInbandReceivedData; /* CTRL_NVLINK_GET_INBAND_RECEIVED_DATA */
|
||||
RpcCtrlGetCePceMask *rpcCtrlGetCePceMask; /* CTRL_GET_CE_PCE_MASK */
|
||||
RpcCtrlGetNvlinkPeerIdMask *rpcCtrlGetNvlinkPeerIdMask; /* CTRL_GET_NVLINK_PEER_ID_MASK */
|
||||
RpcCtrlGpuEvictCtx *rpcCtrlGpuEvictCtx; /* CTRL_GPU_EVICT_CTX */
|
||||
RpcCtrlGetMmuDebugMode *rpcCtrlGetMmuDebugMode; /* CTRL_GET_MMU_DEBUG_MODE */
|
||||
RpcInvalidateTlb *rpcInvalidateTlb; /* INVALIDATE_TLB */
|
||||
RpcCtrlDbgSetSingleSmSingleStep *rpcCtrlDbgSetSingleSmSingleStep; /* CTRL_DBG_SET_SINGLE_SM_SINGLE_STEP */
|
||||
RpcUnloadingGuestDriver *rpcUnloadingGuestDriver; /* UNLOADING_GUEST_DRIVER */
|
||||
RpcGetEngineUtilizationWrapper *rpcGetEngineUtilizationWrapper; /* Get engine utilization wrapper */
|
||||
RpcGetConsolidatedGrStaticInfo *rpcGetConsolidatedGrStaticInfo; /* GET_CONSOLIDATED_GR_STATIC_INFO */
|
||||
RpcSwitchToVga *rpcSwitchToVga; /* SWITCH_TO_VGA */
|
||||
RpcCtrlResetChannel *rpcCtrlResetChannel; /* CTRL_RESET_CHANNEL */
|
||||
RpcCtrlGpfifoSchedule *rpcCtrlGpfifoSchedule; /* CTRL_GPFIFO_SCHEDULE */
|
||||
RpcSetRegistry *rpcSetRegistry; /* GSP Init Set registry values */
|
||||
RpcRmfsCloseQueue *rpcRmfsCloseQueue; /* Resman File Streaming Close Queue */
|
||||
RpcGetStaticInfo *rpcGetStaticInfo; /* GET_STATIC_INFO */
|
||||
RpcCtrlGetNvlinkStatus *rpcCtrlGetNvlinkStatus; /* CTRL_NVLINK_GET_NVLINK_STATUS */
|
||||
RpcGetStaticData *rpcGetStaticData; /* GET_STATIC_DATA published for OpenRM */
|
||||
RpcCtrlGrGetTpcPartitionMode *rpcCtrlGrGetTpcPartitionMode; /* CTRL_GR_GET_TPC_PARTITION_MODE */
|
||||
RpcCtrlStopChannel *rpcCtrlStopChannel; /* CTRL_STOP_CHANNEL */
|
||||
RpcSetSurfaceProperties *rpcSetSurfaceProperties; /* SET_SURFACE_PROPERTIES */
|
||||
RpcCtrlGpfifoSetWorkSubmitTokenNotifIndex *rpcCtrlGpfifoSetWorkSubmitTokenNotifIndex; /* CTRL_GPFIFO_SET_WORK_SUBMIT_TOKEN_NOTIF_INDEX */
|
||||
RpcCtrlTimerSetGrTickFreq *rpcCtrlTimerSetGrTickFreq; /* CTRL_TIMER_SET_GR_TICK_FREQ */
|
||||
RpcAllocEvent *rpcAllocEvent; /* ALLOC_EVENT */
|
||||
RpcCtrlGrPcSamplingMode *rpcCtrlGrPcSamplingMode; /* CTRL_GR_PC_SAMPLING_MODE */
|
||||
RpcCtrlMcServiceInterrupts *rpcCtrlMcServiceInterrupts; /* CTRL_MC_SERVICE_INTERRUPTS */
|
||||
RpcCtrlDbgReadAllSmErrorStates *rpcCtrlDbgReadAllSmErrorStates; /* CTRL_DBG_READ_ALL_SM_ERROR_STATES */
|
||||
RpcCtrlSetZbcColorClear *rpcCtrlSetZbcColorClear; /* CTRL_SET_ZBC_COLOR_CLEAR */
|
||||
RpcGetEncoderCapacity *rpcGetEncoderCapacity; /* Get encoder capacity */
|
||||
RpcCtrlGetP2pCaps *rpcCtrlGetP2pCaps; /* CTRL_GET_P2P_CAPS */
|
||||
RpcPerfGetLevelInfo *rpcPerfGetLevelInfo; /* PERF_GET_LEVEL_INFO */
|
||||
RpcAllocObject *rpcAllocObject; /* ALLOC_OBJECT */
|
||||
RpcCtrlGpuHandleVfPriFault *rpcCtrlGpuHandleVfPriFault; /* CTRL_GPU_HANDLE_VF_PRI_FAULT */
|
||||
RpcRmApiControl *rpcRmApiControl; /* RM_API_CONTROL */
|
||||
RpcCtrlFabricMemStats *rpcCtrlFabricMemStats; /* CTRL_FABRIC_MEM_STATS */
|
||||
RpcCtrlGrCtxswZcullBind *rpcCtrlGrCtxswZcullBind; /* CTRL_GR_CTXSW_ZCULL_BIND */
|
||||
RpcCtrlInternalMemsysSetZbcReferenced *rpcCtrlInternalMemsysSetZbcReferenced; /* CTRL_INTERNAL_MEMSYS_SET_ZBC_REFERENCED */
|
||||
RpcCtrlPerfRatedTdpSetControl *rpcCtrlPerfRatedTdpSetControl; /* CTRL_PERF_RATED_TDP_SET_CONTROL */
|
||||
RpcCtrlExecPartitionsCreate *rpcCtrlExecPartitionsCreate; /* CTRL_EXEC_PARTITIONS_CREATE */
|
||||
RpcCtrlGpfifoGetWorkSubmitToken *rpcCtrlGpfifoGetWorkSubmitToken; /* CTRL_GPFIFO_GET_WORK_SUBMIT_TOKEN */
|
||||
RpcIdleChannels *rpcIdleChannels; /* IDLE_CHANNELS */
|
||||
RpcCtrlCmdInternalGpuStartFabricProbe *rpcCtrlCmdInternalGpuStartFabricProbe; /* CTRL_CMD_INTERNAL_START_GPU_FABRIC_PROBE_INFO_PARAMS */
|
||||
RpcGetBrandCaps *rpcGetBrandCaps; /* GET_BRAND_CAPS */
|
||||
RpcRestoreHibernationData *rpcRestoreHibernationData; /* RESTORE_HIBERNATION_DATA */
|
||||
RpcCtrlFlaSetupInstanceMemBlock *rpcCtrlFlaSetupInstanceMemBlock; /* NV2080_CTRL_CMD_FLA_SETUP_INSTANCE_MEM_BLOCK */
|
||||
RpcCtrlInternalSriovPromotePmaStream *rpcCtrlInternalSriovPromotePmaStream; /* CTRL_INTERNAL_SRIOV_PROMOTE_PMA_STREAM */
|
||||
RpcCtrlFbGetFsInfo *rpcCtrlFbGetFsInfo; /* CTRL_FB_GET_FS_INFO */
|
||||
RpcCtrlSetChannelInterleaveLevel *rpcCtrlSetChannelInterleaveLevel; /* CTRL_SET_CHANNEL_INTERLEAVE_LEVEL */
|
||||
RpcCtrlDbgResumeContext *rpcCtrlDbgResumeContext; /* CTRL_DBG_RESUME_CONTEXT */
|
||||
RpcAllocRoot *rpcAllocRoot; /* ALLOC_ROOT */
|
||||
RpcCtrlFifoDisableChannels *rpcCtrlFifoDisableChannels; /* CTRL_FIFO_DISABLE_CHANNELS */
|
||||
RpcCtrlSetHsCredits *rpcCtrlSetHsCredits; /* CTRL_SET_HS_CREDITS */
|
||||
RpcGetEngineUtilization *rpcGetEngineUtilization; /* GET_ENGINE_UTILIZATION */
|
||||
RpcCtrlGetZbcClearTableEntry *rpcCtrlGetZbcClearTableEntry; /* CTRL_GET_ZBC_CLEAR_TABLE_ENTRY */
|
||||
RpcCtrlNvencSwSessionUpdateInfo *rpcCtrlNvencSwSessionUpdateInfo; /* CTRL_NVENC_SW_SESSION_UPDATE_INFO */
|
||||
RpcCtrlDbgSuspendContext *rpcCtrlDbgSuspendContext; /* CTRL_DBG_SUSPEND_CONTEXT */
|
||||
RpcCtrlGetP2pCapsMatrix *rpcCtrlGetP2pCapsMatrix; /* CTRL_GET_P2P_CAPS_MATRIX */
|
||||
RpcCtrlDbgExecRegOps *rpcCtrlDbgExecRegOps; /* CTRL_DBG_EXEC_REG_OPS */
|
||||
RpcCtrlFreePmaStream *rpcCtrlFreePmaStream; /* CTRL_FREE_PMA_STREAM */
|
||||
RpcCtrlSetTsgInterleaveLevel *rpcCtrlSetTsgInterleaveLevel; /* CTRL_SET_TSG_INTERLEAVE_LEVEL */
|
||||
RpcCtrlMasterGetVirtualFunctionErrorContIntrMask *rpcCtrlMasterGetVirtualFunctionErrorContIntrMask; /* CTRL_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK */
|
||||
RpcLog *rpcLog; /* LOG */
|
||||
RpcCtrlExecPartitionsDelete *rpcCtrlExecPartitionsDelete; /* CTRL_EXEC_PARTITIONS_DELETE */
|
||||
RpcCtrlPerfBoost *rpcCtrlPerfBoost; /* CTRL_PERF_BOOST */
|
||||
RpcCtrlDbgSetModeMmuDebug *rpcCtrlDbgSetModeMmuDebug; /* CTRL_DBG_SET_MODE_MMU_DEBUG */
|
||||
RpcCtrlFifoSetChannelProperties *rpcCtrlFifoSetChannelProperties; /* CTRL_FIFO_SET_CHANNEL_PROPERTIES */
|
||||
RpcCtrlSubdeviceGetP2pCaps *rpcCtrlSubdeviceGetP2pCaps; /* CTRL_SUBDEVICE_GET_P2P_CAPS */
|
||||
RpcUpdateBarPde *rpcUpdateBarPde; /* Update the value of BAR1/BAR2 PDE */
|
||||
RpcCtrlBindPmResources *rpcCtrlBindPmResources; /* CTRL_BIND_PM_RESOURCES */
|
||||
RpcMapMemoryDma *rpcMapMemoryDma; /* MAP_MEMORY_DMA */
|
||||
RpcUnmapMemoryDma *rpcUnmapMemoryDma; /* UNMAP_MEMORY_DMA */
|
||||
RpcRmfsTest *rpcRmfsTest; /* Resman File Streaming Test */
|
||||
RpcSetGuestSystemInfoExt *rpcSetGuestSystemInfoExt; /* SET_GUEST_SYSTEM_INFO_EXT */
|
||||
Rpc_iGrp_ipVersions_getInfo *rpc_iGrp_ipVersions_getInfo; /* Return lookup table of hal interface ptrs based on IP_VERSION */
|
||||
} RPC_HAL_IFACES;
|
||||
|
||||
@@ -128,46 +358,266 @@ typedef struct RPC_HAL_IFACES {
|
||||
// eg: #define rpcReadFoo_HAL(_pGpu, _pRpc) _pRpc->hal.rpcReadFoo(_pGpu, _pRpc)
|
||||
//
|
||||
|
||||
#define rpcCtrlFifoSetupVfZombieSubctxPdb_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \
|
||||
(_pRpc)->_hal.rpcCtrlFifoSetupVfZombieSubctxPdb(_pGpu, _pRpc, _arg0, _arg1, _pArg2)
|
||||
#define rpcVgpuPfRegRead32_HAL(_pGpu, _pRpc, _arg0, _pArg1, _arg2) \
|
||||
(_pRpc)->_hal.rpcVgpuPfRegRead32(_pGpu, _pRpc, _arg0, _pArg1, _arg2)
|
||||
#define rpcCtrlBusUnsetP2pMapping_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \
|
||||
(_pRpc)->_hal.rpcCtrlBusUnsetP2pMapping(_pGpu, _pRpc, _arg0, _arg1, _pArg2)
|
||||
#define rpcDumpProtobufComponent_HAL(_pGpu, _pRpc, _pPrbEnc, _pNvDumpState, _component) \
|
||||
(_pRpc)->_hal.rpcDumpProtobufComponent(_pGpu, _pRpc, _pPrbEnc, _pNvDumpState, _component)
|
||||
#define rpcEccNotifierWriteAck_HAL(_pGpu, _pRpc) \
|
||||
(_pRpc)->_hal.rpcEccNotifierWriteAck(_pGpu, _pRpc)
|
||||
#define rpcAllocMemory_HAL(_pGpu, _pRpc, _arg0, _arg1, _arg2, _arg3, _arg4, _pArg5) \
|
||||
(_pRpc)->_hal.rpcAllocMemory(_pGpu, _pRpc, _arg0, _arg1, _arg2, _arg3, _arg4, _pArg5)
|
||||
#define rpcCtrlDbgReadSingleSmErrorState_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \
|
||||
(_pRpc)->_hal.rpcCtrlDbgReadSingleSmErrorState(_pGpu, _pRpc, _arg0, _arg1, _pArg2)
|
||||
#define rpcDisableChannels_HAL(_pGpu, _pRpc, _arg0) \
|
||||
(_pRpc)->_hal.rpcDisableChannels(_pGpu, _pRpc, _arg0)
|
||||
#define rpcGpuExecRegOps_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2, _pArg3) \
|
||||
(_pRpc)->_hal.rpcGpuExecRegOps(_pGpu, _pRpc, _arg0, _arg1, _pArg2, _pArg3)
|
||||
#define rpcRmfsInit_HAL(_pGpu, _pRpc, _arg0) \
|
||||
(_pRpc)->_hal.rpcRmfsInit(_pGpu, _pRpc, _arg0)
|
||||
#define rpcCtrlGpuPromoteCtx_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \
|
||||
(_pRpc)->_hal.rpcCtrlGpuPromoteCtx(_pGpu, _pRpc, _arg0, _arg1, _pArg2)
|
||||
#define rpcCtrlDbgSetNextStopTriggerType_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \
|
||||
(_pRpc)->_hal.rpcCtrlDbgSetNextStopTriggerType(_pGpu, _pRpc, _arg0, _arg1, _pArg2)
|
||||
#define rpcAllocShareDevice_HAL(_pGpu, _pRpc, _arg0, _arg1, _arg2, _arg3, _arg4, _arg5, _arg6, _arg7, _arg8) \
|
||||
(_pRpc)->_hal.rpcAllocShareDevice(_pGpu, _pRpc, _arg0, _arg1, _arg2, _arg3, _arg4, _arg5, _arg6, _arg7, _arg8)
|
||||
#define rpcCtrlPreempt_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \
|
||||
(_pRpc)->_hal.rpcCtrlPreempt(_pGpu, _pRpc, _arg0, _arg1, _pArg2)
|
||||
#define rpcCtrlGpuInitializeCtx_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \
|
||||
(_pRpc)->_hal.rpcCtrlGpuInitializeCtx(_pGpu, _pRpc, _arg0, _arg1, _pArg2)
|
||||
#define rpcCtrlReservePmAreaSmpc_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \
|
||||
(_pRpc)->_hal.rpcCtrlReservePmAreaSmpc(_pGpu, _pRpc, _arg0, _arg1, _pArg2)
|
||||
#define rpcCtrlGpuMigratableOps_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \
|
||||
(_pRpc)->_hal.rpcCtrlGpuMigratableOps(_pGpu, _pRpc, _arg0, _arg1, _pArg2)
|
||||
#define rpcCtrlDbgSetModeErrbarDebug_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \
|
||||
(_pRpc)->_hal.rpcCtrlDbgSetModeErrbarDebug(_pGpu, _pRpc, _arg0, _arg1, _pArg2)
|
||||
#define rpcCtrlPmaStreamUpdateGetPut_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \
|
||||
(_pRpc)->_hal.rpcCtrlPmaStreamUpdateGetPut(_pGpu, _pRpc, _arg0, _arg1, _pArg2)
|
||||
#define rpcCtrlFabricMemoryDescribe_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \
|
||||
(_pRpc)->_hal.rpcCtrlFabricMemoryDescribe(_pGpu, _pRpc, _arg0, _arg1, _pArg2)
|
||||
#define rpcAllocChannelDma_HAL(_pGpu, _pRpc, _arg0, _arg1, _arg2, _arg3, _pArg4, _pArg5) \
|
||||
(_pRpc)->_hal.rpcAllocChannelDma(_pGpu, _pRpc, _arg0, _arg1, _arg2, _arg3, _pArg4, _pArg5)
|
||||
#define rpcCtrlSetZbcDepthClear_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \
|
||||
(_pRpc)->_hal.rpcCtrlSetZbcDepthClear(_pGpu, _pRpc, _arg0, _arg1, _pArg2)
|
||||
#define rpcCtrlResetIsolatedChannel_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \
|
||||
(_pRpc)->_hal.rpcCtrlResetIsolatedChannel(_pGpu, _pRpc, _arg0, _arg1, _pArg2)
|
||||
#define rpcCtrlDmaSetDefaultVaspace_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \
|
||||
(_pRpc)->_hal.rpcCtrlDmaSetDefaultVaspace(_pGpu, _pRpc, _arg0, _arg1, _pArg2)
|
||||
#define rpcAllocSubdevice_HAL(_pGpu, _pRpc, _arg0, _arg1, _arg2, _arg3, _arg4) \
|
||||
(_pRpc)->_hal.rpcAllocSubdevice(_pGpu, _pRpc, _arg0, _arg1, _arg2, _arg3, _arg4)
|
||||
#define rpcFree_HAL(_pGpu, _pRpc, _arg0, _arg1, _arg2) \
|
||||
(_pRpc)->_hal.rpcFree(_pGpu, _pRpc, _arg0, _arg1, _arg2)
|
||||
#define rpcDmaControl_HAL(_pGpu, _pRpc, _arg0, _arg1, _arg2, _pArg3, _arg4) \
|
||||
(_pRpc)->_hal.rpcDmaControl(_pGpu, _pRpc, _arg0, _arg1, _arg2, _pArg3, _arg4)
|
||||
#define rpcCtrlDbgClearSingleSmErrorState_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \
|
||||
(_pRpc)->_hal.rpcCtrlDbgClearSingleSmErrorState(_pGpu, _pRpc, _arg0, _arg1, _pArg2)
|
||||
#define rpcUnsetPageDirectory_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \
|
||||
(_pRpc)->_hal.rpcUnsetPageDirectory(_pGpu, _pRpc, _arg0, _arg1, _pArg2)
|
||||
#define rpcGetGspStaticInfo_HAL(_pGpu, _pRpc) \
|
||||
(_pRpc)->_hal.rpcGetGspStaticInfo(_pGpu, _pRpc)
|
||||
#define rpcSaveHibernationData_HAL(_pGpu, _pRpc) \
|
||||
(_pRpc)->_hal.rpcSaveHibernationData(_pGpu, _pRpc)
|
||||
#define rpcDupObject_HAL(_pGpu, _pRpc, _arg0, _arg1, _arg2, _arg3, _arg4, _arg5) \
|
||||
(_pRpc)->_hal.rpcDupObject(_pGpu, _pRpc, _arg0, _arg1, _arg2, _arg3, _arg4, _arg5)
|
||||
#define rpcGspSetSystemInfo_HAL(_pGpu, _pRpc) \
|
||||
(_pRpc)->_hal.rpcGspSetSystemInfo(_pGpu, _pRpc)
|
||||
#define rpcRmfsCleanup_HAL(_pGpu, _pRpc) \
|
||||
(_pRpc)->_hal.rpcRmfsCleanup(_pGpu, _pRpc)
|
||||
#define rpcCtrlPmAreaPcSampler_HAL(_pGpu, _pRpc, _arg0, _arg1, _arg2, _pArg3) \
|
||||
(_pRpc)->_hal.rpcCtrlPmAreaPcSampler(_pGpu, _pRpc, _arg0, _arg1, _arg2, _pArg3)
|
||||
#define rpcCtrlDbgSetExceptionMask_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \
|
||||
(_pRpc)->_hal.rpcCtrlDbgSetExceptionMask(_pGpu, _pRpc, _arg0, _arg1, _pArg2)
|
||||
#define rpcCtrlVaspaceCopyServerReservedPdes_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \
|
||||
(_pRpc)->_hal.rpcCtrlVaspaceCopyServerReservedPdes(_pGpu, _pRpc, _arg0, _arg1, _pArg2)
|
||||
#define rpcCtrlGrCtxswPreemptionBind_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \
|
||||
(_pRpc)->_hal.rpcCtrlGrCtxswPreemptionBind(_pGpu, _pRpc, _arg0, _arg1, _pArg2)
|
||||
#define rpcCtrlAllocPmaStream_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \
|
||||
(_pRpc)->_hal.rpcCtrlAllocPmaStream(_pGpu, _pRpc, _arg0, _arg1, _pArg2)
|
||||
#define rpcCtrlReserveHwpmLegacy_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \
|
||||
(_pRpc)->_hal.rpcCtrlReserveHwpmLegacy(_pGpu, _pRpc, _arg0, _arg1, _pArg2)
|
||||
#define rpcCtrlInternalQuiescePmaChannel_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \
|
||||
(_pRpc)->_hal.rpcCtrlInternalQuiescePmaChannel(_pGpu, _pRpc, _arg0, _arg1, _pArg2)
|
||||
#define rpcCtrlPerfRatedTdpGetStatus_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \
|
||||
(_pRpc)->_hal.rpcCtrlPerfRatedTdpGetStatus(_pGpu, _pRpc, _arg0, _arg1, _pArg2)
|
||||
#define rpcCtrlBusSetP2pMapping_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \
|
||||
(_pRpc)->_hal.rpcCtrlBusSetP2pMapping(_pGpu, _pRpc, _arg0, _arg1, _pArg2)
|
||||
#define rpcCtrlGpuGetInfoV2_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \
|
||||
(_pRpc)->_hal.rpcCtrlGpuGetInfoV2(_pGpu, _pRpc, _arg0, _arg1, _pArg2)
|
||||
#define rpcCtrlGetHsCredits_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \
|
||||
(_pRpc)->_hal.rpcCtrlGetHsCredits(_pGpu, _pRpc, _arg0, _arg1, _pArg2)
|
||||
#define rpcCtrlGrSetCtxswPreemptionMode_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \
|
||||
(_pRpc)->_hal.rpcCtrlGrSetCtxswPreemptionMode(_pGpu, _pRpc, _arg0, _arg1, _pArg2)
|
||||
#define rpcCtrlB0ccExecRegOps_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \
|
||||
(_pRpc)->_hal.rpcCtrlB0ccExecRegOps(_pGpu, _pRpc, _arg0, _arg1, _pArg2)
|
||||
#define rpcCtrlGrmgrGetGrFsInfo_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \
|
||||
(_pRpc)->_hal.rpcCtrlGrmgrGetGrFsInfo(_pGpu, _pRpc, _arg0, _arg1, _pArg2)
|
||||
#define rpcCtrlGetZbcClearTable_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \
|
||||
(_pRpc)->_hal.rpcCtrlGetZbcClearTable(_pGpu, _pRpc, _arg0, _arg1, _pArg2)
|
||||
#define rpcCleanupSurface_HAL(_pGpu, _pRpc, _pArg0) \
|
||||
(_pRpc)->_hal.rpcCleanupSurface(_pGpu, _pRpc, _pArg0)
|
||||
#define rpcCtrlSetTimeslice_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \
|
||||
(_pRpc)->_hal.rpcCtrlSetTimeslice(_pGpu, _pRpc, _arg0, _arg1, _pArg2)
|
||||
#define rpcCtrlGpuQueryEccStatus_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \
|
||||
(_pRpc)->_hal.rpcCtrlGpuQueryEccStatus(_pGpu, _pRpc, _arg0, _arg1, _pArg2)
|
||||
#define rpcCtrlDbgGetModeMmuDebug_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \
|
||||
(_pRpc)->_hal.rpcCtrlDbgGetModeMmuDebug(_pGpu, _pRpc, _arg0, _arg1, _pArg2)
|
||||
#define rpcCtrlDbgClearAllSmErrorStates_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \
|
||||
(_pRpc)->_hal.rpcCtrlDbgClearAllSmErrorStates(_pGpu, _pRpc, _arg0, _arg1, _pArg2)
|
||||
#define rpcVgpuGspRingDoorbell_HAL(_pRpc, _pGpu, _arg0) \
|
||||
(_pRpc)->_hal.rpcVgpuGspRingDoorbell(_pGpu, _arg0)
|
||||
#define rpcCtrlGrSetTpcPartitionMode_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \
|
||||
(_pRpc)->_hal.rpcCtrlGrSetTpcPartitionMode(_pGpu, _pRpc, _arg0, _arg1, _pArg2)
|
||||
#define rpcCtrlGetTotalHsCredits_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \
|
||||
(_pRpc)->_hal.rpcCtrlGetTotalHsCredits(_pGpu, _pRpc, _arg0, _arg1, _pArg2)
|
||||
#define rpcCtrlInternalPromoteFaultMethodBuffers_HAL(_pArg0, _pRpc, _arg1, _arg2, _pArg3) \
|
||||
(_pRpc)->_hal.rpcCtrlInternalPromoteFaultMethodBuffers(_pArg0, _pRpc, _arg1, _arg2, _pArg3)
|
||||
#define rpcCtrlFbGetInfoV2_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \
|
||||
(_pRpc)->_hal.rpcCtrlFbGetInfoV2(_pGpu, _pRpc, _arg0, _arg1, _pArg2)
|
||||
#define rpcVgpuGspWriteScratchRegister_HAL(_pRpc, _pGpu, _arg0) \
|
||||
(_pRpc)->_hal.rpcVgpuGspWriteScratchRegister(_pGpu, _arg0)
|
||||
#define rpcSetPageDirectory_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \
|
||||
(_pRpc)->_hal.rpcSetPageDirectory(_pGpu, _pRpc, _arg0, _arg1, _pArg2)
|
||||
#define rpcCtrlGetP2pCapsV2_HAL(_pGpu, _pRpc, _pArg0) \
|
||||
(_pRpc)->_hal.rpcCtrlGetP2pCapsV2(_pGpu, _pRpc, _pArg0)
|
||||
#define rpcCtrlNvlinkGetInbandReceivedData_HAL(_pGpu, _pRpc, _pArg0, _arg1, _pArg2) \
|
||||
(_pRpc)->_hal.rpcCtrlNvlinkGetInbandReceivedData(_pGpu, _pRpc, _pArg0, _arg1, _pArg2)
|
||||
#define rpcCtrlGetCePceMask_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \
|
||||
(_pRpc)->_hal.rpcCtrlGetCePceMask(_pGpu, _pRpc, _arg0, _arg1, _pArg2)
|
||||
#define rpcCtrlGetNvlinkPeerIdMask_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \
|
||||
(_pRpc)->_hal.rpcCtrlGetNvlinkPeerIdMask(_pGpu, _pRpc, _arg0, _arg1, _pArg2)
|
||||
#define rpcCtrlGpuEvictCtx_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \
|
||||
(_pRpc)->_hal.rpcCtrlGpuEvictCtx(_pGpu, _pRpc, _arg0, _arg1, _pArg2)
|
||||
#define rpcCtrlGetMmuDebugMode_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \
|
||||
(_pRpc)->_hal.rpcCtrlGetMmuDebugMode(_pGpu, _pRpc, _arg0, _arg1, _pArg2)
|
||||
#define rpcInvalidateTlb_HAL(_pGpu, _pRpc, _arg0, _arg1) \
|
||||
(_pRpc)->_hal.rpcInvalidateTlb(_pGpu, _pRpc, _arg0, _arg1)
|
||||
#define rpcCtrlDbgSetSingleSmSingleStep_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \
|
||||
(_pRpc)->_hal.rpcCtrlDbgSetSingleSmSingleStep(_pGpu, _pRpc, _arg0, _arg1, _pArg2)
|
||||
#define rpcUnloadingGuestDriver_HAL(_pGpu, _pRpc, _arg0, _arg1, _arg2) \
|
||||
(_pRpc)->_hal.rpcUnloadingGuestDriver(_pGpu, _pRpc, _arg0, _arg1, _arg2)
|
||||
#define rpcGetEngineUtilizationWrapper_HAL(_pGpu, _pRpc, _arg0, _arg1, _arg2, _pArg3, _arg4) \
|
||||
(_pRpc)->_hal.rpcGetEngineUtilizationWrapper(_pGpu, _pRpc, _arg0, _arg1, _arg2, _pArg3, _arg4)
|
||||
#define rpcGetConsolidatedGrStaticInfo_HAL(_pGpu, _pRpc) \
|
||||
(_pRpc)->_hal.rpcGetConsolidatedGrStaticInfo(_pGpu, _pRpc)
|
||||
#define rpcSwitchToVga_HAL(_pGpu, _pRpc) \
|
||||
(_pRpc)->_hal.rpcSwitchToVga(_pGpu, _pRpc)
|
||||
#define rpcCtrlResetChannel_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \
|
||||
(_pRpc)->_hal.rpcCtrlResetChannel(_pGpu, _pRpc, _arg0, _arg1, _pArg2)
|
||||
#define rpcCtrlGpfifoSchedule_HAL(_pGpu, _pRpc, _arg0, _arg1, _arg2, _pArg3) \
|
||||
(_pRpc)->_hal.rpcCtrlGpfifoSchedule(_pGpu, _pRpc, _arg0, _arg1, _arg2, _pArg3)
|
||||
#define rpcSetRegistry_HAL(_pGpu, _pRpc) \
|
||||
(_pRpc)->_hal.rpcSetRegistry(_pGpu, _pRpc)
|
||||
#define rpcRmfsCloseQueue_HAL(_pGpu, _pRpc) \
|
||||
(_pRpc)->_hal.rpcRmfsCloseQueue(_pGpu, _pRpc)
|
||||
#define rpcGetStaticInfo_HAL(_pGpu, _pRpc) \
|
||||
(_pRpc)->_hal.rpcGetStaticInfo(_pGpu, _pRpc)
|
||||
#define rpcCtrlGetNvlinkStatus_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \
|
||||
(_pRpc)->_hal.rpcCtrlGetNvlinkStatus(_pGpu, _pRpc, _arg0, _arg1, _pArg2)
|
||||
#define rpcGetStaticData_HAL(_pGpu, _pRpc) \
|
||||
(_pRpc)->_hal.rpcGetStaticData(_pGpu, _pRpc)
|
||||
#define rpcCtrlGrGetTpcPartitionMode_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \
|
||||
(_pRpc)->_hal.rpcCtrlGrGetTpcPartitionMode(_pGpu, _pRpc, _arg0, _arg1, _pArg2)
|
||||
#define rpcCtrlStopChannel_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \
|
||||
(_pRpc)->_hal.rpcCtrlStopChannel(_pGpu, _pRpc, _arg0, _arg1, _pArg2)
|
||||
#define rpcSetSurfaceProperties_HAL(_pGpu, _pRpc, _arg0, _pArg1, _arg2) \
|
||||
(_pRpc)->_hal.rpcSetSurfaceProperties(_pGpu, _pRpc, _arg0, _pArg1, _arg2)
|
||||
#define rpcCtrlGpfifoSetWorkSubmitTokenNotifIndex_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \
|
||||
(_pRpc)->_hal.rpcCtrlGpfifoSetWorkSubmitTokenNotifIndex(_pGpu, _pRpc, _arg0, _arg1, _pArg2)
|
||||
#define rpcCtrlTimerSetGrTickFreq_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \
|
||||
(_pRpc)->_hal.rpcCtrlTimerSetGrTickFreq(_pGpu, _pRpc, _arg0, _arg1, _pArg2)
|
||||
#define rpcAllocEvent_HAL(_pGpu, _pRpc, _arg0, _arg1, _arg2, _arg3, _arg4, _arg5, _arg6) \
|
||||
(_pRpc)->_hal.rpcAllocEvent(_pGpu, _pRpc, _arg0, _arg1, _arg2, _arg3, _arg4, _arg5, _arg6)
|
||||
#define rpcCtrlGrPcSamplingMode_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \
|
||||
(_pRpc)->_hal.rpcCtrlGrPcSamplingMode(_pGpu, _pRpc, _arg0, _arg1, _pArg2)
|
||||
#define rpcCtrlMcServiceInterrupts_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \
|
||||
(_pRpc)->_hal.rpcCtrlMcServiceInterrupts(_pGpu, _pRpc, _arg0, _arg1, _pArg2)
|
||||
#define rpcCtrlDbgReadAllSmErrorStates_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \
|
||||
(_pRpc)->_hal.rpcCtrlDbgReadAllSmErrorStates(_pGpu, _pRpc, _arg0, _arg1, _pArg2)
|
||||
#define rpcCtrlSetZbcColorClear_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \
|
||||
(_pRpc)->_hal.rpcCtrlSetZbcColorClear(_pGpu, _pRpc, _arg0, _arg1, _pArg2)
|
||||
#define rpcGetEncoderCapacity_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \
|
||||
(_pRpc)->_hal.rpcGetEncoderCapacity(_pGpu, _pRpc, _arg0, _arg1, _pArg2)
|
||||
#define rpcCtrlGetP2pCaps_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \
|
||||
(_pRpc)->_hal.rpcCtrlGetP2pCaps(_pGpu, _pRpc, _arg0, _arg1, _pArg2)
|
||||
#define rpcPerfGetLevelInfo_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2, _pArg3) \
|
||||
(_pRpc)->_hal.rpcPerfGetLevelInfo(_pGpu, _pRpc, _arg0, _arg1, _pArg2, _pArg3)
|
||||
#define rpcAllocObject_HAL(_pGpu, _pRpc, _arg0, _arg1, _arg2, _arg3, _pArg4) \
|
||||
(_pRpc)->_hal.rpcAllocObject(_pGpu, _pRpc, _arg0, _arg1, _arg2, _arg3, _pArg4)
|
||||
#define rpcCtrlGpuHandleVfPriFault_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \
|
||||
(_pRpc)->_hal.rpcCtrlGpuHandleVfPriFault(_pGpu, _pRpc, _arg0, _arg1, _pArg2)
|
||||
#define rpcRmApiControl_HAL(_pGpu, _pRpc, _arg0, _arg1, _arg2, _pArg3, _arg4) \
|
||||
(_pRpc)->_hal.rpcRmApiControl(_pGpu, _pRpc, _arg0, _arg1, _arg2, _pArg3, _arg4)
|
||||
#define rpcCtrlFabricMemStats_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \
|
||||
(_pRpc)->_hal.rpcCtrlFabricMemStats(_pGpu, _pRpc, _arg0, _arg1, _pArg2)
|
||||
#define rpcCtrlGrCtxswZcullBind_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \
|
||||
(_pRpc)->_hal.rpcCtrlGrCtxswZcullBind(_pGpu, _pRpc, _arg0, _arg1, _pArg2)
|
||||
#define rpcCtrlInternalMemsysSetZbcReferenced_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \
|
||||
(_pRpc)->_hal.rpcCtrlInternalMemsysSetZbcReferenced(_pGpu, _pRpc, _arg0, _arg1, _pArg2)
|
||||
#define rpcCtrlPerfRatedTdpSetControl_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \
|
||||
(_pRpc)->_hal.rpcCtrlPerfRatedTdpSetControl(_pGpu, _pRpc, _arg0, _arg1, _pArg2)
|
||||
#define rpcCtrlExecPartitionsCreate_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \
|
||||
(_pRpc)->_hal.rpcCtrlExecPartitionsCreate(_pGpu, _pRpc, _arg0, _arg1, _pArg2)
|
||||
#define rpcCtrlGpfifoGetWorkSubmitToken_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \
|
||||
(_pRpc)->_hal.rpcCtrlGpfifoGetWorkSubmitToken(_pGpu, _pRpc, _arg0, _arg1, _pArg2)
|
||||
#define rpcIdleChannels_HAL(_pArg0, _pRpc, _pPhclients, _pPhdevices, _pPhchannels, _nentries, _flags, _timeout) \
|
||||
(_pRpc)->_hal.rpcIdleChannels(_pArg0, _pRpc, _pPhclients, _pPhdevices, _pPhchannels, _nentries, _flags, _timeout)
|
||||
#define rpcCtrlCmdInternalGpuStartFabricProbe_HAL(_pGpu, _pRpc, _pArg0) \
|
||||
(_pRpc)->_hal.rpcCtrlCmdInternalGpuStartFabricProbe(_pGpu, _pRpc, _pArg0)
|
||||
#define rpcGetBrandCaps_HAL(_pGpu, _pRpc, _arg0, _arg1, _arg2, _pArg3, _arg4) \
|
||||
(_pRpc)->_hal.rpcGetBrandCaps(_pGpu, _pRpc, _arg0, _arg1, _arg2, _pArg3, _arg4)
|
||||
#define rpcRestoreHibernationData_HAL(_pGpu, _pRpc) \
|
||||
(_pRpc)->_hal.rpcRestoreHibernationData(_pGpu, _pRpc)
|
||||
#define rpcCtrlFlaSetupInstanceMemBlock_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \
|
||||
(_pRpc)->_hal.rpcCtrlFlaSetupInstanceMemBlock(_pGpu, _pRpc, _arg0, _arg1, _pArg2)
|
||||
#define rpcCtrlInternalSriovPromotePmaStream_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \
|
||||
(_pRpc)->_hal.rpcCtrlInternalSriovPromotePmaStream(_pGpu, _pRpc, _arg0, _arg1, _pArg2)
|
||||
#define rpcCtrlFbGetFsInfo_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \
|
||||
(_pRpc)->_hal.rpcCtrlFbGetFsInfo(_pGpu, _pRpc, _arg0, _arg1, _pArg2)
|
||||
#define rpcCtrlSetChannelInterleaveLevel_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \
|
||||
(_pRpc)->_hal.rpcCtrlSetChannelInterleaveLevel(_pGpu, _pRpc, _arg0, _arg1, _pArg2)
|
||||
#define rpcCtrlDbgResumeContext_HAL(_pGpu, _pRpc, _arg0, _arg1) \
|
||||
(_pRpc)->_hal.rpcCtrlDbgResumeContext(_pGpu, _pRpc, _arg0, _arg1)
|
||||
#define rpcAllocRoot_HAL(_pGpu, _pRpc, _arg0) \
|
||||
(_pRpc)->_hal.rpcAllocRoot(_pGpu, _pRpc, _arg0)
|
||||
#define rpcCtrlFifoDisableChannels_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \
|
||||
(_pRpc)->_hal.rpcCtrlFifoDisableChannels(_pGpu, _pRpc, _arg0, _arg1, _pArg2)
|
||||
#define rpcCtrlSetHsCredits_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \
|
||||
(_pRpc)->_hal.rpcCtrlSetHsCredits(_pGpu, _pRpc, _arg0, _arg1, _pArg2)
|
||||
#define rpcGetEngineUtilization_HAL(_pGpu, _pRpc, _arg0, _arg1, _arg2, _pArg3, _arg4) \
|
||||
(_pRpc)->_hal.rpcGetEngineUtilization(_pGpu, _pRpc, _arg0, _arg1, _arg2, _pArg3, _arg4)
|
||||
#define rpcCtrlGetZbcClearTableEntry_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \
|
||||
(_pRpc)->_hal.rpcCtrlGetZbcClearTableEntry(_pGpu, _pRpc, _arg0, _arg1, _pArg2)
|
||||
#define rpcCtrlNvencSwSessionUpdateInfo_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \
|
||||
(_pRpc)->_hal.rpcCtrlNvencSwSessionUpdateInfo(_pGpu, _pRpc, _arg0, _arg1, _pArg2)
|
||||
#define rpcCtrlDbgSuspendContext_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \
|
||||
(_pRpc)->_hal.rpcCtrlDbgSuspendContext(_pGpu, _pRpc, _arg0, _arg1, _pArg2)
|
||||
#define rpcCtrlGetP2pCapsMatrix_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \
|
||||
(_pRpc)->_hal.rpcCtrlGetP2pCapsMatrix(_pGpu, _pRpc, _arg0, _arg1, _pArg2)
|
||||
#define rpcCtrlDbgExecRegOps_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \
|
||||
(_pRpc)->_hal.rpcCtrlDbgExecRegOps(_pGpu, _pRpc, _arg0, _arg1, _pArg2)
|
||||
#define rpcCtrlFreePmaStream_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \
|
||||
(_pRpc)->_hal.rpcCtrlFreePmaStream(_pGpu, _pRpc, _arg0, _arg1, _pArg2)
|
||||
#define rpcCtrlSetTsgInterleaveLevel_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \
|
||||
(_pRpc)->_hal.rpcCtrlSetTsgInterleaveLevel(_pGpu, _pRpc, _arg0, _arg1, _pArg2)
|
||||
#define rpcCtrlMasterGetVirtualFunctionErrorContIntrMask_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \
|
||||
(_pRpc)->_hal.rpcCtrlMasterGetVirtualFunctionErrorContIntrMask(_pGpu, _pRpc, _arg0, _arg1, _pArg2)
|
||||
#define rpcLog_HAL(_pGpu, _pRpc, _pChar, _arg0) \
|
||||
(_pRpc)->_hal.rpcLog(_pGpu, _pRpc, _pChar, _arg0)
|
||||
#define rpcCtrlExecPartitionsDelete_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \
|
||||
(_pRpc)->_hal.rpcCtrlExecPartitionsDelete(_pGpu, _pRpc, _arg0, _arg1, _pArg2)
|
||||
#define rpcCtrlPerfBoost_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \
|
||||
(_pRpc)->_hal.rpcCtrlPerfBoost(_pGpu, _pRpc, _arg0, _arg1, _pArg2)
|
||||
#define rpcCtrlDbgSetModeMmuDebug_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \
|
||||
(_pRpc)->_hal.rpcCtrlDbgSetModeMmuDebug(_pGpu, _pRpc, _arg0, _arg1, _pArg2)
|
||||
#define rpcCtrlFifoSetChannelProperties_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \
|
||||
(_pRpc)->_hal.rpcCtrlFifoSetChannelProperties(_pGpu, _pRpc, _arg0, _arg1, _pArg2)
|
||||
#define rpcCtrlSubdeviceGetP2pCaps_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \
|
||||
(_pRpc)->_hal.rpcCtrlSubdeviceGetP2pCaps(_pGpu, _pRpc, _arg0, _arg1, _pArg2)
|
||||
#define rpcUpdateBarPde_HAL(_pGpu, _pRpc, _arg0, _arg1, _arg2) \
|
||||
(_pRpc)->_hal.rpcUpdateBarPde(_pGpu, _pRpc, _arg0, _arg1, _arg2)
|
||||
#define rpcCtrlBindPmResources_HAL(_pGpu, _pRpc, _arg0, _arg1) \
|
||||
(_pRpc)->_hal.rpcCtrlBindPmResources(_pGpu, _pRpc, _arg0, _arg1)
|
||||
#define rpcMapMemoryDma_HAL(_pGpu, _pRpc, _arg0, _arg1, _arg2, _arg3, _arg4, _arg5, _arg6, _pArg7) \
|
||||
(_pRpc)->_hal.rpcMapMemoryDma(_pGpu, _pRpc, _arg0, _arg1, _arg2, _arg3, _arg4, _arg5, _arg6, _pArg7)
|
||||
#define rpcUnmapMemoryDma_HAL(_pGpu, _pRpc, _arg0, _arg1, _arg2, _arg3, _arg4, _arg5) \
|
||||
(_pRpc)->_hal.rpcUnmapMemoryDma(_pGpu, _pRpc, _arg0, _arg1, _arg2, _arg3, _arg4, _arg5)
|
||||
#define rpcRmfsTest_HAL(_pGpu, _pRpc, _arg0, _arg1, _arg2, _arg3) \
|
||||
(_pRpc)->_hal.rpcRmfsTest(_pGpu, _pRpc, _arg0, _arg1, _arg2, _arg3)
|
||||
#define rpcSetGuestSystemInfoExt_HAL(_pGpu, _pRpc) \
|
||||
(_pRpc)->_hal.rpcSetGuestSystemInfoExt(_pGpu, _pRpc)
|
||||
#define rpc_iGrp_ipVersions_getInfo_HAL(_pRpc, _pArg0) \
|
||||
(_pRpc)->_hal.rpc_iGrp_ipVersions_getInfo(_pArg0)
|
||||
|
||||
|
||||
Reference in New Issue
Block a user