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This commit is contained in:
Bernhard Stoeckner
2024-01-24 17:51:53 +01:00
parent bb2dac1f20
commit 91676d6628
1411 changed files with 261367 additions and 145959 deletions
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12
src/nvidia/inc/kernel/gpu/ce/kernel_ce_private.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -28,7 +28,8 @@
#include "gpu_mgr/gpu_mgr.h"
#include "kernel/gpu/mig_mgr/kernel_mig_manager.h"
#define CE_GET_LOWEST_AVAILABLE_IDX(x) portUtilCountTrailingZeros32(x)
#define CE_GET_LOWEST_AVAILABLE_IDX(x) \
(x == 0 || x == 0xFFFFFFFF) ? 0xFFFFFFFF : portUtilCountTrailingZeros32(x)
/*!
* @brief Obtain relative CE index.
@@ -55,14 +56,17 @@ NV_STATUS ceIndexFromType(OBJGPU *pGpu, Device *pDevice, RM_ENGINE_TYPE rmEngine
{
KernelMIGManager *pKernelMIGManager = GPU_GET_KERNEL_MIG_MANAGER(pGpu);
MIG_INSTANCE_REF ref;
NvBool bEnginePresent;
status = kmigmgrGetInstanceRefFromDevice(pGpu, pKernelMIGManager, pDevice, &ref);
if (status != NV_OK)
return status;
status = kmigmgrGetLocalToGlobalEngineType(pGpu, pKernelMIGManager, ref, rmEngineType, &localRmEngType);
bEnginePresent = kmigmgrIsLocalEngineInInstance(pGpu, pKernelMIGManager, rmEngineType, ref);
if (!bEnginePresent)
return NV_ERR_INVALID_ARGUMENT;
status = kmigmgrGetLocalToGlobalEngineType(pGpu, pKernelMIGManager, ref, rmEngineType, &localRmEngType);
if (status != NV_OK)
return status;
}

9
src/nvidia/inc/kernel/gpu/gpu_acpi_data.h
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@@ -33,6 +33,14 @@
#define MAX_DSM_SUPPORTED_FUNCS_RTN_LEN 8 // # bytes to store supported functions
/* Indicates the current state of mux */
typedef enum
{
dispMuxState_None = 0,
dispMuxState_IntegratedGPU,
dispMuxState_DiscreteGPU,
} DISPMUXSTATE;
typedef struct {
// supported function status and cache
NvU32 suppFuncStatus;
@@ -88,6 +96,7 @@ typedef struct MUX_METHOD_DATA
NvU32 tableLen;
MUX_METHOD_DATA_ELEMENT acpiIdMuxModeTable[NV0073_CTRL_SYSTEM_ACPI_ID_MAP_MAX_DISPLAYS];
MUX_METHOD_DATA_ELEMENT acpiIdMuxPartTable[NV0073_CTRL_SYSTEM_ACPI_ID_MAP_MAX_DISPLAYS];
MUX_METHOD_DATA_ELEMENT acpiIdMuxStateTable[NV0073_CTRL_SYSTEM_ACPI_ID_MAP_MAX_DISPLAYS];
} MUX_METHOD_DATA;
typedef struct CAPS_METHOD_DATA

7
src/nvidia/inc/kernel/gpu/gpu_child_list.h
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@@ -199,7 +199,7 @@
GPU_CHILD_SINGLE_INST( OBJRC, GPU_GET_RC, 1, NV_FALSE, pRC )
#endif
#if GPU_CHILD_MODULE(STEREO)
GPU_CHILD_SINGLE_INST( OBJSTEREO, GPU_GET_STEREO, 1, NV_FALSE, pStereo )
GPU_CHILD_SINGLE_INST( Stereo, GPU_GET_STEREO, 1, NV_FALSE, pStereo )
#endif
#if GPU_CHILD_MODULE(INTR)
GPU_CHILD_SINGLE_INST( Intr, GPU_GET_INTR, 1, NV_FALSE, pIntr )
@@ -276,6 +276,9 @@
#if GPU_CHILD_MODULE(HWPM)
GPU_CHILD_SINGLE_INST( OBJHWPM, GPU_GET_HWPM, 1, NV_FALSE, pHwpm )
#endif
#if GPU_CHILD_MODULE(KERNEL_HWPM)
GPU_CHILD_SINGLE_INST( KernelHwpm, GPU_GET_KERNEL_HWPM, 1, NV_FALSE, pKernelHwpm )
#endif
#if GPU_CHILD_MODULE(GRIDDISPLAYLESS)
GPU_CHILD_SINGLE_INST( OBJGRIDDISPLAYLESS, GPU_GET_GRIDDISPLAYLESS, 1, NV_FALSE, pGridDisplayless )
#endif
@@ -295,7 +298,7 @@
GPU_CHILD_SINGLE_INST( KernelFsp, GPU_GET_KERNEL_FSP, 1, NV_FALSE, pKernelFsp )
#endif
#if GPU_CHILD_MODULE(OFA)
GPU_CHILD_MULTI_INST( OBJOFA, GPU_GET_OFA, GPU_MAX_OFAS, NV_FALSE, pOfa )
GPU_CHILD_MULTI_INST( OBJOFA, GPU_GET_OFA, GPU_MAX_OFAS, NV_FALSE, pOfa )
#endif
#if RMCFG_MODULE_CONF_COMPUTE && GPU_CHILD_MODULE(CONF_COMPUTE)
GPU_CHILD_SINGLE_INST( ConfidentialCompute, GPU_GET_CONF_COMPUTE, 1, NV_TRUE, pConfCompute )

49
src/nvidia/inc/kernel/gpu/gpu_engine_type.h
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@@ -71,30 +71,31 @@ typedef enum
RM_ENGINE_TYPE_NVENC0 = (0x00000025),
RM_ENGINE_TYPE_NVENC1 = (0x00000026),
RM_ENGINE_TYPE_NVENC2 = (0x00000027),
RM_ENGINE_TYPE_VP = (0x00000028),
RM_ENGINE_TYPE_ME = (0x00000029),
RM_ENGINE_TYPE_PPP = (0x0000002a),
RM_ENGINE_TYPE_MPEG = (0x0000002b),
RM_ENGINE_TYPE_SW = (0x0000002c),
RM_ENGINE_TYPE_TSEC = (0x0000002d),
RM_ENGINE_TYPE_VIC = (0x0000002e),
RM_ENGINE_TYPE_MP = (0x0000002f),
RM_ENGINE_TYPE_SEC2 = (0x00000030),
RM_ENGINE_TYPE_HOST = (0x00000031),
RM_ENGINE_TYPE_DPU = (0x00000032),
RM_ENGINE_TYPE_PMU = (0x00000033),
RM_ENGINE_TYPE_FBFLCN = (0x00000034),
RM_ENGINE_TYPE_NVJPEG0 = (0x00000035),
RM_ENGINE_TYPE_NVJPEG1 = (0x00000036),
RM_ENGINE_TYPE_NVJPEG2 = (0x00000037),
RM_ENGINE_TYPE_NVJPEG3 = (0x00000038),
RM_ENGINE_TYPE_NVJPEG4 = (0x00000039),
RM_ENGINE_TYPE_NVJPEG5 = (0x0000003a),
RM_ENGINE_TYPE_NVJPEG6 = (0x0000003b),
RM_ENGINE_TYPE_NVJPEG7 = (0x0000003c),
RM_ENGINE_TYPE_OFA0 = (0x0000003d),
RM_ENGINE_TYPE_RESERVED3e = (0x0000003e),
RM_ENGINE_TYPE_LAST = (0x0000003f),
RM_ENGINE_TYPE_RESERVED28 = (0x00000028),
RM_ENGINE_TYPE_VP = (0x00000029),
RM_ENGINE_TYPE_ME = (0x0000002a),
RM_ENGINE_TYPE_PPP = (0x0000002b),
RM_ENGINE_TYPE_MPEG = (0x0000002c),
RM_ENGINE_TYPE_SW = (0x0000002d),
RM_ENGINE_TYPE_TSEC = (0x0000002e),
RM_ENGINE_TYPE_VIC = (0x0000002f),
RM_ENGINE_TYPE_MP = (0x00000030),
RM_ENGINE_TYPE_SEC2 = (0x00000031),
RM_ENGINE_TYPE_HOST = (0x00000032),
RM_ENGINE_TYPE_DPU = (0x00000033),
RM_ENGINE_TYPE_PMU = (0x00000034),
RM_ENGINE_TYPE_FBFLCN = (0x00000035),
RM_ENGINE_TYPE_NVJPEG0 = (0x00000036),
RM_ENGINE_TYPE_NVJPEG1 = (0x00000037),
RM_ENGINE_TYPE_NVJPEG2 = (0x00000038),
RM_ENGINE_TYPE_NVJPEG3 = (0x00000039),
RM_ENGINE_TYPE_NVJPEG4 = (0x0000003a),
RM_ENGINE_TYPE_NVJPEG5 = (0x0000003b),
RM_ENGINE_TYPE_NVJPEG6 = (0x0000003c),
RM_ENGINE_TYPE_NVJPEG7 = (0x0000003d),
RM_ENGINE_TYPE_OFA0 = (0x0000003e),
RM_ENGINE_TYPE_RESERVED3f = (0x0000003f),
RM_ENGINE_TYPE_LAST = (0x00000040),
} RM_ENGINE_TYPE;
//

12
src/nvidia/inc/kernel/gpu/gpu_fabric_probe.h
View File

@@ -26,6 +26,7 @@
#include "nvlink_inband_msg.h"
#include "ctrl/ctrl2080/ctrl2080nvlink.h"
#define GPU_FABRIC_PROBE_SEC_TO_NS 1000000000ULL
@@ -53,6 +54,7 @@ NV_STATUS gpuFabricProbeGetFlaAddress(GPU_FABRIC_PROBE_INFO_KERNEL *pInfo, NvU64
NV_STATUS gpuFabricProbeGetFlaAddressRange(GPU_FABRIC_PROBE_INFO_KERNEL *pInfo, NvU64 *pFlaAddressRange);
NV_STATUS gpuFabricProbeGetNumProbeReqs(GPU_FABRIC_PROBE_INFO_KERNEL *pInfo, NvU64 *numProbes);
NV_STATUS gpuFabricProbeGetFabricCliqueId(GPU_FABRIC_PROBE_INFO_KERNEL *pInfo, NvU32 *pFabricCliqueId);
NV_STATUS gpuFabricProbeGetFabricHealthStatus(GPU_FABRIC_PROBE_INFO_KERNEL *pInfo, NvU32 *pFabricHealthStatusMask);
NvBool gpuFabricProbeIsReceived(GPU_FABRIC_PROBE_INFO_KERNEL *pGpuFabricProbeInfoKernel);
NvBool gpuFabricProbeIsSuccess(GPU_FABRIC_PROBE_INFO_KERNEL *pGpuFabricProbeInfoKernel);
@@ -61,4 +63,14 @@ NvBool gpuFabricProbeIsSupported(OBJGPU *pGpu);
NV_STATUS gpuFabricProbeSetBwMode(NvU8 mode);
NV_STATUS gpuFabricProbeGetlinkMaskToBeReduced(GPU_FABRIC_PROBE_INFO_KERNEL *pGpuFabricProbeInfoKernel,
NvU32 *linkMaskToBeReduced);
NV_STATUS gpuFabricProbeReceiveUpdateKernelCallback(NvU32 gpuInstance, NvU64 *pNotifyGfIdMask,
NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_PARAMS *pInbandRcvParams);
NV_STATUS gpuFabricProbeReceiveKernelCallback(NvU32 gpuInstance, NvU64 *pNotifyGfIdMask,
NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_PARAMS *pInbandRcvParams);
NV_STATUS gpuFabricProbeReceivePhysicalCallback(NvU32 gpuInstance, NvU64 *pNotifyGfIdMask,
NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_PARAMS *pInbandRcvParams);
NV_STATUS gpuFabricProbeReceiveUpdatePhysicalCallback(NvU32 gpuInstance, NvU64 *pNotifyGfIdMask,
NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_PARAMS *pInbandRcvParams);
#endif // GPU_FABRIC_PROBE_H

3
src/nvidia/inc/kernel/gpu/gr/kernel_graphics_context_buffers.h
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@@ -59,7 +59,8 @@ NV_ENUM_DEF(GR_GLOBALCTX_BUFFER, GR_GLOBALCTX_BUFFER_DEF)
NV_ENUM_ENTRY(x, GR_CTX_BUFFER_BETA_CB, 0x00000005) \
NV_ENUM_ENTRY(x, GR_CTX_BUFFER_PAGEPOOL, 0x00000006) \
NV_ENUM_ENTRY(x, GR_CTX_BUFFER_RTV_CB, 0x00000007) \
NV_ENUM_ENTRY(x, GR_CTX_BUFFER_PATCH, 0x00000008)
NV_ENUM_ENTRY(x, GR_CTX_BUFFER_PATCH, 0x00000008) \
NV_ENUM_ENTRY(x, GR_CTX_BUFFER_SETUP, 0x00000009)
NV_ENUM_DEF(GR_CTX_BUFFER, GR_CTX_BUFFER_DEF)

7
src/nvidia/inc/kernel/gpu/gsp/gsp_static_config.h
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@@ -27,8 +27,7 @@
//
// This header describes the set of static GPU configuration information
// that is collected during GSP RM init and made available to the
// CPU RM (aka GSP client) via the NV_RM_RPC_GET_STATIC_INFO() and
// NV_RM_RPC_GET_GSP_STATIC_INFO() calls.
// CPU RM (aka GSP client) via NV_RM_RPC_GET_GSP_STATIC_INFO() call.
#include "ctrl/ctrl0080/ctrl0080gpu.h"
#include "ctrl/ctrl0080/ctrl0080gr.h"
@@ -78,7 +77,6 @@ typedef struct GspStaticConfigInfo_t
NV2080_CTRL_GPU_GET_FERMI_ZCULL_INFO_PARAMS zcullInfo[MAX_GPC_COUNT];
NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS SKUInfo;
NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_PARAMS fbRegionInfoParams;
COMPUTE_BRANDING_TYPE computeBranding;
NV0080_CTRL_GPU_GET_SRIOV_CAPS_PARAMS sriovCaps;
NvU32 sriovMaxGfid;
@@ -155,6 +153,7 @@ typedef struct GspSystemInfo
NvU64 gpuPhysInstAddr;
NvU64 nvDomainBusDeviceFunc;
NvU64 simAccessBufPhysAddr;
NvU64 notifyOpSharedSurfacePhysAddr;
NvU64 pcieAtomicsOpMask;
NvU64 consoleMemSize;
NvU64 maxUserVa;
@@ -171,6 +170,7 @@ typedef struct GspSystemInfo
NvBool bUpstreamL1Unsupported;
NvBool bUpstreamL1PorSupported;
NvBool bUpstreamL1PorMobileOnly;
NvBool bSystemHasMux;
NvU8 upstreamAddressValid;
BUSINFO FHBBusInfo;
BUSINFO chipsetIDInfo;
@@ -179,6 +179,7 @@ typedef struct GspSystemInfo
NvBool bIsPassthru;
NvU64 sysTimerOffsetNs;
GSP_VF_INFO gspVFInfo;
NvBool isGridBuild;
} GspSystemInfo;

44
src/nvidia/inc/kernel/gpu/gsp/gsp_trace_rats_macro.h Normal file
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@@ -0,0 +1,44 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
/*
* This file defines macros to place tracepoints for RATS (RM All-around Trace
* System). The names of the functions and variables associated with this are
* temporary as we begin to unify all RM tracing tools under one system.
*/
#ifndef GSP_TRACE_RATS_MACRO_H
#define GSP_TRACE_RATS_MACRO_H
#include "core/core.h"
#define GSP_TRACING_RATS_ENABLED 0
#define GSP_TRACE_RATS_ADD_RECORD(recordIdentifier, pGpu, info) (void) 0
#define KERNEL_GSP_TRACING_RATS_ENABLED 0
#ifndef GET_RATS_TIMESTAMP_NS
#define GET_RATS_TIMESTAMP_NS() NV_ASSERT(0)
#endif
#endif

3
src/nvidia/inc/kernel/gpu/hwpm/kern_hwpm.h Normal file
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@@ -0,0 +1,3 @@
#include "g_kern_hwpm_nvoc.h"

3
src/nvidia/inc/kernel/gpu/hwpm/kern_hwpm_common_defs.h Normal file
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@@ -0,0 +1,3 @@
#include "g_kern_hwpm_common_defs_nvoc.h"

3
src/nvidia/inc/kernel/gpu/hwpm/kern_hwpm_power.h Normal file
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@@ -0,0 +1,3 @@
#include "g_kern_hwpm_power_nvoc.h"

133
src/nvidia/inc/kernel/gpu/intr/engine_idx.h
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@@ -78,79 +78,82 @@
#define MC_ENGINE_IDX_NVENC 38
#define MC_ENGINE_IDX_NVENC1 39
#define MC_ENGINE_IDX_NVENC2 40
#define MC_ENGINE_IDX_C2C 41
#define MC_ENGINE_IDX_LTC 42
#define MC_ENGINE_IDX_FBHUB 43
#define MC_ENGINE_IDX_HDACODEC 44
#define MC_ENGINE_IDX_GMMU 45
#define MC_ENGINE_IDX_SEC2 46
#define MC_ENGINE_IDX_FSP 47
#define MC_ENGINE_IDX_NVLINK 48
#define MC_ENGINE_IDX_GSP 49
#define MC_ENGINE_IDX_NVJPG 50
#define MC_ENGINE_IDX_RESERVED41 41
#define MC_ENGINE_IDX_C2C 42
#define MC_ENGINE_IDX_LTC 43
#define MC_ENGINE_IDX_FBHUB 44
#define MC_ENGINE_IDX_HDACODEC 45
#define MC_ENGINE_IDX_GMMU 46
#define MC_ENGINE_IDX_SEC2 47
#define MC_ENGINE_IDX_FSP 48
#define MC_ENGINE_IDX_NVLINK 49
#define MC_ENGINE_IDX_GSP 50
#define MC_ENGINE_IDX_NVJPG 51
#define MC_ENGINE_IDX_NVJPEG MC_ENGINE_IDX_NVJPG
#define MC_ENGINE_IDX_NVJPEG0 MC_ENGINE_IDX_NVJPEG
#define MC_ENGINE_IDX_NVJPEG1 51
#define MC_ENGINE_IDX_NVJPEG2 52
#define MC_ENGINE_IDX_NVJPEG3 53
#define MC_ENGINE_IDX_NVJPEG4 54
#define MC_ENGINE_IDX_NVJPEG5 55
#define MC_ENGINE_IDX_NVJPEG6 56
#define MC_ENGINE_IDX_NVJPEG7 57
#define MC_ENGINE_IDX_REPLAYABLE_FAULT 58
#define MC_ENGINE_IDX_ACCESS_CNTR 59
#define MC_ENGINE_IDX_NON_REPLAYABLE_FAULT 60
#define MC_ENGINE_IDX_REPLAYABLE_FAULT_ERROR 61
#define MC_ENGINE_IDX_NON_REPLAYABLE_FAULT_ERROR 62
#define MC_ENGINE_IDX_INFO_FAULT 63
#define MC_ENGINE_IDX_BSP 64
#define MC_ENGINE_IDX_NVJPEG1 52
#define MC_ENGINE_IDX_NVJPEG2 53
#define MC_ENGINE_IDX_NVJPEG3 54
#define MC_ENGINE_IDX_NVJPEG4 55
#define MC_ENGINE_IDX_NVJPEG5 56
#define MC_ENGINE_IDX_NVJPEG6 57
#define MC_ENGINE_IDX_NVJPEG7 58
#define MC_ENGINE_IDX_REPLAYABLE_FAULT 59
#define MC_ENGINE_IDX_ACCESS_CNTR 60
#define MC_ENGINE_IDX_NON_REPLAYABLE_FAULT 61
#define MC_ENGINE_IDX_REPLAYABLE_FAULT_ERROR 62
#define MC_ENGINE_IDX_NON_REPLAYABLE_FAULT_ERROR 63
#define MC_ENGINE_IDX_INFO_FAULT 64
#define MC_ENGINE_IDX_BSP 65
#define MC_ENGINE_IDX_NVDEC MC_ENGINE_IDX_BSP
#define MC_ENGINE_IDX_NVDEC0 MC_ENGINE_IDX_NVDEC
#define MC_ENGINE_IDX_NVDEC1 65
#define MC_ENGINE_IDX_NVDEC2 66
#define MC_ENGINE_IDX_NVDEC3 67
#define MC_ENGINE_IDX_NVDEC4 68
#define MC_ENGINE_IDX_NVDEC5 69
#define MC_ENGINE_IDX_NVDEC6 70
#define MC_ENGINE_IDX_NVDEC7 71
#define MC_ENGINE_IDX_CPU_DOORBELL 72
#define MC_ENGINE_IDX_PRIV_DOORBELL 73
#define MC_ENGINE_IDX_MMU_ECC_ERROR 74
#define MC_ENGINE_IDX_BLG 75
#define MC_ENGINE_IDX_PERFMON 76
#define MC_ENGINE_IDX_BUF_RESET 77
#define MC_ENGINE_IDX_XBAR 78
#define MC_ENGINE_IDX_ZPW 79
#define MC_ENGINE_IDX_OFA0 80
#define MC_ENGINE_IDX_RESERVED81 81
#define MC_ENGINE_IDX_TEGRA 82
#define MC_ENGINE_IDX_GR 83
#define MC_ENGINE_IDX_NVDEC1 66
#define MC_ENGINE_IDX_NVDEC2 67
#define MC_ENGINE_IDX_NVDEC3 68
#define MC_ENGINE_IDX_NVDEC4 69
#define MC_ENGINE_IDX_NVDEC5 70
#define MC_ENGINE_IDX_NVDEC6 71
#define MC_ENGINE_IDX_NVDEC7 72
#define MC_ENGINE_IDX_CPU_DOORBELL 73
#define MC_ENGINE_IDX_PRIV_DOORBELL 74
#define MC_ENGINE_IDX_MMU_ECC_ERROR 75
#define MC_ENGINE_IDX_BLG 76
#define MC_ENGINE_IDX_PERFMON 77
#define MC_ENGINE_IDX_BUF_RESET 78
#define MC_ENGINE_IDX_XBAR 79
#define MC_ENGINE_IDX_ZPW 80
#define MC_ENGINE_IDX_OFA0 81
#define MC_ENGINE_IDX_RESERVED81 82
#define MC_ENGINE_IDX_TEGRA 83
#define MC_ENGINE_IDX_GR 84
#define MC_ENGINE_IDX_GR0 MC_ENGINE_IDX_GR
#define MC_ENGINE_IDX_GR1 84
#define MC_ENGINE_IDX_GR2 85
#define MC_ENGINE_IDX_GR3 86
#define MC_ENGINE_IDX_GR4 87
#define MC_ENGINE_IDX_GR5 88
#define MC_ENGINE_IDX_GR6 89
#define MC_ENGINE_IDX_GR7 90
#define MC_ENGINE_IDX_ESCHED 91
#define MC_ENGINE_IDX_GR1 85
#define MC_ENGINE_IDX_GR2 86
#define MC_ENGINE_IDX_GR3 87
#define MC_ENGINE_IDX_GR4 88
#define MC_ENGINE_IDX_GR5 89
#define MC_ENGINE_IDX_GR6 90
#define MC_ENGINE_IDX_GR7 91
#define MC_ENGINE_IDX_ESCHED 92
#define MC_ENGINE_IDX_ESCHED__SIZE 64
#define MC_ENGINE_IDX_GR_FECS_LOG 155
#define MC_ENGINE_IDX_GR_FECS_LOG 156
#define MC_ENGINE_IDX_GR0_FECS_LOG MC_ENGINE_IDX_GR_FECS_LOG
#define MC_ENGINE_IDX_GR1_FECS_LOG 156
#define MC_ENGINE_IDX_GR2_FECS_LOG 157
#define MC_ENGINE_IDX_GR3_FECS_LOG 158
#define MC_ENGINE_IDX_GR4_FECS_LOG 159
#define MC_ENGINE_IDX_GR5_FECS_LOG 160
#define MC_ENGINE_IDX_GR6_FECS_LOG 161
#define MC_ENGINE_IDX_GR7_FECS_LOG 162
#define MC_ENGINE_IDX_TMR_SWRL 163
#define MC_ENGINE_IDX_DISP_GSP 164
#define MC_ENGINE_IDX_REPLAYABLE_FAULT_CPU 165
#define MC_ENGINE_IDX_NON_REPLAYABLE_FAULT_CPU 166
#define MC_ENGINE_IDX_PXUC 167
#define MC_ENGINE_IDX_GR1_FECS_LOG 157
#define MC_ENGINE_IDX_GR2_FECS_LOG 158
#define MC_ENGINE_IDX_GR3_FECS_LOG 159
#define MC_ENGINE_IDX_GR4_FECS_LOG 160
#define MC_ENGINE_IDX_GR5_FECS_LOG 161
#define MC_ENGINE_IDX_GR6_FECS_LOG 162
#define MC_ENGINE_IDX_GR7_FECS_LOG 163
#define MC_ENGINE_IDX_TMR_SWRL 164
#define MC_ENGINE_IDX_DISP_GSP 165
#define MC_ENGINE_IDX_REPLAYABLE_FAULT_CPU 166
#define MC_ENGINE_IDX_NON_REPLAYABLE_FAULT_CPU 167
#define MC_ENGINE_IDX_PXUC 168
#define MC_ENGINE_IDX_SYSLTC 169
#define MC_ENGINE_IDX_LRCC 170
// This must be kept as the max bit if we need to add more engines
#define MC_ENGINE_IDX_MAX 168
#define MC_ENGINE_IDX_MAX 171
// Index GR reference
#define MC_ENGINE_IDX_GRn(x) (MC_ENGINE_IDX_GR0 + (x))

118
src/nvidia/inc/kernel/gpu/mem_mgr/ce_utils.h
View File

@@ -1,121 +1,3 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#include "g_ce_utils_nvoc.h"
#ifndef CE_UTILS_H
#define CE_UTILS_H
#include "gpu/gpu_resource.h" // GpuResource
#include "class/cl0050.h"
#include "ctrl/ctrl0050.h"
#include "kernel/gpu/mem_mgr/channel_utils.h"
typedef struct
{
MEMORY_DESCRIPTOR *pMemDesc;
NvU64 offset;
NvU64 length;
NvU32 pattern;
NvU64 flags;
NvU64 submittedWorkId; // Payload to poll for async completion
} CEUTILS_MEMSET_PARAMS;
typedef struct
{
MEMORY_DESCRIPTOR *pSrcMemDesc;
MEMORY_DESCRIPTOR *pDstMemDesc;
NvU64 dstOffset;
NvU64 srcOffset;
NvU64 length;
NvU64 flags;
NvU64 submittedWorkId; // Payload to poll for async completion
} CEUTILS_MEMCOPY_PARAMS;
class KernelChannel;
NVOC_PREFIX(ceutils) class CeUtils : Object
{
public:
NV_STATUS ceutilsConstruct(CeUtils *pCeUtils, OBJGPU *pGpu, KERNEL_MIG_GPU_INSTANCE *pKernelMIGGPUInstance,
NV0050_ALLOCATION_PARAMETERS *pAllocParams);
void ceutilsDestruct(CeUtils *pCeUtils);
NV_STATUS ceutilsMemset(CeUtils *pCeUtils, CEUTILS_MEMSET_PARAMS *pParams);
NV_STATUS ceutilsMemcopy(CeUtils *pCeUtils, CEUTILS_MEMCOPY_PARAMS *pParams);
NvU64 ceutilsUpdateProgress(CeUtils *pCeUtils);
void ceutilsServiceInterrupts(CeUtils *pCeUtils);
//
// Internal states
//
NvHandle hClient;
NvHandle hDevice;
NvHandle hSubdevice;
OBJCHANNEL *pChannel;
OBJGPU *pGpu;
KernelCE *pKCe;
NvBool bUseVasForCeCopy;
NvU32 hTdCopyClass;
NvU64 lastSubmittedPayload;
NvU64 lastCompletedPayload;
// Only used by fifo lite implementation
KernelChannel *pLiteKernelChannel;
};
#if defined(DEBUG) || defined (DEVELOP)
NVOC_PREFIX(ceutilsapi) class CeUtilsApi : GpuResource
{
public:
NV_STATUS ceutilsapiConstruct(CeUtilsApi *pCeUtilsApi, CALL_CONTEXT *pCallContext,
RS_RES_ALLOC_PARAMS_INTERNAL *pParams)
: GpuResource(pCallContext, pParams);
void ceutilsapiDestruct(CeUtilsApi *pCeUtilsApi);
//
// Below APIs are only provided for SRT testing, thus only available for debug or
// develop driver builds
//
//
RMCTRL_EXPORT(NV0050_CTRL_CMD_MEMSET, RMCTRL_FLAGS(PRIVILEGED, API_LOCK_READONLY))
NV_STATUS ceutilsapiCtrlCmdMemset(CeUtilsApi *pCeUtilsApi, NV0050_CTRL_MEMSET_PARAMS *pParams);
RMCTRL_EXPORT(NV0050_CTRL_CMD_MEMCOPY, RMCTRL_FLAGS(PRIVILEGED, API_LOCK_READONLY))
NV_STATUS ceutilsapiCtrlCmdMemcopy(CeUtilsApi *pCeUtilsApi, NV0050_CTRL_MEMCOPY_PARAMS *pParams);
RMCTRL_EXPORT(NV0050_CTRL_CMD_CHECK_PROGRESS, RMCTRL_FLAGS(PRIVILEGED, API_LOCK_READONLY))
NV_STATUS ceutilsapiCtrlCmdCheckProgress(CeUtilsApi *pCeUtilsApi, NV0050_CTRL_CHECK_PROGRESS_PARAMS *pParams);
CeUtils *pCeUtils;
};
#endif
#endif // CE_UTILS_H

3
src/nvidia/inc/kernel/gpu/mem_mgr/mem_scrub.h
View File

@@ -127,9 +127,6 @@ NV_STATUS scrubberConstruct(struct OBJGPU *pGpu, struct Heap *pHeap);
*
*/
NV_STATUS vgpuAllocGuestPmaScrubberSharedBuffer(struct OBJGPU *pGpu, OBJMEMSCRUB *pScrubber);
void vgpuFreeGuestPmaScrubberSharedBuffer(struct OBJGPU *pGpu, OBJMEMSCRUB *pScrubber);
void scrubberDestruct(struct OBJGPU *pGpu, struct Heap *pHeap, OBJMEMSCRUB *pMemscrub);

244
src/nvidia/inc/kernel/gpu/mem_mgr/phys_mem_allocator/addrtree.h
View File

@@ -1,244 +0,0 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2015-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
/*!
* @brief Implement PMA address tree
*
*/
#ifndef ADDRTREE_H
#define ADDRTREE_H
#ifdef __cplusplus
extern "C" {
#endif
#include "map_defines.h"
// Declare this before its definition because it refers to itself
typedef struct addrtree_node ADDRTREE_NODE;
struct addrtree_node
{
NvU32 level; // The level this node belongs to
NvU32 numChildren; // The number of children in the children array
NvU64 frame; // The first frame this node holds
NvU64 state[PMA_BITS_PER_PAGE]; // Tracks the actual state for each map
NvU64 seeChild[PMA_BITS_PER_PAGE]; // Whether this node is partially allocated
// If it is partially allocated, we must go to the children
// to find the correct information.
ADDRTREE_NODE *parent; // The node's parent
ADDRTREE_NODE *children; // Pointer to an array of children
};
typedef struct addrtree_level
{
NvU64 nodeCount; // Count of total number of nodes on this level
ADDRTREE_NODE *pNodeList; // Pointer to the start of the list of nodes on this level
NvU32 pageSizeShift; // Page size this level is tracking
NvU32 maxFramesPerNode; // The max number of this level frames per node
} ADDRTREE_LEVEL;
typedef struct pma_addrtree
{
NvU64 totalFrames; // Total number of 64KB frames being tracked
NvU32 levelCount; // Number of levels in this tree
ADDRTREE_LEVEL *levels; // List of levels in the tree
ADDRTREE_NODE *root; // Start of the node list
NvU64 numPaddingFrames; // Number of 64KB frames needed for padding for alignment
NvU64 frameEvictionsInProcess; // Count of frame evictions in-process
PMA_STATS *pPmaStats; // Point back to the public struct in PMA structure
NvBool bProtected; // The memory segment tracked by this tree is protected (VPR/CPR)
} PMA_ADDRTREE;
/*!
* @brief Initializes the addrtree for PMA uses
*
* Allocates the address tree structure for all the pages being managed in this tree.
* Address Tree implementation will use a default configuration for its own level
* structures.
*
* @param[in] numPages The number of pages being managed in this tree
* @param[in] addrBase The base address of this region. Required for addrtree alignment
* @param[in] pPmaStats Pointer to the PMA-wide stats structure
* @param[in] bProtected The tree tracks pages in protected memory
*
* @return PMA_ADDRTREE Pointer to the addrtree if succeeded, NULL otherwise
*/
void *pmaAddrtreeInit(NvU64 numFrames, NvU64 addrBase, PMA_STATS *pPmaStats, NvBool bProtected);
/*!
* @brief Destroys the addrtree and free the memory
*
* @param[in] pMap The addrtree to destroy
*
* @return void
*/
void pmaAddrtreeDestroy(void *pMap);
/*!
* @brief Get/set number of evicting frames
* Used for sanity checking in PMA layer as well as performance optimization
* for the map layer to scan faster.
*/
NvU64 pmaAddrtreeGetEvictingFrames(void *pMap);
void pmaAddrtreeSetEvictingFrames(void *pMap, NvU64 frameEvictionsInProcess);
/*!
* @brief Scans the addrtree for contiguous space that has the certain status.
*
* @param[in] pMap The addrtree to be scanned
* @param[in] addrBase The base address of this region
* @param[in] rangeStart The start of the restricted range
* @param[in] rangeEnd The end of the restricted range
* @param[in] numPages The number of pages we are scanning for
* @param[out] freeList A list of free frame numbers -- contains only 1 element
* @param[in] pageSize Size of one page
* @param[in] alignment Alignment requested by client
* @param[out] pagesAllocated Number of pages this call allocated
* @param[in] bSkipEvict Whether it's ok to skip the scan for evictable pages
*
* @return NV_OK if succeeded
* @return NV_ERR_IN_USE if found pages that can be evicted
* @return NV_ERR_NO_MEMORY if no available pages could be found
*/
NV_STATUS pmaAddrtreeScanContiguous(
void *pMap, NvU64 addrBase, NvU64 rangeStart, NvU64 rangeEnd,
NvU64 numPages, NvU64 *freelist, NvU64 pageSize, NvU64 alignment,
NvU64 *pagesAllocated, NvBool bSkipEvict, NvBool bReverseAlloc);
NV_STATUS pmaAddrtreeScanDiscontiguous(
void *pMap, NvU64 addrBase, NvU64 rangeStart, NvU64 rangeEnd,
NvU64 numPages, NvU64 *freelist, NvU64 pageSize, NvU64 alignment,
NvU64 *pagesAllocated, NvBool bSkipEvict, NvBool bReverseAlloc);
void pmaAddrtreePrintTree(void *pMap, const char* str);
/*!
* @brief Changes the state & attrib bits specified by mask
*
* Changes the state of the bits given the physical frame number
* TODO: all four interfaces need to be merged from PMA level so we can remove them!
*
* @param[in] pMap The addrtree to change
* @param[in] frameNum The frame number to change
* @param[in] newState The new state to change to
* @param[in] newStateMask Specific bits to write
*
* @return void
*/
void pmaAddrtreeChangeStateAttribEx(void *pMap, NvU64 frameNum, PMA_PAGESTATUS newState, PMA_PAGESTATUS newStateMask);
void pmaAddrtreeChangePageStateAttribEx(void * pMap, NvU64 startFrame, NvU64 pageSize,
PMA_PAGESTATUS newState, PMA_PAGESTATUS newStateMask);
/*!
* @brief Changes the state & attrib bits specified by mask
*
* Changes the state of the bits given the physical frame number
* and the number of frames to change
*
* @param[in] pMap The addrtree to change
* @param[in] frameNum The frame number to change
* @param[in] numFrames The number of frames to change
* @param[in] newState The new state to change to
* @param[in] newStateMask Specific bits to write
*
* @return void
*/
void pmaAddrtreeChangeBlockStateAttrib(void *pMap, NvU64 frameNum,
NvU64 numFrames,
PMA_PAGESTATUS newState,
PMA_PAGESTATUS newStateMask);
/*!
* @brief Read the page state & attrib bits
*
* Read the state of the page given the physical frame number
*
* @param[in] pMap The addrtree to read
* @param[in] frameNum The frame number to read
* @param[in] readAttrib Read attribute bits as well
*
* @return PAGESTATUS of the frame
*/
PMA_PAGESTATUS pmaAddrtreeRead(void *pMap, NvU64 frameNum, NvBool readAttrib);
/*!
* @brief Gets the total size of specified PMA managed region.
*
* Gets the total size of current PMA managed region in the FB.
*
* @param[in] pMap Pointer to the addrtree for the region
* @param[in] pBytesTotal Pointer that will return total bytes for current region.
*
*/
void pmaAddrtreeGetSize(void *pMap, NvU64 *pBytesTotal);
/*!
* @brief Gets the size of the maximum free chunk of memory in specified region.
*
* Gets the size of the maximum free chunk of memory in the specified PMA managed
* region of the FB.
*
* @param[in] pMap Pointer to the addrtree for the region
* @param[in] pLargestFree Pointer that will return largest free in current region.
*
*/
void pmaAddrtreeGetLargestFree(void *pMap, NvU64 *pLargestFree);
/*!
* @brief Returns the address range that is completely available for eviction.
* - Should be ALLOC_UNPIN.
* In NUMA, OS manages memory and PMA will only track allocated memory in ALLOC_PIN
* and ALLOC_UNPIN state. FREE memory is managed by OS and cannot be tracked by PMA
* and hence PMA cannot consider FREE memory for eviction and can only consider frames
* in known state to PMA or eviction. ALLOC_PIN cannot be evicted and hence only ALLOC_UNPIN
* can be evictable.
*
*
* @param[in] pMap Pointer to the regmap for the region
* @param[in] addrBase Base address of the region
* @param[in] actualSize Size of the eviction range
* @param[in] pageSize Pagesize
* @param[out] evictStart Starting address of the eviction range
* @param[out] evictEnd End address of the eviction range.
*
* Returns:
* - NV_OK If there is evictable range of given size : actualSize
*
* - NV_ERR_NO_MEMORY if no contiguous range is evictable.
*/
NV_STATUS pmaAddrtreeScanContiguousNumaEviction(void *pMap, NvU64 addrBase,
NvLength actualSize, NvU64 pageSize, NvU64 *evictStart, NvU64 *evictEnd);
#ifdef __cplusplus
}
#endif
#endif // ADDRTREE_H

31
src/nvidia/inc/kernel/gpu/mem_mgr/phys_mem_allocator/map_defines.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2015-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2015-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -22,7 +22,7 @@
*/
/*!
* @brief Contains common defines between addrtree and regmap
* @brief Contains common defines for regmap
*/
#ifndef MAP_DEFINES_H
@@ -44,30 +44,11 @@ extern "C" {
#define PMA_GRANULARITY 0x10000
#define PMA_PAGE_SHIFT 16
//
// _PMA_1GB will cause overflows with an NvU32. It's bigger than NvU32 can store,
// but compilation still fails when using a NvU64 instead
// So just use bitshift.
// 1 << _TREE_64KB == sizeof(1 frame)
//
#define _TREE_64KB 16
#define _TREE_128KB 17
#define _TREE_2MB 21
#define _TREE_128MB 27
#define _TREE_512MB 29
#define _TREE_32GB 35
#define _TREE_2TB 40
// Defines shared between pma.c and regmap.c
#define _PMA_64KB (64 * 1024)
#define _PMA_128KB (128 * 1024)
#define _PMA_2MB (2 * 1024 * 1024)
#define _PMA_512MB (512 * 1024 * 1024)
// Scanning function return code
#define EVICTABLE -2
#define ALL_FREE -3
#define _PMA_64KB (64ULL * 1024)
#define _PMA_128KB (128ULL * 1024)
#define _PMA_2MB (2ULL * 1024 * 1024)
#define _PMA_512MB (512ULL * 1024 * 1024)
typedef NvU32 PMA_PAGESTATUS;

38
src/nvidia/inc/kernel/gpu/mem_mgr/phys_mem_allocator/phys_mem_allocator.h
View File

@@ -42,7 +42,6 @@
#include "nvport/nvport.h"
#include "regmap.h"
#include "addrtree.h"
#include "nvmisc.h"
#if defined(SRT_BUILD)
@@ -72,7 +71,7 @@ typedef struct SCRUB_NODE SCRUB_NODE;
#define PMA_INIT_NUMA NVBIT(2)
#define PMA_INIT_INTERNAL NVBIT(3) // Used after heap is removed
#define PMA_INIT_FORCE_PERSISTENCE NVBIT(4)
#define PMA_INIT_ADDRTREE NVBIT(5)
// unused
#define PMA_INIT_NUMA_AUTO_ONLINE NVBIT(6)
// These flags are used for querying PMA's config and/or state.
@@ -178,8 +177,8 @@ typedef NV_STATUS (*pmaEvictRangeCb_t)(void *ctxPtr, NvU64 physBegin, NvU64 phys
*/
typedef void *(*pmaMapInit_t)(NvU64 numFrames, NvU64 addrBase, PMA_STATS *pPmaStats, NvBool bProtected);
typedef void (*pmaMapDestroy_t)(void *pMap);
typedef void (*pmaMapChangeStateAttribEx_t)(void *pMap, NvU64 frameNum, PMA_PAGESTATUS newState, PMA_PAGESTATUS newStateMask);
typedef void (*pmaMapChangePageStateAttribEx_t)(void *pMap, NvU64 startFrame, NvU64 pageSize, PMA_PAGESTATUS newState, PMA_PAGESTATUS newStateMask);
typedef void (*pmaMapChangeStateAttrib_t)(void *pMap, NvU64 frameNum, PMA_PAGESTATUS newState, PMA_PAGESTATUS newStateMask);
typedef void (*pmaMapChangePageStateAttrib_t)(void *pMap, NvU64 startFrame, NvU64 pageSize, PMA_PAGESTATUS newState, PMA_PAGESTATUS newStateMask);
typedef void (*pmaMapChangeBlockStateAttrib_t)(void *pMap, NvU64 frameNum, NvU64 numFrames, PMA_PAGESTATUS newState, PMA_PAGESTATUS newStateMask);
typedef PMA_PAGESTATUS (*pmaMapRead_t)(void *pMap, NvU64 frameNum, NvBool readAttrib);
typedef NV_STATUS (*pmaMapScanContiguous_t)(void *pMap, NvU64 addrBase, NvU64 rangeStart, NvU64 rangeEnd,
@@ -200,8 +199,8 @@ struct _PMA_MAP_INFO
NvU32 mode;
pmaMapInit_t pmaMapInit;
pmaMapDestroy_t pmaMapDestroy;
pmaMapChangeStateAttribEx_t pmaMapChangeStateAttribEx;
pmaMapChangePageStateAttribEx_t pmaMapChangePageStateAttribEx;
pmaMapChangeStateAttrib_t pmaMapChangeStateAttrib;
pmaMapChangePageStateAttrib_t pmaMapChangePageStateAttrib;
pmaMapChangeBlockStateAttrib_t pmaMapChangeBlockStateAttrib;
pmaMapRead_t pmaMapRead;
pmaMapScanContiguous_t pmaMapScanContiguous;
@@ -474,33 +473,6 @@ NV_STATUS pmaAllocatePagesBroadcast(PMA **pPma, NvU32 pmaCount, NvLength allocat
*/
NV_STATUS pmaPinPages(PMA *pPma, NvU64 *pPages, NvLength pageCount, NvU64 pageSize);
/*!
* @brief Marks previously pinned pages as unpinned.
*
* It will return an error and rollback any change if any page is not
* previously marked "pinned". Behaviour is undefined is any blacklisted
* pages are unpinned.
*
* @param[in] pPages
* Array of base addresses of pages to pin
*
* @param[in] pageCount
* Number of pages to pin
*
* @param[in] pageSize
* Page size of each page being unpinned
*
* @return
* NV_ERR_GENERIC:
* Unexpected error. We try hard to avoid returning this error
* code,because it is not very informative.
* TODO some error for rollback
*
*/
NV_STATUS pmaUnpinPages(PMA *pPma, NvU64 *pPages, NvLength pageCount, NvU64 pageSize);
/*!
* @brief Marks a list of pages as free.
* This operation is also used by RM to mark pages as "scrubbed" for the

10
src/nvidia/inc/kernel/gpu/mem_mgr/phys_mem_allocator/regmap.h
View File

@@ -103,8 +103,8 @@ void pmaRegmapSetEvictingFrames(void *pMap, NvU64 frameEvictionsInProcess);
*
* @return void
*/
void pmaRegmapChangePageStateAttribEx(void * pMap, NvU64 frameNumStart, NvU64 pageSize,
PMA_PAGESTATUS newState, PMA_PAGESTATUS newStateMask);
void pmaRegmapChangePageStateAttrib(void * pMap, NvU64 startFrame, NvU64 pageSize,
PMA_PAGESTATUS newState, PMA_PAGESTATUS newStateMask);
/*!
* @brief Changes the state & attrib bits specified by mask
@@ -118,9 +118,9 @@ void pmaRegmapChangePageStateAttribEx(void * pMap, NvU64 frameNumStart, NvU64 pa
*
* @return void
*/
void pmaRegmapChangeStateAttribEx(void *pMap, NvU64 frameNum,
PMA_PAGESTATUS newState,
PMA_PAGESTATUS newStateMask);
void pmaRegmapChangeStateAttrib(void *pMap, NvU64 frameNum,
PMA_PAGESTATUS newState,
PMA_PAGESTATUS newStateMask);
/*!
* @brief Changes the state & attrib bits specified by mask

109
src/nvidia/inc/kernel/gpu/mem_mgr/sec2_utils.h
View File

@@ -1,112 +1,3 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#include "g_sec2_utils_nvoc.h"
#ifndef SEC2_UTILS_H
#define SEC2_UTILS_H
#include "gpu/gpu_resource.h" // GpuResource
#include "kernel/gpu/mem_mgr/channel_utils.h"
#include "kernel/gpu/conf_compute/ccsl_context.h"
#define SEC2_AUTH_TAG_BUF_SIZE_BYTES (16)
#define SHA_256_HASH_SIZE_BYTES (32)
typedef struct
{
MEMORY_DESCRIPTOR *pMemDesc;
NvU64 offset;
NvU64 length;
NvU64 submittedWorkId;
} SEC2UTILS_MEMSET_PARAMS;
typedef struct
{
NvHandle hPhysMem;
NvHandle hVirtMem;
NvHandle hVASpace;
NvU64 gpuVA;
NvU64 size;
MEMORY_DESCRIPTOR *pMemDesc;
} SEC2UTILS_BUFFER_INFO;
NVOC_PREFIX(sec2utils) class Sec2Utils : Object
{
public:
NV_STATUS sec2utilsConstruct(Sec2Utils *psec2utils, OBJGPU *pGpu, KERNEL_MIG_GPU_INSTANCE *pKernelMIGGPUInstance);
void sec2utilsDestruct(Sec2Utils *psec2utils);
NV_STATUS sec2utilsMemset(Sec2Utils *psec2utils, SEC2UTILS_MEMSET_PARAMS *pParams);
NvU64 sec2utilsUpdateProgress(Sec2Utils *psec2utils);
void sec2utilsServiceInterrupts(Sec2Utils *psec2utils);
//
// Internal states
//
NvHandle hClient;
NvHandle hDevice;
NvHandle hSubdevice;
OBJCHANNEL *pChannel;
OBJGPU *pGpu;
NvU32 sec2Class;
NvU64 lastSubmittedPayload;
NvU64 lastCompletedPayload;
CCSL_CONTEXT *pCcslCtx;
//
// 4K page consisting of 128 auth tag buffers.
// One buffer is used per sec2 method stream.
// RM scrubber can submit multiple scrub method streams per sec2 operation.
//
SEC2UTILS_BUFFER_INFO scrubMthdAuthTagBuf;
//
// 4K page consisting of 128 auth tag buffers.
// One buffer is used per scrubber operation (not per sec2 scrub method stream).
// One scrub op corresponds to one call to sec2UtilsMemSet
//
SEC2UTILS_BUFFER_INFO semaMthdAuthTagBuf;
//
// Updated by RM to point to current auth tag buffer index (0-127)
// so its incremented for every scrub method stream.
//
NvU32 authTagPutIndex;
//
// Updated by SEC2 engine to point to last used/ last "seen" auth tag buffer index.
// This is updated based on completion of every scrub method stream.
//
NvU32 authTagGetIndex;
};
#endif // SEC2_UTILS_H

3
src/nvidia/inc/kernel/gpu/nvenc/nvencsession.h Normal file
View File

@@ -0,0 +1,3 @@
#include "g_nvencsession_nvoc.h"

3
src/nvidia/inc/kernel/gpu/perf/kern_cuda_limit.h
View File

@@ -25,13 +25,14 @@
#define KERNEL_CUDA_LIMIT_H
/* ------------------------ Includes --------------------------------------- */
#include "gpu/device/device.h"
/* ------------------------ Macros ----------------------------------------- */
/* ------------------------ Datatypes -------------------------------------- */
typedef struct Device Device;
/* -------------------- Function Prototypes -------------------------------- */
// Device CLI interfaces

1
src/nvidia/inc/kernel/gpu/rc/kernel_rc_watchdog_private.h
View File

@@ -79,6 +79,7 @@ typedef struct {
NvNotification *notifiers[NV_MAX_SUBDEVICES];
NvNotification *errorContext;
NvNotification *notifierToken;
NvBool bHandleValid;
} KernelWatchdog;

4
src/nvidia/inc/kernel/gpu/subdevice/subdevice_ctrl_event.h
View File

@@ -55,3 +55,7 @@
NV_STATUS subdeviceCtrlCmdEventVideoBindEvtbuf(Subdevice *pSubdevice,
NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_PARAMS *pBindParams);
RMCTRL_EXPORT(NV2080_CTRL_CMD_EVENT_RATS_GSP_TRACE_BIND_EVTBUF,
RMCTRL_FLAGS(PRIVILEGED))
NV_STATUS subdeviceCtrlCmdEventGspTraceRatsBindEvtbuf(Subdevice *pSubdevice,
NV2080_CTRL_EVENT_RATS_GSP_TRACE_BIND_EVTBUF_PARAMS *pBindParams);