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515.57

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This commit is contained in:
Andy Ritger
2022-06-28 08:00:06 -07:00
parent 965db98552
commit 94eaea9726
37 changed files with 556 additions and 353 deletions
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5
src/common/displayport/inc/dp_messages.h
View File

@@ -116,7 +116,9 @@ namespace DisplayPort
bool isBeingDestroyed;
bool isPaused;
// Properties from regkey
bool bNoReplyTimerForBusyWaiting;
bool bDpcdProbingForBusyWaiting;
List messageReceivers;
List notYetSentDownRequest; // Down Messages yet to be processed
@@ -159,7 +161,8 @@ namespace DisplayPort
{
DP_ASSERT(dpRegkeyDatabase.bInitialized &&
"All regkeys are invalid because dpRegkeyDatabase is not initialized!");
bNoReplyTimerForBusyWaiting = dpRegkeyDatabase.bNoReplyTimerForBusyWaiting;
bNoReplyTimerForBusyWaiting = dpRegkeyDatabase.bNoReplyTimerForBusyWaiting;
bDpcdProbingForBusyWaiting = dpRegkeyDatabase.bDpcdProbingForBusyWaiting;
}
MessageManager(DPCDHAL * hal, Timer * timer)

4
src/common/displayport/inc/dp_regkeydatabase.h
View File

@@ -72,6 +72,9 @@
#define NV_DP_DSC_OPTIMIZE_LT_BUG_3534707 "DP_DSC_OPTIMIZE_LT_BUG_3534707"
#define NV_DP_REGKEY_NO_REPLY_TIMER_FOR_BUSY_WAITING "NO_REPLY_TIMER_FOR_BUSY_WAITING"
#define NV_DP_REGKEY_DPCD_PROBING_FOR_BUSY_WAITING "DP_DPCD_PROBING_FOR_BUSY_WAITING"
//
// Data Base used to store all the regkey values.
// The actual data base is declared statically in dp_evoadapter.cpp.
@@ -106,6 +109,7 @@ struct DP_REGKEY_DATABASE
bool bDscMstEnablePassThrough;
bool bDscOptimizeLTBug3534707;
bool bNoReplyTimerForBusyWaiting;
bool bDpcdProbingForBusyWaiting;
};
#endif //INCLUDED_DP_REGKEYDATABASE_H

3
src/common/displayport/src/dp_evoadapter.cpp
View File

@@ -96,7 +96,8 @@ const struct
{NV_DP_DSC_MST_CAP_BUG_3143315, &dpRegkeyDatabase.bDscMstCapBug3143315, DP_REG_VAL_BOOL},
{NV_DP_DSC_MST_ENABLE_PASS_THROUGH, &dpRegkeyDatabase.bDscMstEnablePassThrough, DP_REG_VAL_BOOL},
{NV_DP_DSC_OPTIMIZE_LT_BUG_3534707, &dpRegkeyDatabase.bDscOptimizeLTBug3534707, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_NO_REPLY_TIMER_FOR_BUSY_WAITING, &dpRegkeyDatabase.bNoReplyTimerForBusyWaiting, DP_REG_VAL_BOOL}
{NV_DP_REGKEY_NO_REPLY_TIMER_FOR_BUSY_WAITING, &dpRegkeyDatabase.bNoReplyTimerForBusyWaiting, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_DPCD_PROBING_FOR_BUSY_WAITING, &dpRegkeyDatabase.bDpcdProbingForBusyWaiting, DP_REG_VAL_BOOL}
};
EvoMainLink::EvoMainLink(EvoInterface * provider, Timer * timer) :

15
src/common/displayport/src/dp_messages.cpp
View File

@@ -72,6 +72,20 @@ bool MessageManager::send(MessageManager::Message * message, NakData & nakData)
startTime = timer->getTimeUs();
do
{
if (bDpcdProbingForBusyWaiting)
{
hal->updateDPCDOffline();
if (hal->isDpcdOffline())
{
DP_LOG(("DP-MM> Device went offline while waiting for reply and so ignoring message %p (ID = %02X, target = %s)",
(Message*)this, ((Message*)this)->requestIdentifier, (((Message*)this)->state.target).toString(sb)));
nakData = completion.nakData;
completion.failed = true;
break;
}
}
hal->notifyIRQ();
if (hal->interruptDownReplyReady())
IRQDownReply();
@@ -81,6 +95,7 @@ bool MessageManager::send(MessageManager::Message * message, NakData & nakData)
nakData = completion.nakData;
break;
}
elapsedTime = timer->getTimeUs() - startTime;
if (elapsedTime > (DPCD_MESSAGE_REPLY_TIMEOUT * 1000))

34
src/common/displayport/src/dp_wardatabase.cpp
View File

@@ -568,18 +568,28 @@ void Edid::applyEdidWorkArounds(NvU32 warFlag, const DpMonitorDenylistData *pDen
}
break;
//
// This panel advertise DSC capabilities, but panel doesn't support DSC
// So ignoring DSC capability on this panel
//
case 0x6F0E:
if (ProductID == 0x1609)
{
this->WARFlags.bIgnoreDscCap = true;
DP_LOG(("DP-WAR> Ignoring DSC capability on Lenovo CSOT 1609 Panel."));
DP_LOG(("DP-WAR> Bug 3444252"));
}
break;
//
// This panel advertise DSC capabilities, but panel doesn't support DSC
// So ignoring DSC capability on this panel
//
case 0x6F0E:
if (ProductID == 0x1609)
{
this->WARFlags.bIgnoreDscCap = true;
DP_LOG(("DP-WAR> Ignoring DSC capability on Lenovo CSOT 1609 Panel."));
DP_LOG(("DP-WAR> Bug 3444252"));
}
break;
// Asus
case 0x6D1E:
if(ProductID == 0x7707)
{
this->WARFlags.bIgnoreDscCap = true;
DP_LOG(("DP-WAR> Panel incorrectly exposing DSC capability. Ignoring it."));
DP_LOG(("DP-WAR> Bug 3543158"));
}
break;
default:
break;

20
src/common/inc/nvBldVer.h
View File

@@ -36,25 +36,25 @@
// and then checked back in. You cannot make changes to these sections without
// corresponding changes to the buildmeister script
#ifndef NV_BUILD_BRANCH
#define NV_BUILD_BRANCH r516_10
#define NV_BUILD_BRANCH r515_00
#endif
#ifndef NV_PUBLIC_BRANCH
#define NV_PUBLIC_BRANCH r516_10
#define NV_PUBLIC_BRANCH r515_00
#endif
#if defined(NV_LINUX) || defined(NV_BSD) || defined(NV_SUNOS)
#define NV_BUILD_BRANCH_VERSION "rel/gpu_drv/r515/r516_10-205"
#define NV_BUILD_CHANGELIST_NUM (31396299)
#define NV_BUILD_BRANCH_VERSION "rel/gpu_drv/r515/r515_00-269"
#define NV_BUILD_CHANGELIST_NUM (31485447)
#define NV_BUILD_TYPE "Official"
#define NV_BUILD_NAME "rel/gpu_drv/r515/r516_10-205"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (31396299)
#define NV_BUILD_NAME "rel/gpu_drv/r515/r515_00-269"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (31485447)
#else /* Windows builds */
#define NV_BUILD_BRANCH_VERSION "r516_10-10"
#define NV_BUILD_CHANGELIST_NUM (31385161)
#define NV_BUILD_BRANCH_VERSION "r515_00-210"
#define NV_BUILD_CHANGELIST_NUM (31485447)
#define NV_BUILD_TYPE "Official"
#define NV_BUILD_NAME "516.26"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (31385161)
#define NV_BUILD_NAME "516.56"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (31485447)
#define NV_BUILD_BRANCH_BASE_VERSION R515
#endif
// End buildmeister python edited section

2
src/common/inc/nvUnixVersion.h
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@@ -4,7 +4,7 @@
#if defined(NV_LINUX) || defined(NV_BSD) || defined(NV_SUNOS) || defined(NV_VMWARE) || defined(NV_QNX) || defined(NV_INTEGRITY) || \
(defined(RMCFG_FEATURE_PLATFORM_GSP) && RMCFG_FEATURE_PLATFORM_GSP == 1)
#define NV_VERSION_STRING "515.48.07"
#define NV_VERSION_STRING "515.57"
#else

15
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080internal.h
View File

@@ -2223,4 +2223,19 @@ typedef struct NV2080_CTRL_INTERNAL_BIF_SET_PCIE_RO_PARAMS {
NvBool enableRo;
} NV2080_CTRL_INTERNAL_BIF_SET_PCIE_RO_PARAMS;
/*!
* NV2080_CTRL_CMD_INTERNAL_GET_COHERENT_FB_APERTURE_SIZE
*
* Query Coherent FB Aperture Size.
*
*/
#define NV2080_CTRL_CMD_INTERNAL_GET_COHERENT_FB_APERTURE_SIZE (0x20800aba) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GET_COHERENT_FB_APERTURE_SIZE_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_INTERNAL_GET_COHERENT_FB_APERTURE_SIZE_PARAMS_MESSAGE_ID (0xbaU)
typedef struct NV2080_CTRL_INTERNAL_GET_COHERENT_FB_APERTURE_SIZE_PARAMS {
// Get Coherent Fb Aperture Size
NV_DECLARE_ALIGNED(NvU64 coherentFbApertureSize, 8);
} NV2080_CTRL_INTERNAL_GET_COHERENT_FB_APERTURE_SIZE_PARAMS;
/* ctrl2080internal_h */