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This commit is contained in:
Andy Ritger
2022-05-27 16:40:24 -07:00
parent af26e1ea89
commit 965db98552
114 changed files with 18493 additions and 22785 deletions
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4
src/common/displayport/inc/dp_connectorimpl.h
View File

@@ -320,6 +320,9 @@ namespace DisplayPort
//
bool bDscMstEnablePassThrough;
// Reduce number of 2H1OR LTs which fixes bug 3534707
bool bDscOptimizeLTBug3534707;
//
// Synaptics branch device doesn't support Virtual Peer Devices so DSC
// capability of downstream device should be decided based on device's own
@@ -505,6 +508,7 @@ namespace DisplayPort
void populateDscGpuCaps(DSC_INFO* dscInfo);
void populateForcedDscParams(DSC_INFO* dscInfo, DSC_INFO::FORCED_DSC_PARAMS* forcedParams);
void populateDscSinkCaps(DSC_INFO* dscInfo, DeviceImpl * dev);
void populateDscBranchCaps(DSC_INFO* dscInfo, DeviceImpl * dev);
void populateDscModesetInfo(MODESET_INFO * pModesetInfo, const DpModesetParams * pModesetParams);
bool train(const LinkConfiguration & lConfig, bool force, LinkTrainingType trainType = NORMAL_LINK_TRAINING);

2
src/common/displayport/inc/dp_deviceimpl.h
View File

@@ -425,7 +425,9 @@ namespace DisplayPort
NvBool isDSCPossible();
bool isFECSupported();
bool readAndParseDSCCaps();
bool readAndParseBranchSpecificDSCCaps();
bool parseDscCaps(const NvU8 *buffer, NvU32 bufferSize);
bool parseBranchSpecificDscCaps(const NvU8 *buffer, NvU32 bufferSize);
bool setDscEnable(bool enable);
bool getDscEnable(bool *pEnable);
unsigned getDscVersionMajor();

4
src/common/displayport/inc/dp_groupimpl.h
View File

@@ -53,6 +53,8 @@ namespace DisplayPort
bool bWaitForDeAllocACT;
bool bDeferredPayloadAlloc;
ModesetInfo lastModesetInfo;
DSC_MODE dscModeRequest; // DSC mode requested during NAB
DSC_MODE dscModeActive; // DSC mode currently active, set in NAE
DP_SINGLE_HEAD_MULTI_STREAM_PIPELINE_ID singleHeadMultiStreamID;
DP_SINGLE_HEAD_MULTI_STREAM_MODE singleHeadMultiStreamMode;
DP_COLORFORMAT colorFormat;
@@ -76,6 +78,8 @@ namespace DisplayPort
hdcpEnabled(false),
hdcpPreviousStatus(false),
bWaitForDeAllocACT(false),
dscModeRequest(DSC_MODE_NONE),
dscModeActive(DSC_MODE_NONE),
singleHeadMultiStreamID(DP_SINGLE_HEAD_MULTI_STREAM_PIPELINE_ID_PRIMARY),
singleHeadMultiStreamMode(DP_SINGLE_HEAD_MULTI_STREAM_MODE_NONE),
bIsCurrentModesetGroup(false),

11
src/common/displayport/inc/dp_messages.h
View File

@@ -116,6 +116,8 @@ namespace DisplayPort
bool isBeingDestroyed;
bool isPaused;
bool bNoReplyTimerForBusyWaiting;
List messageReceivers;
List notYetSentDownRequest; // Down Messages yet to be processed
List notYetSentUpReply; // Up Reply Messages yet to be processed
@@ -153,6 +155,13 @@ namespace DisplayPort
mergerDownReply.mailboxInterrupt();
}
void applyRegkeyOverrides(const DP_REGKEY_DATABASE& dpRegkeyDatabase)
{
DP_ASSERT(dpRegkeyDatabase.bInitialized &&
"All regkeys are invalid because dpRegkeyDatabase is not initialized!");
bNoReplyTimerForBusyWaiting = dpRegkeyDatabase.bNoReplyTimerForBusyWaiting;
}
MessageManager(DPCDHAL * hal, Timer * timer)
: timer(timer), hal(hal),
splitterDownRequest(hal, timer),
@@ -236,6 +245,7 @@ namespace DisplayPort
MessageManager * parent;
bool transmitReply;
bool bTransmitted;
bool bBusyWaiting;
unsigned requestIdentifier;
unsigned messagePriority;
unsigned sinkPort;
@@ -261,6 +271,7 @@ namespace DisplayPort
parent(0),
transmitReply(false),
bTransmitted(false),
bBusyWaiting(false),
requestIdentifier(requestIdentifier),
messagePriority(messagePriority),
sinkPort(0xFF)

8
src/common/displayport/inc/dp_regkeydatabase.h
View File

@@ -65,11 +65,13 @@
//
#define NV_DP_DSC_MST_CAP_BUG_3143315 "DP_DSC_MST_CAP_BUG_3143315"
//
// Enable DSC Pass through support in MST mode.
//
#define NV_DP_DSC_MST_ENABLE_PASS_THROUGH "DP_DSC_MST_ENABLE_PASS_THROUGH"
// Regkey to reduce number of 2H1OR LTs which fixes bug 3534707
#define NV_DP_DSC_OPTIMIZE_LT_BUG_3534707 "DP_DSC_OPTIMIZE_LT_BUG_3534707"
#define NV_DP_REGKEY_NO_REPLY_TIMER_FOR_BUSY_WAITING "NO_REPLY_TIMER_FOR_BUSY_WAITING"
//
// Data Base used to store all the regkey values.
// The actual data base is declared statically in dp_evoadapter.cpp.
@@ -102,6 +104,8 @@ struct DP_REGKEY_DATABASE
bool bBypassEDPRevCheck;
bool bDscMstCapBug3143315;
bool bDscMstEnablePassThrough;
bool bDscOptimizeLTBug3534707;
bool bNoReplyTimerForBusyWaiting;
};
#endif //INCLUDED_DP_REGKEYDATABASE_H

116
src/common/displayport/src/dp_connectorimpl.cpp
View File

@@ -189,6 +189,7 @@ void ConnectorImpl::applyRegkeyOverrides(const DP_REGKEY_DATABASE& dpRegkeyDatab
this->bEnableFastLT = dpRegkeyDatabase.bFastLinkTrainingEnabled;
this->bDscMstCapBug3143315 = dpRegkeyDatabase.bDscMstCapBug3143315;
this->bDscMstEnablePassThrough = dpRegkeyDatabase.bDscMstEnablePassThrough;
this->bDscOptimizeLTBug3534707 = dpRegkeyDatabase.bDscOptimizeLTBug3534707;
}
void ConnectorImpl::setPolicyModesetOrderMitigation(bool enabled)
@@ -630,6 +631,12 @@ create:
{
// Read and parse DSC caps only if panel supports DSC
newDev->readAndParseDSCCaps();
// Read and Parse Branch Specific DSC Caps
if (!newDev->isVideoSink() && !newDev->isAudioSink())
{
newDev->readAndParseBranchSpecificDSCCaps();
}
}
// Decide if DSC stream can be sent to new device
@@ -655,13 +662,13 @@ create:
if (this->bDscMstEnablePassThrough)
{
//
// Check the device's own and its parent's DSC capability.
// - Sink device will do DSC cecompression when
// Check the device's own and its parent's DSC capability.
// - Sink device will do DSC cecompression when
// 1. Sink device is capable of DSC decompression and parent
// supports DSC pass through.
//
// - Sink device's parent will do DSC decompression
// 1. If sink device supports DSC decompression but it's parent does not support
// - Sink device's parent will do DSC decompression
// 1. If sink device supports DSC decompression but it's parent does not support
// DSC Pass through, but supports DSC decompression.
// 2. If the device does not support DSC decompression, but parent supports it.
//
@@ -672,7 +679,7 @@ create:
if (newDev->parent->isDSCPassThroughSupported())
{
//
// This condition takes care of DSC capable sink devices
// This condition takes care of DSC capable sink devices
// connected behind a DSC Pass through capable branch
//
newDev->devDoingDscDecompression = newDev;
@@ -681,12 +688,12 @@ create:
else if (newDev->parent->isDSCSupported())
{
//
// This condition takes care of DSC capable sink devices
// This condition takes care of DSC capable sink devices
// connected behind a branch device that is not capable
// of DSC pass through but can do DSC decompression.
//
newDev->bDSCPossible = true;
newDev->devDoingDscDecompression = newDev->parent;
newDev->devDoingDscDecompression = newDev->parent;
}
}
else
@@ -695,11 +702,11 @@ create:
newDev->devDoingDscDecompression = newDev;
newDev->bDSCPossible = true;
}
}
}
else if (newDev->parent && newDev->parent->isDSCSupported())
{
//
// This condition takes care of sink devices not capable of DSC
// This condition takes care of sink devices not capable of DSC
// but parent is capable of DSC decompression.
//
newDev->bDSCPossible = true;
@@ -709,7 +716,7 @@ create:
else
{
//
// Revert to old code if DSC Pass through support is not requested.
// Revert to old code if DSC Pass through support is not requested.
// This code will be deleted once DSC Pass through support will be enabled
// by default which will be done when 2Head1OR MST (GR-133) will be in production.
//
@@ -1726,6 +1733,15 @@ void ConnectorImpl::populateDscGpuCaps(DSC_INFO* dscInfo)
dscInfo->gpuCaps.lineBufferBitDepth = lineBufferBitDepth;
}
void ConnectorImpl::populateDscBranchCaps(DSC_INFO* dscInfo, DeviceImpl * dev)
{
dscInfo->branchCaps.overallThroughputMode0 = dev->dscCaps.branchDSCOverallThroughputMode0;
dscInfo->branchCaps.overallThroughputMode1 = dev->dscCaps.branchDSCOverallThroughputMode1;
dscInfo->branchCaps.maxLineBufferWidth = dev->dscCaps.branchDSCMaximumLineBufferWidth;
return;
}
void ConnectorImpl::populateDscSinkCaps(DSC_INFO* dscInfo, DeviceImpl * dev)
{
// Early return if dscInfo or dev is NULL
@@ -1846,6 +1862,12 @@ void ConnectorImpl::populateDscCaps(DSC_INFO* dscInfo, DeviceImpl * dev, DSC_INF
// Sink DSC capabilities
populateDscSinkCaps(dscInfo, dev);
// Branch Specific DSC Capabilities
if (!dev->isVideoSink() && !dev->isAudioSink())
{
populateDscBranchCaps(dscInfo, dev);
}
// GPU DSC capabilities
populateDscGpuCaps(dscInfo);
@@ -2621,11 +2643,6 @@ bool ConnectorImpl::notifyAttachBegin(Group * target, // Gr
}
}
if (bEnableDsc)
{
DP_LOG(("DPCONN> DSC Mode = %s", (modesetParams.modesetInfo.mode == DSC_SINGLE) ? "SINGLE" : "DUAL"));
}
for (Device * dev = target->enumDevices(0); dev; dev = target->enumDevices(dev))
{
Address::StringBuffer buffer;
@@ -2641,6 +2658,12 @@ bool ConnectorImpl::notifyAttachBegin(Group * target, // Gr
GroupImpl* targetImpl = (GroupImpl*)target;
targetImpl->bIsCurrentModesetGroup = true;
if (bEnableDsc)
{
DP_LOG(("DPCONN> DSC Mode = %s", (modesetParams.modesetInfo.mode == DSC_SINGLE) ? "SINGLE" : "DUAL"));
targetImpl->dscModeRequest = modesetParams.modesetInfo.mode;
}
DP_ASSERT(!(targetImpl->isHeadAttached() && targetImpl->bIsHeadShutdownNeeded) && "Head should have been shut down but it is still active!");
targetImpl->headInFirmware = false;
@@ -2788,6 +2811,10 @@ void ConnectorImpl::notifyAttachEnd(bool modesetCancelled)
currentModesetDeviceGroup->setHeadAttached(false);
}
// set dscModeActive to what was requested in NAB and clear dscModeRequest
currentModesetDeviceGroup->dscModeActive = currentModesetDeviceGroup->dscModeRequest;
currentModesetDeviceGroup->dscModeRequest = DSC_MODE_NONE;
currentModesetDeviceGroup->setHeadAttached(true);
RmDfpCache dfpCache = {0};
dfpCache.updMask = 0;
@@ -2934,6 +2961,7 @@ void ConnectorImpl::notifyDetachEnd(bool bKeepOdAlive)
dpMemZero(&currentModesetDeviceGroup->lastModesetInfo, sizeof(ModesetInfo));
currentModesetDeviceGroup->setHeadAttached(false);
currentModesetDeviceGroup->headInFirmware = false;
currentModesetDeviceGroup->dscModeActive = DSC_MODE_NONE;
// Mark head as disconnected
bNoLtDoneAfterHeadDetach = true;
@@ -3980,18 +4008,36 @@ bool ConnectorImpl::trainLinkOptimized(LinkConfiguration lConfig)
GroupImpl * groupAttached = 0;
for (ListElement * e = activeGroups.begin(); e != activeGroups.end(); e = e->next)
{
DP_ASSERT(bIsUefiSystem || (!groupAttached && "Multiple attached heads"));
DP_ASSERT(bIsUefiSystem);
groupAttached = (GroupImpl * )e;
if ((groupAttached->lastModesetInfo.mode == DSC_DUAL) && groupAttached->bIsCurrentModesetGroup)
if (bDscOptimizeLTBug3534707)
{
//
// If current modeset group requires 2Head1OR mode, we should retrain link.
// For SST, there will be only one group per connector.
// For MST, we need to re-run LT in case the current modeset group requires DSC_DUAL.
//
bTwoHeadOneOrLinkRetrain = true;
break;
if ((groupAttached->dscModeRequest == DSC_DUAL) && (groupAttached->dscModeActive != DSC_DUAL))
{
//
// If current modeset group requires 2Head1OR and
// - group is not active yet (first modeset on the group)
// - group is active but not in 2Head1OR mode (last modeset on the group did not require 2Head1OR)
// then re-train the link
// This is because for 2Head1OR mode, we need to set some LT parametes for slave SOR after
// successful LT on primary SOR without which 2Head1OR modeset will lead to HW hang.
//
bTwoHeadOneOrLinkRetrain = true;
break;
}
}
else
{
if (groupAttached->lastModesetInfo.mode == DSC_DUAL && groupAttached->bIsCurrentModesetGroup)
{
//
// If current modeset group requires 2Head1OR mode, we should retrain link.
// For SST, there will be only one group per connector.
// For MST, we need to re-run LT in case the current modeset group requires DSC_DUAL.
bTwoHeadOneOrLinkRetrain = true;
break;
}
}
}
@@ -4077,10 +4123,10 @@ bool ConnectorImpl::trainLinkOptimized(LinkConfiguration lConfig)
{
//
// Check if we are already trained to the desired link config?
// Even if we are, we need to redo LT if FEC is enabled or DSC mode is DSC_DUAL
// since if current modeset requires 2H1OR, LT done during assessLink will not
// have 2H1Or flag set or if last modeset required DSC but not 2H1OR, still 2H1Or
// flag will not be set and modeset will lead to HW hang.
// Make sure requested FEC state matches with the current FEC state of link.
// If 2Head1OR mode is requested, retrain if group is not active or
// last modeset on active group was not in 2Head1OR mode.
// bTwoHeadOneOrLinkRetrain tracks this requirement.
//
//
@@ -4093,7 +4139,8 @@ bool ConnectorImpl::trainLinkOptimized(LinkConfiguration lConfig)
if ((activeLinkConfig == lowestSelected) &&
(!isLinkInD3()) &&
(!isLinkLost()) &&
!(this->bFECEnable) &&
((!bDscOptimizeLTBug3534707 && !this->bFECEnable) ||
(bDscOptimizeLTBug3534707 && (this->bFECEnable == activeLinkConfig.bEnableFEC))) &&
!bTwoHeadOneOrLinkRetrain)
{
if (bSkipRedundantLt || main->isInternalPanelDynamicMuxCapable())
@@ -4209,11 +4256,9 @@ bool ConnectorImpl::trainLinkOptimized(LinkConfiguration lConfig)
//
// Make sure link is physically active and healthy, otherwise re-train.
// We need to retrain if the link is in 2Head1OR MST mode. For example,
// if we plug in a 2Head1OR panel to an active link that is already driving
// a MST panel in DSC mode, RM will assign a secondary OR to the 2Head1OR panel.
// But since there is no change required in linkConfig DPlib will skip
// LT, resutling in not adding secondary OR to LT; this will lead to HW hang.
// Make sure requested FEC state matches with the current FEC state of link.
// If 2Head1OR mode is requested, retrain if group is not active or last modeset on active group
// was not in 2Head1OR mode. bTwoHeadOneOrLinkRetrain tracks this requirement.
//
bRetrainToEnsureLinkStatus = (isLinkActive() && isLinkInD3()) ||
isLinkLost() ||
@@ -5660,7 +5705,7 @@ void ConnectorImpl::notifyLongPulseInternal(bool statusConnected)
if (hal->getSupportsMultistream() && main->hasMultistream())
{
bool bDeleteFirmwareVC = false;
const DP_REGKEY_DATABASE& dpRegkeyDatabase = main->getRegkeyDatabase();
DP_LOG(("DP> Multistream panel detected, building message manager"));
//
@@ -5669,6 +5714,7 @@ void ConnectorImpl::notifyLongPulseInternal(bool statusConnected)
//
messageManager = new MessageManager(hal, timer);
messageManager->registerReceiver(&ResStatus);
messageManager->applyRegkeyOverrides(dpRegkeyDatabase);
//
// Create a discovery manager to initiate detection

59
src/common/displayport/src/dp_deviceimpl.cpp
View File

@@ -1687,6 +1687,50 @@ bool DeviceImpl::parseDscCaps(const NvU8 *buffer, NvU32 bufferSize)
return true;
}
bool DeviceImpl::parseBranchSpecificDscCaps(const NvU8 *buffer, NvU32 bufferSize)
{
if (bufferSize < 3)
{
DP_LOG((" Branch DSC caps buffer must be greater than or equal to 3"));
return false;
}
dscCaps.branchDSCOverallThroughputMode0 = DRF_VAL(_DPCD20, _BRANCH_DSC_OVERALL_THROUGHPUT_MODE_0, _VALUE, buffer[0x0]);
if (dscCaps.branchDSCOverallThroughputMode0 == 1)
{
dscCaps.branchDSCOverallThroughputMode0 = 680;
}
else if (dscCaps.branchDSCOverallThroughputMode0 >= 2)
{
dscCaps.branchDSCOverallThroughputMode0 = 600 + dscCaps.branchDSCOverallThroughputMode0 * 50;
}
dscCaps.branchDSCOverallThroughputMode1 = DRF_VAL(_DPCD20, _BRANCH_DSC_OVERALL_THROUGHPUT_MODE_1, _VALUE, buffer[0x1]);
if (dscCaps.branchDSCOverallThroughputMode1 == 1)
{
dscCaps.branchDSCOverallThroughputMode1 = 680;
}
else if (dscCaps.branchDSCOverallThroughputMode1 >= 2)
{
dscCaps.branchDSCOverallThroughputMode1 = 600 + dscCaps.branchDSCOverallThroughputMode1 * 50;
}
dscCaps.branchDSCMaximumLineBufferWidth = DRF_VAL(_DPCD20, _BRANCH_DSC_MAXIMUM_LINE_BUFFER_WIDTH, _VALUE, buffer[0x2]);
if (dscCaps.branchDSCMaximumLineBufferWidth != 0)
{
if (dscCaps.branchDSCMaximumLineBufferWidth >= 16)
{
dscCaps.branchDSCMaximumLineBufferWidth = dscCaps.branchDSCMaximumLineBufferWidth * 320;
}
else
{
dscCaps.branchDSCMaximumLineBufferWidth = 0;
DP_LOG(("Value of branch DSC maximum line buffer width is invalid, so setting it to 0."));
}
}
return true;
}
bool DeviceImpl::readAndParseDSCCaps()
{
// Allocate a buffer of 16 bytes to read DSC caps
@@ -1703,6 +1747,21 @@ bool DeviceImpl::readAndParseDSCCaps()
return parseDscCaps(&rawDscCaps[0], sizeof(rawDscCaps));
}
bool DeviceImpl::readAndParseBranchSpecificDSCCaps()
{
unsigned sizeCompleted = 0;
unsigned nakReason = NakUndefined;
NvU8 rawBranchSpecificDscCaps[3];
if(AuxBus::success != this->getDpcdData(NV_DPCD20_BRANCH_DSC_OVERALL_THROUGHPUT_MODE_0,
&rawBranchSpecificDscCaps[0], sizeof(rawBranchSpecificDscCaps), &sizeCompleted, &nakReason))
{
return false;
}
return parseBranchSpecificDscCaps(&rawBranchSpecificDscCaps[0], sizeof(rawBranchSpecificDscCaps));
}
bool DeviceImpl::getDscEnable(bool *pEnable)
{
AuxBus::status status = AuxBus::success;

4
src/common/displayport/src/dp_evoadapter.cpp
View File

@@ -94,7 +94,9 @@ const struct
{NV_DP_REGKEY_KEEP_OPT_LINK_ALIVE_SST, &dpRegkeyDatabase.bOptLinkKeptAliveSst, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_FORCE_EDP_ILR, &dpRegkeyDatabase.bBypassEDPRevCheck, DP_REG_VAL_BOOL},
{NV_DP_DSC_MST_CAP_BUG_3143315, &dpRegkeyDatabase.bDscMstCapBug3143315, DP_REG_VAL_BOOL},
{NV_DP_DSC_MST_ENABLE_PASS_THROUGH, &dpRegkeyDatabase.bDscMstEnablePassThrough, DP_REG_VAL_BOOL}
{NV_DP_DSC_MST_ENABLE_PASS_THROUGH, &dpRegkeyDatabase.bDscMstEnablePassThrough, DP_REG_VAL_BOOL},
{NV_DP_DSC_OPTIMIZE_LT_BUG_3534707, &dpRegkeyDatabase.bDscOptimizeLTBug3534707, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_NO_REPLY_TIMER_FOR_BUSY_WAITING, &dpRegkeyDatabase.bNoReplyTimerForBusyWaiting, DP_REG_VAL_BOOL}
};
EvoMainLink::EvoMainLink(EvoInterface * provider, Timer * timer) :

18
src/common/displayport/src/dp_messages.cpp
View File

@@ -63,6 +63,11 @@ bool MessageManager::send(MessageManager::Message * message, NakData & nakData)
DP_USED(sb);
NvU64 startTime, elapsedTime;
if (bNoReplyTimerForBusyWaiting)
{
message->bBusyWaiting = true;
}
post(message, &completion);
startTime = timer->getTimeUs();
do
@@ -152,14 +157,13 @@ void MessageManager::Message::splitterTransmitted(OutgoingTransactionManager * f
if (from == &parent->splitterDownRequest)
{
//
// Start the countdown timer for the reply
//
parent->timer->queueCallback(this, "SPLI", DPCD_MESSAGE_REPLY_TIMEOUT);
//
// Client will busy-waiting for the message to complete, we don't need the countdown timer.
if (!bBusyWaiting)
{
// Start the countdown timer for the reply
parent->timer->queueCallback(this, "SPLI", DPCD_MESSAGE_REPLY_TIMEOUT);
}
// Tell the message manager he may begin sending the next message
//
parent->transmitAwaitingDownRequests();
}
else // UpReply

4
src/common/inc/displayport/displayport.h
View File

@@ -262,6 +262,10 @@ typedef struct DscCaps
unsigned dscPeakThroughputMode1;
unsigned dscMaxSliceWidth;
unsigned branchDSCOverallThroughputMode0;
unsigned branchDSCOverallThroughputMode1;
unsigned branchDSCMaximumLineBufferWidth;
BITS_PER_PIXEL_INCREMENT dscBitsPerPixelIncrement;
} DscCaps;

1
src/common/inc/displayport/dpcd.h
View File

@@ -1083,6 +1083,7 @@ number of Downstream ports will be limited to 32.
#define NV_DPCD_EDP_DISPLAY_CTL_COLOR_ENGINE_EN_DISABLED (0x00000000) /* RWXUV */
#define NV_DPCD_EDP_DISPLAY_CTL_OVERDRIVE_CTL 5:4 /* RWXUF */
#define NV_DPCD_EDP_DISPLAY_CTL_OVERDRIVE_CTL_AUTONOMOUS (0x00000000) /* RWXUV */
#define NV_DPCD_EDP_DISPLAY_CTL_OVERDRIVE_CTL_AUTONOMOUS_1 (0x00000001) /* RWXUV */
#define NV_DPCD_EDP_DISPLAY_CTL_OVERDRIVE_CTL_DISABLE (0x00000002) /* RWXUV */
#define NV_DPCD_EDP_DISPLAY_CTL_OVERDRIVE_CTL_ENABLE (0x00000003) /* RWXUV */
#define NV_DPCD_EDP_DISPLAY_CTL_VBLANK_BKLGHT_UPDATE_EN 7:7 /* RWXUF */

11
src/common/inc/displayport/dpcd20.h
View File

@@ -44,3 +44,14 @@
#define NV_DPCD20_PANEL_REPLAY_CONFIGURATION_ENABLE_PR_MODE 0:0
#define NV_DPCD20_PANEL_REPLAY_CONFIGURATION_ENABLE_PR_MODE_NO (0x00000000)
#define NV_DPCD20_PANEL_REPLAY_CONFIGURATION_ENABLE_PR_MODE_YES (0x00000001)
/// BRANCH SPECIFIC DSC CAPS
#define NV_DPCD20_BRANCH_DSC_OVERALL_THROUGHPUT_MODE_0 (0x000000A0)
#define NV_DPCD20_BRANCH_DSC_OVERALL_THROUGHPUT_MODE_0_VALUE 7:0
#define NV_DPCD20_BRANCH_DSC_OVERALL_THROUGHPUT_MODE_1 (0x000000A1)
#define NV_DPCD20_BRANCH_DSC_OVERALL_THROUGHPUT_MODE_1_VALUE 7:0
#define NV_DPCD20_BRANCH_DSC_MAXIMUM_LINE_BUFFER_WIDTH (0x000000A2)
#define NV_DPCD20_BRANCH_DSC_MAXIMUM_LINE_BUFFER_WIDTH_VALUE 7:0

21
src/common/inc/nvBldVer.h
View File

@@ -36,25 +36,26 @@
// and then checked back in. You cannot make changes to these sections without
// corresponding changes to the buildmeister script
#ifndef NV_BUILD_BRANCH
#define NV_BUILD_BRANCH r515_95
#define NV_BUILD_BRANCH r516_10
#endif
#ifndef NV_PUBLIC_BRANCH
#define NV_PUBLIC_BRANCH r515_95
#define NV_PUBLIC_BRANCH r516_10
#endif
#if defined(NV_LINUX) || defined(NV_BSD) || defined(NV_SUNOS)
#define NV_BUILD_BRANCH_VERSION "rel/gpu_drv/r515/r515_95-155"
#define NV_BUILD_CHANGELIST_NUM (31261195)
#define NV_BUILD_BRANCH_VERSION "rel/gpu_drv/r515/r516_10-205"
#define NV_BUILD_CHANGELIST_NUM (31396299)
#define NV_BUILD_TYPE "Official"
#define NV_BUILD_NAME "rel/gpu_drv/r515/r515_95-155"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (31261195)
#define NV_BUILD_NAME "rel/gpu_drv/r515/r516_10-205"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (31396299)
#else /* Windows builds */
#define NV_BUILD_BRANCH_VERSION "r515_95-3"
#define NV_BUILD_CHANGELIST_NUM (31249857)
#define NV_BUILD_BRANCH_VERSION "r516_10-10"
#define NV_BUILD_CHANGELIST_NUM (31385161)
#define NV_BUILD_TYPE "Official"
#define NV_BUILD_NAME "516.01"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (31249857)
#define NV_BUILD_NAME "516.26"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (31385161)
#define NV_BUILD_BRANCH_BASE_VERSION R515
#endif
// End buildmeister python edited section

2
src/common/inc/nvPNPVendorIds.h
View File

@@ -29,7 +29,7 @@
* type const char*.
*
* References:
* http://www.uefi.org/pnp_id_list
* https://uefi.org/pnp_id_list
*
*/

2
src/common/inc/nvSha1.h
View File

@@ -26,7 +26,7 @@
* byte array, using the Secure Hashing Algorithm 1 (SHA-1) as defined
* in FIPS PUB 180-1 published April 17, 1995:
*
* http://www.itl.nist.gov/fipspubs/fip180-1.htm
* https://www.itl.nist.gov/fipspubs/fip180-1.htm
*
* Some common test cases (see Appendices A and B of the above document):
*

2
src/common/inc/nvUnixVersion.h
View File

@@ -4,7 +4,7 @@
#if defined(NV_LINUX) || defined(NV_BSD) || defined(NV_SUNOS) || defined(NV_VMWARE) || defined(NV_QNX) || defined(NV_INTEGRITY) || \
(defined(RMCFG_FEATURE_PLATFORM_GSP) && RMCFG_FEATURE_PLATFORM_GSP == 1)
#define NV_VERSION_STRING "515.43.04"
#define NV_VERSION_STRING "515.48.07"
#else

4
src/common/inc/swref/published/ampere/ga100/dev_fuse.h
View File

@@ -130,4 +130,8 @@
#define NV_FUSE_OPT_FPF_GSP_UCODE16_VERSION 0x008241FC /* RW-4R */
#define NV_FUSE_OPT_FPF_GSP_UCODE16_VERSION_DATA 15:0 /* RWIVF */
#define NV_FUSE_STATUS_OPT_DISPLAY 0x00820C04 /* R-I4R */
#define NV_FUSE_STATUS_OPT_DISPLAY_DATA 0:0 /* R-IVF */
#define NV_FUSE_STATUS_OPT_DISPLAY_DATA_ENABLE 0x00000000 /* R---V */
#endif // __ga100_dev_fuse_h__

9
src/common/inc/swref/published/ampere/ga100/dev_nv_xve_addendum.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2021 NVIDIA CORPORATION & AFFILIATES
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -42,4 +42,11 @@
//
#define NV_XVE_PASSTHROUGH_EMULATED_CONFIG_ROOT_PORT_SPEED 3:0
//
// On some platforms it's beneficial to enable relaxed ordering after vetting
// it's safe to do so. To automate this process on virtualized platforms, allow
// RO to be requested through this emulated config space bit.
//
#define NV_XVE_PASSTHROUGH_EMULATED_CONFIG_RELAXED_ORDERING_ENABLE 4:4
#endif

7
src/common/inc/swref/published/ampere/ga102/dev_gc6_island.h
View File

@@ -29,8 +29,9 @@
#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_03(i) (0x00118214+(i)*4) /* RW-4A */
#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_05(i) (0x00118234+(i)*4) /* RW-4A */
#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_42 0x001183a4 /* RW-4R */
#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_03(i) (0x00118214+(i)*4) /* RW-4A */
#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_05(i) (0x00118234+(i)*4) /* RW-4A */
#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_42 0x001183a4 /* RW-4R */
#define NV_PGC6_BSI_SECURE_SCRATCH_14 0x001180f8 /* RW-4R */
#endif // __ga102_dev_gc6_island_h__

3
src/common/inc/swref/published/ampere/ga102/dev_gc6_island_addendum.h
View File

@@ -33,6 +33,9 @@
#define NV_USABLE_FB_SIZE_IN_MB NV_PGC6_AON_SECURE_SCRATCH_GROUP_42
#define NV_USABLE_FB_SIZE_IN_MB_VALUE 31:0
#define NV_USABLE_FB_SIZE_IN_MB_VALUE_INIT 0
#define NV_PGC6_BSI_SECURE_SCRATCH_14_BOOT_STAGE_3_HANDOFF 26:26
#define NV_PGC6_BSI_SECURE_SCRATCH_14_BOOT_STAGE_3_HANDOFF_VALUE_INIT 0x0
#define NV_PGC6_BSI_SECURE_SCRATCH_14_BOOT_STAGE_3_HANDOFF_VALUE_DONE 0x1
#endif // __ga102_dev_gc6_island_addendum_h__

31
src/common/inc/swref/published/maxwell/gm107/dev_fuse.h Normal file
View File

@@ -0,0 +1,31 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gm107_dev_fuse_h__
#define __gm107_dev_fuse_h__
#define NV_FUSE_STATUS_OPT_DISPLAY 0x00021C04 /* R-I4R */
#define NV_FUSE_STATUS_OPT_DISPLAY_DATA 0:0 /* R-IVF */
#define NV_FUSE_STATUS_OPT_DISPLAY_DATA_ENABLE 0x00000000 /* R---V */
#endif // __gm107_dev_fuse_h__

5
src/common/inc/swref/published/turing/tu102/dev_gc6_island.h
View File

@@ -29,7 +29,8 @@
#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_03(i) (0x00118214+(i)*4) /* RW-4A */
#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_05(i) (0x00118234+(i)*4) /* RW-4A */
#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_03(i) (0x00118214+(i)*4) /* RW-4A */
#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_05(i) (0x00118234+(i)*4) /* RW-4A */
#define NV_PGC6_BSI_SECURE_SCRATCH_14 0x001180f8 /* RW-4R */
#endif // __tu102_dev_gc6_island_h__

3
src/common/inc/swref/published/turing/tu102/dev_gc6_island_addendum.h
View File

@@ -30,6 +30,9 @@
#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_0_GFW_BOOT NV_PGC6_AON_SECURE_SCRATCH_GROUP_05(0)
#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_0_GFW_BOOT_PROGRESS 7:0
#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_0_GFW_BOOT_PROGRESS_COMPLETED 0x000000FF
#define NV_PGC6_BSI_SECURE_SCRATCH_14_BOOT_STAGE_3_HANDOFF 26:26
#define NV_PGC6_BSI_SECURE_SCRATCH_14_BOOT_STAGE_3_HANDOFF_VALUE_INIT 0x0
#define NV_PGC6_BSI_SECURE_SCRATCH_14_BOOT_STAGE_3_HANDOFF_VALUE_DONE 0x1
#endif // __tu102_dev_gc6_island_addendum_h__

23
src/common/modeset/timing/nvt_dsc_pps.c
View File

@@ -84,6 +84,7 @@
#define MAX_BITS_PER_PIXEL 32
// Max HBlank pixel count
#define MAX_HBLANK_PIXELS 7680
#define MHZ_TO_HZ 1000000
/* ------------------------ Datatypes -------------------------------------- */
@@ -1570,12 +1571,26 @@ _validateInput
return NVT_STATUS_INVALID_PARAMETER;
}
if ((pDscInfo->branchCaps.overallThroughputMode0 != 0) &&
(pModesetInfo->pixelClockHz > pDscInfo->branchCaps.overallThroughputMode0 * MHZ_TO_HZ))
{
DSC_Print("ERROR - Pixel clock cannot be greater than Branch DSC Overall Throughput Mode 0");
return NVT_STATUS_INVALID_PARAMETER;
}
if (pModesetInfo->activeWidth == 0)
{
DSC_Print("ERROR - Invalid active width for mode.");
return NVT_STATUS_INVALID_PARAMETER;
}
if (pDscInfo->branchCaps.maxLineBufferWidth != 0 &&
pModesetInfo->activeWidth > pDscInfo->branchCaps.maxLineBufferWidth)
{
DSC_Print("ERROR - Active width cannot be greater than DSC Decompressor max line buffer width");
return NVT_STATUS_INVALID_PARAMETER;
}
if (pModesetInfo->activeHeight == 0)
{
DSC_Print("ERROR - Invalid active height for mode.");
@@ -1919,7 +1934,13 @@ DSC_GeneratePPS
if (*pBitsPerPixelX16 != 0)
{
*pBitsPerPixelX16 = DSC_AlignDownForBppPrecision(*pBitsPerPixelX16, pDscInfo->sinkCaps.bitsPerPixelPrecision);
if (*pBitsPerPixelX16 > in->bits_per_pixel)
// The calculation of in->bits_per_pixel here in PPSlib, which is the maximum bpp that is allowed by available bandwidth,
// which is applicable to DP alone and not to HDMI FRL.
// Before calling PPS lib to generate PPS data, HDMI library has done calculation according to HDMI2.1 spec
// to determine if FRL rate is sufficient for the requested bpp. So restricting the condition to DP alone.
if ((pWARData && (pWARData->connectorType == DSC_DP)) &&
(*pBitsPerPixelX16 > in->bits_per_pixel))
{
DSC_Print("ERROR - Invalid bits per pixel value specified.");
ret = NVT_STATUS_INVALID_PARAMETER;

7
src/common/modeset/timing/nvt_dsc_pps.h
View File

@@ -196,6 +196,13 @@ typedef struct
NvU32 maxBitsPerPixelX16;
}sinkCaps;
struct BRANCH_DSC_CAPS
{
NvU32 overallThroughputMode0;
NvU32 overallThroughputMode1;
NvU32 maxLineBufferWidth;
}branchCaps;
struct GPU_DSC_CAPS
{
// Mask of all color formats for which encoding supported by GPU

2
src/common/modeset/timing/nvt_edid.c
View File

@@ -2410,7 +2410,7 @@ NvU32 NvTiming_CalculateCommonEDIDCRC32(NvU8* pEDIDBuffer, NvU32 edidVersion)
CommonEDIDBuffer[0x7F] = 0;
CommonEDIDBuffer[0xFF] = 0;
// We also need to zero out any "EDID Other Monitor Descriptors" (http://en.wikipedia.org/wiki/Extended_display_identification_data)
// We also need to zero out any "EDID Other Monitor Descriptors" (https://en.wikipedia.org/wiki/Extended_display_identification_data)
for (edidBufferIndex = 54; edidBufferIndex <= 108; edidBufferIndex += 18)
{
if (CommonEDIDBuffer[edidBufferIndex] == 0 && CommonEDIDBuffer[edidBufferIndex+1] == 0)

6
src/common/nvswitch/kernel/inc/rom_nvswitch.h
View File

@@ -64,7 +64,7 @@
//
// AT24CM02 EEPROM
// http://ww1.microchip.com/downloads/en/DeviceDoc/Atmel-8828-SEEPROM-AT24CM02-Datasheet.pdf
// https://ww1.microchip.com/downloads/en/DeviceDoc/Atmel-8828-SEEPROM-AT24CM02-Datasheet.pdf
//
#define AT24CM02_INDEX_SIZE 18 // Addressing bits
@@ -72,7 +72,7 @@
//
// AT24C02C EEPROM
// http://ww1.microchip.com/downloads/en/DeviceDoc/Atmel-8700-SEEPROM-AT24C01C-02C-Datasheet.pdf
// https://ww1.microchip.com/downloads/en/DeviceDoc/Atmel-8700-SEEPROM-AT24C01C-02C-Datasheet.pdf
//
#define AT24C02C_INDEX_SIZE 8 // Addressing bits
@@ -80,7 +80,7 @@
//
// AT24C02D EEPROM
// http://ww1.microchip.com/downloads/en/devicedoc/atmel-8871f-seeprom-at24c01d-02d-datasheet.pdf
// https://ww1.microchip.com/downloads/en/devicedoc/atmel-8871f-seeprom-at24c01d-02d-datasheet.pdf
// 2kb EEPROM used on LR10 P4790 B00 platform
//

15
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080internal.h
View File

@@ -2208,4 +2208,19 @@ typedef struct NV2080_CTRL_INTERNAL_GET_PCIE_P2P_CAPS_PARAMS {
NvU8 p2pWriteCapsStatus;
} NV2080_CTRL_INTERNAL_GET_PCIE_P2P_CAPS_PARAMS;
/*!
* NV2080_CTRL_CMD_INTERNAL_BIF_SET_PCIE_RO
*
* Enable/disable PCIe Relaxed Ordering.
*
*/
#define NV2080_CTRL_CMD_INTERNAL_BIF_SET_PCIE_RO (0x20800ab9) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_BIF_SET_PCIE_RO_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_INTERNAL_BIF_SET_PCIE_RO_PARAMS_MESSAGE_ID (0xb9U)
typedef struct NV2080_CTRL_INTERNAL_BIF_SET_PCIE_RO_PARAMS {
// Enable/disable PCIe relaxed ordering
NvBool enableRo;
} NV2080_CTRL_INTERNAL_BIF_SET_PCIE_RO_PARAMS;
/* ctrl2080internal_h */

6
src/common/sdk/nvidia/inc/nverror.h
View File

@@ -99,7 +99,11 @@
#define GSP_RPC_TIMEOUT (119)
#define GSP_ERROR (120)
#define C2C_ERROR (121)
#define ROBUST_CHANNEL_LAST_ERROR (C2C_ERROR)
#define SPI_PMU_RPC_READ_FAIL (122)
#define SPI_PMU_RPC_WRITE_FAIL (123)
#define SPI_PMU_RPC_ERASE_FAIL (124)
#define INFOROM_FS_ERROR (125)
#define ROBUST_CHANNEL_LAST_ERROR (INFOROM_FS_ERROR)
// Indexed CE reference

2
src/common/sdk/nvidia/inc/nvfixedtypes.h
View File

@@ -306,7 +306,7 @@ typedef NvUFXP64 NvUFXP52_12;
* 2^(_EXPONENT - _EXPONENT_BIAS) *
* (1 + _MANTISSA / (1 << 23))
*/
// [1] : http://en.wikipedia.org/wiki/Single_precision_floating-point_format
// [1] : https://en.wikipedia.org/wiki/Single_precision_floating-point_format
#define NV_TYPES_SINGLE_SIGN 31:31
#define NV_TYPES_SINGLE_SIGN_POSITIVE 0x00000000
#define NV_TYPES_SINGLE_SIGN_NEGATIVE 0x00000001

2
src/common/unix/common/utils/nv_memory_tracker.c
View File

@@ -54,7 +54,7 @@ typedef union {
/*
* Unused. For alignment purposes only. Guarantee alignment to
* twice pointer size. That is the alignment guaranteed by glibc:
* http://www.gnu.org/software/libc/manual/html_node/Aligned-Memory-Blocks.html
* https://www.gnu.org/software/libc/manual/html_node/Aligned-Memory-Blocks.html
* which seems reasonable to match here.
*/
NvU8 align __attribute__((aligned(sizeof(void*) * 2)));

2
src/common/uproc/os/libos-v2.0.0/debug/lines.c
View File

@@ -56,7 +56,7 @@ static void libosDwarfBuildTables(libosDebugResolver *pThis);
static void dwarfBuildARangeTable(libosDebugResolver *pThis);
static void dwarfSetARangeTableLineUnit(libosDebugResolver *pThis, DwarfStream unit, NvU64 address);
// http://www.dwarfstd.org/doc/dwarf-2.0.0.pdf
// https://www.dwarfstd.org/doc/dwarf-2.0.0.pdf
// Debug Line information related structures
// (for branch history and call stacks)