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515.48.07

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This commit is contained in:
Andy Ritger
2022-05-27 16:40:24 -07:00
parent af26e1ea89
commit 965db98552
114 changed files with 18493 additions and 22785 deletions
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4
src/common/inc/displayport/displayport.h
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@@ -262,6 +262,10 @@ typedef struct DscCaps
unsigned dscPeakThroughputMode1;
unsigned dscMaxSliceWidth;
unsigned branchDSCOverallThroughputMode0;
unsigned branchDSCOverallThroughputMode1;
unsigned branchDSCMaximumLineBufferWidth;
BITS_PER_PIXEL_INCREMENT dscBitsPerPixelIncrement;
} DscCaps;

1
src/common/inc/displayport/dpcd.h
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@@ -1083,6 +1083,7 @@ number of Downstream ports will be limited to 32.
#define NV_DPCD_EDP_DISPLAY_CTL_COLOR_ENGINE_EN_DISABLED (0x00000000) /* RWXUV */
#define NV_DPCD_EDP_DISPLAY_CTL_OVERDRIVE_CTL 5:4 /* RWXUF */
#define NV_DPCD_EDP_DISPLAY_CTL_OVERDRIVE_CTL_AUTONOMOUS (0x00000000) /* RWXUV */
#define NV_DPCD_EDP_DISPLAY_CTL_OVERDRIVE_CTL_AUTONOMOUS_1 (0x00000001) /* RWXUV */
#define NV_DPCD_EDP_DISPLAY_CTL_OVERDRIVE_CTL_DISABLE (0x00000002) /* RWXUV */
#define NV_DPCD_EDP_DISPLAY_CTL_OVERDRIVE_CTL_ENABLE (0x00000003) /* RWXUV */
#define NV_DPCD_EDP_DISPLAY_CTL_VBLANK_BKLGHT_UPDATE_EN 7:7 /* RWXUF */

11
src/common/inc/displayport/dpcd20.h
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@@ -44,3 +44,14 @@
#define NV_DPCD20_PANEL_REPLAY_CONFIGURATION_ENABLE_PR_MODE 0:0
#define NV_DPCD20_PANEL_REPLAY_CONFIGURATION_ENABLE_PR_MODE_NO (0x00000000)
#define NV_DPCD20_PANEL_REPLAY_CONFIGURATION_ENABLE_PR_MODE_YES (0x00000001)
/// BRANCH SPECIFIC DSC CAPS
#define NV_DPCD20_BRANCH_DSC_OVERALL_THROUGHPUT_MODE_0 (0x000000A0)
#define NV_DPCD20_BRANCH_DSC_OVERALL_THROUGHPUT_MODE_0_VALUE 7:0
#define NV_DPCD20_BRANCH_DSC_OVERALL_THROUGHPUT_MODE_1 (0x000000A1)
#define NV_DPCD20_BRANCH_DSC_OVERALL_THROUGHPUT_MODE_1_VALUE 7:0
#define NV_DPCD20_BRANCH_DSC_MAXIMUM_LINE_BUFFER_WIDTH (0x000000A2)
#define NV_DPCD20_BRANCH_DSC_MAXIMUM_LINE_BUFFER_WIDTH_VALUE 7:0

21
src/common/inc/nvBldVer.h
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@@ -36,25 +36,26 @@
// and then checked back in. You cannot make changes to these sections without
// corresponding changes to the buildmeister script
#ifndef NV_BUILD_BRANCH
#define NV_BUILD_BRANCH r515_95
#define NV_BUILD_BRANCH r516_10
#endif
#ifndef NV_PUBLIC_BRANCH
#define NV_PUBLIC_BRANCH r515_95
#define NV_PUBLIC_BRANCH r516_10
#endif
#if defined(NV_LINUX) || defined(NV_BSD) || defined(NV_SUNOS)
#define NV_BUILD_BRANCH_VERSION "rel/gpu_drv/r515/r515_95-155"
#define NV_BUILD_CHANGELIST_NUM (31261195)
#define NV_BUILD_BRANCH_VERSION "rel/gpu_drv/r515/r516_10-205"
#define NV_BUILD_CHANGELIST_NUM (31396299)
#define NV_BUILD_TYPE "Official"
#define NV_BUILD_NAME "rel/gpu_drv/r515/r515_95-155"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (31261195)
#define NV_BUILD_NAME "rel/gpu_drv/r515/r516_10-205"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (31396299)
#else /* Windows builds */
#define NV_BUILD_BRANCH_VERSION "r515_95-3"
#define NV_BUILD_CHANGELIST_NUM (31249857)
#define NV_BUILD_BRANCH_VERSION "r516_10-10"
#define NV_BUILD_CHANGELIST_NUM (31385161)
#define NV_BUILD_TYPE "Official"
#define NV_BUILD_NAME "516.01"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (31249857)
#define NV_BUILD_NAME "516.26"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (31385161)
#define NV_BUILD_BRANCH_BASE_VERSION R515
#endif
// End buildmeister python edited section

2
src/common/inc/nvPNPVendorIds.h
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@@ -29,7 +29,7 @@
* type const char*.
*
* References:
* http://www.uefi.org/pnp_id_list
* https://uefi.org/pnp_id_list
*
*/

2
src/common/inc/nvSha1.h
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@@ -26,7 +26,7 @@
* byte array, using the Secure Hashing Algorithm 1 (SHA-1) as defined
* in FIPS PUB 180-1 published April 17, 1995:
*
* http://www.itl.nist.gov/fipspubs/fip180-1.htm
* https://www.itl.nist.gov/fipspubs/fip180-1.htm
*
* Some common test cases (see Appendices A and B of the above document):
*

2
src/common/inc/nvUnixVersion.h
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@@ -4,7 +4,7 @@
#if defined(NV_LINUX) || defined(NV_BSD) || defined(NV_SUNOS) || defined(NV_VMWARE) || defined(NV_QNX) || defined(NV_INTEGRITY) || \
(defined(RMCFG_FEATURE_PLATFORM_GSP) && RMCFG_FEATURE_PLATFORM_GSP == 1)
#define NV_VERSION_STRING "515.43.04"
#define NV_VERSION_STRING "515.48.07"
#else

4
src/common/inc/swref/published/ampere/ga100/dev_fuse.h
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@@ -130,4 +130,8 @@
#define NV_FUSE_OPT_FPF_GSP_UCODE16_VERSION 0x008241FC /* RW-4R */
#define NV_FUSE_OPT_FPF_GSP_UCODE16_VERSION_DATA 15:0 /* RWIVF */
#define NV_FUSE_STATUS_OPT_DISPLAY 0x00820C04 /* R-I4R */
#define NV_FUSE_STATUS_OPT_DISPLAY_DATA 0:0 /* R-IVF */
#define NV_FUSE_STATUS_OPT_DISPLAY_DATA_ENABLE 0x00000000 /* R---V */
#endif // __ga100_dev_fuse_h__

9
src/common/inc/swref/published/ampere/ga100/dev_nv_xve_addendum.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2021 NVIDIA CORPORATION & AFFILIATES
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -42,4 +42,11 @@
//
#define NV_XVE_PASSTHROUGH_EMULATED_CONFIG_ROOT_PORT_SPEED 3:0
//
// On some platforms it's beneficial to enable relaxed ordering after vetting
// it's safe to do so. To automate this process on virtualized platforms, allow
// RO to be requested through this emulated config space bit.
//
#define NV_XVE_PASSTHROUGH_EMULATED_CONFIG_RELAXED_ORDERING_ENABLE 4:4
#endif

7
src/common/inc/swref/published/ampere/ga102/dev_gc6_island.h
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@@ -29,8 +29,9 @@
#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_03(i) (0x00118214+(i)*4) /* RW-4A */
#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_05(i) (0x00118234+(i)*4) /* RW-4A */
#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_42 0x001183a4 /* RW-4R */
#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_03(i) (0x00118214+(i)*4) /* RW-4A */
#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_05(i) (0x00118234+(i)*4) /* RW-4A */
#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_42 0x001183a4 /* RW-4R */
#define NV_PGC6_BSI_SECURE_SCRATCH_14 0x001180f8 /* RW-4R */
#endif // __ga102_dev_gc6_island_h__

3
src/common/inc/swref/published/ampere/ga102/dev_gc6_island_addendum.h
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@@ -33,6 +33,9 @@
#define NV_USABLE_FB_SIZE_IN_MB NV_PGC6_AON_SECURE_SCRATCH_GROUP_42
#define NV_USABLE_FB_SIZE_IN_MB_VALUE 31:0
#define NV_USABLE_FB_SIZE_IN_MB_VALUE_INIT 0
#define NV_PGC6_BSI_SECURE_SCRATCH_14_BOOT_STAGE_3_HANDOFF 26:26
#define NV_PGC6_BSI_SECURE_SCRATCH_14_BOOT_STAGE_3_HANDOFF_VALUE_INIT 0x0
#define NV_PGC6_BSI_SECURE_SCRATCH_14_BOOT_STAGE_3_HANDOFF_VALUE_DONE 0x1
#endif // __ga102_dev_gc6_island_addendum_h__

31
src/common/inc/swref/published/maxwell/gm107/dev_fuse.h Normal file
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@@ -0,0 +1,31 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gm107_dev_fuse_h__
#define __gm107_dev_fuse_h__
#define NV_FUSE_STATUS_OPT_DISPLAY 0x00021C04 /* R-I4R */
#define NV_FUSE_STATUS_OPT_DISPLAY_DATA 0:0 /* R-IVF */
#define NV_FUSE_STATUS_OPT_DISPLAY_DATA_ENABLE 0x00000000 /* R---V */
#endif // __gm107_dev_fuse_h__

5
src/common/inc/swref/published/turing/tu102/dev_gc6_island.h
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@@ -29,7 +29,8 @@
#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_03(i) (0x00118214+(i)*4) /* RW-4A */
#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_05(i) (0x00118234+(i)*4) /* RW-4A */
#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_03(i) (0x00118214+(i)*4) /* RW-4A */
#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_05(i) (0x00118234+(i)*4) /* RW-4A */
#define NV_PGC6_BSI_SECURE_SCRATCH_14 0x001180f8 /* RW-4R */
#endif // __tu102_dev_gc6_island_h__

3
src/common/inc/swref/published/turing/tu102/dev_gc6_island_addendum.h
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@@ -30,6 +30,9 @@
#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_0_GFW_BOOT NV_PGC6_AON_SECURE_SCRATCH_GROUP_05(0)
#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_0_GFW_BOOT_PROGRESS 7:0
#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_0_GFW_BOOT_PROGRESS_COMPLETED 0x000000FF
#define NV_PGC6_BSI_SECURE_SCRATCH_14_BOOT_STAGE_3_HANDOFF 26:26
#define NV_PGC6_BSI_SECURE_SCRATCH_14_BOOT_STAGE_3_HANDOFF_VALUE_INIT 0x0
#define NV_PGC6_BSI_SECURE_SCRATCH_14_BOOT_STAGE_3_HANDOFF_VALUE_DONE 0x1
#endif // __tu102_dev_gc6_island_addendum_h__