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515.48.07

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This commit is contained in:
Andy Ritger
2022-05-27 16:40:24 -07:00
parent af26e1ea89
commit 965db98552
114 changed files with 18493 additions and 22785 deletions
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7
src/nvidia/arch/nvalloc/common/inc/flcnretval.h
View File

@@ -276,4 +276,11 @@ typedef NvU8 FLCN_STATUS;
// Lane Margining errors
#define FLCN_ERR_LM_INVALID_RECEIVER_NUMBER (0xF5U)
// APM errors
#define FLCN_ERR_APM_NOT_FUSED_FOR_EK (0xF6U)
#define FLCN_ERR_APM_BROM_SIGN_FAIL (0xF7U)
// Booter Reload on SEC2-RTOS errors
#define FLCN_ERR_AUTH_GSP_RM_HANDOFF_FAILED (0xF8U)
#define FLCN_ERR_INVALID_WPRMETA_MAGIC_OR_REVISION (0xF9U)
#endif // FLCNRETVAL_H

45
src/nvidia/arch/nvalloc/unix/include/nv-reg.h
View File

@@ -301,23 +301,6 @@
#define __NV_ENABLE_MSI EnableMSI
#define NV_REG_ENABLE_MSI NV_REG_STRING(__NV_ENABLE_MSI)
/*
* Option: RegisterForACPIEvents
*
* Description:
*
* When this option is enabled, the NVIDIA driver will register with the
* ACPI subsystem to receive notification of ACPI events.
*
* Possible values:
*
* 1 - register for ACPI events (default)
* 0 - do not register for ACPI events
*/
#define __NV_REGISTER_FOR_ACPI_EVENTS RegisterForACPIEvents
#define NV_REG_REGISTER_FOR_ACPI_EVENTS NV_REG_STRING(__NV_REGISTER_FOR_ACPI_EVENTS)
/*
* Option: EnablePCIeGen3
*
@@ -817,6 +800,30 @@
#define NV_REG_OPENRM_ENABLE_UNSUPPORTED_GPUS_ENABLE 0x00000001
#define NV_REG_OPENRM_ENABLE_UNSUPPORTED_GPUS_DEFAULT NV_REG_OPENRM_ENABLE_UNSUPPORTED_GPUS_DISABLE
/*
* Option: NVreg_DmaRemapPeerMmio
*
* Description:
*
* When this option is enabled, the NVIDIA driver will use device driver
* APIs provided by the Linux kernel for DMA-remapping part of a device's
* MMIO region to another device, creating e.g., IOMMU mappings as necessary.
* When this option is disabled, the NVIDIA driver will instead only apply a
* fixed offset, which may be zero, to CPU physical addresses to produce the
* DMA address for the peer's MMIO region, and no IOMMU mappings will be
* created.
*
* This option only affects peer MMIO DMA mappings, and not system memory
* mappings.
*
* Possible Values:
* 0 = disable dynamic DMA remapping of peer MMIO regions
* 1 = enable dynamic DMA remapping of peer MMIO regions (default)
*/
#define __NV_DMA_REMAP_PEER_MMIO DmaRemapPeerMmio
#define NV_DMA_REMAP_PEER_MMIO NV_REG_STRING(__NV_DMA_REMAP_PEER_MMIO)
#define NV_DMA_REMAP_PEER_MMIO_DISABLE 0x00000000
#define NV_DMA_REMAP_PEER_MMIO_ENABLE 0x00000001
#if defined(NV_DEFINE_REGISTRY_KEY_TABLE)
@@ -832,7 +839,6 @@ NV_DEFINE_REG_ENTRY(__NV_DEVICE_FILE_GID, 0);
NV_DEFINE_REG_ENTRY(__NV_DEVICE_FILE_MODE, 0666);
NV_DEFINE_REG_ENTRY(__NV_INITIALIZE_SYSTEM_MEMORY_ALLOCATIONS, 1);
NV_DEFINE_REG_ENTRY(__NV_USE_PAGE_ATTRIBUTE_TABLE, ~0);
NV_DEFINE_REG_ENTRY(__NV_REGISTER_FOR_ACPI_EVENTS, 1);
NV_DEFINE_REG_ENTRY(__NV_ENABLE_PCIE_GEN3, 0);
NV_DEFINE_REG_ENTRY(__NV_ENABLE_MSI, 1);
NV_DEFINE_REG_ENTRY(__NV_TCE_BYPASS_MODE, NV_TCE_BYPASS_MODE_DEFAULT);
@@ -863,6 +869,7 @@ NV_DEFINE_REG_STRING_ENTRY(__NV_RM_MSG, NULL);
NV_DEFINE_REG_STRING_ENTRY(__NV_GPU_BLACKLIST, NULL);
NV_DEFINE_REG_STRING_ENTRY(__NV_TEMPORARY_FILE_PATH, NULL);
NV_DEFINE_REG_STRING_ENTRY(__NV_EXCLUDED_GPUS, NULL);
NV_DEFINE_REG_ENTRY(__NV_DMA_REMAP_PEER_MMIO, NV_DMA_REMAP_PEER_MMIO_ENABLE);
/*
*----------------registry database definition----------------------
@@ -885,7 +892,6 @@ nv_parm_t nv_parms[] = {
NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_INITIALIZE_SYSTEM_MEMORY_ALLOCATIONS),
NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_USE_PAGE_ATTRIBUTE_TABLE),
NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_ENABLE_MSI),
NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_REGISTER_FOR_ACPI_EVENTS),
NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_ENABLE_PCIE_GEN3),
NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_MEMORY_POOL_SIZE),
NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_KMALLOC_HEAP_MAX_SIZE),
@@ -908,6 +914,7 @@ nv_parm_t nv_parms[] = {
NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_ENABLE_GPU_FIRMWARE_LOGS),
NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_ENABLE_DBG_BREAKPOINT),
NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_OPENRM_ENABLE_UNSUPPORTED_GPUS),
NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_DMA_REMAP_PEER_MMIO),
{NULL, NULL}
};

14
src/nvidia/arch/nvalloc/unix/include/nv.h
View File

@@ -571,11 +571,9 @@ typedef enum
((nv)->iso_iommu_present)
/*
* NVIDIA ACPI event IDs to be passed into the core NVIDIA
* driver for various events like display switch events,
* AC/battery events, etc..
* NVIDIA ACPI event ID to be passed into the core NVIDIA driver for
* AC/DC event.
*/
#define NV_SYSTEM_ACPI_DISPLAY_SWITCH_EVENT 0x8001
#define NV_SYSTEM_ACPI_BATTERY_POWER_EVENT 0x8002
/*
@@ -584,14 +582,6 @@ typedef enum
#define NV_SYSTEM_GPU_ADD_EVENT 0x9001
#define NV_SYSTEM_GPU_REMOVE_EVENT 0x9002
/*
* Status bit definitions for display switch hotkey events.
*/
#define NV_HOTKEY_STATUS_DISPLAY_ENABLE_LCD 0x01
#define NV_HOTKEY_STATUS_DISPLAY_ENABLE_CRT 0x02
#define NV_HOTKEY_STATUS_DISPLAY_ENABLE_TV 0x04
#define NV_HOTKEY_STATUS_DISPLAY_ENABLE_DFP 0x08
/*
* NVIDIA ACPI sub-event IDs (event types) to be passed into
* to core NVIDIA driver for ACPI events.

60
src/nvidia/arch/nvalloc/unix/src/osapi.c
View File

@@ -1112,10 +1112,6 @@ NV_STATUS RmSystemEvent(
switch (event_type)
{
case NV_SYSTEM_ACPI_DISPLAY_SWITCH_EVENT:
// Legacy kepler case, do nothing.
break;
case NV_SYSTEM_ACPI_BATTERY_POWER_EVENT:
{
Nv2080PowerEventNotification powerParams;
@@ -3052,6 +3048,38 @@ NV_STATUS rm_update_device_mapping_info(
return RmStatus;
}
static void rm_is_device_rm_firmware_capable(
nv_state_t *pNv,
NvU32 pmcBoot42,
NvBool *pbIsFirmwareCapable,
NvBool *pbEnableByDefault
)
{
NvBool bIsFirmwareCapable = NV_FALSE;
NvBool bEnableByDefault = NV_FALSE;
NvU16 pciDeviceId = pNv->pci_info.device_id;
if (NV_IS_SOC_DISPLAY_DEVICE(pNv))
{
bIsFirmwareCapable = NV_TRUE;
}
else
{
bIsFirmwareCapable = gpumgrIsDeviceRmFirmwareCapable(pciDeviceId,
pmcBoot42,
&bEnableByDefault);
}
if (pbIsFirmwareCapable != NULL)
{
*pbIsFirmwareCapable = bIsFirmwareCapable;
}
if (pbEnableByDefault != NULL)
{
*pbEnableByDefault = bEnableByDefault;
}
}
static NvBool NV_API_CALL rm_is_legacy_device(
NvU16 device_id,
NvU16 subsystem_vendor,
@@ -3138,7 +3166,31 @@ NV_STATUS NV_API_CALL rm_is_supported_device(
rmStatus = halmgrGetHalForGpu(pHalMgr, pmc_boot_0, pmc_boot_42, &myHalPublicID);
if (rmStatus != NV_OK)
{
NvBool bIsFirmwareCapable;
rm_is_device_rm_firmware_capable(pNv,
pmc_boot_42,
&bIsFirmwareCapable,
NULL);
if (!bIsFirmwareCapable)
{
nv_printf(NV_DBG_ERRORS,
"NVRM: The NVIDIA GPU %04x:%02x:%02x.%x (PCI ID: %04x:%04x)\n"
"NVRM: installed in this system is not supported by open\n"
"NVRM: nvidia.ko because it does not include the required GPU\n"
"NVRM: System Processor (GSP).\n"
"NVRM: Please see the 'Open Linux Kernel Modules' and 'GSP\n"
"NVRM: Firmware' sections in the driver README, available on\n"
"NVRM: the Linux graphics driver download page at\n"
"NVRM: www.nvidia.com.\n",
pNv->pci_info.domain, pNv->pci_info.bus, pNv->pci_info.slot,
pNv->pci_info.function, pNv->pci_info.vendor_id,
pNv->pci_info.device_id, NV_VERSION_STRING);
goto threadfree;
}
goto print_unsupported;
}
goto threadfree;