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This commit is contained in:
Andy Ritger
2022-08-02 08:35:13 -07:00
parent 1e2a1b5fbe
commit 9855350159
35 changed files with 382 additions and 263 deletions
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3
src/nvidia/arch/nvalloc/common/inc/nvcst.h
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@@ -63,6 +63,7 @@ CHIPSET_SETUP_FUNC(Intel_A301_setupFunc)
CHIPSET_SETUP_FUNC(Intel_0685_setupFunc)
CHIPSET_SETUP_FUNC(Intel_4381_setupFunc)
CHIPSET_SETUP_FUNC(Intel_7A82_setupFunc)
CHIPSET_SETUP_FUNC(Intel_7A04_setupFunc)
CHIPSET_SETUP_FUNC(SiS_656_setupFunc)
CHIPSET_SETUP_FUNC(ATI_RS400_setupFunc)
CHIPSET_SETUP_FUNC(ATI_RS480_setupFunc)
@@ -182,6 +183,8 @@ CSINFO chipsetInfo[] =
{PCI_VENDOR_ID_INTEL, 0x7A82, CS_INTEL_7A82, "Intel-AlderLake", Intel_7A82_setupFunc},
{PCI_VENDOR_ID_INTEL, 0x7A84, CS_INTEL_7A82, "Intel-AlderLake", Intel_7A82_setupFunc},
{PCI_VENDOR_ID_INTEL, 0x1B81, CS_INTEL_1B81, "Intel-SapphireRapids", NULL},
{PCI_VENDOR_ID_INTEL, 0x18DC, CS_INTEL_18DC, "Intel-IceLake", NULL},
{PCI_VENDOR_ID_INTEL, 0x7A04, CS_INTEL_7A04, "Intel-RaptorLake", Intel_7A04_setupFunc},
{PCI_VENDOR_ID_NVIDIA, 0x0FAE, CS_NVIDIA_T210, "T210", Nvidia_T210_setupFunc},
{PCI_VENDOR_ID_NVIDIA, 0x0FAF, CS_NVIDIA_T210, "T210", Nvidia_T210_setupFunc},

2
src/nvidia/arch/nvalloc/common/inc/nvdevid.h
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@@ -642,6 +642,8 @@ enum {
, CS_PHYTIUM_S2500
, CS_MELLANOX_BLUEFIELD2
, CS_INTEL_1B81
, CS_INTEL_18DC
, CS_INTEL_7A04
, CS_MAX_PCIE
};

1
src/nvidia/arch/nvalloc/unix/include/nv.h
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@@ -943,6 +943,7 @@ NvBool NV_API_CALL rm_disable_iomap_wc(void);
void NV_API_CALL rm_init_dynamic_power_management(nvidia_stack_t *, nv_state_t *, NvBool);
void NV_API_CALL rm_cleanup_dynamic_power_management(nvidia_stack_t *, nv_state_t *);
void NV_API_CALL rm_enable_dynamic_power_management(nvidia_stack_t *, nv_state_t *);
NV_STATUS NV_API_CALL rm_ref_dynamic_power(nvidia_stack_t *, nv_state_t *, nv_dynamic_power_mode_t);
void NV_API_CALL rm_unref_dynamic_power(nvidia_stack_t *, nv_state_t *, nv_dynamic_power_mode_t);
NV_STATUS NV_API_CALL rm_transition_dynamic_power(nvidia_stack_t *, nv_state_t *, NvBool);

7
src/nvidia/arch/nvalloc/unix/src/exports-stubs.c
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@@ -50,6 +50,13 @@ void NV_API_CALL rm_cleanup_dynamic_power_management(
{
}
void NV_API_CALL rm_enable_dynamic_power_management(
nvidia_stack_t *sp,
nv_state_t *nv
)
{
}
NV_STATUS NV_API_CALL rm_ref_dynamic_power(
nvidia_stack_t *sp,
nv_state_t *nv,

1
src/nvidia/exports_link_command.txt
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@@ -178,6 +178,7 @@
--undefined=rm_schedule_gpu_wakeup
--undefined=rm_init_dynamic_power_management
--undefined=rm_cleanup_dynamic_power_management
--undefined=rm_enable_dynamic_power_management
--undefined=rm_ref_dynamic_power
--undefined=rm_unref_dynamic_power
--undefined=rm_transition_dynamic_power

2
src/nvidia/generated/g_nv_name_released.h
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@@ -868,6 +868,8 @@ static const CHIPS_RELEASED sChipsReleased[] = {
{ 0x2233, 0x165a, 0x10de, "NVIDIA RTX A5500" },
{ 0x2233, 0x165a, 0x17aa, "NVIDIA RTX A5500" },
{ 0x2235, 0x145a, 0x10de, "NVIDIA A40" },
{ 0x2236, 0x1482, 0x10de, "NVIDIA A10" },
{ 0x2237, 0x152f, 0x10de, "NVIDIA A10G" },
{ 0x2238, 0x1677, 0x10de, "NVIDIA A10M" },
{ 0x2414, 0x0000, 0x0000, "NVIDIA GeForce RTX 3060 Ti" },
{ 0x2420, 0x0000, 0x0000, "NVIDIA GeForce RTX 3080 Ti Laptop GPU" },

1
src/nvidia/generated/g_rs_resource_nvoc.h
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@@ -491,6 +491,7 @@ struct RS_CPU_UNMAP_PARAMS
NvP64 pLinearAddress; ///< [in] Address of mapped memory
NvU32 flags; ///< [in] Resource-specific flags
NvU32 processId;
NvBool bTeardown; ///< [in] Unmap operation is due to client teardown
/// [in] hContext Handle of resource that provides a context for the mapping (e.g., subdevice for channel map)
NvHandle hContext;

1
src/nvidia/inc/libraries/resserv/rs_resource.h
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@@ -465,6 +465,7 @@ struct RS_CPU_UNMAP_PARAMS
NvP64 pLinearAddress; ///< [in] Address of mapped memory
NvU32 flags; ///< [in] Resource-specific flags
NvU32 processId;
NvBool bTeardown; ///< [in] Unmap operation is due to client teardown
/// [in] hContext Handle of resource that provides a context for the mapping (e.g., subdevice for channel map)
NvHandle hContext;

2
src/nvidia/src/kernel/gpu/disp/disp_sf_user.c
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@@ -56,6 +56,8 @@ dispsfConstruct_IMPL
return NV_ERR_INSUFFICIENT_PERMISSIONS;
}
NV_CHECK_OR_RETURN(LEVEL_ERROR, pKernelDisplay != NULL, NV_ERR_NOT_SUPPORTED);
// Set sf user RegBase offset
kdispGetDisplaySfUserBaseAndSize_HAL(pGpu, pKernelDisplay,
&pDispSfUser->ControlOffset,

1
src/nvidia/src/kernel/mem_mgr/gpu_vaspace.c
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@@ -3713,6 +3713,7 @@ gvaspaceWalkUserCtxRelease_IMPL
{
// If current context doesn't match, must have nested acquires (not allowed).
NV_ASSERT_OR_RETURN_VOID(pUserCtx->pGpuState);
NV_ASSERT_OR_RETURN_VOID(pUserCtx->pGpuState->pWalk);
NV_ASSERT(pUserCtx == mmuWalkGetUserCtx(pUserCtx->pGpuState->pWalk));
mmuWalkSetUserCtx(pUserCtx->pGpuState->pWalk, NULL);
}

12
src/nvidia/src/kernel/platform/chipset/chipset_info.c
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@@ -880,6 +880,18 @@ Intel_7A82_setupFunc
return NV_OK;
}
// Intel Z790 platform (Raptor Lake)
static NV_STATUS
Intel_7A04_setupFunc
(
OBJCL *pCl
)
{
pCl->setProperty(pCl, PDB_PROP_CL_HAS_RESIZABLE_BAR_ISSUE, NV_TRUE);
return NV_OK;
}
static NV_STATUS
Nvidia_T210_setupFunc
(

15
src/nvidia/src/kernel/rmapi/mapping_cpu.c
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@@ -974,11 +974,24 @@ serverUnmap_Prologue
{
rmStatus = osAttachToProcess(&pProcessHandle, ProcessId);
if (rmStatus != NV_OK)
return rmStatus;
{
if (pUnmapParams->bTeardown)
pProcessHandle = NULL;
else
return rmStatus;
}
pUnmapParams->pProcessHandle = pProcessHandle;
}
// Don't do any filtering if this is a tear-down path
if (pUnmapParams->bTeardown)
{
pUnmapParams->fnFilter = NULL;
return NV_OK;
}
pUnmapParams->fnFilter = bKernel
? serverutilMappingFilterKernel
: serverutilMappingFilterCurrentUserProc;

5
src/nvidia/src/libraries/mmu/mmu_walk.c
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@@ -205,7 +205,10 @@ mmuWalkLevelInstancesForceFree
MMU_WALK *pWalk
)
{
_mmuWalkLevelInstancesForceFree(pWalk, &pWalk->root);
if (pWalk != NULL)
{
_mmuWalkLevelInstancesForceFree(pWalk, &pWalk->root);
}
}
/*----------------------------Private Functions--------------------------------*/

2
src/nvidia/src/libraries/mmu/mmu_walk_reserve.c
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@@ -110,6 +110,8 @@ mmuWalkReleaseEntries
MMU_WALK_OP_PARAMS opParams = {0};
NV_STATUS status = NV_OK;
NV_ASSERT_OR_RETURN(NULL != pWalk, NV_ERR_INVALID_ARGUMENT);
NV_ASSERT_OR_RETURN(NULL != mmuWalkFindLevel(pWalk, pLevelFmt),
NV_ERR_INVALID_ARGUMENT);
NV_ASSERT_OR_RETURN(NV_IS_ALIGNED(vaLo, mmuFmtLevelPageSize(pLevelFmt)),

4
src/nvidia/src/libraries/resserv/src/rs_client.c
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@@ -1084,7 +1084,8 @@ _clientUnmapResourceRefMappings
: pCpuMapping->pContextRef->hResource;
params.hMemory = pResourceRef->hResource;
params.pLinearAddress = pCpuMapping->pLinearAddress;
params.processId = pCpuMapping->processId;
params.processId = pCpuMapping->processId;
params.bTeardown = NV_TRUE;
params.flags = pCpuMapping->flags;
params.pSecInfo = &pCallContext->secInfo;
params.pLockInfo = &lockInfo;
@@ -1147,6 +1148,7 @@ _clientUnmapBackRefMappings
params.hMemory = pBackRef->hResource;
params.pLinearAddress = pCpuMapping->pLinearAddress;
params.processId = pCpuMapping->processId;
params.bTeardown = NV_TRUE;
params.flags = pCpuMapping->flags;
params.pSecInfo = &pCallContext->secInfo;
params.pLockInfo = &lockInfo;