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535.261.03

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This commit is contained in:
Bernhard Stoeckner
2025-07-17 17:13:07 +02:00
parent f468568958
commit 9c67f19366
37 changed files with 425 additions and 177 deletions
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20
src/common/inc/nvBldVer.h
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@@ -36,25 +36,25 @@
// and then checked back in. You cannot make changes to these sections without
// corresponding changes to the buildmeister script
#ifndef NV_BUILD_BRANCH
#define NV_BUILD_BRANCH r539_28
#define NV_BUILD_BRANCH r539_41
#endif
#ifndef NV_PUBLIC_BRANCH
#define NV_PUBLIC_BRANCH r539_28
#define NV_PUBLIC_BRANCH r539_41
#endif
#if defined(NV_LINUX) || defined(NV_BSD) || defined(NV_SUNOS)
#define NV_BUILD_BRANCH_VERSION "rel/gpu_drv/r535/r539_28-859"
#define NV_BUILD_CHANGELIST_NUM (35750789)
#define NV_BUILD_BRANCH_VERSION "rel/gpu_drv/r535/r539_41-927"
#define NV_BUILD_CHANGELIST_NUM (36124219)
#define NV_BUILD_TYPE "Official"
#define NV_BUILD_NAME "rel/gpu_drv/r535/r539_28-859"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (35750789)
#define NV_BUILD_NAME "rel/gpu_drv/r535/r539_41-927"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (36124219)
#else /* Windows builds */
#define NV_BUILD_BRANCH_VERSION "r539_28-1"
#define NV_BUILD_CHANGELIST_NUM (35750715)
#define NV_BUILD_BRANCH_VERSION "r539_41-1"
#define NV_BUILD_CHANGELIST_NUM (36117060)
#define NV_BUILD_TYPE "Official"
#define NV_BUILD_NAME "539.29"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (35750715)
#define NV_BUILD_NAME "539.42"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (36117060)
#define NV_BUILD_BRANCH_BASE_VERSION R535
#endif
// End buildmeister python edited section

2
src/common/inc/nvUnixVersion.h
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@@ -4,7 +4,7 @@
#if defined(NV_LINUX) || defined(NV_BSD) || defined(NV_SUNOS) || defined(NV_VMWARE) || defined(NV_QNX) || defined(NV_INTEGRITY) || \
(defined(RMCFG_FEATURE_PLATFORM_GSP) && RMCFG_FEATURE_PLATFORM_GSP == 1)
#define NV_VERSION_STRING "535.247.01"
#define NV_VERSION_STRING "535.261.03"
#else

1
src/common/nvswitch/kernel/ls10/minion_ls10.c
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@@ -934,7 +934,6 @@ cleanup:
if (tempStatus != NVL_SUCCESS)
{
NVSWITCH_PRINT(device, ERROR, "Link %d Inband Buffer transfer for RX_BUFFER_CLEAR\n", linkId);
return;
}
if (device->link[linkId].inbandData.message != NULL)
{

5
src/nvidia/arch/nvalloc/common/inc/nvcst.h
View File

@@ -65,7 +65,6 @@ CHIPSET_SETUP_FUNC(Intel_0685_setupFunc)
CHIPSET_SETUP_FUNC(Intel_4381_setupFunc)
CHIPSET_SETUP_FUNC(Intel_7A82_setupFunc)
CHIPSET_SETUP_FUNC(Intel_7A04_setupFunc)
CHIPSET_SETUP_FUNC(Intel_1B81_setupFunc)
CHIPSET_SETUP_FUNC(SiS_656_setupFunc)
CHIPSET_SETUP_FUNC(ATI_RS400_setupFunc)
CHIPSET_SETUP_FUNC(ATI_RS480_setupFunc)
@@ -187,8 +186,8 @@ CSINFO chipsetInfo[] =
{PCI_VENDOR_ID_INTEL, 0x4385, CS_INTEL_4381, "Intel-RocketLake", Intel_4381_setupFunc},
{PCI_VENDOR_ID_INTEL, 0x7A82, CS_INTEL_7A82, "Intel-AlderLake", Intel_7A82_setupFunc},
{PCI_VENDOR_ID_INTEL, 0x7A84, CS_INTEL_7A82, "Intel-AlderLake", Intel_7A82_setupFunc},
{PCI_VENDOR_ID_INTEL, 0x1B81, CS_INTEL_1B81, "Intel-SapphireRapids", Intel_1B81_setupFunc},
{PCI_VENDOR_ID_INTEL, 0x7A8A, CS_INTEL_1B81, "Intel-SapphireRapids", Intel_1B81_setupFunc},
{PCI_VENDOR_ID_INTEL, 0x1B81, CS_INTEL_1B81, "Intel-SapphireRapids", NULL},
{PCI_VENDOR_ID_INTEL, 0x7A8A, CS_INTEL_1B81, "Intel-SapphireRapids", NULL},
{PCI_VENDOR_ID_INTEL, 0x18DC, CS_INTEL_18DC, "Intel-IceLake", NULL},
{PCI_VENDOR_ID_INTEL, 0x7A04, CS_INTEL_7A04, "Intel-RaptorLake", Intel_7A04_setupFunc},
{PCI_VENDOR_ID_INTEL, 0x5795, CS_INTEL_5795, "Intel-GraniteRapids", NULL},

14
src/nvidia/arch/nvalloc/common/inc/nvpcie.h
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@@ -224,6 +224,20 @@
#define NV_PCI_VIRTUAL_P2P_APPROVAL_SIGNATURE 0x00503250
#define NV_PCI_VIRTUAL_CONFIG_BITS_CAP_0 0x000000D4
#define NV_PCI_VIRTUAL_CONFIG_BITS_CAP_0_ID 7:0
#define NV_PCI_VIRTUAL_CONFIG_BITS_CAP_0_NEXT 15:8
#define NV_PCI_VIRTUAL_CONFIG_BITS_CAP_0_LENGTH 23:16
#define NV_PCI_VIRTUAL_CONFIG_BITS_CAP_0_SIG_LO 31:24
#define NV_PCI_VIRTUAL_CONFIG_BITS_CAP_1 0x000000D8
#define NV_PCI_VIRTUAL_CONFIG_BITS_CAP_1_SIG_HI 15:0
#define NV_PCI_VIRTUAL_CONFIG_BITS_CAP_1_VALUE 31:16
#define NV_PCI_VIRTUAL_CONFIG_BITS_SIGNATURE 0x00535442 //"BTS"
// Allocation of _VALUE bits
#define NV_PCI_VIRTUAL_CONFIG_BITS_PCI_EGRESS_POISON_ENABLE 0:0
// Chipset-specific definitions.
// Intel SantaRosa definitions
#define INTEL_2A00_CONFIG_SPACE_BASE 0x60

30
src/nvidia/arch/nvalloc/common/inc/oob/smbpbi_priv.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2010-2017 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2010-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -47,33 +47,13 @@
#define NV_MSGBOX_CMD_ERR_MORE_PROCESSING_REQUIRED 0x000000F0
//
// Alternative encodings of the command word
// These are distinguished by a non-zero value in the 29:29 bit,
// previously known as _RSVD.
// Alternative encodings of the command word.
// These were distinguished by a non-zero value in the 29:29 bit.
// Bit 29 is now reserved and must be 0 i.e. only standard requests will be processed
// and debug requests would fail.
//
#define NV_MSGBOX_CMD_ENCODING 29:29
#define NV_MSGBOX_CMD_ENCODING_STANDARD 0x00000000
#define NV_MSGBOX_CMD_ENCODING_DEBUG 0x00000001
// Debug command structure
#define NV_MSGBOX_DEBUG_CMD_OPCODE 1:0
#define NV_MSGBOX_DEBUG_CMD_OPCODE_READ_PRIV 0x00000000
#define NV_MSGBOX_DEBUG_CMD_ARG 23:2
/* Utility command constructor macros */
#define NV_MSGBOX_DEBUG_CMD(opcode, arg) \
( \
DRF_DEF(_MSGBOX, _DEBUG_CMD, _OPCODE, opcode) | \
DRF_NUM(_MSGBOX, _DEBUG_CMD, _ARG, (arg)) | \
DRF_DEF(_MSGBOX, _CMD, _STATUS, _NULL) | \
DRF_DEF(_MSGBOX, _CMD, _ENCODING, _DEBUG) | \
DRF_DEF(_MSGBOX, _CMD, _INTR, _PENDING) \
)
#define NV_MSGBOX_DEBUG_CMD_READ_PRIV(offset) \
NV_MSGBOX_DEBUG_CMD(_READ_PRIV, (offset) >> 2)
#endif // _SMBPBI_PRIV_H_

8
src/nvidia/generated/g_gpu_access_nvoc.h
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@@ -216,6 +216,14 @@ void regCheckAndLogReadFailure(RegisterAccess *, NvU32 addr, NvU32 mask, NvU32 v
// Get the address of a register given the Aperture and offset.
#define REG_GET_ADDR(ap, offset) ioaprtGetRegAddr(ap, offset)
//
// These UNCHECKED macros are provided for extenuating circumstances to avoid the 0xbadf
// sanity checking done by the usual register read utilities and must not be used generally
//
//
#define GPU_REG_RD08_UNCHECKED(g,a) osDevReadReg008(g, gpuGetDeviceMapping(g, DEVICE_INDEX_GPU, 0), a)
#define GPU_REG_RD32_UNCHECKED(g,a) osDevReadReg032(g, gpuGetDeviceMapping(g, DEVICE_INDEX_GPU, 0), a)
// GPU macros defined in terms of DEV_ macros
#define GPU_REG_RD08(g,a) REG_INST_RD08(g,GPU,0,a)
#define GPU_REG_RD16(g,a) REG_INST_RD16(g,GPU,0,a)

3
src/nvidia/generated/g_gpu_nvoc.h
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@@ -7,7 +7,7 @@ extern "C" {
#endif
/*
* SPDX-FileCopyrightText: Copyright (c) 2004-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2004-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -1016,6 +1016,7 @@ struct OBJGPU {
NvBool gpuLinkTerminationEnabled;
NvBool gspRmInitialized;
_GPU_PCIE_PEER_CLIQUE pciePeerClique;
NvU16 virtualConfigBits;
NvU32 i2cPortForExtdev;
GPUIDINFO idInfo;
_GPU_CHIP_INFO chipInfo;

1
src/nvidia/generated/rmconfig.h
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@@ -294,6 +294,7 @@
#define RMCFG_FEATURE_FEATURE_GH180 1 // RMconfig to encapsulate GH180 features
#define RMCFG_FEATURE_MULTICAST_FABRIC 1 // Support for MULTICAST_FABRIC
#define RMCFG_FEATURE_NVLINK_ERROR_THRESHOLD 1 // Support for NVLINK_ERROR_THRESHOLD
#define RMCFG_FEATURE_TPC_REPAIR 1 // Support for TPC swapping in-field
#define RMCFG_FEATURE_FABRIC_LINEAR_ADDRESSING 1 // Unicast fabric memory management

1
src/nvidia/inc/kernel/gpu/gsp/gsp_static_config.h
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@@ -174,6 +174,7 @@ typedef struct GspSystemInfo
BUSINFO chipsetIDInfo;
ACPI_METHOD_DATA acpiMethodData;
NvU32 hypervisorType;
NvU16 virtualConfigBits;
NvBool bIsPassthru;
NvU64 sysTimerOffsetNs;
GSP_VF_INFO gspVFInfo;

7
src/nvidia/kernel/vgpu/nv/rpc.c
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2008-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2008-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -1337,6 +1337,7 @@ NV_STATUS rpcGspSetSystemInfo_v17_00
rpcInfo->upstreamAddressValid = pGpu->gpuClData.upstreamPort.addr.valid;
rpcInfo->hypervisorType = hypervisorGetHypervisorType(pHypervisor);
rpcInfo->virtualConfigBits = pGpu->virtualConfigBits;
rpcInfo->bIsPassthru = pGpu->bIsPassthru;
// Fill in VF related GPU flags
@@ -1457,6 +1458,8 @@ NV_STATUS rpcDumpProtobufComponent_v18_12
if (IS_GSP_CLIENT(pGpu))
{
rpc_dump_protobuf_component_v18_12 *rpc_params = &rpc_message->dump_protobuf_component_v18_12;
const NvU32 fixed_param_size = sizeof(rpc_message_header_v) + sizeof(*rpc_params);
NV_ASSERT_OR_RETURN(fixed_param_size <= pRpc->maxRpcSize, NV_ERR_INVALID_STATE);
status = rpcWriteCommonHeader(pGpu, pRpc, NV_VGPU_MSG_FUNCTION_DUMP_PROTOBUF_COMPONENT,
sizeof(*rpc_params));
@@ -1468,7 +1471,7 @@ NV_STATUS rpcDumpProtobufComponent_v18_12
rpc_params->countOnly = ((pPrbEnc->flags & PRB_COUNT_ONLY) != 0);
rpc_params->bugCheckCode = pNvDumpState->bugCheckCode;
rpc_params->internalCode = pNvDumpState->internalCode;
rpc_params->bufferSize = NV_MIN(pRpc->maxRpcSize, prbEncBufLeft(pPrbEnc));
rpc_params->bufferSize = NV_MIN(pRpc->maxRpcSize - fixed_param_size, prbEncBufLeft(pPrbEnc));
status = _issueRpcAndWait(pGpu, pRpc);

5
src/nvidia/src/kernel/gpu/arch/hopper/kern_gpu_gh100.c
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2021-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -22,6 +22,7 @@
*/
#include "gpu/gpu.h"
#include "gpu/gpu_access.h"
#include "gpu/gpu_child_class_defs.h"
#include "os/os.h"
#include "nverror.h"
@@ -95,7 +96,7 @@ gpuReadVgpuConfigReg_GH100
NvU32 *pData
)
{
*pData = GPU_REG_RD32(pGpu, DEVICE_BASE(NV_EP_PCFGM) + index);
*pData = GPU_REG_RD32_UNCHECKED(pGpu, DEVICE_BASE(NV_EP_PCFGM) + index);
return NV_OK;
}

63
src/nvidia/src/kernel/gpu/fsp/kern_fsp.c
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2021-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -229,8 +229,30 @@ kfspIsQueueEmpty_IMPL
return (cmdqHead == cmdqTail);
}
/*
* @brief GpuWaitConditionFunc for MBOX receiver ready
*
* @param[in] pGpu GPU object pointer
* @param[in] pCondData KernelFsp object pointer
*
* @returns NvBool NV_TRUE if command and message fsp
* queues are empty
*/
static NvBool
_kfspWaitForQueuesEmpty
(
OBJGPU *pGpu,
void *pCondData
)
{
KernelFsp *pKernelFsp = (KernelFsp*) pCondData;
return kfspIsQueueEmpty(pGpu, pKernelFsp) &&
kfspIsMsgQueueEmpty(pGpu, pKernelFsp);
}
/*!
* @brief Wait for FSP RM command queue to be empty
* @brief Wait for FSP RM queues to be empty
*
* @param[in] pGpu OBJGPU pointer
* @param[in] pKernelFsp KernelFsp pointer
@@ -251,40 +273,11 @@ kfspPollForQueueEmpty_IMPL
GPU_TIMEOUT_FLAGS_OSTIMER |
GPU_TIMEOUT_FLAGS_BYPASS_THREAD_STATE);
while (!kfspIsQueueEmpty(pGpu, pKernelFsp))
status = gpuTimeoutCondWait(pGpu, _kfspWaitForQueuesEmpty, pKernelFsp, &timeout);
if (status != NV_OK)
{
//
// For now we assume that any response from FSP before RM message
// send is complete indicates an error and we should abort.
//
// Ongoing dicussion on usefullness of this check. Bug to be filed.
//
if (!kfspIsMsgQueueEmpty(pGpu, pKernelFsp))
{
kfspReadMessage(pGpu, pKernelFsp, NULL, 0);
NV_PRINTF(LEVEL_ERROR,
"Received error message from FSP while waiting for CMDQ to be empty.\n");
status = NV_ERR_GENERIC;
break;
}
osSpinLoop();
status = gpuCheckTimeout(pGpu, &timeout);
if (status != NV_OK)
{
if ((status == NV_ERR_TIMEOUT) &&
kfspIsQueueEmpty(pGpu, pKernelFsp))
{
status = NV_OK;
}
else
{
NV_PRINTF(LEVEL_ERROR,
"Timed out waiting for FSP command queue to be empty.\n");
}
break;
}
NV_PRINTF(LEVEL_ERROR,
"Timed out waiting for FSP queues to be empty.\n");
}
return status;

2
src/nvidia/src/kernel/gpu/mig_mgr/gpu_instance_subscription.c
View File

@@ -421,7 +421,7 @@ gisubscriptionCtrlCmdExecPartitionsCreate_IMPL
.inst.request.requestFlags = pParams->flags
};
if (!hypervisorIsVgxHyper())
if (!gpuIsSriovEnabled(pGpu))
{
request.inst.request.requestFlags = FLD_SET_DRF(C637_CTRL, _DMA_EXEC_PARTITIONS_CREATE_REQUEST, _WITH_PART_ID, _FALSE, request.inst.request.requestFlags);
}

13
src/nvidia/src/kernel/platform/chipset/chipset_info.c
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2004-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2004-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -903,17 +903,6 @@ Intel_7A04_setupFunc
return NV_OK;
}
static NV_STATUS
Intel_1B81_setupFunc
(
OBJCL *pCl
)
{
pCl->setProperty(pCl, PDB_PROP_CL_RELAXED_ORDERING_NOT_CAPABLE, NV_TRUE);
return NV_OK;
}
static NV_STATUS
Nvidia_T210_setupFunc
(

55
src/nvidia/src/kernel/platform/chipset/chipset_pcie.c
View File

@@ -73,6 +73,7 @@ static void objClGpuMapEnhCfgSpace(OBJGPU *, OBJCL *);
static void objClGpuUnmapEnhCfgSpace(OBJGPU *);
static NV_STATUS objClGpuIs3DController(OBJGPU *);
static void objClLoadPcieVirtualP2PApproval(OBJGPU *);
static void objClLoadPcieVirtualConfigBits(OBJGPU *);
static void objClCheckForExternalGpu(OBJGPU *, OBJCL *);
static void _objClAdjustTcVcMap(OBJGPU *, OBJCL *, PORTDATA *);
static void _objClGetDownstreamAtomicsEnabledMask(void *, NvU32, NvU32 *);
@@ -953,6 +954,9 @@ clUpdatePcieConfig_IMPL(OBJGPU *pGpu, OBJCL *pCl)
// Load PCI Express virtual P2P approval config
objClLoadPcieVirtualP2PApproval(pGpu);
// Load additional configuraiton bits from virtualized cfg space
objClLoadPcieVirtualConfigBits(pGpu);
//
// Disable NOSNOOP bit for Passthrough.
//
@@ -4329,6 +4333,57 @@ objClLoadPcieVirtualP2PApproval(OBJGPU *pGpu)
gpuGetInstance(pGpu), pGpu->pciePeerClique.id);
}
static void
objClLoadPcieVirtualConfigBits(OBJGPU *pGpu)
{
void *handle;
NvU32 data32;
NvU8 cap;
NvU8 bus = gpuGetBus(pGpu);
NvU8 device = gpuGetDevice(pGpu);
NvU32 domain = gpuGetDomain(pGpu);
NvU32 offset = 0;
NvU32 sig = 0;
if (!IS_PASSTHRU(pGpu))
{
NV_PRINTF(LEVEL_INFO,
"Skipping non-pass-through GPU%u\n", gpuGetInstance(pGpu));
return;
}
handle = osPciInitHandle(domain, bus, device, 0, NULL, NULL);
//
// Walk the list and find enable bits
//
cap = osPciReadByte(handle, PCI_CAPABILITY_LIST);
while ((cap != 0) && (sig != NV_PCI_VIRTUAL_CONFIG_BITS_SIGNATURE))
{
offset = cap;
data32 = osPciReadDword(handle, offset);
cap = (NvU8)((data32 >> 8) & 0xFF);
if ((data32 & CAP_ID_MASK) != CAP_ID_VENDOR_SPECIFIC)
continue;
sig = DRF_VAL(_PCI, _VIRTUAL_CONFIG_BITS_CAP_0, _SIG_LO, data32);
data32 = osPciReadDword(handle, offset + 4);
sig |= (DRF_VAL(_PCI, _VIRTUAL_CONFIG_BITS_CAP_1, _SIG_HI, data32) << 8);
}
if (sig == NV_PCI_VIRTUAL_CONFIG_BITS_SIGNATURE)
{
// data32 now contains the second dword of the capability structure.
pGpu->virtualConfigBits =
(NvU16) DRF_VAL(_PCI, _VIRTUAL_CONFIG_BITS_CAP_1, _VALUE, data32);
NV_PRINTF(LEVEL_INFO,
"Hypervisor has specified config bits %u for GPU%u\n",
pGpu->virtualConfigBits, gpuGetInstance(pGpu));
}
}
/*!
* @brief Traverse bus topology till Gpu's root port.
* If any of the intermediate bridge has TB3 supported vendorId and hotplug