565.77

src/nvidia/generated/g_all_dcl_pb.c

@@ -122,6 +122,18 @@ const PRB_FIELD_DESC prb_fields_dcl_dclmsg[] = {
         PRB_MAYBE_FIELD_NAME("engine")
         PRB_MAYBE_FIELD_DEFAULT(0)
     },
+    {
+        331,
+        {
+            PRB_OPTIONAL,
+            PRB_MESSAGE,
+            0,
+        },
+        RC_RCDIAGRECORD,
+        0,
+        PRB_MAYBE_FIELD_NAME("rc_diag_recs")
+        PRB_MAYBE_FIELD_DEFAULT(0)
+    },
 };
 
 // 'ErrorBlock' field defaults
@@ -150,7 +162,7 @@ const PRB_MSG_DESC prb_messages_dcl[] = {
         PRB_MAYBE_MESSAGE_NAME("Dcl.Engines")
     },
     {
-        7,
+        8,
         prb_fields_dcl_dclmsg,
         PRB_MAYBE_MESSAGE_NAME("Dcl.DclMsg")
     },

src/nvidia/generated/g_all_dcl_pb.h

@@ -18,8 +18,8 @@ extern const PRB_MSG_DESC prb_messages_dcl[];
 // Message maximum lengths
 // Does not include repeated fields, strings and byte arrays.
 #define DCL_ENGINES_LEN 136
-#define DCL_DCLMSG_LEN 573
-#define DCL_ERRORBLOCK_LEN 577
+#define DCL_DCLMSG_LEN 616
+#define DCL_ERRORBLOCK_LEN 620
 
 extern const PRB_FIELD_DESC prb_fields_dcl_engines[];
 
@@ -41,6 +41,7 @@ extern const PRB_FIELD_DESC prb_fields_dcl_dclmsg[];
 #define DCL_DCLMSG_JOURNAL_BUGCHECK (&prb_fields_dcl_dclmsg[4])
 #define DCL_DCLMSG_RCCOUNTER (&prb_fields_dcl_dclmsg[5])
 #define DCL_DCLMSG_ENGINE (&prb_fields_dcl_dclmsg[6])
+#define DCL_DCLMSG_RC_DIAG_RECS (&prb_fields_dcl_dclmsg[7])
 
 // 'DclMsg' field lengths
 #define DCL_DCLMSG_COMMON_LEN 42
@@ -50,6 +51,7 @@ extern const PRB_FIELD_DESC prb_fields_dcl_dclmsg[];
 #define DCL_DCLMSG_JOURNAL_BUGCHECK_LEN 69
 #define DCL_DCLMSG_RCCOUNTER_LEN 64
 #define DCL_DCLMSG_ENGINE_LEN 139
+#define DCL_DCLMSG_RC_DIAG_RECS_LEN 42
 
 extern const PRB_FIELD_DESC prb_fields_dcl_errorblock[];
 
@@ -57,7 +59,7 @@ extern const PRB_FIELD_DESC prb_fields_dcl_errorblock[];
 #define DCL_ERRORBLOCK_DATA (&prb_fields_dcl_errorblock[0])
 
 // 'ErrorBlock' field lengths
-#define DCL_ERRORBLOCK_DATA_LEN 576
+#define DCL_ERRORBLOCK_DATA_LEN 619
 
 extern const PRB_SERVICE_DESC prb_services_dcl[];
 

src/nvidia/generated/g_intr_nvoc.h

@@ -157,6 +157,11 @@ interruptEntryIsEmpty(const InterruptEntry *pEntry)
 // Default value for intrStuckThreshold
 #define INTR_STUCK_THRESHOLD 1000
 
+// Minimum length of interrupt to log as long-running
+#define LONG_INTR_LOG_LENGTH_NS (1000000LLU) // 1ms
+// Maximum frequency of long-running interrupt print, per engine
+#define LONG_INTR_LOG_RATELIMIT_NS (10000000000LLU) // 10s
+
 #define INTR_TABLE_INIT_KERNEL (1 << 0)
 #define INTR_TABLE_INIT_PHYSICAL (1 << 1)
 
@@ -274,6 +279,13 @@ typedef struct Device Device;
 // Metadata including vtable
 struct NVOC_VTABLE__Intr;
 
+struct __nvoc_inner_struc_Intr_1__ {
+    NvU32 intrCount;
+    NvU64 intrLength;
+    NvU64 lastPrintTime;
+};
+
+
 
 struct Intr {
 
@@ -347,6 +359,7 @@ struct Intr {
     NvU32 intrEn0Orig;
     NvBool halIntrEnabled;
     NvU32 saveIntrEn0;
+    struct __nvoc_inner_struc_Intr_1__ longIntrStats[175];
 };
 
 

src/nvidia/generated/g_kernel_gsp_nvoc.h

@@ -455,7 +455,7 @@ struct KernelGsp {
     NvBool bHasVgpuLogs;
     void *pLogElf;
     NvU64 logElfDataSize;
-    PORT_MUTEX *pNvlogFlushMtx;
+    volatile NvS32 logDumpLock;
     NvBool bLibosLogsPollingEnabled;
     NvU8 bootAttempts;
     NvBool bInInit;

src/nvidia/generated/g_kernel_hostvgpudeviceapi_nvoc.h

@@ -170,7 +170,7 @@ struct KernelHostVgpuDeviceApi {
 
     // Data members
     struct KernelHostVgpuDeviceShr *pShared;
-    NvU32 notifyActions[7];
+    NvU32 notifyActions[8];
 };
 
 

src/nvidia/generated/g_nv_name_released.h

@@ -5220,6 +5220,8 @@ static const CHIPS_RELEASED sChipsReleased[] = {
     { 0x2324, 0x17a8, 0x10de, "NVIDIA H800" },
     { 0x2329, 0x198b, 0x10de, "NVIDIA H20" },
     { 0x2329, 0x198c, 0x10de, "NVIDIA H20" },
+    { 0x232C, 0x2063, 0x10de, "NVIDIA H20-3e" },
+    { 0x232C, 0x2064, 0x10de, "NVIDIA H20-3e" },
     { 0x2330, 0x16c0, 0x10de, "NVIDIA H100 80GB HBM3" },
     { 0x2330, 0x16c1, 0x10de, "NVIDIA H100 80GB HBM3" },
     { 0x2331, 0x1626, 0x10de, "NVIDIA H100 PCIe" },
@@ -5302,10 +5304,12 @@ static const CHIPS_RELEASED sChipsReleased[] = {
     { 0x25AD, 0x0000, 0x0000, "NVIDIA GeForce RTX 2050" },
     { 0x25B0, 0x1878, 0x1028, "NVIDIA RTX A1000" },
     { 0x25B0, 0x1878, 0x103c, "NVIDIA RTX A1000" },
+    { 0x25B0, 0x8d96, 0x103c, "NVIDIA RTX A1000" },
     { 0x25B0, 0x1878, 0x10de, "NVIDIA RTX A1000" },
     { 0x25B0, 0x1878, 0x17aa, "NVIDIA RTX A1000" },
     { 0x25B2, 0x1879, 0x1028, "NVIDIA RTX A400" },
     { 0x25B2, 0x1879, 0x103c, "NVIDIA RTX A400" },
+    { 0x25B2, 0x8d95, 0x103c, "NVIDIA RTX A400" },
     { 0x25B2, 0x1879, 0x10de, "NVIDIA RTX A400" },
     { 0x25B2, 0x1879, 0x17aa, "NVIDIA RTX A400" },
     { 0x25B6, 0x14a9, 0x10de, "NVIDIA A16" },

src/nvidia/generated/g_nvdebug_pb.h

@@ -43,7 +43,7 @@ extern const PRB_MSG_DESC prb_messages_nvdebug[];
 // Does not include repeated fields, strings and byte arrays.
 #define NVDEBUG_SYSTEMINFO_LEN 354
 #define NVDEBUG_GPUINFO_LEN 262
-#define NVDEBUG_NVDUMP_LEN 1570
+#define NVDEBUG_NVDUMP_LEN 1613
 #define NVDEBUG_SYSTEMINFO_NORTHBRIDGEINFO_LEN 12
 #define NVDEBUG_SYSTEMINFO_SOCINFO_LEN 12
 #define NVDEBUG_SYSTEMINFO_CPUINFO_LEN 24
@@ -114,7 +114,7 @@ extern const PRB_FIELD_DESC prb_fields_nvdebug_nvdump[];
 
 // 'NvDump' field lengths
 #define NVDEBUG_NVDUMP_SYSTEM_INFO_LEN 357
-#define NVDEBUG_NVDUMP_DCL_MSG_LEN 576
+#define NVDEBUG_NVDUMP_DCL_MSG_LEN 619
 #define NVDEBUG_NVDUMP_GPU_INFO_LEN 265
 #define NVDEBUG_NVDUMP_EXCEPTION_ADDRESS_LEN 10
 #define NVDEBUG_NVDUMP_SYSTEM_INFO_GSPRM_LEN 357

src/nvidia/generated/g_nvencsession_nvoc.c

@@ -23,10 +23,10 @@ extern const struct NVOC_CLASS_DEF __nvoc_class_def_RmResource;
 
 extern const struct NVOC_CLASS_DEF __nvoc_class_def_GpuResource;
 
-void __nvoc_init_NvencSession(NvencSession*, RmHalspecOwner* );
-void __nvoc_init_funcTable_NvencSession(NvencSession*, RmHalspecOwner* );
-NV_STATUS __nvoc_ctor_NvencSession(NvencSession*, RmHalspecOwner* , struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams);
-void __nvoc_init_dataField_NvencSession(NvencSession*, RmHalspecOwner* );
+void __nvoc_init_NvencSession(NvencSession*);
+void __nvoc_init_funcTable_NvencSession(NvencSession*);
+NV_STATUS __nvoc_ctor_NvencSession(NvencSession*, struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams);
+void __nvoc_init_dataField_NvencSession(NvencSession*);
 void __nvoc_dtor_NvencSession(NvencSession*);
 extern const struct NVOC_EXPORT_INFO __nvoc_export_info_NvencSession;
 
@@ -103,7 +103,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_NvencSes
 #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x8u)
         /*pFunc=*/      (void (*)(void)) NULL,
 #else
-        /*pFunc=*/      (void (*)(void)) nvencsessionCtrlCmdNvencSwSessionUpdateInfo_DISPATCH,
+        /*pFunc=*/      (void (*)(void)) nvencsessionCtrlCmdNvencSwSessionUpdateInfo_IMPL,
 #endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x8u)
         /*flags=*/      0x8u,
         /*accessRight=*/0x0u,
@@ -118,7 +118,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_NvencSes
 #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x8u)
         /*pFunc=*/      (void (*)(void)) NULL,
 #else
-        /*pFunc=*/      (void (*)(void)) nvencsessionCtrlCmdNvencSwSessionUpdateInfoV2_DISPATCH,
+        /*pFunc=*/      (void (*)(void)) nvencsessionCtrlCmdNvencSwSessionUpdateInfoV2_IMPL,
 #endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x8u)
         /*flags=*/      0x8u,
         /*accessRight=*/0x0u,
@@ -341,21 +341,16 @@ void __nvoc_dtor_NvencSession(NvencSession *pThis) {
     PORT_UNREFERENCED_VARIABLE(pThis);
 }
 
-void __nvoc_init_dataField_NvencSession(NvencSession *pThis, RmHalspecOwner *pRmhalspecowner) {
-    RmVariantHal *rmVariantHal = &pRmhalspecowner->rmVariantHal;
-    const unsigned long rmVariantHal_HalVarIdx = (unsigned long)rmVariantHal->__nvoc_HalVarIdx;
+void __nvoc_init_dataField_NvencSession(NvencSession *pThis) {
     PORT_UNREFERENCED_VARIABLE(pThis);
-    PORT_UNREFERENCED_VARIABLE(pRmhalspecowner);
-    PORT_UNREFERENCED_VARIABLE(rmVariantHal);
-    PORT_UNREFERENCED_VARIABLE(rmVariantHal_HalVarIdx);
 }
 
 NV_STATUS __nvoc_ctor_GpuResource(GpuResource* , struct CALL_CONTEXT *, struct RS_RES_ALLOC_PARAMS_INTERNAL *);
-NV_STATUS __nvoc_ctor_NvencSession(NvencSession *pThis, RmHalspecOwner *pRmhalspecowner, struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) {
+NV_STATUS __nvoc_ctor_NvencSession(NvencSession *pThis, struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) {
     NV_STATUS status = NV_OK;
     status = __nvoc_ctor_GpuResource(&pThis->__nvoc_base_GpuResource, arg_pCallContext, arg_pParams);
     if (status != NV_OK) goto __nvoc_ctor_NvencSession_fail_GpuResource;
-    __nvoc_init_dataField_NvencSession(pThis, pRmhalspecowner);
+    __nvoc_init_dataField_NvencSession(pThis);
 
     status = __nvoc_nvencsessionConstruct(pThis, arg_pCallContext, arg_pParams);
     if (status != NV_OK) goto __nvoc_ctor_NvencSession_fail__init;
@@ -370,41 +365,30 @@ __nvoc_ctor_NvencSession_exit:
 }
 
 // Vtable initialization
-static void __nvoc_init_funcTable_NvencSession_1(NvencSession *pThis, RmHalspecOwner *pRmhalspecowner) {
-    RmVariantHal *rmVariantHal = &pRmhalspecowner->rmVariantHal;
-    const unsigned long rmVariantHal_HalVarIdx = (unsigned long)rmVariantHal->__nvoc_HalVarIdx;
+static void __nvoc_init_funcTable_NvencSession_1(NvencSession *pThis) {
     PORT_UNREFERENCED_VARIABLE(pThis);
-    PORT_UNREFERENCED_VARIABLE(pRmhalspecowner);
-    PORT_UNREFERENCED_VARIABLE(rmVariantHal);
-    PORT_UNREFERENCED_VARIABLE(rmVariantHal_HalVarIdx);
 
-    // nvencsessionCtrlCmdNvencSwSessionUpdateInfo -- halified (2 hals) exported (id=0xa0bc0101) body
-    if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ 
-    {
-        pThis->__nvencsessionCtrlCmdNvencSwSessionUpdateInfo__ = &nvencsessionCtrlCmdNvencSwSessionUpdateInfo_46f6a7;
-    }
-    else
-    {
-        pThis->__nvencsessionCtrlCmdNvencSwSessionUpdateInfo__ = &nvencsessionCtrlCmdNvencSwSessionUpdateInfo_IMPL;
-    }
+    // nvencsessionCtrlCmdNvencSwSessionUpdateInfo -- exported (id=0xa0bc0101)
+#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x8u)
+    pThis->__nvencsessionCtrlCmdNvencSwSessionUpdateInfo__ = &nvencsessionCtrlCmdNvencSwSessionUpdateInfo_IMPL;
+#endif
 
-    // nvencsessionCtrlCmdNvencSwSessionUpdateInfoV2 -- halified (2 hals) exported (id=0xa0bc0102) body
-    if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ 
-    {
-        pThis->__nvencsessionCtrlCmdNvencSwSessionUpdateInfoV2__ = &nvencsessionCtrlCmdNvencSwSessionUpdateInfoV2_46f6a7;
-    }
-    else
-    {
-        pThis->__nvencsessionCtrlCmdNvencSwSessionUpdateInfoV2__ = &nvencsessionCtrlCmdNvencSwSessionUpdateInfoV2_IMPL;
-    }
-} // End __nvoc_init_funcTable_NvencSession_1 with approximately 4 basic block(s).
+    // nvencsessionCtrlCmdNvencSwSessionUpdateInfoV2 -- exported (id=0xa0bc0102)
+#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x8u)
+    pThis->__nvencsessionCtrlCmdNvencSwSessionUpdateInfoV2__ = &nvencsessionCtrlCmdNvencSwSessionUpdateInfoV2_IMPL;
+#endif
+} // End __nvoc_init_funcTable_NvencSession_1 with approximately 2 basic block(s).
 
 
 // Initialize vtable(s) for 27 virtual method(s).
-void __nvoc_init_funcTable_NvencSession(NvencSession *pThis, RmHalspecOwner *pRmhalspecowner) {
+void __nvoc_init_funcTable_NvencSession(NvencSession *pThis) {
 
     // Per-class vtable definition
     static const struct NVOC_VTABLE__NvencSession vtable = {
+#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x8u)
+#endif
+#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x8u)
+#endif
         .__nvencsessionControl__ = &__nvoc_up_thunk_GpuResource_nvencsessionControl,    // virtual inherited (gpures) base (gpures)
         .GpuResource.__gpuresControl__ = &gpuresControl_IMPL,    // virtual override (res) base (rmres)
         .GpuResource.RmResource.__rmresControl__ = &__nvoc_up_thunk_RsResource_rmresControl,    // virtual inherited (res) base (res)
@@ -503,11 +487,11 @@ void __nvoc_init_funcTable_NvencSession(NvencSession *pThis, RmHalspecOwner *pRm
     pThis->__nvoc_vtable = &vtable;    // (nvencsession) this
 
     // Initialize vtable(s) with 2 per-object function pointer(s).
-    __nvoc_init_funcTable_NvencSession_1(pThis, pRmhalspecowner);
+    __nvoc_init_funcTable_NvencSession_1(pThis);
 }
 
 void __nvoc_init_GpuResource(GpuResource*);
-void __nvoc_init_NvencSession(NvencSession *pThis, RmHalspecOwner *pRmhalspecowner) {
+void __nvoc_init_NvencSession(NvencSession *pThis) {
     pThis->__nvoc_pbase_NvencSession = pThis;
     pThis->__nvoc_pbase_Object = &pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object;
     pThis->__nvoc_pbase_RsResource = &pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource;
@@ -515,7 +499,7 @@ void __nvoc_init_NvencSession(NvencSession *pThis, RmHalspecOwner *pRmhalspecown
     pThis->__nvoc_pbase_RmResource = &pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource;
     pThis->__nvoc_pbase_GpuResource = &pThis->__nvoc_base_GpuResource;
     __nvoc_init_GpuResource(&pThis->__nvoc_base_GpuResource);
-    __nvoc_init_funcTable_NvencSession(pThis, pRmhalspecowner);
+    __nvoc_init_funcTable_NvencSession(pThis);
 }
 
 NV_STATUS __nvoc_objCreate_NvencSession(NvencSession **ppThis, Dynamic *pParent, NvU32 createFlags, struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams)
@@ -523,7 +507,6 @@ NV_STATUS __nvoc_objCreate_NvencSession(NvencSession **ppThis, Dynamic *pParent,
     NV_STATUS status;
     Object *pParentObj = NULL;
     NvencSession *pThis;
-    RmHalspecOwner *pRmhalspecowner;
 
     // Assign `pThis`, allocating memory unless suppressed by flag.
     status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(NvencSession), (void**)&pThis, (void**)ppThis);
@@ -538,11 +521,8 @@ NV_STATUS __nvoc_objCreate_NvencSession(NvencSession **ppThis, Dynamic *pParent,
 
     pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags;
 
-    // pParent must be a valid object that derives from a halspec owner class.
-    NV_ASSERT_OR_RETURN(pParent != NULL, NV_ERR_INVALID_ARGUMENT);
-
-    // Link the child into the parent unless flagged not to do so.
-    if (!(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY))
+    // Link the child into the parent if there is one unless flagged not to do so.
+    if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY))
     {
         pParentObj = dynamicCast(pParent, Object);
         objAddChild(pParentObj, &pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object);
@@ -552,12 +532,8 @@ NV_STATUS __nvoc_objCreate_NvencSession(NvencSession **ppThis, Dynamic *pParent,
         pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.pParent = NULL;
     }
 
-    if ((pRmhalspecowner = dynamicCast(pParent, RmHalspecOwner)) == NULL)
-        pRmhalspecowner = objFindAncestorOfType(RmHalspecOwner, pParent);
-    NV_ASSERT_OR_RETURN(pRmhalspecowner != NULL, NV_ERR_INVALID_ARGUMENT);
-
-    __nvoc_init_NvencSession(pThis, pRmhalspecowner);
-    status = __nvoc_ctor_NvencSession(pThis, pRmhalspecowner, arg_pCallContext, arg_pParams);
+    __nvoc_init_NvencSession(pThis);
+    status = __nvoc_ctor_NvencSession(pThis, arg_pCallContext, arg_pParams);
     if (status != NV_OK) goto __nvoc_objCreate_NvencSession_cleanup;
 
     // Assignment has no effect if NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT is set.

src/nvidia/generated/g_nvencsession_nvoc.h

@@ -45,6 +45,7 @@ extern "C" {
 #include "core/core.h"
 #include "rmapi/client.h"
 #include "gpu/gpu_halspec.h"
+#include "gpu/gpu_halspec.h"
 #include "gpu/gpu_resource.h"
 #include "class/cla0bc.h"
 #include "ctrl/ctrla0bc.h"
@@ -117,8 +118,8 @@ struct NvencSession {
     struct NvencSession *__nvoc_pbase_NvencSession;    // nvencsession
 
     // Vtable with 2 per-object function pointers
-    NV_STATUS (*__nvencsessionCtrlCmdNvencSwSessionUpdateInfo__)(struct NvencSession * /*this*/, NVA0BC_CTRL_NVENC_SW_SESSION_UPDATE_INFO_PARAMS *);  // halified (2 hals) exported (id=0xa0bc0101) body
-    NV_STATUS (*__nvencsessionCtrlCmdNvencSwSessionUpdateInfoV2__)(struct NvencSession * /*this*/, NVA0BC_CTRL_NVENC_SW_SESSION_UPDATE_INFO_V2_PARAMS *);  // halified (2 hals) exported (id=0xa0bc0102) body
+    NV_STATUS (*__nvencsessionCtrlCmdNvencSwSessionUpdateInfo__)(struct NvencSession * /*this*/, NVA0BC_CTRL_NVENC_SW_SESSION_UPDATE_INFO_PARAMS *);  // exported (id=0xa0bc0101)
+    NV_STATUS (*__nvencsessionCtrlCmdNvencSwSessionUpdateInfoV2__)(struct NvencSession * /*this*/, NVA0BC_CTRL_NVENC_SW_SESSION_UPDATE_INFO_V2_PARAMS *);  // exported (id=0xa0bc0102)
 
     // Data members
     NvHandle handle;
@@ -196,10 +197,8 @@ NV_STATUS __nvoc_objCreate_NvencSession(NvencSession**, Dynamic*, NvU32, struct
 // Wrapper macros
 #define nvencsessionCtrlCmdNvencSwSessionUpdateInfo_FNPTR(pNvencSession) pNvencSession->__nvencsessionCtrlCmdNvencSwSessionUpdateInfo__
 #define nvencsessionCtrlCmdNvencSwSessionUpdateInfo(pNvencSession, pParams) nvencsessionCtrlCmdNvencSwSessionUpdateInfo_DISPATCH(pNvencSession, pParams)
-#define nvencsessionCtrlCmdNvencSwSessionUpdateInfo_HAL(pNvencSession, pParams) nvencsessionCtrlCmdNvencSwSessionUpdateInfo_DISPATCH(pNvencSession, pParams)
 #define nvencsessionCtrlCmdNvencSwSessionUpdateInfoV2_FNPTR(pNvencSession) pNvencSession->__nvencsessionCtrlCmdNvencSwSessionUpdateInfoV2__
 #define nvencsessionCtrlCmdNvencSwSessionUpdateInfoV2(pNvencSession, pParams) nvencsessionCtrlCmdNvencSwSessionUpdateInfoV2_DISPATCH(pNvencSession, pParams)
-#define nvencsessionCtrlCmdNvencSwSessionUpdateInfoV2_HAL(pNvencSession, pParams) nvencsessionCtrlCmdNvencSwSessionUpdateInfoV2_DISPATCH(pNvencSession, pParams)
 #define nvencsessionControl_FNPTR(pGpuResource) pGpuResource->__nvoc_base_GpuResource.__nvoc_vtable->__gpuresControl__
 #define nvencsessionControl(pGpuResource, pCallContext, pParams) nvencsessionControl_DISPATCH(pGpuResource, pCallContext, pParams)
 #define nvencsessionMap_FNPTR(pGpuResource) pGpuResource->__nvoc_base_GpuResource.__nvoc_vtable->__gpuresMap__
@@ -360,16 +359,8 @@ static inline void nvencsessionAddAdditionalDependants_DISPATCH(struct RsClient
     pResource->__nvoc_vtable->__nvencsessionAddAdditionalDependants__(pClient, pResource, pReference);
 }
 
-static inline NV_STATUS nvencsessionCtrlCmdNvencSwSessionUpdateInfo_46f6a7(struct NvencSession *pNvencSession, NVA0BC_CTRL_NVENC_SW_SESSION_UPDATE_INFO_PARAMS *pParams) {
-    return NV_ERR_NOT_SUPPORTED;
-}
-
 NV_STATUS nvencsessionCtrlCmdNvencSwSessionUpdateInfo_IMPL(struct NvencSession *pNvencSession, NVA0BC_CTRL_NVENC_SW_SESSION_UPDATE_INFO_PARAMS *pParams);
 
-static inline NV_STATUS nvencsessionCtrlCmdNvencSwSessionUpdateInfoV2_46f6a7(struct NvencSession *pNvencSession, NVA0BC_CTRL_NVENC_SW_SESSION_UPDATE_INFO_V2_PARAMS *pParams) {
-    return NV_ERR_NOT_SUPPORTED;
-}
-
 NV_STATUS nvencsessionCtrlCmdNvencSwSessionUpdateInfoV2_IMPL(struct NvencSession *pNvencSession, NVA0BC_CTRL_NVENC_SW_SESSION_UPDATE_INFO_V2_PARAMS *pParams);
 
 NV_STATUS nvencsessionConstruct_IMPL(struct NvencSession *arg_pNvencSession, struct CALL_CONTEXT *arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *arg_pParams);

src/nvidia/generated/g_objtmr_nvoc.c

@@ -351,26 +351,6 @@ static void __nvoc_init_funcTable_OBJTMR_1(OBJTMR *pThis, RmHalspecOwner *pRmhal
         }
     }
 
-    // tmrGetTimeLo -- halified (2 hals) body
-    if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ 
-    {
-        pThis->__tmrGetTimeLo__ = &tmrGetTimeLo_GM107;
-    }
-    else
-    {
-        pThis->__tmrGetTimeLo__ = &tmrGetTimeLo_cf0499;
-    }
-
-    // tmrGetTime -- halified (2 hals) body
-    if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ 
-    {
-        pThis->__tmrGetTime__ = &tmrGetTime_GM107;
-    }
-    else
-    {
-        pThis->__tmrGetTime__ = &tmrGetTime_fa6bbe;
-    }
-
     // tmrGetTimeEx -- halified (2 hals) body
     if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0xd0000000UL) )) /* ChipHal: GH100 | GB100 | GB102 */ 
     {
@@ -420,10 +400,10 @@ static void __nvoc_init_funcTable_OBJTMR_1(OBJTMR *pThis, RmHalspecOwner *pRmhal
     {
         pThis->__tmrGetGpuPtimerOffset__ = &tmrGetGpuPtimerOffset_GA100;
     }
-} // End __nvoc_init_funcTable_OBJTMR_1 with approximately 22 basic block(s).
+} // End __nvoc_init_funcTable_OBJTMR_1 with approximately 18 basic block(s).
 
 
-// Initialize vtable(s) for 27 virtual method(s).
+// Initialize vtable(s) for 25 virtual method(s).
 void __nvoc_init_funcTable_OBJTMR(OBJTMR *pThis, RmHalspecOwner *pRmhalspecowner) {
 
     // Per-class vtable definition
@@ -470,7 +450,7 @@ void __nvoc_init_funcTable_OBJTMR(OBJTMR *pThis, RmHalspecOwner *pRmhalspecowner
     pThis->__nvoc_base_IntrService.__nvoc_vtable = &vtable.IntrService;    // (intrserv) super
     pThis->__nvoc_vtable = &vtable;    // (tmr) this
 
-    // Initialize vtable(s) with 10 per-object function pointer(s).
+    // Initialize vtable(s) with 8 per-object function pointer(s).
     __nvoc_init_funcTable_OBJTMR_1(pThis, pRmhalspecowner);
 }
 

src/nvidia/generated/g_objtmr_nvoc.h

@@ -218,12 +218,10 @@ struct OBJTMR {
     struct IntrService *__nvoc_pbase_IntrService;    // intrserv super
     struct OBJTMR *__nvoc_pbase_OBJTMR;    // tmr
 
-    // Vtable with 10 per-object function pointers
+    // Vtable with 8 per-object function pointers
     NV_STATUS (*__tmrDelay__)(struct OBJTMR * /*this*/, NvU32);  // halified (2 hals)
     NvU32 (*__tmrServiceInterrupt__)(OBJGPU *, struct OBJTMR * /*this*/, IntrServiceServiceInterruptArguments *);  // virtual halified (3 hals) override (intrserv) base (intrserv) body
     NV_STATUS (*__tmrSetCurrentTime__)(OBJGPU *, struct OBJTMR * /*this*/);  // halified (3 hals) body
-    NvU32 (*__tmrGetTimeLo__)(OBJGPU *, struct OBJTMR * /*this*/);  // halified (2 hals) body
-    NvU64 (*__tmrGetTime__)(OBJGPU *, struct OBJTMR * /*this*/);  // halified (2 hals) body
     NvU64 (*__tmrGetTimeEx__)(OBJGPU *, struct OBJTMR * /*this*/, struct THREAD_STATE_NODE *);  // halified (2 hals) body
     NV_STATUS (*__tmrSetCountdownIntrDisable__)(OBJGPU *, struct OBJTMR * /*this*/);  // halified (2 hals) body
     NV_STATUS (*__tmrSetCountdown__)(OBJGPU *, struct OBJTMR * /*this*/, NvU32, NvU32, struct THREAD_STATE_NODE *);  // halified (2 hals) body
@@ -359,12 +357,6 @@ NV_STATUS __nvoc_objCreate_OBJTMR(OBJTMR**, Dynamic*, NvU32);
 #define tmrSetCurrentTime_FNPTR(pTmr) pTmr->__tmrSetCurrentTime__
 #define tmrSetCurrentTime(pGpu, pTmr) tmrSetCurrentTime_DISPATCH(pGpu, pTmr)
 #define tmrSetCurrentTime_HAL(pGpu, pTmr) tmrSetCurrentTime_DISPATCH(pGpu, pTmr)
-#define tmrGetTimeLo_FNPTR(pTmr) pTmr->__tmrGetTimeLo__
-#define tmrGetTimeLo(pGpu, pTmr) tmrGetTimeLo_DISPATCH(pGpu, pTmr)
-#define tmrGetTimeLo_HAL(pGpu, pTmr) tmrGetTimeLo_DISPATCH(pGpu, pTmr)
-#define tmrGetTime_FNPTR(pTmr) pTmr->__tmrGetTime__
-#define tmrGetTime(pGpu, pTmr) tmrGetTime_DISPATCH(pGpu, pTmr)
-#define tmrGetTime_HAL(pGpu, pTmr) tmrGetTime_DISPATCH(pGpu, pTmr)
 #define tmrGetTimeEx_FNPTR(pTmr) pTmr->__tmrGetTimeEx__
 #define tmrGetTimeEx(pGpu, pTmr, arg3) tmrGetTimeEx_DISPATCH(pGpu, pTmr, arg3)
 #define tmrGetTimeEx_HAL(pGpu, pTmr, arg3) tmrGetTimeEx_DISPATCH(pGpu, pTmr, arg3)
@@ -446,14 +438,6 @@ static inline NV_STATUS tmrSetCurrentTime_DISPATCH(OBJGPU *pGpu, struct OBJTMR *
     return pTmr->__tmrSetCurrentTime__(pGpu, pTmr);
 }
 
-static inline NvU32 tmrGetTimeLo_DISPATCH(OBJGPU *pGpu, struct OBJTMR *pTmr) {
-    return pTmr->__tmrGetTimeLo__(pGpu, pTmr);
-}
-
-static inline NvU64 tmrGetTime_DISPATCH(OBJGPU *pGpu, struct OBJTMR *pTmr) {
-    return pTmr->__tmrGetTime__(pGpu, pTmr);
-}
-
 static inline NvU64 tmrGetTimeEx_DISPATCH(OBJGPU *pGpu, struct OBJTMR *pTmr, struct THREAD_STATE_NODE *arg3) {
     return pTmr->__tmrGetTimeEx__(pGpu, pTmr, arg3);
 }
@@ -627,6 +611,34 @@ static inline NV_STATUS tmrGetIntrStatus(OBJGPU *pGpu, struct OBJTMR *pTmr, NvU3
 
 #define tmrGetIntrStatus_HAL(pGpu, pTmr, pStatus, arg4) tmrGetIntrStatus(pGpu, pTmr, pStatus, arg4)
 
+NvU32 tmrGetTimeLo_GM107(OBJGPU *pGpu, struct OBJTMR *pTmr);
+
+
+#ifdef __nvoc_objtmr_h_disabled
+static inline NvU32 tmrGetTimeLo(OBJGPU *pGpu, struct OBJTMR *pTmr) {
+    NV_ASSERT_FAILED_PRECOMP("OBJTMR was disabled!");
+    return 0;
+}
+#else //__nvoc_objtmr_h_disabled
+#define tmrGetTimeLo(pGpu, pTmr) tmrGetTimeLo_GM107(pGpu, pTmr)
+#endif //__nvoc_objtmr_h_disabled
+
+#define tmrGetTimeLo_HAL(pGpu, pTmr) tmrGetTimeLo(pGpu, pTmr)
+
+NvU64 tmrGetTime_GM107(OBJGPU *pGpu, struct OBJTMR *pTmr);
+
+
+#ifdef __nvoc_objtmr_h_disabled
+static inline NvU64 tmrGetTime(OBJGPU *pGpu, struct OBJTMR *pTmr) {
+    NV_ASSERT_FAILED_PRECOMP("OBJTMR was disabled!");
+    return 0;
+}
+#else //__nvoc_objtmr_h_disabled
+#define tmrGetTime(pGpu, pTmr) tmrGetTime_GM107(pGpu, pTmr)
+#endif //__nvoc_objtmr_h_disabled
+
+#define tmrGetTime_HAL(pGpu, pTmr) tmrGetTime(pGpu, pTmr)
+
 NvU32 tmrReadTimeLoReg_TU102(OBJGPU *pGpu, struct OBJTMR *pTmr, struct THREAD_STATE_NODE *arg3);
 
 
@@ -914,18 +926,6 @@ NV_STATUS tmrSetCurrentTime_GV100(OBJGPU *pGpu, struct OBJTMR *pTmr);
 
 NV_STATUS tmrSetCurrentTime_GH100(OBJGPU *pGpu, struct OBJTMR *pTmr);
 
-static inline NvU32 tmrGetTimeLo_cf0499(OBJGPU *pGpu, struct OBJTMR *pTmr) {
-    return ((NvU32)(((NvU64)(osGetTimestamp())) & 4294967295U));
-}
-
-NvU32 tmrGetTimeLo_GM107(OBJGPU *pGpu, struct OBJTMR *pTmr);
-
-static inline NvU64 tmrGetTime_fa6bbe(OBJGPU *pGpu, struct OBJTMR *pTmr) {
-    return osGetTimestamp();
-}
-
-NvU64 tmrGetTime_GM107(OBJGPU *pGpu, struct OBJTMR *pTmr);
-
 NvU64 tmrGetTimeEx_GM107(OBJGPU *pGpu, struct OBJTMR *pTmr, struct THREAD_STATE_NODE *arg3);
 
 NvU64 tmrGetTimeEx_GH100(OBJGPU *pGpu, struct OBJTMR *pTmr, struct THREAD_STATE_NODE *arg3);