From a0e46cabd37740f32c2e5a6f6fe120154189d70d Mon Sep 17 00:00:00 2001 From: Andy Ritger Date: Tue, 25 Apr 2023 14:05:57 -0700 Subject: [PATCH] 525.116.03 --- CHANGELOG.md | 25 +++++- README.md | 17 +++- kernel-open/Kbuild | 2 +- kernel-open/conftest.sh | 41 +++++++++ kernel-open/nvidia-drm/nvidia-drm-drv.c | 2 + .../nvidia-drm/nvidia-drm-gem-nvkms-memory.c | 2 + .../nvidia-drm/nvidia-drm-gem-nvkms-memory.h | 2 + kernel-open/nvidia-drm/nvidia-drm.Kbuild | 1 + kernel-open/nvidia/nv-p2p.c | 5 +- src/common/displayport/inc/dp_connectorimpl.h | 8 ++ .../displayport/src/dp_connectorimpl.cpp | 4 +- src/common/displayport/src/dp_wardatabase.cpp | 11 +++ src/common/inc/nvBldVer.h | 22 ++--- src/common/inc/nvUnixVersion.h | 2 +- src/common/modeset/hdmipacket/nvhdmipkt.c | 3 +- .../nvswitch/common/inc/soe/soeifcore.h | 14 ++- src/common/nvswitch/kernel/inc/ls10/ls10.h | 2 - .../ls10/minion_nvlink_defines_public_ls10.h | 2 +- .../nvswitch/kernel/inc/ls10/soe_ls10.h | 2 +- .../kernel/inc/soe/bin/g_soeuc_lr10_dbg.h | 8 +- .../kernel/inc/soe/bin/g_soeuc_lr10_prd.h | 8 +- src/common/nvswitch/kernel/lr10/lr10.c | 24 +---- src/common/nvswitch/kernel/ls10/intr_ls10.c | 2 +- src/common/nvswitch/kernel/ls10/ls10.c | 72 ++++++++++++++- src/common/nvswitch/kernel/ls10/soe_ls10.c | 61 ++++++++++++- .../include/nvkms-headsurface-priv.h | 3 +- src/nvidia-modeset/include/nvkms-private.h | 2 - src/nvidia-modeset/include/nvkms-surface.h | 3 +- src/nvidia-modeset/src/nvkms-cursor.c | 2 +- src/nvidia-modeset/src/nvkms-flip.c | 2 +- .../src/nvkms-headsurface-config.c | 15 +++- .../src/nvkms-headsurface-ioctl.c | 6 +- src/nvidia-modeset/src/nvkms-headsurface.c | 34 +++++-- src/nvidia-modeset/src/nvkms-surface.c | 12 ++- src/nvidia-modeset/src/nvkms.c | 7 -- src/nvidia/generated/g_gpu_nvoc.c | 12 +++ src/nvidia/generated/g_gpu_nvoc.h | 13 ++- src/nvidia/generated/g_nv_name_released.h | 9 ++ src/nvidia/generated/g_system_nvoc.h | 13 ++- .../gpu/bus/arch/maxwell/kern_bus_gm107.c | 2 +- .../kernel/gpu/gr/kernel_graphics_context.c | 3 - .../arch/maxwell/virt_mem_allocator_gm107.c | 15 +++- .../gpu/mmu/arch/ampere/kern_gmmu_ga100.c | 5 +- .../gpu/mmu/arch/maxwell/kern_gmmu_gm107.c | 2 +- .../nvlink/arch/volta/kernel_nvlink_gv100.c | 5 +- src/nvidia/src/kernel/platform/cpu.c | 17 +++- .../src/libraries/resserv/src/rs_client.c | 90 ++++++++++--------- version.mk | 2 +- 48 files changed, 460 insertions(+), 156 deletions(-) diff --git a/CHANGELOG.md b/CHANGELOG.md index d7ab6c56b..457a16b28 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -2,6 +2,30 @@ ## Release 525 Entries +### [525.105.17] 2023-03-30 + +### [525.89.02] 2023-02-08 + +### [525.85.12] 2023-01-30 + +### [525.85.05] 2023-01-19 + +#### Fixed + +- Fix build problems with Clang 15.0, [#377](https://github.com/NVIDIA/open-gpu-kernel-modules/issues/377) by @ptr1337 + +### [525.78.01] 2023-01-05 + +### [525.60.13] 2022-12-05 + +### [525.60.11] 2022-11-28 + +#### Fixed + +- Fixed nvenc compatibility with usermode clients [#104](https://github.com/NVIDIA/open-gpu-kernel-modules/issues/104) + +### [525.53] 2022-11-10 + #### Changed - GSP firmware is now distributed as multiple firmware files: this release has `gsp_tu10x.bin` and `gsp_ad10x.bin` replacing `gsp.bin` from previous releases. @@ -10,7 +34,6 @@ #### Fixed -- Fix build problems with Clang 15.0, [#https://github.com/NVIDIA/open-gpu-kernel-modules/issues/377] by @ptr1337 - Add support for IBT (indirect branch tracking) on supported platforms, [#256](https://github.com/NVIDIA/open-gpu-kernel-modules/issues/256) by @rnd-ash - Return EINVAL when [failing to] allocating memory, [#280](https://github.com/NVIDIA/open-gpu-kernel-modules/pull/280) by @YusufKhan-gamedev - Fix various typos in nvidia/src/kernel, [#16](https://github.com/NVIDIA/open-gpu-kernel-modules/pull/16) by @alexisgeoffrey diff --git a/README.md b/README.md index d7471ce1d..6bf5f1dd2 100644 --- a/README.md +++ b/README.md @@ -1,7 +1,7 @@ # NVIDIA Linux Open GPU Kernel Module Source This is the source release of the NVIDIA Linux open GPU kernel modules, -version 525.105.17. +version 525.116.03. ## How to Build @@ -17,7 +17,7 @@ as root: Note that the kernel modules built here must be used with GSP firmware and user-space NVIDIA GPU driver components from a corresponding -525.105.17 driver release. This can be achieved by installing +525.116.03 driver release. This can be achieved by installing the NVIDIA GPU driver from the .run file using the `--no-kernel-modules` option. E.g., @@ -167,7 +167,7 @@ for the target kernel. ## Compatible GPUs The open-gpu-kernel-modules can be used on any Turing or later GPU -(see the table below). However, in the 525.105.17 release, +(see the table below). However, in the 525.116.03 release, GeForce and Workstation support is still considered alpha-quality. To enable use of the open kernel modules on GeForce and Workstation GPUs, @@ -175,7 +175,7 @@ set the "NVreg_OpenRmEnableUnsupportedGpus" nvidia.ko kernel module parameter to 1. For more details, see the NVIDIA GPU driver end user README here: -https://us.download.nvidia.com/XFree86/Linux-x86_64/525.105.17/README/kernel_open.html +https://us.download.nvidia.com/XFree86/Linux-x86_64/525.116.03/README/kernel_open.html In the below table, if three IDs are listed, the first is the PCI Device ID, the second is the PCI Subsystem Vendor ID, and the third is the PCI @@ -754,6 +754,7 @@ Subsystem Device ID. | NVIDIA RTX A3000 12GB Laptop GPU | 24B9 | | NVIDIA RTX A4500 Laptop GPU | 24BA | | NVIDIA RTX A3000 12GB Laptop GPU | 24BB | +| NVIDIA GeForce RTX 3060 | 24C7 | | NVIDIA GeForce RTX 3060 Ti | 24C9 | | NVIDIA GeForce RTX 3080 Laptop GPU | 24DC | | NVIDIA GeForce RTX 3070 Laptop GPU | 24DD | @@ -799,6 +800,8 @@ Subsystem Device ID. | NVIDIA RTX A1000 Laptop GPU | 25B9 | | NVIDIA RTX A2000 8GB Laptop GPU | 25BA | | NVIDIA RTX A500 Laptop GPU | 25BB | +| NVIDIA RTX A1000 6GB Laptop GPU | 25BC | +| NVIDIA RTX A500 Laptop GPU | 25BD | | NVIDIA GeForce RTX 3050 Ti Laptop GPU | 25E0 | | NVIDIA GeForce RTX 3050 Laptop GPU | 25E2 | | NVIDIA GeForce RTX 3050 Laptop GPU | 25E5 | @@ -816,8 +819,10 @@ Subsystem Device ID. | NVIDIA L40 | 26B5 10DE 17DA | | NVIDIA GeForce RTX 4080 | 2704 | | NVIDIA GeForce RTX 4090 Laptop GPU | 2717 | +| NVIDIA RTX 5000 Ada Generation Laptop GPU | 2730 | | NVIDIA GeForce RTX 4090 Laptop GPU | 2757 | | NVIDIA GeForce RTX 4070 Ti | 2782 | +| NVIDIA GeForce RTX 4070 | 2786 | | NVIDIA GeForce RTX 4080 Laptop GPU | 27A0 | | NVIDIA RTX 4000 SFF Ada Generation | 27B0 1028 16FA | | NVIDIA RTX 4000 SFF Ada Generation | 27B0 103C 16FA | @@ -825,10 +830,14 @@ Subsystem Device ID. | NVIDIA RTX 4000 SFF Ada Generation | 27B0 17AA 16FA | | NVIDIA L4 | 27B8 10DE 16CA | | NVIDIA L4 | 27B8 10DE 16EE | +| NVIDIA RTX 4000 Ada Generation Laptop GPU | 27BA | +| NVIDIA RTX 3500 Ada Generation Laptop GPU | 27BB | | NVIDIA GeForce RTX 4080 Laptop GPU | 27E0 | | NVIDIA GeForce RTX 4070 Laptop GPU | 2820 | +| NVIDIA RTX 3000 Ada Generation Laptop GPU | 2838 | | NVIDIA GeForce RTX 4070 Laptop GPU | 2860 | | NVIDIA GeForce RTX 4060 Laptop GPU | 28A0 | | NVIDIA GeForce RTX 4050 Laptop GPU | 28A1 | +| NVIDIA RTX 2000 Ada Generation Laptop GPU | 28B8 | | NVIDIA GeForce RTX 4060 Laptop GPU | 28E0 | | NVIDIA GeForce RTX 4050 Laptop GPU | 28E1 | diff --git a/kernel-open/Kbuild b/kernel-open/Kbuild index 5b3a1e787..360dd67ff 100644 --- a/kernel-open/Kbuild +++ b/kernel-open/Kbuild @@ -72,7 +72,7 @@ EXTRA_CFLAGS += -I$(src)/common/inc EXTRA_CFLAGS += -I$(src) EXTRA_CFLAGS += -Wall -MD $(DEFINES) $(INCLUDES) -Wno-cast-qual -Wno-error -Wno-format-extra-args EXTRA_CFLAGS += -D__KERNEL__ -DMODULE -DNVRM -EXTRA_CFLAGS += -DNV_VERSION_STRING=\"525.105.17\" +EXTRA_CFLAGS += -DNV_VERSION_STRING=\"525.116.03\" EXTRA_CFLAGS += -Wno-unused-function diff --git a/kernel-open/conftest.sh b/kernel-open/conftest.sh index 49afdc9d5..a629eb986 100755 --- a/kernel-open/conftest.sh +++ b/kernel-open/conftest.sh @@ -942,6 +942,23 @@ compile_test() { compile_check_conftest "$CODE" "NV_VFIO_MIGRATION_OPS_PRESENT" "" "types" ;; + vfio_migration_ops_has_migration_get_data_size) + # + # Determine if vfio_migration_ops struct has .migration_get_data_size field. + # + # Added by commit in 4e016f969529f ("vfio: Add an option to get migration + # data size") in v6.2 kernel. + # + CODE=" + #include + #include + int conftest_mdev_vfio_migration_ops_has_migration_get_data_size(void) { + return offsetof(struct vfio_migration_ops, migration_get_data_size); + }" + + compile_check_conftest "$CODE" "NV_VFIO_MIGRATION_OPS_HAS_MIGRATION_GET_DATA_SIZE" "" "types" + ;; + mdev_parent) # # Determine if the struct mdev_parent type is present. @@ -5494,6 +5511,30 @@ compile_test() { compile_check_conftest "$CODE" "NV_VM_AREA_STRUCT_HAS_CONST_VM_FLAGS" "" "types" ;; + drm_driver_has_dumb_destroy) + # + # Determine if the 'drm_driver' structure has a 'dumb_destroy' + # function pointer. + # + # Removed by commit 96a7b60f6ddb2 ("drm: remove dumb_destroy + # callback") in v6.3 linux-next (2023-02-10). + # + CODE=" + #if defined(NV_DRM_DRMP_H_PRESENT) + #include + #endif + + #if defined(NV_DRM_DRM_DRV_H_PRESENT) + #include + #endif + + int conftest_drm_driver_has_dumb_destroy(void) { + return offsetof(struct drm_driver, dumb_destroy); + }" + + compile_check_conftest "$CODE" "NV_DRM_DRIVER_HAS_DUMB_DESTROY" "" "types" + ;; + # When adding a new conftest entry, please use the correct format for # specifying the relevant upstream Linux kernel commit. # diff --git a/kernel-open/nvidia-drm/nvidia-drm-drv.c b/kernel-open/nvidia-drm/nvidia-drm-drv.c index cc6626a0c..875689066 100644 --- a/kernel-open/nvidia-drm/nvidia-drm-drv.c +++ b/kernel-open/nvidia-drm/nvidia-drm-drv.c @@ -921,7 +921,9 @@ static void nv_drm_update_drm_driver_features(void) nv_drm_driver.dumb_create = nv_drm_dumb_create; nv_drm_driver.dumb_map_offset = nv_drm_dumb_map_offset; +#if defined(NV_DRM_DRIVER_HAS_DUMB_DESTROY) nv_drm_driver.dumb_destroy = nv_drm_dumb_destroy; +#endif /* NV_DRM_DRIVER_HAS_DUMB_DESTROY */ #endif /* NV_DRM_ATOMIC_MODESET_AVAILABLE */ } diff --git a/kernel-open/nvidia-drm/nvidia-drm-gem-nvkms-memory.c b/kernel-open/nvidia-drm/nvidia-drm-gem-nvkms-memory.c index fdc6de69b..aafe1a3bc 100644 --- a/kernel-open/nvidia-drm/nvidia-drm-gem-nvkms-memory.c +++ b/kernel-open/nvidia-drm/nvidia-drm-gem-nvkms-memory.c @@ -583,11 +583,13 @@ int nv_drm_dumb_map_offset(struct drm_file *file, return ret; } +#if defined(NV_DRM_DRIVER_HAS_DUMB_DESTROY) int nv_drm_dumb_destroy(struct drm_file *file, struct drm_device *dev, uint32_t handle) { return drm_gem_handle_delete(file, handle); } +#endif /* NV_DRM_DRIVER_HAS_DUMB_DESTROY */ #endif diff --git a/kernel-open/nvidia-drm/nvidia-drm-gem-nvkms-memory.h b/kernel-open/nvidia-drm/nvidia-drm-gem-nvkms-memory.h index 7ecbb94d6..ea218a058 100644 --- a/kernel-open/nvidia-drm/nvidia-drm-gem-nvkms-memory.h +++ b/kernel-open/nvidia-drm/nvidia-drm-gem-nvkms-memory.h @@ -97,9 +97,11 @@ int nv_drm_dumb_map_offset(struct drm_file *file, struct drm_device *dev, uint32_t handle, uint64_t *offset); +#if defined(NV_DRM_DRIVER_HAS_DUMB_DESTROY) int nv_drm_dumb_destroy(struct drm_file *file, struct drm_device *dev, uint32_t handle); +#endif /* NV_DRM_DRIVER_HAS_DUMB_DESTROY */ struct drm_gem_object *nv_drm_gem_nvkms_prime_import( struct drm_device *dev, diff --git a/kernel-open/nvidia-drm/nvidia-drm.Kbuild b/kernel-open/nvidia-drm/nvidia-drm.Kbuild index 04233469d..a114b23de 100644 --- a/kernel-open/nvidia-drm/nvidia-drm.Kbuild +++ b/kernel-open/nvidia-drm/nvidia-drm.Kbuild @@ -125,3 +125,4 @@ NV_CONFTEST_TYPE_COMPILE_TESTS += dma_resv_reserve_fences NV_CONFTEST_TYPE_COMPILE_TESTS += reservation_object_reserve_shared_has_num_fences_arg NV_CONFTEST_TYPE_COMPILE_TESTS += drm_connector_has_override_edid NV_CONFTEST_TYPE_COMPILE_TESTS += vm_area_struct_has_const_vm_flags +NV_CONFTEST_TYPE_COMPILE_TESTS += drm_driver_has_dumb_destroy diff --git a/kernel-open/nvidia/nv-p2p.c b/kernel-open/nvidia/nv-p2p.c index 45b23ea71..e6fa5c5e8 100644 --- a/kernel-open/nvidia/nv-p2p.c +++ b/kernel-open/nvidia/nv-p2p.c @@ -431,6 +431,8 @@ static int nv_p2p_get_pages( goto failed; } + (*page_table)->gpu_uuid = gpu_uuid; + rc = nvidia_dev_get_uuid(gpu_uuid, sp); if (rc != 0) { @@ -461,10 +463,11 @@ static int nv_p2p_get_pages( { goto failed; } + + (*page_table)->gpu_uuid = gpu_uuid; } bGetPages = NV_TRUE; - (*page_table)->gpu_uuid = gpu_uuid; status = os_alloc_mem((void *)&(*page_table)->pages, (entries * sizeof(page))); diff --git a/src/common/displayport/inc/dp_connectorimpl.h b/src/common/displayport/inc/dp_connectorimpl.h index 76b89bbd3..c258af3a1 100644 --- a/src/common/displayport/inc/dp_connectorimpl.h +++ b/src/common/displayport/inc/dp_connectorimpl.h @@ -335,6 +335,14 @@ namespace DisplayPort // bool bPowerDownPhyBeforeD3; + // + // Reset the MSTM_CTRL registers on Synaptics branch device irrespective of + // IRQ VECTOR register having stale message. Synaptics device needs to reset + // the topology before issue of new LAM message if previous LAM was not finished + // bug 3928070 + // + bool bForceClearPendingMsg; + void sharedInit(); ConnectorImpl(MainLink * main, AuxBus * auxBus, Timer * timer, Connector::EventSink * sink); diff --git a/src/common/displayport/src/dp_connectorimpl.cpp b/src/common/displayport/src/dp_connectorimpl.cpp index 58ef89007..471090466 100644 --- a/src/common/displayport/src/dp_connectorimpl.cpp +++ b/src/common/displayport/src/dp_connectorimpl.cpp @@ -5756,7 +5756,7 @@ void ConnectorImpl::notifyLongPulseInternal(bool statusConnected) discoveryManager = new DiscoveryManager(messageManager, this, timer, hal); // Check and clear if any pending message here - if (hal->clearPendingMsg()) + if (hal->clearPendingMsg() || bForceClearPendingMsg) { DP_LOG(("DP> Stale MSG found: set branch to D3 and back to D0...")); if (hal->isAtLeastVersion(1, 4)) @@ -6799,6 +6799,7 @@ bool ConnectorImpl::updatePsrLinkState(bool bTrainLink) { // Bug 3438892 If the panel is turned off the reciever on its side, // force panel link on by writting 600 = 1 + this->hal->setDirtyLinkStatus(true); if (this->isLinkLost()) { hal->setPowerState(PowerStateD0); @@ -6963,5 +6964,6 @@ void ConnectorImpl::configInit() bNoFallbackInPostLQA = 0; LT2FecLatencyMs = 0; bDscCapBasedOnParent = false; + bForceClearPendingMsg = false; } diff --git a/src/common/displayport/src/dp_wardatabase.cpp b/src/common/displayport/src/dp_wardatabase.cpp index f4e6c483e..6ad8c947c 100644 --- a/src/common/displayport/src/dp_wardatabase.cpp +++ b/src/common/displayport/src/dp_wardatabase.cpp @@ -84,6 +84,17 @@ void ConnectorImpl::applyOuiWARs() // LT2FecLatencyMs = 57; + // + // This is to reset the MSTM control bit on the branch device. On this + // device, if continuous LAM message are sent very close then IRQ vector + // will fail to see stale/pending message and will not reset the MSTM_CTRL + // register. Currently making this specific to linux so as to have minimum + // effect on windows. Later proper fix for this will be generic. + // +#if defined(NV_UNIX) + bForceClearPendingMsg = true; +#endif + if (bDscMstCapBug3143315) { // diff --git a/src/common/inc/nvBldVer.h b/src/common/inc/nvBldVer.h index 5196b1a68..4530f8dc0 100644 --- a/src/common/inc/nvBldVer.h +++ b/src/common/inc/nvBldVer.h @@ -36,25 +36,25 @@ // and then checked back in. You cannot make changes to these sections without // corresponding changes to the buildmeister script #ifndef NV_BUILD_BRANCH - #define NV_BUILD_BRANCH r528_79 + #define NV_BUILD_BRANCH r528_95 #endif #ifndef NV_PUBLIC_BRANCH - #define NV_PUBLIC_BRANCH r528_79 + #define NV_PUBLIC_BRANCH r528_95 #endif #if defined(NV_LINUX) || defined(NV_BSD) || defined(NV_SUNOS) -#define NV_BUILD_BRANCH_VERSION "rel/gpu_drv/r525/r528_79-332" -#define NV_BUILD_CHANGELIST_NUM (32663405) +#define NV_BUILD_BRANCH_VERSION "rel/gpu_drv/r525/r528_95-360" +#define NV_BUILD_CHANGELIST_NUM (32748200) #define NV_BUILD_TYPE "Official" -#define NV_BUILD_NAME "rel/gpu_drv/r525/r528_79-332" -#define NV_LAST_OFFICIAL_CHANGELIST_NUM (32663405) +#define NV_BUILD_NAME "rel/gpu_drv/r525/r528_95-360" +#define NV_LAST_OFFICIAL_CHANGELIST_NUM (32748200) #else /* Windows builds */ -#define NV_BUILD_BRANCH_VERSION "r528_79-9" -#define NV_BUILD_CHANGELIST_NUM (32663405) -#define NV_BUILD_TYPE "Official" -#define NV_BUILD_NAME "528.89" -#define NV_LAST_OFFICIAL_CHANGELIST_NUM (32663405) +#define NV_BUILD_BRANCH_VERSION "r528_95-2" +#define NV_BUILD_CHANGELIST_NUM (32745585) +#define NV_BUILD_TYPE "Nightly" +#define NV_BUILD_NAME "r528_95-230419" +#define NV_LAST_OFFICIAL_CHANGELIST_NUM (32745585) #define NV_BUILD_BRANCH_BASE_VERSION R525 #endif // End buildmeister python edited section diff --git a/src/common/inc/nvUnixVersion.h b/src/common/inc/nvUnixVersion.h index f4708e473..8c1e4b3b7 100644 --- a/src/common/inc/nvUnixVersion.h +++ b/src/common/inc/nvUnixVersion.h @@ -4,7 +4,7 @@ #if defined(NV_LINUX) || defined(NV_BSD) || defined(NV_SUNOS) || defined(NV_VMWARE) || defined(NV_QNX) || defined(NV_INTEGRITY) || \ (defined(RMCFG_FEATURE_PLATFORM_GSP) && RMCFG_FEATURE_PLATFORM_GSP == 1) -#define NV_VERSION_STRING "525.105.17" +#define NV_VERSION_STRING "525.116.03" #else diff --git a/src/common/modeset/hdmipacket/nvhdmipkt.c b/src/common/modeset/hdmipacket/nvhdmipkt.c index f544d0790..42033621e 100644 --- a/src/common/modeset/hdmipacket/nvhdmipkt.c +++ b/src/common/modeset/hdmipacket/nvhdmipkt.c @@ -315,7 +315,8 @@ NvHdmi_QueryFRLConfig(NvHdmiPkt_Handle libHandle, } // if there is no FRL capability reported fail this call - if (pSinkCaps->linkMaxFRLRate == HDMI_FRL_DATA_RATE_NONE) + if ((pSrcCaps->linkMaxFRLRate == HDMI_FRL_DATA_RATE_NONE) || + (pSinkCaps->linkMaxFRLRate == HDMI_FRL_DATA_RATE_NONE)) { return NVHDMIPKT_FAIL; } diff --git a/src/common/nvswitch/common/inc/soe/soeifcore.h b/src/common/nvswitch/common/inc/soe/soeifcore.h index 99c4ca5ba..6e4af772d 100644 --- a/src/common/nvswitch/common/inc/soe/soeifcore.h +++ b/src/common/nvswitch/common/inc/soe/soeifcore.h @@ -86,6 +86,11 @@ enum * Read Power */ RM_SOE_CORE_CMD_GET_POWER_VALUES, + + /*! + * Set NPORT interrupts + */ + RM_SOE_CORE_CMD_SET_NPORT_INTRS, }; // Timeout for SOE reset callback function @@ -162,6 +167,13 @@ typedef struct NvU8 cmdType; } RM_SOE_CORE_CMD_GET_POWER; +typedef struct +{ + NvU8 cmdType; + NvU32 nport; + NvBool bEnable; +} RM_SOE_CORE_CMD_NPORT_INTRS; + typedef union { NvU8 cmdType; @@ -174,9 +186,9 @@ typedef union RM_SOE_CORE_CMD_GET_VOLTAGE getVoltage; RM_SOE_CORE_CMD_L2_STATE l2State; RM_SOE_CORE_CMD_GET_POWER getPower; + RM_SOE_CORE_CMD_NPORT_INTRS nportIntrs; } RM_SOE_CORE_CMD; - typedef struct { NvU8 msgType; diff --git a/src/common/nvswitch/kernel/inc/ls10/ls10.h b/src/common/nvswitch/kernel/inc/ls10/ls10.h index b968e9c1d..04e1635a3 100644 --- a/src/common/nvswitch/kernel/inc/ls10/ls10.h +++ b/src/common/nvswitch/kernel/inc/ls10/ls10.h @@ -792,7 +792,6 @@ typedef const struct #define nvswitch_ctrl_get_info_ls10 nvswitch_ctrl_get_info_lr10 #define nvswitch_ctrl_set_switch_port_config_ls10 nvswitch_ctrl_set_switch_port_config_lr10 -#define nvswitch_ctrl_get_fom_values_ls10 nvswitch_ctrl_get_fom_values_lr10 #define nvswitch_ctrl_get_throughput_counters_ls10 nvswitch_ctrl_get_throughput_counters_lr10 #define nvswitch_save_nvlink_seed_data_from_minion_to_inforom_ls10 nvswitch_save_nvlink_seed_data_from_minion_to_inforom_lr10 @@ -868,7 +867,6 @@ NvlStatus nvswitch_ctrl_get_nvlink_status_ls10(nvswitch_device *device, NVSWITCH NvlStatus nvswitch_ctrl_get_info_lr10(nvswitch_device *device, NVSWITCH_GET_INFO *p); NvlStatus nvswitch_ctrl_set_switch_port_config_lr10(nvswitch_device *device, NVSWITCH_SET_SWITCH_PORT_CONFIG *p); -NvlStatus nvswitch_ctrl_get_fom_values_lr10(nvswitch_device *device, NVSWITCH_GET_FOM_VALUES_PARAMS *p); NvlStatus nvswitch_ctrl_get_throughput_counters_lr10(nvswitch_device *device, NVSWITCH_GET_THROUGHPUT_COUNTERS_PARAMS *p); void nvswitch_save_nvlink_seed_data_from_minion_to_inforom_lr10(nvswitch_device *device, NvU32 linkId); void nvswitch_store_seed_data_from_inforom_to_corelib_lr10(nvswitch_device *device); diff --git a/src/common/nvswitch/kernel/inc/ls10/minion_nvlink_defines_public_ls10.h b/src/common/nvswitch/kernel/inc/ls10/minion_nvlink_defines_public_ls10.h index e9854ca85..e698a3631 100644 --- a/src/common/nvswitch/kernel/inc/ls10/minion_nvlink_defines_public_ls10.h +++ b/src/common/nvswitch/kernel/inc/ls10/minion_nvlink_defines_public_ls10.h @@ -47,5 +47,5 @@ typedef enum _MINION_STATUS } MINION_STATUS; #define LINKSTATUS_EMERGENCY_SHUTDOWN 0x29 -#define LINKSTATUS_INITPHASE1 0x24 + #define LINKSTATUS_INITPHASE1 0x24 #endif // _MINION_NVLINK_DEFINES_PUBLIC_H_ diff --git a/src/common/nvswitch/kernel/inc/ls10/soe_ls10.h b/src/common/nvswitch/kernel/inc/ls10/soe_ls10.h index 9cb717da8..921aa56d8 100644 --- a/src/common/nvswitch/kernel/inc/ls10/soe_ls10.h +++ b/src/common/nvswitch/kernel/inc/ls10/soe_ls10.h @@ -45,5 +45,5 @@ NvlStatus nvswitch_soe_register_event_callbacks_ls10(nvswitch_device *device); NvlStatus nvswitch_soe_restore_nport_state_ls10(nvswitch_device *device, NvU32 nport); NvlStatus nvswitch_soe_issue_nport_reset_ls10(nvswitch_device *device, NvU32 nport); void nvswitch_soe_init_l2_state_ls10(nvswitch_device *device); - +NvlStatus nvswitch_soe_set_nport_interrupts_ls10(nvswitch_device *device, NvU32 nport, NvBool bEnable); #endif //_SOE_LS10_H_ diff --git a/src/common/nvswitch/kernel/inc/soe/bin/g_soeuc_lr10_dbg.h b/src/common/nvswitch/kernel/inc/soe/bin/g_soeuc_lr10_dbg.h index 5f4c15f6e..e24f0361f 100644 --- a/src/common/nvswitch/kernel/inc/soe/bin/g_soeuc_lr10_dbg.h +++ b/src/common/nvswitch/kernel/inc/soe/bin/g_soeuc_lr10_dbg.h @@ -569,7 +569,7 @@ const NvU32 soe_ucode_data_lr10_dbg[] = { 0x328908f4, 0xfbfa324f, 0xbf02f971, 0xbcb0b2b9, 0xb9a6b0c9, 0xe41708f4, 0xbcffffd9, 0xfba6f09b, 0x980b08f4, 0xf9a60109, 0xf8050df4, 0xb2dc7202, 0x28d77eed, 0xb201fb00, 0x05ab98b9, 0xdeb2cfb2, 0xfd729cb2, 0x0042a97e, 0xf0fc00f8, 0xf9fc30f4, 0xbf62f9f0, 0x08e1b0b9, 0xd4b2a5b2, 0xa630c9bc, - 0x1d08f439, 0xa6f0d3bc, 0x1508f4f3, 0xa601b998, 0x0d0cf4f9, 0x24bd0101, 0x763efc06, 0x02f80043, + 0x1d08f439, 0xa6f0d3bc, 0x1508f4f3, 0xa601b998, 0x0d0cf4f9, 0x010124bd, 0x763efc06, 0x02f80043, 0x853e0101, 0x42bc0043, 0x0096b192, 0x060df401, 0x90010049, 0x96ff0399, 0x0b947e04, 0xb23bb200, 0xdd0c725a, 0x00001200, 0x7e3030bc, 0x320028d7, 0x00a433a1, 0x08b0b434, 0xb209c0b4, 0x1200da2d, 0x20bc0000, 0x01004e20, 0x0021367e, 0x0a00a033, 0x853e02f8, 0x00da0043, 0xbd000012, 0x01004cb4, @@ -590,7 +590,7 @@ const NvU32 soe_ucode_data_lr10_dbg[] = { 0xb3070bf4, 0xf80a00a4, 0xf8020a02, 0xffb9e400, 0xf4020a0f, 0x7cd9451b, 0x98000029, 0x903e049f, 0xf9180045, 0x00903308, 0x09f91828, 0x21009033, 0x5802f958, 0x93f003fe, 0x0c94b600, 0x08f4b9a6, 0xffe9e40f, 0x0c94b6ff, 0x0df4b9a6, 0x04ff980a, 0xd200f4b3, 0x350acfa0, 0x30f400f8, 0x05dcdff8, - 0x52f90000, 0xa4b2ffbf, 0xfe0149fe, 0x99900142, 0xb2b0b21c, 0xa0d5b2c3, 0x0a14bd9f, 0x18229035, + 0x52f90000, 0xa4b2ffbf, 0xfe0149fe, 0x99900142, 0xb2b0b21c, 0xa0d5b2c3, 0xbd350a9f, 0x18229014, 0x0046513e, 0x0bb24ab2, 0x2db2040c, 0x0028d77e, 0x8900ad33, 0xb329bf00, 0x900e0094, 0x00902011, 0x46513e04, 0x019eb900, 0x8904e9fd, 0xffff0000, 0xfcf094e9, 0x01f6f00b, 0x00ff00d9, 0x94e9ffff, 0xf00bbcf0, 0xf0d901b6, 0xfff0f0f0, 0xccf094e9, 0x01c6f00b, 0xccccccd9, 0x94e9ffcc, 0xf00bdcf0, @@ -2269,8 +2269,8 @@ const NvU32 soe_ucode_data_lr10_dbg[] = { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0xb32dc4cc, 0x58018cca, 0x7c52cad0, 0x4a5277fe, 0xf4188925, 0x3294f034, 0x06c315a3, 0x41c3e219, - 0x705ea2e7, 0x0577e70f, 0xcf75f41f, 0xfe6e071a, 0x8cd89b95, 0x33df19d3, 0xaba62f3f, 0x5fd448c8, + 0xb32dc4cc, 0x58018cca, 0x7c52cad0, 0x4a5277fe, 0xb63be2f4, 0x80eae4c6, 0xf2d546fa, 0xb745274e, + 0x705ea2e7, 0x0577e70f, 0xcf75f41f, 0xfe6e071a, 0x226d94df, 0xdb2e0eeb, 0xd11c2f47, 0x7666acd9, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, diff --git a/src/common/nvswitch/kernel/inc/soe/bin/g_soeuc_lr10_prd.h b/src/common/nvswitch/kernel/inc/soe/bin/g_soeuc_lr10_prd.h index 16d70610d..3f22e81ac 100644 --- a/src/common/nvswitch/kernel/inc/soe/bin/g_soeuc_lr10_prd.h +++ b/src/common/nvswitch/kernel/inc/soe/bin/g_soeuc_lr10_prd.h @@ -569,7 +569,7 @@ const NvU32 soe_ucode_data_lr10_prd[] = { 0x328908f4, 0xfbfa324f, 0xbf02f971, 0xbcb0b2b9, 0xb9a6b0c9, 0xe41708f4, 0xbcffffd9, 0xfba6f09b, 0x980b08f4, 0xf9a60109, 0xf8050df4, 0xb2dc7202, 0x28d77eed, 0xb201fb00, 0x05ab98b9, 0xdeb2cfb2, 0xfd729cb2, 0x0042a97e, 0xf0fc00f8, 0xf9fc30f4, 0xbf62f9f0, 0x08e1b0b9, 0xd4b2a5b2, 0xa630c9bc, - 0x1d08f439, 0xa6f0d3bc, 0x1508f4f3, 0xa601b998, 0x0d0cf4f9, 0x24bd0101, 0x763efc06, 0x02f80043, + 0x1d08f439, 0xa6f0d3bc, 0x1508f4f3, 0xa601b998, 0x0d0cf4f9, 0x010124bd, 0x763efc06, 0x02f80043, 0x853e0101, 0x42bc0043, 0x0096b192, 0x060df401, 0x90010049, 0x96ff0399, 0x0b947e04, 0xb23bb200, 0xdd0c725a, 0x00001200, 0x7e3030bc, 0x320028d7, 0x00a433a1, 0x08b0b434, 0xb209c0b4, 0x1200da2d, 0x20bc0000, 0x01004e20, 0x0021367e, 0x0a00a033, 0x853e02f8, 0x00da0043, 0xbd000012, 0x01004cb4, @@ -590,7 +590,7 @@ const NvU32 soe_ucode_data_lr10_prd[] = { 0xb3070bf4, 0xf80a00a4, 0xf8020a02, 0xffb9e400, 0xf4020a0f, 0x7cd9451b, 0x98000029, 0x903e049f, 0xf9180045, 0x00903308, 0x09f91828, 0x21009033, 0x5802f958, 0x93f003fe, 0x0c94b600, 0x08f4b9a6, 0xffe9e40f, 0x0c94b6ff, 0x0df4b9a6, 0x04ff980a, 0xd200f4b3, 0x350acfa0, 0x30f400f8, 0x05dcdff8, - 0x52f90000, 0xa4b2ffbf, 0xfe0149fe, 0x99900142, 0xb2b0b21c, 0xa0d5b2c3, 0x0a14bd9f, 0x18229035, + 0x52f90000, 0xa4b2ffbf, 0xfe0149fe, 0x99900142, 0xb2b0b21c, 0xa0d5b2c3, 0xbd350a9f, 0x18229014, 0x0046513e, 0x0bb24ab2, 0x2db2040c, 0x0028d77e, 0x8900ad33, 0xb329bf00, 0x900e0094, 0x00902011, 0x46513e04, 0x019eb900, 0x8904e9fd, 0xffff0000, 0xfcf094e9, 0x01f6f00b, 0x00ff00d9, 0x94e9ffff, 0xf00bbcf0, 0xf0d901b6, 0xfff0f0f0, 0xccf094e9, 0x01c6f00b, 0xccccccd9, 0x94e9ffcc, 0xf00bdcf0, @@ -2269,8 +2269,8 @@ const NvU32 soe_ucode_data_lr10_prd[] = { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0xb32dc4cc, 0x58018cca, 0x7c52cad0, 0x4a5277fe, 0xf4188925, 0x3294f034, 0x06c315a3, 0x41c3e219, - 0x705ea2e7, 0x0577e70f, 0xcf75f41f, 0xfe6e071a, 0x8cd89b95, 0x33df19d3, 0xaba62f3f, 0x5fd448c8, + 0xb32dc4cc, 0x58018cca, 0x7c52cad0, 0x4a5277fe, 0xb63be2f4, 0x80eae4c6, 0xf2d546fa, 0xb745274e, + 0x705ea2e7, 0x0577e70f, 0xcf75f41f, 0xfe6e071a, 0x226d94df, 0xdb2e0eeb, 0xd11c2f47, 0x7666acd9, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, diff --git a/src/common/nvswitch/kernel/lr10/lr10.c b/src/common/nvswitch/kernel/lr10/lr10.c index 0dc9ae9c9..37586b3f6 100644 --- a/src/common/nvswitch/kernel/lr10/lr10.c +++ b/src/common/nvswitch/kernel/lr10/lr10.c @@ -3855,7 +3855,7 @@ nvswitch_initialize_device_state_lr10 } else { - NVSWITCH_PRINT(device, ERROR, + NVSWITCH_PRINT(device, WARN, "%s: Skipping SPI init.\n", __FUNCTION__); } @@ -3874,7 +3874,7 @@ nvswitch_initialize_device_state_lr10 } else { - NVSWITCH_PRINT(device, ERROR, + NVSWITCH_PRINT(device, WARN, "%s: Skipping SMBPBI init.\n", __FUNCTION__); } @@ -4579,17 +4579,6 @@ _nvswitch_get_info_revision_minor_ext return (DRF_VAL(_PSMC, _BOOT_42, _MINOR_EXTENDED_REVISION, val)); } -static NvU32 -_nvswitch_get_info_voltage -( - nvswitch_device *device -) -{ - NvU32 voltage = 0; - - return voltage; -} - static NvBool _nvswitch_inforom_nvl_supported ( @@ -4769,7 +4758,7 @@ nvswitch_ctrl_get_info_lr10 p->info[i] = device->switch_pll.vco_freq_khz; break; case NVSWITCH_GET_INFO_INDEX_VOLTAGE_MVOLT: - p->info[i] = _nvswitch_get_info_voltage(device); + retval = -NVL_ERR_NOT_SUPPORTED; break; case NVSWITCH_GET_INFO_INDEX_PHYSICAL_ID: p->info[i] = nvswitch_read_physical_id(device); @@ -6413,13 +6402,6 @@ nvswitch_ctrl_get_fom_values_lr10 return -NVL_BAD_ARGS; } - if (nvswitch_is_link_in_reset(device, link)) - { - NVSWITCH_PRINT(device, ERROR, "%s: link #%d is in reset\n", - __FUNCTION__, p->linkId); - return -NVL_ERR_INVALID_STATE; - } - status = nvswitch_minion_get_dl_status(device, p->linkId, NV_NVLSTAT_TR16, 0, &statData); p->figureOfMeritValues[0] = (NvU16) (statData & 0xFFFF); diff --git a/src/common/nvswitch/kernel/ls10/intr_ls10.c b/src/common/nvswitch/kernel/ls10/intr_ls10.c index 1db53815b..49fc019e4 100644 --- a/src/common/nvswitch/kernel/ls10/intr_ls10.c +++ b/src/common/nvswitch/kernel/ls10/intr_ls10.c @@ -6335,7 +6335,7 @@ _nvswitch_service_nvlipt_lnk_nonfatal_ls10 lnkStateRequest = NVSWITCH_LINK_RD32_LS10(device, link_info->linkNumber, NVLIPT_LNK , _NVLIPT_LNK , _CTRL_LINK_STATE_REQUEST); - if(FLD_TEST_DRF(_NVLIPT_LNK, _CTRL_LINK_STATE_REQUEST, _REQUEST, _ACTIVE, lnkStateRequest) && + if(FLD_TEST_DRF(_NVLIPT_LNK, _CTRL_LINK_STATE_REQUEST, _REQUEST, _ACTIVE, lnkStateRequest) && linkState == NV_NVLDL_TOP_LINK_STATE_STATE_FAULT) { chip_device->deferredLinkErrors[link].bResetAndDrainRetry = NV_TRUE; diff --git a/src/common/nvswitch/kernel/ls10/ls10.c b/src/common/nvswitch/kernel/ls10/ls10.c index e317f97b6..78355b485 100644 --- a/src/common/nvswitch/kernel/ls10/ls10.c +++ b/src/common/nvswitch/kernel/ls10/ls10.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2020-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -1103,6 +1103,18 @@ nvswitch_link_disable_interrupts_ls10 instance = link / NVSWITCH_LINKS_PER_NVLIPT_LS10; localLinkIdx = link % NVSWITCH_LINKS_PER_NVLIPT_LS10; + if (nvswitch_is_soe_supported(device)) + { + nvswitch_soe_set_nport_interrupts_ls10(device, link, NV_FALSE); + } + else + { + NVSWITCH_NPORT_WR32_LS10(device, link, _NPORT, _ERR_CONTROL_COMMON_NPORT, + DRF_NUM(_NPORT, _ERR_CONTROL_COMMON_NPORT, _CORRECTABLEENABLE, 0x0) | + DRF_NUM(_NPORT, _ERR_CONTROL_COMMON_NPORT, _FATALENABLE, 0x0) | + DRF_NUM(_NPORT, _ERR_CONTROL_COMMON_NPORT, _NONFATALENABLE, 0x0)); + } + NVSWITCH_ENG_WR32(device, NVLW, , instance, _NVLW, _LINK_INTR_0_MASK(localLinkIdx), DRF_NUM(_NVLW, _LINK_INTR_0_MASK, _FATAL, 0x0) | DRF_NUM(_NVLW, _LINK_INTR_0_MASK, _NONFATAL, 0x0) | @@ -1133,6 +1145,18 @@ _nvswitch_link_reset_interrupts_ls10 NvU32 eng_instance = link / NVSWITCH_LINKS_PER_NVLIPT_LS10; NvU32 localLinkNum = link % NVSWITCH_LINKS_PER_NVLIPT_LS10; + if (nvswitch_is_soe_supported(device)) + { + nvswitch_soe_set_nport_interrupts_ls10(device, link, NV_TRUE); + } + else + { + NVSWITCH_NPORT_WR32_LS10(device, link, _NPORT, _ERR_CONTROL_COMMON_NPORT, + DRF_NUM(_NPORT, _ERR_CONTROL_COMMON_NPORT, _CORRECTABLEENABLE, 0x1) | + DRF_NUM(_NPORT, _ERR_CONTROL_COMMON_NPORT, _FATALENABLE, 0x1) | + DRF_NUM(_NPORT, _ERR_CONTROL_COMMON_NPORT, _NONFATALENABLE, 0x1)); + } + NVSWITCH_ENG_WR32(device, NVLW, , eng_instance, _NVLW, _LINK_INTR_0_MASK(localLinkNum), DRF_NUM(_NVLW, _LINK_INTR_0_MASK, _FATAL, 0x1) | DRF_NUM(_NVLW, _LINK_INTR_0_MASK, _NONFATAL, 0x0) | @@ -1477,7 +1501,7 @@ nvswitch_reset_and_drain_links_ls10 // DEBUG_CLEAR (0x144) register // - Assert NPortWarmReset[i] using the WARMRESET (0x140) register // - // nvswitch_soe_issue_nport_reset_ls10(device, link); + nvswitch_soe_issue_nport_reset_ls10(device, link); // // Step 5.0 : Issue Minion request to perform the link reset sequence @@ -1555,7 +1579,7 @@ nvswitch_reset_and_drain_links_ls10 // - Assert NPORT INITIALIZATION and program the state tracking RAMS // - Restore NPORT state after reset // - // nvswitch_soe_restore_nport_state_ls10(device, link); + nvswitch_soe_restore_nport_state_ls10(device, link); // Step 7.0 : Re-program the routing table for DBEs @@ -2715,6 +2739,46 @@ nvswitch_get_num_links_ls10 return NVSWITCH_NUM_LINKS_LS10; } +NvlStatus +nvswitch_ctrl_get_fom_values_ls10 +( + nvswitch_device *device, + NVSWITCH_GET_FOM_VALUES_PARAMS *p +) +{ + NvlStatus status; + NvU32 statData; + nvlink_link *link; + + link = nvswitch_get_link(device, p->linkId); + if (link == NULL) + { + NVSWITCH_PRINT(device, ERROR, "%s: link #%d invalid\n", + __FUNCTION__, p->linkId); + return -NVL_BAD_ARGS; + } + + if (nvswitch_is_link_in_reset(device, link)) + { + NVSWITCH_PRINT(device, ERROR, "%s: link #%d is in reset\n", + __FUNCTION__, p->linkId); + return -NVL_ERR_INVALID_STATE; + } + + status = nvswitch_minion_get_dl_status(device, p->linkId, + NV_NVLSTAT_TR16, 0, &statData); + p->figureOfMeritValues[0] = (NvU16) (statData & 0xFFFF); + p->figureOfMeritValues[1] = (NvU16) ((statData >> 16) & 0xFFFF); + + status = nvswitch_minion_get_dl_status(device, p->linkId, + NV_NVLSTAT_TR17, 0, &statData); + p->figureOfMeritValues[2] = (NvU16) (statData & 0xFFFF); + p->figureOfMeritValues[3] = (NvU16) ((statData >> 16) & 0xFFFF); + + p->numLanes = nvswitch_get_sublink_width(device, p->linkId); + + return status; +} void nvswitch_set_fatal_error_ls10 @@ -5406,7 +5470,7 @@ nvswitch_ctrl_get_board_part_number_ls10 if (!pInforom->OBD.bValid) { NVSWITCH_PRINT(device, ERROR, "OBD data is not available\n"); - return -NVL_ERR_GENERIC; + return -NVL_ERR_NOT_SUPPORTED; } pOBDObj = &pInforom->OBD.object.v2; diff --git a/src/common/nvswitch/kernel/ls10/soe_ls10.c b/src/common/nvswitch/kernel/ls10/soe_ls10.c index 0488b9154..4bee38438 100644 --- a/src/common/nvswitch/kernel/ls10/soe_ls10.c +++ b/src/common/nvswitch/kernel/ls10/soe_ls10.c @@ -400,7 +400,7 @@ nvswitch_soe_init_l2_state_ls10 nvswitch_os_memset(&cmd, 0, sizeof(cmd)); cmd.hdr.unitId = RM_SOE_UNIT_CORE; - cmd.hdr.size = sizeof(cmd); + cmd.hdr.size = RM_SOE_CMD_SIZE(CORE, L2_STATE); pL2State = &cmd.cmd.core.l2State; pL2State->cmdType = RM_SOE_CORE_CMD_INIT_L2_STATE; @@ -420,6 +420,65 @@ nvswitch_soe_init_l2_state_ls10 } } +/* + * @Brief : Enable/Disable NPORT interrupts + * + * @param[in] device + * @param[in] nport + */ +NvlStatus +nvswitch_soe_set_nport_interrupts_ls10 +( + nvswitch_device *device, + NvU32 nport, + NvBool bEnable +) +{ + FLCN *pFlcn; + NvU32 cmdSeqDesc = 0; + NV_STATUS status; + RM_FLCN_CMD_SOE cmd; + NVSWITCH_TIMEOUT timeout; + RM_SOE_CORE_CMD_NPORT_INTRS *pNportIntrs; + + if (!nvswitch_is_soe_supported(device)) + { + NVSWITCH_PRINT(device, ERROR, + "%s: SOE is not supported\n", + __FUNCTION__); + return -NVL_ERR_INVALID_STATE; + } + + pFlcn = device->pSoe->pFlcn; + + nvswitch_os_memset(&cmd, 0, sizeof(cmd)); + cmd.hdr.unitId = RM_SOE_UNIT_CORE; + cmd.hdr.size = RM_SOE_CMD_SIZE(CORE, NPORT_INTRS); + + pNportIntrs = &cmd.cmd.core.nportIntrs; + pNportIntrs->cmdType = RM_SOE_CORE_CMD_SET_NPORT_INTRS; + pNportIntrs->nport = nport; + pNportIntrs->bEnable = bEnable; + + nvswitch_timeout_create(NVSWITCH_INTERVAL_5MSEC_IN_NS, &timeout); + status = flcnQueueCmdPostBlocking(device, pFlcn, + (PRM_FLCN_CMD)&cmd, + NULL, // pMsg + NULL, // pPayload + SOE_RM_CMDQ_LOG_ID, + &cmdSeqDesc, + &timeout); + if (status != NV_OK) + { + NVSWITCH_PRINT(device, ERROR, + "%s: Failed to send SET_NPORT_INTRS command to SOE, status 0x%x\n", + __FUNCTION__, status); + return -NVL_ERR_GENERIC; + } + + return NVL_SUCCESS; +} + /* * @Brief : Init sequence for SOE FSP RISCV image * diff --git a/src/nvidia-modeset/include/nvkms-headsurface-priv.h b/src/nvidia-modeset/include/nvkms-headsurface-priv.h index ca4a61a60..a52e09e3b 100644 --- a/src/nvidia-modeset/include/nvkms-headsurface-priv.h +++ b/src/nvidia-modeset/include/nvkms-headsurface-priv.h @@ -481,6 +481,7 @@ static inline void HsIncrementNextIndex( } static inline void HsChangeSurfaceFlipRefCount( + NVDevEvoPtr pDevEvo, NVSurfaceEvoPtr pSurfaceEvo, NvBool increase) { @@ -488,7 +489,7 @@ static inline void HsChangeSurfaceFlipRefCount( if (increase) { nvEvoIncrementSurfaceRefCnts(pSurfaceEvo); } else { - nvEvoDecrementSurfaceRefCnts(pSurfaceEvo); + nvEvoDecrementSurfaceRefCnts(pDevEvo, pSurfaceEvo); } } } diff --git a/src/nvidia-modeset/include/nvkms-private.h b/src/nvidia-modeset/include/nvkms-private.h index cfb5eb9e5..d8230639a 100644 --- a/src/nvidia-modeset/include/nvkms-private.h +++ b/src/nvidia-modeset/include/nvkms-private.h @@ -69,8 +69,6 @@ NVEvoApiHandlesRec *nvGetSurfaceHandlesFromOpenDev( struct NvKmsPerOpenDev *pOpenDev); const NVEvoApiHandlesRec *nvGetSurfaceHandlesFromOpenDevConst( const struct NvKmsPerOpenDev *pOpenDev); -NVDevEvoPtr nvGetDevEvoFromOpenDev( - const struct NvKmsPerOpenDev *pOpenDev); void nvKmsServiceNonStallInterrupt(void *dataPtr, NvU32 dataU32); diff --git a/src/nvidia-modeset/include/nvkms-surface.h b/src/nvidia-modeset/include/nvkms-surface.h index 0a05242cd..181986e91 100644 --- a/src/nvidia-modeset/include/nvkms-surface.h +++ b/src/nvidia-modeset/include/nvkms-surface.h @@ -47,7 +47,8 @@ void nvEvoIncrementSurfaceStructRefCnt(NVSurfaceEvoPtr pSurfaceEvo); void nvEvoDecrementSurfaceStructRefCnt(NVSurfaceEvoPtr pSurfaceEvo); void nvEvoIncrementSurfaceRefCnts(NVSurfaceEvoPtr pSurfaceEvo); -void nvEvoDecrementSurfaceRefCnts(NVSurfaceEvoPtr pSurfaceEvo); +void nvEvoDecrementSurfaceRefCnts(NVDevEvoPtr pDevEvo, + NVSurfaceEvoPtr pSurfaceEvo); NvBool nvEvoSurfaceRefCntsTooLarge(const NVSurfaceEvoRec *pSurfaceEvo); diff --git a/src/nvidia-modeset/src/nvkms-cursor.c b/src/nvidia-modeset/src/nvkms-cursor.c index 30467d681..1ffd9ea23 100644 --- a/src/nvidia-modeset/src/nvkms-cursor.c +++ b/src/nvidia-modeset/src/nvkms-cursor.c @@ -118,7 +118,7 @@ SetCursorImage(NVDispEvoPtr pDispEvo, } if (pSurfaceEvoOld) { - nvEvoDecrementSurfaceRefCnts(pSurfaceEvoOld); + nvEvoDecrementSurfaceRefCnts(pDevEvo, pSurfaceEvoOld); } pDevEvo->gpus[sd].headState[head].cursor.pSurfaceEvo = pSurfaceEvoNew; diff --git a/src/nvidia-modeset/src/nvkms-flip.c b/src/nvidia-modeset/src/nvkms-flip.c index 14e38b078..de564b2fe 100644 --- a/src/nvidia-modeset/src/nvkms-flip.c +++ b/src/nvidia-modeset/src/nvkms-flip.c @@ -2368,7 +2368,7 @@ static void ChangeSurfaceFlipRefCount( if (increase) { nvEvoIncrementSurfaceRefCnts(pSurfaceEvo); } else { - nvEvoDecrementSurfaceRefCnts(pSurfaceEvo); + nvEvoDecrementSurfaceRefCnts(pDevEvo, pSurfaceEvo); } } } diff --git a/src/nvidia-modeset/src/nvkms-headsurface-config.c b/src/nvidia-modeset/src/nvkms-headsurface-config.c index b6dfaeb5b..f44a258e4 100644 --- a/src/nvidia-modeset/src/nvkms-headsurface-config.c +++ b/src/nvidia-modeset/src/nvkms-headsurface-config.c @@ -1835,16 +1835,21 @@ static void HsConfigInitFlipQueue( } static void HsConfigUpdateSurfaceRefCount( + NVDevEvoPtr pDevEvo, const NVHsChannelConfig *pChannelConfig, NvBool increase) { - HsChangeSurfaceFlipRefCount(pChannelConfig->warpMesh.pSurface, increase); + HsChangeSurfaceFlipRefCount( + pDevEvo, pChannelConfig->warpMesh.pSurface, increase); - HsChangeSurfaceFlipRefCount(pChannelConfig->pBlendTexSurface, increase); + HsChangeSurfaceFlipRefCount( + pDevEvo, pChannelConfig->pBlendTexSurface, increase); - HsChangeSurfaceFlipRefCount(pChannelConfig->pOffsetTexSurface, increase); + HsChangeSurfaceFlipRefCount( + pDevEvo, pChannelConfig->pOffsetTexSurface, increase); - HsChangeSurfaceFlipRefCount(pChannelConfig->cursor.pSurfaceEvo, increase); + HsChangeSurfaceFlipRefCount( + pDevEvo, pChannelConfig->cursor.pSurfaceEvo, increase); } /*! @@ -2444,6 +2449,7 @@ void nvHsConfigStart( */ if (pHsConfigOneHead->pHsChannel != NULL) { HsConfigUpdateSurfaceRefCount( + pDevEvo, &pHsConfigOneHead->channelConfig, TRUE /* increase */); } @@ -2454,6 +2460,7 @@ void nvHsConfigStart( */ if (pDispEvo->pHsChannel[apiHead] != NULL) { HsConfigUpdateSurfaceRefCount( + pDevEvo, &pDispEvo->pHsChannel[apiHead]->config, FALSE /* increase */); } diff --git a/src/nvidia-modeset/src/nvkms-headsurface-ioctl.c b/src/nvidia-modeset/src/nvkms-headsurface-ioctl.c index f75c9fb17..a68fd2db8 100644 --- a/src/nvidia-modeset/src/nvkms-headsurface-ioctl.c +++ b/src/nvidia-modeset/src/nvkms-headsurface-ioctl.c @@ -197,6 +197,8 @@ static void HsIoctlSetCursorImage( NVHsChannelEvoRec *pHsChannel, NVSurfaceEvoRec *pSurfaceEvo) { + NVDevEvoPtr pDevEvo = pHsChannel->pDispEvo->pDevEvo; + /* * Increment the refcnt of the new surface, and * decrement the refcnt of the old surface. @@ -206,10 +208,10 @@ static void HsIoctlSetCursorImage( */ HsChangeSurfaceFlipRefCount( - pSurfaceEvo, TRUE /* increase */); + pDevEvo, pSurfaceEvo, TRUE /* increase */); HsChangeSurfaceFlipRefCount( - pHsChannel->config.cursor.pSurfaceEvo, FALSE /* increase */); + pDevEvo, pHsChannel->config.cursor.pSurfaceEvo, FALSE /* increase */); pHsChannel->config.cursor.pSurfaceEvo = pSurfaceEvo; diff --git a/src/nvidia-modeset/src/nvkms-headsurface.c b/src/nvidia-modeset/src/nvkms-headsurface.c index 42777c097..060af4271 100644 --- a/src/nvidia-modeset/src/nvkms-headsurface.c +++ b/src/nvidia-modeset/src/nvkms-headsurface.c @@ -549,24 +549,25 @@ static NvBool HsFlipQueueEntryIsReady( * Update the reference count of all the surfaces described in the pHwState. */ static void HsUpdateFlipQueueEntrySurfaceRefCount( + NVDevEvoPtr pDevEvo, const NVFlipChannelEvoHwState *pHwState, NvBool increase) { HsChangeSurfaceFlipRefCount( - pHwState->pSurfaceEvo[NVKMS_LEFT], increase); + pDevEvo, pHwState->pSurfaceEvo[NVKMS_LEFT], increase); HsChangeSurfaceFlipRefCount( - pHwState->pSurfaceEvo[NVKMS_RIGHT], increase); + pDevEvo, pHwState->pSurfaceEvo[NVKMS_RIGHT], increase); HsChangeSurfaceFlipRefCount( - pHwState->completionNotifier.surface.pSurfaceEvo, increase); + pDevEvo, pHwState->completionNotifier.surface.pSurfaceEvo, increase); if (!pHwState->syncObject.usingSyncpt) { HsChangeSurfaceFlipRefCount( - pHwState->syncObject.u.semaphores.acquireSurface.pSurfaceEvo, increase); + pDevEvo, pHwState->syncObject.u.semaphores.acquireSurface.pSurfaceEvo, increase); HsChangeSurfaceFlipRefCount( - pHwState->syncObject.u.semaphores.releaseSurface.pSurfaceEvo, increase); + pDevEvo, pHwState->syncObject.u.semaphores.releaseSurface.pSurfaceEvo, increase); } } @@ -605,7 +606,7 @@ static void HsReleaseFlipQueueEntry( * HeadSurface no longer needs to read from the surfaces in pHwState; * decrement their reference counts. */ - HsUpdateFlipQueueEntrySurfaceRefCount(pHwState, FALSE); + HsUpdateFlipQueueEntrySurfaceRefCount(pDevEvo, pHwState, FALSE); } /*! @@ -687,6 +688,7 @@ void nvHsPushFlipQueueEntry( const NvU8 layer, const NVFlipChannelEvoHwState *pHwState) { + NVDevEvoPtr pDevEvo = pHsChannel->pDispEvo->pDevEvo; NVListRec *pFlipQueue = &pHsChannel->flipQueue[layer].queue; NVHsChannelFlipQueueEntry *pEntry = nvCalloc(1, sizeof(*pEntry)); @@ -703,7 +705,7 @@ void nvHsPushFlipQueueEntry( /* Increment the ref counts on the surfaces in the flip queue entry. */ - HsUpdateFlipQueueEntrySurfaceRefCount(&pEntry->hwState, TRUE); + HsUpdateFlipQueueEntrySurfaceRefCount(pDevEvo, &pEntry->hwState, TRUE); /* "Fast forward" through existing flip queue entries that are ready. */ @@ -2092,6 +2094,17 @@ static NvBool HsCanOmitNonSgHsUpdate(NVHsChannelEvoPtr pHsChannel) const NVSwapGroupRec *pHeadSwapGroup = pHsChannel->pDispEvo->pSwapGroup[pHsChannel->apiHead]; + /* + * When fullscreen swapgroup flipping, updating + * non-swapgroup content at vblank is unnecessary and + * dangerous, since it results in releasing client + * semaphores before their contents have actually been + * displayed. + */ + if (pHsChannel->swapGroupFlipping) { + return NV_TRUE; + } + /* * In the case of a fullscreen swapgroup, we can generally omit updating * the headsurface entirely upon vblank as long as the client is @@ -2251,8 +2264,11 @@ static void HsVBlankCallback(NVDispEvoRec *pDispEvo, */ /* - * When fullscreen swapgroup flipping, we don't need to update - * non-swapgroup content at vblank. + * When fullscreen swapgroup flipping, updating + * non-swapgroup content at vblank is unnecessary and + * dangerous, since it results in releasing client + * semaphores before their contents have actually been + * displayed. */ if (!pHsChannel->swapGroupFlipping) { nvHsNextFrame(pHsDevice, pHsChannel, diff --git a/src/nvidia-modeset/src/nvkms-surface.c b/src/nvidia-modeset/src/nvkms-surface.c index ce2f95a2c..7db9234f4 100644 --- a/src/nvidia-modeset/src/nvkms-surface.c +++ b/src/nvidia-modeset/src/nvkms-surface.c @@ -992,7 +992,7 @@ void nvEvoFreeClientSurfaces(NVDevEvoPtr pDevEvo, nvEvoDestroyApiHandle(pOpenDevSurfaceHandles, surfaceHandle); if (isOwner) { - nvEvoDecrementSurfaceRefCnts(pSurfaceEvo); + nvEvoDecrementSurfaceRefCnts(pDevEvo, pSurfaceEvo); } else { nvEvoDecrementSurfaceStructRefCnt(pSurfaceEvo); } @@ -1037,7 +1037,7 @@ void nvEvoUnregisterSurface(NVDevEvoPtr pDevEvo, /* Remove the handle from the calling client's namespace. */ nvEvoDestroyApiHandle(pOpenDevSurfaceHandles, surfaceHandle); - nvEvoDecrementSurfaceRefCnts(pSurfaceEvo); + nvEvoDecrementSurfaceRefCnts(pDevEvo, pSurfaceEvo); } void nvEvoReleaseSurface(NVDevEvoPtr pDevEvo, @@ -1075,15 +1075,13 @@ void nvEvoIncrementSurfaceRefCnts(NVSurfaceEvoPtr pSurfaceEvo) pSurfaceEvo->structRefCnt++; } -void nvEvoDecrementSurfaceRefCnts(NVSurfaceEvoPtr pSurfaceEvo) +void nvEvoDecrementSurfaceRefCnts(NVDevEvoPtr pDevEvo, + NVSurfaceEvoPtr pSurfaceEvo) { nvAssert(pSurfaceEvo->rmRefCnt >= 1); pSurfaceEvo->rmRefCnt--; if (pSurfaceEvo->rmRefCnt == 0) { - NVDevEvoPtr pDevEvo = - nvGetDevEvoFromOpenDev(pSurfaceEvo->owner.pOpenDev); - /* * Don't sync if this surface was registered as not requiring display * hardware access, to WAR timeouts that result from OGL unregistering @@ -1288,7 +1286,7 @@ void nvEvoUnregisterDeferredRequestFifo( pDeferredRequestFifo->fifo, 0); - nvEvoDecrementSurfaceRefCnts(pDeferredRequestFifo->pSurfaceEvo); + nvEvoDecrementSurfaceRefCnts(pDevEvo, pDeferredRequestFifo->pSurfaceEvo); nvFree(pDeferredRequestFifo); } diff --git a/src/nvidia-modeset/src/nvkms.c b/src/nvidia-modeset/src/nvkms.c index 3a660f097..9f6681920 100644 --- a/src/nvidia-modeset/src/nvkms.c +++ b/src/nvidia-modeset/src/nvkms.c @@ -5568,13 +5568,6 @@ NvBool nvSurfaceEvoInAnyOpens(const NVSurfaceEvoRec *pSurfaceEvo) } #endif -NVDevEvoPtr nvGetDevEvoFromOpenDev( - const struct NvKmsPerOpenDev *pOpenDev) -{ - nvAssert(pOpenDev != NULL); - return pOpenDev->pDevEvo; -} - const struct NvKmsFlipPermissions *nvGetFlipPermissionsFromOpenDev( const struct NvKmsPerOpenDev *pOpenDev) { diff --git a/src/nvidia/generated/g_gpu_nvoc.c b/src/nvidia/generated/g_gpu_nvoc.c index c03aa99f0..1494211ad 100644 --- a/src/nvidia/generated/g_gpu_nvoc.c +++ b/src/nvidia/generated/g_gpu_nvoc.c @@ -220,6 +220,7 @@ void __nvoc_init_dataField_OBJGPU(OBJGPU *pThis) { pThis->setProperty(pThis, PDB_PROP_GPU_SKIP_CE_MAPPINGS_NO_NVLINK, ((NvBool)(0 == 0))); } pThis->setProperty(pThis, PDB_PROP_GPU_OPTIMUS_GOLD_CFG_SPACE_RESTORE, ((NvBool)(0 == 0))); + pThis->setProperty(pThis, PDB_PROP_GPU_SRIOV_HEAVY_FORCE_INVALIDATE_ALL_PDBS_WAR_BUG3896322, ((NvBool)(0 != 0))); pThis->boardId = ~0; @@ -313,6 +314,17 @@ void __nvoc_init_dataField_OBJGPU(OBJGPU *pThis) { { pThis->bSriovCapable = ((NvBool)(0 == 0)); } + + // Hal field -- bEnableBar1SparseForFillPteMemUnmap + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ + { + pThis->bEnableBar1SparseForFillPteMemUnmap = ((NvBool)(0 == 0)); + } + // default + else + { + pThis->bEnableBar1SparseForFillPteMemUnmap = ((NvBool)(0 != 0)); + } } NV_STATUS __nvoc_ctor_Object(Object* ); diff --git a/src/nvidia/generated/g_gpu_nvoc.h b/src/nvidia/generated/g_gpu_nvoc.h index 8931cf8fa..9f9bfdc07 100644 --- a/src/nvidia/generated/g_gpu_nvoc.h +++ b/src/nvidia/generated/g_gpu_nvoc.h @@ -7,7 +7,7 @@ extern "C" { #endif /* - * SPDX-FileCopyrightText: Copyright (c) 2004-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2004-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -843,6 +843,7 @@ struct OBJGPU { NvBool PDB_PROP_GPU_IN_HIBERNATE; NvBool PDB_PROP_GPU_IN_PM_CODEPATH; NvBool PDB_PROP_GPU_IN_PM_RESUME_CODEPATH; + NvBool PDB_PROP_GPU_PM_RESUME_WAR_BUG_3936017_ENABLED; NvBool PDB_PROP_GPU_STATE_INITIALIZED; NvBool PDB_PROP_GPU_EMULATION; NvBool PDB_PROP_GPU_PRIMARY_DEVICE; @@ -918,6 +919,7 @@ struct OBJGPU { NvBool PDB_PROP_GPU_IS_MXM_3X; NvBool PDB_PROP_GPU_GSYNC_III_ATTACHED; NvBool PDB_PROP_GPU_QSYNC_II_ATTACHED; + NvBool PDB_PROP_GPU_SRIOV_HEAVY_FORCE_INVALIDATE_ALL_PDBS_WAR_BUG3896322; OS_GPU_INFO *pOsGpuInfo; OS_RM_CAPS *pOsRmCaps; NvU32 halImpl; @@ -1106,6 +1108,7 @@ struct OBJGPU { NvU8 fabricProbeSlowdownThreshold; NvBool bVgpuGspPluginOffloadEnabled; NvBool bSriovCapable; + NvBool bEnableBar1SparseForFillPteMemUnmap; }; #ifndef __NVOC_CLASS_OBJGPU_TYPEDEF__ @@ -1237,6 +1240,8 @@ extern const struct NVOC_CLASS_DEF __nvoc_class_def_OBJGPU; #define PDB_PROP_GPU_IS_BR03_PRESENT_BASE_NAME PDB_PROP_GPU_IS_BR03_PRESENT #define PDB_PROP_GPU_IS_GEMINI_BASE_CAST #define PDB_PROP_GPU_IS_GEMINI_BASE_NAME PDB_PROP_GPU_IS_GEMINI +#define PDB_PROP_GPU_SRIOV_HEAVY_FORCE_INVALIDATE_ALL_PDBS_WAR_BUG3896322_BASE_CAST +#define PDB_PROP_GPU_SRIOV_HEAVY_FORCE_INVALIDATE_ALL_PDBS_WAR_BUG3896322_BASE_NAME PDB_PROP_GPU_SRIOV_HEAVY_FORCE_INVALIDATE_ALL_PDBS_WAR_BUG3896322 #define PDB_PROP_GPU_STATE_INITIALIZED_BASE_CAST #define PDB_PROP_GPU_STATE_INITIALIZED_BASE_NAME PDB_PROP_GPU_STATE_INITIALIZED #define PDB_PROP_GPU_NV_USERMODE_ENABLED_BASE_CAST @@ -1261,12 +1266,14 @@ extern const struct NVOC_CLASS_DEF __nvoc_class_def_OBJGPU; #define PDB_PROP_GPU_UPSTREAM_PORT_L1_POR_SUPPORTED_BASE_NAME PDB_PROP_GPU_UPSTREAM_PORT_L1_POR_SUPPORTED #define PDB_PROP_GPU_ZERO_FB_BASE_CAST #define PDB_PROP_GPU_ZERO_FB_BASE_NAME PDB_PROP_GPU_ZERO_FB +#define PDB_PROP_GPU_PM_RESUME_WAR_BUG_3936017_ENABLED_BASE_CAST +#define PDB_PROP_GPU_PM_RESUME_WAR_BUG_3936017_ENABLED_BASE_NAME PDB_PROP_GPU_PM_RESUME_WAR_BUG_3936017_ENABLED #define PDB_PROP_GPU_SWRL_GRANULAR_LOCKING_BASE_CAST #define PDB_PROP_GPU_SWRL_GRANULAR_LOCKING_BASE_NAME PDB_PROP_GPU_SWRL_GRANULAR_LOCKING -#define PDB_PROP_GPU_SKIP_CE_MAPPINGS_NO_NVLINK_BASE_CAST -#define PDB_PROP_GPU_SKIP_CE_MAPPINGS_NO_NVLINK_BASE_NAME PDB_PROP_GPU_SKIP_CE_MAPPINGS_NO_NVLINK #define PDB_PROP_GPU_TEGRA_SOC_IGPU_BASE_CAST #define PDB_PROP_GPU_TEGRA_SOC_IGPU_BASE_NAME PDB_PROP_GPU_TEGRA_SOC_IGPU +#define PDB_PROP_GPU_SKIP_CE_MAPPINGS_NO_NVLINK_BASE_CAST +#define PDB_PROP_GPU_SKIP_CE_MAPPINGS_NO_NVLINK_BASE_NAME PDB_PROP_GPU_SKIP_CE_MAPPINGS_NO_NVLINK #define PDB_PROP_GPU_ATS_SUPPORTED_BASE_CAST #define PDB_PROP_GPU_ATS_SUPPORTED_BASE_NAME PDB_PROP_GPU_ATS_SUPPORTED #define PDB_PROP_GPU_EMULATION_BASE_CAST diff --git a/src/nvidia/generated/g_nv_name_released.h b/src/nvidia/generated/g_nv_name_released.h index 7ace7bb87..2d8420b85 100644 --- a/src/nvidia/generated/g_nv_name_released.h +++ b/src/nvidia/generated/g_nv_name_released.h @@ -918,6 +918,7 @@ static const CHIPS_RELEASED sChipsReleased[] = { { 0x24B9, 0x0000, 0x0000, "NVIDIA RTX A3000 12GB Laptop GPU" }, { 0x24BA, 0x0000, 0x0000, "NVIDIA RTX A4500 Laptop GPU" }, { 0x24BB, 0x0000, 0x0000, "NVIDIA RTX A3000 12GB Laptop GPU" }, + { 0x24C7, 0x0000, 0x0000, "NVIDIA GeForce RTX 3060" }, { 0x24C9, 0x0000, 0x0000, "NVIDIA GeForce RTX 3060 Ti" }, { 0x24DC, 0x0000, 0x0000, "NVIDIA GeForce RTX 3080 Laptop GPU" }, { 0x24DD, 0x0000, 0x0000, "NVIDIA GeForce RTX 3070 Laptop GPU" }, @@ -963,6 +964,8 @@ static const CHIPS_RELEASED sChipsReleased[] = { { 0x25B9, 0x0000, 0x0000, "NVIDIA RTX A1000 Laptop GPU" }, { 0x25BA, 0x0000, 0x0000, "NVIDIA RTX A2000 8GB Laptop GPU" }, { 0x25BB, 0x0000, 0x0000, "NVIDIA RTX A500 Laptop GPU" }, + { 0x25BC, 0x0000, 0x0000, "NVIDIA RTX A1000 6GB Laptop GPU" }, + { 0x25BD, 0x0000, 0x0000, "NVIDIA RTX A500 Laptop GPU" }, { 0x25E0, 0x0000, 0x0000, "NVIDIA GeForce RTX 3050 Ti Laptop GPU" }, { 0x25E2, 0x0000, 0x0000, "NVIDIA GeForce RTX 3050 Laptop GPU" }, { 0x25E5, 0x0000, 0x0000, "NVIDIA GeForce RTX 3050 Laptop GPU" }, @@ -980,8 +983,10 @@ static const CHIPS_RELEASED sChipsReleased[] = { { 0x26B5, 0x17da, 0x10de, "NVIDIA L40" }, { 0x2704, 0x0000, 0x0000, "NVIDIA GeForce RTX 4080" }, { 0x2717, 0x0000, 0x0000, "NVIDIA GeForce RTX 4090 Laptop GPU" }, + { 0x2730, 0x0000, 0x0000, "NVIDIA RTX 5000 Ada Generation Laptop GPU" }, { 0x2757, 0x0000, 0x0000, "NVIDIA GeForce RTX 4090 Laptop GPU" }, { 0x2782, 0x0000, 0x0000, "NVIDIA GeForce RTX 4070 Ti" }, + { 0x2786, 0x0000, 0x0000, "NVIDIA GeForce RTX 4070" }, { 0x27A0, 0x0000, 0x0000, "NVIDIA GeForce RTX 4080 Laptop GPU" }, { 0x27B0, 0x16fa, 0x1028, "NVIDIA RTX 4000 SFF Ada Generation" }, { 0x27B0, 0x16fa, 0x103c, "NVIDIA RTX 4000 SFF Ada Generation" }, @@ -989,11 +994,15 @@ static const CHIPS_RELEASED sChipsReleased[] = { { 0x27B0, 0x16fa, 0x17aa, "NVIDIA RTX 4000 SFF Ada Generation" }, { 0x27B8, 0x16ca, 0x10de, "NVIDIA L4" }, { 0x27B8, 0x16ee, 0x10de, "NVIDIA L4" }, + { 0x27BA, 0x0000, 0x0000, "NVIDIA RTX 4000 Ada Generation Laptop GPU" }, + { 0x27BB, 0x0000, 0x0000, "NVIDIA RTX 3500 Ada Generation Laptop GPU" }, { 0x27E0, 0x0000, 0x0000, "NVIDIA GeForce RTX 4080 Laptop GPU" }, { 0x2820, 0x0000, 0x0000, "NVIDIA GeForce RTX 4070 Laptop GPU" }, + { 0x2838, 0x0000, 0x0000, "NVIDIA RTX 3000 Ada Generation Laptop GPU" }, { 0x2860, 0x0000, 0x0000, "NVIDIA GeForce RTX 4070 Laptop GPU" }, { 0x28A0, 0x0000, 0x0000, "NVIDIA GeForce RTX 4060 Laptop GPU" }, { 0x28A1, 0x0000, 0x0000, "NVIDIA GeForce RTX 4050 Laptop GPU" }, + { 0x28B8, 0x0000, 0x0000, "NVIDIA RTX 2000 Ada Generation Laptop GPU" }, { 0x28E0, 0x0000, 0x0000, "NVIDIA GeForce RTX 4060 Laptop GPU" }, { 0x28E1, 0x0000, 0x0000, "NVIDIA GeForce RTX 4050 Laptop GPU" }, { 0x13BD, 0x11cc, 0x10DE, "GRID M10-0B" }, diff --git a/src/nvidia/generated/g_system_nvoc.h b/src/nvidia/generated/g_system_nvoc.h index f309b2c27..b9e73385d 100644 --- a/src/nvidia/generated/g_system_nvoc.h +++ b/src/nvidia/generated/g_system_nvoc.h @@ -7,7 +7,7 @@ extern "C" { #endif /* - * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -322,6 +322,16 @@ typedef struct SYS_STATIC_CONFIG NvBool bOsSevEnabled; } SYS_STATIC_CONFIG; +typedef enum +{ + CPU_VENDOR_UNKNOWN = 0, + CPU_VENDOR_INTEL, + CPU_VENDOR_AMD, + CPU_VENDOR_WINCHIP, + CPU_VENDOR_CYRIX, + CPU_VENDOR_TRANSM +} CPU_VENDOR; + typedef struct { NvBool bInitialized; // Set to true once we id the CPU @@ -340,6 +350,7 @@ typedef struct // filled in if CPU has embedded name NvU32 family; // Vendor defined Family/extended Family NvU32 model; // Vendor defined Model/extended Model + NvU8 vendor; // Vendor CPU_VENDOR NvU32 coresOnDie; // # of cores on the die (0 if unknown) NvU32 platformID; // Chip package type NvU8 stepping; // Silicon stepping diff --git a/src/nvidia/src/kernel/gpu/bus/arch/maxwell/kern_bus_gm107.c b/src/nvidia/src/kernel/gpu/bus/arch/maxwell/kern_bus_gm107.c index 7c7c50fe3..ccb56721a 100644 --- a/src/nvidia/src/kernel/gpu/bus/arch/maxwell/kern_bus_gm107.c +++ b/src/nvidia/src/kernel/gpu/bus/arch/maxwell/kern_bus_gm107.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2004-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2004-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a diff --git a/src/nvidia/src/kernel/gpu/gr/kernel_graphics_context.c b/src/nvidia/src/kernel/gpu/gr/kernel_graphics_context.c index cebaa508a..082d1342a 100644 --- a/src/nvidia/src/kernel/gpu/gr/kernel_graphics_context.c +++ b/src/nvidia/src/kernel/gpu/gr/kernel_graphics_context.c @@ -2310,7 +2310,6 @@ kgrctxIsFinalGlobalBufMapRefDuped_IMPL } return NV_FALSE; } - /** * @brief Unmap associated ctx buffers (main, patch, global buffers etc). * @@ -3071,7 +3070,6 @@ kgrctxIncObjectCount_IMPL NV_ASSERT_OK_OR_ELSE(status, kgrctxGetUnicast(pGpu, pKernelGraphicsContext, &pKernelGraphicsContextUnicast), return;); - switch (objType) { case GR_OBJECT_TYPE_COMPUTE: @@ -3584,4 +3582,3 @@ void shrkgrctxDetach_IMPL SLI_LOOP_END; } } - diff --git a/src/nvidia/src/kernel/gpu/mem_mgr/arch/maxwell/virt_mem_allocator_gm107.c b/src/nvidia/src/kernel/gpu/mem_mgr/arch/maxwell/virt_mem_allocator_gm107.c index 7d5197968..4646a0a27 100644 --- a/src/nvidia/src/kernel/gpu/mem_mgr/arch/maxwell/virt_mem_allocator_gm107.c +++ b/src/nvidia/src/kernel/gpu/mem_mgr/arch/maxwell/virt_mem_allocator_gm107.c @@ -1622,9 +1622,7 @@ dmaUpdateVASpace_GF100 NvU32 alignSize = pMemorySystemConfig->comprPageSize; KernelGmmu *pKernelGmmu = GPU_GET_KERNEL_GMMU(pGpu); NvBool bFillPteMem = !!(flags & DMA_UPDATE_VASPACE_FLAGS_FILL_PTE_MEM); - NvBool bUnmap = !bFillPteMem && - (flags & DMA_UPDATE_VASPACE_FLAGS_UPDATE_VALID) && - (SF_VAL(_MMU, _PTE_VALID, valid) == NV_MMU_PTE_VALID_FALSE); + NvBool bUnmap; NvBool bIsIndirectPeer; VAS_PTE_UPDATE_TYPE update_type; @@ -1635,6 +1633,17 @@ dmaUpdateVASpace_GF100 readDisable = !!(flags & DMA_UPDATE_VASPACE_FLAGS_SHADER_WRITE_ONLY); bIsIndirectPeer = !!(flags & DMA_UPDATE_VASPACE_FLAGS_INDIRECT_PEER); + if (pGpu->bEnableBar1SparseForFillPteMemUnmap) + { + bUnmap = (flags & DMA_UPDATE_VASPACE_FLAGS_UPDATE_VALID) && + (SF_VAL(_MMU, _PTE_VALID, valid) == NV_MMU_PTE_VALID_FALSE); + } + else + { + bUnmap = !bFillPteMem && + (flags & DMA_UPDATE_VASPACE_FLAGS_UPDATE_VALID) && + (SF_VAL(_MMU, _PTE_VALID, valid) == NV_MMU_PTE_VALID_FALSE); + } // // Determine whether we are invalidating or revoking privileges, so we know // whether to flush page accesses or not. ReadDisable and writeDisable have diff --git a/src/nvidia/src/kernel/gpu/mmu/arch/ampere/kern_gmmu_ga100.c b/src/nvidia/src/kernel/gpu/mmu/arch/ampere/kern_gmmu_ga100.c index a6abc17fb..805fa08ee 100644 --- a/src/nvidia/src/kernel/gpu/mmu/arch/ampere/kern_gmmu_ga100.c +++ b/src/nvidia/src/kernel/gpu/mmu/arch/ampere/kern_gmmu_ga100.c @@ -91,6 +91,7 @@ kgmmuValidateFabricBaseAddress_GA100 OBJGPU *pGpu = ENG_GET_GPU(pKernelGmmu); MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); NvU64 fbSizeBytes; + NvU64 fbUpperLimit; fbSizeBytes = pMemoryManager->Ram.fbTotalMemSizeMb << 20; @@ -109,8 +110,10 @@ kgmmuValidateFabricBaseAddress_GA100 // Align fbSize to mapslot size. fbSizeBytes = RM_ALIGN_UP(fbSizeBytes, NVBIT64(36)); + fbUpperLimit = fabricBaseAddr + fbSizeBytes; + // Make sure the address range doesn't go beyond the limit, (2K * 64GB). - if ((fabricBaseAddr + fbSizeBytes) > NVBIT64(47)) + if (fbUpperLimit > NVBIT64(47)) { return NV_ERR_INVALID_ARGUMENT; } diff --git a/src/nvidia/src/kernel/gpu/mmu/arch/maxwell/kern_gmmu_gm107.c b/src/nvidia/src/kernel/gpu/mmu/arch/maxwell/kern_gmmu_gm107.c index 478f61930..a18353287 100644 --- a/src/nvidia/src/kernel/gpu/mmu/arch/maxwell/kern_gmmu_gm107.c +++ b/src/nvidia/src/kernel/gpu/mmu/arch/maxwell/kern_gmmu_gm107.c @@ -133,7 +133,7 @@ kgmmuInvalidateTlb_GM107 // Not using range-based invalidate. params.regVal = FLD_SET_DRF(_PFB_PRI, _MMU_INVALIDATE, _ALL_VA, _TRUE, params.regVal); - if (NULL != pRootPageDir) + if ((NULL != pRootPageDir) && !pGpu->getProperty(pGpu, PDB_PROP_GPU_SRIOV_HEAVY_FORCE_INVALIDATE_ALL_PDBS_WAR_BUG3896322)) { // Invalidatating only one VAS. params.regVal = FLD_SET_DRF(_PFB_PRI, _MMU_INVALIDATE, _ALL_PDB, _FALSE, params.regVal); diff --git a/src/nvidia/src/kernel/gpu/nvlink/arch/volta/kernel_nvlink_gv100.c b/src/nvidia/src/kernel/gpu/nvlink/arch/volta/kernel_nvlink_gv100.c index 1db8e82f6..e5091dc28 100644 --- a/src/nvidia/src/kernel/gpu/nvlink/arch/volta/kernel_nvlink_gv100.c +++ b/src/nvidia/src/kernel/gpu/nvlink/arch/volta/kernel_nvlink_gv100.c @@ -500,6 +500,7 @@ knvlinkValidateFabricBaseAddress_GV100 { MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); NvU64 fbSizeBytes; + NvU64 fbUpperLimit; fbSizeBytes = pMemoryManager->Ram.fbTotalMemSizeMb << 20; @@ -518,8 +519,10 @@ knvlinkValidateFabricBaseAddress_GV100 // Align fbSize to mapslot size. fbSizeBytes = RM_ALIGN_UP(fbSizeBytes, NVBIT64(34)); + fbUpperLimit = fabricBaseAddr + fbSizeBytes; + // Make sure the address range doesn't go beyond the limit, (8K * 16GB). - if ((fabricBaseAddr + fbSizeBytes) > NVBIT64(47)) + if (fbUpperLimit > NVBIT64(47)) { return NV_ERR_INVALID_ARGUMENT; } diff --git a/src/nvidia/src/kernel/platform/cpu.c b/src/nvidia/src/kernel/platform/cpu.c index 7c30a5bd8..d783d6d41 100644 --- a/src/nvidia/src/kernel/platform/cpu.c +++ b/src/nvidia/src/kernel/platform/cpu.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2014-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2014-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -749,16 +749,31 @@ void RmInitCpuInfo(void) getEmbeddedProcessorName(pSys->cpuInfo.name, sizeof(pSys->cpuInfo.name)); if (IS_INTEL(cpuinfo.Foundry)) + { cpuidInfoIntel(pSys, &cpuinfo); + pSys->cpuInfo.vendor = CPU_VENDOR_INTEL; + } else if (IS_AMD(cpuinfo.Foundry)) + { cpuidInfoAMD(pSys, &cpuinfo); + pSys->cpuInfo.vendor = CPU_VENDOR_AMD; + } #if defined(_M_IX86) || defined(NVCPU_X86) else if (IS_WINCHIP(cpuinfo.Foundry)) + { cpuidInfoWinChip(pSys, &cpuinfo); + pSys->cpuInfo.vendor = CPU_VENDOR_WINCHIP; + } else if (IS_CYRIX(cpuinfo.Foundry)) + { cpuidInfoCyrix(pSys, &cpuinfo); + pSys->cpuInfo.vendor = CPU_VENDOR_CYRIX; + } else if (IS_TRANSM(cpuinfo.Foundry)) + { cpuidInfoTransmeta(pSys, &cpuinfo); + pSys->cpuInfo.vendor = CPU_VENDOR_TRANSM; + } #endif else { diff --git a/src/nvidia/src/libraries/resserv/src/rs_client.c b/src/nvidia/src/libraries/resserv/src/rs_client.c index a8a02b035..efa1301b6 100644 --- a/src/nvidia/src/libraries/resserv/src/rs_client.c +++ b/src/nvidia/src/libraries/resserv/src/rs_client.c @@ -591,6 +591,50 @@ clientCopyResource_IMPL return _clientAllocResourceHelper(pClient, pServer, ¶ms, &pParams->hResourceDst); } +static +void +_refCleanupDependencies +( + RsResourceRef *pResourceRef +) +{ + RsResourceRef **ppIndepRef; + while (NULL != (ppIndepRef = multimapFirstItem(&pResourceRef->depBackRefMap))) + { + refRemoveDependant(*ppIndepRef, pResourceRef); + } +} + +static +void +_refCleanupDependants +( + RsResourceRef *pResourceRef +) +{ + RsResourceRef **ppDepRef; + while (NULL != (ppDepRef = multimapFirstItem(&pResourceRef->depRefMap))) + { + refRemoveDependant(pResourceRef, *ppDepRef); + } +} + +static +void +_refRemoveAllDependencies +( + RsResourceRef *pResourceRef +) +{ + _refCleanupDependencies(pResourceRef); + + if (pResourceRef->pDependantSession != NULL) + sessionRemoveDependency(pResourceRef->pDependantSession, pResourceRef); + + if (pResourceRef->pSession != NULL) + sessionRemoveDependant(pResourceRef->pSession, pResourceRef); +} + static NV_STATUS _clientAllocResourceHelper @@ -693,11 +737,7 @@ fail: pOldContext = NULL; // First undo dependency tracking since it might access the resource - if (pResourceRef->pDependantSession != NULL) - sessionRemoveDependency(pResourceRef->pDependantSession, pResourceRef); - - if (pResourceRef->pSession != NULL) - sessionRemoveDependant(pResourceRef->pSession, pResourceRef); + _refRemoveAllDependencies(pResourceRef); portMemSet(¶ms, 0, sizeof(params)); portMemSet(&callContext, 0, sizeof(callContext)); @@ -727,38 +767,6 @@ fail: return status; } -static -NV_STATUS -_refCleanupDependencies -( - RsResourceRef *pResourceRef -) -{ - RsResourceRef **ppIndepRef; - while (NULL != (ppIndepRef = multimapFirstItem(&pResourceRef->depBackRefMap))) - { - refRemoveDependant(*ppIndepRef, pResourceRef); - } - - return NV_OK; -} - -static -NV_STATUS -_refCleanupDependants -( - RsResourceRef *pResourceRef -) -{ - RsResourceRef **ppDepRef; - while (NULL != (ppDepRef = multimapFirstItem(&pResourceRef->depRefMap))) - { - refRemoveDependant(pResourceRef, *ppDepRef); - } - - return NV_OK; -} - NV_STATUS clientFreeResource_IMPL ( @@ -814,13 +822,7 @@ clientFreeResource_IMPL // Remove this resource as a dependency from other resources pResourceRef->bInvalidated = NV_TRUE; - _refCleanupDependencies(pResourceRef); - - if (pResourceRef->pDependantSession != NULL) - sessionRemoveDependency(pResourceRef->pDependantSession, pResourceRef); - - if (pResourceRef->pSession != NULL) - sessionRemoveDependant(pResourceRef->pSession, pResourceRef); + _refRemoveAllDependencies(pResourceRef); status = serverFreeResourceRpcUnderLock(pServer, pParams); NV_ASSERT(status == NV_OK); diff --git a/version.mk b/version.mk index e0a7d27ac..a2242a51c 100644 --- a/version.mk +++ b/version.mk @@ -1,4 +1,4 @@ -NVIDIA_VERSION = 525.105.17 +NVIDIA_VERSION = 525.116.03 # This file. VERSION_MK_FILE := $(lastword $(MAKEFILE_LIST))