NVIDIA/open-gpu-kernel-modules
1
0
Fork 0
mirror of https://github.com/NVIDIA/open-gpu-kernel-modules.git synced 2026-01-30 04:59:46 +00:00
Code Issues Packages Projects Releases Wiki Activity

580.94.13

Browse Source
This commit is contained in:
russellcnv
2025-12-18 14:38:12 -08:00
parent 58a0f49bed
commit a3af2867b7
94 changed files with 77091 additions and 74546 deletions
Download Patch File Download Diff File Expand all files Collapse all files

7
src/common/displayport/inc/dp_configcaps.h
View File

@@ -552,7 +552,7 @@ namespace DisplayPort
virtual bool readPrSinkDebugInfo(panelReplaySinkDebugInfo *prDbgInfo) = 0;
virtual bool isDpInTunnelingSupported() = 0;
virtual void enableDpTunnelingBwAllocationSupport() = 0;
virtual void setDpTunnelingBwAllocationSupport(bool bEnable) = 0;
virtual bool isDpTunnelBwAllocationEnabled() = 0;
virtual bool getDpTunnelEstimatedBw(NvU8 &estimatedBw) = 0;
virtual bool getDpTunnelGranularityMultiplier(NvU8 &granularityMultiplier) = 0;
@@ -1474,10 +1474,9 @@ namespace DisplayPort
{
return caps.dpInTunnelingCaps.bIsSupported;
}
virtual void enableDpTunnelingBwAllocationSupport()
virtual void setDpTunnelingBwAllocationSupport(bool bEnable)
{
bEnableDpTunnelBwAllocationSupport = true;
bEnableDpTunnelBwAllocationSupport = bEnable;
}
virtual bool isDpTunnelBwAllocationEnabled()

5
src/common/displayport/inc/dp_connectorimpl.h
View File

@@ -363,7 +363,9 @@ namespace DisplayPort
bool bForceHeadShutdownPerMonitor;
//
// Use max DSC compression for MST topologies
bool bUseMaxDSCCompressionMST;
// Dual SST Partner connector object pointer
ConnectorImpl *pCoupledConnector;
@@ -632,6 +634,7 @@ namespace DisplayPort
bool allocateMaxDpTunnelBw();
NvU64 getMaxTunnelBw();
void enableDpTunnelingBwAllocationSupport();
void cancelDpTunnelBwAllocation();
void assessLink(LinkTrainingType trainType = NORMAL_LINK_TRAINING);

3
src/common/displayport/inc/dp_regkeydatabase.h
View File

@@ -100,6 +100,8 @@
// Bug 5088957 : Force head shutdown in DpLib
#define NV_DP_REGKEY_FORCE_HEAD_SHUTDOWN "DP_WAR_5088957"
// Use max DSC compression for MST topologies
#define NV_DP_REGKEY_USE_MAX_DSC_COMPRESSION_MST "DP_USE_MAX_DSC_COMPRESSION_MST"
// This regkey forces devID to be exposed to vendors via DPCD 0x309 for DSC-enabled SKUs.
#define NV_DP_REGKEY_EXPOSE_DSC_DEVID_WAR "DP_DSC_DEVID_WAR"
@@ -157,6 +159,7 @@ struct DP_REGKEY_DATABASE
bool bHDMIOnDPPlusPlus;
bool bIgnoreCapsAndForceHighestLc;
bool bOptimizeDscBppForTunnellingBw;
bool bUseMaxDSCCompressionMST;
};
extern struct DP_REGKEY_DATABASE dpRegkeyDatabase;

56
src/common/displayport/src/dp_connectorimpl.cpp
View File

@@ -196,7 +196,8 @@ void ConnectorImpl::applyRegkeyOverrides(const DP_REGKEY_DATABASE& dpRegkeyDatab
this->bSkipZeroOuiCache = dpRegkeyDatabase.bSkipZeroOuiCache;
this->bForceHeadShutdownFromRegkey = dpRegkeyDatabase.bForceHeadShutdown;
this->bEnableDevId = dpRegkeyDatabase.bEnableDevId;
this->bIgnoreCapsAndForceHighestLc = dpRegkeyDatabase.bIgnoreCapsAndForceHighestLc;
this->bIgnoreCapsAndForceHighestLc = dpRegkeyDatabase.bIgnoreCapsAndForceHighestLc;
this->bUseMaxDSCCompressionMST = dpRegkeyDatabase.bUseMaxDSCCompressionMST;
this->bDisableEffBppSST8b10b = dpRegkeyDatabase.bDisableEffBppSST8b10b;
this->bHDMIOnDPPlusPlus = dpRegkeyDatabase.bHDMIOnDPPlusPlus;
this->bOptimizeDscBppForTunnellingBw = dpRegkeyDatabase.bOptimizeDscBppForTunnellingBw;
@@ -1492,11 +1493,19 @@ bool ConnectorImpl::compoundQueryAttachMSTDsc(Group * target,
if (!pDscParams->bitsPerPixelX16)
{
//
// For now, we will keep a pre defined value for bitsPerPixel for MST = 10
// bitsPerPixelX16 = 160
//
pDscParams->bitsPerPixelX16 = PREDEFINED_DSC_MST_BPPX16;
if (this->bUseMaxDSCCompressionMST)
{
//do max dsc compression so that the desired mode can be supported
pDscParams->bitsPerPixelX16 = MAX_DSC_COMPRESSION_BPPX16;
}
else
{
//
// For now, we will keep a pre defined value for bitsPerPixel for MST = 10
// bitsPerPixelX16 = 160
//
pDscParams->bitsPerPixelX16 = PREDEFINED_DSC_MST_BPPX16;
}
}
else
{
@@ -4175,7 +4184,7 @@ void ConnectorImpl::enableDpTunnelingBwAllocationSupport()
return;
}
hal->enableDpTunnelingBwAllocationSupport();
hal->setDpTunnelingBwAllocationSupport(true);
}
/*!
@@ -4189,6 +4198,31 @@ NvU64 ConnectorImpl::getMaxTunnelBw()
return highestAssessedLC.getTotalDataRate() * 8;
}
/*!
* @brief Function to cancel the tunnel bw allocation.
* This function is called when the tunneling chip does not respond to the initial or fallback BW request
* This function also re-assesses the link to get the updated link config
*/
void ConnectorImpl::cancelDpTunnelBwAllocation()
{
LinkConfiguration _origHighestAssessedLC = highestAssessedLC;
hal->setDpTunnelBwAllocation(false);
hal->setDpTunnelingBwAllocationSupport(false);
hal->notifyHPD(true, false);
assessLink();
if (highestAssessedLC != _origHighestAssessedLC)
{
for (Device *i = enumDevices(0); i; i = enumDevices(i))
{
DeviceImpl *dev = (DeviceImpl *)i;
if ((dev->activeGroup != NULL) && (dev->plugged))
{
sink->bandwidthChangeNotification(dev, false);
}
}
}
}
/*!
* @brief Allocate the requested Tunnel BW
*
@@ -4248,7 +4282,8 @@ bool ConnectorImpl::allocateDpTunnelBw(NvU64 bandwidth)
// This shouldn't be Indeterminate. The request can succeed or fail. Indeterminate means something else went wrong
if (requestStatus == Indeterminate)
{
DP_PRINTF(DP_ERROR, "Tunneling chip didn't reply for the BW request\n");
DP_PRINTF(DP_ERROR, "Tunneling chip didn't reply for the initial BW request, cancel tunnel bw allocation support");
cancelDpTunnelBwAllocation();
return false;
}
@@ -4276,6 +4311,8 @@ bool ConnectorImpl::allocateDpTunnelBw(NvU64 bandwidth)
//
if (requestStatus == Indeterminate)
{
DP_PRINTF(DP_ERROR, "Tunneling chip didn't reply for the fallback BW request, cancel tunnel bw allocation support");
cancelDpTunnelBwAllocation();
return false;
}
}
@@ -5123,9 +5160,10 @@ bool ConnectorImpl::trainLinkOptimized(LinkConfiguration lConfig)
}
}
if (bPConConnected)
if (bPConConnected || bKeepOptLinkAlive)
{
// When PCON is connected, always LT to max to avoid LT.
// When bKeepOptLinkAlive is set, we need to LT to max to avoid LT.
bSkipLowestConfigCheck = true;
}

3
src/common/displayport/src/dp_connectorimpl2x.cpp
View File

@@ -110,6 +110,9 @@ bool ConnectorImpl2x::getValidLowestLinkConfig
{
// Get next entry.
lowestSelected = this->allPossibleLinkCfgs[i+1];
// Update enhancedFraming/bDisableDownspread/bEnableFEC for target config
lowestSelected.enhancedFraming = lConfig.enhancedFraming;
lowestSelected.bDisableDownspread = lConfig.bDisableDownspread;
lowestSelected.enableFEC(lConfig.bEnableFEC);
}
}

5
src/common/displayport/src/dp_deviceimpl.cpp
View File

@@ -3306,6 +3306,8 @@ bool DeviceImpl::setModeList(DisplayPort::DpModesetParams *modeList, unsigned nu
maxModeBwRequired = 0;
DP_PRINTF(DP_NOTICE, "DP-DEV> setModeList: numModes: %d", numModes);
for (unsigned modeItr = 0; modeItr < numModes; modeItr++)
{
connector->beginCompoundQuery();
@@ -3335,9 +3337,8 @@ bool DeviceImpl::setModeList(DisplayPort::DpModesetParams *modeList, unsigned nu
DP_PRINTF(DP_INFO, "Computed Max mode BW: %" NvU64_fmtu " Mbps", maxModeBwRequired / (1000 * 1000));
connector->updateDpTunnelBwAllocation();
return connector->updateDpTunnelBwAllocation();
return true;
}
void

3
src/common/displayport/src/dp_evoadapter.cpp
View File

@@ -110,7 +110,8 @@ const struct
{NV_DP_REGKEY_EXPOSE_DSC_DEVID_WAR, &dpRegkeyDatabase.bEnableDevId, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_HDMI_ON_DP_PLUS_PLUS, &dpRegkeyDatabase.bHDMIOnDPPlusPlus, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_IGNORE_CAPS_AND_FORCE_HIGHEST_LC, &dpRegkeyDatabase.bIgnoreCapsAndForceHighestLc, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_OPTIMIZE_DSC_BPP_FOR_TUNNELLING_BW, &dpRegkeyDatabase.bOptimizeDscBppForTunnellingBw, DP_REG_VAL_BOOL}
{NV_DP_REGKEY_OPTIMIZE_DSC_BPP_FOR_TUNNELLING_BW, &dpRegkeyDatabase.bOptimizeDscBppForTunnellingBw, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_USE_MAX_DSC_COMPRESSION_MST, &dpRegkeyDatabase.bUseMaxDSCCompressionMST, DP_REG_VAL_BOOL}
};
EvoMainLink::EvoMainLink(EvoInterface * provider, Timer * timer) :

16
src/common/inc/nvBldVer.h
View File

@@ -43,18 +43,18 @@
#endif
#if defined(NV_LINUX) || defined(NV_BSD) || defined(NV_SUNOS)
#define NV_BUILD_BRANCH_VERSION "rel/gpu_drv/r580/VK580_65-187"
#define NV_BUILD_CHANGELIST_NUM (36921184)
#define NV_BUILD_BRANCH_VERSION "rel/gpu_drv/r580/VK580_65-189"
#define NV_BUILD_CHANGELIST_NUM (37068878)
#define NV_BUILD_TYPE "Official"
#define NV_BUILD_NAME "rel/gpu_drv/r580/VK580_65-187"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (36921184)
#define NV_BUILD_NAME "rel/gpu_drv/r580/VK580_65-189"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (37068878)
#else /* Windows builds */
#define NV_BUILD_BRANCH_VERSION "VK580_65-13"
#define NV_BUILD_CHANGELIST_NUM (36921184)
#define NV_BUILD_BRANCH_VERSION "VK580_65-15"
#define NV_BUILD_CHANGELIST_NUM (37068878)
#define NV_BUILD_TYPE "Official"
#define NV_BUILD_NAME "581.96"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (36921184)
#define NV_BUILD_NAME "582.15"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (37068878)
#define NV_BUILD_BRANCH_BASE_VERSION R580
#endif
// End buildmeister python edited section

2
src/common/inc/nvUnixVersion.h
View File

@@ -4,7 +4,7 @@
#if defined(NV_LINUX) || defined(NV_BSD) || defined(NV_SUNOS) || defined(NV_VMWARE) || defined(NV_QNX) || defined(NV_INTEGRITY) || \
(defined(RMCFG_FEATURE_PLATFORM_GSP) && RMCFG_FEATURE_PLATFORM_GSP == 1)
#define NV_VERSION_STRING "580.94.11"
#define NV_VERSION_STRING "580.94.13"
#else

3
src/common/inc/nv_smg.h
View File

@@ -29,6 +29,8 @@ extern "C" {
#include "nvtypes.h"
#include "nvlimits.h"
#include "nvgputypes.h"
#include "nvctassert.h"
#include "nvrmcontext.h"
#include "nv_mig_types.h"
@@ -69,6 +71,7 @@ typedef struct nvMIGDeviceDescriptionRec {
NvBool migAccessOk;
/* MIG exec partition UUID string */
char migUuid[NV_MIG_DEVICE_UUID_STR_LENGTH];
NvU8 migUuidBin[NV_GPU_UUID_LEN];
} nvMIGDeviceDescription;
NvBool nvSMGSubscribeSubDevToPartition(nvRMContextPtr rmctx,

23
src/common/inc/swref/published/ampere/ga102/dev_riscv_pri.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2024 NVIDIA CORPORATION & AFFILIATES
* SPDX-FileCopyrightText: Copyright (c) 2003-2025 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -27,10 +27,31 @@
#define NV_FALCON2_GSP_BASE 0x00111000
#define NV_PRISCV_RISCV_IRQMASK 0x00000528 /* R-I4R */
#define NV_PRISCV_RISCV_IRQDEST 0x0000052c /* RW-4R */
#define NV_PRISCV_RISCV_IRQDELEG 0x00000534 /* RWI4R */
#define NV_PRISCV_RISCV_RPC 0x000003ec /* R--4R */
#define NV_PRISCV_RISCV_CPUCTL 0x00000388 /* RWI4R */
#define NV_PRISCV_RISCV_CPUCTL_ACTIVE_STAT 7:7 /* R-IVF */
#define NV_PRISCV_RISCV_CPUCTL_ACTIVE_STAT_ACTIVE 0x00000001 /* R---V */
#define NV_PRISCV_RISCV_CPUCTL_HALTED 4:4 /* R-IVF */
#define NV_PRISCV_RISCV_ICD_CMD 0x000003d0 /* RW-4R */
#define NV_PRISCV_RISCV_ICD_ADDR0 0x000003d4 /* RW-4R */
#define NV_PRISCV_RISCV_ICD_ADDR1 0x000003d8 /* RW-4R */
#define NV_PRISCV_RISCV_ICD_RDATA0 0x000003e4 /* R--4R */
#define NV_PRISCV_RISCV_ICD_RDATA1 0x000003e8 /* R--4R */
#define NV_PRISCV_RISCV_TRACECTL 0x00000400 /* RW-4R */
#define NV_PRISCV_RISCV_TRACECTL_FULL 30:30 /* RWIVF */
#define NV_PRISCV_RISCV_TRACE_RDIDX 0x00000404 /* RW-4R */
#define NV_PRISCV_RISCV_TRACE_RDIDX_RDIDX 7:0 /* RWIVF */
#define NV_PRISCV_RISCV_TRACE_RDIDX_MAXIDX 23:16 /* R-IVF */
#define NV_PRISCV_RISCV_TRACE_WTIDX 0x00000408 /* RW-4R */
#define NV_PRISCV_RISCV_TRACE_WTIDX_WTIDX 31:24 /* RWIVF */
#define NV_PRISCV_RISCV_TRACEPC_HI 0x00000410 /* RW-4R */
#define NV_PRISCV_RISCV_TRACEPC_LO 0x0000040c /* RW-4R */
#define NV_PRISCV_RISCV_PRIV_ERR_STAT 0x00000500 /* RWI4R */
#define NV_PRISCV_RISCV_PRIV_ERR_INFO 0x00000504 /* R-I4R */
#define NV_PRISCV_RISCV_PRIV_ERR_ADDR 0x00000508 /* R-I4R */
#define NV_PRISCV_RISCV_PRIV_ERR_ADDR_HI 0x0000050c /* R-I4R */
#define NV_PRISCV_RISCV_HUB_ERR_STAT 0x00000510 /* RWI4R */
#define NV_PRISCV_RISCV_BCR_CTRL 0x00000668 /* RWI4R */
#define NV_PRISCV_RISCV_BCR_CTRL_VALID 0:0 /* R-IVF */
#define NV_PRISCV_RISCV_BCR_CTRL_VALID_TRUE 0x00000001 /* R---V */

38
src/common/inc/swref/published/blackwell/gb202/dev_riscv_pri.h Normal file
View File

@@ -0,0 +1,38 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2025 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gb202_dev_riscv_pri_h__
#define __gb202_dev_riscv_pri_h__
#define NV_PRISCV_RISCV_CPUCTL 0x00000388 /* RW-4R */
#define NV_PRISCV_RISCV_RPC 0x000003ec /* R--4R */
#define NV_PRISCV_RISCV_IRQDELEG 0x00000534 /* RW-4R */
#define NV_PRISCV_RISCV_IRQDEST 0x0000052c /* RW-4R */
#define NV_PRISCV_RISCV_IRQMASK 0x00000528 /* R--4R */
#define NV_PRISCV_RISCV_PRIV_ERR_STAT 0x00000420 /* RW-4R */
#define NV_PRISCV_RISCV_PRIV_ERR_INFO 0x00000424 /* R--4R */
#define NV_PRISCV_RISCV_PRIV_ERR_ADDR 0x00000428 /* R--4R */
#define NV_PRISCV_RISCV_PRIV_ERR_ADDR_HI 0x0000042c /* R--4R */
#define NV_PRISCV_RISCV_HUB_ERR_STAT 0x00000430 /* RW-4R */
#endif // __gb202_dev_riscv_pri_h__

23
src/common/inc/swref/published/hopper/gh100/dev_fb.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES
* SPDX-FileCopyrightText: Copyright (c) 2003-2025 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -30,4 +30,25 @@
#define NV_PFB_FBHUB_PCIE_FLUSH_SYSMEM_ADDR_HI_ADR 31:0 /* RWIVF */
#define NV_PFB_FBHUB_PCIE_FLUSH_SYSMEM_ADDR_HI_ADR_MASK 0x000FFFFF /* ----V */
#define NV_PFB_PRI_MMU_WPR1_ADDR_LO 0x001FA81C /* RW-4R */
#define NV_PFB_PRI_MMU_WPR1_ADDR_LO__PRIV_LEVEL_MASK 0x001FA7CC /* */
#define NV_PFB_PRI_MMU_WPR1_ADDR_LO_VAL 31:4 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR1_ADDR_LO_VAL_INIT 0x0fffffff /* RWE-V */
#define NV_PFB_PRI_MMU_WPR1_ADDR_LO_ALIGNMENT 0x0000000c /* */
#define NV_PFB_PRI_MMU_WPR1_ADDR_HI 0x001FA820 /* RW-4R */
#define NV_PFB_PRI_MMU_WPR1_ADDR_HI__PRIV_LEVEL_MASK 0x001FA7CC /* */
#define NV_PFB_PRI_MMU_WPR1_ADDR_HI_VAL 31:4 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR1_ADDR_HI_VAL_INIT 0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_WPR1_ADDR_HI_ALIGNMENT 0x0000000c /* */
#define NV_PFB_PRI_MMU_WPR2_ADDR_LO 0x001FA824 /* RW-4R */
#define NV_PFB_PRI_MMU_WPR2_ADDR_LO__PRIV_LEVEL_MASK 0x001FA7CC /* */
#define NV_PFB_PRI_MMU_WPR2_ADDR_LO_VAL 31:4 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR2_ADDR_LO_VAL_INIT 0x0fffffff /* RWE-V */
#define NV_PFB_PRI_MMU_WPR2_ADDR_LO_ALIGNMENT 0x0000000c /* */
#define NV_PFB_PRI_MMU_WPR2_ADDR_HI 0x001FA828 /* RW-4R */
#define NV_PFB_PRI_MMU_WPR2_ADDR_HI__PRIV_LEVEL_MASK 0x001FA7CC /* */
#define NV_PFB_PRI_MMU_WPR2_ADDR_HI_VAL 31:4 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR2_ADDR_HI_VAL_INIT 0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_WPR2_ADDR_HI_ALIGNMENT 0x0000000c /* */
#endif // __gh100_dev_fb_h_

1
src/common/inc/swref/published/turing/tu102/dev_falcon_v4.h
View File

@@ -33,6 +33,7 @@
#define NV_PFALCON_FALCON_IRQSTAT_HALT_TRUE 0x00000001 /* R---V */
#define NV_PFALCON_FALCON_IRQSTAT_SWGEN0 6:6 /* R-XVF */
#define NV_PFALCON_FALCON_IRQSTAT_SWGEN0_TRUE 0x00000001 /* R---V */
#define NV_PFALCON_FALCON_IRQMODE 0x0000000c /* RW-4R */
#define NV_PFALCON_FALCON_IRQMSET 0x00000010 /* -W-4R */
#define NV_PFALCON_FALCON_IRQMCLR 0x00000014 /* -W-4R */
#define NV_PFALCON_FALCON_IRQMASK 0x00000018 /* R--4R */

7
src/common/inc/swref/published/turing/tu102/dev_fbif_v4.h
View File

@@ -30,8 +30,15 @@
#define NV_PFALCON_FBIF_TRANSCFG_TARGET_COHERENT_SYSMEM 0x00000001 /* R---V */
#define NV_PFALCON_FBIF_TRANSCFG_MEM_TYPE 2:2 /* RWIVF */
#define NV_PFALCON_FBIF_TRANSCFG_MEM_TYPE_PHYSICAL 0x00000001 /* R---V */
#define NV_PFALCON_FBIF_INSTBLK 0x00000020 /* R--4R */
#define NV_PFALCON_FBIF_CTL 0x00000024 /* RW-4R */
#define NV_PFALCON_FBIF_CTL_ALLOW_PHYS_NO_CTX 7:7 /* RWIVF */
#define NV_PFALCON_FBIF_CTL_ALLOW_PHYS_NO_CTX_ALLOW 0x00000001 /* RW--V */
#define NV_PFALCON_FBIF_THROTTLE 0x0000002c /* RW-4R */
#define NV_PFALCON_FBIF_ACHK_BLK(i) (0x00000030+(i)*8) /* RW-4A */
#define NV_PFALCON_FBIF_ACHK_BLK__SIZE_1 2 /* */
#define NV_PFALCON_FBIF_ACHK_CTL(i) (0x00000034+(i)*8) /* RW-4A */
#define NV_PFALCON_FBIF_ACHK_CTL__SIZE_1 2 /* */
#define NV_PFALCON_FBIF_CG1 0x00000074 /* RW-4R */
#endif // __tu102_dev_fbif_v4_h__

35
src/common/inc/swref/published/turing/tu102/dev_riscv_pri.h
View File

@@ -28,7 +28,42 @@
#define NV_PRISCV_RISCV_CORE_SWITCH_RISCV_STATUS 0x00000240 /* R-I4R */
#define NV_PRISCV_RISCV_CORE_SWITCH_RISCV_STATUS_ACTIVE_STAT 0:0 /* R-IVF */
#define NV_PRISCV_RISCV_CORE_SWITCH_RISCV_STATUS_ACTIVE_STAT_ACTIVE 0x00000001 /* R---V */
#define NV_PRISCV_RISCV_CPUCTL 0x00000268 /* RWI4R */
#define NV_PRISCV_RISCV_IRQMASK 0x000002b4 /* R-I4R */
#define NV_PRISCV_RISCV_IRQDEST 0x000002b8 /* RW-4R */
#define NV_PRISCV_RISCV_ICD_CMD 0x00000300 /* RW-4R */
#define NV_PRISCV_RISCV_ICD_CMD_OPC 4:0 /* RW-VF */
#define NV_PRISCV_RISCV_ICD_CMD_OPC_STOP 0x00000000 /* RW--V */
#define NV_PRISCV_RISCV_ICD_CMD_OPC_RREG 0x00000008 /* RW--V */
#define NV_PRISCV_RISCV_ICD_CMD_OPC_RDM 0x0000000a /* RW--V */
#define NV_PRISCV_RISCV_ICD_CMD_OPC_RSTAT 0x0000000e /* RW--V */
#define NV_PRISCV_RISCV_ICD_CMD_OPC_RCSR 0x00000010 /* RW--V */
#define NV_PRISCV_RISCV_ICD_CMD_OPC_RPC 0x00000012 /* RW--V */
#define NV_PRISCV_RISCV_ICD_CMD_SZ 7:6 /* RW-VF */
#define NV_PRISCV_RISCV_ICD_CMD_IDX 12:8 /* RW-VF */
#define NV_PRISCV_RISCV_ICD_CMD_ERROR 14:14 /* R-IVF */
#define NV_PRISCV_RISCV_ICD_CMD_ERROR_TRUE 0x00000001 /* R---V */
#define NV_PRISCV_RISCV_ICD_CMD_ERROR_FALSE 0x00000000 /* R-I-V */
#define NV_PRISCV_RISCV_ICD_CMD_BUSY 15:15 /* R-IVF */
#define NV_PRISCV_RISCV_ICD_CMD_BUSY_FALSE 0x00000000 /* R-I-V */
#define NV_PRISCV_RISCV_ICD_CMD_BUSY_TRUE 0x00000001 /* R---V */
#define NV_PRISCV_RISCV_ICD_CMD_PARM 31:16 /* RW-VF */
#define NV_PRISCV_RISCV_ICD_RDATA0 0x0000030c /* R--4R */
#define NV_PRISCV_RISCV_ICD_RDATA1 0x00000318 /* R--4R */
#define NV_PRISCV_RISCV_ICD_ADDR0 0x00000304 /* RW-4R */
#define NV_PRISCV_RISCV_ICD_ADDR1 0x00000310 /* RW-4R */
#define NV_PRISCV_RISCV_TRACECTL 0x00000344 /* RW-4R */
#define NV_PRISCV_RISCV_TRACECTL_FULL 30:30 /* RWIVF */
#define NV_PRISCV_RISCV_TRACE_RDIDX 0x00000348 /* RW-4R */
#define NV_PRISCV_RISCV_TRACE_RDIDX_RDIDX 7:0 /* RWIVF */
#define NV_PRISCV_RISCV_TRACE_RDIDX_MAXIDX 23:16 /* R-IVF */
#define NV_PRISCV_RISCV_TRACE_WTIDX 0x0000034c /* RW-4R */
#define NV_PRISCV_RISCV_TRACE_WTIDX_WTIDX 31:24 /* RWIVF */
#define NV_PRISCV_RISCV_TRACEPC_HI 0x00000350 /* RW-4R */
#define NV_PRISCV_RISCV_TRACEPC_LO 0x00000354 /* RW-4R */
#define NV_PRISCV_RISCV_PRIV_ERR_STAT 0x00000360 /* RWI4R */
#define NV_PRISCV_RISCV_PRIV_ERR_INFO 0x00000364 /* R-I4R */
#define NV_PRISCV_RISCV_PRIV_ERR_ADDR 0x00000368 /* R-I4R */
#define NV_PRISCV_RISCV_HUB_ERR_STAT 0x0000036c /* RWI4R */
#endif // __tu102_dev_riscv_pri_h__

37
src/common/modeset/hdmipacket/nvhdmipkt_C671.c
View File

@@ -1136,17 +1136,9 @@ hdmiQueryFRLConfigC671(NVHDMIPKT_CLASS *pThis,
NvU32 bppMinX16Itr, bppMaxX16Itr;
NvBool bHasPreCalcFRLData = NV_FALSE;
NvBool forceFRLRateDSC = pClientCtrl->forceFRLRate;
HDMI_FRL_DATA_RATE requestedFRLRate = pClientCtrl->frlRate;
#if defined(NVHDMIPKT_NVKMS)
NvU32 rr = (pVidTransInfo->pTiming->pclk * (NvU64)10000) /
(pVidTransInfo->pTiming->HTotal * (NvU64)pVidTransInfo->pTiming->VTotal);
if (!pVidTransInfo->pTiming->interlaced && (rr >= 480)) {
forceFRLRateDSC = NV_TRUE;
requestedFRLRate = dscMaxFRLRate;
}
NvU32 hVisible, vVisible, rr;
NvBool clampBpp;
#endif
// DSC_All_bpp = 1:
@@ -1256,16 +1248,16 @@ hdmiQueryFRLConfigC671(NVHDMIPKT_CLASS *pThis,
frlParams.compressionInfo.hSlices = NV_UNSIGNED_DIV_CEIL(pVidTransInfo->pTiming->HVisible, pClientCtrl->sliceWidth);
}
if (forceFRLRateDSC)
if (pClientCtrl->forceFRLRate)
{
if (requestedFRLRate > dscMaxFRLRate)
if (pClientCtrl->frlRate > dscMaxFRLRate)
{
result = NVHDMIPKT_FAIL;
goto frlQuery_fail;
}
minFRLRateItr = requestedFRLRate;
maxFRLRateItr = requestedFRLRate;
minFRLRateItr = pClientCtrl->frlRate;
maxFRLRateItr = pClientCtrl->frlRate;
}
if (pClientCtrl->forceBppx16)
@@ -1274,6 +1266,23 @@ hdmiQueryFRLConfigC671(NVHDMIPKT_CLASS *pThis,
bppMaxX16Itr = pClientCtrl->bitsPerPixelX16;
}
#if defined(NVHDMIPKT_NVKMS)
hVisible = pVidTransInfo->pTiming->HVisible;
vVisible = pVidTransInfo->pTiming->VVisible;
rr = (pVidTransInfo->pTiming->pclk * (NvU64)10000) /
(pVidTransInfo->pTiming->HTotal * (NvU64)pVidTransInfo->pTiming->VTotal);
clampBpp = ((rr >= 480) || ((rr >= 165) && (hVisible == 5120) && (vVisible == 2160))) &&
(!pVidTransInfo->pTiming->interlaced) &&
(bppMinX16Itr <= 8 * 16) &&
(bppMaxX16Itr >= 8 * 16);
if (clampBpp) {
bppMaxX16Itr = 8 * 16;
}
#endif
// Determine Primary Compressed Format
// First determine the FRL rate at which video transport is possible even at bppMin
// Then iterate over bppTarget - start at max n decrement until we hit bppMin. The max bpp for which

4
src/common/modeset/timing/nvt_gtf.c
View File

@@ -103,6 +103,7 @@ NVT_STATUS NvTiming_CalcGTF(NvU32 width, NvU32 height, NvU32 rr, NvU32 flag, NVT
// A proper way to calculate fixed HTotal*VTotal*Rr/10000
pT->pclk = axb_div_c(dwHTCells*dwVTotal, dwRefreshRate, 10000/NVT_GTF_CELL_GRAN);
pT->pclk1khz = pT->pclk * 10;
pT->HSyncPol = NVT_H_SYNC_NEGATIVE;
pT->VSyncPol = NVT_V_SYNC_POSITIVE;
@@ -111,7 +112,7 @@ NVT_STATUS NvTiming_CalcGTF(NvU32 width, NvU32 height, NvU32 rr, NvU32 flag, NVT
// fill in the extra timing info
pT->etc.flag = 0;
pT->etc.rr = (NvU16)rr;
pT->etc.rrx1k = axb_div_c((NvU32)pT->pclk, (NvU32)10000*(NvU32)1000, (NvU32)pT->HTotal*(NvU32)pT->VTotal);
pT->etc.rrx1k = axb_div_c((NvU32)pT->pclk1khz, (NvU32)1000*(NvU32)1000, (NvU32)pT->HTotal*(NvU32)pT->VTotal);
pT->etc.aspect = 0;
pT->etc.rep = 0x1;
pT->etc.status = NVT_STATUS_GTF;
@@ -128,6 +129,7 @@ NVT_STATUS NvTiming_CalcGTF(NvU32 width, NvU32 height, NvU32 rr, NvU32 flag, NVT
pT->interlaced = NVT_INTERLACED_NO_EXTRA_VBLANK_ON_FIELD2;
pT->pclk >>= 1;
pT->pclk1khz >>= 1;
pT->VTotal >>= 1;
pT->VVisible = (pT->VVisible + 1) / 2;
}

20
src/common/nvlink/inband/interface/nvlink_inband_msg.h
View File

@@ -83,7 +83,9 @@ typedef struct
#define NVLINK_INBAND_GPU_PROBE_CAPS_EGM_SUPPORT NVBIT(2)
#define NVLINK_INBAND_GPU_PROBE_CAPS_ATS_SUPPORT NVBIT(3)
#define NVLINK_INBAND_GPU_PROBE_CAPS_LINK_RETRAIN_SUPPORT NVBIT(4)
#define NVLINK_INBAND_GPU_PROBE_CAPS_ADAPTIVE_BANDWIDTH_SUPPORT NVBIT(5)
#define NVLINK_INBAND_GPU_PROBE_CAPS_HEALTH_SUMMARY NVBIT(6)
#define NVLINK_INBAND_GPU_PROBE_CAPS_GPU_PROBE_REQUEST_ACTION NVBIT(7)
#define NVLINK_INBAND_GPU_PROBE_CAPS_MC_RETRY NVBIT(8)
/* Add more caps as need in the future */
@@ -135,10 +137,11 @@ typedef struct
#define NVLINK_INBAND_FABRIC_HEALTH_MASK_ROUTE_UPDATE_TRUE 1
#define NVLINK_INBAND_FABRIC_HEALTH_MASK_ROUTE_UPDATE_FALSE 2
#define NVLINK_INBAND_FABRIC_HEALTH_MASK_CONNECTION_UNHEALTHY 5:4
#define NVLINK_INBAND_FABRIC_HEALTH_MASK_CONNECTION_UNHEALTHY_NOT_SUPPORTED 0
#define NVLINK_INBAND_FABRIC_HEALTH_MASK_CONNECTION_UNHEALTHY_TRUE 1
#define NVLINK_INBAND_FABRIC_HEALTH_MASK_CONNECTION_UNHEALTHY_FALSE 2
#define NVLINK_INBAND_FABRIC_HEALTH_MASK_CONNECTION_UNHEALTHY 5:4
#define NVLINK_INBAND_FABRIC_HEALTH_MASK_CONNECTION_UNHEALTHY_NOT_SUPPORTED 0
#define NVLINK_INBAND_FABRIC_HEALTH_MASK_CONNECTION_UNHEALTHY_TRUE 1
#define NVLINK_INBAND_FABRIC_HEALTH_MASK_CONNECTION_UNHEALTHY_FALSE 2
#define NVLINK_INBAND_FABRIC_HEALTH_MASK_CONNECTION_UNHEALTHY_TRUE_RESET_REQUIRED 3
#define NVLINK_INBAND_FABRIC_HEALTH_MASK_ACCESS_TIMEOUT_RECOVERY 7:6
#define NVLINK_INBAND_FABRIC_HEALTH_MASK_ACCESS_TIMEOUT_RECOVERY_NOT_SUPPORTED 0
@@ -191,7 +194,8 @@ typedef struct
*/
#define NVLINK_INBAND_GPU_PROBE_UPDATE_ACTION_NONE 0x0 /*! < no action requested */
#define NVLINK_INBAND_GPU_PROBE_UPDATE_ACTION_PROBE_REQUEST_NEEDED 0x1 /*! < probe request needed */
#define NVLINK_INBAND_GPU_PROBE_UPDATE_ACTION_CHANGE_AMAP 0x2 /*! < Change AMAP */
#define NVLINK_INBAND_GPU_PROBE_UPDATE_ACTION_CHANGE_AMAP_AND_QUIESCE 0x3 /*! < Change AMAP and Quiesce */
typedef struct
{
@@ -199,8 +203,9 @@ typedef struct
NvU32 cliqueId; /* Fabric Clique Id*/
NvU32 fabricHealthMask; /* Mask containing bits indicating various fabric health parameters */
NvU32 epoch; /* Epoch to be matched by RM when allowing P2P between GPUs */
NvU8 action; /*! < action request from FM */
NvU8 reserved[27]; /* For future use. Must be initialized to zero */
NvU8 action; /* Action request from FM */
NvU64 linkMask; /* Enabled link mask */
NvU8 reserved[19]; /* For future use. Must be initialized to zero */
} nvlink_inband_gpu_probe_update_req_t;
typedef struct
@@ -369,6 +374,7 @@ static NV_INLINE NvU8 nvlinkGetFabricHealthSummary
}
if (REF_VAL(NVLINK_INBAND_FABRIC_HEALTH_MASK_CONNECTION_UNHEALTHY, fabricHealth) == NVLINK_INBAND_FABRIC_HEALTH_MASK_CONNECTION_UNHEALTHY_TRUE ||
REF_VAL(NVLINK_INBAND_FABRIC_HEALTH_MASK_CONNECTION_UNHEALTHY, fabricHealth) == NVLINK_INBAND_FABRIC_HEALTH_MASK_CONNECTION_UNHEALTHY_TRUE_RESET_REQUIRED ||
REF_VAL(NVLINK_INBAND_FABRIC_HEALTH_MASK_ACCESS_TIMEOUT_RECOVERY, fabricHealth) == NVLINK_INBAND_FABRIC_HEALTH_MASK_ACCESS_TIMEOUT_RECOVERY_TRUE ||
(REF_VAL(NVLINK_INBAND_FABRIC_HEALTH_MASK_INCORRECT_CONFIGURATION, fabricHealth) != NVLINK_INBAND_FABRIC_HEALTH_MASK_INCORRECT_CONFIGURATION_NONE &&
REF_VAL(NVLINK_INBAND_FABRIC_HEALTH_MASK_INCORRECT_CONFIGURATION, fabricHealth) != NVLINK_INBAND_FABRIC_HEALTH_MASK_INCORRECT_CONFIGURATION_NOT_SUPPORTED))

10
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080internal.h
View File

@@ -5409,4 +5409,14 @@ typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_THROTTLE_CTRL_PARAMS
typedef NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_THROTTLE_CTRL_PARAMS NV2080_CTRL_INTERNAL_STATIC_KGR_GET_SM_ISSUE_THROTTLE_CTRL_PARAMS;
/*!
* NV2080_CTRL_CMD_INTERNAL_NVLINK_RC_USER_MODE_CHANNELS
*
* This command is used to perform recovery actions after the fabric has been
* idled due to a fatal nvlink error.
* This command accepts no parameters.
*
*/
#define NV2080_CTRL_CMD_INTERNAL_NVLINK_RC_USER_MODE_CHANNELS (0x20800b08) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_2_INTERFACE_ID << 8) | 0x08" */
/* ctrl2080internal_h */

19
src/common/shared/inc/g_vgpu_chip_flags.h
View File

@@ -621,6 +621,25 @@ ENTRY(0x2238, 0x16B8, 0x10de, "NVIDIA A10M-10C"),
ENTRY(0x2238, 0x16B9, 0x10de, "NVIDIA A10M-20C"),
ENTRY(0x2238, 0x16E6, 0x10de, "NVIDIA A10M-1"),
ENTRY(0x2238, 0x2208, 0x10de, "NVIDIA A10M-3B"),
ENTRY(0x230E, 0x20F5, 0x10de, "NVIDIA H20L-1-15CME"),
ENTRY(0x230E, 0x20F6, 0x10de, "NVIDIA H20L-1-15C"),
ENTRY(0x230E, 0x20F7, 0x10de, "NVIDIA H20L-1-30C"),
ENTRY(0x230E, 0x20F8, 0x10de, "NVIDIA H20L-2-30C"),
ENTRY(0x230E, 0x20F9, 0x10de, "NVIDIA H20L-3-60C"),
ENTRY(0x230E, 0x20FA, 0x10de, "NVIDIA H20L-4-60C"),
ENTRY(0x230E, 0x20FB, 0x10de, "NVIDIA H20L-7-120C"),
ENTRY(0x230E, 0x20FC, 0x10de, "NVIDIA H20L-4C"),
ENTRY(0x230E, 0x20FD, 0x10de, "NVIDIA H20L-5C"),
ENTRY(0x230E, 0x20FE, 0x10de, "NVIDIA H20L-6C"),
ENTRY(0x230E, 0x20FF, 0x10de, "NVIDIA H20L-8C"),
ENTRY(0x230E, 0x2100, 0x10de, "NVIDIA H20L-10C"),
ENTRY(0x230E, 0x2101, 0x10de, "NVIDIA H20L-12C"),
ENTRY(0x230E, 0x2102, 0x10de, "NVIDIA H20L-15C"),
ENTRY(0x230E, 0x2103, 0x10de, "NVIDIA H20L-20C"),
ENTRY(0x230E, 0x2104, 0x10de, "NVIDIA H20L-30C"),
ENTRY(0x230E, 0x2105, 0x10de, "NVIDIA H20L-40C"),
ENTRY(0x230E, 0x2106, 0x10de, "NVIDIA H20L-60C"),
ENTRY(0x230E, 0x2107, 0x10de, "NVIDIA H20L-120C"),
ENTRY(0x2321, 0x1853, 0x10de, "NVIDIA H100L-1-12CME"),
ENTRY(0x2321, 0x1854, 0x10de, "NVIDIA H100L-1-12C"),
ENTRY(0x2321, 0x1855, 0x10de, "NVIDIA H100L-1-24C"),

8
src/common/shared/inc/g_vgpu_resman_specific.h
View File

@@ -17,6 +17,7 @@ static inline void _get_chip_id_for_alias_pgpu(NvU32 *dev_id, NvU32 *subdev_id)
{ 0x20B7, 0x1804, 0x20B7, 0x1532 },
{ 0x20B9, 0x157F, 0x20B7, 0x1532 },
{ 0x20FD, 0x17F8, 0x20F5, 0x0 },
{ 0x230E, 0x20DF, 0x230E, 0x20DF },
{ 0x2324, 0x17A8, 0x2324, 0x17A6 },
{ 0x2329, 0x198C, 0x2329, 0x198B },
{ 0x232C, 0x2064, 0x232C, 0x2063 },
@@ -121,6 +122,13 @@ static const struct {
{0x20F610DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_HALF_GPU , 1094}, // GRID A800-4-20C
{0x20F610DE, NV2080_CTRL_GPU_PARTITION_FLAG_FULL_GPU , 1095}, // GRID A800-7-40C
{0x20F610DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_MINI_QUARTER_GPU , 1091}, // GRID A800-1-10C
{0x230E10DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_EIGHTHED_GPU | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _REQ_DEC_JPG_OFA, _ENABLE), 1499}, // NVIDIA H20L-1-15CME
{0x230E10DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_EIGHTHED_GPU , 1500}, // NVIDIA H20L-1-15C
{0x230E10DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_MINI_QUARTER_GPU , 1501}, // NVIDIA H20L-1-30C
{0x230E10DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_QUARTER_GPU , 1502}, // NVIDIA H20L-2-30C
{0x230E10DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_MINI_HALF_GPU , 1503}, // NVIDIA H20L-3-60C
{0x230E10DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_HALF_GPU , 1504}, // NVIDIA H20L-4-60C
{0x230E10DE, NV2080_CTRL_GPU_PARTITION_FLAG_FULL_GPU , 1505}, // NVIDIA H20L-7-120C
{0x232110DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_EIGHTHED_GPU | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _REQ_DEC_JPG_OFA, _ENABLE), 1061}, // NVIDIA H100L-1-12CME
{0x232110DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_EIGHTHED_GPU , 1062}, // NVIDIA H100L-1-12C
{0x232110DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_MINI_QUARTER_GPU , 1063}, // NVIDIA H100L-1-24C

5
src/common/src/nv_smg.c
View File

@@ -601,6 +601,11 @@ static NvBool GetGraphicsPartitionUUIDForDevice(nvRMContextPtr rmctx, nvMIGDevic
smg_memcpy(migDev->migUuid,
ws->getUuidParams.uuidStr,
NV_MIG_DEVICE_UUID_STR_LENGTH);
ct_assert(NVC638_UUID_LEN == NV_GPU_UUID_LEN);
smg_memcpy(migDev->migUuidBin,
ws->getUuidParams.uuid,
NV_GPU_UUID_LEN);
success = NV_TRUE;
out:

12
src/common/unix/common/utils/interface/nv_mode_timings_utils.h
View File

@@ -89,7 +89,7 @@ static inline NvU16 NV_NVT_TIMING_VVISIBLE(const NVT_TIMING *pTiming)
* When non-zero, NVT_TIMING::etc::aspect contains bytes 12, 13, and
* 14 from the Detailed Timing Definition of the EDID. This contains
* a packed width and height. The width and height is either an
* aspect ratio (16:9 or 4:3), or a physical image size in
* aspect ratio (e.g., 16:9 or 4:3), or a physical image size in
* millimeters. See Table 3.21, and the subsequent notes, in the
* E-EDID 1.4 specification.
*/
@@ -108,8 +108,14 @@ static inline NvBool NV_NVT_TIMING_HAS_ASPECT_RATIO(const NVT_TIMING *pTiming)
NvU16 w = NV_NVT_TIMING_IMAGE_SIZE_WIDTH(pTiming);
NvU16 h = NV_NVT_TIMING_IMAGE_SIZE_HEIGHT(pTiming);
return (((w == 16) && (h == 9)) ||
((w == 4) && (h == 3)));
return (((w == 1) && (h == 1)) ||
((w == 5) && (h == 4)) ||
((w == 4) && (h == 3)) ||
((w == 15) && (h == 9)) ||
((w == 16) && (h == 9)) ||
((w == 16) && (h == 10)) ||
((w == 64) && (h == 27)) ||
((w == 256) && (h == 135)));
}
static inline NvBool NV_NVT_TIMING_HAS_IMAGE_SIZE(const NVT_TIMING *pTiming)