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580.94.13

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russellcnv
2025-12-18 14:38:12 -08:00
parent 58a0f49bed
commit a3af2867b7
94 changed files with 77091 additions and 74546 deletions
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37
src/common/modeset/hdmipacket/nvhdmipkt_C671.c
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@@ -1136,17 +1136,9 @@ hdmiQueryFRLConfigC671(NVHDMIPKT_CLASS *pThis,
NvU32 bppMinX16Itr, bppMaxX16Itr;
NvBool bHasPreCalcFRLData = NV_FALSE;
NvBool forceFRLRateDSC = pClientCtrl->forceFRLRate;
HDMI_FRL_DATA_RATE requestedFRLRate = pClientCtrl->frlRate;
#if defined(NVHDMIPKT_NVKMS)
NvU32 rr = (pVidTransInfo->pTiming->pclk * (NvU64)10000) /
(pVidTransInfo->pTiming->HTotal * (NvU64)pVidTransInfo->pTiming->VTotal);
if (!pVidTransInfo->pTiming->interlaced && (rr >= 480)) {
forceFRLRateDSC = NV_TRUE;
requestedFRLRate = dscMaxFRLRate;
}
NvU32 hVisible, vVisible, rr;
NvBool clampBpp;
#endif
// DSC_All_bpp = 1:
@@ -1256,16 +1248,16 @@ hdmiQueryFRLConfigC671(NVHDMIPKT_CLASS *pThis,
frlParams.compressionInfo.hSlices = NV_UNSIGNED_DIV_CEIL(pVidTransInfo->pTiming->HVisible, pClientCtrl->sliceWidth);
}
if (forceFRLRateDSC)
if (pClientCtrl->forceFRLRate)
{
if (requestedFRLRate > dscMaxFRLRate)
if (pClientCtrl->frlRate > dscMaxFRLRate)
{
result = NVHDMIPKT_FAIL;
goto frlQuery_fail;
}
minFRLRateItr = requestedFRLRate;
maxFRLRateItr = requestedFRLRate;
minFRLRateItr = pClientCtrl->frlRate;
maxFRLRateItr = pClientCtrl->frlRate;
}
if (pClientCtrl->forceBppx16)
@@ -1274,6 +1266,23 @@ hdmiQueryFRLConfigC671(NVHDMIPKT_CLASS *pThis,
bppMaxX16Itr = pClientCtrl->bitsPerPixelX16;
}
#if defined(NVHDMIPKT_NVKMS)
hVisible = pVidTransInfo->pTiming->HVisible;
vVisible = pVidTransInfo->pTiming->VVisible;
rr = (pVidTransInfo->pTiming->pclk * (NvU64)10000) /
(pVidTransInfo->pTiming->HTotal * (NvU64)pVidTransInfo->pTiming->VTotal);
clampBpp = ((rr >= 480) || ((rr >= 165) && (hVisible == 5120) && (vVisible == 2160))) &&
(!pVidTransInfo->pTiming->interlaced) &&
(bppMinX16Itr <= 8 * 16) &&
(bppMaxX16Itr >= 8 * 16);
if (clampBpp) {
bppMaxX16Itr = 8 * 16;
}
#endif
// Determine Primary Compressed Format
// First determine the FRL rate at which video transport is possible even at bppMin
// Then iterate over bppTarget - start at max n decrement until we hit bppMin. The max bpp for which

4
src/common/modeset/timing/nvt_gtf.c
View File

@@ -103,6 +103,7 @@ NVT_STATUS NvTiming_CalcGTF(NvU32 width, NvU32 height, NvU32 rr, NvU32 flag, NVT
// A proper way to calculate fixed HTotal*VTotal*Rr/10000
pT->pclk = axb_div_c(dwHTCells*dwVTotal, dwRefreshRate, 10000/NVT_GTF_CELL_GRAN);
pT->pclk1khz = pT->pclk * 10;
pT->HSyncPol = NVT_H_SYNC_NEGATIVE;
pT->VSyncPol = NVT_V_SYNC_POSITIVE;
@@ -111,7 +112,7 @@ NVT_STATUS NvTiming_CalcGTF(NvU32 width, NvU32 height, NvU32 rr, NvU32 flag, NVT
// fill in the extra timing info
pT->etc.flag = 0;
pT->etc.rr = (NvU16)rr;
pT->etc.rrx1k = axb_div_c((NvU32)pT->pclk, (NvU32)10000*(NvU32)1000, (NvU32)pT->HTotal*(NvU32)pT->VTotal);
pT->etc.rrx1k = axb_div_c((NvU32)pT->pclk1khz, (NvU32)1000*(NvU32)1000, (NvU32)pT->HTotal*(NvU32)pT->VTotal);
pT->etc.aspect = 0;
pT->etc.rep = 0x1;
pT->etc.status = NVT_STATUS_GTF;
@@ -128,6 +129,7 @@ NVT_STATUS NvTiming_CalcGTF(NvU32 width, NvU32 height, NvU32 rr, NvU32 flag, NVT
pT->interlaced = NVT_INTERLACED_NO_EXTRA_VBLANK_ON_FIELD2;
pT->pclk >>= 1;
pT->pclk1khz >>= 1;
pT->VTotal >>= 1;
pT->VVisible = (pT->VVisible + 1) / 2;
}