mirror of
https://github.com/NVIDIA/open-gpu-kernel-modules.git
synced 2026-02-01 05:59:48 +00:00
590.44.01
This commit is contained in:
Maneet Singh
53
kernel-open/common/inc/controller/sbios_table_version.h
Normal file
53
kernel-open/common/inc/controller/sbios_table_version.h
Normal file
@@ -0,0 +1,53 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
||||
* DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef SBIOS_TABLE_VERSION_H
|
||||
#define SBIOS_TABLE_VERSION_H
|
||||
|
||||
#define CONTROLLER_SBIOS_TABLE_VERSION_10 (0x10)
|
||||
#define CONTROLLER_SBIOS_TABLE_VERSION_20 (0x20)
|
||||
#define CONTROLLER_SBIOS_TABLE_VERSION_21 (0x21)
|
||||
#define CONTROLLER_SBIOS_TABLE_VERSION_22 (0x22)
|
||||
#define CONTROLLER_SBIOS_TABLE_VERSION_23 (0x23)
|
||||
#define CONTROLLER_SBIOS_TABLE_VERSION_24 (0x24)
|
||||
#define CONTROLLER_SBIOS_TABLE_VERSION_25 (0x25)
|
||||
#define CONTROLLER_SBIOS_TABLE_MAX_ENTRIES (8)
|
||||
|
||||
// NOTE: When adding a new version, make sure to update MAX_VERSION accordingly.
|
||||
#define CONTROLLER_SBIOS_TABLE_MAX_VERSION (0x25)
|
||||
|
||||
/*!
|
||||
* Layout of Controller 2x data used for static config
|
||||
*/
|
||||
#define NVPCF_CONTROLLER_STATIC_TABLE_VERSION_20 (0x20)
|
||||
#define NVPCF_CONTROLLER_STATIC_TABLE_VERSION_21 (0x21)
|
||||
#define NVPCF_CONTROLLER_STATIC_TABLE_VERSION_22 (0x22)
|
||||
#define NVPCF_CONTROLLER_STATIC_TABLE_VERSION_23 (0x23)
|
||||
#define NVPCF_CONTROLLER_STATIC_TABLE_VERSION_24 (0x24)
|
||||
#define NVPCF_CONTROLLER_STATIC_TABLE_VERSION_25 (0x25)
|
||||
#define NVPCF_CONTROLLER_STATIC_TABLE_MAX_ENTRIES (8)
|
||||
|
||||
// NOTE: When adding a new version, make sure to update MAX_VERSION accordingly.
|
||||
#define NVPCF_CONTROLLER_STATIC_TABLE_MAX_VERSION (0x25)
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||||
|
||||
#endif // SBIOS_TABLE_VERSION_H
|
||||
@@ -24,7 +24,6 @@
|
||||
#define __NV_HASH_H__
|
||||
|
||||
#include "conftest.h"
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||||
#include "nv-list-helpers.h"
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||||
#include <linux/types.h>
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||||
#include <linux/kernel.h>
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||||
#include <linux/hash.h>
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||||
|
||||
@@ -26,8 +26,10 @@
|
||||
#define NV_IOCTL_H
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||||
|
||||
#include <nv-ioctl-numbers.h>
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#include <nv-ioctl-numa.h>
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||||
#include <nvtypes.h>
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||||
|
||||
|
||||
typedef struct {
|
||||
NvU32 domain; /* PCI domain number */
|
||||
NvU8 bus; /* PCI bus number */
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||||
@@ -113,7 +115,7 @@ typedef struct nv_ioctl_query_device_intr
|
||||
{
|
||||
NvU32 intrStatus NV_ALIGN_BYTES(4);
|
||||
NvU32 status;
|
||||
} nv_ioctl_query_device_intr;
|
||||
} nv_ioctl_query_device_intr_t;
|
||||
|
||||
/* system parameters that the kernel driver may use for configuration */
|
||||
typedef struct nv_ioctl_sys_params
|
||||
|
||||
@@ -102,17 +102,6 @@
|
||||
#include <linux/dma-buf.h>
|
||||
#endif
|
||||
|
||||
#if defined(NV_DRM_AVAILABLE)
|
||||
#include <drm/drm_device.h>
|
||||
#include <drm/drm_drv.h>
|
||||
|
||||
#if defined(NV_DRM_DRMP_H_PRESENT)
|
||||
#include <drm/drmP.h>
|
||||
#endif
|
||||
|
||||
#include <drm/drm_gem.h>
|
||||
#endif /* NV_DRM_AVAILABLE */
|
||||
|
||||
/* task and signal-related items */
|
||||
#include <linux/sched/signal.h>
|
||||
#include <linux/sched/task.h>
|
||||
@@ -141,8 +130,6 @@
|
||||
#include <asm/bitops.h> /* __set_bit() */
|
||||
#include <linux/time.h> /* FD_SET() */
|
||||
|
||||
#include "nv-list-helpers.h"
|
||||
|
||||
/*
|
||||
* Use current->cred->euid, instead of calling current_euid().
|
||||
* The latter can pull in the GPL-only debug_lockdep_rcu_enabled()
|
||||
@@ -274,14 +261,8 @@ extern int nv_pat_mode;
|
||||
user_function, NULL, args)
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_PREEMPT_RT) || defined(CONFIG_PREEMPT_RT_FULL)
|
||||
#define NV_CONFIG_PREEMPT_RT 1
|
||||
#endif
|
||||
|
||||
#define NV_PAGE_COUNT(page) \
|
||||
((unsigned int)page_count(page))
|
||||
#define NV_GET_PAGE_FLAGS(page_ptr) \
|
||||
(NV_GET_PAGE_STRUCT(page_ptr->phys_addr)->flags)
|
||||
|
||||
#if !defined(DEBUG) && defined(__GFP_NOWARN)
|
||||
#define NV_GFP_KERNEL (GFP_KERNEL | __GFP_NOWARN)
|
||||
@@ -298,9 +279,9 @@ extern int nv_pat_mode;
|
||||
* such as Linux/x86-64; the alternative is to use an IOMMU such
|
||||
* as the one implemented with the K8 GART, if available.
|
||||
*/
|
||||
#define NV_GFP_DMA32 (NV_GFP_KERNEL | GFP_DMA32)
|
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#define NV_GFP_DMA32 (GFP_DMA32)
|
||||
#else
|
||||
#define NV_GFP_DMA32 (NV_GFP_KERNEL)
|
||||
#define NV_GFP_DMA32 0
|
||||
#endif
|
||||
|
||||
#if defined(NVCPU_AARCH64) || defined(NVCPU_RISCV64)
|
||||
@@ -388,11 +369,7 @@ static inline void nv_vfree(void *ptr, NvU64 size)
|
||||
|
||||
static inline void *nv_ioremap(NvU64 phys, NvU64 size)
|
||||
{
|
||||
#if IS_ENABLED(CONFIG_INTEL_TDX_GUEST) && defined(NV_IOREMAP_DRIVER_HARDENED_PRESENT)
|
||||
void *ptr = ioremap_driver_hardened(phys, size);
|
||||
#else
|
||||
void *ptr = ioremap(phys, size);
|
||||
#endif
|
||||
NV_MEMDBG_ADD(ptr, size);
|
||||
return ptr;
|
||||
}
|
||||
@@ -405,9 +382,7 @@ static inline void *nv_ioremap_nocache(NvU64 phys, NvU64 size)
|
||||
static inline void *nv_ioremap_cache(NvU64 phys, NvU64 size)
|
||||
{
|
||||
void *ptr = NULL;
|
||||
#if IS_ENABLED(CONFIG_INTEL_TDX_GUEST) && defined(NV_IOREMAP_CACHE_SHARED_PRESENT)
|
||||
ptr = ioremap_cache_shared(phys, size);
|
||||
#elif defined(NV_IOREMAP_CACHE_PRESENT)
|
||||
#if defined(NV_IOREMAP_CACHE_PRESENT)
|
||||
ptr = ioremap_cache(phys, size);
|
||||
#else
|
||||
return nv_ioremap(phys, size);
|
||||
@@ -421,9 +396,7 @@ static inline void *nv_ioremap_cache(NvU64 phys, NvU64 size)
|
||||
static inline void *nv_ioremap_wc(NvU64 phys, NvU64 size)
|
||||
{
|
||||
void *ptr = NULL;
|
||||
#if IS_ENABLED(CONFIG_INTEL_TDX_GUEST) && defined(NV_IOREMAP_DRIVER_HARDENED_WC_PRESENT)
|
||||
ptr = ioremap_driver_hardened_wc(phys, size);
|
||||
#elif defined(NV_IOREMAP_WC_PRESENT)
|
||||
#if defined(NV_IOREMAP_WC_PRESENT)
|
||||
ptr = ioremap_wc(phys, size);
|
||||
#else
|
||||
return nv_ioremap_nocache(phys, size);
|
||||
@@ -465,13 +438,7 @@ static NvBool nv_numa_node_has_memory(int node_id)
|
||||
NV_MEMDBG_ADD(ptr, size); \
|
||||
}
|
||||
|
||||
#if defined(__GFP_RETRY_MAYFAIL)
|
||||
#define NV_GFP_NO_OOM (NV_GFP_KERNEL | __GFP_RETRY_MAYFAIL)
|
||||
#elif defined(__GFP_NORETRY)
|
||||
#define NV_GFP_NO_OOM (NV_GFP_KERNEL | __GFP_NORETRY)
|
||||
#else
|
||||
#define NV_GFP_NO_OOM (NV_GFP_KERNEL)
|
||||
#endif
|
||||
|
||||
#define NV_KMALLOC_NO_OOM(ptr, size) \
|
||||
{ \
|
||||
@@ -528,22 +495,12 @@ static inline pgprot_t nv_adjust_pgprot(pgprot_t vm_prot)
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#define NV_GET_CURRENT_PROCESS() current->tgid
|
||||
#define NV_IN_ATOMIC() in_atomic()
|
||||
#define NV_COPY_TO_USER(to, from, n) copy_to_user(to, from, n)
|
||||
#define NV_COPY_FROM_USER(to, from, n) copy_from_user(to, from, n)
|
||||
|
||||
#define NV_IS_SUSER() capable(CAP_SYS_ADMIN)
|
||||
#define NV_CLI() local_irq_disable()
|
||||
#define NV_SAVE_FLAGS(eflags) local_save_flags(eflags)
|
||||
#define NV_RESTORE_FLAGS(eflags) local_irq_restore(eflags)
|
||||
#define NV_MAY_SLEEP() (!irqs_disabled() && !in_interrupt() && !NV_IN_ATOMIC())
|
||||
#define NV_MAY_SLEEP() (!irqs_disabled() && !in_interrupt() && !in_atomic())
|
||||
#define NV_MODULE_PARAMETER(x) module_param(x, int, 0)
|
||||
#define NV_MODULE_STRING_PARAMETER(x) module_param(x, charp, 0)
|
||||
#undef MODULE_PARM
|
||||
|
||||
#define NV_NUM_CPUS() num_possible_cpus()
|
||||
|
||||
#define NV_HAVE_MEMORY_ENCRYPT_DECRYPT 0
|
||||
|
||||
#if defined(NVCPU_X86_64) && \
|
||||
@@ -596,7 +553,6 @@ static inline dma_addr_t nv_phys_to_dma(struct device *dev, NvU64 pa)
|
||||
#endif
|
||||
}
|
||||
|
||||
#define NV_GET_OFFSET_IN_PAGE(phys_page) offset_in_page(phys_page)
|
||||
#define NV_GET_PAGE_STRUCT(phys_page) virt_to_page(__va(phys_page))
|
||||
#define NV_VMA_PGOFF(vma) ((vma)->vm_pgoff)
|
||||
#define NV_VMA_SIZE(vma) ((vma)->vm_end - (vma)->vm_start)
|
||||
@@ -711,13 +667,6 @@ static inline dma_addr_t nv_phys_to_dma(struct device *dev, NvU64 pa)
|
||||
# define minor(x) MINOR(x)
|
||||
#endif
|
||||
|
||||
#if !defined(PCI_COMMAND_SERR)
|
||||
#define PCI_COMMAND_SERR 0x100
|
||||
#endif
|
||||
#if !defined(PCI_COMMAND_INTX_DISABLE)
|
||||
#define PCI_COMMAND_INTX_DISABLE 0x400
|
||||
#endif
|
||||
|
||||
#ifndef PCI_CAP_ID_EXP
|
||||
#define PCI_CAP_ID_EXP 0x10
|
||||
#endif
|
||||
@@ -983,6 +932,7 @@ typedef struct nv_alloc_s {
|
||||
NvBool unencrypted : 1;
|
||||
NvBool coherent : 1;
|
||||
NvBool carveout : 1;
|
||||
NvBool pool : 1;
|
||||
} flags;
|
||||
unsigned int cache_type;
|
||||
unsigned int num_pages;
|
||||
@@ -1143,14 +1093,18 @@ typedef struct nv_dma_map_s {
|
||||
i++, sm = &dm->mapping.discontig.submaps[i])
|
||||
|
||||
/*
|
||||
* On 4K ARM kernels, use max submap size a multiple of 64K to keep nv-p2p happy.
|
||||
* Despite 4K OS pages, we still use 64K P2P pages due to dependent modules still using 64K.
|
||||
* Instead of using (4G-4K), use max submap size as (4G-64K) since the mapped IOVA range
|
||||
* must be aligned at 64K boundary.
|
||||
* On 4K ARM kernels, use max submap size a multiple of 2M to avoid breaking up 2M page size
|
||||
* sysmem allocations.
|
||||
*
|
||||
* Instead of using (4G-4K), use max submap size as (4G-2M) since the mapped IOVA range
|
||||
* must be aligned at 2M boundary.
|
||||
*
|
||||
* Bug 5401803: Tracks migrating away from making IOMMU mappings using submaps in favor of
|
||||
* using sg_chain() to chain a single large scatterlist.
|
||||
*/
|
||||
#if defined(CONFIG_ARM64_4K_PAGES)
|
||||
#define NV_DMA_U32_MAX_4K_PAGES ((NvU32)((NV_U32_MAX >> PAGE_SHIFT) + 1))
|
||||
#define NV_DMA_SUBMAP_MAX_PAGES ((NvU32)(NV_DMA_U32_MAX_4K_PAGES - 16))
|
||||
#define NV_DMA_SUBMAP_MAX_PAGES ((NvU32)(NV_DMA_U32_MAX_4K_PAGES - 512))
|
||||
#else
|
||||
#define NV_DMA_SUBMAP_MAX_PAGES ((NvU32)(NV_U32_MAX >> PAGE_SHIFT))
|
||||
#endif
|
||||
@@ -1294,7 +1248,8 @@ struct nv_pci_tegra_devfreq_dev;
|
||||
typedef struct nv_linux_state_s {
|
||||
nv_state_t nv_state;
|
||||
|
||||
atomic_t usage_count;
|
||||
atomic_t usage_count;
|
||||
|
||||
NvU32 suspend_count;
|
||||
|
||||
struct device *dev;
|
||||
@@ -1470,6 +1425,8 @@ typedef struct nv_linux_state_s {
|
||||
|
||||
int (*devfreq_suspend)(struct device *dev);
|
||||
int (*devfreq_resume)(struct device *dev);
|
||||
int (*devfreq_enable_boost)(struct device *dev, unsigned int duration);
|
||||
int (*devfreq_disable_boost)(struct device *dev);
|
||||
#endif
|
||||
} nv_linux_state_t;
|
||||
|
||||
@@ -1640,6 +1597,7 @@ extern NvU32 NVreg_EnableUserNUMAManagement;
|
||||
extern NvU32 NVreg_RegisterPCIDriver;
|
||||
extern NvU32 NVreg_RegisterPlatformDeviceDriver;
|
||||
extern NvU32 NVreg_EnableResizableBar;
|
||||
extern NvU32 NVreg_TegraGpuPgMask;
|
||||
extern NvU32 NVreg_EnableNonblockingOpen;
|
||||
|
||||
extern NvU32 num_probed_nv_devices;
|
||||
@@ -1697,10 +1655,7 @@ static inline NvU32 nv_default_irq_flags(nv_state_t *nv)
|
||||
return flags;
|
||||
}
|
||||
|
||||
#define MODULE_BASE_NAME "nvidia"
|
||||
#define MODULE_INSTANCE_NUMBER 0
|
||||
#define MODULE_INSTANCE_STRING ""
|
||||
#define MODULE_NAME MODULE_BASE_NAME MODULE_INSTANCE_STRING
|
||||
#define MODULE_NAME "nvidia"
|
||||
|
||||
NvS32 nv_request_soc_irq(nv_linux_state_t *, NvU32, nv_soc_irq_type_t, NvU32, NvU32, const char*);
|
||||
NV_STATUS nv_imp_icc_get(nv_state_t *nv);
|
||||
|
||||
@@ -26,45 +26,12 @@
|
||||
#include <linux/list.h>
|
||||
#include "conftest.h"
|
||||
|
||||
/*
|
||||
* list_first_entry_or_null added by commit 6d7581e62f8b ("list: introduce
|
||||
* list_first_entry_or_null") in v3.10 (2013-05-29).
|
||||
*/
|
||||
#if !defined(list_first_entry_or_null)
|
||||
#define list_first_entry_or_null(ptr, type, member) \
|
||||
(!list_empty(ptr) ? list_first_entry(ptr, type, member) : NULL)
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Added by commit 93be3c2eb337 ("list: introduce list_last_entry(), use
|
||||
* list_{first,last}_entry()") in v3.13 (2013-11-12).
|
||||
*/
|
||||
#if !defined(list_last_entry)
|
||||
#define list_last_entry(ptr, type, member) \
|
||||
list_entry((ptr)->prev, type, member)
|
||||
#endif
|
||||
|
||||
/* list_last_entry_or_null() doesn't actually exist in the kernel */
|
||||
#if !defined(list_last_entry_or_null)
|
||||
#define list_last_entry_or_null(ptr, type, member) \
|
||||
(!list_empty(ptr) ? list_last_entry(ptr, type, member) : NULL)
|
||||
#endif
|
||||
|
||||
/*
|
||||
* list_prev_entry() and list_next_entry added by commit 008208c6b26f
|
||||
* ("list: introduce list_next_entry() and list_prev_entry()") in
|
||||
* v3.13 (2013-11-12).
|
||||
*/
|
||||
#if !defined(list_prev_entry)
|
||||
#define list_prev_entry(pos, member) \
|
||||
list_entry((pos)->member.prev, typeof(*(pos)), member)
|
||||
#endif
|
||||
|
||||
#if !defined(list_next_entry)
|
||||
#define list_next_entry(pos, member) \
|
||||
list_entry((pos)->member.next, typeof(*(pos)), member)
|
||||
#endif
|
||||
|
||||
#if !defined(NV_LIST_IS_FIRST_PRESENT)
|
||||
static inline int list_is_first(const struct list_head *list,
|
||||
const struct list_head *head)
|
||||
|
||||
@@ -32,18 +32,6 @@
|
||||
#include <linux/semaphore.h>
|
||||
#include <linux/sched/signal.h> /* signal_pending */
|
||||
|
||||
#if defined(CONFIG_PREEMPT_RT) || defined(CONFIG_PREEMPT_RT_FULL)
|
||||
typedef raw_spinlock_t nv_spinlock_t;
|
||||
#define NV_DEFINE_SPINLOCK(lock) DEFINE_RAW_SPINLOCK(lock)
|
||||
#define NV_SPIN_LOCK_INIT(lock) raw_spin_lock_init(lock)
|
||||
#define NV_SPIN_LOCK_IRQ(lock) raw_spin_lock_irq(lock)
|
||||
#define NV_SPIN_UNLOCK_IRQ(lock) raw_spin_unlock_irq(lock)
|
||||
#define NV_SPIN_LOCK_IRQSAVE(lock,flags) raw_spin_lock_irqsave(lock,flags)
|
||||
#define NV_SPIN_UNLOCK_IRQRESTORE(lock,flags) raw_spin_unlock_irqrestore(lock,flags)
|
||||
#define NV_SPIN_LOCK(lock) raw_spin_lock(lock)
|
||||
#define NV_SPIN_UNLOCK(lock) raw_spin_unlock(lock)
|
||||
#define NV_SPIN_UNLOCK_WAIT(lock) raw_spin_unlock_wait(lock)
|
||||
#else
|
||||
typedef spinlock_t nv_spinlock_t;
|
||||
#define NV_DEFINE_SPINLOCK(lock) DEFINE_SPINLOCK(lock)
|
||||
#define NV_SPIN_LOCK_INIT(lock) spin_lock_init(lock)
|
||||
@@ -54,7 +42,6 @@ typedef spinlock_t nv_spinlock_t;
|
||||
#define NV_SPIN_LOCK(lock) spin_lock(lock)
|
||||
#define NV_SPIN_UNLOCK(lock) spin_unlock(lock)
|
||||
#define NV_SPIN_UNLOCK_WAIT(lock) spin_unlock_wait(lock)
|
||||
#endif
|
||||
|
||||
#define NV_INIT_MUTEX(mutex) sema_init(mutex, 1)
|
||||
|
||||
|
||||
@@ -47,9 +47,6 @@ void NV_API_CALL nv_init_msi (nv_state_t *);
|
||||
void NV_API_CALL nv_init_msix (nv_state_t *);
|
||||
NvS32 NV_API_CALL nv_request_msix_irq (nv_linux_state_t *);
|
||||
|
||||
#define NV_PCI_MSIX_FLAGS 2
|
||||
#define NV_PCI_MSIX_FLAGS_QSIZE 0x7FF
|
||||
|
||||
static inline void nv_free_msix_irq(nv_linux_state_t *nvl)
|
||||
{
|
||||
int i;
|
||||
@@ -67,17 +64,8 @@ static inline int nv_get_max_irq(struct pci_dev *pci_dev)
|
||||
NvU16 ctrl;
|
||||
|
||||
cap_ptr = pci_find_capability(pci_dev, PCI_CAP_ID_MSIX);
|
||||
/*
|
||||
* The 'PCI_MSIX_FLAGS' was added in 2.6.21-rc3 by:
|
||||
* 2007-03-05 f5f2b13129a6541debf8851bae843cbbf48298b7
|
||||
*/
|
||||
#if defined(PCI_MSIX_FLAGS)
|
||||
pci_read_config_word(pci_dev, cap_ptr + PCI_MSIX_FLAGS, &ctrl);
|
||||
nvec = (ctrl & PCI_MSIX_FLAGS_QSIZE) + 1;
|
||||
#else
|
||||
pci_read_config_word(pci_dev, cap_ptr + NV_PCI_MSIX_FLAGS, &ctrl);
|
||||
nvec = (ctrl & NV_PCI_MSIX_FLAGS_QSIZE) + 1;
|
||||
#endif
|
||||
|
||||
return nvec;
|
||||
}
|
||||
|
||||
@@ -73,31 +73,22 @@ extern NvBool nvos_is_chipset_io_coherent(void);
|
||||
|
||||
#define NV_PGPROT_UNCACHED_DEVICE(old_prot) pgprot_noncached(old_prot)
|
||||
#if defined(NVCPU_AARCH64)
|
||||
#define NV_PROT_WRITE_COMBINED_DEVICE (PROT_DEFAULT | PTE_PXN | PTE_UXN | \
|
||||
PTE_ATTRINDX(MT_DEVICE_nGnRE))
|
||||
#define NV_PGPROT_WRITE_COMBINED_DEVICE(old_prot) \
|
||||
__pgprot_modify(old_prot, PTE_ATTRINDX_MASK, NV_PROT_WRITE_COMBINED_DEVICE)
|
||||
#define NV_PGPROT_WRITE_COMBINED(old_prot) NV_PGPROT_UNCACHED(old_prot)
|
||||
#define NV_PGPROT_READ_ONLY(old_prot) \
|
||||
__pgprot_modify(old_prot, 0, PTE_RDONLY)
|
||||
#elif defined(NVCPU_X86_64)
|
||||
#define NV_PGPROT_UNCACHED_WEAK(old_prot) pgprot_noncached_weak(old_prot)
|
||||
#define NV_PGPROT_WRITE_COMBINED_DEVICE(old_prot) \
|
||||
pgprot_modify_writecombine(old_prot)
|
||||
#define NV_PGPROT_WRITE_COMBINED(old_prot) \
|
||||
NV_PGPROT_WRITE_COMBINED_DEVICE(old_prot)
|
||||
pgprot_modify_writecombine(old_prot)
|
||||
#define NV_PGPROT_READ_ONLY(old_prot) \
|
||||
__pgprot(pgprot_val((old_prot)) & ~_PAGE_RW)
|
||||
#elif defined(NVCPU_RISCV64)
|
||||
#define NV_PGPROT_WRITE_COMBINED_DEVICE(old_prot) \
|
||||
#define NV_PGPROT_WRITE_COMBINED(old_prot) \
|
||||
pgprot_writecombine(old_prot)
|
||||
/* Don't attempt to mark sysmem pages as write combined on riscv */
|
||||
#define NV_PGPROT_WRITE_COMBINED(old_prot) old_prot
|
||||
#define NV_PGPROT_READ_ONLY(old_prot) \
|
||||
__pgprot(pgprot_val((old_prot)) & ~_PAGE_WRITE)
|
||||
#else
|
||||
/* Writecombine is not supported */
|
||||
#undef NV_PGPROT_WRITE_COMBINED_DEVICE(old_prot)
|
||||
#undef NV_PGPROT_WRITE_COMBINED(old_prot)
|
||||
#define NV_PGPROT_READ_ONLY(old_prot)
|
||||
#endif
|
||||
|
||||
@@ -57,8 +57,6 @@ int nv_uvm_init (void);
|
||||
void nv_uvm_exit (void);
|
||||
NV_STATUS nv_uvm_suspend (void);
|
||||
NV_STATUS nv_uvm_resume (void);
|
||||
void nv_uvm_notify_start_device (const NvU8 *uuid);
|
||||
void nv_uvm_notify_stop_device (const NvU8 *uuid);
|
||||
NV_STATUS nv_uvm_event_interrupt (const NvU8 *uuid);
|
||||
NV_STATUS nv_uvm_drain_P2P (const NvU8 *uuid);
|
||||
NV_STATUS nv_uvm_resume_P2P (const NvU8 *uuid);
|
||||
|
||||
@@ -86,6 +86,8 @@ extern const NvBool nv_is_rm_firmware_supported_os;
|
||||
|
||||
#define NV_RM_DEVICE_INTR_ADDRESS 0x100
|
||||
|
||||
#define NV_TEGRA_PCI_IGPU_PG_MASK_DEFAULT 0xFFFFFFFF
|
||||
|
||||
/*
|
||||
* Clock domain identifier, which is used for fetching the engine
|
||||
* load backed by the specified clock domain for Tegra platforms
|
||||
@@ -413,6 +415,7 @@ typedef struct nv_soc_irq_info_s {
|
||||
|
||||
#define NV_MAX_SOC_IRQS 10
|
||||
#define NV_MAX_DPAUX_NUM_DEVICES 4
|
||||
#define NV_MAX_DPAUX_DEV_NAME_SIZE 10
|
||||
|
||||
#define NV_MAX_SOC_DPAUX_NUM_DEVICES 4
|
||||
|
||||
@@ -429,6 +432,12 @@ typedef struct nv_phys_addr_range
|
||||
NvU64 len;
|
||||
} nv_phys_addr_range_t;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
char vbios_version[15];
|
||||
char firmware_version[64];
|
||||
} nv_cached_gpu_info_t;
|
||||
|
||||
typedef struct nv_state_t
|
||||
{
|
||||
void *priv; /* private data */
|
||||
@@ -465,6 +474,7 @@ typedef struct nv_state_t
|
||||
NvU32 num_dpaux_instance;
|
||||
NvU32 interrupt_line;
|
||||
NvU32 dpaux_irqs[NV_MAX_DPAUX_NUM_DEVICES];
|
||||
char dpaux_devname[NV_MAX_DPAUX_NUM_DEVICES][NV_MAX_DPAUX_DEV_NAME_SIZE];
|
||||
nv_soc_irq_info_t soc_irq_info[NV_MAX_SOC_IRQS];
|
||||
NvS32 current_soc_irq;
|
||||
NvU32 num_soc_irqs;
|
||||
@@ -481,6 +491,7 @@ typedef struct nv_state_t
|
||||
NvBool is_tegra_pci_igpu;
|
||||
NvBool supports_tegra_igpu_rg;
|
||||
NvBool is_tegra_pci_igpu_rg_enabled;
|
||||
NvU32 tegra_pci_igpu_pg_mask;
|
||||
|
||||
NvBool primary_vga;
|
||||
|
||||
@@ -588,8 +599,12 @@ typedef struct nv_state_t
|
||||
/* Console is managed by drm drivers or NVKMS */
|
||||
NvBool client_managed_console;
|
||||
|
||||
/* Bool to check if power management is unsupported */
|
||||
/* Struct to cache the gpu info details */
|
||||
nv_cached_gpu_info_t cached_gpu_info;
|
||||
|
||||
/* Bool to check if power management is supported */
|
||||
NvBool is_pm_unsupported;
|
||||
|
||||
} nv_state_t;
|
||||
|
||||
#define NVFP_TYPE_NONE 0x0
|
||||
@@ -651,7 +666,7 @@ typedef struct UvmGpuPagingChannelInfo_tag *nvgpuPagingChannelInfo_t;
|
||||
typedef enum UvmPmaGpuMemoryType_tag nvgpuGpuMemoryType_t;
|
||||
typedef NV_STATUS (*nvPmaEvictPagesCallback)(void *, NvU64, NvU64 *, NvU32, NvU64, NvU64, nvgpuGpuMemoryType_t);
|
||||
typedef NV_STATUS (*nvPmaEvictRangeCallback)(void *, NvU64, NvU64, nvgpuGpuMemoryType_t);
|
||||
|
||||
typedef struct UvmGpuAccessBitsBufferAlloc_tag *nvgpuAccessBitBufferAlloc_t;
|
||||
/*
|
||||
* flags
|
||||
*/
|
||||
@@ -988,6 +1003,7 @@ NvBool NV_API_CALL nv_match_gpu_os_info(nv_state_t *, void *);
|
||||
|
||||
void NV_API_CALL nv_get_updated_emu_seg(NvU32 *start, NvU32 *end);
|
||||
void NV_API_CALL nv_get_screen_info(nv_state_t *, NvU64 *, NvU32 *, NvU32 *, NvU32 *, NvU32 *, NvU64 *);
|
||||
void NV_API_CALL nv_set_gpu_pg_mask(nv_state_t *);
|
||||
|
||||
struct dma_buf;
|
||||
typedef struct nv_dma_buf nv_dma_buf_t;
|
||||
@@ -1107,16 +1123,15 @@ NvBool NV_API_CALL rm_isr (nvidia_stack_t *, nv_state_t *
|
||||
void NV_API_CALL rm_isr_bh (nvidia_stack_t *, nv_state_t *);
|
||||
void NV_API_CALL rm_isr_bh_unlocked (nvidia_stack_t *, nv_state_t *);
|
||||
NvBool NV_API_CALL rm_is_msix_allowed (nvidia_stack_t *, nv_state_t *);
|
||||
NvBool NV_API_CALL rm_wait_for_bar_firewall (nvidia_stack_t *, NvU32 domain, NvU8 bus, NvU8 device, NvU8 function, NvU16 devId, NvU16 subsystemId);
|
||||
NV_STATUS NV_API_CALL rm_pmu_perfmon_get_load (nvidia_stack_t *, nv_state_t *, NvU32 *, TEGRASOC_DEVFREQ_CLK);
|
||||
NV_STATUS NV_API_CALL rm_power_management (nvidia_stack_t *, nv_state_t *, nv_pm_action_t);
|
||||
NV_STATUS NV_API_CALL rm_stop_user_channels (nvidia_stack_t *, nv_state_t *);
|
||||
NV_STATUS NV_API_CALL rm_restart_user_channels (nvidia_stack_t *, nv_state_t *);
|
||||
NV_STATUS NV_API_CALL rm_save_low_res_mode (nvidia_stack_t *, nv_state_t *);
|
||||
void NV_API_CALL rm_get_vbios_version (nvidia_stack_t *, nv_state_t *, char *);
|
||||
char* NV_API_CALL rm_get_gpu_uuid (nvidia_stack_t *, nv_state_t *);
|
||||
const NvU8* NV_API_CALL rm_get_gpu_uuid_raw (nvidia_stack_t *, nv_state_t *);
|
||||
void NV_API_CALL rm_set_rm_firmware_requested(nvidia_stack_t *, nv_state_t *);
|
||||
void NV_API_CALL rm_get_firmware_version (nvidia_stack_t *, nv_state_t *, char *, NvLength);
|
||||
void NV_API_CALL rm_cleanup_file_private (nvidia_stack_t *, nv_state_t *, nv_file_private_t *);
|
||||
void NV_API_CALL rm_unbind_lock (nvidia_stack_t *, nv_state_t *);
|
||||
NV_STATUS NV_API_CALL rm_read_registry_dword (nvidia_stack_t *, nv_state_t *, const char *, NvU32 *);
|
||||
|
||||
@@ -33,6 +33,12 @@ typedef NvU32 MIGDeviceId;
|
||||
|
||||
#define NO_MIG_DEVICE 0L
|
||||
|
||||
/* Convert a MIGDeviceId into a 0-based per-GPU subdevice index. */
|
||||
#define MIG_DEVICE_ID_SUBDEV_MASK 0xf0000000
|
||||
#define MIG_DEVICE_ID_SUBDEV_SHIFT 28
|
||||
|
||||
#define MIG_DEVICE_ID_TO_SUBDEV(migDeviceId) (((migDeviceId) & MIG_DEVICE_ID_SUBDEV_MASK) >> MIG_DEVICE_ID_SUBDEV_SHIFT)
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2013-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2013-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
@@ -29,7 +29,7 @@
|
||||
#define _NV_UVM_INTERFACE_H_
|
||||
|
||||
// Forward references, to break circular header file dependencies:
|
||||
struct UvmOpsUvmEvents;
|
||||
struct UvmEventsLinux;
|
||||
|
||||
#if defined(NVIDIA_UVM_ENABLED)
|
||||
|
||||
@@ -1008,6 +1008,65 @@ NV_STATUS nvUvmInterfaceFlushReplayableFaultBuffer(UvmGpuFaultInfo *pFaultInfo,
|
||||
*/
|
||||
NV_STATUS nvUvmInterfaceTogglePrefetchFaults(UvmGpuFaultInfo *pFaultInfo,
|
||||
NvBool bEnable);
|
||||
/*******************************************************************************
|
||||
nvUvmInterfaceAccessBitsBufAlloc
|
||||
|
||||
This function allocates a buffer for access bits.
|
||||
|
||||
Arguments:
|
||||
device[IN] - Device handle associated with the gpu
|
||||
pAccessBitsInfo[OUT] - Information provided by RM for access bits handling
|
||||
|
||||
Error codes:
|
||||
NV_ERR_INVALID_ARGUMENT - If the parameter/s is invalid.
|
||||
NV_ERR_NO_MEMORY - If the memory allocation fails.
|
||||
NV_ERR_GENERIC - Unexpected error. We try hard to
|
||||
avoid returning this error code,
|
||||
because it is not very informative.
|
||||
*/
|
||||
NV_STATUS nvUvmInterfaceAccessBitsBufAlloc(uvmGpuDeviceHandle device,
|
||||
UvmGpuAccessBitsBufferAlloc* pAccessBitsInfo);
|
||||
|
||||
/*******************************************************************************
|
||||
nvUvmInterfaceAccessBitsBufFree
|
||||
|
||||
This function frees the buffer used for access bits.
|
||||
|
||||
Arguments:
|
||||
device[IN] - Device handle associated with the gpu
|
||||
pAccessBitsInfo[IN] - Information containing the access bits buffer handle to be freed
|
||||
|
||||
Error codes:
|
||||
NV_ERR_INVALID_ARGUMENT - If the parameter/s is invalid.
|
||||
NV_ERR_GENERIC - Unexpected error. We try hard to
|
||||
avoid returning this error code,
|
||||
because it is not very informative.
|
||||
*/
|
||||
NV_STATUS nvUvmInterfaceAccessBitsBufFree(uvmGpuDeviceHandle device,
|
||||
UvmGpuAccessBitsBufferAlloc* pAccessBitsInfo);
|
||||
|
||||
/*******************************************************************************
|
||||
nvUvmInterfaceAccessBitsDump
|
||||
|
||||
This function get the access bits information in accordance with the mode
|
||||
requested and stores it in the buffer provided by the client.
|
||||
|
||||
Arguments:
|
||||
device[IN] - Device handle associated with the gpu
|
||||
pAccessBitsInfo[IN/OUT] - Information containing the access bits buffer
|
||||
handle to be used for dumping the access bits
|
||||
and the buffer where the dumped data will be stored
|
||||
mode[IN] - Mode in which the access bits are dumped
|
||||
|
||||
Error codes:
|
||||
NV_ERR_INVALID_ARGUMENT - If the parameter/s is invalid.
|
||||
NV_ERR_GENERIC - Unexpected error. We try hard to
|
||||
avoid returning this error code,
|
||||
because it is not very informative.
|
||||
*/
|
||||
NV_STATUS nvUvmInterfaceAccessBitsDump(uvmGpuDeviceHandle device,
|
||||
UvmGpuAccessBitsBufferAlloc* pAccessBitsInfo,
|
||||
UVM_ACCESS_BITS_DUMP_MODE mode);
|
||||
|
||||
/*******************************************************************************
|
||||
nvUvmInterfaceInitAccessCntrInfo
|
||||
@@ -1086,20 +1145,20 @@ NV_STATUS nvUvmInterfaceDisableAccessCntr(uvmGpuDeviceHandle device,
|
||||
UvmGpuAccessCntrInfo *pAccessCntrInfo);
|
||||
|
||||
//
|
||||
// Called by the UVM driver to register operations with RM. Only one set of
|
||||
// Called by the UVM driver to register event callbacks with RM. Only one set of
|
||||
// callbacks can be registered by any driver at a time. If another set of
|
||||
// callbacks was already registered, NV_ERR_IN_USE is returned.
|
||||
//
|
||||
NV_STATUS nvUvmInterfaceRegisterUvmCallbacks(struct UvmOpsUvmEvents *importedUvmOps);
|
||||
NV_STATUS nvUvmInterfaceRegisterUvmEvents(struct UvmEventsLinux *importedEvents);
|
||||
|
||||
//
|
||||
// Counterpart to nvUvmInterfaceRegisterUvmCallbacks. This must only be called
|
||||
// if nvUvmInterfaceRegisterUvmCallbacks returned NV_OK.
|
||||
// Counterpart to nvUvmInterfaceRegisterUvmEvents. This must only be called if
|
||||
// nvUvmInterfaceRegisterUvmEvents returned NV_OK.
|
||||
//
|
||||
// Upon return, the caller is guaranteed that any outstanding callbacks are done
|
||||
// and no new ones will be invoked.
|
||||
//
|
||||
void nvUvmInterfaceDeRegisterUvmOps(void);
|
||||
void nvUvmInterfaceDeRegisterUvmEvents(void);
|
||||
|
||||
/*******************************************************************************
|
||||
nvUvmInterfaceGetNvlinkInfo
|
||||
|
||||
@@ -221,9 +221,11 @@ typedef struct UvmGpuChannelInstanceInfo_tag
|
||||
// Ampere+ GPUs
|
||||
volatile NvU32 *pChramChannelRegister;
|
||||
|
||||
// Out: Address of the Runlist PRI Base Register required to ring the
|
||||
// doorbell after clearing the faulted bit.
|
||||
volatile NvU32 *pRunlistPRIBaseRegister;
|
||||
// Out: Address of the doorbell.
|
||||
volatile NvU32 *workSubmissionOffset;
|
||||
|
||||
// Out: channel handle required to ring the doorbell.
|
||||
NvU32 workSubmissionToken;
|
||||
|
||||
// Out: SMC engine id to which the GR channel is bound, or zero if the GPU
|
||||
// does not support SMC or it is a CE channel
|
||||
@@ -365,6 +367,9 @@ typedef struct
|
||||
// True if the CE supports encryption
|
||||
NvBool secure:1;
|
||||
|
||||
// True if the CE can be used for fast scrub
|
||||
NvBool scrub:1;
|
||||
|
||||
// Mask of physical CEs assigned to this LCE
|
||||
//
|
||||
// The value returned by RM for this field may change when a GPU is
|
||||
@@ -383,6 +388,7 @@ typedef enum
|
||||
{
|
||||
UVM_LINK_TYPE_NONE,
|
||||
UVM_LINK_TYPE_PCIE,
|
||||
UVM_LINK_TYPE_PCIE_BAR1,
|
||||
UVM_LINK_TYPE_NVLINK_1,
|
||||
UVM_LINK_TYPE_NVLINK_2,
|
||||
UVM_LINK_TYPE_NVLINK_3,
|
||||
@@ -539,6 +545,12 @@ typedef struct UvmGpuP2PCapsParams_tag
|
||||
// Size is 0 if bar1 p2p is not supported.
|
||||
NvU64 bar1DmaAddress[2];
|
||||
NvU64 bar1DmaSize[2];
|
||||
|
||||
// True if GPU i can use PCIe atomics on locations in GPU[i-1]
|
||||
// BAR1. This implies that GPU[i] can issue PCIe atomics,
|
||||
// GPU[i-1] can accept PCIe atomics, and the bus interconnect
|
||||
// between the two GPUs can correctly route PCIe atomics.
|
||||
NvBool bar1PcieAtomics[2];
|
||||
} UvmGpuP2PCapsParams;
|
||||
|
||||
// Platform-wide information
|
||||
@@ -830,11 +842,7 @@ typedef NV_STATUS (*uvmEventServiceInterrupt_t) (void *pDeviceObject,
|
||||
NV_OK if the UVM driver handled the interrupt
|
||||
NV_ERR_NO_INTR_PENDING if the interrupt is not for the UVM driver
|
||||
*/
|
||||
#if defined (__linux__)
|
||||
typedef NV_STATUS (*uvmEventIsrTopHalf_t) (const NvProcessorUuid *pGpuUuidStruct);
|
||||
#else
|
||||
typedef void (*uvmEventIsrTopHalf_t) (void);
|
||||
#endif
|
||||
|
||||
/*******************************************************************************
|
||||
uvmEventDrainP2P
|
||||
@@ -871,20 +879,24 @@ typedef NV_STATUS (*uvmEventDrainP2P_t) (const NvProcessorUuid *pGpuUuidStruct);
|
||||
*/
|
||||
typedef NV_STATUS (*uvmEventResumeP2P_t) (const NvProcessorUuid *pGpuUuidStruct);
|
||||
|
||||
struct UvmOpsUvmEvents
|
||||
struct UvmEventsLinux
|
||||
{
|
||||
uvmEventIsrTopHalf_t isrTopHalf;
|
||||
uvmEventSuspend_t suspend;
|
||||
uvmEventResume_t resume;
|
||||
uvmEventDrainP2P_t drainP2P;
|
||||
uvmEventResumeP2P_t resumeP2P;
|
||||
};
|
||||
|
||||
struct UvmEventsWindows
|
||||
{
|
||||
uvmEventSuspend_t suspend;
|
||||
uvmEventResume_t resume;
|
||||
uvmEventStartDevice_t startDevice;
|
||||
uvmEventStopDevice_t stopDevice;
|
||||
uvmEventIsrTopHalf_t isrTopHalf;
|
||||
uvmEventStopDevice_t stopDevice;
|
||||
#if defined (_WIN32)
|
||||
uvmEventWddmResetDuringTimeout_t wddmResetDuringTimeout;
|
||||
uvmEventWddmRestartAfterTimeout_t wddmRestartAfterTimeout;
|
||||
uvmEventServiceInterrupt_t serviceInterrupt;
|
||||
#endif
|
||||
uvmEventDrainP2P_t drainP2P;
|
||||
uvmEventResumeP2P_t resumeP2P;
|
||||
};
|
||||
|
||||
#define UVM_CSL_SIGN_AUTH_TAG_SIZE_BYTES 32
|
||||
@@ -1043,6 +1055,22 @@ typedef struct UvmGpuAccessCntrConfig_tag
|
||||
NvU32 threshold;
|
||||
} UvmGpuAccessCntrConfig;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
UVM_ACCESS_BITS_DUMP_MODE_AGGREGATE = 0,
|
||||
UVM_ACCESS_BITS_DUMP_MODE_DIFF = 1,
|
||||
UVM_ACCESS_BITS_DUMP_MODE_CURRENT = 2,
|
||||
} UVM_ACCESS_BITS_DUMP_MODE;
|
||||
|
||||
typedef struct UvmGpuAccessBitsBufferAlloc_tag
|
||||
{
|
||||
NvHandle accessBitsBufferHandle;
|
||||
NvBool bDirtyBits;
|
||||
NvU32 granularity;
|
||||
NV_DECLARE_ALIGNED(NvU64 enabledMask[64], 8);
|
||||
NV_DECLARE_ALIGNED(NvU64 currentBits[64], 8);
|
||||
} UvmGpuAccessBitsBufferAlloc;
|
||||
|
||||
//
|
||||
// When modifying this enum, make sure they are compatible with the mirrored
|
||||
// MEMORY_PROTECTION enum in phys_mem_allocator.h.
|
||||
@@ -1080,6 +1108,7 @@ typedef UvmGpuPagingChannel *gpuPagingChannelHandle;
|
||||
typedef UvmGpuPagingChannelInfo gpuPagingChannelInfo;
|
||||
typedef UvmGpuPagingChannelAllocParams gpuPagingChannelAllocParams;
|
||||
typedef UvmPmaAllocationOptions gpuPmaAllocationOptions;
|
||||
typedef UvmGpuAccessBitsBufferAlloc gpuAccessBitsBufferAlloc;
|
||||
|
||||
typedef struct UvmCslIv
|
||||
{
|
||||
|
||||
@@ -142,6 +142,8 @@ typedef enum {
|
||||
UvmGpuCompressionTypeCount = 2
|
||||
} UvmGpuCompressionType;
|
||||
|
||||
#define UVM_PMA_MAX_LOCALIZED_REGION_COUNT 2
|
||||
|
||||
//
|
||||
// Mirrored in PMA (PMA_STATS)
|
||||
//
|
||||
@@ -153,6 +155,9 @@ typedef struct UvmPmaStatistics_tag
|
||||
volatile NvU64 numPages2mProtected; // PMA-wide 2MB pages count in protected memory
|
||||
volatile NvU64 numFreePages64kProtected; // PMA-wide free 64KB page count in protected memory
|
||||
volatile NvU64 numFreePages2mProtected; // PMA-wide free 2MB pages count in protected memory
|
||||
volatile NvU64 numPages2mLocalizable[UVM_PMA_MAX_LOCALIZED_REGION_COUNT]; // Localizable free 64KB per-uGPU frame count
|
||||
volatile NvU64 numFreePages64kLocalizable[UVM_PMA_MAX_LOCALIZED_REGION_COUNT]; // Localizable free 64KB per-uGPU frame count
|
||||
volatile NvU64 numFreePages2mLocalizable[UVM_PMA_MAX_LOCALIZED_REGION_COUNT]; // Localizable free 64KB per-uGPU frame count
|
||||
} UvmPmaStatistics;
|
||||
|
||||
typedef enum
|
||||
|
||||
@@ -174,10 +174,7 @@ struct NvKmsKapiDeviceResourcesInfo {
|
||||
|
||||
NvBool supportsSyncpts;
|
||||
|
||||
NvBool requiresVrrSemaphores;
|
||||
|
||||
NvBool supportsInputColorRange;
|
||||
NvBool supportsInputColorSpace;
|
||||
NvBool contiguousPhysicalMappings;
|
||||
} caps;
|
||||
|
||||
NvU64 supportedSurfaceMemoryFormats[NVKMS_KAPI_LAYER_MAX];
|
||||
@@ -451,7 +448,6 @@ struct NvKmsKapiHeadReplyConfig {
|
||||
struct NvKmsKapiModeSetReplyConfig {
|
||||
enum NvKmsFlipResult flipResult;
|
||||
NvBool vrrFlip;
|
||||
NvS32 vrrSemaphoreIndex;
|
||||
struct NvKmsKapiHeadReplyConfig
|
||||
headReplyConfig[NVKMS_KAPI_MAX_HEADS];
|
||||
};
|
||||
@@ -1550,22 +1546,6 @@ struct NvKmsKapiFunctionsTable {
|
||||
NvU32 semaphoreIndex
|
||||
);
|
||||
|
||||
/*!
|
||||
* Signal the VRR semaphore at the specified index from the CPU.
|
||||
* If device does not support VRR semaphores, this is a no-op.
|
||||
* Returns true if signal is success or no-op, otherwise returns false.
|
||||
*
|
||||
* \param [in] device A device allocated using allocateDevice().
|
||||
*
|
||||
* \param [in] index The VRR semaphore index to be signalled.
|
||||
*/
|
||||
NvBool
|
||||
(*signalVrrSemaphore)
|
||||
(
|
||||
struct NvKmsKapiDevice *device,
|
||||
NvS32 index
|
||||
);
|
||||
|
||||
/*!
|
||||
* Check or wait on a head's LUT notifier.
|
||||
*
|
||||
|
||||
@@ -213,6 +213,7 @@ int NV_API_CALL os_nv_cap_validate_and_dup_fd (const nv_cap_t *, int
|
||||
void NV_API_CALL os_nv_cap_close_fd (int);
|
||||
NvS32 NV_API_CALL os_imex_channel_get (NvU64);
|
||||
NvS32 NV_API_CALL os_imex_channel_count (void);
|
||||
NV_STATUS NV_API_CALL os_tegra_igpu_perf_boost (void *, NvBool, NvU32);
|
||||
|
||||
NV_STATUS NV_API_CALL os_get_tegra_platform (NvU32 *);
|
||||
enum os_pci_req_atomics_type {
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 1999-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-FileCopyrightText: Copyright (c) 1999-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
@@ -83,6 +83,9 @@ NV_STATUS NV_API_CALL rm_gpu_ops_destroy_access_cntr_info(nvidia_stack_t *, nvg
|
||||
NV_STATUS NV_API_CALL rm_gpu_ops_own_access_cntr_intr(nvidia_stack_t *, nvgpuSessionHandle_t, nvgpuAccessCntrInfo_t, NvBool);
|
||||
NV_STATUS NV_API_CALL rm_gpu_ops_enable_access_cntr(nvidia_stack_t *, nvgpuDeviceHandle_t, nvgpuAccessCntrInfo_t, const nvgpuAccessCntrConfig_t *);
|
||||
NV_STATUS NV_API_CALL rm_gpu_ops_disable_access_cntr(nvidia_stack_t *, nvgpuDeviceHandle_t, nvgpuAccessCntrInfo_t);
|
||||
NV_STATUS NV_API_CALL rm_gpu_ops_access_bits_buffer_alloc(nvidia_stack_t *, nvgpuDeviceHandle_t, nvgpuAccessBitBufferAlloc_t);
|
||||
NV_STATUS NV_API_CALL rm_gpu_ops_access_bits_buffer_free(nvidia_stack_t *, nvgpuDeviceHandle_t, nvgpuAccessBitBufferAlloc_t);
|
||||
NV_STATUS NV_API_CALL rm_gpu_ops_access_bits_dump(nvidia_stack_t *, nvgpuDeviceHandle_t, nvgpuAccessBitBufferAlloc_t, UVM_ACCESS_BITS_DUMP_MODE);
|
||||
NV_STATUS NV_API_CALL rm_gpu_ops_set_page_directory (nvidia_stack_t *, nvgpuAddressSpaceHandle_t, NvU64, unsigned, NvBool, NvU32, NvU64 *);
|
||||
NV_STATUS NV_API_CALL rm_gpu_ops_unset_page_directory (nvidia_stack_t *, nvgpuAddressSpaceHandle_t);
|
||||
NV_STATUS NV_API_CALL rm_gpu_ops_get_nvlink_info(nvidia_stack_t *, nvgpuDeviceHandle_t, nvgpuNvlinkInfo_t);
|
||||
|
||||
Reference in New Issue
Block a user