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This commit is contained in:
Maneet Singh
2025-12-02 15:32:25 -08:00
parent 2af9f1f0f7
commit a5bfb10e75
954 changed files with 421883 additions and 408177 deletions
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35
kernel-open/nvidia-uvm/uvm_hopper_mmu.c
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@@ -1,5 +1,5 @@
/*******************************************************************************
Copyright (c) 2020-2024 NVIDIA Corporation
Copyright (c) 2020-2025 NVIDIA Corporation
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to
@@ -121,7 +121,10 @@ static NvLength allocation_size_hopper(NvU32 depth, NvU64 page_size)
if (depth == 5 && page_size == UVM_PAGE_SIZE_64K)
return 256;
// depth 0 requires only a 16-byte allocation, but it must be 4k aligned.
// depth 0 requires only a 16-byte allocation to house the 2 entries at the
// 0-depth level. Due to HW constraints, the effective minimum allocation
// size is 32 bytes. It must be 4k aligned.
// See comments in uvm_gpu.h:gmmu_pt_depth0_init_required for details.
return 4096;
}
@@ -250,7 +253,7 @@ static NvU64 unmapped_pte_hopper(NvU64 page_size)
HWCONST64(_MMU_VER3, PTE, PCF, NO_VALID_4KB_PAGE);
}
static NvU64 poisoned_pte_hopper(void)
static NvU64 poisoned_pte_hopper(uvm_page_tree_t *tree)
{
// An invalid PTE won't be fatal from faultable units like SM, which is the
// most likely source of bad PTE accesses.
@@ -264,7 +267,7 @@ static NvU64 poisoned_pte_hopper(void)
// be aligned to page_size.
NvU64 phys_addr = 0x2bad000000ULL;
NvU64 pte_bits = make_pte_hopper(UVM_APERTURE_VID, phys_addr, UVM_PROT_READ_ONLY, UVM_MMU_PTE_FLAGS_NONE);
NvU64 pte_bits = tree->hal->make_pte(UVM_APERTURE_VID, phys_addr, UVM_PROT_READ_ONLY, UVM_MMU_PTE_FLAGS_NONE);
return WRITE_HWCONST64(pte_bits, _MMU_VER3, PTE, PCF, PRIVILEGE_RO_NO_ATOMIC_UNCACHED_ACD);
}
@@ -380,10 +383,10 @@ static NvU64 single_pde_hopper(uvm_mmu_page_table_alloc_t *phys_alloc, uvm_page_
pde_bits |= HWCONST64(_MMU_VER3, PDE, APERTURE, VIDEO_MEMORY);
break;
case UVM_APERTURE_SYS_NON_COHERENT:
// SYS_NON_COHERENT aperture is currently only used for testing
// in kernel_driver_get_rm_ptes. Since UVM never places page
// tables in peer memory. SYS_NON_COHERENT should never be used
// in PDEs.
// SYS_NON_COHERENT aperture is currently only used for some
// BAR1 P2P addresses and testing in kernel_driver_get_rm_ptes.
// Since UVM never places page tables in peer memory,
// SYS_NON_COHERENT should never be used in PDEs.
// falls through
default:
UVM_ASSERT_MSG(0, "Invalid aperture: %d\n", phys_alloc->addr.aperture);
@@ -415,10 +418,10 @@ static NvU64 big_half_pde_hopper(uvm_mmu_page_table_alloc_t *phys_alloc, uvm_pag
pde_bits |= HWCONST64(_MMU_VER3, DUAL_PDE, APERTURE_BIG, VIDEO_MEMORY);
break;
case UVM_APERTURE_SYS_NON_COHERENT:
// SYS_NON_COHERENT aperture is currently only used for testing
// in kernel_driver_get_rm_ptes. Since UVM never places page
// tables in peer memory. SYS_NON_COHERENT should never be used
// in PDEs.
// SYS_NON_COHERENT aperture is currently only used for some
// BAR1 P2P addresses and testing in kernel_driver_get_rm_ptes.
// Since UVM never places page tables in peer memory,
// SYS_NON_COHERENT should never be used in PDEs.
// falls through
default:
UVM_ASSERT_MSG(0, "Invalid big aperture %d\n", phys_alloc->addr.aperture);
@@ -453,10 +456,10 @@ static NvU64 small_half_pde_hopper(uvm_mmu_page_table_alloc_t *phys_alloc, uvm_p
pde_bits |= HWCONST64(_MMU_VER3, DUAL_PDE, APERTURE_SMALL, VIDEO_MEMORY);
break;
case UVM_APERTURE_SYS_NON_COHERENT:
// SYS_NON_COHERENT aperture is currently only used for testing
// in kernel_driver_get_rm_ptes. Since UVM never places page
// tables in peer memory. SYS_NON_COHERENT should never be used
// in PDEs.
// SYS_NON_COHERENT aperture is currently only used for some
// BAR1 P2P addresses and testing in kernel_driver_get_rm_ptes.
// Since UVM never places page tables in peer memory,
// SYS_NON_COHERENT should never be used in PDEs.
// falls through
default:
UVM_ASSERT_MSG(0, "Invalid small aperture %d\n", phys_alloc->addr.aperture);