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This commit is contained in:
Maneet Singh
2025-12-02 15:32:25 -08:00
parent 2af9f1f0f7
commit a5bfb10e75
954 changed files with 421883 additions and 408177 deletions
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18
src/common/displayport/inc/dp_configcaps.h
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@@ -552,7 +552,9 @@ namespace DisplayPort
virtual bool readPrSinkDebugInfo(panelReplaySinkDebugInfo *prDbgInfo) = 0;
virtual bool isDpInTunnelingSupported() = 0;
virtual void enableDpTunnelingBwAllocationSupport() = 0;
virtual void setDpTunnelingBwAllocationSupport(bool bEnable) = 0;
virtual bool isDpInTunnelingPanelReplayOptimizationSupported() = 0;
virtual bool isDpInTunnelingBwAllocationSupported() = 0;
virtual bool isDpTunnelBwAllocationEnabled() = 0;
virtual bool getDpTunnelEstimatedBw(NvU8 &estimatedBw) = 0;
virtual bool getDpTunnelGranularityMultiplier(NvU8 &granularityMultiplier) = 0;
@@ -574,6 +576,7 @@ namespace DisplayPort
virtual AuxRetry::status setMainLinkChannelCoding(MainLinkChannelCoding channelCoding) = 0;
virtual void setUSBCCableIDInfo(NV0073_CTRL_DP_USBC_CABLEID_INFO *cableIDInfo) = 0;
virtual void setCableVconnSourceUnknown() = 0;
virtual bool isCableIdHandshakeCompleted() = 0;
virtual ~DPCDHAL() {}
};
@@ -1475,9 +1478,17 @@ namespace DisplayPort
return caps.dpInTunnelingCaps.bIsSupported;
}
virtual void enableDpTunnelingBwAllocationSupport()
virtual bool isDpInTunnelingPanelReplayOptimizationSupported()
{
bEnableDpTunnelBwAllocationSupport = true;
return caps.dpInTunnelingCaps.bIsPanelReplayOptimizationSupported;
}
virtual bool isDpInTunnelingBwAllocationSupported()
{
return caps.dpInTunnelingCaps.bIsBwAllocationSupported;
}
virtual void setDpTunnelingBwAllocationSupport(bool bEnable)
{
bEnableDpTunnelBwAllocationSupport = bEnable;
}
virtual bool isDpTunnelBwAllocationEnabled()
@@ -1505,6 +1516,7 @@ namespace DisplayPort
virtual MainLinkChannelCoding getMainLinkChannelCoding() { return ChannelCoding8B10B; }
virtual void setConnectorTypeC(bool bTypeC) { return; }
virtual void setUSBCCableIDInfo(NV0073_CTRL_DP_USBC_CABLEID_INFO *cableIDInfo) {}
virtual bool isCableIdHandshakeCompleted() { return false; }
};
}

2
src/common/displayport/inc/dp_configcaps2x.h
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@@ -83,6 +83,7 @@ namespace DisplayPort
bool bUHBR_13_5GSupported;
bool bUHBR_20GSupported;
CableType cableType;
bool bHandshakeCompleted;
} rxCableCaps;
/*
@@ -167,6 +168,7 @@ namespace DisplayPort
setIgnoreCableIdCaps(false);
}
virtual void setConnectorTypeC(bool bTypeC);
virtual bool isCableIdHandshakeCompleted() { return caps2x.rxCableCaps.bHandshakeCompleted; }
DPCDHALImpl2x(AuxBus * bus, Timer * timer) : DPCDHALImpl(bus, timer), bIgnoreCableIdCaps(false), bConnectorIsTypeC(false)
{

4
src/common/displayport/inc/dp_connector.h
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@@ -780,6 +780,10 @@ namespace DisplayPort
virtual bool willLinkSupportModeSST(const LinkConfiguration &linkConfig,
const ModesetInfo &modesetInfo,
const DscParams *pDscParams = NULL) = 0;
virtual bool isDpInTunnelingSupported() = 0;
virtual bool isDpInTunnelingPanelReplayOptimizationSupported() = 0;
virtual bool isDpInTunnelingBwAllocationSupported() = 0;
virtual bool getUSBDpInAdapterInfo(NvU32 displayId, NV0073_CTRL_DP_USB4_INFO *pInfo) = 0;
protected:
virtual ~Connector() {}

37
src/common/displayport/inc/dp_connectorimpl.h
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@@ -23,7 +23,7 @@
/******************************* DisplayPort********************************\
* *
* Module: dp_connectorimpl.cpp *
* Module: dp_connectorimpl.h *
* DP connector implementation *
* *
\***************************************************************************/
@@ -137,6 +137,7 @@ namespace DisplayPort
bool bPConConnected; // HDMI2.1-Protocol Converter (Support SRC control mode) connected.
bool bSkipAssessLinkForPCon; // Skip assessLink() for PCON. DD will call assessFRLLink later.
bool bHdcpAuthOnlyOnDemand; // True if only initiate Hdcp authentication on demand and MST won't auto-trigger authenticate at device attach.
bool bHdcpStrmEncrEnblOnlyOnDemand; // True if only initiate Hdcp Stream Encryption Enable on demand and MST won't auto-trigger.
bool bReassessMaxLink; // Retry assessLink() if the first assessed link config is lower than the panel max config.
bool constructorFailed;
@@ -186,6 +187,7 @@ namespace DisplayPort
List activeGroups;
LinkedList<GroupImpl> intransitionGroups;
LinkedList<GroupImpl> addStreamMSTIntransitionGroups;
LinkedList<GroupImpl> hdcpEnableTransitionGroups;
List inactiveGroups;
LinkedList<Device> dscEnabledDevices;
@@ -259,18 +261,18 @@ namespace DisplayPort
// Flag to check if the system is UEFI.
bool bIsUefiSystem;
//
// Flag to ensure we take into account that
// Displayport++ supports HDMI as well.
//
bool bHDMIOnDPPlusPlus;
//
// Flag to enable accounting available DP tunnelling BW while generating PPS
// for the mode
//
bool bOptimizeDscBppForTunnellingBw;
//
// Flag to minimize link config for SST if it is 128b/132b.
// Enables gR-3336 if set.
//
bool bEnable128b132bDSCLnkCfgReduction;
bool bSkipResetLinkStateDuringPlug;
// Flag to check if LT should be skipped.
@@ -340,9 +342,6 @@ namespace DisplayPort
//
bool bForceHeadShutdownOnModeTransition;
// Set to true when we want to skip reset MST_EN before LT
bool bSkipResetMSTMBeforeLt;
bool bReportDeviceLostBeforeNew;
bool bDisableSSC;
bool bEnableFastLT;
@@ -363,6 +362,16 @@ namespace DisplayPort
bool bForceHeadShutdownPerMonitor;
// Use max DSC compression for MST topologies
bool bUseMaxDSCCompressionMST;
// Enable stats collection for compoundQueryAttach()
bool bEnableCqaStatsCollection;
NvU64 cqaStatsMinUs = static_cast<NvU64>(-1);
NvU64 cqaStatsMaxUs = 0;
NvU64 cqaStatsSumUs = 0;
NvU64 cqaStatsCount = 0;
//
// Dual SST Partner connector object pointer
ConnectorImpl *pCoupledConnector;
@@ -556,6 +565,7 @@ namespace DisplayPort
char tagDelayedHdcpCapRead;
char tagDelayedHDCPCPIrqHandling;
char tagDpBwAllocationChanged;
char tagHDCPStreamEncrEnable;
//
// Enable disable TMDS mode
@@ -613,6 +623,7 @@ namespace DisplayPort
unsigned rasterBlankEndX,
unsigned depth) ;
void ensureMstNodesPoweredUp(Group * target);
virtual void readRemoteHdcpCaps();
virtual void notifyAttachEnd(bool modesetCancelled);
virtual void notifyDetachBegin(Group * target);
@@ -632,6 +643,7 @@ namespace DisplayPort
bool allocateMaxDpTunnelBw();
NvU64 getMaxTunnelBw();
void enableDpTunnelingBwAllocationSupport();
void cancelDpTunnelBwAllocation();
void assessLink(LinkTrainingType trainType = NORMAL_LINK_TRAINING);
@@ -798,6 +810,11 @@ namespace DisplayPort
{
activeLinkConfig.setLTCounter(0);
}
virtual bool isDpInTunnelingSupported();
virtual bool isDpInTunnelingPanelReplayOptimizationSupported();
virtual bool isDpInTunnelingBwAllocationSupported();
virtual bool getUSBDpInAdapterInfo(NvU32 displayId, NV0073_CTRL_DP_USB4_INFO *pInfo);
};
//

46
src/common/displayport/inc/dp_connectorimpl2x.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2023-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2023-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -33,6 +33,7 @@
#include "dp_connector.h"
#include "ctrl/ctrl0073/ctrl0073dp.h"
#include "dp_hashmap.h"
namespace DisplayPort
{
@@ -99,6 +100,7 @@ namespace DisplayPort
bool bApplyStuffDummySymbolsWAR;
bool bStuffDummySymbolsFor128b132b;
bool bStuffDummySymbolsFor8b10b;
bool bDisableWatermarkCaching;
// Do not enable downspread while link training.
bool bDisableDownspread;
@@ -111,6 +113,48 @@ namespace DisplayPort
{
return this->bDisableDownspread;
}
private:
class WatermarkCacheElement : public HashMapElement
{
public:
LinkConfiguration m_linkConfig;
ModesetInfo m_modesetInfo;
bool m_forcedDscParamsValid;
DSC_INFO::FORCED_DSC_PARAMS m_forcedDscParams;
NV0073_CTRL_DP_IMP_WATERMARK m_watermark;
WatermarkCacheElement(
const LinkConfiguration &linkConfig, const ModesetInfo &modesetInfo,
const DscParams *pDscParams) :
m_linkConfig(linkConfig), m_modesetInfo(modesetInfo), m_forcedDscParamsValid(false),
m_forcedDscParams{}, m_watermark{}
{
if (pDscParams != NULL && pDscParams->forcedParams != NULL)
{
m_forcedDscParamsValid = true;
m_forcedDscParams = *(pDscParams->forcedParams);
}
}
WatermarkCacheElement(
const LinkConfiguration &linkConfig, const ModesetInfo &modesetInfo,
const DscParams *pDscParams, const NV0073_CTRL_DP_IMP_WATERMARK &watermark) :
m_linkConfig(linkConfig), m_modesetInfo(modesetInfo), m_forcedDscParamsValid(false),
m_forcedDscParams{}, m_watermark(watermark)
{
if (pDscParams != NULL && pDscParams->forcedParams != NULL)
{
m_forcedDscParamsValid = true;
m_forcedDscParams = *(pDscParams->forcedParams);
}
}
virtual ~WatermarkCacheElement() = default;
unsigned int hash() const override;
bool isEqual(const HashMapElement *other) const override;
};
HashMap m_watermarkCache;
};
}

2
src/common/displayport/inc/dp_deviceimpl.h
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@@ -538,6 +538,7 @@ namespace DisplayPort
bool retryRemoteBKSVReadMessage;
bool retryRemoteBCapsReadMessage;
bool retryRemote22BCapsReadMessage;
bool tryRemote1XCaps;
bool bBKSVReadMessagePending;
bool bBCapsReadMessagePending;
@@ -563,6 +564,7 @@ namespace DisplayPort
bool hdcpValidateKsv(const NvU8 *ksv, NvU32 Size);
void handleRemoteDpcdReadDownReply(MessageManager::Message * from);
void readRemoteHdcp1xCaps(void);
void messageFailed(MessageManager::Message * from, NakData * nakData);
void messageCompleted(MessageManager::Message * from);
};

1
src/common/displayport/inc/dp_edid.h
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@@ -174,7 +174,6 @@ namespace DisplayPort
bool bDP2XPreferNonDSCForLowPClk;
bool bSkipCableIdCheck;
bool bAllocateManualTimeslots;
bool bSkipResetMSTMBeforeLt;
}_WARFlags;
_WARFlags WARFlags;

106
src/common/displayport/inc/dp_hashmap.h Normal file
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@@ -0,0 +1,106 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
/******************************* DisplayPort********************************\
* *
* Module: dp_hashmap.h *
* DP hash map implementation *
* *
\***************************************************************************/
#ifndef INCLUDED_DP_HASHMAP_H
#define INCLUDED_DP_HASHMAP_H
#include "dp_list.h"
#include "dp_object.h"
#define DP_HASHMAP_CAPACITY 2000U // Hashmap size and maximum size it can dynamically grow to
#define DP_HASHMAP_PRUNED_SIZE 500U // Desired size of hashmap after pruning
#define DP_HASHMAP_PRUNED_THRESHOLD 500U // Age difference from current age for pruning
namespace DisplayPort
{
struct HashMapElement : virtual public Object, public ListElement
{
friend class HashMap;
HashMapElement() = default;
virtual ~HashMapElement() = default;
/**
* Calculate the hash value of the element.
* @return The hash value of the element.
*/
virtual unsigned int hash() const = 0;
/**
* Determine if two HashMapElements are equal. Used for collision resolution.
* @param other The element to compare to.
* @return True if the elements are equal, false otherwise.
*/
virtual bool isEqual(const HashMapElement *other) const = 0;
private:
unsigned int m_age = 0;
};
//
// Hash map implementation with LRU eviction policy, maintaining a cache capacity of
// DP_HASHMAP_CAPACITY.
//
// The HashMap is implemented as an array of linked lists, where each linked list contains
// elements with the same hash value.
//
// The HashMap is pruned when the number of elements in the HashMap exceeds DP_HASHMAP_CAPACITY
// until the number of elements in the HashMap is DP_HASHMAP_PRUNED_SIZE. Any element whose age
// is greater than current age minus DP_HASHMAP_PRUNED_THRESHOLD is pruned.
//
class HashMap : virtual public Object
{
public:
HashMap() = default;
virtual ~HashMap();
/**
* Get an element from the cache.
* @param query The element to query.
* @return The element from the cache, or NULL if the element is not found.
*/
HashMapElement *get(const HashMapElement *query);
/**
* Add an element to the cache.
* @param element The element to add to the cache. The HashMap will take ownership of the
* element and handle memory management.
*/
void add(HashMapElement *element);
private:
void pruneCache();
List m_hashMap[DP_HASHMAP_CAPACITY];
unsigned int m_currentAge = 0;
unsigned int m_added = 0;
};
}
#endif // INCLUDED_DP_HASHMAP_H

36
src/common/displayport/inc/dp_qse.h Normal file
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@@ -0,0 +1,36 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2010-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
/******************************* DisplayPort *******************************\
* *
* Module: dp_qse.h *
* Class definition for HDCP Query Stream Encryption and relative reading.*
* *
\***************************************************************************/
#ifndef INCLUDED_DP_QSE_H
#define INCLUDED_DP_QSE_H
#include "dp_messagecodings.h"
#include "dp_auxdefs.h"
#endif // INCLUDED_DP_QSE_H

32
src/common/displayport/inc/dp_regkeydatabase.h
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@@ -83,33 +83,40 @@
#define NV_DP2X_REGKEY_VCONN_SOURCE_UNKNOWN_WAR "DP2X_VCONN_SOURCE_UNKNOWN_WAR"
#define NV_DP2X_REGKEY_DISABLE_WATERMARK_CACHING "DP2X_DISABLE_WATERMARK_CACHING"
#define NV_DP2X_REGKEY_DISABLE_EFF_BPP_SST_8b10b "DP2X_REGKEY_DISABLE_EFF_BPP_SST_8b10b"
//
// Bug 4388987 : This regkey will disable reading PCON caps for MST.
//
#define NV_DP_REGKEY_MST_PCON_CAPS_READ_DISABLED "DP_BUG_4388987_WAR"
#define NV_DP_REGKEY_DISABLE_TUNNEL_BW_ALLOCATION "DP_DISABLE_TUNNEL_BW_ALLOCATION"
#define NV_DP_REGKEY_MST_PCON_CAPS_READ_DISABLED "DP_BUG_4388987_WAR"
#define NV_DP_REGKEY_DISABLE_TUNNEL_BW_ALLOCATION "DP_DISABLE_TUNNEL_BW_ALLOCATION"
#define NV_DP_REGKEY_DISABLE_AVOID_HBR3_WAR "DP_DISABLE_AVOID_HBR3_WAR"
#define NV_DP_REGKEY_DISABLE_AVOID_HBR3_WAR "DP_DISABLE_AVOID_HBR3_WAR"
// Bug 4793112 : On eDP panel, do not cache source OUI if it reads zero
#define NV_DP_REGKEY_SKIP_ZERO_OUI_CACHE "DP_SKIP_ZERO_OUI_CACHE"
#define NV_DP_REGKEY_SKIP_ZERO_OUI_CACHE "DP_SKIP_ZERO_OUI_CACHE"
#define NV_DP_REGKEY_ENABLE_FIX_FOR_5147205 "DP_ENABLE_5147205_FIX"
#define NV_DP_REGKEY_ENABLE_FIX_FOR_5147205 "DP_ENABLE_5147205_FIX"
// Bug 5088957 : Force head shutdown in DpLib
#define NV_DP_REGKEY_FORCE_HEAD_SHUTDOWN "DP_WAR_5088957"
#define NV_DP_REGKEY_FORCE_HEAD_SHUTDOWN "DP_WAR_5088957"
// Use max DSC compression for MST topologies
#define NV_DP_REGKEY_USE_MAX_DSC_COMPRESSION_MST "DP_USE_MAX_DSC_COMPRESSION_MST"
// This regkey forces devID to be exposed to vendors via DPCD 0x309 for DSC-enabled SKUs.
#define NV_DP_REGKEY_EXPOSE_DSC_DEVID_WAR "DP_DSC_DEVID_WAR"
#define NV_DP_REGKEY_EXPOSE_DSC_DEVID_WAR "DP_DSC_DEVID_WAR"
// This regkey ensures DPLib takes into account Displayport++ supports HDMI.
#define NV_DP_REGKEY_HDMI_ON_DP_PLUS_PLUS "HDMI_ON_DP_PLUS_PLUS"
#define NV_DP_REGKEY_ENABLE_CQA_STATS_COLLECTION "DP_ENABLE_CQA_STATS_COLLECTION"
#define NV_DP_REGKEY_IGNORE_CAPS_AND_FORCE_HIGHEST_LC "DP_IGNORE_CAPS_AND_FORCE_HIGHEST_LC_WAR"
// This regkey ensures DP IMP takes DP tunnelling BW into account while calculating DSC BPP
#define NV_DP_REGKEY_OPTIMIZE_DSC_BPP_FOR_TUNNELLING_BW "OPTIMIZE_DSC_BPP_FOR_TUNNELLING_BW"
#define NV_DP_REGKEY_IGNORE_CAPS_AND_FORCE_HIGHEST_LC "DP_IGNORE_CAPS_AND_FORCE_HIGHEST_LC_WAR"
// This regkey disables GR-3336 that disables minimizing link config if it is 128b/132b.
#define NV_DP_REGKEY_ENABLE_128b132b_DSC_LNK_CFG_REDUCTION "ENABLE_128b132b_DSC_LNK_CFG_REDUCTION"
//
// Data Base used to store all the regkey values.
@@ -145,6 +152,7 @@ struct DP_REGKEY_DATABASE
NvU32 supportInternalUhbrOnFpga;
bool bIgnoreCableIdCaps;
bool bDisableEffBppSST8b10b;
bool bDisableWatermarkCaching;
bool bMSTPCONCapsReadDisabled;
bool bForceDisableTunnelBwAllocation;
bool bDownspreadDisabled;
@@ -154,9 +162,11 @@ struct DP_REGKEY_DATABASE
bool bEnable5147205Fix;
bool bForceHeadShutdown;
bool bEnableDevId;
bool bHDMIOnDPPlusPlus;
bool bEnableCqaStatsCollection;
bool bIgnoreCapsAndForceHighestLc;
bool bOptimizeDscBppForTunnellingBw;
bool bEnable128b132bDSCLnkCfgReduction;
bool bUseMaxDSCCompressionMST;
};
extern struct DP_REGKEY_DATABASE dpRegkeyDatabase;

17
src/common/displayport/inc/dp_watermark.h
View File

@@ -93,6 +93,23 @@ namespace DisplayPort
bEnablePassThroughForPCON(newBEnablePassThroughForPCON),
mode(newMode),
colorFormat(dpColorFormat) {}
bool operator==(const ModesetInfo &other) const
{
return twoChannelAudioHz == other.twoChannelAudioHz &&
eightChannelAudioHz == other.eightChannelAudioHz &&
pixelClockHz == other.pixelClockHz &&
rasterWidth == other.rasterWidth &&
rasterHeight == other.rasterHeight &&
surfaceWidth == other.surfaceWidth &&
surfaceHeight == other.surfaceHeight &&
depth == other.depth &&
rasterBlankStartX == other.rasterBlankStartX &&
rasterBlankEndX == other.rasterBlankEndX &&
bitsPerComponent == other.bitsPerComponent &&
colorFormat == other.colorFormat &&
bEnableDsc == other.bEnableDsc;
}
};
struct Watermark

7
src/common/displayport/src/dp_configcaps.cpp
View File

@@ -1315,6 +1315,13 @@ AuxRetry::status DPCDHALImpl::setMessagingEnable(bool _uprequestEnable, bool _up
{
bMultistream = false;
}
if (isDpInTunnelingSupported())
{
if (!bMultistream)
return AuxRetry::ack;
}
mstmCtrl = 0;
if (bMultistream)

7
src/common/displayport/src/dp_configcaps2x.cpp
View File

@@ -67,8 +67,8 @@ void DPCDHALImpl2x::parseAndSetCableId(NvU8 cableId)
void DPCDHALImpl2x::performCableIdHandshakeForTypeC()
{
NvU8 txCableCaps = 0;
NvU8 rxCableCaps = 0;
NvU8 txCableCaps = 0;
NvU8 rxCableCaps = 0;
if (AuxRetry::ack !=
bus.read(NV_DPCD20_CABLE_ATTRIBUTES_UPDATED_BY_DPRX, &rxCableCaps, sizeof rxCableCaps))
@@ -79,6 +79,7 @@ void DPCDHALImpl2x::performCableIdHandshakeForTypeC()
{
parseAndSetCableId(rxCableCaps);
}
caps2x.rxCableCaps.bHandshakeCompleted = (rxCableCaps != 0);
if (caps2x.txCableCaps.bIsSupported)
{
@@ -210,6 +211,7 @@ void DPCDHALImpl2x::performCableIdHandshakeForTypeC()
{
parseAndSetCableId(rxCableCaps);
}
caps2x.rxCableCaps.bHandshakeCompleted = (rxCableCaps != 0);
// If no matches, reflect that to the DPRX
if (txCableCaps != rxCableCaps)
@@ -238,6 +240,7 @@ void DPCDHALImpl2x::performCableIdHandshake()
{
parseAndSetCableId(rxCableCaps);
}
caps2x.rxCableCaps.bHandshakeCompleted = NV_TRUE;
}
void DPCDHALImpl2x::setUSBCCableIDInfo(NV0073_CTRL_DP_USBC_CABLEID_INFO *cableIDInfo)

396
src/common/displayport/src/dp_connectorimpl.cpp
View File

@@ -91,6 +91,11 @@ ConnectorImpl::ConnectorImpl(MainLink * main, AuxBus * auxBus, Timer * timer, Co
bFromResumeToNAB(false),
bAttachOnResume(false),
bHdcpAuthOnlyOnDemand(true),
#if DP_OPTION_AUTO_ENABLE_MST_STREAM_ENCR
bHdcpStrmEncrEnblOnlyOnDemand(false),
#else
bHdcpStrmEncrEnblOnlyOnDemand(true),
#endif
constructorFailed(false),
policyModesetOrderMitigation(false),
policyForceLTAtNAB(false),
@@ -183,23 +188,25 @@ void ConnectorImpl::applyRegkeyOverrides(const DP_REGKEY_DATABASE& dpRegkeyDatab
this->bKeepLinkAliveMST = dpRegkeyDatabase.bOptLinkKeptAliveMst;
this->bKeepLinkAliveSST = dpRegkeyDatabase.bOptLinkKeptAliveSst;
}
this->bReportDeviceLostBeforeNew = dpRegkeyDatabase.bReportDeviceLostBeforeNew;
this->bDisableSSC = dpRegkeyDatabase.bSscDisabled;
this->bEnableFastLT = dpRegkeyDatabase.bFastLinkTrainingEnabled;
this->bDscMstCapBug3143315 = dpRegkeyDatabase.bDscMstCapBug3143315;
this->bPowerDownPhyBeforeD3 = dpRegkeyDatabase.bPowerDownPhyBeforeD3;
this->bReportDeviceLostBeforeNew = dpRegkeyDatabase.bReportDeviceLostBeforeNew;
this->bDisableSSC = dpRegkeyDatabase.bSscDisabled;
this->bEnableFastLT = dpRegkeyDatabase.bFastLinkTrainingEnabled;
this->bDscMstCapBug3143315 = dpRegkeyDatabase.bDscMstCapBug3143315;
this->bPowerDownPhyBeforeD3 = dpRegkeyDatabase.bPowerDownPhyBeforeD3;
if (dpRegkeyDatabase.applyMaxLinkRateOverrides)
{
this->maxLinkRateFromRegkey = hal->mapLinkBandiwdthToLinkrate(dpRegkeyDatabase.applyMaxLinkRateOverrides); // BW to linkrate
this->maxLinkRateFromRegkey = hal->mapLinkBandiwdthToLinkrate(dpRegkeyDatabase.applyMaxLinkRateOverrides); // BW to linkrate
}
this->bForceDisableTunnelBwAllocation = dpRegkeyDatabase.bForceDisableTunnelBwAllocation;
this->bSkipZeroOuiCache = dpRegkeyDatabase.bSkipZeroOuiCache;
this->bForceHeadShutdownFromRegkey = dpRegkeyDatabase.bForceHeadShutdown;
this->bEnableDevId = dpRegkeyDatabase.bEnableDevId;
this->bIgnoreCapsAndForceHighestLc = dpRegkeyDatabase.bIgnoreCapsAndForceHighestLc;
this->bDisableEffBppSST8b10b = dpRegkeyDatabase.bDisableEffBppSST8b10b;
this->bHDMIOnDPPlusPlus = dpRegkeyDatabase.bHDMIOnDPPlusPlus;
this->bOptimizeDscBppForTunnellingBw = dpRegkeyDatabase.bOptimizeDscBppForTunnellingBw;
this->bForceDisableTunnelBwAllocation = true;
this->bSkipZeroOuiCache = dpRegkeyDatabase.bSkipZeroOuiCache;
this->bForceHeadShutdownFromRegkey = dpRegkeyDatabase.bForceHeadShutdown;
this->bEnableDevId = dpRegkeyDatabase.bEnableDevId;
this->bIgnoreCapsAndForceHighestLc = dpRegkeyDatabase.bIgnoreCapsAndForceHighestLc;
this->bUseMaxDSCCompressionMST = dpRegkeyDatabase.bUseMaxDSCCompressionMST;
this->bDisableEffBppSST8b10b = dpRegkeyDatabase.bDisableEffBppSST8b10b;
this->bEnableCqaStatsCollection = dpRegkeyDatabase.bEnableCqaStatsCollection;
this->bOptimizeDscBppForTunnellingBw = dpRegkeyDatabase.bOptimizeDscBppForTunnellingBw;
this->bEnable128b132bDSCLnkCfgReduction = dpRegkeyDatabase.bEnable128b132bDSCLnkCfgReduction;
}
void ConnectorImpl::setPolicyModesetOrderMitigation(bool enabled)
@@ -413,8 +420,7 @@ void ConnectorImpl::processNewDevice(const DiscoveryManager::Device & device,
{
case DISPLAY_PORT:
case DISPLAY_PORT_PLUSPLUS: // DP port that supports DP and TMDS
if (bHDMIOnDPPlusPlus &&
existingDev &&
if (existingDev &&
existingDev->connectorType == connectorHDMI)
{
connector = connectorHDMI;
@@ -1251,6 +1257,13 @@ bool ConnectorImpl::compoundQueryAttach(Group * target,
DscParams *pDscParams, // DSC parameters
DP_IMP_ERROR *pErrorCode)
{
NvU64 startUs = 0;
NvU64 endUs = 0;
NvU64 duration = 0;
if (bEnableCqaStatsCollection)
startUs = timer->getTimeUs();
DP_ASSERT(compoundQueryActive);
if (pErrorCode)
*pErrorCode = DP_IMP_ERROR_NONE;
@@ -1283,6 +1296,17 @@ bool ConnectorImpl::compoundQueryAttach(Group * target,
compoundQueryResult = compoundQueryAttachTunneling(_dpModesetParams, pDscParams, pErrorCode);
}
if (bEnableCqaStatsCollection)
{
endUs = timer->getTimeUs();
duration = endUs - startUs;
cqaStatsCount++;
cqaStatsSumUs += duration;
cqaStatsMinUs = DP_MIN(cqaStatsMinUs, duration);
cqaStatsMaxUs = DP_MAX(cqaStatsMaxUs, duration);
}
return compoundQueryResult;
}
@@ -1492,11 +1516,19 @@ bool ConnectorImpl::compoundQueryAttachMSTDsc(Group * target,
if (!pDscParams->bitsPerPixelX16)
{
//
// For now, we will keep a pre defined value for bitsPerPixel for MST = 10
// bitsPerPixelX16 = 160
//
pDscParams->bitsPerPixelX16 = PREDEFINED_DSC_MST_BPPX16;
if (this->bUseMaxDSCCompressionMST)
{
//do max dsc compression so that the desired mode can be supported
pDscParams->bitsPerPixelX16 = MAX_DSC_COMPRESSION_BPPX16;
}
else
{
//
// For now, we will keep a pre defined value for bitsPerPixel for MST = 10
// bitsPerPixelX16 = 160
//
pDscParams->bitsPerPixelX16 = PREDEFINED_DSC_MST_BPPX16;
}
}
else
{
@@ -1865,7 +1897,7 @@ bool ConnectorImpl::compoundQueryAttachSSTDsc
WAR_DATA warData;
NvU64 availableBandwidthBitsPerSecond = 0;
unsigned PPS[DSC_MAX_PPS_SIZE_DWORD];
unsigned bitsPerPixelX16 = pDscParams->bitsPerPixelX16;
unsigned bitsPerPixelX16;
bool result;
NVT_STATUS ppsStatus;
ModesetInfo localModesetInfo = modesetParams.modesetInfo;
@@ -1907,6 +1939,47 @@ bool ConnectorImpl::compoundQueryAttachSSTDsc
}
}
//
// Always force max DSC compression (8bpp) for DP Tunneling SST DSC use case.
// And reduce available BW based on below table
// 4L: <= 88.23%
// 2L: <= 81.34%
// 1L: <= 68.60%
// This is a temporary WAR to unblock validation.
// Should be removed after Bug 5512353 if fixed.
//
if (hal->isDpInTunnelingSupported() && main->isDpTunnelingHwBugWarEnabled())
{
NvU64 bwRestriction = 0U;
// Force compression to max
pDscParams->bitsPerPixelX16 = MAX_DSC_COMPRESSION_BPPX16;
if (lc.lanes == 4U)
{
bwRestriction = 8823U;
}
else if (lc.lanes == 2U)
{
bwRestriction = 8134U;
}
else if (lc.lanes == 1U)
{
bwRestriction = 6860U;
}
else
{
DP_PRINTF(DP_ERROR, "Invalid lane count %u", lc.lanes);
}
if (bwRestriction != 0U)
{
availableBandwidthBitsPerSecond = (availableBandwidthBitsPerSecond * bwRestriction) / 10000ULL;
}
}
bitsPerPixelX16 = pDscParams->bitsPerPixelX16;
warData.dpData.linkRateHz = lc.peakRate;
warData.dpData.bIs128b132bChannelCoding = lc.bIs128b132bChannelCoding;
warData.dpData.bDisableEffBppSST8b10b = this->bDisableEffBppSST8b10b;
@@ -1960,8 +2033,68 @@ bool ConnectorImpl::compoundQueryAttachSSTDsc
// this mode. Refer Bug 200379426.
//
bIsModeSupported = getValidLowestLinkConfig(lc, lowestSelected, localModesetInfo, pDscParams);
//
// If lowest link config is 128b/132b, then we check if bpp
// can be optimized such that link rate can be minimized to 8b/10b.
//
if (this->bEnable128b132bDSCLnkCfgReduction &&
bIsModeSupported &&
lowestSelected.bIs128b132bChannelCoding &&
!pDscParams->bitsPerPixelX16)
{
unsigned i;
LinkConfiguration selectedConfig;
NVT_STATUS ppsStatusLoop;
unsigned bppx16;
NvU32 sliceCountMask;
unsigned PPS_Local[DSC_MAX_PPS_SIZE_DWORD];
dpMemZero(PPS_Local, sizeof(unsigned) * DSC_MAX_PPS_SIZE_DWORD);
for (i = 0; i < numPossibleLnkCfg; i++)
{
if (this->allPossibleLinkCfgs[i].bIs128b132bChannelCoding)
{
continue;
}
selectedConfig = this->allPossibleLinkCfgs[i];
selectedConfig.enableFEC(nativeDev->isFECSupported());
availableBandwidthBitsPerSecond = selectedConfig.convertMinRateToDataRate() * 8 * selectedConfig.lanes;
warData.dpData.linkRateHz = selectedConfig.peakRate;
warData.dpData.bIs128b132bChannelCoding = false;
warData.dpData.laneCount = selectedConfig.lanes;
bppx16 = 0U;
sliceCountMask = 0U;
ppsStatusLoop = DSC_GeneratePPSWithSliceCountMask(&dscInfo,
&modesetInfoDSC,
&warData,
availableBandwidthBitsPerSecond,
(NvU32*)(PPS_Local),
(NvU32*)(&bppx16),
&sliceCountMask);
localModesetInfo.depth = bppx16;
if (ppsStatusLoop == NVT_STATUS_SUCCESS &&
willLinkSupportModeSST(selectedConfig, localModesetInfo, pDscParams))
{
break;
}
}
if (i != numPossibleLnkCfg)
{
pDscParams->sliceCountMask = sliceCountMask;
bitsPerPixelX16 = bppx16;
dpMemCopy(PPS, PPS_Local, sizeof(unsigned) * DSC_MAX_PPS_SIZE_DWORD);
}
}
}
localModesetInfo.depth = bitsPerPixelX16;
if (!bIsModeSupported)
{
pDscParams->bEnableDsc = false;
@@ -2118,6 +2251,25 @@ bool ConnectorImpl::compoundQueryAttachSST(Group * target,
{
// Mode was successful
compoundQueryResult = true;
if (this->bEnable128b132bDSCLnkCfgReduction &&
lc.bIs128b132bChannelCoding &&
!this->preferredLinkConfig.isValid())
{
LinkConfiguration lowestSelected;
getValidLowestLinkConfig(lc, lowestSelected, modesetParams.modesetInfo, NULL);
if (lowestSelected.bIs128b132bChannelCoding)
{
if (compoundQueryAttachSSTIsDscPossible(modesetParams, pDscParams))
{
compoundQueryAttachSSTDsc(modesetParams,
lc,
pDscParams,
pErrorCode);
}
}
}
}
}
@@ -3298,6 +3450,8 @@ bool ConnectorImpl::notifyAttachBegin(Group * target, // Gr
}
}
ensureMstNodesPoweredUp(target);
for (Device * dev = target->enumDevices(0); dev; dev = target->enumDevices(dev))
{
Address::StringBuffer buffer;
@@ -4175,7 +4329,7 @@ void ConnectorImpl::enableDpTunnelingBwAllocationSupport()
return;
}
hal->enableDpTunnelingBwAllocationSupport();
hal->setDpTunnelingBwAllocationSupport(true);
}
/*!
@@ -4189,6 +4343,31 @@ NvU64 ConnectorImpl::getMaxTunnelBw()
return highestAssessedLC.getTotalDataRate() * 8;
}
/*!
* @brief Function to cancel the tunnel bw allocation.
* This function is called when the tunneling chip does not respond to the initial or fallback BW request
* This function also re-assesses the link to get the updated link config
*/
void ConnectorImpl::cancelDpTunnelBwAllocation()
{
LinkConfiguration _origHighestAssessedLC = highestAssessedLC;
hal->setDpTunnelBwAllocation(false);
hal->setDpTunnelingBwAllocationSupport(false);
hal->notifyHPD(true, false);
assessLink();
if (highestAssessedLC != _origHighestAssessedLC)
{
for (Device *i = enumDevices(0); i; i = enumDevices(i))
{
DeviceImpl *dev = (DeviceImpl *)i;
if ((dev->activeGroup != NULL) && (dev->plugged))
{
sink->bandwidthChangeNotification(dev, false);
}
}
}
}
/*!
* @brief Allocate the requested Tunnel BW
*
@@ -4248,7 +4427,8 @@ bool ConnectorImpl::allocateDpTunnelBw(NvU64 bandwidth)
// This shouldn't be Indeterminate. The request can succeed or fail. Indeterminate means something else went wrong
if (requestStatus == Indeterminate)
{
DP_PRINTF(DP_ERROR, "Tunneling chip didn't reply for the BW request\n");
DP_PRINTF(DP_ERROR, "Tunneling chip didn't reply for the initial BW request, cancel tunnel bw allocation support");
cancelDpTunnelBwAllocation();
return false;
}
@@ -4276,6 +4456,8 @@ bool ConnectorImpl::allocateDpTunnelBw(NvU64 bandwidth)
//
if (requestStatus == Indeterminate)
{
DP_PRINTF(DP_ERROR, "Tunneling chip didn't reply for the fallback BW request, cancel tunnel bw allocation support");
cancelDpTunnelBwAllocation();
return false;
}
}
@@ -4815,17 +4997,20 @@ bool ConnectorImpl::isLinkLost()
if (isLinkActive())
{
// Bug 200320196: Add DPCD offline check to avoid link-train in unplugged state.
if (!hal->isDpcdOffline())
if (!(hal->isDpInTunnelingSupported() && main->isDpTunnelingHwBugWarEnabled()))
{
unsigned laneCount;
NvU64 linkRate;
getCurrentLinkConfig(laneCount, linkRate);
//
// Check SW lane count in RM in case it's disabled beyond DPLib.
// Bug 1933751/2897747
//
if (laneCount == laneCount_0)
return true;
if (!hal->isDpcdOffline())
{
unsigned laneCount;
NvU64 linkRate;
getCurrentLinkConfig(laneCount, linkRate);
//
// Check SW lane count in RM in case it's disabled beyond DPLib.
// Bug 1933751/2897747
//
if (laneCount == laneCount_0)
return true;
}
}
// update the sw cache if required
@@ -5123,9 +5308,10 @@ bool ConnectorImpl::trainLinkOptimized(LinkConfiguration lConfig)
}
}
if (bPConConnected)
if (bPConConnected || bKeepOptLinkAlive)
{
// When PCON is connected, always LT to max to avoid LT.
// When bKeepOptLinkAlive is set, we need to LT to max to avoid LT.
bSkipLowestConfigCheck = true;
}
@@ -5700,9 +5886,14 @@ bool ConnectorImpl::validateLinkConfiguration(const LinkConfiguration & lConfig)
bool ConnectorImpl::train(const LinkConfiguration & lConfig, bool force,
LinkTrainingType trainType)
{
LinkTrainingType preferredTrainingType = trainType;
bool result = true;
NvBool bSkipSettingStreamMode = false;
LinkTrainingType preferredTrainingType = trainType;
bool result = true;
if (this->bIgnoreCapsAndForceHighestLc)
{
force = true;
hal->setPowerState(PowerStateD3);
}
// Validate link config against caps
if (!force && !validateLinkConfiguration(lConfig))
@@ -5710,12 +5901,6 @@ bool ConnectorImpl::train(const LinkConfiguration & lConfig, bool force,
return false;
}
if (this->bIgnoreCapsAndForceHighestLc)
{
force = true;
hal->setPowerState(PowerStateD3);
}
//
// Cancel pending HDCP authentication callbacks if have or may interrupt
// active link training that violates spec.
@@ -5751,16 +5936,12 @@ if (this->bIgnoreCapsAndForceHighestLc)
}
//
// Don't set the stream if we're:
// - forcing the config
// - Skipping LT and the flag to skip stream mode setting is true
// - shutting off the link
// Don't set MSTM on the sink if
// 1. we're shutting off the link (lConfig.lanes == 0)
// 2. we're forcing the config (force == true)
// 3. The sink does not support MST
//
bSkipSettingStreamMode = force ||
(bSkipLt && this->bSkipResetMSTMBeforeLt) ||
(lConfig.lanes == 0);
if (!bSkipSettingStreamMode)
if (hal->getSupportsMultistream() && lConfig.lanes != 0 && !force)
{
if (isLinkActive())
{
@@ -6808,7 +6989,6 @@ void ConnectorImpl::notifyLongPulseInternal(bool statusConnected)
{
hal->setSinkCount(1);
}
// disconnect all devices
for (ListElement * i = activeGroups.begin(); i != activeGroups.end(); i = i->next) {
GroupImpl * g = (GroupImpl *)i;
@@ -7081,8 +7261,6 @@ void ConnectorImpl::notifyLongPulseInternal(bool statusConnected)
{
bDelayAfterD3 = true;
}
// Do not reset MST_EN before LT for Sony SDM27Q10S in SST mode
this->bSkipResetMSTMBeforeLt = tmpEdid.WARFlags.bSkipResetMSTMBeforeLt;
// Panels use Legacy address range for interrupt reporting
if (tmpEdid.WARFlags.useLegacyAddress)
@@ -7463,7 +7641,8 @@ void ConnectorImpl::notifyShortPulse()
if (main->isConnectorUSBTypeC() &&
activeLinkConfig.bIs128b132bChannelCoding &&
activeLinkConfig.peakRate > dp2LinkRate_10_0Gbps &&
main->isCableVconnSourceUnknown())
main->isCableVconnSourceUnknown() &&
!hal->isCableIdHandshakeCompleted())
{
//
// Cancel pending HDCP authentication callbacks if have or may interrupt
@@ -7685,6 +7864,7 @@ void ConnectorImpl::cancelHdcpCallbacks()
timer->cancelCallback(this, &tagHDCPReauthentication); // Cancel any queue the auth callback.
timer->cancelCallback(this, &tagDelayedHdcpCapRead); // Cancel any HDCP cap callbacks.
timer->cancelCallback(this, &tagHDCPStreamEncrEnable); // Cancel any queued the stream encr enable callback.
for (ListElement * i = activeGroups.begin(); i != activeGroups.end(); i = i->next)
@@ -8377,7 +8557,6 @@ void ConnectorImpl::configInit()
bDisableDscMaxBppLimit = false;
bForceHeadShutdownOnModeTransition = false;
bDP2XPreferNonDSCForLowPClk = false;
bSkipResetMSTMBeforeLt = false;
}
bool ConnectorImpl::dpUpdateDscStream(Group *target, NvU32 dscBpp)
@@ -8386,3 +8565,104 @@ bool ConnectorImpl::dpUpdateDscStream(Group *target, NvU32 dscBpp)
return true;
}
void ConnectorImpl::ensureMstNodesPoweredUp(Group * target)
{
if (!target)
{
DP_PRINTF(DP_ERROR, "DPCONN> sendPowerUpPhyMessages: NULL target group. Returning Early.");
return;
}
for (Device * dev = target->enumDevices(0); dev; dev = target->enumDevices(dev))
{
// Only send POWER_UP_PHY to video sinks
if (!dev->isVideoSink())
continue;
Address deviceAddress = dev->getTopologyAddress();
Address::StringBuffer buffer;
DP_USED(buffer);
// Only applicable for MST devices (address size > 1)
if (deviceAddress.size() <= 1)
continue;
NakData nakData;
PowerUpPhyMessage powerUpPhyMessage;
// Set message: parent address, port on parent, path message enabled
// isPathMessage = NV_TRUE ensures all branch devices along the path process it
powerUpPhyMessage.set(deviceAddress.parent(), deviceAddress.tail(), NV_TRUE);
DP_PRINTF(DP_NOTICE, "DPCONN> Sending POWER_UP_PHY for device %s (port %d)",
deviceAddress.toString(buffer), deviceAddress.tail());
if (!messageManager->send(&powerUpPhyMessage, nakData))
{
DP_PRINTF(DP_ERROR, "DPCONN> POWER_UP_PHY failed for device %s (reason: %d)",
deviceAddress.toString(buffer), nakData.reason);
switch (nakData.reason)
{
case NakTimeout:
DP_PRINTF(DP_ERROR, "DPCONN> POWER_UP_PHY timeout");
break;
case NakInvalidRAD:
DP_PRINTF(DP_ERROR, "DPCONN> POWER_UP_PHY invalid RAD");
break;
case NakDefer:
DP_PRINTF(DP_ERROR, "DPCONN> POWER_UP_PHY deferred");
break;
default:
DP_PRINTF(DP_ERROR, "DPCONN> POWER_UP_PHY NAK reason: %d", nakData.reason);
break;
}
}
else
{
DP_PRINTF(DP_NOTICE, "DPCONN> POWER_UP_PHY succeeded for device %s",
deviceAddress.toString(buffer));
}
}
}
bool ConnectorImpl::isDpInTunnelingSupported()
{
return hal->isDpInTunnelingSupported();
}
bool ConnectorImpl::isDpInTunnelingPanelReplayOptimizationSupported()
{
return hal->isDpInTunnelingPanelReplayOptimizationSupported();
}
bool ConnectorImpl::isDpInTunnelingBwAllocationSupported()
{
return hal->isDpInTunnelingBwAllocationSupported();
}
bool ConnectorImpl::getUSBDpInAdapterInfo(NvU32 displayId, NV0073_CTRL_DP_USB4_INFO *pInfo)
{
EvoInterface *provider = ((EvoMainLink *)main)->getProvider();
NvU32 nvosStatus;
NV0073_CTRL_CMD_GET_USB_DPIN_ADAPTER_INFO_PARAMS dpParams = {0};
if (!pInfo)
{
DP_ASSERT(0 && "Invalida argument");
return false;
}
dpParams.subDeviceInstance = provider->getSubdeviceIndex();
dpParams.displayId = displayId;
nvosStatus = provider->rmControl0073(NV0073_CTRL_CMD_GET_USB_DPIN_ADAPTER_INFO, &dpParams, sizeof dpParams);
if (nvosStatus != NVOS_STATUS_SUCCESS)
{
DP_ASSERT(0 && "Unable to get USB4 DP_IN adapter Info");
return false;
}
dpMemCopy(pInfo, &(dpParams.usb4Info), sizeof(dpParams.usb4Info));
return true;
}

123
src/common/displayport/src/dp_connectorimpl2x.cpp
View File

@@ -56,6 +56,47 @@ using namespace DisplayPort;
//
NvU32 bSupportInternalUhbrOnFpga;
unsigned int ConnectorImpl2x::WatermarkCacheElement::hash() const
{
// Hash the parameters used in DP IMP calculation
unsigned int hash =
(m_linkConfig.lanes ^ static_cast<unsigned int>(m_linkConfig.peakRate) ^
static_cast<unsigned int>(m_linkConfig.bIs128b132bChannelCoding) ^
static_cast<unsigned int>(m_linkConfig.bEnableFEC) ^
static_cast<unsigned int>(m_linkConfig.multistream)) ^
(m_modesetInfo.twoChannelAudioHz ^ m_modesetInfo.eightChannelAudioHz ^
static_cast<unsigned int>(m_modesetInfo.pixelClockHz) ^ m_modesetInfo.rasterWidth ^
m_modesetInfo.surfaceWidth ^ m_modesetInfo.surfaceHeight ^ m_modesetInfo.depth ^
m_modesetInfo.rasterBlankStartX ^ m_modesetInfo.rasterBlankEndX ^
m_modesetInfo.bitsPerComponent ^ static_cast<unsigned int>(m_modesetInfo.colorFormat) ^
static_cast<unsigned int>(m_modesetInfo.bEnableDsc));
if (m_forcedDscParamsValid)
{
hash ^= (m_forcedDscParams.sliceCount ^ m_forcedDscParams.sliceWidth ^
m_forcedDscParams.sliceHeight ^ m_forcedDscParams.dscRevision.versionMajor ^
m_forcedDscParams.dscRevision.versionMinor);
}
return hash;
}
bool ConnectorImpl2x::WatermarkCacheElement::isEqual(const HashMapElement *other) const
{
const auto *pOther = (const WatermarkCacheElement *)other;
if (pOther == NULL)
return false;
// Equality is based on the parameters used in DP IMP calculation
return (m_linkConfig == pOther->m_linkConfig && m_modesetInfo == pOther->m_modesetInfo) &&
((m_forcedDscParamsValid == false && pOther->m_forcedDscParamsValid == false) ||
(m_forcedDscParamsValid == true && pOther->m_forcedDscParamsValid == true &&
m_forcedDscParams.sliceCount == pOther->m_forcedDscParams.sliceCount &&
m_forcedDscParams.sliceWidth == pOther->m_forcedDscParams.sliceWidth &&
m_forcedDscParams.sliceHeight == pOther->m_forcedDscParams.sliceHeight &&
m_forcedDscParams.dscRevision.versionMajor == pOther->m_forcedDscParams.dscRevision.versionMajor &&
m_forcedDscParams.dscRevision.versionMinor == pOther->m_forcedDscParams.dscRevision.versionMinor));
}
/*!
* @brief Convert data rate to link rate
*
@@ -72,6 +113,9 @@ void ConnectorImpl2x::applyDP2xRegkeyOverrides()
this->bSupportUHBR5_00 = dpRegkeyDatabase.supportInternalUhbrOnFpga & NV_DP2X_REGKEY_FPGA_UHBR_SUPPORT_5_0G;
this->maxLinkRateFromRegkey = dpRegkeyDatabase.applyMaxLinkRateOverrides;
bSupportInternalUhbrOnFpga = dpRegkeyDatabase.supportInternalUhbrOnFpga;
// Disabling watermark caching by default on 590 irrespective of the regkey
// TODO: Set it back to read regkey value while fixing the issues on 595
this->bDisableWatermarkCaching = true;
if (dpRegkeyDatabase.bIgnoreCableIdCaps)
{
hal->setIgnoreCableIdCaps(true);
@@ -110,6 +154,9 @@ bool ConnectorImpl2x::getValidLowestLinkConfig
{
// Get next entry.
lowestSelected = this->allPossibleLinkCfgs[i+1];
// Update enhancedFraming/bDisableDownspread/bEnableFEC for target config
lowestSelected.enhancedFraming = lConfig.enhancedFraming;
lowestSelected.bDisableDownspread = lConfig.bDisableDownspread;
lowestSelected.enableFEC(lConfig.bEnableFEC);
}
}
@@ -123,23 +170,22 @@ bool ConnectorImpl2x::willLinkSupportModeSST
const DscParams *pDscParams
)
{
NvBool result = false;
LinkConfiguration lc = linkConfig;
if (!main->isSupportedDPLinkConfig(lc))
return false;
// no headIndex (default 0) for mode enumeration.
result = willLinkSupportMode(linkConfig, modesetInfo, 0, NULL, pDscParams);
if (result && linkConfig.bIs128b132bChannelCoding)
if (linkConfig.bIs128b132bChannelCoding)
{
unsigned base_pbn, slots, slots_pbn;
lc.pbnRequired(modesetInfo, base_pbn, slots, slots_pbn);
if (slots_pbn > lc.pbnTotal())
{
result = false;
return false;
}
}
return result;
// no headIndex (default 0) for mode enumeration.
return willLinkSupportMode(linkConfig, modesetInfo, 0, NULL, pDscParams);
}
bool ConnectorImpl2x::willLinkSupportMode
@@ -164,6 +210,28 @@ bool ConnectorImpl2x::willLinkSupportMode
DP_ASSERT(this->isFECSupported());
if (!this->bDisableWatermarkCaching)
{
// Check if the watermark is already cached
WatermarkCacheElement query{linkConfig, modesetInfo, pDscParams};
auto *pCachedWatermark = (WatermarkCacheElement *)m_watermarkCache.get(&query);
if (pCachedWatermark != NULL)
{
if (watermark != NULL)
{
// If there's a cache hit, return the cached watermark
watermark->waterMark = pCachedWatermark->m_watermark.waterMark;
watermark->tuSize = pCachedWatermark->m_watermark.tuSize;
watermark->hBlankSym = pCachedWatermark->m_watermark.hBlankSym;
watermark->vBlankSym = pCachedWatermark->m_watermark.vBlankSym;
watermark->effectiveBpp = pCachedWatermark->m_watermark.effectiveBpp;
}
return pCachedWatermark->m_watermark.bIsModePossible;
}
}
// If there's no cache hit, calculate the watermark and add it to the cache
EvoInterface *provider = ((EvoMainLink *)main)->getProvider();
NvU32 nvosStatus = NVOS_STATUS_SUCCESS;
@@ -207,13 +275,20 @@ bool ConnectorImpl2x::willLinkSupportMode
nvosStatus = provider->rmControl0073(NV0073_CTRL_CMD_CALCULATE_DP_IMP,
&impParams, sizeof impParams);
if ((nvosStatus == NVOS_STATUS_SUCCESS) && (watermark != NULL))
if (nvosStatus == NVOS_STATUS_SUCCESS)
{
watermark->waterMark = impParams.watermark.waterMark;
watermark->tuSize = impParams.watermark.tuSize;
watermark->hBlankSym = impParams.watermark.hBlankSym;
watermark->vBlankSym = impParams.watermark.vBlankSym;
watermark->effectiveBpp = impParams.watermark.effectiveBpp;
if (watermark != NULL)
{
watermark->waterMark = impParams.watermark.waterMark;
watermark->tuSize = impParams.watermark.tuSize;
watermark->hBlankSym = impParams.watermark.hBlankSym;
watermark->vBlankSym = impParams.watermark.vBlankSym;
watermark->effectiveBpp = impParams.watermark.effectiveBpp;
}
if (!this->bDisableWatermarkCaching)
m_watermarkCache.add(new WatermarkCacheElement(
linkConfig, modesetInfo, pDscParams, impParams.watermark));
}
return impParams.watermark.bIsModePossible;
@@ -522,8 +597,8 @@ bool ConnectorImpl2x::compoundQueryAttachMSTGeneric(Group * target,
else
{
//
// If DSC is enabled bpp will already be multiplied by 16, we need to mulitply by another 16
// to match scalar of 256 which is used in non-DSC case.
// If DSC is enabled bpp will already be multiplied by 16, we need to mulitply by another 16
// to match scalar of 256 which is used in non-DSC case.
//
localInfo->localModesetInfo.depth = localInfo->localModesetInfo.depth * EFF_BPP_DSC_SCALER;
}
@@ -574,12 +649,19 @@ bool ConnectorImpl2x::compoundQueryAttachMSTGeneric(Group * target,
tail->bandwidth.compound_query_state.totalTimeSlots)
{
compoundQueryResult = false;
tail->bandwidth.compound_query_state.timeslots_used_by_query -= linkConfig->slotsForPBN(base_pbn);
tail->bandwidth.compound_query_state.bandwidthAllocatedForIndex &= ~(1 << compoundQueryCount);
SET_DP_IMP_ERROR(pErrorCode, DP_IMP_ERROR_INSUFFICIENT_BANDWIDTH)
}
}
tail = (DeviceImpl*)tail->getParent();
}
}
// If the compoundQueryResult is false, we need to reset the compoundQueryLocalLinkPBN
if (!compoundQueryResult)
{
compoundQueryLocalLinkPBN -= slots_pbn;
}
}
else
{
@@ -668,6 +750,8 @@ bool ConnectorImpl2x::notifyAttachBegin(Group *target, const DpModesetParams &mo
return false;
}
ensureMstNodesPoweredUp(target);
for (Device * dev = target->enumDevices(0); dev; dev = target->enumDevices(dev))
{
Address::StringBuffer buffer;
@@ -676,7 +760,7 @@ bool ConnectorImpl2x::notifyAttachBegin(Group *target, const DpModesetParams &mo
dev->isVideoSink() ? "VIDEO" : "BRANCH");
//
// Note: This makes an assumption that all devices in the group have the same values for
// Note: This makes an assumption that all devices in the group have the same values for
// bApplyStuffDummySymbolsWAR, bStuffDummySymbolsFor8b10b and bStuffDummySymbolsFor128b132b
//
bApplyStuffDummySymbolsWAR |= ((DeviceImpl *)dev)->getApplyStuffDummySymbolsWAR();
@@ -814,7 +898,7 @@ bool ConnectorImpl2x::notifyAttachBegin(Group *target, const DpModesetParams &mo
NvU32 bitsPerLane = (NvU32)NV_CEIL(modesetParams.modesetInfo.surfaceWidth, LOGICAL_LANES) * depth;
NvU32 totalSymbolsPerLane = (NvU32)NV_CEIL(bitsPerLane, symbolSize);
NvU32 totalSymbols = totalSymbolsPerLane * LOGICAL_LANES;
targetImpl->lastModesetInfo.depth = (NvU32)NV_CEIL((totalSymbols * symbolSize * EFF_BPP_NON_DSC_SCALER),
targetImpl->lastModesetInfo.depth = (NvU32)NV_CEIL((totalSymbols * symbolSize * EFF_BPP_NON_DSC_SCALER),
modesetParams.modesetInfo.surfaceWidth);
}
}
@@ -872,8 +956,8 @@ bool ConnectorImpl2x::notifyAttachBegin(Group *target, const DpModesetParams &mo
// Apply dummy symbol WAR if link training succeeded and device requires dummy symbols
// for the channel coding mode as per the device's WAR flags
if (bLinkTrainingStatus &&
bApplyStuffDummySymbolsWAR &&
if (bLinkTrainingStatus &&
bApplyStuffDummySymbolsWAR &&
((activeLinkConfig.bIs128b132bChannelCoding && bStuffDummySymbolsFor128b132b) ||
((!activeLinkConfig.bIs128b132bChannelCoding) && bStuffDummySymbolsFor8b10b)))
{
@@ -1274,7 +1358,8 @@ bool ConnectorImpl2x::train(const LinkConfiguration &lConfig, bool force, LinkTr
// and VCONN source is unknown.
if (!trainResult && main->isConnectorUSBTypeC() &&
lConfig.bIs128b132bChannelCoding && lConfig.peakRate > dp2LinkRate_10_0Gbps &&
main->isCableVconnSourceUnknown())
main->isCableVconnSourceUnknown() &&
!hal->isCableIdHandshakeCompleted())
{
hal->overrideCableIdCap(lConfig.peakRate, false);
}

221
src/common/displayport/src/dp_deviceimpl.cpp
View File

@@ -3306,6 +3306,8 @@ bool DeviceImpl::setModeList(DisplayPort::DpModesetParams *modeList, unsigned nu
maxModeBwRequired = 0;
DP_PRINTF(DP_NOTICE, "DP-DEV> setModeList: numModes: %d", numModes);
for (unsigned modeItr = 0; modeItr < numModes; modeItr++)
{
connector->beginCompoundQuery();
@@ -3335,9 +3337,8 @@ bool DeviceImpl::setModeList(DisplayPort::DpModesetParams *modeList, unsigned nu
DP_PRINTF(DP_INFO, "Computed Max mode BW: %" NvU64_fmtu " Mbps", maxModeBwRequired / (1000 * 1000));
connector->updateDpTunnelBwAllocation();
return connector->updateDpTunnelBwAllocation();
return true;
}
void
@@ -3359,43 +3360,41 @@ DeviceHDCPDetection::start()
NativeDPCDHDCPCAPRead:
BCaps bCaps = {0};
unsigned char hdcp22BCAPS[HDCP22_BCAPS_SIZE];
parent->hal->getBCaps(bCaps, parent->BCAPS);
*(parent->nvBCaps) = *(parent->BCAPS);
// Check if hdcp2.x only device and probe hdcp22Bcaps.
parent->hal->getHdcp22BCaps(bCaps, hdcp22BCAPS);
if (bCaps.HDCPCapable)
{
NvU8 tempBKSV[HDCP_KSV_SIZE] = {0};
if (parent->hal->getBKSV(tempBKSV))
{
if (hdcpValidateKsv(tempBKSV, HDCP_KSV_SIZE))
{
for (unsigned i=0; i<HDCP_KSV_SIZE; i++)
parent->BKSV[i] = tempBKSV[i];
}
}
parent->nvBCaps[0] = FLD_SET_DRF_NUM(_DPCD, _HDCP_BCAPS_OFFSET,
_HDCP_CAPABLE, bCaps.HDCPCapable,
parent->nvBCaps[0]) |
FLD_SET_DRF_NUM(_DPCD, _HDCP_BCAPS_OFFSET, _HDCP_REPEATER,
bCaps.repeater, parent->nvBCaps[0]);
//
// No need to validate 1.x bksv here and hdcp22 authentication would
// validate certificate with bksv in uproc.
//
parent->isHDCPCap = True;
waivePendingHDCPCapDoneNotification();
return;
}
else
{
unsigned char hdcp22BCAPS[HDCP22_BCAPS_SIZE];
// Check if hdcp2.x only device and probe hdcp22Bcaps.
parent->hal->getHdcp22BCaps(bCaps, hdcp22BCAPS);
if (bCaps.HDCPCapable)
{
parent->nvBCaps[0] = FLD_SET_DRF_NUM(_DPCD, _HDCP_BCAPS_OFFSET,
_HDCP_CAPABLE, bCaps.HDCPCapable,
parent->nvBCaps[0]) |
FLD_SET_DRF_NUM(_DPCD, _HDCP_BCAPS_OFFSET, _HDCP_REPEATER,
bCaps.repeater, parent->nvBCaps[0]);
//
// No need to validate 1.x bksv here and hdcp22 authentication would
// validate certificate with bksv in uproc.
//
else
{
parent->hal->getBCaps(bCaps, parent->BCAPS);
*(parent->nvBCaps) = *(parent->BCAPS);
if (bCaps.HDCPCapable)
{
NvU8 tempBKSV[HDCP_KSV_SIZE] = {0};
if (parent->hal->getBKSV(tempBKSV))
{
if (hdcpValidateKsv(tempBKSV, HDCP_KSV_SIZE))
{
for (unsigned i=0; i<HDCP_KSV_SIZE; i++)
parent->BKSV[i] = tempBKSV[i];
}
}
parent->isHDCPCap = True;
waivePendingHDCPCapDoneNotification();
return;
@@ -3426,6 +3425,27 @@ DeviceHDCPDetection::messageCompleted
}
}
void
DeviceHDCPDetection::readRemoteHdcp1xCaps
(
void
)
{
Address parentAddress = parent->address.parent();
//For DP1.4 atomic messaging, HDCP detection can be delayed, so lowering the priority.
remoteBKSVReadMessage.setMessagePriority(NV_DP_SBMSG_PRIORITY_LEVEL_DEFAULT);
remoteBKSVReadMessage.set(parentAddress, parent->address.tail(), NV_DPCD_HDCP_BKSV_OFFSET, HDCP_KSV_SIZE);
bksvReadCompleted = false;
bBKSVReadMessagePending = true;
messageManager->post(&remoteBKSVReadMessage, this);
//For DP1.4 atomic messaging, HDCP detection can be delayed, so lowering the priority.
remoteBCapsReadMessage.setMessagePriority(NV_DP_SBMSG_PRIORITY_LEVEL_DEFAULT);
remoteBCapsReadMessage.set(parentAddress, parent->address.tail(), NV_DPCD_HDCP_BCAPS_OFFSET, HDCP_BCAPS_SIZE);
bCapsReadCompleted = false;
bBCapsReadMessagePending = true;
messageManager->post(&remoteBCapsReadMessage, this);
}
void
DeviceHDCPDetection::handleRemoteDpcdReadDownReply
(
@@ -3438,7 +3458,55 @@ DeviceHDCPDetection::handleRemoteDpcdReadDownReply
Address::StringBuffer sb;
DP_USED(sb);
if (from == &remoteBKSVReadMessage)
if (from == &remote22BCapsReadMessage)
{
bCapsReadCompleted = true;
bBCapsReadMessagePending = false;
DP_PRINTF(DP_NOTICE, "DP-QM> REMOTE_DPCD_READ(22BCaps) {%p} at '%s' completed",
(MessageManager::Message *)&remote22BCapsReadMessage,
parent->address.toString(sb));
if (remote22BCapsReadMessage.replyNumOfBytesReadDPCD() != HDCP22_BCAPS_SIZE)
{
DP_ASSERT(0 && "Incomplete 22BCaps in remote DPCD read message");
parent->isHDCPCap = False;
// Destruct only when no message is pending
if (!(bBKSVReadMessagePending || bBCapsReadMessagePending))
{
parent->isDeviceHDCPDetectionAlive = false;
delete this;
}
return;
}
DP_ASSERT(remote22BCapsReadMessage.replyPortNumber() == parent->address.tail());
if (!!(*remote22BCapsReadMessage.replyGetData() & 0x2))
{
unsigned char hdcp22BCAPS;
bksvReadCompleted = true;
bBKSVReadMessagePending = false;
hdcp22BCAPS = *remote22BCapsReadMessage.replyGetData();
parent->nvBCaps[0] = FLD_SET_DRF_NUM(_DPCD, _HDCP_BCAPS_OFFSET,
_HDCP_CAPABLE, (hdcp22BCAPS & 0x2) ? 1 : 0,
parent->nvBCaps[0]) |
FLD_SET_DRF_NUM(_DPCD, _HDCP_BCAPS_OFFSET, _HDCP_REPEATER,
(hdcp22BCAPS & 0x1) ? 1 : 0, parent->nvBCaps[0]);
// hdcp22 will validate certificate's bksv directly.
isBCapsHDCP = isValidBKSV = true;
DP_PRINTF(DP_NOTICE, "DP-QM> Device at '%s' is with valid 22BCAPS : %x",
parent->address.toString(sb), *remote22BCapsReadMessage.replyGetData());
}
else
{
readRemoteHdcp1xCaps();
}
}
else if (from == &remoteBKSVReadMessage)
{
bksvReadCompleted = true;
bBKSVReadMessagePending = false;
@@ -3525,59 +3593,6 @@ DeviceHDCPDetection::handleRemoteDpcdReadDownReply
*(parent->nvBCaps) = *(parent->BCAPS);
}
}
else
{
DP_PRINTF(DP_NOTICE, "DP-QM> Device at '%s' is without valid BKSV and BCAPS, thus try 22BCAPS", parent->address.toString(sb));
Address parentAddress = parent->address.parent();
remote22BCapsReadMessage.setMessagePriority(NV_DP_SBMSG_PRIORITY_LEVEL_DEFAULT);
remote22BCapsReadMessage.set(parentAddress, parent->address.tail(), NV_DPCD_HDCP22_BCAPS_OFFSET, HDCP22_BCAPS_SIZE);
bCapsReadCompleted = false;
bBCapsReadMessagePending = true;
messageManager->post(&remote22BCapsReadMessage, this);
}
}
}
else if (from == &remote22BCapsReadMessage)
{
bCapsReadCompleted = true;
bBCapsReadMessagePending = false;
DP_PRINTF(DP_NOTICE, "DP-QM> REMOTE_DPCD_READ(22BCaps) {%p} at '%s' completed",
(MessageManager::Message *)&remote22BCapsReadMessage,
parent->address.toString(sb));
if (remote22BCapsReadMessage.replyNumOfBytesReadDPCD() != HDCP22_BCAPS_SIZE)
{
DP_ASSERT(0 && "Incomplete 22BCaps in remote DPCD read message");
parent->isHDCPCap = False;
// Destruct only when no message is pending
if (!(bBKSVReadMessagePending || bBCapsReadMessagePending))
{
parent->isDeviceHDCPDetectionAlive = false;
delete this;
}
return;
}
DP_ASSERT(remote22BCapsReadMessage.replyPortNumber() == parent->address.tail());
if (!!(*remote22BCapsReadMessage.replyGetData() & 0x2))
{
unsigned char hdcp22BCAPS;
hdcp22BCAPS = *remote22BCapsReadMessage.replyGetData();
parent->nvBCaps[0] = FLD_SET_DRF_NUM(_DPCD, _HDCP_BCAPS_OFFSET,
_HDCP_CAPABLE, (hdcp22BCAPS & 0x2) ? 1 : 0,
parent->nvBCaps[0]) |
FLD_SET_DRF_NUM(_DPCD, _HDCP_BCAPS_OFFSET, _HDCP_REPEATER,
(hdcp22BCAPS & 0x1) ? 1 : 0, parent->nvBCaps[0]);
// hdcp22 will validate certificate's bksv directly.
isBCapsHDCP = isValidBKSV = true;
DP_PRINTF(DP_NOTICE, "DP-QM> Device at '%s' is with valid 22BCAPS : %x",
parent->address.toString(sb), *remote22BCapsReadMessage.replyGetData());
}
}
@@ -3694,11 +3709,23 @@ DeviceHDCPDetection::messageFailed
timer->queueCallback(this, "22BCaps", DPCD_REMOTE_DPCD_READ_MESSAGE_COOLDOWN_BKSV);
return;
}
//
// If message failed is called after all retries have expired or due to
// any other reason then reset the bBCapsReadMessagePending flag
//
bBCapsReadMessagePending = false;
else
{
//
// If message failed is called after all retries have expired (or) due to
// any other reason like NakNoResources/NakUndefined/NakDpcdFail etc
// then reset the bBCapsReadMessagePending flag and try to read HDCP1X
// capability
//
Address::StringBuffer sb;
DP_USED(sb);
DP_PRINTF(DP_ERROR, "DP-QM> Message REMOTE_DPC_READ(22BCaps) {%p} at '%s' failed.",
from, parent->address.toString(sb));
bBCapsReadMessagePending = false;
tryRemote1XCaps = true;
timer->queueCallback(this, "22BCaps-Try1X", DPCD_REMOTE_DPCD_READ_MESSAGE_COOLDOWN_BKSV);
return;
}
}
parent->isHDCPCap = False;
@@ -3750,6 +3777,12 @@ DeviceHDCPDetection::expired
retryRemote22BCapsReadMessage = false;
bBCapsReadMessagePending = false;
}
else if (tryRemote1XCaps)
{
tryRemote1XCaps = false;
bBKSVReadMessagePending = false;
bBCapsReadMessagePending = false;
}
if (!(bBKSVReadMessagePending || bBCapsReadMessagePending))
{
@@ -3807,6 +3840,12 @@ DeviceHDCPDetection::expired
messageManager->post(&remote22BCapsReadMessage, this);
}
if (tryRemote1XCaps)
{
tryRemote1XCaps = false;
readRemoteHdcp1xCaps();
}
}
DeviceHDCPDetection::~DeviceHDCPDetection()

73
src/common/displayport/src/dp_evoadapter.cpp
View File

@@ -76,41 +76,44 @@ const struct
DP_REG_VAL_TYPE valueType;
} DP_REGKEY_TABLE [] =
{
{NV_DP_REGKEY_OVERRIDE_DPCD_REV, &dpRegkeyDatabase.dpcdRevOveride, DP_REG_VAL_U32},
{NV_DP_REGKEY_DISABLE_SSC, &dpRegkeyDatabase.bSscDisabled, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_ENABLE_FAST_LINK_TRAINING, &dpRegkeyDatabase.bFastLinkTrainingEnabled, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_DISABLE_MST, &dpRegkeyDatabase.bMstDisabled, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_ENABLE_INBAND_STEREO_SIGNALING, &dpRegkeyDatabase.bInbandStereoSignalingEnabled, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_SKIP_POWEROFF_EDP_IN_HEAD_DETACH, &dpRegkeyDatabase.bPoweroffEdpInHeadDetachSkipped, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_ENABLE_OCA_LOGGING, &dpRegkeyDatabase.bOcaLoggingEnabled, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_REPORT_DEVICE_LOST_BEFORE_NEW, &dpRegkeyDatabase.bReportDeviceLostBeforeNew, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_APPLY_LINK_BW_OVERRIDE_WAR, &dpRegkeyDatabase.bLinkBwOverrideWarApplied, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_APPLY_MAX_LINK_RATE_OVERRIDES, &dpRegkeyDatabase.applyMaxLinkRateOverrides, DP_REG_VAL_U32},
{NV_DP_REGKEY_DISABLE_DSC, &dpRegkeyDatabase.bDscDisabled, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_SKIP_ASSESSLINK_FOR_EDP, &dpRegkeyDatabase.bAssesslinkForEdpSkipped, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_MST_AUTO_HDCP_AUTH_AT_ATTACH, &dpRegkeyDatabase.bMstAutoHdcpAuthAtAttach, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_ENABLE_MSA_OVER_MST, &dpRegkeyDatabase.bMsaOverMstEnabled, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_KEEP_OPT_LINK_ALIVE, &dpRegkeyDatabase.bOptLinkKeptAlive, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_KEEP_OPT_LINK_ALIVE_MST, &dpRegkeyDatabase.bOptLinkKeptAliveMst, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_KEEP_OPT_LINK_ALIVE_SST, &dpRegkeyDatabase.bOptLinkKeptAliveSst, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_FORCE_EDP_ILR, &dpRegkeyDatabase.bBypassEDPRevCheck, DP_REG_VAL_BOOL},
{NV_DP_DSC_MST_CAP_BUG_3143315, &dpRegkeyDatabase.bDscMstCapBug3143315, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_POWER_DOWN_PHY, &dpRegkeyDatabase.bPowerDownPhyBeforeD3, DP_REG_VAL_BOOL},
{NV_DP2X_REGKEY_FPGA_UHBR_SUPPORT, &dpRegkeyDatabase.supportInternalUhbrOnFpga, DP_REG_VAL_U32},
{NV_DP2X_IGNORE_CABLE_ID_CAPS, &dpRegkeyDatabase.bIgnoreCableIdCaps, DP_REG_VAL_BOOL},
{NV_DP2X_REGKEY_VCONN_SOURCE_UNKNOWN_WAR, &dpRegkeyDatabase.bCableVconnSourceUnknownWar, DP_REG_VAL_BOOL},
{NV_DP2X_REGKEY_DISABLE_EFF_BPP_SST_8b10b, &dpRegkeyDatabase.bDisableEffBppSST8b10b, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_MST_PCON_CAPS_READ_DISABLED, &dpRegkeyDatabase.bMSTPCONCapsReadDisabled, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_DISABLE_TUNNEL_BW_ALLOCATION, &dpRegkeyDatabase.bForceDisableTunnelBwAllocation, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_DISABLE_DOWNSPREAD, &dpRegkeyDatabase.bDownspreadDisabled, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_DISABLE_AVOID_HBR3_WAR, &dpRegkeyDatabase.bDisableAvoidHBR3War, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_SKIP_ZERO_OUI_CACHE, &dpRegkeyDatabase.bSkipZeroOuiCache, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_ENABLE_FIX_FOR_5147205, &dpRegkeyDatabase.bEnable5147205Fix, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_FORCE_HEAD_SHUTDOWN, &dpRegkeyDatabase.bForceHeadShutdown, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_EXPOSE_DSC_DEVID_WAR, &dpRegkeyDatabase.bEnableDevId, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_HDMI_ON_DP_PLUS_PLUS, &dpRegkeyDatabase.bHDMIOnDPPlusPlus, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_IGNORE_CAPS_AND_FORCE_HIGHEST_LC, &dpRegkeyDatabase.bIgnoreCapsAndForceHighestLc, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_OPTIMIZE_DSC_BPP_FOR_TUNNELLING_BW, &dpRegkeyDatabase.bOptimizeDscBppForTunnellingBw, DP_REG_VAL_BOOL}
{NV_DP_REGKEY_OVERRIDE_DPCD_REV, &dpRegkeyDatabase.dpcdRevOveride, DP_REG_VAL_U32},
{NV_DP_REGKEY_DISABLE_SSC, &dpRegkeyDatabase.bSscDisabled, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_ENABLE_FAST_LINK_TRAINING, &dpRegkeyDatabase.bFastLinkTrainingEnabled, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_DISABLE_MST, &dpRegkeyDatabase.bMstDisabled, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_ENABLE_INBAND_STEREO_SIGNALING, &dpRegkeyDatabase.bInbandStereoSignalingEnabled, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_SKIP_POWEROFF_EDP_IN_HEAD_DETACH, &dpRegkeyDatabase.bPoweroffEdpInHeadDetachSkipped, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_ENABLE_OCA_LOGGING, &dpRegkeyDatabase.bOcaLoggingEnabled, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_REPORT_DEVICE_LOST_BEFORE_NEW, &dpRegkeyDatabase.bReportDeviceLostBeforeNew, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_APPLY_LINK_BW_OVERRIDE_WAR, &dpRegkeyDatabase.bLinkBwOverrideWarApplied, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_APPLY_MAX_LINK_RATE_OVERRIDES, &dpRegkeyDatabase.applyMaxLinkRateOverrides, DP_REG_VAL_U32},
{NV_DP_REGKEY_DISABLE_DSC, &dpRegkeyDatabase.bDscDisabled, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_SKIP_ASSESSLINK_FOR_EDP, &dpRegkeyDatabase.bAssesslinkForEdpSkipped, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_MST_AUTO_HDCP_AUTH_AT_ATTACH, &dpRegkeyDatabase.bMstAutoHdcpAuthAtAttach, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_ENABLE_MSA_OVER_MST, &dpRegkeyDatabase.bMsaOverMstEnabled, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_KEEP_OPT_LINK_ALIVE, &dpRegkeyDatabase.bOptLinkKeptAlive, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_KEEP_OPT_LINK_ALIVE_MST, &dpRegkeyDatabase.bOptLinkKeptAliveMst, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_KEEP_OPT_LINK_ALIVE_SST, &dpRegkeyDatabase.bOptLinkKeptAliveSst, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_FORCE_EDP_ILR, &dpRegkeyDatabase.bBypassEDPRevCheck, DP_REG_VAL_BOOL},
{NV_DP_DSC_MST_CAP_BUG_3143315, &dpRegkeyDatabase.bDscMstCapBug3143315, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_POWER_DOWN_PHY, &dpRegkeyDatabase.bPowerDownPhyBeforeD3, DP_REG_VAL_BOOL},
{NV_DP2X_REGKEY_FPGA_UHBR_SUPPORT, &dpRegkeyDatabase.supportInternalUhbrOnFpga, DP_REG_VAL_U32},
{NV_DP2X_IGNORE_CABLE_ID_CAPS, &dpRegkeyDatabase.bIgnoreCableIdCaps, DP_REG_VAL_BOOL},
{NV_DP2X_REGKEY_VCONN_SOURCE_UNKNOWN_WAR, &dpRegkeyDatabase.bCableVconnSourceUnknownWar, DP_REG_VAL_BOOL},
{NV_DP2X_REGKEY_DISABLE_EFF_BPP_SST_8b10b, &dpRegkeyDatabase.bDisableEffBppSST8b10b, DP_REG_VAL_BOOL},
{NV_DP2X_REGKEY_DISABLE_WATERMARK_CACHING, &dpRegkeyDatabase.bDisableWatermarkCaching, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_MST_PCON_CAPS_READ_DISABLED, &dpRegkeyDatabase.bMSTPCONCapsReadDisabled, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_DISABLE_TUNNEL_BW_ALLOCATION, &dpRegkeyDatabase.bForceDisableTunnelBwAllocation, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_DISABLE_DOWNSPREAD, &dpRegkeyDatabase.bDownspreadDisabled, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_DISABLE_AVOID_HBR3_WAR, &dpRegkeyDatabase.bDisableAvoidHBR3War, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_SKIP_ZERO_OUI_CACHE, &dpRegkeyDatabase.bSkipZeroOuiCache, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_ENABLE_FIX_FOR_5147205, &dpRegkeyDatabase.bEnable5147205Fix, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_FORCE_HEAD_SHUTDOWN, &dpRegkeyDatabase.bForceHeadShutdown, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_EXPOSE_DSC_DEVID_WAR, &dpRegkeyDatabase.bEnableDevId, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_ENABLE_CQA_STATS_COLLECTION, &dpRegkeyDatabase.bEnableCqaStatsCollection, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_IGNORE_CAPS_AND_FORCE_HIGHEST_LC, &dpRegkeyDatabase.bIgnoreCapsAndForceHighestLc, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_OPTIMIZE_DSC_BPP_FOR_TUNNELLING_BW, &dpRegkeyDatabase.bOptimizeDscBppForTunnellingBw, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_ENABLE_128b132b_DSC_LNK_CFG_REDUCTION, &dpRegkeyDatabase.bEnable128b132bDSCLnkCfgReduction, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_USE_MAX_DSC_COMPRESSION_MST, &dpRegkeyDatabase.bUseMaxDSCCompressionMST, DP_REG_VAL_BOOL}
};
EvoMainLink::EvoMainLink(EvoInterface * provider, Timer * timer) :

104
src/common/displayport/src/dp_hashmap.cpp Normal file
View File

@@ -0,0 +1,104 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
/******************************* DisplayPort********************************\
* *
* Module: dp_hashmap.cpp *
* DP hashmap implementation *
* *
\***************************************************************************/
#include "dp_hashmap.h"
using namespace DisplayPort;
HashMap::~HashMap()
{
for (unsigned int i = 0; i < DP_HASHMAP_CAPACITY; i++)
m_hashMap[i].clear();
}
HashMapElement* HashMap::get(const HashMapElement *query)
{
if (query == NULL)
return NULL;
unsigned int index = query->hash() % DP_HASHMAP_CAPACITY;
if (m_hashMap[index].isEmpty())
return NULL;
// Traverse in reverse order to find the most recent cache hit
for (ListElement *i = m_hashMap[index].last(); i != m_hashMap[index].end(); i = i->prev)
{
auto *pCachedElement = (HashMapElement *)i;
if (query->isEqual(pCachedElement))
return pCachedElement;
}
return NULL;
}
void HashMap::add(HashMapElement *element)
{
if (element == NULL)
return;
unsigned int index = element->hash() % DP_HASHMAP_CAPACITY;
element->m_age = m_currentAge++;
m_hashMap[index].insertBack(element);
m_added++;
if (m_added >= DP_HASHMAP_CAPACITY)
pruneCache();
}
void HashMap::pruneCache()
{
// Prune the cache by removing the oldest cache elements until we reach the prune size
for (unsigned int i = 0; i < DP_HASHMAP_CAPACITY; i++)
{
if (m_hashMap[i].isEmpty())
continue;
// From the front, remove the oldest cache elements until we reach the prune size
auto *pCurr = (HashMapElement *)m_hashMap[i].front();
while (pCurr != m_hashMap[i].end() && m_added > DP_HASHMAP_PRUNED_SIZE)
{
if ((m_currentAge - pCurr->m_age) > DP_HASHMAP_PRUNED_THRESHOLD)
{
auto *pNext = (HashMapElement *)pCurr->next;
m_hashMap[i].remove(pCurr);
delete pCurr;
pCurr = pNext;
m_added--;
}
else
{
// Current element is too "young" to be pruned, go to next list
break;
}
}
}
}

32
src/common/displayport/src/dp_qse.cpp Normal file
View File

@@ -0,0 +1,32 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2010-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
/******************************* DisplayPort *******************************\
* *
* Module: dp_qse.cpp *
* The DP HDCP Query Stream Encryption. *
* *
\***************************************************************************/
#include "dp_auxdefs.h"

15
src/common/displayport/src/dp_wardatabase.cpp
View File

@@ -1,4 +1,4 @@
/*
/*
* SPDX-FileCopyrightText: Copyright (c) 1993-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
@@ -460,6 +460,11 @@ void Edid::applyEdidWorkArounds(NvU32 warFlag, const DpMonitorDenylistData *pDen
DP_PRINTF(DP_NOTICE, "DP-WAR> Sharp EDP implements only Legacy interrupt address range");
}
break;
case 0x157F:
// Bug 5317617 - ALPM doesn't work with Sharp panel at lower link rates.
this->WARFlags.forceMaxLinkConfig = true;
break;
}
break;
@@ -675,14 +680,6 @@ void Edid::applyEdidWorkArounds(NvU32 warFlag, const DpMonitorDenylistData *pDen
DP_PRINTF(DP_NOTICE, "DP-WAR> VRT monitor does not work with GB20x when downspread is enabled. Disabling downspread.");
}
break;
case 0xD94D: // Sony
if (ProductID == 0x07EE) // Sony SDM27Q10S
{
this->WARFlags.bSkipResetMSTMBeforeLt = true;
DP_PRINTF(DP_NOTICE, "DP-WAR> Sony SDM27Q10S needs to skip reset MST_EN before LT");
}
break;
case 0xAC10:
switch (ProductID)
{

53
src/common/inc/controller/sbios_table_version.h Normal file
View File

@@ -0,0 +1,53 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef SBIOS_TABLE_VERSION_H
#define SBIOS_TABLE_VERSION_H
#define CONTROLLER_SBIOS_TABLE_VERSION_10 (0x10)
#define CONTROLLER_SBIOS_TABLE_VERSION_20 (0x20)
#define CONTROLLER_SBIOS_TABLE_VERSION_21 (0x21)
#define CONTROLLER_SBIOS_TABLE_VERSION_22 (0x22)
#define CONTROLLER_SBIOS_TABLE_VERSION_23 (0x23)
#define CONTROLLER_SBIOS_TABLE_VERSION_24 (0x24)
#define CONTROLLER_SBIOS_TABLE_VERSION_25 (0x25)
#define CONTROLLER_SBIOS_TABLE_MAX_ENTRIES (8)
// NOTE: When adding a new version, make sure to update MAX_VERSION accordingly.
#define CONTROLLER_SBIOS_TABLE_MAX_VERSION (0x25)
/*!
* Layout of Controller 2x data used for static config
*/
#define NVPCF_CONTROLLER_STATIC_TABLE_VERSION_20 (0x20)
#define NVPCF_CONTROLLER_STATIC_TABLE_VERSION_21 (0x21)
#define NVPCF_CONTROLLER_STATIC_TABLE_VERSION_22 (0x22)
#define NVPCF_CONTROLLER_STATIC_TABLE_VERSION_23 (0x23)
#define NVPCF_CONTROLLER_STATIC_TABLE_VERSION_24 (0x24)
#define NVPCF_CONTROLLER_STATIC_TABLE_VERSION_25 (0x25)
#define NVPCF_CONTROLLER_STATIC_TABLE_MAX_ENTRIES (8)
// NOTE: When adding a new version, make sure to update MAX_VERSION accordingly.
#define NVPCF_CONTROLLER_STATIC_TABLE_MAX_VERSION (0x25)
#endif // SBIOS_TABLE_VERSION_H

10
src/common/inc/displayport/displayport.h
View File

@@ -535,11 +535,11 @@ typedef struct VesaPsrEventIndicator
typedef struct VesaPsrSinkCaps
{
NvU8 psrVersion;
NvU8 linkTrainingRequired : 1;
NvU8 psrSetupTime : 3;
NvU8 yCoordinateRequired : 1;
NvU8 psr2UpdateGranularityRequired : 1;
NvU8 reserved : 2;
NvU32 linkTrainingRequired : 1;
NvU32 psrSetupTime : 16;
NvU32 yCoordinateRequired : 1;
NvU32 psr2UpdateGranularityRequired : 1;
NvU32 reserved : 13;
NvU16 suXGranularity;
NvU8 suYGranularity;
} vesaPsrSinkCaps;

22
src/common/inc/nvBldVer.h
View File

@@ -36,26 +36,26 @@
// and then checked back in. You cannot make changes to these sections without
// corresponding changes to the buildmeister script
#ifndef NV_BUILD_BRANCH
#define NV_BUILD_BRANCH r581_66
#define NV_BUILD_BRANCH r591_37
#endif
#ifndef NV_PUBLIC_BRANCH
#define NV_PUBLIC_BRANCH r581_66
#define NV_PUBLIC_BRANCH r591_37
#endif
#if defined(NV_LINUX) || defined(NV_BSD) || defined(NV_SUNOS)
#define NV_BUILD_BRANCH_VERSION "rel/gpu_drv/r580/r581_66-314"
#define NV_BUILD_CHANGELIST_NUM (36773567)
#define NV_BUILD_BRANCH_VERSION "rel/gpu_drv/r590/r591_37-155"
#define NV_BUILD_CHANGELIST_NUM (36926008)
#define NV_BUILD_TYPE "Official"
#define NV_BUILD_NAME "rel/gpu_drv/r580/r581_66-314"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (36773567)
#define NV_BUILD_NAME "rel/gpu_drv/r590/r591_37-155"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (36926008)
#else /* Windows builds */
#define NV_BUILD_BRANCH_VERSION "r581_66-7"
#define NV_BUILD_CHANGELIST_NUM (36773154)
#define NV_BUILD_BRANCH_VERSION "r591_37-1"
#define NV_BUILD_CHANGELIST_NUM (36926008)
#define NV_BUILD_TYPE "Official"
#define NV_BUILD_NAME "581.80"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (36773154)
#define NV_BUILD_BRANCH_BASE_VERSION R580
#define NV_BUILD_NAME "591.38"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (36926008)
#define NV_BUILD_BRANCH_BASE_VERSION R590
#endif
// End buildmeister python edited section

5
src/common/inc/nvUnixVersion.h
View File

@@ -2,9 +2,10 @@
#define __NV_UNIX_VERSION_H__
#if defined(NV_LINUX) || defined(NV_BSD) || defined(NV_SUNOS) || defined(NV_VMWARE) || defined(NV_QNX) || defined(NV_INTEGRITY) || \
(defined(RMCFG_FEATURE_PLATFORM_GSP) && RMCFG_FEATURE_PLATFORM_GSP == 1)
(defined(RMCFG_FEATURE_PLATFORM_GSP) && RMCFG_FEATURE_PLATFORM_GSP == 1) || \
defined(NV_DCECORE)
#define NV_VERSION_STRING "580.105.08"
#define NV_VERSION_STRING "590.44.01"
#else

6
src/common/inc/nv_mig_types.h
View File

@@ -33,6 +33,12 @@ typedef NvU32 MIGDeviceId;
#define NO_MIG_DEVICE 0L
/* Convert a MIGDeviceId into a 0-based per-GPU subdevice index. */
#define MIG_DEVICE_ID_SUBDEV_MASK 0xf0000000
#define MIG_DEVICE_ID_SUBDEV_SHIFT 28
#define MIG_DEVICE_ID_TO_SUBDEV(migDeviceId) (((migDeviceId) & MIG_DEVICE_ID_SUBDEV_MASK) >> MIG_DEVICE_ID_SUBDEV_SHIFT)
#ifdef __cplusplus
}
#endif

5
src/common/inc/nv_smg.h
View File

@@ -29,6 +29,8 @@ extern "C" {
#include "nvtypes.h"
#include "nvlimits.h"
#include "nvgputypes.h"
#include "nvctassert.h"
#include "nvrmcontext.h"
#include "nv_mig_types.h"
@@ -66,9 +68,10 @@ typedef struct nvMIGDeviceDescriptionRec {
NvU32 computeInstanceId;
/* Whether this device is accessible to the calling process */
NvBool migAccessOk;
NvBool smgAccessOk;
/* MIG exec partition UUID string */
char migUuid[NV_MIG_DEVICE_UUID_STR_LENGTH];
NvU8 migUuidBin[NV_GPU_UUID_LEN];
} nvMIGDeviceDescription;
NvBool nvSMGSubscribeSubDevToPartition(nvRMContextPtr rmctx,

4
src/common/inc/swref/published/ampere/ga100/dev_runlist.h
View File

@@ -71,6 +71,10 @@
#define NV_CHRAM_CHANNEL_UPDATE_RESET_PBDMA_FAULTED 0x00000011 /* */
#define NV_CHRAM_CHANNEL_UPDATE_RESET_ENG_FAULTED 0x00000021 /* */
#define NV_CHRAM_CHANNEL_UPDATE_CLEAR_CHANNEL 0xFFFFFFFF /* */
#define NV_RUNLIST_INTERNAL_DOORBELL 0x090 /* -W-4R */
#define NV_RUNLIST_INTERNAL_DOORBELL_CHID 11:0 /* */
#define NV_RUNLIST_INTERNAL_DOORBELL_CHID_HW 10:0 /* -WXUF */
#define NV_RUNLIST_INTERNAL_DOORBELL_GFID 21:16 /* -WXUF */
#define NV_RUNLIST_PREEMPT 0x098 /* RW-4R */
#define NV_RUNLIST_PREEMPT_ID 11:0 /* */
#define NV_RUNLIST_PREEMPT_ID_HW 10:0 /* RWIUF */

7
src/common/inc/swref/published/ampere/ga100/dev_top_addendum.h
View File

@@ -24,6 +24,13 @@
#ifndef __ga100_dev_top_addendum_h__
#define __ga100_dev_top_addendum_h__
// Backports from GB100
#define NV_PTOP_ZB_DEVICE_INFO_CFG 0x000004fc
#define NV_PTOP_ZB_DEVICE_INFO(i) (0x00000800+(i)*4)
#define NV_PTOP_ZB_DEVICE_INFO__SIZE_1 NV_PTOP_DEVICE_INFO2__SIZE_1
#define NV_PTOP_ZB_DEVICE_INFO_DEV_TYPE_ENUM_PTOP 52
#define NV_PTOP_ZB_DEVICE_INFO_DEV_TYPE_ENUM_GRAPHICS NV_PTOP_DEVICE_INFO2_DEV_TYPE_ENUM_GRAPHICS
#define NV_PTOP_ZB_DEVICE_INFO_DEV_TYPE_ENUM_NVDEC NV_PTOP_DEVICE_INFO2_DEV_TYPE_ENUM_NVDEC
#define NV_PTOP_ZB_DEVICE_INFO_DEV_TYPE_ENUM_NVENC NV_PTOP_DEVICE_INFO2_DEV_TYPE_ENUM_NVENC

39
src/common/inc/swref/published/blackwell/gb100/dev_boot_zb.h Normal file
View File

@@ -0,0 +1,39 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gb100_dev_boot_zb_h__
#define __gb100_dev_boot_zb_h__
#define NV_PMC_ZB 0x00000FFF:0x00000000 /* RW--D */
#define NV_PMC_ZB_SCRATCH_RESET_2(i) (0x00000580+(i)*4) /* RW-4A */
#define NV_PMC_ZB_SCRATCH_RESET_2__SIZE_1 16 /* */
#define NV_PMC_ZB_SCRATCH_RESET_2_VALUE 31:0 /* RWBVF */
#define NV_PMC_ZB_SCRATCH_RESET_2_VALUE_INIT 0 /* RWB-V */
#define NV_PMC_ZB_ENABLE_PERFMON 28:28 /* RWBVF */
#define NV_PMC_ZB_ENABLE_PERFMON_DISABLED 0x00000000 /* RWB-V */
#define NV_PMC_ZB_ENABLE_PERFMON_ENABLED 0x00000001 /* RW--V */
#define NV_PMC_ZB_ENABLE_PDISP 30:30 /* RWBVF */
#define NV_PMC_ZB_ENABLE_PDISP_DISABLED 0x00000000 /* RW--V */
#define NV_PMC_ZB_ENABLE_PDISP_ENABLED 0x00000001 /* RWB-V */
#endif // __gb100_dev_boot_zb_h__

28
src/common/inc/swref/published/blackwell/gb100/dev_boot_addendum.h → src/common/inc/swref/published/blackwell/gb100/dev_boot_zb_addendum.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -21,18 +21,18 @@
* DEALINGS IN THE SOFTWARE.
*/
#ifndef gb100_dev_boot_addendum_h
#define gb100_dev_boot_addendum_h
#ifndef __gb100_dev_boot_zb_addendum_h__
#define __gb100_dev_boot_zb_addendum_h__
#define NV_PMC_SCRATCH_RESET_2_CC NV_PMC_SCRATCH_RESET_2(4)
#define NV_PMC_SCRATCH_RESET_2_CC_MODE_ENABLED 0:0
#define NV_PMC_SCRATCH_RESET_2_CC_MODE_ENABLED_TRUE 0x1
#define NV_PMC_SCRATCH_RESET_2_CC_MODE_ENABLED_FALSE 0x0
#define NV_PMC_SCRATCH_RESET_2_CC_DEV_ENABLED 1:1
#define NV_PMC_SCRATCH_RESET_2_CC_DEV_ENABLED_TRUE 0x1
#define NV_PMC_SCRATCH_RESET_2_CC_DEV_ENABLED_FALSE 0x0
#define NV_PMC_SCRATCH_RESET_2_CC_NVLE_MODE_ENABLED 6:6
#define NV_PMC_SCRATCH_RESET_2_CC_NVLE_MODE_ENABLED_TRUE 0x1
#define NV_PMC_SCRATCH_RESET_2_CC_NVLE_MODE_ENABLED_FALSE 0x0
#define NV_PMC_ZB_SCRATCH_RESET_2_CC NV_PMC_ZB_SCRATCH_RESET_2(4)
#define NV_PMC_ZB_SCRATCH_RESET_2_CC_MODE_ENABLED 0:0
#define NV_PMC_ZB_SCRATCH_RESET_2_CC_MODE_ENABLED_TRUE 0x1
#define NV_PMC_ZB_SCRATCH_RESET_2_CC_MODE_ENABLED_FALSE 0x0
#define NV_PMC_ZB_SCRATCH_RESET_2_CC_DEV_ENABLED 1:1
#define NV_PMC_ZB_SCRATCH_RESET_2_CC_DEV_ENABLED_TRUE 0x1
#define NV_PMC_ZB_SCRATCH_RESET_2_CC_DEV_ENABLED_FALSE 0x0
#define NV_PMC_ZB_SCRATCH_RESET_2_CC_NVLE_MODE_ENABLED 6:6
#define NV_PMC_ZB_SCRATCH_RESET_2_CC_NVLE_MODE_ENABLED_TRUE 0x1
#define NV_PMC_ZB_SCRATCH_RESET_2_CC_NVLE_MODE_ENABLED_FALSE 0x0
#endif // gb100_dev_boot_addendum_h
#endif // __gb100_dev_boot_zb_addendum_h__

47
src/common/inc/swref/published/blackwell/gb100/dev_bus_zb_addendum.h Normal file
View File

@@ -0,0 +1,47 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef gb100_dev_nv_bus_zb_addendum_h
#define gb100_dev_nv_bus_zb_addendum_h
/*!
* @defgroup FRTS_INSECURE_SCRATCH_REGISTERS
*
* Used to communicate the location/size of insecure FRTS
*
* @{
*/
#define NV_PBUS_ZB_SW_FRTS_INSECURE_ADDR_LO32 NV_PBUS_ZB_SW_SCRATCH(0x3D)
#define NV_PBUS_ZB_SW_FRTS_INSECURE_ADDR_HI32 NV_PBUS_ZB_SW_SCRATCH(0x3E)
#define NV_PBUS_ZB_SW_FRTS_INSECURE_CONFIG NV_PBUS_ZB_SW_SCRATCH(0x3F)
#define NV_PBUS_ZB_SW_FRTS_INSECURE_CONFIG_SIZE_4K 15U:0U
#define NV_PBUS_ZB_SW_FRTS_INSECURE_CONFIG_SIZE_4K_INVALID 0x0000
#define NV_PBUS_ZB_SW_FRTS_INSECURE_CONFIG_SIZE_4K_SHIFT 12U
#define NV_PBUS_ZB_SW_FRTS_INSECURE_CONFIG_MEDIA_TYPE 16U:16U
#define NV_PBUS_ZB_SW_FRTS_INSECURE_CONFIG_MEDIA_TYPE_FB 0U
#define NV_PBUS_ZB_SW_FRTS_INSECURE_CONFIG_MEDIA_TYPE_SYSMEM 1U
/*!@}*/
#endif // gb100_dev_nv_bus_zb_addendum_h

4
src/common/inc/swref/published/blackwell/gb100/dev_fsp_pri.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES
* SPDX-FileCopyrightText: Copyright (c) 2024-2025 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -34,6 +34,6 @@
#define NV_PFSP_FALCON_COMMON_SCRATCH_GROUP_3_VAL 31:0 /* RWIVF */
#define NV_PFSP_FALCON_COMMON_SCRATCH_GROUP_3_VAL_INIT 0x00000000 /* RWI-V */
#define NV_PFSP_MNOC_BASE (0x008f1e00) /* -W-4A */
#define NV_PFSP_MNOC_RX_FIFO_DATA(i) (0x008f1e00+(i)*8) /* -W-4A */
#endif // __gb100_dev_fsp_pri_h__

48
src/common/inc/swref/published/blackwell/gb100/dev_fuse_zb.h Normal file
View File

@@ -0,0 +1,48 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2025 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gb100_dev_fuse_zb_h__
#define __gb100_dev_fuse_zb_h__
#define NV_FUSE_ZB_FEATURE_READOUT 0x00003814 /* R--4R */
#define NV_FUSE_ZB_FEATURE_READOUT_ECC_DRAM 16:16 /* R--VF */
#define NV_FUSE_ZB_FEATURE_READOUT_ECC_DRAM_DISABLED 0x00000000 /* R---V */
#define NV_FUSE_ZB_FEATURE_READOUT_ECC_DRAM_ENABLED 0x00000001 /* R---V */
#define NV_FUSE_ZB_OPT_FPF_GSP_UCODE1_VERSION 0x000041C0 /* RW-4R */
#define NV_FUSE_ZB_OPT_FPF_GSP_UCODE1_VERSION__PRIV_LEVEL_MASK 0x000000FC /* */
#define NV_FUSE_ZB_OPT_FPF_GSP_UCODE1_VERSION_DATA 15:0 /* RWIVF */
#define NV_FUSE_ZB_OPT_FPF_GSP_UCODE1_VERSION_DATA_INIT 0x00000000 /* RWI-V */
#define NV_FUSE_ZB_STATUS_OPT_DISPLAY 0x00000C04 /* R-I4R */
#define NV_FUSE_ZB_STATUS_OPT_DISPLAY_DATA 0:0 /* R-IVF */
#define NV_FUSE_ZB_STATUS_OPT_DISPLAY_DATA_ENABLE 0x00000000 /* R---V */
#define NV_FUSE_ZB_OPT_FPF_SEC2_UCODE1_VERSION 0x00004140 /* RW-4R */
#define NV_FUSE_ZB_OPT_FPF_SEC2_UCODE1_VERSION__PRIV_LEVEL_MASK 0x000000FC /* */
#define NV_FUSE_ZB_OPT_FPF_SEC2_UCODE1_VERSION_DATA 15:0 /* RWIVF */
#define NV_FUSE_ZB_OPT_FPF_SEC2_UCODE1_VERSION_DATA_INIT 0x00000000 /* RWI-V */
#define NV_FUSE_ZB_OPT_SECURE_GSP_DEBUG_DIS 0x0000074C /* RW-4R */
#define NV_FUSE_ZB_OPT_SECURE_GSP_DEBUG_DIS__PRIV_LEVEL_MASK 0x000000FC /* */
#define NV_FUSE_ZB_OPT_SECURE_GSP_DEBUG_DIS_DATA 0:0 /* RWIVF */
#define NV_FUSE_ZB_OPT_SECURE_GSP_DEBUG_DIS_DATA_INIT 0x00000001 /* RWI-V */
#define NV_FUSE_ZB_OPT_SECURE_GSP_DEBUG_DIS_DATA_NO 0x00000000 /* RW--V */
#define NV_FUSE_ZB_OPT_SECURE_GSP_DEBUG_DIS_DATA_YES 0x00000001 /* RW--V */
#endif // __gb100_dev_fuse_zb_h__

19
src/common/unix/nvidia-3d/include/nvidia-3d-maxwell.h → src/common/inc/swref/published/blackwell/gb100/dev_hshub.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2017 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2025 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -14,22 +14,17 @@
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __NVIDIA_3D_MAXWELL_H__
#define __NVIDIA_3D_MAXWELL_H__
#ifndef __gb100_dev_hshub_h__
#define __gb100_dev_hshub_h__
#include "nvidia-3d-types.h"
// Needed to boot GSP before we get the whole device info table.
#define NV_PFB_HSHUB0 0x00870fff:0x00870000
void _nv3dInitChannelMaxwell(Nv3dChannelRec *p3dChannel);
void _nv3dAssignNv3dTextureMaxwell(
Nv3dRenderTexInfo info,
Nv3dTexture *tex);
#endif /* __NVIDIA_3D_MAXWELL__ */
#endif // __gb100_dev_hshub_h__

29
src/common/inc/swref/published/blackwell/gb100/dev_ltc_zb.h Normal file
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@@ -0,0 +1,29 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2025 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gb100_dev_ltc_zb_h__
#define __gb100_dev_ltc_zb_h__
#define NV_PLTC_LTS0_L2_CACHE_ECC_UNCORRECTED_ERR_COUNT 0x000004f8 /* RW-4R */
#endif

92
src/common/inc/swref/published/blackwell/gb100/dev_riscv_pri.h Normal file
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@@ -0,0 +1,92 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2025 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gb100_dev_riscv_pri_h__
#define __gb100_dev_riscv_pri_h__
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT 0x00000700 /* R--4R */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_GLOBAL_MEM 0:0 /* R-IVF */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_GLOBAL_MEM_FAULTED 0x00000001 /* R---V */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_GLOBAL_MEM_NO_FAULT 0x00000000 /* R-I-V */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_ROM 1:1 /* R-IVF */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_ROM_FAULTED 0x00000001 /* R---V */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_ROM_NO_FAULT 0x00000000 /* R-I-V */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_ITCM 2:2 /* R-IVF */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_ITCM_FAULTED 0x00000001 /* R---V */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_ITCM_NO_FAULT 0x00000000 /* R-I-V */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_DTCM 3:3 /* R-IVF */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_DTCM_FAULTED 0x00000001 /* R---V */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_DTCM_NO_FAULT 0x00000000 /* R-I-V */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_ICACHE 4:4 /* R-IVF */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_ICACHE_FAULTED 0x00000001 /* R---V */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_ICACHE_NO_FAULT 0x00000000 /* R-I-V */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_DCACHE 5:5 /* R-IVF */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_DCACHE_FAULTED 0x00000001 /* R---V */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_DCACHE_NO_FAULT 0x00000000 /* R-I-V */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_RVCORE 6:6 /* R-IVF */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_RVCORE_FAULTED 0x00000001 /* R---V */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_RVCORE_NO_FAULT 0x00000000 /* R-I-V */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_REG 7:7 /* R-IVF */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_REG_FAULTED 0x00000001 /* R---V */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_REG_NO_FAULT 0x00000000 /* R-I-V */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_SE_LOGIC 8:8 /* R-IVF */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_SE_LOGIC_FAULTED 0x00000001 /* R---V */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_SE_LOGIC_NO_FAULT 0x00000000 /* R-I-V */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_SE_KSLT 9:9 /* R-IVF */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_SE_KSLT_FAULTED 0x00000001 /* R---V */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_SE_KSLT_NO_FAULT 0x00000000 /* R-I-V */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_TKE 10:10 /* R-IVF */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_TKE_FAULTED 0x00000001 /* R---V */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_TKE_NO_FAULT 0x00000000 /* R-I-V */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_FBIF 11:11 /* R-IVF */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_FBIF_FAULTED 0x00000001 /* R---V */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_FBIF_NO_FAULT 0x00000000 /* R-I-V */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_MPURAM 12:12 /* R-IVF */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_MPURAM_FAULTED 0x00000001 /* R---V */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_MPURAM_NO_FAULT 0x00000000 /* R-I-V */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_ENGINE_IN0 16:16 /* R-IVF */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_ENGINE_IN0_FAULTED 0x00000001 /* R---V */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_ENGINE_IN0_NO_FAULT 0x00000000 /* R-I-V */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_ENGINE_IN1 17:17 /* R-IVF */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_ENGINE_IN1_FAULTED 0x00000001 /* R---V */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_ENGINE_IN1_NO_FAULT 0x00000000 /* R-I-V */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_ENGINE_IN2 18:18 /* R-IVF */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_ENGINE_IN2_FAULTED 0x00000001 /* R---V */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_ENGINE_IN2_NO_FAULT 0x00000000 /* R-I-V */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_ENGINE_IN3 19:19 /* R-IVF */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_ENGINE_IN3_FAULTED 0x00000001 /* R---V */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_ENGINE_IN3_NO_FAULT 0x00000000 /* R-I-V */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_ENGINE_IN4 20:20 /* R-IVF */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_ENGINE_IN4_FAULTED 0x00000001 /* R---V */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_ENGINE_IN4_NO_FAULT 0x00000000 /* R-I-V */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_ENGINE_IN5 21:21 /* R-IVF */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_ENGINE_IN5_FAULTED 0x00000001 /* R---V */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_ENGINE_IN5_NO_FAULT 0x00000000 /* R-I-V */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_ENGINE_IN6 22:22 /* R-IVF */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_ENGINE_IN6_FAULTED 0x00000001 /* R---V */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_ENGINE_IN6_NO_FAULT 0x00000000 /* R-I-V */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_ENGINE_IN7 23:23 /* R-IVF */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_ENGINE_IN7_FAULTED 0x00000001 /* R---V */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_ENGINE_IN7_NO_FAULT 0x00000000 /* R-I-V */
#endif // __gb100_dev_riscv_pri_h__

30
src/common/inc/swref/published/blackwell/gb100/dev_tmr.h Normal file
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@@ -0,0 +1,30 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2025 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gb100_dev_tmr_h__
#define __gb100_dev_tmr_h__
#define NV_TMR 0x00000fff:0x00000000 /* RW--D */
#define NV_TMR_TIME_0_NSEC 31:5 /* R-XUF */
#endif // __gb100_dev_tmr_h__

29
src/common/inc/swref/published/blackwell/gb100/dev_top_zb.h Normal file
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@@ -0,0 +1,29 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2025 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gb100_dev_top_zb__h__
#define __gb100_dev_top_zb__h__
#define NV_PTOP_ZB_DEVICE_INFO_DEV_TYPE_ENUM_TMR 0x1f /* */
#endif // __gb100_dev_top_zb__h__

7
src/common/inc/swref/published/blackwell/gb100/hwproject.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES
* SPDX-FileCopyrightText: Copyright (c) 2024-2025 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -24,8 +24,13 @@
#ifndef __gb100_hwproject_h__
#define __gb100_hwproject_h__
#define NV_PMC0_PRI_BASE 0x0
#define NV_LITTER_NUM_SUBCTX 64
#define NV_LOCALIZATION_MODE_BIT_IN_ADDRESS_OFFSET 39
#define NV_FUSE0_PRI_BASE 0x820000
#define NV_LTC_PRI_BASE 0x140000
#define NV_LTC_PRI_STRIDE 0x2000
#define NV_LTS_PRI_STRIDE 0x200
#endif // __gb100_hwproject_h__

47
src/common/inc/swref/published/blackwell/gb102/dev_bus_zb_addendum.h Normal file
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@@ -0,0 +1,47 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef gb100_dev_nv_bus_zb_addendum_h
#define gb100_dev_nv_bus_zb_addendum_h
/*!
* @defgroup FRTS_INSECURE_SCRATCH_REGISTERS
*
* Used to communicate the location/size of insecure FRTS
*
* @{
*/
#define NV_PBUS_ZB_SW_FRTS_INSECURE_ADDR_LO32 NV_PBUS_ZB_SW_SCRATCH(0x3D)
#define NV_PBUS_ZB_SW_FRTS_INSECURE_ADDR_HI32 NV_PBUS_ZB_SW_SCRATCH(0x3E)
#define NV_PBUS_ZB_SW_FRTS_INSECURE_CONFIG NV_PBUS_ZB_SW_SCRATCH(0x3F)
#define NV_PBUS_ZB_SW_FRTS_INSECURE_CONFIG_SIZE_4K 15U:0U
#define NV_PBUS_ZB_SW_FRTS_INSECURE_CONFIG_SIZE_4K_INVALID 0x0000
#define NV_PBUS_ZB_SW_FRTS_INSECURE_CONFIG_SIZE_4K_SHIFT 12U
#define NV_PBUS_ZB_SW_FRTS_INSECURE_CONFIG_MEDIA_TYPE 16U:16U
#define NV_PBUS_ZB_SW_FRTS_INSECURE_CONFIG_MEDIA_TYPE_FB 0U
#define NV_PBUS_ZB_SW_FRTS_INSECURE_CONFIG_MEDIA_TYPE_SYSMEM 1U
/*!@}*/
#endif // gb100_dev_nv_bus_zb_addendum_h

92
src/common/inc/swref/published/blackwell/gb102/dev_riscv_pri.h Normal file
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@@ -0,0 +1,92 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2025 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gb102_dev_riscv_pri_h__
#define __gb102_dev_riscv_pri_h__
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT 0x00000700 /* R--4R */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_GLOBAL_MEM 0:0 /* R-IVF */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_GLOBAL_MEM_FAULTED 0x00000001 /* R---V */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_GLOBAL_MEM_NO_FAULT 0x00000000 /* R-I-V */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_ROM 1:1 /* R-IVF */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_ROM_FAULTED 0x00000001 /* R---V */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_ROM_NO_FAULT 0x00000000 /* R-I-V */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_ITCM 2:2 /* R-IVF */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_ITCM_FAULTED 0x00000001 /* R---V */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_ITCM_NO_FAULT 0x00000000 /* R-I-V */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_DTCM 3:3 /* R-IVF */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_DTCM_FAULTED 0x00000001 /* R---V */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_DTCM_NO_FAULT 0x00000000 /* R-I-V */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_ICACHE 4:4 /* R-IVF */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_ICACHE_FAULTED 0x00000001 /* R---V */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_ICACHE_NO_FAULT 0x00000000 /* R-I-V */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_DCACHE 5:5 /* R-IVF */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_DCACHE_FAULTED 0x00000001 /* R---V */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_DCACHE_NO_FAULT 0x00000000 /* R-I-V */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_RVCORE 6:6 /* R-IVF */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_RVCORE_FAULTED 0x00000001 /* R---V */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_RVCORE_NO_FAULT 0x00000000 /* R-I-V */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_REG 7:7 /* R-IVF */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_REG_FAULTED 0x00000001 /* R---V */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_REG_NO_FAULT 0x00000000 /* R-I-V */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_SE_LOGIC 8:8 /* R-IVF */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_SE_LOGIC_FAULTED 0x00000001 /* R---V */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_SE_LOGIC_NO_FAULT 0x00000000 /* R-I-V */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_SE_KSLT 9:9 /* R-IVF */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_SE_KSLT_FAULTED 0x00000001 /* R---V */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_SE_KSLT_NO_FAULT 0x00000000 /* R-I-V */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_TKE 10:10 /* R-IVF */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_TKE_FAULTED 0x00000001 /* R---V */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_TKE_NO_FAULT 0x00000000 /* R-I-V */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_FBIF 11:11 /* R-IVF */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_FBIF_FAULTED 0x00000001 /* R---V */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_FBIF_NO_FAULT 0x00000000 /* R-I-V */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_MPURAM 12:12 /* R-IVF */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_MPURAM_FAULTED 0x00000001 /* R---V */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_MPURAM_NO_FAULT 0x00000000 /* R-I-V */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_ENGINE_IN0 16:16 /* R-IVF */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_ENGINE_IN0_FAULTED 0x00000001 /* R---V */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_ENGINE_IN0_NO_FAULT 0x00000000 /* R-I-V */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_ENGINE_IN1 17:17 /* R-IVF */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_ENGINE_IN1_FAULTED 0x00000001 /* R---V */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_ENGINE_IN1_NO_FAULT 0x00000000 /* R-I-V */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_ENGINE_IN2 18:18 /* R-IVF */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_ENGINE_IN2_FAULTED 0x00000001 /* R---V */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_ENGINE_IN2_NO_FAULT 0x00000000 /* R-I-V */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_ENGINE_IN3 19:19 /* R-IVF */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_ENGINE_IN3_FAULTED 0x00000001 /* R---V */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_ENGINE_IN3_NO_FAULT 0x00000000 /* R-I-V */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_ENGINE_IN4 20:20 /* R-IVF */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_ENGINE_IN4_FAULTED 0x00000001 /* R---V */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_ENGINE_IN4_NO_FAULT 0x00000000 /* R-I-V */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_ENGINE_IN5 21:21 /* R-IVF */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_ENGINE_IN5_FAULTED 0x00000001 /* R---V */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_ENGINE_IN5_NO_FAULT 0x00000000 /* R-I-V */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_ENGINE_IN6 22:22 /* R-IVF */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_ENGINE_IN6_FAULTED 0x00000001 /* R---V */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_ENGINE_IN6_NO_FAULT 0x00000000 /* R-I-V */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_ENGINE_IN7 23:23 /* R-IVF */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_ENGINE_IN7_FAULTED 0x00000001 /* R---V */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_ENGINE_IN7_NO_FAULT 0x00000000 /* R-I-V */
#endif // __gb102_dev_riscv_pri_h__

26
src/common/inc/swref/published/blackwell/gb10b/dev_boot.h → src/common/inc/swref/published/blackwell/gb10b/dev_boot_zb.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2024 NVIDIA CORPORATION & AFFILIATES
* SPDX-FileCopyrightText: Copyright (c) 2025 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -21,17 +21,17 @@
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gb10b_dev_boot_h__
#define __gb10b_dev_boot_h__
#ifndef __gb10b_dev_boot_zb_h__
#define __gb10b_dev_boot_zb_h__
#define NV_SYSCTRL_SEC_FAULT 0x3:0x0 /* R---M */
#define NV_SYSCTRL_SEC_FAULT_BIT_POSITION_FUSE_POD 0:0 /* R-XUF */
#define NV_SYSCTRL_SEC_FAULT_BIT_POSITION_SEC2_SCPM 1:1 /* R-XUF */
#define NV_SYSCTRL_SEC_FAULT_BIT_POSITION_SEC2_DCLS 2:2 /* R-XUF */
#define NV_SYSCTRL_SEC_FAULT_BIT_POSITION_SEC2_L5_WDT 3:3 /* R-XUF */
#define NV_SYSCTRL_SEC_FAULT_BIT_POSITION_GSP_DCLS 4:4 /* R-XUF */
#define NV_SYSCTRL_SEC_FAULT_BIT_POSITION_GSP_L5_WDT 5:5 /* R-XUF */
#define NV_SYSCTRL_SEC_FAULT_BIT_POSITION_PMU_DCLS 6:6 /* R-XUF */
#define NV_SYSCTRL_SEC_FAULT_BIT_POSITION_PMU_L5_WDT 7:7 /* R-XUF */
#define NV_SYSCTRL_SEC_FAULT 0x3:0x0 /* R---M */
#define NV_SYSCTRL_SEC_FAULT_BIT_POSITION_FUSE_POD 0:0 /* R-XUF */
#define NV_SYSCTRL_SEC_FAULT_BIT_POSITION_SEC2_SCPM 1:1 /* R-XUF */
#define NV_SYSCTRL_SEC_FAULT_BIT_POSITION_SEC2_DCLS 2:2 /* R-XUF */
#define NV_SYSCTRL_SEC_FAULT_BIT_POSITION_SEC2_L5_WDT 3:3 /* R-XUF */
#define NV_SYSCTRL_SEC_FAULT_BIT_POSITION_GSP_DCLS 4:4 /* R-XUF */
#define NV_SYSCTRL_SEC_FAULT_BIT_POSITION_GSP_L5_WDT 5:5 /* R-XUF */
#define NV_SYSCTRL_SEC_FAULT_BIT_POSITION_PMU_DCLS 6:6 /* R-XUF */
#define NV_SYSCTRL_SEC_FAULT_BIT_POSITION_PMU_L5_WDT 7:7 /* R-XUF */
#endif // __gb10b_dev_boot_h__
#endif // __gb10b_dev_boot_zb_h__

27
src/common/inc/swref/published/blackwell/gb10b/dev_nv_xal_ep_zb.h Normal file
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@@ -0,0 +1,27 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2025 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gb10b_dev_nv_xal_ep_zb_h__
#define __gb10b_dev_nv_xal_ep_zb_h__
#define NV_XAL_EP_ZB 0x00000FFF:0x00000000 /* RW--D */
#endif // __gb10b_dev_nv_xal_ep_zb_h__

3
src/common/inc/swref/published/blackwell/gb10b/hwproject.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES
* SPDX-FileCopyrightText: Copyright (c) 2022-2025 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -24,6 +24,7 @@
#ifndef __gb10b_hwproject_h__
#define __gb10b_hwproject_h__
#define NV_XAL_BASE_ADDRESS 1110016
#define NV_CHIP_EXTENDED_SYSTEM_PHYSICAL_ADDRESS_BITS 41
#endif // __gb10b_hwproject_h__

92
src/common/inc/swref/published/blackwell/gb110/dev_riscv_pri.h Normal file
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@@ -0,0 +1,92 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2025 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gb110_dev_riscv_pri_h__
#define __gb110_dev_riscv_pri_h__
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT 0x00000700 /* R--4R */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_GLOBAL_MEM 0:0 /* R-IVF */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_GLOBAL_MEM_FAULTED 0x00000001 /* R---V */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_GLOBAL_MEM_NO_FAULT 0x00000000 /* R-I-V */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_ROM 1:1 /* R-IVF */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_ROM_FAULTED 0x00000001 /* R---V */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_ROM_NO_FAULT 0x00000000 /* R-I-V */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_ITCM 2:2 /* R-IVF */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_ITCM_FAULTED 0x00000001 /* R---V */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_ITCM_NO_FAULT 0x00000000 /* R-I-V */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_DTCM 3:3 /* R-IVF */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_DTCM_FAULTED 0x00000001 /* R---V */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_DTCM_NO_FAULT 0x00000000 /* R-I-V */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_ICACHE 4:4 /* R-IVF */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_ICACHE_FAULTED 0x00000001 /* R---V */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_ICACHE_NO_FAULT 0x00000000 /* R-I-V */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_DCACHE 5:5 /* R-IVF */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_DCACHE_FAULTED 0x00000001 /* R---V */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_DCACHE_NO_FAULT 0x00000000 /* R-I-V */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_RVCORE 6:6 /* R-IVF */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_RVCORE_FAULTED 0x00000001 /* R---V */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_RVCORE_NO_FAULT 0x00000000 /* R-I-V */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_REG 7:7 /* R-IVF */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_REG_FAULTED 0x00000001 /* R---V */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_REG_NO_FAULT 0x00000000 /* R-I-V */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_SE_LOGIC 8:8 /* R-IVF */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_SE_LOGIC_FAULTED 0x00000001 /* R---V */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_SE_LOGIC_NO_FAULT 0x00000000 /* R-I-V */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_SE_KSLT 9:9 /* R-IVF */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_SE_KSLT_FAULTED 0x00000001 /* R---V */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_SE_KSLT_NO_FAULT 0x00000000 /* R-I-V */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_TKE 10:10 /* R-IVF */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_TKE_FAULTED 0x00000001 /* R---V */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_TKE_NO_FAULT 0x00000000 /* R-I-V */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_FBIF 11:11 /* R-IVF */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_FBIF_FAULTED 0x00000001 /* R---V */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_FBIF_NO_FAULT 0x00000000 /* R-I-V */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_MPURAM 12:12 /* R-IVF */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_MPURAM_FAULTED 0x00000001 /* R---V */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_MPURAM_NO_FAULT 0x00000000 /* R-I-V */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_ENGINE_IN0 16:16 /* R-IVF */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_ENGINE_IN0_FAULTED 0x00000001 /* R---V */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_ENGINE_IN0_NO_FAULT 0x00000000 /* R-I-V */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_ENGINE_IN1 17:17 /* R-IVF */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_ENGINE_IN1_FAULTED 0x00000001 /* R---V */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_ENGINE_IN1_NO_FAULT 0x00000000 /* R-I-V */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_ENGINE_IN2 18:18 /* R-IVF */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_ENGINE_IN2_FAULTED 0x00000001 /* R---V */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_ENGINE_IN2_NO_FAULT 0x00000000 /* R-I-V */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_ENGINE_IN3 19:19 /* R-IVF */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_ENGINE_IN3_FAULTED 0x00000001 /* R---V */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_ENGINE_IN3_NO_FAULT 0x00000000 /* R-I-V */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_ENGINE_IN4 20:20 /* R-IVF */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_ENGINE_IN4_FAULTED 0x00000001 /* R---V */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_ENGINE_IN4_NO_FAULT 0x00000000 /* R-I-V */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_ENGINE_IN5 21:21 /* R-IVF */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_ENGINE_IN5_FAULTED 0x00000001 /* R---V */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_ENGINE_IN5_NO_FAULT 0x00000000 /* R-I-V */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_ENGINE_IN6 22:22 /* R-IVF */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_ENGINE_IN6_FAULTED 0x00000001 /* R---V */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_ENGINE_IN6_NO_FAULT 0x00000000 /* R-I-V */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_ENGINE_IN7 23:23 /* R-IVF */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_ENGINE_IN7_FAULTED 0x00000001 /* R---V */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_ENGINE_IN7_NO_FAULT 0x00000000 /* R-I-V */
#endif // __gb110_dev_riscv_pri_h__

92
src/common/inc/swref/published/blackwell/gb112/dev_riscv_pri.h Normal file
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@@ -0,0 +1,92 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2025 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gb112_dev_riscv_pri_h__
#define __gb112_dev_riscv_pri_h__
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT 0x00000700 /* R--4R */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_GLOBAL_MEM 0:0 /* R-IVF */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_GLOBAL_MEM_FAULTED 0x00000001 /* R---V */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_GLOBAL_MEM_NO_FAULT 0x00000000 /* R-I-V */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_ROM 1:1 /* R-IVF */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_ROM_FAULTED 0x00000001 /* R---V */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_ROM_NO_FAULT 0x00000000 /* R-I-V */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_ITCM 2:2 /* R-IVF */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_ITCM_FAULTED 0x00000001 /* R---V */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_ITCM_NO_FAULT 0x00000000 /* R-I-V */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_DTCM 3:3 /* R-IVF */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_DTCM_FAULTED 0x00000001 /* R---V */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_DTCM_NO_FAULT 0x00000000 /* R-I-V */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_ICACHE 4:4 /* R-IVF */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_ICACHE_FAULTED 0x00000001 /* R---V */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_ICACHE_NO_FAULT 0x00000000 /* R-I-V */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_DCACHE 5:5 /* R-IVF */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_DCACHE_FAULTED 0x00000001 /* R---V */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_DCACHE_NO_FAULT 0x00000000 /* R-I-V */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_RVCORE 6:6 /* R-IVF */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_RVCORE_FAULTED 0x00000001 /* R---V */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_RVCORE_NO_FAULT 0x00000000 /* R-I-V */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_REG 7:7 /* R-IVF */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_REG_FAULTED 0x00000001 /* R---V */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_REG_NO_FAULT 0x00000000 /* R-I-V */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_SE_LOGIC 8:8 /* R-IVF */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_SE_LOGIC_FAULTED 0x00000001 /* R---V */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_SE_LOGIC_NO_FAULT 0x00000000 /* R-I-V */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_SE_KSLT 9:9 /* R-IVF */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_SE_KSLT_FAULTED 0x00000001 /* R---V */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_SE_KSLT_NO_FAULT 0x00000000 /* R-I-V */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_TKE 10:10 /* R-IVF */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_TKE_FAULTED 0x00000001 /* R---V */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_TKE_NO_FAULT 0x00000000 /* R-I-V */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_FBIF 11:11 /* R-IVF */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_FBIF_FAULTED 0x00000001 /* R---V */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_FBIF_NO_FAULT 0x00000000 /* R-I-V */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_MPURAM 12:12 /* R-IVF */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_MPURAM_FAULTED 0x00000001 /* R---V */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_MPURAM_NO_FAULT 0x00000000 /* R-I-V */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_ENGINE_IN0 16:16 /* R-IVF */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_ENGINE_IN0_FAULTED 0x00000001 /* R---V */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_ENGINE_IN0_NO_FAULT 0x00000000 /* R-I-V */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_ENGINE_IN1 17:17 /* R-IVF */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_ENGINE_IN1_FAULTED 0x00000001 /* R---V */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_ENGINE_IN1_NO_FAULT 0x00000000 /* R-I-V */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_ENGINE_IN2 18:18 /* R-IVF */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_ENGINE_IN2_FAULTED 0x00000001 /* R---V */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_ENGINE_IN2_NO_FAULT 0x00000000 /* R-I-V */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_ENGINE_IN3 19:19 /* R-IVF */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_ENGINE_IN3_FAULTED 0x00000001 /* R---V */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_ENGINE_IN3_NO_FAULT 0x00000000 /* R-I-V */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_ENGINE_IN4 20:20 /* R-IVF */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_ENGINE_IN4_FAULTED 0x00000001 /* R---V */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_ENGINE_IN4_NO_FAULT 0x00000000 /* R-I-V */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_ENGINE_IN5 21:21 /* R-IVF */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_ENGINE_IN5_FAULTED 0x00000001 /* R---V */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_ENGINE_IN5_NO_FAULT 0x00000000 /* R-I-V */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_ENGINE_IN6 22:22 /* R-IVF */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_ENGINE_IN6_FAULTED 0x00000001 /* R---V */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_ENGINE_IN6_NO_FAULT 0x00000000 /* R-I-V */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_ENGINE_IN7 23:23 /* R-IVF */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_ENGINE_IN7_FAULTED 0x00000001 /* R---V */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_ENGINE_IN7_NO_FAULT 0x00000000 /* R-I-V */
#endif // __gb112_dev_riscv_pri_h__

56
src/common/inc/swref/published/blackwell/gb202/dev_boot.h
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@@ -1,56 +0,0 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gb202_dev_boot_h__
#define __gb202_dev_boot_h__
#define NV_SYSCTRL_SEC_FAULT 0x3:0x0 /* R---M */
#define NV_SYSCTRL_SEC_FAULT_BIT_POSITION_FUSE_POD 0:0 /* R-XUF */
#define NV_SYSCTRL_SEC_FAULT_BIT_POSITION_FUSE_SCPM 1:1 /* R-XUF */
#define NV_SYSCTRL_SEC_FAULT_BIT_POSITION_IFF_SEQUENCE_TOO_BIG 2:2 /* R-XUF */
#define NV_SYSCTRL_SEC_FAULT_BIT_POSITION_IFF_PRE_IFF_CRC_CHECK_FAILED 3:3 /* R-XUF */
#define NV_SYSCTRL_SEC_FAULT_BIT_POSITION_IFF_POST_IFF_CRC_CHECK_FAILED 4:4 /* R-XUF */
#define NV_SYSCTRL_SEC_FAULT_BIT_POSITION_IFF_ECC_UNCORRECTABLE_ERROR 5:5 /* R-XUF */
#define NV_SYSCTRL_SEC_FAULT_BIT_POSITION_IFF_CMD_FORMAT_ERROR 6:6 /* R-XUF */
#define NV_SYSCTRL_SEC_FAULT_BIT_POSITION_IFF_PRI_ERROR 7:7 /* R-XUF */
#define NV_SYSCTRL_SEC_FAULT_BIT_POSITION_FSP_SCPM 10:10 /* R-XUF */
#define NV_SYSCTRL_SEC_FAULT_BIT_POSITION_FSP_DCLS 11:11 /* R-XUF */
#define NV_SYSCTRL_SEC_FAULT_BIT_POSITION_FSP_EMP 12:12 /* R-XUF */
#define NV_SYSCTRL_SEC_FAULT_BIT_POSITION_FSP_UNCORRECTABLE_ERROR 13:13 /* R-XUF */
#define NV_SYSCTRL_SEC_FAULT_BIT_POSITION_FSP_L5_WDT 14:14 /* R-XUF */
#define NV_SYSCTRL_SEC_FAULT_BIT_POSITION_SEC2_SCPM 15:15 /* R-XUF */
#define NV_SYSCTRL_SEC_FAULT_BIT_POSITION_SEC2_DCLS 16:16 /* R-XUF */
#define NV_SYSCTRL_SEC_FAULT_BIT_POSITION_SEC2_L5_WDT 17:17 /* R-XUF */
#define NV_SYSCTRL_SEC_FAULT_BIT_POSITION_GSP_DCLS 18:18 /* R-XUF */
#define NV_SYSCTRL_SEC_FAULT_BIT_POSITION_GSP_L5_WDT 19:19 /* R-XUF */
#define NV_SYSCTRL_SEC_FAULT_BIT_POSITION_PMU_DCLS 20:20 /* R-XUF */
#define NV_SYSCTRL_SEC_FAULT_BIT_POSITION_PMU_L5_WDT 21:21 /* R-XUF */
#define NV_SYSCTRL_SEC_FAULT_BIT_POSITION_XTAL_CTFDC 22:22 /* R-XUF */
#define NV_SYSCTRL_SEC_FAULT_BIT_POSITION_CLOCK_XTAL_FMON 23:23 /* R-XUF */
#define NV_SYSCTRL_SEC_FAULT_BIT_POSITION_CLOCK_GPC_FMON 24:24 /* R-XUF */
#define NV_SYSCTRL_SEC_FAULT_BIT_POSITION_DEVICE_LOCKDOWN 30:30 /* R-XUF */
#define NV_SYSCTRL_SEC_FAULT_BIT_POSITION_FUNCTION_LOCKDOWN 31:31 /* R-XUF */
#define NV_SYSCTRL_SEC_FAULT_BIT_POSITION_INTERRUPT 32:32 /* R-XUF */
#endif // __gb202_dev_boot_h__

54
src/common/inc/swref/published/blackwell/gb202/dev_boot_zb.h Normal file
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@@ -0,0 +1,54 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gb202_dev_boot_zb_h__
#define __gb202_dev_boot_zb_h__
#define NV_SYSCTRL_SEC_FAULT 0x3:0x0 /* R---M */
#define NV_SYSCTRL_SEC_FAULT_BIT_POSITION_FUSE_POD 0:0 /* R-XUF */
#define NV_SYSCTRL_SEC_FAULT_BIT_POSITION_FUSE_SCPM 1:1 /* R-XUF */
#define NV_SYSCTRL_SEC_FAULT_BIT_POSITION_IFF_SEQUENCE_TOO_BIG 2:2 /* R-XUF */
#define NV_SYSCTRL_SEC_FAULT_BIT_POSITION_IFF_PRE_IFF_CRC_CHECK_FAILED 3:3 /* R-XUF */
#define NV_SYSCTRL_SEC_FAULT_BIT_POSITION_IFF_POST_IFF_CRC_CHECK_FAILED 4:4 /* R-XUF */
#define NV_SYSCTRL_SEC_FAULT_BIT_POSITION_IFF_ECC_UNCORRECTABLE_ERROR 5:5 /* R-XUF */
#define NV_SYSCTRL_SEC_FAULT_BIT_POSITION_IFF_CMD_FORMAT_ERROR 6:6 /* R-XUF */
#define NV_SYSCTRL_SEC_FAULT_BIT_POSITION_IFF_PRI_ERROR 7:7 /* R-XUF */
#define NV_SYSCTRL_SEC_FAULT_BIT_POSITION_FSP_SCPM 10:10 /* R-XUF */
#define NV_SYSCTRL_SEC_FAULT_BIT_POSITION_FSP_DCLS 11:11 /* R-XUF */
#define NV_SYSCTRL_SEC_FAULT_BIT_POSITION_FSP_EMP 12:12 /* R-XUF */
#define NV_SYSCTRL_SEC_FAULT_BIT_POSITION_FSP_UNCORRECTABLE_ERROR 13:13 /* R-XUF */
#define NV_SYSCTRL_SEC_FAULT_BIT_POSITION_FSP_L5_WDT 14:14 /* R-XUF */
#define NV_SYSCTRL_SEC_FAULT_BIT_POSITION_SEC2_SCPM 15:15 /* R-XUF */
#define NV_SYSCTRL_SEC_FAULT_BIT_POSITION_SEC2_DCLS 16:16 /* R-XUF */
#define NV_SYSCTRL_SEC_FAULT_BIT_POSITION_SEC2_L5_WDT 17:17 /* R-XUF */
#define NV_SYSCTRL_SEC_FAULT_BIT_POSITION_GSP_DCLS 18:18 /* R-XUF */
#define NV_SYSCTRL_SEC_FAULT_BIT_POSITION_GSP_L5_WDT 19:19 /* R-XUF */
#define NV_SYSCTRL_SEC_FAULT_BIT_POSITION_PMU_DCLS 20:20 /* R-XUF */
#define NV_SYSCTRL_SEC_FAULT_BIT_POSITION_PMU_L5_WDT 21:21 /* R-XUF */
#define NV_SYSCTRL_SEC_FAULT_BIT_POSITION_XTAL_CTFDC 22:22 /* R-XUF */
#define NV_SYSCTRL_SEC_FAULT_BIT_POSITION_CLOCK_XTAL_FMON 23:23 /* R-XUF */
#define NV_SYSCTRL_SEC_FAULT_BIT_POSITION_CLOCK_GPC_FMON 24:24 /* R-XUF */
#define NV_SYSCTRL_SEC_FAULT_BIT_POSITION_DEVICE_LOCKDOWN 30:30 /* R-XUF */
#define NV_SYSCTRL_SEC_FAULT_BIT_POSITION_FUNCTION_LOCKDOWN 31:31 /* R-XUF */
#define NV_SYSCTRL_SEC_FAULT_BIT_POSITION_INTERRUPT 32:32 /* R-XUF */
#endif // __gb202_dev_boot_zb_h__

44
src/common/inc/swref/published/blackwell/gb20b/dev_boot.h
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@@ -1,44 +0,0 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2024-2025 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gb20b_dev_boot_h__
#define __gb20b_dev_boot_h__
#define NV_PMC_SCRATCH_RESET_PLUS_2 0x000005e0 /* RW-4R */
#define NV_PMC_SCRATCH_RESET_PLUS_2__SAFETY "parity" /* */
#define NV_PMC_SCRATCH_RESET_PLUS_2__PRIV_LEVEL_MASK 0x000005e4 /* */
#define NV_PMC_SCRATCH_RESET_PLUS_2_VALUE 31:0 /* RWBVF */
#define NV_PMC_SCRATCH_RESET_PLUS_2_VALUE_INIT 0 /* RWB-V */
#define NV_SYSCTRL_SEC_FAULT 0x3:0x0 /* R---M */
#define NV_SYSCTRL_SEC_FAULT_BIT_POSITION_SEC2_DCLS 2:2 /* R-XUF */
#define NV_SYSCTRL_SEC_FAULT_BIT_POSITION_SEC2_L5_WDT 3:3 /* R-XUF */
#define NV_SYSCTRL_SEC_FAULT_BIT_POSITION_GSP_DCLS 4:4 /* R-XUF */
#define NV_SYSCTRL_SEC_FAULT_BIT_POSITION_GSP_L5_WDT 5:5 /* R-XUF */
#define NV_SYSCTRL_SEC_FAULT_BIT_POSITION_PMU_DCLS 6:6 /* R-XUF */
#define NV_SYSCTRL_SEC_FAULT_BIT_POSITION_PMU_L5_WDT 7:7 /* R-XUF */
#define NV_SYSCTRL_SEC_FAULT_BIT_POSITION_GPMVDD_VMON 8:8 /* R-XUF */
#define NV_SYSCTRL_SEC_FAULT_BIT_POSITION_GPCVDD_VMON 9:9 /* R-XUF */
#define NV_SYSCTRL_SEC_FAULT_BIT_POSITION_SOC2GPU_SEC_FAULT_FUNCTION_LOCKDOWN_REQ 10:10 /* R-XUF */
#define NV_SYSCTRL_SEC_FAULT_BIT_POSITION_FUNCTION_LOCKDOWN 11:11 /* R-XUF */
#define NV_SYSCTRL_SEC_FAULT_BIT_POSITION_DEVICE_LOCKDOWN 12:12 /* R-XUF */
#endif // __gb20b_dev_boot_h__

44
src/common/inc/swref/published/blackwell/gb20b/dev_boot_zb.h Normal file
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@@ -0,0 +1,44 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2025 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gb20b_dev_boot_zb_h__
#define __gb20b_dev_boot_zb_h__
#define NV_PMC_ZB_SCRATCH_RESET_PLUS_2 0x000005e0 /* RW-4R */
#define NV_PMC_ZB_SCRATCH_RESET_PLUS_2__SAFETY "parity" /* */
#define NV_PMC_ZB_SCRATCH_RESET_PLUS_2__PRIV_LEVEL_MASK 0x000005e4 /* */
#define NV_PMC_ZB_SCRATCH_RESET_PLUS_2_VALUE 31:0 /* RWBVF */
#define NV_PMC_ZB_SCRATCH_RESET_PLUS_2_VALUE_INIT 0 /* RWB-V */
#define NV_SYSCTRL_SEC_FAULT 0x3:0x0 /* R---M */
#define NV_SYSCTRL_SEC_FAULT_BIT_POSITION_SEC2_DCLS 2:2 /* R-XUF */
#define NV_SYSCTRL_SEC_FAULT_BIT_POSITION_SEC2_L5_WDT 3:3 /* R-XUF */
#define NV_SYSCTRL_SEC_FAULT_BIT_POSITION_GSP_DCLS 4:4 /* R-XUF */
#define NV_SYSCTRL_SEC_FAULT_BIT_POSITION_GSP_L5_WDT 5:5 /* R-XUF */
#define NV_SYSCTRL_SEC_FAULT_BIT_POSITION_PMU_DCLS 6:6 /* R-XUF */
#define NV_SYSCTRL_SEC_FAULT_BIT_POSITION_PMU_L5_WDT 7:7 /* R-XUF */
#define NV_SYSCTRL_SEC_FAULT_BIT_POSITION_GPMVDD_VMON 8:8 /* R-XUF */
#define NV_SYSCTRL_SEC_FAULT_BIT_POSITION_GPCVDD_VMON 9:9 /* R-XUF */
#define NV_SYSCTRL_SEC_FAULT_BIT_POSITION_SOC2GPU_SEC_FAULT_FUNCTION_LOCKDOWN_REQ 10:10 /* R-XUF */
#define NV_SYSCTRL_SEC_FAULT_BIT_POSITION_FUNCTION_LOCKDOWN 11:11 /* R-XUF */
#define NV_SYSCTRL_SEC_FAULT_BIT_POSITION_DEVICE_LOCKDOWN 12:12 /* R-XUF */
#endif // __gb20b_dev_boot_zb_h__

36
src/common/inc/swref/published/blackwell/gb20b/dev_bus.h Normal file
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@@ -0,0 +1,36 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2025 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gb20b_dev_bus_h__
#define __gb20b_dev_bus_h__
#define NV_PBUS_SW_SCRATCH(i) (0x00001400+(i)*4) /* RW-4A */
#define NV_PBUS_SW_SCRATCH__SIZE_1 64 /* */
#define NV_PBUS_SW_SCRATCH_FIELD 31:0 /* RWBVF */
#define NV_PBUS_SW_SCRATCH_FIELD_INIT 0x00000000 /* RWB-V */
#define NV_PBUS0_SW_SCRATCH(i) (0x00001400+(i)*4) /* RW-4A */
#define NV_PBUS0_SW_SCRATCH__SIZE_1 64 /* */
#define NV_PBUS0_SW_SCRATCH_FIELD 31:0 /* RWBVF */
#define NV_PBUS0_SW_SCRATCH_FIELD_INIT 0x00000000 /* RWB-V */
#endif // __gb20b_dev_bus_h__

7
src/common/inc/swref/published/blackwell/gb20b/dev_gsp.h
View File

@@ -30,6 +30,13 @@
#define NV_PGSP_MAILBOX_DATA 31:0 /* RWIVF */
#define NV_PGSP_MAILBOX_DATA_INIT 0x00000000 /* RWI-V */
#define NV_PGSP_FALCON_MAILBOX0 0x00110040 /* RW-4R */
#define NV_PGSP_FALCON_MAILBOX0_DATA 31:0 /* RWIVF */
#define NV_PGSP_FALCON_MAILBOX0_DATA_INIT 0x00000000 /* RWI-V */
#define NV_PGSP_FALCON_MAILBOX1 0x00110044 /* RW-4R */
#define NV_PGSP_FALCON_MAILBOX1_DATA 31:0 /* RWIVF */
#define NV_PGSP_FALCON_MAILBOX1_DATA_INIT 0x00000000 /* RWI-V */
#define NV_PGSP_QUEUE_HEAD(i) (0x00110c00+(i)*8) /* RW-4A */
#define NV_PGSP_QUEUE_HEAD__SIZE_1 8 /* */
#define NV_PGSP_QUEUE_TAIL(i) (0x00110c04+(i)*8) /* RW-4A */

7
src/common/inc/swref/published/blackwell/gb20b/dev_sec_pri.h
View File

@@ -59,4 +59,11 @@
#define NV_PSEC_MSGQ_TAIL_VAL 31:0 /* RWIUF */
#define NV_PSEC_MSGQ_TAIL_VAL_INIT 0x00000000 /* RWI-V */
#define NV_PSEC_FALCON_COMMON_SCRATCH_GROUP_2(i) (0x00840320+(i)*4) /* RW-4A */
#define NV_PSEC_FALCON_COMMON_SCRATCH_GROUP_2__SIZE_1 4 /* */
#define NV_PSEC_FALCON_COMMON_SCRATCH_GROUP_2__DEVICE_MAP 0x00000016 /* */
#define NV_PSEC_FALCON_COMMON_SCRATCH_GROUP_2__PRIV_LEVEL_MASK 0x008403f8 /* */
#define NV_PSEC_FALCON_COMMON_SCRATCH_GROUP_2_VAL 31:0 /* RWIVF */
#define NV_PSEC_FALCON_COMMON_SCRATCH_GROUP_2_VAL_INIT 0x00000000 /* RWI-V */
#endif // __gb20b_dev_sec_pri_h__

30
src/common/inc/swref/published/blackwell/gb20b/hwproject.h Normal file
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@@ -0,0 +1,30 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2025 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gb20b_hwproject_h__
#define __gb20b_hwproject_h__
#define NV_PMC0_PRI_BASE 0x0
#endif // __gb20b_hwproject_h__

18
src/common/inc/swref/published/blackwell/gb100/dev_boot.h → src/common/inc/swref/published/blackwell/gb20c/dev_disp_misc.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -21,12 +21,10 @@
* DEALINGS IN THE SOFTWARE.
*/
#ifndef gb100_dev_boot_h
#define gb100_dev_boot_h
#define NV_PMC_SCRATCH_RESET_2(i) (0x00000580+(i)*4) /* RW-4A */
#define NV_PMC_SCRATCH_RESET_2__SIZE_1 16 /* */
#define NV_PMC_SCRATCH_RESET_2_VALUE 31:0 /* RWBVF */
#define NV_PMC_SCRATCH_RESET_2_VALUE_INIT 0 /* RWB-V */
#endif // gb100_dev_boot_h
#ifndef __gb20c_dev_disp_misc_h__
#define __gb20c_dev_disp_misc_h__
#define NV_PDISP_MISC_SDM_RESOURCE 0x02290008
#define NV_PDISP_MISC_SDM_RESOURCE_NVDISPLAY 0:0
#define NV_PDISP_MISC_SDM_RESOURCE_NVDISPLAY_SDM 0x1
#define NV_PDISP_MISC_SDM_RESOURCE_NVDISPLAY_INIT 0x0
#endif // __gb20c_dev_disp_misc_h__

23
src/common/inc/swref/published/hopper/gh100/dev_fb.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES
* SPDX-FileCopyrightText: Copyright (c) 2003-2025 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -30,4 +30,25 @@
#define NV_PFB_FBHUB_PCIE_FLUSH_SYSMEM_ADDR_HI_ADR 31:0 /* RWIVF */
#define NV_PFB_FBHUB_PCIE_FLUSH_SYSMEM_ADDR_HI_ADR_MASK 0x000FFFFF /* ----V */
#define NV_PFB_PRI_MMU_WPR1_ADDR_LO 0x001FA81C /* RW-4R */
#define NV_PFB_PRI_MMU_WPR1_ADDR_LO__PRIV_LEVEL_MASK 0x001FA7CC /* */
#define NV_PFB_PRI_MMU_WPR1_ADDR_LO_VAL 31:4 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR1_ADDR_LO_VAL_INIT 0x0fffffff /* RWE-V */
#define NV_PFB_PRI_MMU_WPR1_ADDR_LO_ALIGNMENT 0x0000000c /* */
#define NV_PFB_PRI_MMU_WPR1_ADDR_HI 0x001FA820 /* RW-4R */
#define NV_PFB_PRI_MMU_WPR1_ADDR_HI__PRIV_LEVEL_MASK 0x001FA7CC /* */
#define NV_PFB_PRI_MMU_WPR1_ADDR_HI_VAL 31:4 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR1_ADDR_HI_VAL_INIT 0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_WPR1_ADDR_HI_ALIGNMENT 0x0000000c /* */
#define NV_PFB_PRI_MMU_WPR2_ADDR_LO 0x001FA824 /* RW-4R */
#define NV_PFB_PRI_MMU_WPR2_ADDR_LO__PRIV_LEVEL_MASK 0x001FA7CC /* */
#define NV_PFB_PRI_MMU_WPR2_ADDR_LO_VAL 31:4 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR2_ADDR_LO_VAL_INIT 0x0fffffff /* RWE-V */
#define NV_PFB_PRI_MMU_WPR2_ADDR_LO_ALIGNMENT 0x0000000c /* */
#define NV_PFB_PRI_MMU_WPR2_ADDR_HI 0x001FA828 /* RW-4R */
#define NV_PFB_PRI_MMU_WPR2_ADDR_HI__PRIV_LEVEL_MASK 0x001FA7CC /* */
#define NV_PFB_PRI_MMU_WPR2_ADDR_HI_VAL 31:4 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR2_ADDR_HI_VAL_INIT 0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_WPR2_ADDR_HI_ALIGNMENT 0x0000000c /* */
#endif // __gh100_dev_fb_h_

47
src/common/inc/swref/published/hopper/gh100/dev_fuse_zb.h Normal file
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@@ -0,0 +1,47 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2025 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gh100_dev_fuse_zb_h__
#define __gh100_dev_fuse_zb_h__
#define NV_FUSE_ZB_SPARE_BIT_0 0x00004E04 /* RW-4R */
#define NV_FUSE_ZB_SPARE_BIT_0_DATA 0:0 /* RWIVF */
#define NV_FUSE_ZB_SPARE_BIT_0_DATA_INIT 0x00000000 /* RWI-V */
#define NV_FUSE_ZB_SPARE_BIT_0_DATA_DISABLE 0x00000000 /* RW--V */
#define NV_FUSE_ZB_SPARE_BIT_0_DATA_ENABLE 0x00000001 /* RW--V */
#define NV_FUSE_ZB_SPARE_BIT_1 0x00004E08 /* RW-4R */
#define NV_FUSE_ZB_SPARE_BIT_1_DATA 0:0 /* RWIVF */
#define NV_FUSE_ZB_SPARE_BIT_1_DATA_INIT 0x00000000 /* RWI-V */
#define NV_FUSE_ZB_SPARE_BIT_1_DATA_DISABLE 0x00000000 /* RW--V */
#define NV_FUSE_ZB_SPARE_BIT_1_DATA_ENABLE 0x00000001 /* RW--V */
#define NV_FUSE_ZB_SPARE_BIT_2 0x00004E0C /* RW-4R */
#define NV_FUSE_ZB_SPARE_BIT_2_DATA 0:0 /* RWIVF */
#define NV_FUSE_ZB_SPARE_BIT_2_DATA_INIT 0x00000000 /* RWI-V */
#define NV_FUSE_ZB_SPARE_BIT_2_DATA_DISABLE 0x00000000 /* RW--V */
#define NV_FUSE_ZB_SPARE_BIT_2_DATA_ENABLE 0x00000001 /* RW--V */
#define NV_FUSE_ZB_OPT_SECURE_GSP_DEBUG_DIS 0x0000074C /* RW-4R */
#define NV_FUSE_ZB_OPT_SECURE_GSP_DEBUG_DIS_DATA 0:0 /* RWIVF */
#define NV_FUSE_ZB_OPT_SECURE_GSP_DEBUG_DIS_DATA_NO 0x00000000 /* RW--V */
#define NV_FUSE_ZB_OPT_SECURE_GSP_DEBUG_DIS_DATA_YES 0x00000001 /* RW--V */
#endif // __gh100_dev_fuse_zb_h__

26
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@@ -0,0 +1,26 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2025 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gh100_dev_nv_xal_ep_p2p_zb_h__
#define __gh100_dev_nv_xal_ep_p2p_zb_h__
#define NV_XAL_EP_P2P_ZB 0x00001fff:0x00000000 /* RW--D */
#endif // __gh100_dev_nv_xal_ep_p2p_zb_h__

27
src/common/inc/swref/published/hopper/gh100/dev_nv_xal_ep_zb.h Normal file
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@@ -0,0 +1,27 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2025 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gh100_dev_nv_xal_ep_zb_h__
#define __gh100_dev_nv_xal_ep_zb_h__
#define NV_XAL_EP_ZB 0x00000FFF:0x00000000 /* RW--D */
#endif // __gh100_dev_nv_xal_ep_zb_h__

7
src/common/inc/swref/published/hopper/gh100/hwproject.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES
* SPDX-FileCopyrightText: Copyright (c) 2003-2025 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -28,5 +28,10 @@
#define NV_XPL_BASE_ADDRESS 540672
#define NV_XTL_BASE_ADDRESS 593920
#define NV_FBPA_PRI_STRIDE 16384
#define NV_FUSE0_PRI_BASE 8519680
#define NV_XAL_BASE_ADDRESS 1110016
#define NV_XAL_FUNC_BASE_ADDRESS 8585216
#define NV_XAL_P2P_BASE_ADDRESS 8544256
#define NV_FBPA_PRI_STRIDE 16384
#endif // GH100_HWPROJECT_H_INCLUDED

42
src/common/inc/swref/published/maxwell/gm107/dev_hubmmu_base_addendum.h Normal file
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/*
* SPDX-FileCopyrightText: Copyright (c) 2025 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gm107_dev_hubmmu_base_addendum_h__
#define __gm107_dev_hubmmu_base_addendum_h__
#define NV_HUBMMU_PRI_MMU_INVALIDATE_ALL_VA NV_PFB_PRI_MMU_INVALIDATE_ALL_VA
#define NV_HUBMMU_PRI_MMU_INVALIDATE_ALL_VA_FALSE NV_PFB_PRI_MMU_INVALIDATE_ALL_VA_FALSE
#define NV_HUBMMU_PRI_MMU_INVALIDATE_ALL_VA_TRUE NV_PFB_PRI_MMU_INVALIDATE_ALL_VA_TRUE
#define NV_HUBMMU_PRI_MMU_INVALIDATE_ALL_PDB NV_PFB_PRI_MMU_INVALIDATE_ALL_PDB
#define NV_HUBMMU_PRI_MMU_INVALIDATE_ALL_PDB_FALSE NV_PFB_PRI_MMU_INVALIDATE_ALL_PDB_FALSE
#define NV_HUBMMU_PRI_MMU_INVALIDATE_ALL_PDB_TRUE NV_PFB_PRI_MMU_INVALIDATE_ALL_PDB_TRUE
#define NV_HUBMMU_PRI_MMU_INVALIDATE_TRIGGER NV_PFB_PRI_MMU_INVALIDATE_TRIGGER
#define NV_HUBMMU_PRI_MMU_INVALIDATE_TRIGGER_FALSE NV_PFB_PRI_MMU_INVALIDATE_TRIGGER_FALSE
#define NV_HUBMMU_PRI_MMU_INVALIDATE_TRIGGER_TRUE NV_PFB_PRI_MMU_INVALIDATE_TRIGGER_TRUE
#define NV_HUBMMU_PRI_MMU_INVALIDATE_HUBTLB_ONLY NV_PFB_PRI_MMU_INVALIDATE_HUBTLB_ONLY
#define NV_HUBMMU_PRI_MMU_INVALIDATE_HUBTLB_ONLY_FALSE NV_PFB_PRI_MMU_INVALIDATE_HUBTLB_ONLY_FALSE
#define NV_HUBMMU_PRI_MMU_INVALIDATE_HUBTLB_ONLY_TRUE NV_PFB_PRI_MMU_INVALIDATE_HUBTLB_ONLY_TRUE
#define NV_HUBMMU_PRI_MMU_INVALIDATE_PDB_APERTURE_VID_MEM NV_PFB_PRI_MMU_INVALIDATE_PDB_APERTURE_VID_MEM
#define NV_HUBMMU_PRI_MMU_INVALIDATE_PDB_APERTURE_SYS_MEM NV_PFB_PRI_MMU_INVALIDATE_PDB_APERTURE_SYS_MEM
#endif // __gm107_dev_hubmmu_base_addendum_h__

67
src/common/inc/swref/published/pascal/gp100/dev_hubmmu_base_addendum.h Normal file
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@@ -0,0 +1,67 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2025 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gp100_dev_hubmmu_base_addendum_h__
#define __gp100_dev_hubmmu_base_addendum_h__
#define NV_HUBMMU_PRI_MMU_INVALIDATE_HUBTLB_ONLY NV_PFB_PRI_MMU_INVALIDATE_HUBTLB_ONLY
#define NV_HUBMMU_PRI_MMU_INVALIDATE_HUBTLB_ONLY_FALSE NV_PFB_PRI_MMU_INVALIDATE_HUBTLB_ONLY_FALSE
#define NV_HUBMMU_PRI_MMU_INVALIDATE_HUBTLB_ONLY_TRUE NV_PFB_PRI_MMU_INVALIDATE_HUBTLB_ONLY_TRUE
#define NV_HUBMMU_PRI_MMU_INVALIDATE_REPLAY NV_PFB_PRI_MMU_INVALIDATE_REPLAY
#define NV_HUBMMU_PRI_MMU_INVALIDATE_REPLAY_NONE NV_PFB_PRI_MMU_INVALIDATE_REPLAY_NONE
#define NV_HUBMMU_PRI_MMU_INVALIDATE_REPLAY_START NV_PFB_PRI_MMU_INVALIDATE_REPLAY_START
#define NV_HUBMMU_PRI_MMU_INVALIDATE_REPLAY_START_ACK_ALL NV_PFB_PRI_MMU_INVALIDATE_REPLAY_START_ACK_ALL
#define NV_HUBMMU_PRI_MMU_INVALIDATE_REPLAY_CANCEL_TARGETED NV_PFB_PRI_MMU_INVALIDATE_REPLAY_CANCEL_TARGETED
#define NV_HUBMMU_PRI_MMU_INVALIDATE_REPLAY_CANCEL_GLOBAL NV_PFB_PRI_MMU_INVALIDATE_REPLAY_CANCEL_GLOBAL
#define NV_HUBMMU_PRI_MMU_INVALIDATE_SYS_MEMBAR NV_PFB_PRI_MMU_INVALIDATE_SYS_MEMBAR
#define NV_HUBMMU_PRI_MMU_INVALIDATE_SYS_MEMBAR_FALSE NV_PFB_PRI_MMU_INVALIDATE_SYS_MEMBAR_FALSE
#define NV_HUBMMU_PRI_MMU_INVALIDATE_SYS_MEMBAR_TRUE NV_PFB_PRI_MMU_INVALIDATE_SYS_MEMBAR_TRUE
#define NV_HUBMMU_PRI_MMU_INVALIDATE_ACK NV_PFB_PRI_MMU_INVALIDATE_ACK
#define NV_HUBMMU_PRI_MMU_INVALIDATE_ACK_NONE_REQUIRED NV_PFB_PRI_MMU_INVALIDATE_ACK_NONE_REQUIRED
#define NV_HUBMMU_PRI_MMU_INVALIDATE_ACK_INTRANODE NV_PFB_PRI_MMU_INVALIDATE_ACK_INTRANODE
#define NV_HUBMMU_PRI_MMU_INVALIDATE_ACK_GLOBALLY NV_PFB_PRI_MMU_INVALIDATE_ACK_GLOBALLY
#define NV_HUBMMU_PRI_MMU_INVALIDATE_CANCEL_CLIENT_ID NV_PFB_PRI_MMU_INVALIDATE_CANCEL_CLIENT_ID
#define NV_HUBMMU_PRI_MMU_INVALIDATE_CANCEL_GPC_ID NV_PFB_PRI_MMU_INVALIDATE_CANCEL_GPC_ID
#define NV_HUBMMU_PRI_MMU_INVALIDATE_CANCEL_CLIENT_TYPE NV_PFB_PRI_MMU_INVALIDATE_CANCEL_CLIENT_TYPE
#define NV_HUBMMU_PRI_MMU_INVALIDATE_CANCEL_CLIENT_TYPE_GPC NV_PFB_PRI_MMU_INVALIDATE_CANCEL_CLIENT_TYPE_GPC
#define NV_HUBMMU_PRI_MMU_INVALIDATE_CANCEL_CLIENT_TYPE_HUB NV_PFB_PRI_MMU_INVALIDATE_CANCEL_CLIENT_TYPE_HUB
#define NV_HUBMMU_PRI_MMU_INVALIDATE_CACHE_LEVEL NV_PFB_PRI_MMU_INVALIDATE_CACHE_LEVEL
#define NV_HUBMMU_PRI_MMU_INVALIDATE_CACHE_LEVEL_ALL NV_PFB_PRI_MMU_INVALIDATE_CACHE_LEVEL_ALL
#define NV_HUBMMU_PRI_MMU_INVALIDATE_CACHE_LEVEL_PTE_ONLY NV_PFB_PRI_MMU_INVALIDATE_CACHE_LEVEL_PTE_ONLY
#define NV_HUBMMU_PRI_MMU_INVALIDATE_CACHE_LEVEL_UP_TO_PDE0 NV_PFB_PRI_MMU_INVALIDATE_CACHE_LEVEL_UP_TO_PDE0
#define NV_HUBMMU_PRI_MMU_INVALIDATE_CACHE_LEVEL_UP_TO_PDE1 NV_PFB_PRI_MMU_INVALIDATE_CACHE_LEVEL_UP_TO_PDE1
#define NV_HUBMMU_PRI_MMU_INVALIDATE_CACHE_LEVEL_UP_TO_PDE2 NV_PFB_PRI_MMU_INVALIDATE_CACHE_LEVEL_UP_TO_PDE2
#define NV_HUBMMU_PRI_MMU_INVALIDATE_CACHE_LEVEL_UP_TO_PDE3 NV_PFB_PRI_MMU_INVALIDATE_CACHE_LEVEL_UP_TO_PDE3
#define NV_HUBMMU_PRI_MMU_INVALIDATE_CACHE_LEVEL_UP_TO_PDE4 NV_PFB_PRI_MMU_INVALIDATE_CACHE_LEVEL_UP_TO_PDE4
#define NV_HUBMMU_PRI_MMU_INVALIDATE_CACHE_LEVEL_UP_TO_PDE5 NV_PFB_PRI_MMU_INVALIDATE_CACHE_LEVEL_UP_TO_PDE5
#define NV_HUBMMU_PRI_MMU_INVALIDATE_ALL_VA NV_PFB_PRI_MMU_INVALIDATE_ALL_VA
#define NV_HUBMMU_PRI_MMU_INVALIDATE_ALL_VA_FALSE NV_PFB_PRI_MMU_INVALIDATE_ALL_VA_FALSE
#define NV_HUBMMU_PRI_MMU_INVALIDATE_ALL_VA_TRUE NV_PFB_PRI_MMU_INVALIDATE_ALL_VA_TRUE
#define NV_HUBMMU_PRI_MMU_INVALIDATE_ALL_PDB NV_PFB_PRI_MMU_INVALIDATE_ALL_PDB
#define NV_HUBMMU_PRI_MMU_INVALIDATE_ALL_PDB_FALSE NV_PFB_PRI_MMU_INVALIDATE_ALL_PDB_FALSE
#define NV_HUBMMU_PRI_MMU_INVALIDATE_ALL_PDB_TRUE NV_PFB_PRI_MMU_INVALIDATE_ALL_PDB_TRUE
#define NV_HUBMMU_PRI_MMU_INVALIDATE_TRIGGER NV_PFB_PRI_MMU_INVALIDATE_TRIGGER
#define NV_HUBMMU_PRI_MMU_INVALIDATE_TRIGGER_FALSE NV_PFB_PRI_MMU_INVALIDATE_TRIGGER_FALSE
#define NV_HUBMMU_PRI_MMU_INVALIDATE_TRIGGER_TRUE NV_PFB_PRI_MMU_INVALIDATE_TRIGGER_TRUE
#endif // __gp100_dev_hubmmu_base_addendum_h__

82
src/common/inc/swref/published/volta/gv100/dev_hubmmu_base_addendum.h Normal file
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@@ -0,0 +1,82 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2025 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gv100_dev_hubmmu_base_addendum_h__
#define __gv100_dev_hubmmu_base_addendum_h__
#define NV_HUBMMU_PRI_MMU_FAULT_BUFFER_GET_PTR NV_PFB_PRI_MMU_FAULT_BUFFER_GET_PTR
#define NV_HUBMMU_PRI_MMU_FAULT_BUFFER_PUT_PTR NV_PFB_PRI_MMU_FAULT_BUFFER_PUT_PTR
#define NV_HUBMMU_PRI_MMU_FAULT_STATUS_REPLAYABLE_GETPTR_CORRUPTED NV_PFB_PRI_MMU_FAULT_STATUS_REPLAYABLE_GETPTR_CORRUPTED
#define NV_HUBMMU_PRI_MMU_FAULT_STATUS_REPLAYABLE_GETPTR_CORRUPTED_RESET NV_PFB_PRI_MMU_FAULT_STATUS_REPLAYABLE_GETPTR_CORRUPTED_RESET
#define NV_HUBMMU_PRI_MMU_FAULT_STATUS_REPLAYABLE_GETPTR_CORRUPTED_SET NV_PFB_PRI_MMU_FAULT_STATUS_REPLAYABLE_GETPTR_CORRUPTED_SET
#define NV_HUBMMU_PRI_MMU_FAULT_STATUS_NON_REPLAYABLE_GETPTR_CORRUPTED NV_PFB_PRI_MMU_FAULT_STATUS_NON_REPLAYABLE_GETPTR_CORRUPTED
#define NV_HUBMMU_PRI_MMU_FAULT_STATUS_NON_REPLAYABLE_GETPTR_CORRUPTED_RESET NV_PFB_PRI_MMU_FAULT_STATUS_NON_REPLAYABLE_GETPTR_CORRUPTED_RESET
#define NV_HUBMMU_PRI_MMU_FAULT_STATUS_NON_REPLAYABLE_GETPTR_CORRUPTED_SET NV_PFB_PRI_MMU_FAULT_STATUS_NON_REPLAYABLE_GETPTR_CORRUPTED_SET
#define NV_HUBMMU_PRI_MMU_FAULT_STATUS_NON_REPLAYABLE_OVERFLOW NV_PFB_PRI_MMU_FAULT_STATUS_NON_REPLAYABLE_OVERFLOW
#define NV_HUBMMU_PRI_MMU_FAULT_STATUS_NON_REPLAYABLE_OVERFLOW_RESET NV_PFB_PRI_MMU_FAULT_STATUS_NON_REPLAYABLE_OVERFLOW_RESET
#define NV_HUBMMU_PRI_MMU_FAULT_STATUS_NON_REPLAYABLE_OVERFLOW_SET NV_PFB_PRI_MMU_FAULT_STATUS_NON_REPLAYABLE_OVERFLOW_SET
#define NV_HUBMMU_PRI_MMU_NON_REPLAY_FAULT_BUFFER NV_PFB_PRI_MMU_NON_REPLAY_FAULT_BUFFER
#define NV_HUBMMU_PRI_MMU_REPLAY_FAULT_BUFFER NV_PFB_PRI_MMU_REPLAY_FAULT_BUFFER
#define NV_HUBMMU_PRI_MMU_FAULT_BUFFER_SIZE_OVERFLOW_INTR NV_PFB_PRI_MMU_FAULT_BUFFER_SIZE_OVERFLOW_INTR
#define NV_HUBMMU_PRI_MMU_FAULT_BUFFER_SIZE_OVERFLOW_INTR_DISABLE NV_PFB_PRI_MMU_FAULT_BUFFER_SIZE_OVERFLOW_INTR_DISABLE
#define NV_HUBMMU_PRI_MMU_FAULT_BUFFER_SIZE_OVERFLOW_INTR_ENABLE NV_PFB_PRI_MMU_FAULT_BUFFER_SIZE_OVERFLOW_INTR_ENABLE
#define NV_HUBMMU_PRI_MMU_FAULT_BUFFER_SIZE_ENABLE NV_PFB_PRI_MMU_FAULT_BUFFER_SIZE_ENABLE
#define NV_HUBMMU_PRI_MMU_FAULT_BUFFER_SIZE_ENABLE_FALSE NV_PFB_PRI_MMU_FAULT_BUFFER_SIZE_ENABLE_FALSE
#define NV_HUBMMU_PRI_MMU_FAULT_BUFFER_SIZE_ENABLE_TRUE NV_PFB_PRI_MMU_FAULT_BUFFER_SIZE_ENABLE_TRUE
#define NV_HUBMMU_PRI_MMU_FAULT_STATUS_BUSY NV_PFB_PRI_MMU_FAULT_STATUS_BUSY
#define NV_HUBMMU_PRI_MMU_FAULT_STATUS_BUSY_FALSE NV_PFB_PRI_MMU_FAULT_STATUS_BUSY_FALSE
#define NV_HUBMMU_PRI_MMU_FAULT_STATUS_BUSY_TRUE NV_PFB_PRI_MMU_FAULT_STATUS_BUSY_TRUE
#define NV_HUBMMU_PRI_MMU_FAULT_STATUS_REPLAYABLE_ERROR NV_PFB_PRI_MMU_FAULT_STATUS_REPLAYABLE_ERROR
#define NV_HUBMMU_PRI_MMU_FAULT_STATUS_REPLAYABLE_ERROR_RESET NV_PFB_PRI_MMU_FAULT_STATUS_REPLAYABLE_ERROR_RESET
#define NV_HUBMMU_PRI_MMU_FAULT_STATUS_REPLAYABLE_ERROR_SET NV_PFB_PRI_MMU_FAULT_STATUS_REPLAYABLE_ERROR_SET
#define NV_HUBMMU_PRI_MMU_FAULT_STATUS_NON_REPLAYABLE_ERROR NV_PFB_PRI_MMU_FAULT_STATUS_NON_REPLAYABLE_ERROR
#define NV_HUBMMU_PRI_MMU_FAULT_STATUS_NON_REPLAYABLE_ERROR_RESET NV_PFB_PRI_MMU_FAULT_STATUS_NON_REPLAYABLE_ERROR_RESET
#define NV_HUBMMU_PRI_MMU_FAULT_STATUS_NON_REPLAYABLE_ERROR_SET NV_PFB_PRI_MMU_FAULT_STATUS_NON_REPLAYABLE_ERROR_SET
#define NV_HUBMMU_PRI_MMU_FAULT_STATUS_VALID NV_PFB_PRI_MMU_FAULT_STATUS_VALID
#define NV_HUBMMU_PRI_MMU_FAULT_STATUS_VALID_CLEAR NV_PFB_PRI_MMU_FAULT_STATUS_VALID_CLEAR
#define NV_HUBMMU_PRI_MMU_FAULT_STATUS_VALID_SET NV_PFB_PRI_MMU_FAULT_STATUS_VALID_SET
#define NV_HUBMMU_PRI_MMU_FAULT_INST_LO_ENGINE_ID NV_PFB_PRI_MMU_FAULT_INST_LO_ENGINE_ID
#define NV_HUBMMU_PRI_MMU_FAULT_INST_LO_APERTURE NV_PFB_PRI_MMU_FAULT_INST_LO_APERTURE
#define NV_HUBMMU_PRI_MMU_FAULT_INST_LO_ADDR NV_PFB_PRI_MMU_FAULT_INST_LO_ADDR
#define NV_HUBMMU_PRI_MMU_FAULT_INST_HI_ADDR NV_PFB_PRI_MMU_FAULT_INST_HI_ADDR
#define NV_HUBMMU_PRI_MMU_FAULT_ADDR_LO_ADDR NV_PFB_PRI_MMU_FAULT_ADDR_LO_ADDR
#define NV_HUBMMU_PRI_MMU_FAULT_ADDR_HI_ADDR NV_PFB_PRI_MMU_FAULT_ADDR_HI_ADDR
#define NV_HUBMMU_PRI_MMU_FAULT_INFO_FAULT_TYPE NV_PFB_PRI_MMU_FAULT_INFO_FAULT_TYPE
#define NV_HUBMMU_PRI_MMU_FAULT_INFO_FAULT_TYPE_RESET NV_PFB_PRI_MMU_FAULT_INFO_FAULT_TYPE_RESET
#define NV_HUBMMU_PRI_MMU_FAULT_INFO_REPLAYABLE_FAULT NV_PFB_PRI_MMU_FAULT_INFO_REPLAYABLE_FAULT
#define NV_HUBMMU_PRI_MMU_FAULT_INFO_CLIENT NV_PFB_PRI_MMU_FAULT_INFO_CLIENT
#define NV_HUBMMU_PRI_MMU_FAULT_INFO_CLIENT_RESET NV_PFB_PRI_MMU_FAULT_INFO_CLIENT_RESET
#define NV_HUBMMU_PRI_MMU_FAULT_INFO_ACCESS_TYPE NV_PFB_PRI_MMU_FAULT_INFO_ACCESS_TYPE
#define NV_HUBMMU_PRI_MMU_FAULT_INFO_CLIENT_TYPE NV_PFB_PRI_MMU_FAULT_INFO_CLIENT_TYPE
#define NV_HUBMMU_PRI_MMU_FAULT_INFO_GPC_ID NV_PFB_PRI_MMU_FAULT_INFO_GPC_ID
#define NV_HUBMMU_PRI_MMU_FAULT_INFO_PROTECTED_MODE NV_PFB_PRI_MMU_FAULT_INFO_PROTECTED_MODE
#define NV_HUBMMU_PRI_MMU_FAULT_INFO_REPLAYABLE_FAULT_EN NV_PFB_PRI_MMU_FAULT_INFO_REPLAYABLE_FAULT_EN
#define NV_HUBMMU_PRI_MMU_FAULT_INFO_VALID NV_PFB_PRI_MMU_FAULT_INFO_VALID
#endif // __gv100_dev_hubmmu_base_addendum_h__

4
src/common/modeset/timing/nvt_dsc_pps.c
View File

@@ -2817,7 +2817,7 @@ DSC_GeneratePPS
((pWARData->dpData.dpMode == DSC_DP_MST) ||
pWARData->dpData.bIs128b132bChannelCoding)))
{
eff_bpp = _calculateEffectiveBppForDSC(pDscInfo, pModesetInfo, pWARData, in->bits_per_pixel, in);
eff_bpp = _calculateEffectiveBppForDSC(pDscInfo, pModesetInfo, pWARData, in->bits_per_pixel, in);
}
}
@@ -2888,7 +2888,7 @@ DSC_GeneratePPS
ret = NVT_STATUS_INVALID_PARAMETER;
goto done;
}
if (in->native_422)
{
// bits_per_pixel in PPS is defined as 5 fractional bits in native422 mode

7
src/common/modeset/timing/nvt_edidext_861.c
View File

@@ -3149,6 +3149,13 @@ void NvTiming_ConstructAdaptiveSyncSDP(
NVT_DP_ADAPTIVE_SYNC_SDP_DB0_VARIABLE_FRAME_RATE_SHIFT);
}
if (pCtrl->bDisableSourceSinkSync)
{
nvt_nvu8_set_bits(pSdp->payload.db0, NVT_DP_ADAPTIVE_SYNC_SDP_DB0_DISABLE_PR_ACTIVE_SOURCE_SINK_SYNC_DISABLED,
NVT_DP_ADAPTIVE_SYNC_SDP_DB0_DISABLE_PR_ACTIVE_MASK,
NVT_DP_ADAPTIVE_SYNC_SDP_DB0_DISABLE_PR_ACTIVE_SHIFT);
}
if (pCtrl->minVTotal)
{
nvt_nvu8_set_bits(pSdp->payload.db1, pCtrl->minVTotal & 0xff,

43
src/common/modeset/timing/nvt_ovt.c
View File

@@ -32,9 +32,8 @@
#include "nvmisc.h"
#include "nvtiming_pvt.h"
PUSH_SEGMENTS
CONS_SEGMENT(PAGE_CONS)
const NvU32 NVT_OVT_PIXEL_CLOCK_GRANULARITY = 1000; // Resulting Pixel Clock will be a multiple of this
@@ -60,20 +59,6 @@ static NvU32 nvFloorPow2_U32(NvU32 x)
return x & ~(x - 1);
}
CODE_SEGMENT(PAGE_DD_CODE)
static NvU32 computeGCD(NvU32 a, NvU32 b)
{
NvU32 temp;
while (b != 0)
{
temp = a % b;
if (temp == 0) return b;
a = b;
b = temp;
}
return a;
}
CODE_SEGMENT(PAGE_DD_CODE)
static NvU32 calculate_aspect_ratio(NVT_TIMING *pT)
{
@@ -292,4 +277,28 @@ NvBool NvTiming_IsTimingOVT(const NVT_TIMING *pTiming)
return NV_FALSE;
}
POP_SEGMENTS
CODE_SEGMENT(PAGE_DD_CODE)
NvU32 computeGCD(NvU32 a, NvU32 b)
{
NvU32 temp;
while (b != 0)
{
temp = a % b;
if (temp == 0) return b;
a = b;
b = temp;
}
return a;
}
CODE_SEGMENT(PAGE_DD_CODE)
NvU32 computeLCM(NvU32 a, NvU32 b)
{
if (a == 0 || b == 0)
{
return 0;
}
return (a / computeGCD(a, b)) * b;
}
POP_SEGMENTS

32
src/common/modeset/timing/nvt_util.c
View File

@@ -213,6 +213,34 @@ void patchChecksum(NvU8 *pBuf)
}
}
CODE_SEGMENT(PAGE_DD_CODE)
NvU32 NvTiming_CalculateVBlankTimeInUs(const NVT_TIMING *pT)
{
NvU32 activeLines, blankLines;
NvU32 blankPixels;
NvU32 pclk1khz = pT->pclk1khz;
if (pclk1khz == 0)
{
pclk1khz = RRx1kToPclk1khz(pT);
if (pclk1khz == 0)
{
return 0;
}
}
// Calculate HBlank pixels on the last active line
blankPixels = pT->HTotal - pT->HVisible;
// Calculate active and blank lines (handle interlaced mode)
activeLines = pT->interlaced ? pT->VVisible * 2 : pT->VVisible;
blankLines = (pT->interlaced == 0) ? (pT->VTotal - activeLines): (pT->VTotal * 2 + 1 - activeLines);
// Include HBlank time on the last active line together with all VBlank lines
blankPixels = blankPixels + (blankLines * pT->HTotal);
return (NvU32)((NvU64)blankPixels * 1000 / pclk1khz);
}
CODE_SEGMENT(PAGE_DD_CODE)
NVT_STATUS NvTiming_ComposeCustTimingString(NVT_TIMING *pT)
{
@@ -341,7 +369,7 @@ NvU32 NvTiming_IsTimingRelaxedEqual(const NVT_TIMING *pT1, const NVT_TIMING *pT2
}
CODE_SEGMENT(NONPAGE_DD_CODE)
NvU32 RRx1kToPclk (NVT_TIMING *pT)
NvU32 RRx1kToPclk (const NVT_TIMING *pT)
{
return (NvU32)axb_div_c_64(pT->HTotal * (pT->VTotal + ((pT->interlaced != 0) ? (pT->VTotal + 1) : 0)),
pT->etc.rrx1k,
@@ -349,7 +377,7 @@ NvU32 RRx1kToPclk (NVT_TIMING *pT)
}
CODE_SEGMENT(NONPAGE_DD_CODE)
NvU32 RRx1kToPclk1khz (NVT_TIMING *pT)
NvU32 RRx1kToPclk1khz (const NVT_TIMING *pT)
{
return (NvU32)axb_div_c_64((NvU32)pT->HTotal * (NvU32)(pT->VTotal + ((pT->interlaced != 0) ? (pT->VTotal + 1) : 0)),
pT->etc.rrx1k,

9
src/common/modeset/timing/nvtiming.h
View File

@@ -3103,6 +3103,7 @@ typedef struct tagNVT_ADAPTIVE_SYNC_SDP_CTRL
NvU32 srCoastingVTotal;
NvBool bFixedVTotal;
NvBool bRefreshRateDivider;
NvBool bDisableSourceSinkSync;
}NVT_ADAPTIVE_SYNC_SDP_CTRL;
//***********************************
@@ -5843,6 +5844,9 @@ NVT_STATUS NvTiming_CalcCVT_RB2(NvU32 width, NvU32 height, NvU32 rr, NvBool is10
NVT_STATUS NvTiming_CalcCVT_RB3(NvU32 width, NvU32 height, NvU32 rr, NvU32 deltaHBlank, NvU32 vBlankMicroSec, NvBool isAltMiniVblankTiming, NvBool isEarlyVSync, NVT_TIMING *pT);
NvBool NvTiming_IsTimingCVTRB(const NVT_TIMING *pTiming);
NvU32 computeGCD(NvU32 a, NvU32 b);
NvU32 computeLCM(NvU32 a, NvU32 b);
// OVT timing calculation
NVT_STATUS NvTiming_CalcOVT(NvU32 width, NvU32 height, NvU32 rr, NVT_TIMING *pT);
NvBool NvTiming_IsTimingOVT(const NVT_TIMING *pTiming);
@@ -5900,9 +5904,10 @@ NvU32 a_div_b(NvU32 a, NvU32 b);
NvU32 calculateCRC32(NvU8* pBuf, NvU32 bufsize);
void patchChecksum(NvU8* pBuf);
NvBool isChecksumValid(NvU8* pBuf);
NvU32 RRx1kToPclk (NVT_TIMING *pT);
NvU32 RRx1kToPclk1khz (NVT_TIMING *pT);
NvU32 RRx1kToPclk (const NVT_TIMING *pT);
NvU32 RRx1kToPclk1khz (const NVT_TIMING *pT);
NvU32 NvTiming_CalculateVBlankTimeInUs(const NVT_TIMING *pT);
NVT_STATUS NvTiming_ComposeCustTimingString(NVT_TIMING *pT);
// Infoframe/SDP composer

6
src/common/nvlink/inband/interface/nvlink_inband_msg.h
View File

@@ -84,6 +84,7 @@ typedef struct
#define NVLINK_INBAND_GPU_PROBE_CAPS_ATS_SUPPORT NVBIT(3)
#define NVLINK_INBAND_GPU_PROBE_CAPS_LINK_RETRAIN_SUPPORT NVBIT(4)
#define NVLINK_INBAND_GPU_PROBE_CAPS_HEALTH_SUMMARY NVBIT(6)
#define NVLINK_INBAND_GPU_PROBE_CAPS_GPU_PROBE_REQUEST_ACTION NVBIT(7)
#define NVLINK_INBAND_GPU_PROBE_CAPS_MC_RETRY NVBIT(8)
/* Add more caps as need in the future */
@@ -199,8 +200,9 @@ typedef struct
NvU32 cliqueId; /* Fabric Clique Id*/
NvU32 fabricHealthMask; /* Mask containing bits indicating various fabric health parameters */
NvU32 epoch; /* Epoch to be matched by RM when allowing P2P between GPUs */
NvU8 action; /*! < action request from FM */
NvU8 reserved[27]; /* For future use. Must be initialized to zero */
NvU8 action; /* Action request from FM */
NvU64 linkMask; /* Enabled link mask */
NvU8 reserved[19]; /* For future use. Must be initialized to zero */
} nvlink_inband_gpu_probe_update_req_t;
typedef struct

4
src/common/nvswitch/kernel/inc/error_nvswitch.h
View File

@@ -137,7 +137,7 @@ typedef struct
NVSWITCH_ERROR_SEVERITY_FATAL, \
_errresolved, \
NULL, 0, \
__LINE__, NULL)
__LINE__, "")
#define NVSWITCH_LOG_FATAL_DATA(_device, _errsrc, _errtype, _instance, _subinstance, _errresolved, _errdata, ...) \
nvswitch_record_error( \
@@ -161,7 +161,7 @@ typedef struct
NVSWITCH_ERROR_SEVERITY_NONFATAL, \
_errresolved, \
NULL, 0, \
__LINE__, NULL)
__LINE__, "")
#define NVSWITCH_LOG_NONFATAL_DATA(_device, _errsrc, _errtype, _instance, _subinstance, _errresolved, _errdata, ...) \
nvswitch_record_error( \

1
src/common/nvswitch/kernel/inc/ls10/minion_nvlink_defines_public_ls10.h
View File

@@ -44,6 +44,7 @@ typedef enum _MINION_STATUS
{
MINION_OK = 0,
MINION_ALARM_BUSY = 80,
MINION_INBAND_BUFFER_BUSY = 89,
} MINION_STATUS;
#define LINKSTATUS_RESET 0x0

11
src/common/nvswitch/kernel/ls10/intr_ls10.c
View File

@@ -61,6 +61,7 @@
#include "nvswitch/ls10/dev_nxbar_tileout_ip.h"
#include "nvswitch/ls10/dev_ctrl_ip_addendum.h"
#include "ls10/minion_nvlink_defines_public_ls10.h"
static void _nvswitch_create_deferred_link_errors_task_ls10(nvswitch_device *device, NvU32 nvlipt_instance, NvU32 link);
@@ -6512,7 +6513,7 @@ _nvswitch_emit_link_errors_minion_nonfatal_ls10
return;
}
// read in the enaled minion interrupts on this minion
// read in the enabled minion interrupts on this minion
regData = NVSWITCH_MINION_RD32_LS10(device, nvlipt_instance, _MINION, _MINION_INTR_STALL_EN);
// Grab the cached interrupt data
@@ -9059,7 +9060,7 @@ nvswitch_service_minion_link_ls10
// get all possible interrupting links associated with this minion
report.raw_pending = DRF_VAL(_MINION, _MINION_INTR, _LINK, minionIntr);
// read in the enaled minion interrupts on this minion
// read in the enabled minion interrupts on this minion
reg = NVSWITCH_MINION_RD32_LS10(device, instance, _MINION, _MINION_INTR_STALL_EN);
// get the links with enabled interrupts on this minion
@@ -9127,6 +9128,12 @@ nvswitch_service_minion_link_ls10
__FUNCTION__, instance, link);
break;
case NV_MINION_NVLINK_LINK_INTR_CODE_DLREQ:
if (DRF_VAL(_MINION, _NVLINK_LINK_INTR, _SUBCODE, linkIntr) == MINION_INBAND_BUFFER_BUSY)
{
// Skip deferred processing for intermediate status that are non-errors
break;
}
// Deliberate fallthrough
case NV_MINION_NVLINK_LINK_INTR_CODE_PMDISABLED:
case NV_MINION_NVLINK_LINK_INTR_CODE_TLREQ:
chip_device->deferredLinkErrors[link].data.nonFatalIntrMask.minionLinkIntr =

18
src/common/nvswitch/kernel/ls10/minion_ls10.c
View File

@@ -175,6 +175,9 @@ nvswitch_minion_send_command_ls10
NvU32 ingressEccRegVal = 0, egressEccRegVal = 0;
NVSWITCH_TIMEOUT timeout;
NvBool keepPolling;
NVSWITCH_RAW_ERROR_LOG_TYPE minion_error = {0, { 0 }};
minion_error.data[0] = command;
localLinkNumber = linkNumber % NVSWITCH_LINKS_PER_MINION_LS10;
@@ -195,6 +198,12 @@ nvswitch_minion_send_command_ls10
"%s: MINION %d is in fault state. NV_MINION_NVLINK_DL_CMD(%d) = %08x\n",
__FUNCTION__, NVSWITCH_GET_LINK_ENG_INST(device, linkNumber, MINION),
linkNumber, data);
minion_error.data[1] = data;
NVSWITCH_REPORT_NONFATAL_LINK(device, linkNumber, _HW_MINION_DLCMD_FAULT,
"DLCMD FAULT: cmd=0x%x DL_CMD=0x%x",
minion_error.data[0],
minion_error.data[1]);
return -NVL_ERR_GENERIC;
}
@@ -263,6 +272,8 @@ nvswitch_minion_send_command_ls10
// The command has completed, success?
if (FLD_TEST_DRF_NUM(_MINION, _NVLINK_DL_CMD, _FAULT, 1, data))
{
minion_error.data[1] = data;
NVSWITCH_PRINT(device, ERROR,
"%s: NVLink MINION command faulted!"
" NV_MINION_NVLINK_DL_CMD(%d) = 0x%08x\n",
@@ -292,6 +303,7 @@ nvswitch_minion_send_command_ls10
data = FLD_SET_DRF_NUM(_MINION, _NVLINK_DL_CMD, _FAULT, 1, 0x0);
NVSWITCH_MINION_LINK_WR32_LS10(device, linkNumber, _MINION, _NVLINK_DL_CMD(localLinkNumber), data);
return -NVL_ERR_INVALID_STATE;
}
else
@@ -313,6 +325,12 @@ nvswitch_minion_send_command_ls10
"%s: Timeout waiting for NVLink MINION command to complete!"
" NV_MINION_NVLINK_DL_CMD(%d) = 0x%08x\n",
__FUNCTION__, linkNumber, data);
minion_error.data[1] = data;
NVSWITCH_REPORT_NONFATAL_LINK(device, linkNumber, _HW_MINION_DLCMD_TIMEOUT,
"DLCMD TIMEOUT: cmd=0x%x DL_CMD=0x%0x",
minion_error.data[0], minion_error.data[1]);
return -NVL_ERR_INVALID_STATE;
}

9
src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208fclk.h → src/common/sdk/nvidia/inc/class/cl008f.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2005-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -21,13 +21,12 @@
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl208f/ctrl208fclk.finn
// Source file: class/cl008f.finn
//
#define KERNEL_WATCHDOG 0x008FU

73
src/common/sdk/nvidia/inc/class/cl00de.h
View File

@@ -132,6 +132,7 @@ enum {
typedef struct RUSD_CLK_PUBLIC_DOMAIN_INFO {
NvU32 targetClkMHz;
NvU32 actualClkKHz;
} RUSD_CLK_PUBLIC_DOMAIN_INFO;
typedef struct RUSD_CLK_PUBLIC_DOMAIN_INFOS {
@@ -352,6 +353,73 @@ typedef struct RUSD_GR_INFO
NvBool bCtxswLoggingEnabled;
} RUSD_GR_INFO;
#define RUSD_PROC_UTIL_SAMPLE_COUNT 5
//
// RUSD_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE is NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE
// without subProcessName and pOsPidInfo
//
typedef struct {
/*!
* Percentage during the sample that the engine remains busy. This
* is in units of pct*100.
*/
NvU32 util;
/*!
* Scaling factor to convert utilization from full GPU to per vGPU.
*/
NvU32 vgpuScale;
/*!
* Process ID of the process that was active on the engine when the
* sample was taken. If no process is active then NV2080_GPUMON_PID_INVALID
* will be returned.
*/
NvU32 procId;
/*!
* Process ID of the process in the vGPU VM that was active on the engine when
* the sample was taken. If no process is active then NV2080_GPUMON_PID_INVALID
* will be returned.
*/
NvU32 subProcessID;
} RUSD_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE;
typedef struct {
NvU64 timeStamp; // Original is NV2080_CTRL_GPUMON_SAMPLE
/*!
* FB bandwidth utilization sample.
*/
RUSD_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE fb;
/*!
* GR utilization sample.
*/
RUSD_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE gr;
/*!
* NV ENCODER utilization sample.
*/
RUSD_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE nvenc;
/*!
* NV DECODER utilization sample.
*/
RUSD_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE nvdec;
/*!
* NV JPEG utilization sample.
*/
RUSD_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE nvjpg;
/*!
* NV OFA utilization sample.
*/
RUSD_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE nvofa;
} RUSD_CTRL_PERF_GPUMON_PERFMON_UTIL_SAMPLE;
typedef struct {
RUSD_CTRL_PERF_GPUMON_PERFMON_UTIL_SAMPLE samples[RUSD_PROC_UTIL_SAMPLE_COUNT];
} RUSD_PROC_UTIL_INFO;
typedef struct {
volatile NvU64 lastModifiedTimestamp;
RUSD_PROC_UTIL_INFO info;
} RUSD_PROC_UTIL;
typedef struct NV00DE_SHARED_DATA {
NV_DECLARE_ALIGNED(RUSD_BAR1_MEMORY_INFO bar1MemoryInfo, 8);
@@ -411,6 +479,10 @@ typedef struct NV00DE_SHARED_DATA {
// POLL_FAN
NV_DECLARE_ALIGNED(RUSD_FAN_COOLER_STATUS fanCoolerStatus, 8);
// POLL_PROC_UTIL
NV_DECLARE_ALIGNED(RUSD_PROC_UTIL procUtil, 8);
} NV00DE_SHARED_DATA;
//
@@ -424,6 +496,7 @@ typedef struct NV00DE_SHARED_DATA {
#define NV00DE_RUSD_POLL_THERMAL 0x10
#define NV00DE_RUSD_POLL_PCI 0x20
#define NV00DE_RUSD_POLL_FAN 0x40
#define NV00DE_RUSD_POLL_PROC_UTIL 0x80
typedef struct NV00DE_ALLOC_PARAMETERS {
NvU64 polledDataMask; // Bitmask of data to request polling at alloc time, 0 if not needed

75
src/common/sdk/nvidia/inc/class/cl00f3.h
View File

@@ -1,75 +0,0 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2018-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: class/cl00f3.finn
//
/*
* Class definition for creating a memory descriptor from a FLA range in RmAllocMemory.
* No memory is allocated, only a memory descriptor and memory object is created
* for later use in other calls. These classes are used by clients who tries to
* import the memory exported by other GPU(s)/FAM/process. The range, size and
* other parameters are passed as Nv01MemoryFla structure.
*/
#define NV01_MEMORY_FLA (0xf3U) /* finn: Evaluated from "NV_FLA_MEMORY_ALLOCATION_PARAMS_MESSAGE_ID" */
/*
* Structure of NV_FLA_MEMORY_ALLOCATION_PARAMS
*
*
*/
#define NV_FLA_MEMORY_ALLOCATION_PARAMS_MESSAGE_ID (0x00f3U)
typedef struct NV_FLA_MEMORY_ALLOCATION_PARAMS {
NvU32 type; /* FBMEM: NVOS32_TYPE_* */
NvU32 flags; /* FBMEM: NVOS32_ALLOC_FLAGS_* */
NvU32 attr; /* FBMEM: NVOS32_ATTR_* */
NvU32 attr2; /* FBMEM: NVOS32_ATTR2_* */
NV_DECLARE_ALIGNED(NvU64 base, 8); /* base of FLA range */
NV_DECLARE_ALIGNED(NvU64 align, 8); /* alignment for FLA range*/
NV_DECLARE_ALIGNED(NvU64 limit, 8);
//
// For Direct connected systems, clients need to program this hSubDevice with
// the exporting GPU, for RM to route the traffic to the destination GPU
// Clients need not program this for NvSwitch connected systems
//
NvHandle hExportSubdevice; /* hSubdevice of the exporting GPU */
//
// Instead of base and limit, clients can also pass the FLA handle (or hExportHandle)
// being exported from destination side to import on the access side
//
NvHandle hExportHandle; /* FLA handle being exported or Export handle */
// The RM client used to export memory
NvHandle hExportClient;
NvU32 flagsOs02;
} NV_FLA_MEMORY_ALLOCATION_PARAMS;

5
src/common/sdk/nvidia/inc/class/cl00fd.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2010-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2010-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -71,6 +71,7 @@
*/
#define NV_MEMORY_MULTICAST_FABRIC_PAGE_SIZE_512M 0x20000000
#define NV_MEMORY_MULTICAST_FABRIC_PAGE_SIZE_256G 0x1000000000000
/*
* This flag must be passed if the object is created using export packet. Note
@@ -90,7 +91,7 @@ typedef struct NV00FD_ALLOCATION_PARAMETERS {
NV_DECLARE_ALIGNED(NvU64 alignment, 8);
NV_DECLARE_ALIGNED(NvU64 allocSize, 8);
NvU32 pageSize;
NV_DECLARE_ALIGNED(NvU64 pageSize, 8);
NvU32 allocFlags;
NvU32 numGpus;
NV_DECLARE_ALIGNED(NvP64 pOsEvent, 8);

3
src/common/sdk/nvidia/inc/class/cl2080_notification.h
View File

@@ -236,7 +236,8 @@ extern "C" {
#define NV2080_NOTIFIERS_CTXSW_UCODE_ERROR (195)
#define NV2080_NOTIFIERS_USE_GC6_REDUCED_THRESHOLD (196)
#define NV2080_NOTIFIERS_GPU_RC_RESET (197)
#define NV2080_NOTIFIERS_MAXCOUNT (198)
#define NV2080_NOTIFIERS_RESERVED_198 (198) // Unused
#define NV2080_NOTIFIERS_MAXCOUNT (199)
// Indexed GR notifier reference
#define NV2080_NOTIFIERS_GR(x) ((x == 0) ? (NV2080_NOTIFIERS_GR0) : (NV2080_NOTIFIERS_GR1 + (x - 1)))

10
src/common/sdk/nvidia/inc/class/cl503b.h
View File

@@ -51,6 +51,10 @@ typedef struct NV503B_BAR1_P2P_DMA_INFO {
NV_DECLARE_ALIGNED(NvU64 dma_size, 8);
} NV503B_BAR1_P2P_DMA_INFO;
typedef struct NV503B_FABRIC_P2P_DMA_INFO {
NV_DECLARE_ALIGNED(NvU64 gpa, 8);
} NV503B_FABRIC_P2P_DMA_INFO;
/* NvRmAlloc parameters */
#define NV503B_ALLOC_PARAMETERS_MESSAGE_ID (0x503bU)
@@ -70,6 +74,8 @@ typedef struct NV503B_ALLOC_PARAMETERS {
NvU32 flags; /* Flag to indicate types/attib of p2p */
NvU32 subDeviceEgmPeerIdMask; /* Bit mask of EGM peer ID of SubDevice */
NvU32 peerSubDeviceEgmPeerIdMask; /* Bit mask of EGM peer ID for PeerSubDevice */
NV_DECLARE_ALIGNED(NV503B_BAR1_P2P_DMA_INFO l2pBar1P2PDmaInfo, 8); /* Bar1 DMA info from local GPU to peer GPU */
NV_DECLARE_ALIGNED(NV503B_BAR1_P2P_DMA_INFO p2lBar1P2PDmaInfo, 8); /* Bar1 DMA info from peer GPU to local GPU */
NV_DECLARE_ALIGNED(NV503B_BAR1_P2P_DMA_INFO l2pBar1P2PDmaInfo, 8); /* Bar1 DMA info from local GPU to peer GPU */
NV_DECLARE_ALIGNED(NV503B_BAR1_P2P_DMA_INFO p2lBar1P2PDmaInfo, 8); /* Bar1 DMA info from peer GPU to local GPU */
NV_DECLARE_ALIGNED(NV503B_FABRIC_P2P_DMA_INFO l2pFabricP2PInfo, 8); /* NVLink fabric base address of the local GPU. Used in switch systems */
NV_DECLARE_ALIGNED(NV503B_FABRIC_P2P_DMA_INFO p2lFabricP2PInfo, 8); /* NVLink fabric base address of the remote GPU. Used in switch systems */
} NV503B_ALLOC_PARAMETERS;

37
src/common/sdk/nvidia/inc/class/cl907dswspare.h
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@@ -1,37 +0,0 @@
/*
* Copyright (c) 2010-2014, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _cl907d_sw_spare_h_
#define _cl907d_sw_spare_h_
/* This file is *not* auto-generated. */
#define NV907D_HEAD_SET_SW_SPARE_A_CODE_VPLL_REF 1:0
#define NV907D_HEAD_SET_SW_SPARE_A_CODE_VPLL_REF_NO_PREF (0x00000000)
#define NV907D_HEAD_SET_SW_SPARE_A_CODE_VPLL_REF_GSYNC (0x00000001)
#define NV907D_PIOR_SET_SW_SPARE_A_CODE_FOR_LOCK_SIGNAL_PROPAGATION_ONLY 1:0
#define NV907D_PIOR_SET_SW_SPARE_A_CODE_FOR_LOCK_SIGNAL_PROPAGATION_ONLY_FALSE (0x00000000)
#define NV907D_PIOR_SET_SW_SPARE_A_CODE_FOR_LOCK_SIGNAL_PROPAGATION_ONLY_TRUE (0x00000001)
#endif // _cl907d_sw_spare_h_

4
src/common/sdk/nvidia/inc/class/cl90cdtrace.h
View File

@@ -31,7 +31,9 @@ typedef struct NV_RATS_GSP_TRACE_RECORD_V1
{
NvU16 seqNo;
NvU16 gspSeqNo;
NvU32 threadId;
NvU8 threadId;
NvU8 partitionId;
NvU16 reserved0;
NvU64 info;
NvU64 timeStamp;
NvU64 recordType;

37
src/common/sdk/nvidia/inc/class/cl917cswspare.h
View File

@@ -1,37 +0,0 @@
/*
* Copyright (c) 2010-2014, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _cl917c_sw_spare_h_
#define _cl917c_sw_spare_h_
/* This file is *not* auto-generated. */
/* NV917C_SET_SPARE_PRE_UPDATE_TRAP is an alias of NV917C_SET_SPARE_NOOP(0) */
#define NV917C_SET_SPARE_PRE_UPDATE_TRAP (0x000003C0)
#define NV917C_SET_SPARE_PRE_UPDATE_TRAP_UNUSED 31:0
/* NV917C_SET_SPARE_POST_UPDATE_TRAP is an alias of NV917C_SET_SPARE_NOOP(1) */
#define NV917C_SET_SPARE_POST_UPDATE_TRAP (0x000003C4)
#define NV917C_SET_SPARE_POST_UPDATE_TRAP_UNUSED 31:0
#endif /* _cl917c_sw_spare_h_ */

45
src/common/sdk/nvidia/inc/class/cl917dcrcnotif.h
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@@ -1,45 +0,0 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2010 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __cl917dcrcnotif_h__
#define __cl917dcrcnotif_h__
/* This file is autogenerated. Do not edit */
#define NV917D_NOTIFIER_CRC_1_STATUS_0 0x00000000
#define NV917D_NOTIFIER_CRC_1_STATUS_0_DONE 0:0
#define NV917D_NOTIFIER_CRC_1_STATUS_0_DONE_FALSE 0x00000000
#define NV917D_NOTIFIER_CRC_1_STATUS_0_DONE_TRUE 0x00000001
#define NV917D_NOTIFIER_CRC_1_STATUS_0_COMPOSITOR_OVERFLOW 3:3
#define NV917D_NOTIFIER_CRC_1_STATUS_0_COMPOSITOR_OVERFLOW_FALSE 0x00000000
#define NV917D_NOTIFIER_CRC_1_STATUS_0_COMPOSITOR_OVERFLOW_TRUE 0x00000001
#define NV917D_NOTIFIER_CRC_1_STATUS_0_PRIMARY_OUTPUT_OVERFLOW 4:4
#define NV917D_NOTIFIER_CRC_1_STATUS_0_PRIMARY_OUTPUT_OVERFLOW_FALSE 0x00000000
#define NV917D_NOTIFIER_CRC_1_STATUS_0_PRIMARY_OUTPUT_OVERFLOW_TRUE 0x00000001
#define NV917D_NOTIFIER_CRC_1_STATUS_0_COUNT 31:24
#define NV917D_NOTIFIER_CRC_1_CRC_ENTRY0_3 0x00000003
#define NV917D_NOTIFIER_CRC_1_CRC_ENTRY0_3_COMPOSITOR_CRC 31:0
#define NV917D_NOTIFIER_CRC_1_CRC_ENTRY0_4 0x00000004
#define NV917D_NOTIFIER_CRC_1_CRC_ENTRY0_4_PRIMARY_OUTPUT_CRC 31:0
#define NV917D_NOTIFIER_CRC_1_CRC_ENTRY1_8 0x00000008
#endif // __cl917dcrcnotif_h__

41
src/common/sdk/nvidia/inc/class/cl9870.h
View File

@@ -1,41 +0,0 @@
/*
* Copyright (c) 1993-2022, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: class/cl9870.finn
//
#define NV9870_DISPLAY (0x9870U) /* finn: Evaluated from "NV9870_ALLOCATION_PARAMETERS_MESSAGE_ID" */
#define NV9870_ALLOCATION_PARAMETERS_MESSAGE_ID (0x9870U)
typedef struct NV9870_ALLOCATION_PARAMETERS {
NvU32 numHeads; // Number of HEADs in this chip/display
NvU32 numDacs; // Number of DACs in this chip/display
NvU32 numSors; // Number of SORs in this chip/display
NvU32 numPiors; // Number of PIORs in this chip/display
} NV9870_ALLOCATION_PARAMETERS;

21
src/common/sdk/nvidia/inc/class/cla084_notification.h
View File

@@ -34,16 +34,17 @@ extern "C" {
// These event values are only for Test purpose.
//
/* event values */
#define NVA084_NOTIFIERS_EVENT_VGPU_PLUGIN_TASK_BOOTLOADED (0)
#define NVA084_NOTIFIERS_EVENT_VGPU_PLUGIN_TASK_UNLOADED (1)
#define NVA084_NOTIFIERS_EVENT_VGPU_PLUGIN_TASK_CRASHED (2)
#define NVA084_NOTIFIERS_EVENT_GUEST_DRIVER_LOADED (3)
#define NVA084_NOTIFIERS_EVENT_GUEST_DRIVER_UNLOADED (4)
#define NVA084_NOTIFIERS_EVENT_PRINT_ERROR_MESSAGE (5)
#define NVA084_NOTIFIERS_EVENT_GUEST_LICENSE_STATE_CHANGED (6)
#define NVA084_NOTIFIERS_EVENT_UPDATE_GUEST_OS_TYPE (7)
#define NVA084_NOTIFIERS_EVENT_INIT_GR_ENGINE (8)
#define NVA084_NOTIFIERS_MAXCOUNT (9)
#define NVA084_NOTIFIERS_EVENT_VGPU_PLUGIN_TASK_BOOTLOADED (0)
#define NVA084_NOTIFIERS_EVENT_VGPU_PLUGIN_TASK_UNLOADED (1)
#define NVA084_NOTIFIERS_EVENT_VGPU_PLUGIN_TASK_CRASHED (2)
#define NVA084_NOTIFIERS_EVENT_GUEST_DRIVER_LOADED (3)
#define NVA084_NOTIFIERS_EVENT_GUEST_DRIVER_UNLOADED (4)
#define NVA084_NOTIFIERS_EVENT_PRINT_ERROR_MESSAGE (5)
#define NVA084_NOTIFIERS_EVENT_GUEST_LICENSE_STATE_CHANGED (6)
#define NVA084_NOTIFIERS_EVENT_UPDATE_GUEST_OS_TYPE (7)
#define NVA084_NOTIFIERS_EVENT_PRINT_GUEST_RPC_TRACE_LOG_MESSAGE (8)
#define NVA084_NOTIFIERS_EVENT_INIT_GR_ENGINE (9)
#define NVA084_NOTIFIERS_MAXCOUNT (10)
#define NVA084_NOTIFICATION_STATUS_IN_PROGRESS (0x8000)
#define NVA084_NOTIFICATION_STATUS_BAD_ARGUMENT (0x4000)

2050
src/common/sdk/nvidia/inc/class/clb097tex.h
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File diff suppressed because it is too large Load Diff

399
src/common/sdk/nvidia/inc/class/clc873.h Normal file
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@@ -0,0 +1,399 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _clc873_h_
#define _clc873_h_
#ifdef __cplusplus
extern "C" {
#endif
#define NVC873_DISP_CAPABILITIES 0xC873
typedef volatile struct _clc873_tag0 {
NvU32 dispCapabilities[0x400];
} _NvC873DispCapabilities,NvC873DispCapabilities_Map ;
#define NVC873_SYS_CAP 0x0 /* RW-4R */
#define NVC873_SYS_CAP_HEAD0_EXISTS 0:0 /* RWIVF */
#define NVC873_SYS_CAP_HEAD0_EXISTS_NO 0x00000000 /* RW--V */
#define NVC873_SYS_CAP_HEAD0_EXISTS_YES 0x00000001 /* RW--V */
#define NVC873_SYS_CAP_HEAD1_EXISTS 1:1 /* RWIVF */
#define NVC873_SYS_CAP_HEAD1_EXISTS_NO 0x00000000 /* RW--V */
#define NVC873_SYS_CAP_HEAD1_EXISTS_YES 0x00000001 /* RW--V */
#define NVC873_SYS_CAP_HEAD2_EXISTS 2:2 /* RWIVF */
#define NVC873_SYS_CAP_HEAD2_EXISTS_NO 0x00000000 /* RW--V */
#define NVC873_SYS_CAP_HEAD2_EXISTS_YES 0x00000001 /* RW--V */
#define NVC873_SYS_CAP_HEAD3_EXISTS 3:3 /* RWIVF */
#define NVC873_SYS_CAP_HEAD3_EXISTS_NO 0x00000000 /* RW--V */
#define NVC873_SYS_CAP_HEAD3_EXISTS_YES 0x00000001 /* RW--V */
#define NVC873_SYS_CAP_HEAD4_EXISTS 4:4 /* RWIVF */
#define NVC873_SYS_CAP_HEAD4_EXISTS_NO 0x00000000 /* RW--V */
#define NVC873_SYS_CAP_HEAD4_EXISTS_YES 0x00000001 /* RW--V */
#define NVC873_SYS_CAP_HEAD5_EXISTS 5:5 /* RWIVF */
#define NVC873_SYS_CAP_HEAD5_EXISTS_NO 0x00000000 /* RW--V */
#define NVC873_SYS_CAP_HEAD5_EXISTS_YES 0x00000001 /* RW--V */
#define NVC873_SYS_CAP_HEAD6_EXISTS 6:6 /* RWIVF */
#define NVC873_SYS_CAP_HEAD6_EXISTS_NO 0x00000000 /* RW--V */
#define NVC873_SYS_CAP_HEAD6_EXISTS_YES 0x00000001 /* RW--V */
#define NVC873_SYS_CAP_HEAD7_EXISTS 7:7 /* RWIVF */
#define NVC873_SYS_CAP_HEAD7_EXISTS_NO 0x00000000 /* RW--V */
#define NVC873_SYS_CAP_HEAD7_EXISTS_YES 0x00000001 /* RW--V */
#define NVC873_SYS_CAP_HEAD_EXISTS(i) (0+(i)):(0+(i)) /* RWIVF */
#define NVC873_SYS_CAP_HEAD_EXISTS__SIZE_1 8 /* */
#define NVC873_SYS_CAP_HEAD_EXISTS_NO 0x00000000 /* RW--V */
#define NVC873_SYS_CAP_HEAD_EXISTS_YES 0x00000001 /* RW--V */
#define NVC873_SYS_CAP_SOR0_EXISTS 8:8 /* RWIVF */
#define NVC873_SYS_CAP_SOR0_EXISTS_NO 0x00000000 /* RW--V */
#define NVC873_SYS_CAP_SOR0_EXISTS_YES 0x00000001 /* RW--V */
#define NVC873_SYS_CAP_SOR1_EXISTS 9:9 /* RWIVF */
#define NVC873_SYS_CAP_SOR1_EXISTS_NO 0x00000000 /* RW--V */
#define NVC873_SYS_CAP_SOR1_EXISTS_YES 0x00000001 /* RW--V */
#define NVC873_SYS_CAP_SOR2_EXISTS 10:10 /* RWIVF */
#define NVC873_SYS_CAP_SOR2_EXISTS_NO 0x00000000 /* RW--V */
#define NVC873_SYS_CAP_SOR2_EXISTS_YES 0x00000001 /* RW--V */
#define NVC873_SYS_CAP_SOR3_EXISTS 11:11 /* RWIVF */
#define NVC873_SYS_CAP_SOR3_EXISTS_NO 0x00000000 /* RW--V */
#define NVC873_SYS_CAP_SOR3_EXISTS_YES 0x00000001 /* RW--V */
#define NVC873_SYS_CAP_SOR4_EXISTS 12:12 /* RWIVF */
#define NVC873_SYS_CAP_SOR4_EXISTS_NO 0x00000000 /* RW--V */
#define NVC873_SYS_CAP_SOR4_EXISTS_YES 0x00000001 /* RW--V */
#define NVC873_SYS_CAP_SOR5_EXISTS 13:13 /* RWIVF */
#define NVC873_SYS_CAP_SOR5_EXISTS_NO 0x00000000 /* RW--V */
#define NVC873_SYS_CAP_SOR5_EXISTS_YES 0x00000001 /* RW--V */
#define NVC873_SYS_CAP_SOR6_EXISTS 14:14 /* RWIVF */
#define NVC873_SYS_CAP_SOR6_EXISTS_NO 0x00000000 /* RW--V */
#define NVC873_SYS_CAP_SOR6_EXISTS_YES 0x00000001 /* RW--V */
#define NVC873_SYS_CAP_SOR7_EXISTS 15:15 /* RWIVF */
#define NVC873_SYS_CAP_SOR7_EXISTS_NO 0x00000000 /* RW--V */
#define NVC873_SYS_CAP_SOR7_EXISTS_YES 0x00000001 /* RW--V */
#define NVC873_SYS_CAP_SOR_EXISTS(i) (8+(i)):(8+(i)) /* RWIVF */
#define NVC873_SYS_CAP_SOR_EXISTS__SIZE_1 8 /* */
#define NVC873_SYS_CAP_SOR_EXISTS_NO 0x00000000 /* RW--V */
#define NVC873_SYS_CAP_SOR_EXISTS_YES 0x00000001 /* RW--V */
#define NVC873_SYS_CAP_DSI0_EXISTS 20:20 /* RWIVF */
#define NVC873_SYS_CAP_DSI0_EXISTS_NO 0x00000000 /* RW--V */
#define NVC873_SYS_CAP_DSI0_EXISTS_YES 0x00000001 /* RW--V */
#define NVC873_SYS_CAP_DSI1_EXISTS 21:21 /* RWIVF */
#define NVC873_SYS_CAP_DSI1_EXISTS_NO 0x00000000 /* RW--V */
#define NVC873_SYS_CAP_DSI1_EXISTS_YES 0x00000001 /* RW--V */
#define NVC873_SYS_CAP_DSI2_EXISTS 22:22 /* RWIVF */
#define NVC873_SYS_CAP_DSI2_EXISTS_NO 0x00000000 /* RW--V */
#define NVC873_SYS_CAP_DSI2_EXISTS_YES 0x00000001 /* RW--V */
#define NVC873_SYS_CAP_DSI3_EXISTS 23:23 /* RWIVF */
#define NVC873_SYS_CAP_DSI3_EXISTS_NO 0x00000000 /* RW--V */
#define NVC873_SYS_CAP_DSI3_EXISTS_YES 0x00000001 /* RW--V */
#define NVC873_SYS_CAP_DSI_EXISTS(i) (20+(i)):(20+(i)) /* RWIVF */
#define NVC873_SYS_CAP_DSI_EXISTS__SIZE_1 4 /* */
#define NVC873_SYS_CAP_DSI_EXISTS_NO 0x00000000 /* RW--V */
#define NVC873_SYS_CAP_DSI_EXISTS_YES 0x00000001 /* RW--V */
#define NVC873_IHUB_COMMON_CAPA 0x10 /* RW-4R */
#define NVC873_IHUB_COMMON_CAPA_MEMPOOL_ENTRIES 15:0 /* RWIUF */
#define NVC873_IHUB_COMMON_CAPA_MEMPOOL_ENTRY_WIDTH 17:16 /* RWIVF */
#define NVC873_IHUB_COMMON_CAPA_MEMPOOL_ENTRY_WIDTH_32B 0x00000000 /* RW--V */
#define NVC873_IHUB_COMMON_CAPA_MEMPOOL_ENTRY_WIDTH_64B 0x00000001 /* RW--V */
#define NVC873_IHUB_COMMON_CAPA_MEMPOOL_ENTRY_WIDTH_128B 0x00000002 /* RW--V */
#define NVC873_IHUB_COMMON_CAPA_MEMPOOL_ENTRY_WIDTH_256B 0x00000003 /* RW--V */
#define NVC873_IHUB_COMMON_CAPA_SUPPORT_ROTATION 18:18 /* RWIVF */
#define NVC873_IHUB_COMMON_CAPA_SUPPORT_ROTATION_FALSE 0x00000000 /* RW--V */
#define NVC873_IHUB_COMMON_CAPA_SUPPORT_ROTATION_TRUE 0x00000001 /* RW--V */
#define NVC873_IHUB_COMMON_CAPA_SUPPORT_PLANAR 19:19 /* RWIVF */
#define NVC873_IHUB_COMMON_CAPA_SUPPORT_PLANAR_FALSE 0x00000000 /* RW--V */
#define NVC873_IHUB_COMMON_CAPA_SUPPORT_PLANAR_TRUE 0x00000001 /* RW--V */
#define NVC873_IHUB_COMMON_CAPA_SUPPORT_VGA 20:20 /* RWIVF */
#define NVC873_IHUB_COMMON_CAPA_SUPPORT_VGA_FALSE 0x00000000 /* RW--V */
#define NVC873_IHUB_COMMON_CAPA_SUPPORT_VGA_TRUE 0x00000001 /* RW--V */
#define NVC873_IHUB_COMMON_CAPA_SUPPORT_MEMPOOL_COMPRESSION 21:21 /* RWIVF */
#define NVC873_IHUB_COMMON_CAPA_SUPPORT_MEMPOOL_COMPRESSION_FALSE 0x00000000 /* RW--V */
#define NVC873_IHUB_COMMON_CAPA_SUPPORT_MEMPOOL_COMPRESSION_TRUE 0x00000001 /* RW--V */
#define NVC873_IHUB_COMMON_CAPA_SUPPORT_MSCG 22:22 /* RWIVF */
#define NVC873_IHUB_COMMON_CAPA_SUPPORT_MSCG_FALSE 0x00000000 /* RW--V */
#define NVC873_IHUB_COMMON_CAPA_SUPPORT_MSCG_TRUE 0x00000001 /* RW--V */
#define NVC873_IHUB_COMMON_CAPA_SUPPORT_MCLK_SWITCH 23:23 /* RWIVF */
#define NVC873_IHUB_COMMON_CAPA_SUPPORT_MCLK_SWITCH_FALSE 0x00000000 /* RW--V */
#define NVC873_IHUB_COMMON_CAPA_SUPPORT_MCLK_SWITCH_TRUE 0x00000001 /* RW--V */
#define NVC873_IHUB_COMMON_CAPA_SUPPORT_LATENCY_EVENT 26:26 /* RWIVF */
#define NVC873_IHUB_COMMON_CAPA_SUPPORT_LATENCY_EVENT_FALSE 0x00000000 /* RW--V */
#define NVC873_IHUB_COMMON_CAPA_SUPPORT_LATENCY_EVENT_TRUE 0x00000001 /* RW--V */
#define NVC873_IHUB_COMMON_CAPA_REQUEST_SIZE_PER_LINE_NON_ROTATION 31:30 /* RWIVF */
#define NVC873_IHUB_COMMON_CAPA_REQUEST_SIZE_PER_LINE_NON_ROTATION_32B 0x00000000 /* RW--V */
#define NVC873_IHUB_COMMON_CAPA_REQUEST_SIZE_PER_LINE_NON_ROTATION_64B 0x00000001 /* RW--V */
#define NVC873_IHUB_COMMON_CAPA_REQUEST_SIZE_PER_LINE_NON_ROTATION_128B 0x00000002 /* RW--V */
#define NVC873_IHUB_COMMON_CAPA_REQUEST_SIZE_PER_LINE_NON_ROTATION_256B 0x00000003 /* RW--V */
#define NVC873_IHUB_COMMON_CAPC 0x18 /* RW-4R */
#define NVC873_IHUB_COMMON_CAPC_PITCH_REQUEST_SIZE 1:0 /* RWIVF */
#define NVC873_IHUB_COMMON_CAPC_PITCH_REQUEST_SIZE_32B 0x00000000 /* RW--V */
#define NVC873_IHUB_COMMON_CAPC_PITCH_REQUEST_SIZE_64B 0x00000001 /* RW--V */
#define NVC873_IHUB_COMMON_CAPC_PITCH_REQUEST_SIZE_128B 0x00000002 /* RW--V */
#define NVC873_IHUB_COMMON_CAPC_PITCH_REQUEST_SIZE_256B 0x00000003 /* RW--V */
#define NVC873_IHUB_COMMON_CAPC_MAX_LINES_BUFFERED 6:4 /* RWIVF */
#define NVC873_IHUB_COMMON_CAPC_MAX_LINES_BUFFERED_NONE 0x00000000 /* RW--V */
#define NVC873_IHUB_COMMON_CAPC_MAX_LINES_BUFFERED_TWO 0x00000001 /* RW--V */
#define NVC873_IHUB_COMMON_CAPC_MAX_LINES_BUFFERED_FOUR 0x00000002 /* RW--V */
#define NVC873_IHUB_COMMON_CAPC_MAX_LINES_BUFFERED_EIGHT 0x00000003 /* RW--V */
#define NVC873_IHUB_COMMON_CAPC_MAX_LINES_BUFFERED_SIXTEEN 0x00000004 /* RW--V */
#define NVC873_IHUB_COMMON_CAPC_SUPPORT_SEMI_PLANAR 11:11 /* RWIVF */
#define NVC873_IHUB_COMMON_CAPC_SUPPORT_SEMI_PLANAR_FALSE 0x00000000 /* RWI-V */
#define NVC873_IHUB_COMMON_CAPC_SUPPORT_SEMI_PLANAR_TRUE 0x00000001 /* RW--V */
#define NVC873_IHUB_COMMON_CAPC_SUPPORT_HOR_VER_FLIP 12:12 /* RWIVF */
#define NVC873_IHUB_COMMON_CAPC_SUPPORT_HOR_VER_FLIP_FALSE 0x00000000 /* RWI-V */
#define NVC873_IHUB_COMMON_CAPC_SUPPORT_HOR_VER_FLIP_TRUE 0x00000001 /* RW--V */
#define NVC873_POSTCOMP_HEAD_HDR_CAPA(i) (0x680+(i)*32) /* RW-4A */
#define NVC873_POSTCOMP_HEAD_HDR_CAPA__SIZE_1 8 /* */
#define NVC873_POSTCOMP_HEAD_HDR_CAPA_FULL_WIDTH 4:0 /* RWIVF */
#define NVC873_POSTCOMP_HEAD_HDR_CAPA_UNIT_WIDTH 9:5 /* RWIVF */
#define NVC873_POSTCOMP_HEAD_HDR_CAPA_OCSC0_PRESENT 16:16 /* RWIVF */
#define NVC873_POSTCOMP_HEAD_HDR_CAPA_OCSC0_PRESENT_TRUE 0x00000001 /* RW--V */
#define NVC873_POSTCOMP_HEAD_HDR_CAPA_OCSC0_PRESENT_FALSE 0x00000000 /* RW--V */
#define NVC873_POSTCOMP_HEAD_HDR_CAPA_OCSC1_PRESENT 17:17 /* RWIVF */
#define NVC873_POSTCOMP_HEAD_HDR_CAPA_OCSC1_PRESENT_TRUE 0x00000001 /* RW--V */
#define NVC873_POSTCOMP_HEAD_HDR_CAPA_OCSC1_PRESENT_FALSE 0x00000000 /* RW--V */
#define NVC873_POSTCOMP_HEAD_HDR_CAPA_SCLR_PRESENT 18:18 /* RWIVF */
#define NVC873_POSTCOMP_HEAD_HDR_CAPA_SCLR_PRESENT_TRUE 0x00000001 /* RW--V */
#define NVC873_POSTCOMP_HEAD_HDR_CAPA_SCLR_PRESENT_FALSE 0x00000000 /* RW--V */
#define NVC873_POSTCOMP_HEAD_HDR_CAPA_HCLPF_PRESENT 19:19 /* RWIVF */
#define NVC873_POSTCOMP_HEAD_HDR_CAPA_HCLPF_PRESENT_TRUE 0x00000001 /* RW--V */
#define NVC873_POSTCOMP_HEAD_HDR_CAPA_HCLPF_PRESENT_FALSE 0x00000000 /* RW--V */
#define NVC873_POSTCOMP_HEAD_HDR_CAPA_DTH_PRESENT 20:20 /* RWIVF */
#define NVC873_POSTCOMP_HEAD_HDR_CAPA_DTH_PRESENT_TRUE 0x00000001 /* RW--V */
#define NVC873_POSTCOMP_HEAD_HDR_CAPA_DTH_PRESENT_FALSE 0x00000000 /* RW--V */
#define NVC873_POSTCOMP_HEAD_HDR_CAPA_OSCAN_PRESENT 21:21 /* RWIVF */
#define NVC873_POSTCOMP_HEAD_HDR_CAPA_OSCAN_PRESENT_TRUE 0x00000001 /* RW--V */
#define NVC873_POSTCOMP_HEAD_HDR_CAPA_OSCAN_PRESENT_FALSE 0x00000000 /* RW--V */
#define NVC873_POSTCOMP_HEAD_HDR_CAPA_DSC_PRESENT 22:22 /* RWIVF */
#define NVC873_POSTCOMP_HEAD_HDR_CAPA_DSC_PRESENT_TRUE 0x00000001 /* RW--V */
#define NVC873_POSTCOMP_HEAD_HDR_CAPA_DSC_PRESENT_FALSE 0x00000000 /* RW--V */
#define NVC873_POSTCOMP_HEAD_HDR_CAPA_VFILTER_PRESENT 23:23 /* RWIVF */
#define NVC873_POSTCOMP_HEAD_HDR_CAPA_VFILTER_PRESENT_TRUE 0x00000001 /* RW--V */
#define NVC873_POSTCOMP_HEAD_HDR_CAPA_VFILTER_PRESENT_FALSE 0x00000000 /* RW--V */
#define NVC873_POSTCOMP_HEAD_HDR_CAPA_RCRC_PRESENT 24:24 /* RWIVF */
#define NVC873_POSTCOMP_HEAD_HDR_CAPA_RCRC_PRESENT_TRUE 0x00000001 /* RW--V */
#define NVC873_POSTCOMP_HEAD_HDR_CAPA_RCRC_PRESENT_FALSE 0x00000000 /* RW--V */
#define NVC873_POSTCOMP_HEAD_HDR_CAPB(i) (0x684+(i)*32) /* RW-4A */
#define NVC873_POSTCOMP_HEAD_HDR_CAPB__SIZE_1 8 /* */
#define NVC873_POSTCOMP_HEAD_HDR_CAPB_VGA 0:0 /* RWIVF */
#define NVC873_POSTCOMP_HEAD_HDR_CAPB_VGA_TRUE 0x00000001 /* RW--V */
#define NVC873_POSTCOMP_HEAD_HDR_CAPB_VGA_FALSE 0x00000000 /* RW--V */
#define NVC873_POSTCOMP_HEAD_HDR_CAPB_OLUT_LOGSZ 9:6 /* RWIVF */
#define NVC873_POSTCOMP_HEAD_HDR_CAPB_OLUT_LOGNR 12:10 /* RWIVF */
#define NVC873_POSTCOMP_HEAD_HDR_CAPB_OLUT_SFCLOAD 14:14 /* RWIVF */
#define NVC873_POSTCOMP_HEAD_HDR_CAPB_OLUT_SFCLOAD_TRUE 0x00000001 /* RW--V */
#define NVC873_POSTCOMP_HEAD_HDR_CAPB_OLUT_SFCLOAD_FALSE 0x00000000 /* RW--V */
#define NVC873_POSTCOMP_HEAD_HDR_CAPB_OLUT_DIRECT 15:15 /* RWIVF */
#define NVC873_POSTCOMP_HEAD_HDR_CAPB_OLUT_DIRECT_TRUE 0x00000001 /* RW--V */
#define NVC873_POSTCOMP_HEAD_HDR_CAPB_OLUT_DIRECT_FALSE 0x00000000 /* RW--V */
#define NVC873_POSTCOMP_HEAD_HDR_CAPC(i) (0x688+(i)*32) /* RW-4A */
#define NVC873_POSTCOMP_HEAD_HDR_CAPC__SIZE_1 8 /* */
#define NVC873_POSTCOMP_HEAD_HDR_CAPC_OCSC0_PRECISION 4:0 /* RWIVF */
#define NVC873_POSTCOMP_HEAD_HDR_CAPC_OCSC0_UNITY_CLAMP 5:5 /* RWIVF */
#define NVC873_POSTCOMP_HEAD_HDR_CAPC_OCSC0_UNITY_CLAMP_TRUE 0x00000001 /* RW--V */
#define NVC873_POSTCOMP_HEAD_HDR_CAPC_OCSC0_UNITY_CLAMP_FALSE 0x00000000 /* RW--V */
#define NVC873_POSTCOMP_HEAD_HDR_CAPC_OCSC1_PRECISION 12:8 /* RWIVF */
#define NVC873_POSTCOMP_HEAD_HDR_CAPC_OCSC1_UNITY_CLAMP 13:13 /* RWIVF */
#define NVC873_POSTCOMP_HEAD_HDR_CAPC_OCSC1_UNITY_CLAMP_TRUE 0x00000001 /* RW--V */
#define NVC873_POSTCOMP_HEAD_HDR_CAPC_OCSC1_UNITY_CLAMP_FALSE 0x00000000 /* RW--V */
#define NVC873_POSTCOMP_HEAD_HDR_CAPC_SCLR_SF_PRECISION 20:16 /* RWIVF */
#define NVC873_POSTCOMP_HEAD_HDR_CAPC_SCLR_CI_PRECISION 24:21 /* RWIVF */
#define NVC873_POSTCOMP_HEAD_HDR_CAPC_SCLR_VS_EXT_RGB 25:25 /* RWIVF */
#define NVC873_POSTCOMP_HEAD_HDR_CAPC_SCLR_VS_EXT_RGB_TRUE 0x00000001 /* RW--V */
#define NVC873_POSTCOMP_HEAD_HDR_CAPC_SCLR_VS_EXT_RGB_FALSE 0x00000000 /* RW--V */
#define NVC873_POSTCOMP_HEAD_HDR_CAPC_SCLR_VS_MAX_SCALE_FACTOR 28:28 /* RWIVF */
#define NVC873_POSTCOMP_HEAD_HDR_CAPC_SCLR_VS_MAX_SCALE_FACTOR_2X 0x00000000 /* RW--V */
#define NVC873_POSTCOMP_HEAD_HDR_CAPC_SCLR_VS_MAX_SCALE_FACTOR_4X 0x00000001 /* RW--V */
#define NVC873_POSTCOMP_HEAD_HDR_CAPC_SCLR_HS_MAX_SCALE_FACTOR 30:30 /* RWIVF */
#define NVC873_POSTCOMP_HEAD_HDR_CAPC_SCLR_HS_MAX_SCALE_FACTOR_2X 0x00000000 /* RW--V */
#define NVC873_POSTCOMP_HEAD_HDR_CAPC_SCLR_HS_MAX_SCALE_FACTOR_4X 0x00000001 /* RW--V */
#define NVC873_POSTCOMP_HEAD_HDR_CAPD(i) (0x68c+(i)*32) /* RW-4A */
#define NVC873_POSTCOMP_HEAD_HDR_CAPD__SIZE_1 8 /* */
#define NVC873_POSTCOMP_HEAD_HDR_CAPD_VSCLR_MAX_PIXELS_2TAP 15:0 /* RWIVF */
#define NVC873_POSTCOMP_HEAD_HDR_CAPD_VSCLR_MAX_PIXELS_5TAP 31:16 /* RWIVF */
#define NVC873_POSTCOMP_HEAD_HDR_CAPE(i) (0x690+(i)*32) /* RW-4A */
#define NVC873_POSTCOMP_HEAD_HDR_CAPE__SIZE_1 8 /* */
#define NVC873_POSTCOMP_HEAD_HDR_CAPE_DSC_RATEBUFSIZE 3:0 /* RWIUF */
#define NVC873_POSTCOMP_HEAD_HDR_CAPE_DSC_LINEBUFSIZE 13:8 /* RWIUF */
#define NVC873_POSTCOMP_HEAD_HDR_CAPE_DSC_NATIVE422 16:16 /* RWIVF */
#define NVC873_POSTCOMP_HEAD_HDR_CAPE_DSC_NATIVE422_TRUE 0x00000001 /* RW--V */
#define NVC873_POSTCOMP_HEAD_HDR_CAPE_DSC_NATIVE422_FALSE 0x00000000 /* RW--V */
#define NVC873_POSTCOMP_HEAD_HDR_CAPE_DSC_NATIVE420 17:17 /* RWIVF */
#define NVC873_POSTCOMP_HEAD_HDR_CAPE_DSC_NATIVE420_TRUE 0x00000001 /* RW--V */
#define NVC873_POSTCOMP_HEAD_HDR_CAPE_DSC_NATIVE420_FALSE 0x00000000 /* RW--V */
#define NVC873_POSTCOMP_HEAD_HDR_CAPF(i) (0x694+(i)*32) /* RW-4A */
#define NVC873_POSTCOMP_HEAD_HDR_CAPF__SIZE_1 8 /* */
#define NVC873_POSTCOMP_HEAD_HDR_CAPF_VFILTER_MAX_PIXELS 15:0 /* RWIVF */
#define NVC873_SOR_CAP(i) (0x144+(i)*8) /* RW-4A */
#define NVC873_SOR_CAP__SIZE_1 8 /* */
#define NVC873_SOR_CAP_SINGLE_LVDS_18 0:0 /* RWIVF */
#define NVC873_SOR_CAP_SINGLE_LVDS_18_FALSE 0x00000000 /* RW--V */
#define NVC873_SOR_CAP_SINGLE_LVDS_18_TRUE 0x00000001 /* RW--V */
#define NVC873_SOR_CAP_SINGLE_LVDS_24 1:1 /* RWIVF */
#define NVC873_SOR_CAP_SINGLE_LVDS_24_FALSE 0x00000000 /* RW--V */
#define NVC873_SOR_CAP_SINGLE_LVDS_24_TRUE 0x00000001 /* RW--V */
#define NVC873_SOR_CAP_DUAL_LVDS_18 2:2 /* RWIVF */
#define NVC873_SOR_CAP_DUAL_LVDS_18_FALSE 0x00000000 /* RW--V */
#define NVC873_SOR_CAP_DUAL_LVDS_18_TRUE 0x00000001 /* RW--V */
#define NVC873_SOR_CAP_DUAL_LVDS_24 3:3 /* RWIVF */
#define NVC873_SOR_CAP_DUAL_LVDS_24_FALSE 0x00000000 /* RW--V */
#define NVC873_SOR_CAP_DUAL_LVDS_24_TRUE 0x00000001 /* RW--V */
#define NVC873_SOR_CAP_SINGLE_TMDS_A 8:8 /* RWIVF */
#define NVC873_SOR_CAP_SINGLE_TMDS_A_FALSE 0x00000000 /* RW--V */
#define NVC873_SOR_CAP_SINGLE_TMDS_A_TRUE 0x00000001 /* RW--V */
#define NVC873_SOR_CAP_SINGLE_TMDS_B 9:9 /* RWIVF */
#define NVC873_SOR_CAP_SINGLE_TMDS_B_FALSE 0x00000000 /* RW--V */
#define NVC873_SOR_CAP_SINGLE_TMDS_B_TRUE 0x00000001 /* RW--V */
#define NVC873_SOR_CAP_DUAL_TMDS 11:11 /* RWIVF */
#define NVC873_SOR_CAP_DUAL_TMDS_FALSE 0x00000000 /* RW--V */
#define NVC873_SOR_CAP_DUAL_TMDS_TRUE 0x00000001 /* RW--V */
#define NVC873_SOR_CAP_DISPLAY_OVER_PCIE 13:13 /* RWIVF */
#define NVC873_SOR_CAP_DISPLAY_OVER_PCIE_FALSE 0x00000000 /* RW--V */
#define NVC873_SOR_CAP_DISPLAY_OVER_PCIE_TRUE 0x00000001 /* RW--V */
#define NVC873_SOR_CAP_SDI 16:16 /* RWIVF */
#define NVC873_SOR_CAP_SDI_FALSE 0x00000000 /* RW--V */
#define NVC873_SOR_CAP_SDI_TRUE 0x00000001 /* RW--V */
#define NVC873_SOR_CAP_DP_A 24:24 /* RWIVF */
#define NVC873_SOR_CAP_DP_A_FALSE 0x00000000 /* RW--V */
#define NVC873_SOR_CAP_DP_A_TRUE 0x00000001 /* RW--V */
#define NVC873_SOR_CAP_DP_B 25:25 /* RWIVF */
#define NVC873_SOR_CAP_DP_B_FALSE 0x00000000 /* RW--V */
#define NVC873_SOR_CAP_DP_B_TRUE 0x00000001 /* RW--V */
#define NVC873_SOR_CAP_DP_INTERLACE 26:26 /* RWIVF */
#define NVC873_SOR_CAP_DP_INTERLACE_FALSE 0x00000000 /* RW--V */
#define NVC873_SOR_CAP_DP_INTERLACE_TRUE 0x00000001 /* RW--V */
#define NVC873_SOR_CAP_DP_8_LANES 27:27 /* RWIVF */
#define NVC873_SOR_CAP_DP_8_LANES_FALSE 0x00000000 /* RW--V */
#define NVC873_SOR_CAP_DP_8_LANES_TRUE 0x00000001 /* RW--V */
#define NVC873_SOR_CAP_HDMI_FRL 28:28 /* RWIVF */
#define NVC873_SOR_CAP_HDMI_FRL_FALSE 0x00000000 /* RW--V */
#define NVC873_SOR_CAP_HDMI_FRL_TRUE 0x00000001 /* RW--V */
#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPA(i) (0x780+(i)*32) /* RW-4A */
#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPA__SIZE_1 32 /* */
#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPA_FULL_WIDTH 4:0 /* RWIVF */
#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPA_UNIT_WIDTH 9:5 /* RWIVF */
#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPA_ALPHA_WIDTH 13:10 /* RWIVF */
#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPA_CSC00_PRESENT 16:16 /* RWIVF */
#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPA_CSC00_PRESENT_TRUE 0x00000001 /* RW--V */
#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPA_CSC00_PRESENT_FALSE 0x00000000 /* RW--V */
#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPA_CSC0LUT_PRESENT 17:17 /* RWIVF */
#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPA_CSC0LUT_PRESENT_TRUE 0x00000001 /* RW--V */
#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPA_CSC0LUT_PRESENT_FALSE 0x00000000 /* RW--V */
#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPA_CSC01_PRESENT 18:18 /* RWIVF */
#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPA_CSC01_PRESENT_TRUE 0x00000001 /* RW--V */
#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPA_CSC01_PRESENT_FALSE 0x00000000 /* RW--V */
#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPA_SCLR_PRESENT 19:19 /* RWIVF */
#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPA_SCLR_PRESENT_TRUE 0x00000001 /* RW--V */
#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPA_SCLR_PRESENT_FALSE 0x00000000 /* RW--V */
#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPA_TMO_PRESENT 20:20 /* RWIVF */
#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPA_TMO_PRESENT_TRUE 0x00000001 /* RW--V */
#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPA_TMO_PRESENT_FALSE 0x00000000 /* RW--V */
#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPA_GMA_PRESENT 21:21 /* RWIVF */
#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPA_GMA_PRESENT_TRUE 0x00000001 /* RW--V */
#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPA_GMA_PRESENT_FALSE 0x00000000 /* RW--V */
#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPA_CSC10_PRESENT 22:22 /* RWIVF */
#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPA_CSC10_PRESENT_TRUE 0x00000001 /* RW--V */
#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPA_CSC10_PRESENT_FALSE 0x00000000 /* RW--V */
#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPA_CSC1LUT_PRESENT 23:23 /* RWIVF */
#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPA_CSC1LUT_PRESENT_TRUE 0x00000001 /* RW--V */
#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPA_CSC1LUT_PRESENT_FALSE 0x00000000 /* RW--V */
#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPA_CSC11_PRESENT 24:24 /* RWIVF */
#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPA_CSC11_PRESENT_TRUE 0x00000001 /* RW--V */
#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPA_CSC11_PRESENT_FALSE 0x00000000 /* RW--V */
#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPB(i) (0x784+(i)*32) /* RW-4A */
#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPB__SIZE_1 32 /* */
#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPB_FMT_PRECISION 4:0 /* RWIVF */
#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPB_ILUT_LOGSZ 9:6 /* RWIVF */
#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPB_ILUT_LOGNR 12:10 /* RWIVF */
#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPB_ILUT_SFCLOAD 14:14 /* RWIVF */
#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPB_ILUT_SFCLOAD_TRUE 0x00000001 /* RW--V */
#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPB_ILUT_SFCLOAD_FALSE 0x00000000 /* RW--V */
#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPB_ILUT_DIRECT 15:15 /* RWIVF */
#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPB_ILUT_DIRECT_TRUE 0x00000001 /* RW--V */
#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPB_ILUT_DIRECT_FALSE 0x00000000 /* RW--V */
#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPC(i) (0x788+(i)*32) /* RW-4A */
#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPC__SIZE_1 32 /* */
#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPC_CSC00_PRECISION 4:0 /* RWIVF */
#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPC_CSC00_UNITY_CLAMP 5:5 /* RWIVF */
#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPC_CSC00_UNITY_CLAMP_TRUE 0x00000001 /* RW--V */
#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPC_CSC00_UNITY_CLAMP_FALSE 0x00000000 /* RW--V */
#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPC_CSC0LUT_LOGSZ 9:6 /* RWIVF */
#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPC_CSC0LUT_LOGNR 12:10 /* RWIVF */
#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPC_CSC0LUT_SFCLOAD 14:14 /* RWIVF */
#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPC_CSC0LUT_SFCLOAD_TRUE 0x00000001 /* RW--V */
#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPC_CSC0LUT_SFCLOAD_FALSE 0x00000000 /* RW--V */
#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPC_CSC0LUT_DIRECT 15:15 /* RWIVF */
#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPC_CSC0LUT_DIRECT_TRUE 0x00000001 /* RW--V */
#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPC_CSC0LUT_DIRECT_FALSE 0x00000000 /* RW--V */
#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPC_CSC01_PRECISION 20:16 /* RWIVF */
#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPC_CSC01_UNITY_CLAMP 21:21 /* RWIVF */
#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPC_CSC01_UNITY_CLAMP_TRUE 0x00000001 /* RW--V */
#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPC_CSC01_UNITY_CLAMP_FALSE 0x00000000 /* RW--V */
#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPD(i) (0x78c+(i)*32) /* RW-4A */
#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPD__SIZE_1 32 /* */
#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPD_TMO_LOGSZ 3:0 /* RWIVF */
#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPD_TMO_LOGNR 6:4 /* RWIVF */
#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPD_TMO_SFCLOAD 8:8 /* RWIVF */
#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPD_TMO_SFCLOAD_TRUE 0x00000001 /* RW--V */
#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPD_TMO_SFCLOAD_FALSE 0x00000000 /* RW--V */
#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPD_TMO_DIRECT 9:9 /* RWIVF */
#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPD_TMO_DIRECT_TRUE 0x00000001 /* RW--V */
#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPD_TMO_DIRECT_FALSE 0x00000000 /* RW--V */
#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_SF_PRECISION 16:12 /* RWIVF */
#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_CI_PRECISION 20:17 /* RWIVF */
#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_VS_EXT_RGB 21:21 /* RWIVF */
#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_VS_EXT_RGB_TRUE 0x00000001 /* RW--V */
#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_VS_EXT_RGB_FALSE 0x00000000 /* RW--V */
#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_EXT_ALPHA 22:22 /* RWIVF */
#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_EXT_ALPHA_TRUE 0x00000001 /* RW--V */
#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_EXT_ALPHA_FALSE 0x00000000 /* RW--V */
#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_VS_MAX_SCALE_FACTOR 28:28 /* RWIVF */
#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_VS_MAX_SCALE_FACTOR_2X 0x00000000 /* RW--V */
#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_VS_MAX_SCALE_FACTOR_4X 0x00000001 /* RW--V */
#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_HS_MAX_SCALE_FACTOR 30:30 /* RWIVF */
#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_HS_MAX_SCALE_FACTOR_2X 0x00000000 /* RW--V */
#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_HS_MAX_SCALE_FACTOR_4X 0x00000001 /* RW--V */
#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPE(i) (0x790+(i)*32) /* RW-4A */
#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPE__SIZE_1 32 /* */
#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPE_CSC10_PRECISION 4:0 /* RWIVF */
#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPE_CSC10_UNITY_CLAMP 5:5 /* RWIVF */
#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPE_CSC10_UNITY_CLAMP_TRUE 0x00000001 /* RW--V */
#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPE_CSC10_UNITY_CLAMP_FALSE 0x00000000 /* RW--V */
#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPE_CSC1LUT_LOGSZ 9:6 /* RWIVF */
#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPE_CSC1LUT_LOGNR 12:10 /* RWIVF */
#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPE_CSC1LUT_SFCLOAD 14:14 /* RWIVF */
#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPE_CSC1LUT_SFCLOAD_TRUE 0x00000001 /* RW--V */
#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPE_CSC1LUT_SFCLOAD_FALSE 0x00000000 /* RW--V */
#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPE_CSC1LUT_DIRECT 15:15 /* RWIVF */
#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPE_CSC1LUT_DIRECT_TRUE 0x00000001 /* RW--V */
#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPE_CSC1LUT_DIRECT_FALSE 0x00000000 /* RW--V */
#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPE_CSC11_PRECISION 20:16 /* RWIVF */
#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPE_CSC11_UNITY_CLAMP 21:21 /* RWIVF */
#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPE_CSC11_UNITY_CLAMP_TRUE 0x00000001 /* RW--V */
#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPE_CSC11_UNITY_CLAMP_FALSE 0x00000000 /* RW--V */
#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPF(i) (0x794+(i)*32) /* RW-4A */
#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPF__SIZE_1 32 /* */
#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPF_VSCLR_MAX_PIXELS_2TAP 15:0 /* RWIVF */
#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPF_VSCLR_MAX_PIXELS_5TAP 31:16 /* RWIVF */
#ifdef __cplusplus
};
#endif /* extern C */
#endif //_clc873_h_

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src/common/sdk/nvidia/inc/class/clc87e.h Normal file
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/*
* SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _clC87e_h_
#define _clC87e_h_
#ifdef __cplusplus
extern "C" {
#endif
#define NVC87E_WINDOW_CHANNEL_DMA (0x0000C87E)
// dma opcode instructions
#define NVC87E_DMA
#define NVC87E_DMA_OPCODE 31:29
#define NVC87E_DMA_OPCODE_METHOD 0x00000000
#define NVC87E_DMA_OPCODE_JUMP 0x00000001
#define NVC87E_DMA_OPCODE_NONINC_METHOD 0x00000002
#define NVC87E_DMA_OPCODE_SET_SUBDEVICE_MASK 0x00000003
#define NVC87E_DMA_METHOD_COUNT 27:18
#define NVC87E_DMA_METHOD_OFFSET 13:2
#define NVC87E_DMA_DATA 31:0
#define NVC87E_DMA_DATA_NOP 0x00000000
#define NVC87E_DMA_JUMP_OFFSET 11:2
#define NVC87E_DMA_SET_SUBDEVICE_MASK_VALUE 11:0
// class methods
#define NVC87E_PUT (0x00000000)
#define NVC87E_PUT_PTR 9:0
#define NVC87E_GET (0x00000004)
#define NVC87E_GET_PTR 9:0
#define NVC87E_UPDATE (0x00000200)
#define NVC87E_UPDATE_RELEASE_ELV 0:0
#define NVC87E_UPDATE_RELEASE_ELV_FALSE (0x00000000)
#define NVC87E_UPDATE_RELEASE_ELV_TRUE (0x00000001)
#define NVC87E_UPDATE_FLIP_LOCK_PIN 8:4
#define NVC87E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_NONE (0x00000000)
#define NVC87E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN(i) (0x00000001 +(i))
#define NVC87E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN__SIZE_1 16
#define NVC87E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_0 (0x00000001)
#define NVC87E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_1 (0x00000002)
#define NVC87E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_2 (0x00000003)
#define NVC87E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_3 (0x00000004)
#define NVC87E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_4 (0x00000005)
#define NVC87E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_5 (0x00000006)
#define NVC87E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_6 (0x00000007)
#define NVC87E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_7 (0x00000008)
#define NVC87E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_8 (0x00000009)
#define NVC87E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_9 (0x0000000A)
#define NVC87E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_A (0x0000000B)
#define NVC87E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_B (0x0000000C)
#define NVC87E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_C (0x0000000D)
#define NVC87E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_D (0x0000000E)
#define NVC87E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_E (0x0000000F)
#define NVC87E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_F (0x00000010)
#define NVC87E_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_0 (0x00000014)
#define NVC87E_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_1 (0x00000015)
#define NVC87E_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_2 (0x00000016)
#define NVC87E_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_3 (0x00000017)
#define NVC87E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK(i) (0x00000018 +(i))
#define NVC87E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK__SIZE_1 8
#define NVC87E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_0 (0x00000018)
#define NVC87E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_1 (0x00000019)
#define NVC87E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_2 (0x0000001A)
#define NVC87E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_3 (0x0000001B)
#define NVC87E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_4 (0x0000001C)
#define NVC87E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_5 (0x0000001D)
#define NVC87E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_6 (0x0000001E)
#define NVC87E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_7 (0x0000001F)
#define NVC87E_UPDATE_INTERLOCK_WITH_WIN_IMM 12:12
#define NVC87E_UPDATE_INTERLOCK_WITH_WIN_IMM_DISABLE (0x00000000)
#define NVC87E_UPDATE_INTERLOCK_WITH_WIN_IMM_ENABLE (0x00000001)
#define NVC87E_SET_SEMAPHORE_ACQUIRE_HI (0x00000204)
#define NVC87E_SET_SEMAPHORE_ACQUIRE_HI_VALUE 31:0
#define NVC87E_GET_LINE (0x00000208)
#define NVC87E_GET_LINE_LINE 15:0
#define NVC87E_SET_SEMAPHORE_CONTROL (0x0000020C)
#define NVC87E_SET_SEMAPHORE_CONTROL_OFFSET 7:0
#define NVC87E_SET_SEMAPHORE_CONTROL_SKIP_ACQ 11:11
#define NVC87E_SET_SEMAPHORE_CONTROL_SKIP_ACQ_FALSE (0x00000000)
#define NVC87E_SET_SEMAPHORE_CONTROL_SKIP_ACQ_TRUE (0x00000001)
#define NVC87E_SET_SEMAPHORE_CONTROL_PAYLOAD_SIZE 15:15
#define NVC87E_SET_SEMAPHORE_CONTROL_PAYLOAD_SIZE_PAYLOAD_32BIT (0x00000000)
#define NVC87E_SET_SEMAPHORE_CONTROL_PAYLOAD_SIZE_PAYLOAD_64BIT (0x00000001)
#define NVC87E_SET_SEMAPHORE_CONTROL_ACQ_MODE 13:12
#define NVC87E_SET_SEMAPHORE_CONTROL_ACQ_MODE_EQ (0x00000000)
#define NVC87E_SET_SEMAPHORE_CONTROL_ACQ_MODE_CGEQ (0x00000001)
#define NVC87E_SET_SEMAPHORE_CONTROL_ACQ_MODE_STRICT_GEQ (0x00000002)
#define NVC87E_SET_SEMAPHORE_CONTROL_REL_MODE 14:14
#define NVC87E_SET_SEMAPHORE_CONTROL_REL_MODE_WRITE (0x00000000)
#define NVC87E_SET_SEMAPHORE_CONTROL_REL_MODE_WRITE_AWAKEN (0x00000001)
#define NVC87E_SET_SEMAPHORE_ACQUIRE (0x00000210)
#define NVC87E_SET_SEMAPHORE_ACQUIRE_VALUE 31:0
#define NVC87E_SET_SEMAPHORE_RELEASE (0x00000214)
#define NVC87E_SET_SEMAPHORE_RELEASE_VALUE 31:0
#define NVC87E_SET_CONTEXT_DMA_SEMAPHORE (0x00000218)
#define NVC87E_SET_CONTEXT_DMA_SEMAPHORE_HANDLE 31:0
#define NVC87E_SET_CONTEXT_DMA_NOTIFIER (0x0000021C)
#define NVC87E_SET_CONTEXT_DMA_NOTIFIER_HANDLE 31:0
#define NVC87E_SET_NOTIFIER_CONTROL (0x00000220)
#define NVC87E_SET_NOTIFIER_CONTROL_MODE 0:0
#define NVC87E_SET_NOTIFIER_CONTROL_MODE_WRITE (0x00000000)
#define NVC87E_SET_NOTIFIER_CONTROL_MODE_WRITE_AWAKEN (0x00000001)
#define NVC87E_SET_NOTIFIER_CONTROL_OFFSET 11:4
#define NVC87E_SET_SIZE (0x00000224)
#define NVC87E_SET_SIZE_WIDTH 15:0
#define NVC87E_SET_SIZE_HEIGHT 31:16
#define NVC87E_SET_STORAGE (0x00000228)
#define NVC87E_SET_STORAGE_BLOCK_HEIGHT 3:0
#define NVC87E_SET_STORAGE_BLOCK_HEIGHT_NVD_BLOCK_HEIGHT_ONE_GOB (0x00000000)
#define NVC87E_SET_STORAGE_BLOCK_HEIGHT_NVD_BLOCK_HEIGHT_TWO_GOBS (0x00000001)
#define NVC87E_SET_STORAGE_BLOCK_HEIGHT_NVD_BLOCK_HEIGHT_FOUR_GOBS (0x00000002)
#define NVC87E_SET_STORAGE_BLOCK_HEIGHT_NVD_BLOCK_HEIGHT_EIGHT_GOBS (0x00000003)
#define NVC87E_SET_STORAGE_BLOCK_HEIGHT_NVD_BLOCK_HEIGHT_SIXTEEN_GOBS (0x00000004)
#define NVC87E_SET_STORAGE_BLOCK_HEIGHT_NVD_BLOCK_HEIGHT_THIRTYTWO_GOBS (0x00000005)
#define NVC87E_SET_PARAMS (0x0000022C)
#define NVC87E_SET_PARAMS_FORMAT 7:0
#define NVC87E_SET_PARAMS_FORMAT_I8 (0x0000001E)
#define NVC87E_SET_PARAMS_FORMAT_R4G4B4A4 (0x0000002F)
#define NVC87E_SET_PARAMS_FORMAT_R5G6B5 (0x000000E8)
#define NVC87E_SET_PARAMS_FORMAT_A1R5G5B5 (0x000000E9)
#define NVC87E_SET_PARAMS_FORMAT_R5G5B5A1 (0x0000002E)
#define NVC87E_SET_PARAMS_FORMAT_A8R8G8B8 (0x000000CF)
#define NVC87E_SET_PARAMS_FORMAT_X8R8G8B8 (0x000000E6)
#define NVC87E_SET_PARAMS_FORMAT_A8B8G8R8 (0x000000D5)
#define NVC87E_SET_PARAMS_FORMAT_X8B8G8R8 (0x000000F9)
#define NVC87E_SET_PARAMS_FORMAT_A2R10G10B10 (0x000000DF)
#define NVC87E_SET_PARAMS_FORMAT_A2B10G10R10 (0x000000D1)
#define NVC87E_SET_PARAMS_FORMAT_R16_G16_B16_A16_NVBIAS (0x00000023)
#define NVC87E_SET_PARAMS_FORMAT_R16_G16_B16_A16 (0x000000C6)
#define NVC87E_SET_PARAMS_FORMAT_RF16_GF16_BF16_AF16 (0x000000CA)
#define NVC87E_SET_PARAMS_FORMAT_Y8_U8__Y8_V8_N422 (0x00000028)
#define NVC87E_SET_PARAMS_FORMAT_U8_Y8__V8_Y8_N422 (0x00000029)
#define NVC87E_SET_PARAMS_FORMAT_Y8___U8V8_N444 (0x00000035)
#define NVC87E_SET_PARAMS_FORMAT_Y8___U8V8_N422 (0x00000036)
#define NVC87E_SET_PARAMS_FORMAT_Y8___V8U8_N420 (0x00000038)
#define NVC87E_SET_PARAMS_FORMAT_Y8___U8___V8_N444 (0x0000003A)
#define NVC87E_SET_PARAMS_FORMAT_Y8___U8___V8_N420 (0x0000003B)
#define NVC87E_SET_PARAMS_FORMAT_Y10___U10V10_N444 (0x00000055)
#define NVC87E_SET_PARAMS_FORMAT_Y10___U10V10_N422 (0x00000056)
#define NVC87E_SET_PARAMS_FORMAT_Y10___V10U10_N420 (0x00000058)
#define NVC87E_SET_PARAMS_FORMAT_Y12___U12V12_N444 (0x00000075)
#define NVC87E_SET_PARAMS_FORMAT_Y12___U12V12_N422 (0x00000076)
#define NVC87E_SET_PARAMS_FORMAT_Y12___V12U12_N420 (0x00000078)
#define NVC87E_SET_PARAMS_CLAMP_BEFORE_BLEND 18:18
#define NVC87E_SET_PARAMS_CLAMP_BEFORE_BLEND_DISABLE (0x00000000)
#define NVC87E_SET_PARAMS_CLAMP_BEFORE_BLEND_ENABLE (0x00000001)
#define NVC87E_SET_PARAMS_SWAP_UV 19:19
#define NVC87E_SET_PARAMS_SWAP_UV_DISABLE (0x00000000)
#define NVC87E_SET_PARAMS_SWAP_UV_ENABLE (0x00000001)
#define NVC87E_SET_PARAMS_FMT_ROUNDING_MODE 22:22
#define NVC87E_SET_PARAMS_FMT_ROUNDING_MODE_ROUND_TO_NEAREST (0x00000000)
#define NVC87E_SET_PARAMS_FMT_ROUNDING_MODE_ROUND_DOWN (0x00000001)
#define NVC87E_SET_PLANAR_STORAGE(b) (0x00000230 + (b)*0x00000004)
#define NVC87E_SET_PLANAR_STORAGE_PITCH 12:0
#define NVC87E_SET_SEMAPHORE_RELEASE_HI (0x0000023C)
#define NVC87E_SET_SEMAPHORE_RELEASE_HI_VALUE 31:0
#define NVC87E_SET_CONTEXT_DMA_ISO(b) (0x00000240 + (b)*0x00000004)
#define NVC87E_SET_CONTEXT_DMA_ISO_HANDLE 31:0
#define NVC87E_SET_OFFSET(b) (0x00000260 + (b)*0x00000004)
#define NVC87E_SET_OFFSET_ORIGIN 31:0
#define NVC87E_SET_POINT_IN(b) (0x00000290 + (b)*0x00000004)
#define NVC87E_SET_POINT_IN_X 15:0
#define NVC87E_SET_POINT_IN_Y 31:16
#define NVC87E_SET_SIZE_IN (0x00000298)
#define NVC87E_SET_SIZE_IN_WIDTH 15:0
#define NVC87E_SET_SIZE_IN_HEIGHT 31:16
#define NVC87E_SET_SIZE_OUT (0x000002A4)
#define NVC87E_SET_SIZE_OUT_WIDTH 15:0
#define NVC87E_SET_SIZE_OUT_HEIGHT 31:16
#define NVC87E_SET_CONTROL_INPUT_SCALER (0x000002A8)
#define NVC87E_SET_CONTROL_INPUT_SCALER_VERTICAL_TAPS 2:0
#define NVC87E_SET_CONTROL_INPUT_SCALER_VERTICAL_TAPS_TAPS_2 (0x00000001)
#define NVC87E_SET_CONTROL_INPUT_SCALER_VERTICAL_TAPS_TAPS_5 (0x00000004)
#define NVC87E_SET_CONTROL_INPUT_SCALER_HORIZONTAL_TAPS 6:4
#define NVC87E_SET_CONTROL_INPUT_SCALER_HORIZONTAL_TAPS_TAPS_2 (0x00000001)
#define NVC87E_SET_CONTROL_INPUT_SCALER_HORIZONTAL_TAPS_TAPS_5 (0x00000004)
#define NVC87E_SET_INPUT_SCALER_COEFF_VALUE (0x000002AC)
#define NVC87E_SET_INPUT_SCALER_COEFF_VALUE_DATA 9:0
#define NVC87E_SET_INPUT_SCALER_COEFF_VALUE_INDEX 19:12
#define NVC87E_SET_COMPOSITION_CONTROL (0x000002EC)
#define NVC87E_SET_COMPOSITION_CONTROL_COLOR_KEY_SELECT 1:0
#define NVC87E_SET_COMPOSITION_CONTROL_COLOR_KEY_SELECT_DISABLE (0x00000000)
#define NVC87E_SET_COMPOSITION_CONTROL_COLOR_KEY_SELECT_SRC (0x00000001)
#define NVC87E_SET_COMPOSITION_CONTROL_COLOR_KEY_SELECT_DST (0x00000002)
#define NVC87E_SET_COMPOSITION_CONTROL_DEPTH 11:4
#define NVC87E_SET_COMPOSITION_CONTROL_BYPASS 16:16
#define NVC87E_SET_COMPOSITION_CONTROL_BYPASS_DISABLE (0x00000000)
#define NVC87E_SET_COMPOSITION_CONTROL_BYPASS_ENABLE (0x00000001)
#define NVC87E_SET_COMPOSITION_CONSTANT_ALPHA (0x000002F0)
#define NVC87E_SET_COMPOSITION_CONSTANT_ALPHA_K1 7:0
#define NVC87E_SET_COMPOSITION_CONSTANT_ALPHA_K2 15:8
#define NVC87E_SET_COMPOSITION_FACTOR_SELECT (0x000002F4)
#define NVC87E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT 3:0
#define NVC87E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT_ZERO (0x00000000)
#define NVC87E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT_ONE (0x00000001)
#define NVC87E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT_K1 (0x00000002)
#define NVC87E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT_K1_TIMES_SRC (0x00000005)
#define NVC87E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT_K1_TIMES_DST (0x00000006)
#define NVC87E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT_NEG_K1_TIMES_DST (0x00000008)
#define NVC87E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_NO_MATCH_SELECT 7:4
#define NVC87E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_NO_MATCH_SELECT_ZERO (0x00000000)
#define NVC87E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_NO_MATCH_SELECT_ONE (0x00000001)
#define NVC87E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_NO_MATCH_SELECT_K1 (0x00000002)
#define NVC87E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_NO_MATCH_SELECT_K1_TIMES_SRC (0x00000005)
#define NVC87E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_NO_MATCH_SELECT_K1_TIMES_DST (0x00000006)
#define NVC87E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_NO_MATCH_SELECT_NEG_K1_TIMES_DST (0x00000008)
#define NVC87E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT 11:8
#define NVC87E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_ZERO (0x00000000)
#define NVC87E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_ONE (0x00000001)
#define NVC87E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_K1 (0x00000002)
#define NVC87E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_K2 (0x00000003)
#define NVC87E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_NEG_K1 (0x00000004)
#define NVC87E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_K1_TIMES_DST (0x00000006)
#define NVC87E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_NEG_K1_TIMES_SRC (0x00000007)
#define NVC87E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_NEG_K1_TIMES_DST (0x00000008)
#define NVC87E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT 15:12
#define NVC87E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_ZERO (0x00000000)
#define NVC87E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_ONE (0x00000001)
#define NVC87E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_K1 (0x00000002)
#define NVC87E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_K2 (0x00000003)
#define NVC87E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_NEG_K1 (0x00000004)
#define NVC87E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_K1_TIMES_DST (0x00000006)
#define NVC87E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_NEG_K1_TIMES_SRC (0x00000007)
#define NVC87E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_NEG_K1_TIMES_DST (0x00000008)
#define NVC87E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_MATCH_SELECT 19:16
#define NVC87E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_MATCH_SELECT_ZERO (0x00000000)
#define NVC87E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_MATCH_SELECT_K1 (0x00000002)
#define NVC87E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_MATCH_SELECT_K2 (0x00000003)
#define NVC87E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_MATCH_SELECT_NEG_K1_TIMES_DST (0x00000008)
#define NVC87E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_NO_MATCH_SELECT 23:20
#define NVC87E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_NO_MATCH_SELECT_ZERO (0x00000000)
#define NVC87E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_NO_MATCH_SELECT_K1 (0x00000002)
#define NVC87E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_NO_MATCH_SELECT_K2 (0x00000003)
#define NVC87E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_NO_MATCH_SELECT_NEG_K1_TIMES_DST (0x00000008)
#define NVC87E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_MATCH_SELECT 27:24
#define NVC87E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_MATCH_SELECT_ZERO (0x00000000)
#define NVC87E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_MATCH_SELECT_ONE (0x00000001)
#define NVC87E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_MATCH_SELECT_K2 (0x00000003)
#define NVC87E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_MATCH_SELECT_NEG_K1_TIMES_SRC (0x00000007)
#define NVC87E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_NO_MATCH_SELECT 31:28
#define NVC87E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_NO_MATCH_SELECT_ZERO (0x00000000)
#define NVC87E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_NO_MATCH_SELECT_ONE (0x00000001)
#define NVC87E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_NO_MATCH_SELECT_K2 (0x00000003)
#define NVC87E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_NO_MATCH_SELECT_NEG_K1_TIMES_SRC (0x00000007)
#define NVC87E_SET_KEY_ALPHA (0x000002F8)
#define NVC87E_SET_KEY_ALPHA_MIN 15:0
#define NVC87E_SET_KEY_ALPHA_MAX 31:16
#define NVC87E_SET_KEY_RED_CR (0x000002FC)
#define NVC87E_SET_KEY_RED_CR_MIN 15:0
#define NVC87E_SET_KEY_RED_CR_MAX 31:16
#define NVC87E_SET_KEY_GREEN_Y (0x00000300)
#define NVC87E_SET_KEY_GREEN_Y_MIN 15:0
#define NVC87E_SET_KEY_GREEN_Y_MAX 31:16
#define NVC87E_SET_KEY_BLUE_CB (0x00000304)
#define NVC87E_SET_KEY_BLUE_CB_MIN 15:0
#define NVC87E_SET_KEY_BLUE_CB_MAX 31:16
#define NVC87E_SET_PRESENT_CONTROL (0x00000308)
#define NVC87E_SET_PRESENT_CONTROL_MIN_PRESENT_INTERVAL 3:0
#define NVC87E_SET_PRESENT_CONTROL_BEGIN_MODE 6:4
#define NVC87E_SET_PRESENT_CONTROL_BEGIN_MODE_NON_TEARING (0x00000000)
#define NVC87E_SET_PRESENT_CONTROL_BEGIN_MODE_IMMEDIATE (0x00000001)
#define NVC87E_SET_PRESENT_CONTROL_TIMESTAMP_MODE 8:8
#define NVC87E_SET_PRESENT_CONTROL_TIMESTAMP_MODE_DISABLE (0x00000000)
#define NVC87E_SET_PRESENT_CONTROL_TIMESTAMP_MODE_ENABLE (0x00000001)
#define NVC87E_SET_PRESENT_CONTROL_STEREO_MODE 13:12
#define NVC87E_SET_PRESENT_CONTROL_STEREO_MODE_MONO (0x00000000)
#define NVC87E_SET_PRESENT_CONTROL_STEREO_MODE_PAIR_FLIP (0x00000001)
#define NVC87E_SET_PRESENT_CONTROL_STEREO_MODE_AT_ANY_FRAME (0x00000002)
#define NVC87E_SET_ACQ_SEMAPHORE_VALUE_HI (0x0000030C)
#define NVC87E_SET_ACQ_SEMAPHORE_VALUE_HI_VALUE 31:0
#define NVC87E_SET_ACQ_SEMAPHORE_CONTROL (0x00000330)
#define NVC87E_SET_ACQ_SEMAPHORE_CONTROL_OFFSET 7:0
#define NVC87E_SET_ACQ_SEMAPHORE_CONTROL_PAYLOAD_SIZE 15:15
#define NVC87E_SET_ACQ_SEMAPHORE_CONTROL_PAYLOAD_SIZE_PAYLOAD_32BIT (0x00000000)
#define NVC87E_SET_ACQ_SEMAPHORE_CONTROL_PAYLOAD_SIZE_PAYLOAD_64BIT (0x00000001)
#define NVC87E_SET_ACQ_SEMAPHORE_CONTROL_ACQ_MODE 13:12
#define NVC87E_SET_ACQ_SEMAPHORE_CONTROL_ACQ_MODE_EQ (0x00000000)
#define NVC87E_SET_ACQ_SEMAPHORE_CONTROL_ACQ_MODE_CGEQ (0x00000001)
#define NVC87E_SET_ACQ_SEMAPHORE_CONTROL_ACQ_MODE_STRICT_GEQ (0x00000002)
#define NVC87E_SET_ACQ_SEMAPHORE_VALUE (0x00000334)
#define NVC87E_SET_ACQ_SEMAPHORE_VALUE_VALUE 31:0
#define NVC87E_SET_CONTEXT_DMA_ACQ_SEMAPHORE (0x00000338)
#define NVC87E_SET_CONTEXT_DMA_ACQ_SEMAPHORE_HANDLE 31:0
#define NVC87E_SET_SCAN_DIRECTION (0x0000033C)
#define NVC87E_SET_SCAN_DIRECTION_HORIZONTAL_DIRECTION 0:0
#define NVC87E_SET_SCAN_DIRECTION_HORIZONTAL_DIRECTION_FROM_LEFT (0x00000000)
#define NVC87E_SET_SCAN_DIRECTION_HORIZONTAL_DIRECTION_FROM_RIGHT (0x00000001)
#define NVC87E_SET_SCAN_DIRECTION_VERTICAL_DIRECTION 1:1
#define NVC87E_SET_SCAN_DIRECTION_VERTICAL_DIRECTION_FROM_TOP (0x00000000)
#define NVC87E_SET_SCAN_DIRECTION_VERTICAL_DIRECTION_FROM_BOTTOM (0x00000001)
#define NVC87E_SET_SCAN_DIRECTION_COLUMN_ORDER 2:2
#define NVC87E_SET_SCAN_DIRECTION_COLUMN_ORDER_FALSE (0x00000000)
#define NVC87E_SET_SCAN_DIRECTION_COLUMN_ORDER_TRUE (0x00000001)
#define NVC87E_SET_TIMESTAMP_ORIGIN_LO (0x00000340)
#define NVC87E_SET_TIMESTAMP_ORIGIN_LO_TIMESTAMP_LO 31:0
#define NVC87E_SET_TIMESTAMP_ORIGIN_HI (0x00000344)
#define NVC87E_SET_TIMESTAMP_ORIGIN_HI_TIMESTAMP_HI 31:0
#define NVC87E_SET_UPDATE_TIMESTAMP_LO (0x00000348)
#define NVC87E_SET_UPDATE_TIMESTAMP_LO_TIMESTAMP_LO 31:0
#define NVC87E_SET_UPDATE_TIMESTAMP_HI (0x0000034C)
#define NVC87E_SET_UPDATE_TIMESTAMP_HI_TIMESTAMP_HI 31:0
#define NVC87E_SET_INTERLOCK_FLAGS (0x00000370)
#define NVC87E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CORE 0:0
#define NVC87E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CORE_DISABLE (0x00000000)
#define NVC87E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CORE_ENABLE (0x00000001)
#define NVC87E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR(i) ((i)+1):((i)+1)
#define NVC87E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR__SIZE_1 8
#define NVC87E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR_DISABLE (0x00000000)
#define NVC87E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR_ENABLE (0x00000001)
#define NVC87E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0 1:1
#define NVC87E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0_DISABLE (0x00000000)
#define NVC87E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0_ENABLE (0x00000001)
#define NVC87E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR1 2:2
#define NVC87E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR1_DISABLE (0x00000000)
#define NVC87E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR1_ENABLE (0x00000001)
#define NVC87E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR2 3:3
#define NVC87E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR2_DISABLE (0x00000000)
#define NVC87E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR2_ENABLE (0x00000001)
#define NVC87E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR3 4:4
#define NVC87E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR3_DISABLE (0x00000000)
#define NVC87E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR3_ENABLE (0x00000001)
#define NVC87E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR4 5:5
#define NVC87E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR4_DISABLE (0x00000000)
#define NVC87E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR4_ENABLE (0x00000001)
#define NVC87E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR5 6:6
#define NVC87E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR5_DISABLE (0x00000000)
#define NVC87E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR5_ENABLE (0x00000001)
#define NVC87E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR6 7:7
#define NVC87E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR6_DISABLE (0x00000000)
#define NVC87E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR6_ENABLE (0x00000001)
#define NVC87E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR7 8:8
#define NVC87E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR7_DISABLE (0x00000000)
#define NVC87E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR7_ENABLE (0x00000001)
#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS (0x00000374)
#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW(i) ((i)+0):((i)+0)
#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW__SIZE_1 32
#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW_DISABLE (0x00000000)
#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW_ENABLE (0x00000001)
#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW0 0:0
#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW0_DISABLE (0x00000000)
#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW0_ENABLE (0x00000001)
#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW1 1:1
#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW1_DISABLE (0x00000000)
#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW1_ENABLE (0x00000001)
#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW2 2:2
#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW2_DISABLE (0x00000000)
#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW2_ENABLE (0x00000001)
#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW3 3:3
#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW3_DISABLE (0x00000000)
#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW3_ENABLE (0x00000001)
#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW4 4:4
#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW4_DISABLE (0x00000000)
#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW4_ENABLE (0x00000001)
#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW5 5:5
#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW5_DISABLE (0x00000000)
#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW5_ENABLE (0x00000001)
#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW6 6:6
#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW6_DISABLE (0x00000000)
#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW6_ENABLE (0x00000001)
#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW7 7:7
#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW7_DISABLE (0x00000000)
#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW7_ENABLE (0x00000001)
#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW8 8:8
#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW8_DISABLE (0x00000000)
#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW8_ENABLE (0x00000001)
#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW9 9:9
#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW9_DISABLE (0x00000000)
#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW9_ENABLE (0x00000001)
#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW10 10:10
#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW10_DISABLE (0x00000000)
#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW10_ENABLE (0x00000001)
#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW11 11:11
#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW11_DISABLE (0x00000000)
#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW11_ENABLE (0x00000001)
#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW12 12:12
#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW12_DISABLE (0x00000000)
#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW12_ENABLE (0x00000001)
#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW13 13:13
#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW13_DISABLE (0x00000000)
#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW13_ENABLE (0x00000001)
#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW14 14:14
#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW14_DISABLE (0x00000000)
#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW14_ENABLE (0x00000001)
#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW15 15:15
#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW15_DISABLE (0x00000000)
#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW15_ENABLE (0x00000001)
#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW16 16:16
#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW16_DISABLE (0x00000000)
#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW16_ENABLE (0x00000001)
#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW17 17:17
#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW17_DISABLE (0x00000000)
#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW17_ENABLE (0x00000001)
#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW18 18:18
#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW18_DISABLE (0x00000000)
#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW18_ENABLE (0x00000001)
#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW19 19:19
#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW19_DISABLE (0x00000000)
#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW19_ENABLE (0x00000001)
#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW20 20:20
#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW20_DISABLE (0x00000000)
#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW20_ENABLE (0x00000001)
#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW21 21:21
#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW21_DISABLE (0x00000000)
#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW21_ENABLE (0x00000001)
#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW22 22:22
#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW22_DISABLE (0x00000000)
#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW22_ENABLE (0x00000001)
#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW23 23:23
#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW23_DISABLE (0x00000000)
#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW23_ENABLE (0x00000001)
#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW24 24:24
#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW24_DISABLE (0x00000000)
#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW24_ENABLE (0x00000001)
#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW25 25:25
#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW25_DISABLE (0x00000000)
#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW25_ENABLE (0x00000001)
#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW26 26:26
#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW26_DISABLE (0x00000000)
#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW26_ENABLE (0x00000001)
#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW27 27:27
#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW27_DISABLE (0x00000000)
#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW27_ENABLE (0x00000001)
#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW28 28:28
#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW28_DISABLE (0x00000000)
#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW28_ENABLE (0x00000001)
#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW29 29:29
#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW29_DISABLE (0x00000000)
#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW29_ENABLE (0x00000001)
#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW30 30:30
#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW30_DISABLE (0x00000000)
#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW30_ENABLE (0x00000001)
#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW31 31:31
#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW31_DISABLE (0x00000000)
#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW31_ENABLE (0x00000001)
#define NVC87E_SET_EXT_PACKET_CONTROL (0x00000398)
#define NVC87E_SET_EXT_PACKET_CONTROL_ENABLE 0:0
#define NVC87E_SET_EXT_PACKET_CONTROL_ENABLE_DISABLE (0x00000000)
#define NVC87E_SET_EXT_PACKET_CONTROL_ENABLE_ENABLE (0x00000001)
#define NVC87E_SET_EXT_PACKET_CONTROL_LOCATION 4:4
#define NVC87E_SET_EXT_PACKET_CONTROL_LOCATION_VSYNC (0x00000000)
#define NVC87E_SET_EXT_PACKET_CONTROL_LOCATION_VBLANK (0x00000001)
#define NVC87E_SET_EXT_PACKET_CONTROL_FREQUENCY 8:8
#define NVC87E_SET_EXT_PACKET_CONTROL_FREQUENCY_EVERY_FRAME (0x00000000)
#define NVC87E_SET_EXT_PACKET_CONTROL_FREQUENCY_ONCE (0x00000001)
#define NVC87E_SET_EXT_PACKET_CONTROL_HEADER_OVERRIDE 12:12
#define NVC87E_SET_EXT_PACKET_CONTROL_HEADER_OVERRIDE_DISABLE (0x00000000)
#define NVC87E_SET_EXT_PACKET_CONTROL_HEADER_OVERRIDE_ENABLE (0x00000001)
#define NVC87E_SET_EXT_PACKET_CONTROL_SIZE 27:16
#define NVC87E_SET_EXT_PACKET_DATA (0x0000039C)
#define NVC87E_SET_EXT_PACKET_DATA_DB0 7:0
#define NVC87E_SET_EXT_PACKET_DATA_DB1 15:8
#define NVC87E_SET_EXT_PACKET_DATA_DB2 23:16
#define NVC87E_SET_EXT_PACKET_DATA_DB3 31:24
#define NVC87E_SET_FMT_COEFFICIENT_C00 (0x00000400)
#define NVC87E_SET_FMT_COEFFICIENT_C00_VALUE 20:0
#define NVC87E_SET_FMT_COEFFICIENT_C01 (0x00000404)
#define NVC87E_SET_FMT_COEFFICIENT_C01_VALUE 20:0
#define NVC87E_SET_FMT_COEFFICIENT_C02 (0x00000408)
#define NVC87E_SET_FMT_COEFFICIENT_C02_VALUE 20:0
#define NVC87E_SET_FMT_COEFFICIENT_C03 (0x0000040C)
#define NVC87E_SET_FMT_COEFFICIENT_C03_VALUE 20:0
#define NVC87E_SET_FMT_COEFFICIENT_C10 (0x00000410)
#define NVC87E_SET_FMT_COEFFICIENT_C10_VALUE 20:0
#define NVC87E_SET_FMT_COEFFICIENT_C11 (0x00000414)
#define NVC87E_SET_FMT_COEFFICIENT_C11_VALUE 20:0
#define NVC87E_SET_FMT_COEFFICIENT_C12 (0x00000418)
#define NVC87E_SET_FMT_COEFFICIENT_C12_VALUE 20:0
#define NVC87E_SET_FMT_COEFFICIENT_C13 (0x0000041C)
#define NVC87E_SET_FMT_COEFFICIENT_C13_VALUE 20:0
#define NVC87E_SET_FMT_COEFFICIENT_C20 (0x00000420)
#define NVC87E_SET_FMT_COEFFICIENT_C20_VALUE 20:0
#define NVC87E_SET_FMT_COEFFICIENT_C21 (0x00000424)
#define NVC87E_SET_FMT_COEFFICIENT_C21_VALUE 20:0
#define NVC87E_SET_FMT_COEFFICIENT_C22 (0x00000428)
#define NVC87E_SET_FMT_COEFFICIENT_C22_VALUE 20:0
#define NVC87E_SET_FMT_COEFFICIENT_C23 (0x0000042C)
#define NVC87E_SET_FMT_COEFFICIENT_C23_VALUE 20:0
#define NVC87E_SET_ILUT_CONTROL (0x00000440)
#define NVC87E_SET_ILUT_CONTROL_INTERPOLATE 0:0
#define NVC87E_SET_ILUT_CONTROL_INTERPOLATE_DISABLE (0x00000000)
#define NVC87E_SET_ILUT_CONTROL_INTERPOLATE_ENABLE (0x00000001)
#define NVC87E_SET_ILUT_CONTROL_MIRROR 1:1
#define NVC87E_SET_ILUT_CONTROL_MIRROR_DISABLE (0x00000000)
#define NVC87E_SET_ILUT_CONTROL_MIRROR_ENABLE (0x00000001)
#define NVC87E_SET_ILUT_CONTROL_MODE 3:2
#define NVC87E_SET_ILUT_CONTROL_MODE_SEGMENTED (0x00000000)
#define NVC87E_SET_ILUT_CONTROL_MODE_DIRECT8 (0x00000001)
#define NVC87E_SET_ILUT_CONTROL_MODE_DIRECT10 (0x00000002)
#define NVC87E_SET_ILUT_CONTROL_SIZE 18:8
#define NVC87E_SET_CONTEXT_DMA_ILUT (0x00000444)
#define NVC87E_SET_CONTEXT_DMA_ILUT_HANDLE 31:0
#define NVC87E_SET_OFFSET_ILUT (0x00000448)
#define NVC87E_SET_OFFSET_ILUT_ORIGIN 31:0
#define NVC87E_SET_CSC00CONTROL (0x0000045C)
#define NVC87E_SET_CSC00CONTROL_ENABLE 0:0
#define NVC87E_SET_CSC00CONTROL_ENABLE_DISABLE (0x00000000)
#define NVC87E_SET_CSC00CONTROL_ENABLE_ENABLE (0x00000001)
#define NVC87E_SET_CSC00COEFFICIENT_C00 (0x00000460)
#define NVC87E_SET_CSC00COEFFICIENT_C00_VALUE 20:0
#define NVC87E_SET_CSC00COEFFICIENT_C01 (0x00000464)
#define NVC87E_SET_CSC00COEFFICIENT_C01_VALUE 20:0
#define NVC87E_SET_CSC00COEFFICIENT_C02 (0x00000468)
#define NVC87E_SET_CSC00COEFFICIENT_C02_VALUE 20:0
#define NVC87E_SET_CSC00COEFFICIENT_C03 (0x0000046C)
#define NVC87E_SET_CSC00COEFFICIENT_C03_VALUE 20:0
#define NVC87E_SET_CSC00COEFFICIENT_C10 (0x00000470)
#define NVC87E_SET_CSC00COEFFICIENT_C10_VALUE 20:0
#define NVC87E_SET_CSC00COEFFICIENT_C11 (0x00000474)
#define NVC87E_SET_CSC00COEFFICIENT_C11_VALUE 20:0
#define NVC87E_SET_CSC00COEFFICIENT_C12 (0x00000478)
#define NVC87E_SET_CSC00COEFFICIENT_C12_VALUE 20:0
#define NVC87E_SET_CSC00COEFFICIENT_C13 (0x0000047C)
#define NVC87E_SET_CSC00COEFFICIENT_C13_VALUE 20:0
#define NVC87E_SET_CSC00COEFFICIENT_C20 (0x00000480)
#define NVC87E_SET_CSC00COEFFICIENT_C20_VALUE 20:0
#define NVC87E_SET_CSC00COEFFICIENT_C21 (0x00000484)
#define NVC87E_SET_CSC00COEFFICIENT_C21_VALUE 20:0
#define NVC87E_SET_CSC00COEFFICIENT_C22 (0x00000488)
#define NVC87E_SET_CSC00COEFFICIENT_C22_VALUE 20:0
#define NVC87E_SET_CSC00COEFFICIENT_C23 (0x0000048C)
#define NVC87E_SET_CSC00COEFFICIENT_C23_VALUE 20:0
#define NVC87E_SET_CSC0LUT_CONTROL (0x000004A0)
#define NVC87E_SET_CSC0LUT_CONTROL_INTERPOLATE 0:0
#define NVC87E_SET_CSC0LUT_CONTROL_INTERPOLATE_DISABLE (0x00000000)
#define NVC87E_SET_CSC0LUT_CONTROL_INTERPOLATE_ENABLE (0x00000001)
#define NVC87E_SET_CSC0LUT_CONTROL_MIRROR 1:1
#define NVC87E_SET_CSC0LUT_CONTROL_MIRROR_DISABLE (0x00000000)
#define NVC87E_SET_CSC0LUT_CONTROL_MIRROR_ENABLE (0x00000001)
#define NVC87E_SET_CSC0LUT_CONTROL_ENABLE 4:4
#define NVC87E_SET_CSC0LUT_CONTROL_ENABLE_DISABLE (0x00000000)
#define NVC87E_SET_CSC0LUT_CONTROL_ENABLE_ENABLE (0x00000001)
#define NVC87E_SET_CSC0LUT_SEGMENT_SIZE (0x000004A4)
#define NVC87E_SET_CSC0LUT_SEGMENT_SIZE_IDX 5:0
#define NVC87E_SET_CSC0LUT_SEGMENT_SIZE_VALUE 18:16
#define NVC87E_SET_CSC0LUT_ENTRY (0x000004A8)
#define NVC87E_SET_CSC0LUT_ENTRY_IDX 10:0
#define NVC87E_SET_CSC0LUT_ENTRY_VALUE 31:16
#define NVC87E_SET_CSC01CONTROL (0x000004BC)
#define NVC87E_SET_CSC01CONTROL_ENABLE 0:0
#define NVC87E_SET_CSC01CONTROL_ENABLE_DISABLE (0x00000000)
#define NVC87E_SET_CSC01CONTROL_ENABLE_ENABLE (0x00000001)
#define NVC87E_SET_CSC01COEFFICIENT_C00 (0x000004C0)
#define NVC87E_SET_CSC01COEFFICIENT_C00_VALUE 20:0
#define NVC87E_SET_CSC01COEFFICIENT_C01 (0x000004C4)
#define NVC87E_SET_CSC01COEFFICIENT_C01_VALUE 20:0
#define NVC87E_SET_CSC01COEFFICIENT_C02 (0x000004C8)
#define NVC87E_SET_CSC01COEFFICIENT_C02_VALUE 20:0
#define NVC87E_SET_CSC01COEFFICIENT_C03 (0x000004CC)
#define NVC87E_SET_CSC01COEFFICIENT_C03_VALUE 20:0
#define NVC87E_SET_CSC01COEFFICIENT_C10 (0x000004D0)
#define NVC87E_SET_CSC01COEFFICIENT_C10_VALUE 20:0
#define NVC87E_SET_CSC01COEFFICIENT_C11 (0x000004D4)
#define NVC87E_SET_CSC01COEFFICIENT_C11_VALUE 20:0
#define NVC87E_SET_CSC01COEFFICIENT_C12 (0x000004D8)
#define NVC87E_SET_CSC01COEFFICIENT_C12_VALUE 20:0
#define NVC87E_SET_CSC01COEFFICIENT_C13 (0x000004DC)
#define NVC87E_SET_CSC01COEFFICIENT_C13_VALUE 20:0
#define NVC87E_SET_CSC01COEFFICIENT_C20 (0x000004E0)
#define NVC87E_SET_CSC01COEFFICIENT_C20_VALUE 20:0
#define NVC87E_SET_CSC01COEFFICIENT_C21 (0x000004E4)
#define NVC87E_SET_CSC01COEFFICIENT_C21_VALUE 20:0
#define NVC87E_SET_CSC01COEFFICIENT_C22 (0x000004E8)
#define NVC87E_SET_CSC01COEFFICIENT_C22_VALUE 20:0
#define NVC87E_SET_CSC01COEFFICIENT_C23 (0x000004EC)
#define NVC87E_SET_CSC01COEFFICIENT_C23_VALUE 20:0
#define NVC87E_SET_TMO_CONTROL (0x00000500)
#define NVC87E_SET_TMO_CONTROL_INTERPOLATE 0:0
#define NVC87E_SET_TMO_CONTROL_INTERPOLATE_DISABLE (0x00000000)
#define NVC87E_SET_TMO_CONTROL_INTERPOLATE_ENABLE (0x00000001)
#define NVC87E_SET_TMO_CONTROL_SAT_MODE 3:2
#define NVC87E_SET_TMO_CONTROL_SIZE 18:8
#define NVC87E_SET_TMO_LOW_INTENSITY_ZONE (0x00000508)
#define NVC87E_SET_TMO_LOW_INTENSITY_ZONE_END 29:16
#define NVC87E_SET_TMO_LOW_INTENSITY_VALUE (0x0000050C)
#define NVC87E_SET_TMO_LOW_INTENSITY_VALUE_LIN_WEIGHT 8:0
#define NVC87E_SET_TMO_LOW_INTENSITY_VALUE_NON_LIN_WEIGHT 20:12
#define NVC87E_SET_TMO_LOW_INTENSITY_VALUE_THRESHOLD 31:24
#define NVC87E_SET_TMO_MEDIUM_INTENSITY_ZONE (0x00000510)
#define NVC87E_SET_TMO_MEDIUM_INTENSITY_ZONE_START 13:0
#define NVC87E_SET_TMO_MEDIUM_INTENSITY_ZONE_END 29:16
#define NVC87E_SET_TMO_MEDIUM_INTENSITY_VALUE (0x00000514)
#define NVC87E_SET_TMO_MEDIUM_INTENSITY_VALUE_LIN_WEIGHT 8:0
#define NVC87E_SET_TMO_MEDIUM_INTENSITY_VALUE_NON_LIN_WEIGHT 20:12
#define NVC87E_SET_TMO_MEDIUM_INTENSITY_VALUE_THRESHOLD 31:24
#define NVC87E_SET_TMO_HIGH_INTENSITY_ZONE (0x00000518)
#define NVC87E_SET_TMO_HIGH_INTENSITY_ZONE_START 13:0
#define NVC87E_SET_TMO_HIGH_INTENSITY_VALUE (0x0000051C)
#define NVC87E_SET_TMO_HIGH_INTENSITY_VALUE_LIN_WEIGHT 8:0
#define NVC87E_SET_TMO_HIGH_INTENSITY_VALUE_NON_LIN_WEIGHT 20:12
#define NVC87E_SET_TMO_HIGH_INTENSITY_VALUE_THRESHOLD 31:24
#define NVC87E_SET_CONTEXT_DMA_TMO_LUT (0x00000528)
#define NVC87E_SET_CONTEXT_DMA_TMO_LUT_HANDLE 31:0
#define NVC87E_SET_OFFSET_TMO_LUT (0x0000052C)
#define NVC87E_SET_OFFSET_TMO_LUT_ORIGIN 31:0
#define NVC87E_SET_CSC10CONTROL (0x0000053C)
#define NVC87E_SET_CSC10CONTROL_ENABLE 0:0
#define NVC87E_SET_CSC10CONTROL_ENABLE_DISABLE (0x00000000)
#define NVC87E_SET_CSC10CONTROL_ENABLE_ENABLE (0x00000001)
#define NVC87E_SET_CSC10COEFFICIENT_C00 (0x00000540)
#define NVC87E_SET_CSC10COEFFICIENT_C00_VALUE 20:0
#define NVC87E_SET_CSC10COEFFICIENT_C01 (0x00000544)
#define NVC87E_SET_CSC10COEFFICIENT_C01_VALUE 20:0
#define NVC87E_SET_CSC10COEFFICIENT_C02 (0x00000548)
#define NVC87E_SET_CSC10COEFFICIENT_C02_VALUE 20:0
#define NVC87E_SET_CSC10COEFFICIENT_C03 (0x0000054C)
#define NVC87E_SET_CSC10COEFFICIENT_C03_VALUE 20:0
#define NVC87E_SET_CSC10COEFFICIENT_C10 (0x00000550)
#define NVC87E_SET_CSC10COEFFICIENT_C10_VALUE 20:0
#define NVC87E_SET_CSC10COEFFICIENT_C11 (0x00000554)
#define NVC87E_SET_CSC10COEFFICIENT_C11_VALUE 20:0
#define NVC87E_SET_CSC10COEFFICIENT_C12 (0x00000558)
#define NVC87E_SET_CSC10COEFFICIENT_C12_VALUE 20:0
#define NVC87E_SET_CSC10COEFFICIENT_C13 (0x0000055C)
#define NVC87E_SET_CSC10COEFFICIENT_C13_VALUE 20:0
#define NVC87E_SET_CSC10COEFFICIENT_C20 (0x00000560)
#define NVC87E_SET_CSC10COEFFICIENT_C20_VALUE 20:0
#define NVC87E_SET_CSC10COEFFICIENT_C21 (0x00000564)
#define NVC87E_SET_CSC10COEFFICIENT_C21_VALUE 20:0
#define NVC87E_SET_CSC10COEFFICIENT_C22 (0x00000568)
#define NVC87E_SET_CSC10COEFFICIENT_C22_VALUE 20:0
#define NVC87E_SET_CSC10COEFFICIENT_C23 (0x0000056C)
#define NVC87E_SET_CSC10COEFFICIENT_C23_VALUE 20:0
#define NVC87E_SET_CSC1LUT_CONTROL (0x00000580)
#define NVC87E_SET_CSC1LUT_CONTROL_INTERPOLATE 0:0
#define NVC87E_SET_CSC1LUT_CONTROL_INTERPOLATE_DISABLE (0x00000000)
#define NVC87E_SET_CSC1LUT_CONTROL_INTERPOLATE_ENABLE (0x00000001)
#define NVC87E_SET_CSC1LUT_CONTROL_MIRROR 1:1
#define NVC87E_SET_CSC1LUT_CONTROL_MIRROR_DISABLE (0x00000000)
#define NVC87E_SET_CSC1LUT_CONTROL_MIRROR_ENABLE (0x00000001)
#define NVC87E_SET_CSC1LUT_CONTROL_ENABLE 4:4
#define NVC87E_SET_CSC1LUT_CONTROL_ENABLE_DISABLE (0x00000000)
#define NVC87E_SET_CSC1LUT_CONTROL_ENABLE_ENABLE (0x00000001)
#define NVC87E_SET_CSC1LUT_SEGMENT_SIZE (0x00000584)
#define NVC87E_SET_CSC1LUT_SEGMENT_SIZE_IDX 5:0
#define NVC87E_SET_CSC1LUT_SEGMENT_SIZE_VALUE 18:16
#define NVC87E_SET_CSC1LUT_ENTRY (0x00000588)
#define NVC87E_SET_CSC1LUT_ENTRY_IDX 10:0
#define NVC87E_SET_CSC1LUT_ENTRY_VALUE 31:16
#define NVC87E_SET_CSC11CONTROL (0x0000059C)
#define NVC87E_SET_CSC11CONTROL_ENABLE 0:0
#define NVC87E_SET_CSC11CONTROL_ENABLE_DISABLE (0x00000000)
#define NVC87E_SET_CSC11CONTROL_ENABLE_ENABLE (0x00000001)
#define NVC87E_SET_CSC11COEFFICIENT_C00 (0x000005A0)
#define NVC87E_SET_CSC11COEFFICIENT_C00_VALUE 20:0
#define NVC87E_SET_CSC11COEFFICIENT_C01 (0x000005A4)
#define NVC87E_SET_CSC11COEFFICIENT_C01_VALUE 20:0
#define NVC87E_SET_CSC11COEFFICIENT_C02 (0x000005A8)
#define NVC87E_SET_CSC11COEFFICIENT_C02_VALUE 20:0
#define NVC87E_SET_CSC11COEFFICIENT_C03 (0x000005AC)
#define NVC87E_SET_CSC11COEFFICIENT_C03_VALUE 20:0
#define NVC87E_SET_CSC11COEFFICIENT_C10 (0x000005B0)
#define NVC87E_SET_CSC11COEFFICIENT_C10_VALUE 20:0
#define NVC87E_SET_CSC11COEFFICIENT_C11 (0x000005B4)
#define NVC87E_SET_CSC11COEFFICIENT_C11_VALUE 20:0
#define NVC87E_SET_CSC11COEFFICIENT_C12 (0x000005B8)
#define NVC87E_SET_CSC11COEFFICIENT_C12_VALUE 20:0
#define NVC87E_SET_CSC11COEFFICIENT_C13 (0x000005BC)
#define NVC87E_SET_CSC11COEFFICIENT_C13_VALUE 20:0
#define NVC87E_SET_CSC11COEFFICIENT_C20 (0x000005C0)
#define NVC87E_SET_CSC11COEFFICIENT_C20_VALUE 20:0
#define NVC87E_SET_CSC11COEFFICIENT_C21 (0x000005C4)
#define NVC87E_SET_CSC11COEFFICIENT_C21_VALUE 20:0
#define NVC87E_SET_CSC11COEFFICIENT_C22 (0x000005C8)
#define NVC87E_SET_CSC11COEFFICIENT_C22_VALUE 20:0
#define NVC87E_SET_CSC11COEFFICIENT_C23 (0x000005CC)
#define NVC87E_SET_CSC11COEFFICIENT_C23_VALUE 20:0
#define NVC87E_SET_CLAMP_RANGE (0x000005D0)
#define NVC87E_SET_CLAMP_RANGE_LOW 15:0
#define NVC87E_SET_CLAMP_RANGE_HIGH 31:16
#define NVC87E_SW_RESERVED(b) (0x000005D4 + (b)*0x00000004)
#define NVC87E_SW_RESERVED_VALUE 31:0
#ifdef __cplusplus
}; /* extern "C" */
#endif
#endif // _clC87e_h

4
src/common/sdk/nvidia/inc/class/clc8b5.h
View File

@@ -30,9 +30,11 @@
#define NVC8B5_SET_SEMAPHORE_B (0x00000244)
#define NVC8B5_SET_SEMAPHORE_B_LOWER 31:0
#define NVC8B5_SET_SEMAPHORE_PAYLOAD (0x00000248)
#define NVC8B5_SET_SRC_PHYS_MODE (0x00000260)
#define NVC8B5_SET_SRC_PHYS_MODE_TARGET 1:0
#define NVC8B5_SET_SRC_PHYS_MODE_TARGET_LOCAL_FB (0x00000000)
#define NVC8B5_SET_SRC_PHYS_MODE_TARGET_COHERENT_SYSMEM (0x00000001)
#define NVC8B5_SET_SRC_PHYS_MODE_TARGET_NONCOHERENT_SYSMEM (0x00000002)
#define NVC8B5_SET_SRC_PHYS_MODE_TARGET_PEERMEM (0x00000003)
#define NVC8B5_SET_SRC_PHYS_MODE_PEER_ID 8:6
#define NVC8B5_SET_SRC_PHYS_MODE_FLA 9:9
@@ -40,6 +42,7 @@
#define NVC8B5_SET_DST_PHYS_MODE_TARGET 1:0
#define NVC8B5_SET_DST_PHYS_MODE_TARGET_LOCAL_FB (0x00000000)
#define NVC8B5_SET_DST_PHYS_MODE_TARGET_COHERENT_SYSMEM (0x00000001)
#define NVC8B5_SET_DST_PHYS_MODE_TARGET_NONCOHERENT_SYSMEM (0x00000002)
#define NVC8B5_SET_DST_PHYS_MODE_TARGET_PEERMEM (0x00000003)
#define NVC8B5_LAUNCH_DMA (0x00000300)
#define NVC8B5_LAUNCH_DMA_DATA_TRANSFER_TYPE 1:0
@@ -66,6 +69,7 @@
#define NVC8B5_LAUNCH_DMA_REMAP_ENABLE_FALSE (0x00000000)
#define NVC8B5_LAUNCH_DMA_REMAP_ENABLE_TRUE (0x00000001)
#define NVC8B5_LAUNCH_DMA_SRC_TYPE 12:12
#define NVC8B5_LAUNCH_DMA_SRC_TYPE_VIRTUAL (0x00000000)
#define NVC8B5_LAUNCH_DMA_SRC_TYPE_PHYSICAL (0x00000001)
#define NVC8B5_LAUNCH_DMA_DST_TYPE 13:13
#define NVC8B5_LAUNCH_DMA_DST_TYPE_VIRTUAL (0x00000000)

17
src/common/sdk/nvidia/inc/class/clc97dswspare.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2023, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2023-2025, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -38,4 +38,19 @@
#define NVC97D_HEAD_SET_SW_SPARE_A_CODE_VPLL_REF_NO_PREF (0x00000000)
#define NVC97D_HEAD_SET_SW_SPARE_A_CODE_VPLL_REF_QSYNC (0x00000001)
//
// DRR (Dynamic Refresh Rate) is a power saving feature that lowers the refresh
// rate when a high flip rate is not required. A modeset is required in order
// to change the target refresh rate for DRR purposes. Such a modeset
// (indicated by the DRR_MODESET bit) does not change any IMP-relevant
// parameters except back porch (and vertical total), so IMP can optimize such
// modesets by, for example, skipping disablement of mclk switch.
//
// If any head has the DRR_MODESET bit set, no other head that is changing is
// allowed to execute a non-DRR transition as part of the same modeset.
//
#define NVC97D_HEAD_SET_SW_RESERVED_DRR_MODESET 31:31
#define NVC97D_HEAD_SET_SW_RESERVED_DRR_MODESET_FALSE (0x00000000)
#define NVC97D_HEAD_SET_SW_RESERVED_DRR_MODESET_TRUE (0x00000001)
#endif // _clc97d_sw_spare_h_

30
src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000gpu.h
View File

@@ -523,36 +523,6 @@ typedef struct NV0000_CTRL_GPU_GET_VIDEO_LINKS_PARAMS {
/*
* NV0000_CTRL_CMD_GPU_GET_SVM_SIZE
*
* This command is used to get the SVM size.
*
* gpuId
* This parameter uniquely identifies the GPU whose associated
* SVM size is to be returned. The value of this field must
* match one of those in the table returned by
* NV0000_CTRL_CMD_GPU_GET_ATTACHED_IDS
*
* SvmSize
* SVM size is returned in this.
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_INVALID_STATE
*
*/
#define NV0000_CTRL_CMD_GPU_GET_SVM_SIZE (0x240U) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_GET_SVM_SIZE_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_GPU_GET_SVM_SIZE_PARAMS_MESSAGE_ID (0x40U)
typedef struct NV0000_CTRL_GPU_GET_SVM_SIZE_PARAMS {
NvU32 gpuId;
NvU32 svmSize;
} NV0000_CTRL_GPU_GET_SVM_SIZE_PARAMS;
/*
* NV0000_CTRL_CMD_GPU_GET_UUID_INFO
*

72
src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000system.h
View File

@@ -382,6 +382,7 @@ typedef struct NV0000_CTRL_SYSTEM_GET_CPU_INFO_PARAMS {
* This parameter specifies NV0000_CTRL_SYSTEM_CHIPSET_FLAG_XXX flags:
* _HAS_RESIZABLE_BAR_ISSUE_YES: Chipset where the use of resizable BAR1
* should be disabled - bug 3440153
* _BAR1_UNALIGNED_ACCESS_YES: unaligned acccess in BAR1 is allowed.
*
* Possible status values returned are:
* NV_OK
@@ -420,6 +421,10 @@ typedef struct NV0000_CTRL_SYSTEM_GET_CHIPSET_INFO_PARAMS {
#define NV0000_CTRL_SYSTEM_CHIPSET_FLAG_HAS_RESIZABLE_BAR_ISSUE_NO (0x00000000U)
#define NV0000_CTRL_SYSTEM_CHIPSET_FLAG_HAS_RESIZABLE_BAR_ISSUE_YES (0x00000001U)
#define NV0000_CTRL_SYSTEM_CHIPSET_FLAG_BAR1_UNALIGNED_ACCESS 1:1
#define NV0000_CTRL_SYSTEM_CHIPSET_FLAG_BAR1_UNALIGNED_ACCESS_NO (0x00000000U)
#define NV0000_CTRL_SYSTEM_CHIPSET_FLAG_BAR1_UNALIGNED_ACCESS_YES (0x00000001U)
/*
@@ -657,68 +662,6 @@ typedef struct NV0000_CTRL_SYSTEM_DEBUG_RMMSG_CTRL_PARAMS {
NvU8 data[NV0000_CTRL_SYSTEM_DEBUG_RMMSG_SIZE];
} NV0000_CTRL_SYSTEM_DEBUG_RMMSG_CTRL_PARAMS;
/*
* NV0000_CTRL_SYSTEM_HWBC_INFO
*
* This structure contains information about the HWBC (BR04) specified by
* hwbcId.
*
* hwbcId
* This field specifies the HWBC ID.
* firmwareVersion
* This field returns the version of the firmware on the HWBC (BR04), if
* present. This is a packed binary number of the form 0x12345678, which
* corresponds to a firmware version of 12.34.56.78.
* subordinateBus
* This field returns the subordinate bus number of the HWBC (BR04).
* secondaryBus
* This field returns the secondary bus number of the HWBC (BR04).
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
*/
typedef struct NV0000_CTRL_SYSTEM_HWBC_INFO {
NvU32 hwbcId;
NvU32 firmwareVersion;
NvU32 subordinateBus;
NvU32 secondaryBus;
} NV0000_CTRL_SYSTEM_HWBC_INFO;
#define NV0000_CTRL_SYSTEM_HWBC_INVALID_ID (0xFFFFFFFFU)
/*
* NV0000_CTRL_CMD_SYSTEM_GET_HWBC_INFO
*
* This command returns information about all Hardware Broadcast (HWBC)
* devices present in the system that are BR04s. To get the complete
* list of HWBCs in the system, all GPUs present in the system must be
* initialized. See the description of NV0000_CTRL_CMD_GPU_ATTACH_IDS to
* accomplish this.
*
* hwbcInfo
* This field is an array of NV0000_CTRL_SYSTEM_HWBC_INFO structures into
* which HWBC information is placed. There is one entry for each HWBC
* present in the system. Valid entries are contiguous, invalid entries
* have the hwbcId equal to NV0000_CTRL_SYSTEM_HWBC_INVALID_ID. If no HWBC
* is present in the system, all the entries would be marked invalid, but
* the return value would still be SUCCESS.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
*/
#define NV0000_CTRL_CMD_SYSTEM_GET_HWBC_INFO (0x124U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_HWBC_INFO_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_SYSTEM_MAX_HWBCS (0x00000080U)
#define NV0000_CTRL_SYSTEM_GET_HWBC_INFO_PARAMS_MESSAGE_ID (0x24U)
typedef struct NV0000_CTRL_SYSTEM_GET_HWBC_INFO_PARAMS {
NV0000_CTRL_SYSTEM_HWBC_INFO hwbcInfo[NV0000_CTRL_SYSTEM_MAX_HWBCS];
} NV0000_CTRL_SYSTEM_GET_HWBC_INFO_PARAMS;
/*
* NV0000_CTRL_CMD_SYSTEM_GPS_CONTROL
*
@@ -2192,6 +2135,11 @@ typedef struct NV0000_CTRL_SYSTEM_NVPCF_GET_POWER_MODE_INFO_PARAMS {
*/
NvU32 dcTspLongTimescaleLimitmA;
/*
* The long timescale limit override.
*/
NvU32 dcTspLongTimescaleLimitOverridemA;
/*
* This is the active arbitrated short timescale limit provided by Qboost and
* honored by RM/PMU

43
src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073dp.h
View File

@@ -3655,4 +3655,47 @@ typedef struct NV0073_CTRL_STUFF_DUMMY_SYMBOL_WAR_PARAMS {
#define NV0073_CTRL_CMD_STUFF_DUMMY_SYMBOL_WAR (0x73138eU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_STUFF_DUMMY_SYMBOL_WAR_PARAMS_MESSAGE_ID" */
/*
* NV0073_CTRL_CMD_GET_USB_DPIN_ADAPTER_INFO
*
* Get USB4 DP_IN Adapter number from RM
*
* subDeviceInstance
* This parameter specifies the subdevice instance within the
* NV04_DISPLAY_COMMON parent device to which the operation should be
* directed. This parameter must specify a value between zero and the
* total number of subdevices within the parent device. This parameter
* should be set to zero for default behavior.
* displayId
* This parameter specifies the ID of the display for which the control
* is being issued. The display ID must be valid.
* driverId
* This parameter uniquely identifies the host router in the system.
* dpInAdapterNumber
* DP_IN adapter number that belongs to the displayId
* topologyId
* Unique number to identify the USB4 router topology
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_PARAM_STRUCT
* NV_ERR_INVALID_ARGUMENT
*/
#define NV0073_CTRL_DP_USB_TOPOLOGY_ID_LENGTH 5
typedef struct NV0073_CTRL_DP_USB4_INFO {
NvU8 driverId;
NvU8 dpInAdapterNumber;
NvU8 topologyId[NV0073_CTRL_DP_USB_TOPOLOGY_ID_LENGTH];
} NV0073_CTRL_DP_USB4_INFO;
#define NV0073_CTRL_CMD_GET_USB_DPIN_ADAPTER_INFO_PARAMS_MESSAGE_ID (0x8FU)
typedef struct NV0073_CTRL_CMD_GET_USB_DPIN_ADAPTER_INFO_PARAMS {
NvU32 subDeviceInstance;
NvU32 displayId;
NV0073_CTRL_DP_USB4_INFO usb4Info;
} NV0073_CTRL_CMD_GET_USB_DPIN_ADAPTER_INFO_PARAMS;
#define NV0073_CTRL_CMD_GET_USB_DPIN_ADAPTER_INFO (0x73138fU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_GET_USB_DPIN_ADAPTER_INFO_PARAMS_MESSAGE_ID" */
/* _ctrl0073dp_h_ */

1027
src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073specific.h
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File diff suppressed because it is too large Load Diff

169
src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073system.h
View File

@@ -849,6 +849,175 @@ typedef struct NV0073_CTRL_SYSTEM_ACPI_SUBSYSTEM_ACTIVATED_PARAMS {
#define NV0073_CTRL_CMD_SYSTEM_ACPI_SUBSYSTEM_ACTIVATED (0x730117U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_SYSTEM_ACPI_SUBSYSTEM_ACTIVATED_PARAMS_MESSAGE_ID" */
/*
* To support RMCTRLs for BOARDOBJGRP_E255, we were required to increase the
* XAPI limit to 16K. It was observed that XP does NOT allow the static array
* size greater then 10K and this was causing the DVS failure. So we are using
* the OLD XAPI value i.e. 4K for NV0073_CTRL_SYSTEM_SRM_BUFFER_MAX while
* internally we are using the new updated XAPI value i.e. 16K.
*/
#define XAPI_ENVELOPE_MAX_PAYLOAD_SIZE_OLD 4096U
/*
* NV0073_CTRL_SYSTEM_SRM_CHUNK
*
* Several control commands require an SRM, which may be larger than the
* available buffer. Therefore, this structure is used to transfer the needed
* data.
*
* startByte
* Index of the byte in the SRM buffer at which the current chunk of data
* starts. If this value is 0, it indicates the start of a new SRM. A
* value other than 0 indicates additional data for an SRM.
* numBytes
* Size in bytes of the current chunk of data.
* totalBytes
* Size in bytes of the entire SRM.
* srmBuffer
* Buffer containing the current chunk of SRM data.
*/
/* Set max SRM size to the XAPI max, minus some space for other fields */
#define NV0073_CTRL_SYSTEM_SRM_BUFFER_MAX (0xe00U) /* finn: Evaluated from "(XAPI_ENVELOPE_MAX_PAYLOAD_SIZE_OLD - 512)" */
typedef struct NV0073_CTRL_SYSTEM_SRM_CHUNK {
NvU32 startByte;
NvU32 numBytes;
NvU32 totalBytes;
/* C form: NvU8 srmBuffer[NV0073_CTRL_SYSTEM_SRM_BUFFER_MAX]; */
NvU8 srmBuffer[NV0073_CTRL_SYSTEM_SRM_BUFFER_MAX];
} NV0073_CTRL_SYSTEM_SRM_CHUNK;
/*
* NV0073_CTRL_CMD_SYSTEM_VALIDATE_SRM
*
* Instructs the RM to validate the SRM for use by HDCP revocation. The SRM
* may be larger than the buffer provided by the API. In that case, the SRM is
* sent in chunks no larger than NV0073_CTRL_SYSTEM_SRM_BUFFER_MAX bytes.
*
* Upon completion of the validation, which is an asynchronous operation, the
* client will receive a <PLACE_HOLDER_EVENT> event. Alternatively, the client
* may poll for completion of SRM validation via
* NV0073_CTRL_CMD_SYSTEM_GET_SRM_STATUS.
*
* subDeviceInstance
* This parameter specifies the subdevice instance within the
* NV04_DISPLAY_COMMON parent device to which the operation should be
* directed. This parameter must specify a value between zero and the
* total number of subdevices within the parent device. This parameter
* should be set to zero for default behavior.
* srm
* A chunk of the SRM.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_NOT_SUPPORTED
* NV_ERR_NOT_READY
* NV_ERR_INVALID_ARGUMENT
* NV_WARN_MORE_PROCESSING_REQUIRED
* NV_ERR_INSUFFICIENT_RESOURCES
*/
#define NV0073_CTRL_CMD_SYSTEM_VALIDATE_SRM (0x730118U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_SYSTEM_VALIDATE_SRM_PARAMS_MESSAGE_ID" */
#define NV0073_CTRL_SYSTEM_VALIDATE_SRM_PARAMS_MESSAGE_ID (0x18U)
typedef struct NV0073_CTRL_SYSTEM_VALIDATE_SRM_PARAMS {
NvU32 subDeviceInstance;
NV0073_CTRL_SYSTEM_SRM_CHUNK srm;
} NV0073_CTRL_SYSTEM_VALIDATE_SRM_PARAMS;
/*
* NV0073_CTRL_CMD_SYSTEM_GET_SRM_STATUS
*
* Retrieves the status of the request to validate the SRM. If a request to
* validate an SRM is still pending, NV_ERR_NOT_READY will be
* returned and the status will not be updated.
*
* subDeviceInstance
* This parameter specifies the subdevice instance within the
* NV04_DISPLAY_COMMON parent device to which the operation should be
* directed. This parameter must specify a value between zero and the
* total number of subdevices within the parent device. This parameter
* should be set to zero for default behavior.
* status
* Result of the last SRM validation request.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_NOT_SUPPORTED
* NV_ERR_NOT_READY
*/
#define NV0073_CTRL_CMD_SYSTEM_GET_SRM_STATUS (0x730119U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_SYSTEM_GET_SRM_STATUS_PARAMS_MESSAGE_ID" */
typedef enum NV0073_CTRL_SYSTEM_SRM_STATUS {
NV0073_CTRL_SYSTEM_SRM_STATUS_OK = 0, // Validation succeeded
NV0073_CTRL_SYSTEM_SRM_STATUS_FAIL = 1, // Validation request failed
NV0073_CTRL_SYSTEM_SRM_STATUS_BAD_FORMAT = 2, // Bad SRM format
NV0073_CTRL_SYSTEM_SRM_STATUS_INVALID = 3, // Bad SRM signature
} NV0073_CTRL_SYSTEM_SRM_STATUS;
#define NV0073_CTRL_SYSTEM_GET_SRM_STATUS_PARAMS_MESSAGE_ID (0x19U)
typedef struct NV0073_CTRL_SYSTEM_GET_SRM_STATUS_PARAMS {
NvU32 subDeviceInstance;
NvU32 status;
} NV0073_CTRL_SYSTEM_GET_SRM_STATUS_PARAMS;
/*
* NV0073_CTRL_CMD_SYSTEM_HDCP_REVOCATION_CHECK
*
* Performs the HDCP revocation process. Given the supplied SRM, all attached
* devices will be checked to see if they are on the revocation list or not.
*
* srm
* The SRM to do the revocation check against. For SRMs larger than
* NV0073_CTRL_SYSTEM_SRM_BUFFER_MAX, the caller will need to break up the
* SRM into chunks and make multiple calls.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_NOT_SUPPORTED
* NV_ERR_NOT_READY
* NV_ERR_INVALID_ARGUMENT
* NV_WARN_MORE_PROCESSING_REQUIRED
* NV_ERR_INSUFFICIENT_RESOURCES
*/
#define NV0073_CTRL_CMD_SYSTEM_HDCP_REVOCATION_CHECK (0x73011bU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_SYSTEM_HDCP_REVOCATE_PARAMS_MESSAGE_ID" */
#define NV0073_CTRL_SYSTEM_HDCP_REVOCATE_PARAMS_MESSAGE_ID (0x1BU)
typedef struct NV0073_CTRL_SYSTEM_HDCP_REVOCATE_PARAMS {
NV0073_CTRL_SYSTEM_SRM_CHUNK srm;
} NV0073_CTRL_SYSTEM_HDCP_REVOCATE_PARAMS;
/*
* NV0073_CTRL_CMD_UPDATE_SRM
*
* Updates the SRM used by RM for HDCP revocation checks. The SRM must have
* been previously validated as authentic.
*
* srm
* The SRM data. For SRMs larger than NV0073_CTRL_SYSTEM_SRM_BUFFER_MAX,
* the caller will need to break up the SRM into chunks and make multiple
* calls.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_NOT_SUPPORTED
* NV_ERR_NOT_READY
* NV_ERR_INVALID_ARGUMENT
* NV_WARN_MORE_PROCESSING_REQUIRED
* NV_ERR_INSUFFICIENT_RESOURCES
*/
#define NV0073_CTRL_CMD_SYSTEM_UPDATE_SRM (0x73011cU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_SYSTEM_UPDATE_SRM_PARAMS_MESSAGE_ID" */
#define NV0073_CTRL_SYSTEM_UPDATE_SRM_PARAMS_MESSAGE_ID (0x1CU)
typedef struct NV0073_CTRL_SYSTEM_UPDATE_SRM_PARAMS {
NV0073_CTRL_SYSTEM_SRM_CHUNK srm;
} NV0073_CTRL_SYSTEM_UPDATE_SRM_PARAMS;
/*
* NV0073_CTRL_SYSTEM_CONNECTOR_INFO

29
src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080bif.h
View File

@@ -77,31 +77,6 @@ typedef struct NV0080_CTRL_BIF_RESET_PARAMS {
/*
* NV0080_CTRL_BIF_SET_ASPM_FEATURE
*
* aspmFeatureSupported
* ASPM feature override by client
*
* Possible status values returned are:
* NV_OK
*/
#define NV0080_CTRL_CMD_BIF_SET_ASPM_FEATURE (0x800104) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_BIF_INTERFACE_ID << 8) | NV0080_CTRL_BIF_SET_ASPM_FEATURE_PARAMS_MESSAGE_ID" */
#define NV0080_CTRL_BIF_SET_ASPM_FEATURE_PARAMS_MESSAGE_ID (0x4U)
typedef struct NV0080_CTRL_BIF_SET_ASPM_FEATURE_PARAMS {
NvU32 aspmFeatureSupported;
} NV0080_CTRL_BIF_SET_ASPM_FEATURE_PARAMS;
#define NV0080_CTRL_BIF_ASPM_FEATURE_DT_L0S 0:0
#define NV0080_CTRL_BIF_ASPM_FEATURE_DT_L0S_ENABLED 0x000000001
#define NV0080_CTRL_BIF_ASPM_FEATURE_DT_L0S_DISABLED 0x000000000
#define NV0080_CTRL_BIF_ASPM_FEATURE_DT_L1 1:1
#define NV0080_CTRL_BIF_ASPM_FEATURE_DT_L1_ENABLED 0x000000001
#define NV0080_CTRL_BIF_ASPM_FEATURE_DT_L1_DISABLED 0x000000000
/*
* NV0080_CTRL_BIF_ASPM_CYA_UPDATE
*
@@ -113,7 +88,7 @@ typedef struct NV0080_CTRL_BIF_SET_ASPM_FEATURE_PARAMS {
* NV_OK
*/
#define NV0080_CTRL_CMD_BIF_ASPM_CYA_UPDATE (0x800105) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_BIF_INTERFACE_ID << 8) | NV0080_CTRL_BIF_ASPM_CYA_UPDATE_PARAMS_MESSAGE_ID" */
#define NV0080_CTRL_CMD_BIF_ASPM_CYA_UPDATE (0x800105) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_BIF_INTERFACE_ID << 8) | NV0080_CTRL_BIF_ASPM_CYA_UPDATE_PARAMS_MESSAGE_ID" */
#define NV0080_CTRL_BIF_ASPM_CYA_UPDATE_PARAMS_MESSAGE_ID (0x5U)
@@ -123,7 +98,7 @@ typedef struct NV0080_CTRL_BIF_ASPM_CYA_UPDATE_PARAMS {
} NV0080_CTRL_BIF_ASPM_CYA_UPDATE_PARAMS;
/*
* NV0080_CTRL_BIF_ASPM_FEATURE
* NV0080_CTRL_CMD_BIF_GET_PCIE_POWER_CONTROL_MASK
*
* pciePowerControlMask
* pciePowerControlIdentifiedKeyOrder

32
src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080dma.h
View File

@@ -715,36 +715,6 @@ typedef struct NV0080_CTRL_DMA_UPDATE_PDE_2_PARAMS {
#define NV0080_CTRL_DMA_UPDATE_PDE_2_FLAGS_SPARSE_FALSE (0x00000000U)
#define NV0080_CTRL_DMA_UPDATE_PDE_2_FLAGS_SPARSE_TRUE (0x00000001U)
/*
* NV0080_CTRL_DMA_ENABLE_PRIVILEGED_RANGE
* This interface will create a corresponding privileged
* kernel address space that will mirror user space allocations in this
* VASPACE.
* The user can either pass a FERMI_VASPACE_A handle or RM will use the
* vaspace associated with the client/device if hVaspace is passed as
* NULL.
* Once this property is set, the user will not be able to make allocations
* from the top most PDE of this address space.
*
* The user is expected to call this function as soon as he has created
* the device/Vaspace object. If the user has already made VA allocations
* in this vaspace then this call will return a failure
* (NV_ERR_INVALID_STATE).
* The Vaspace should have no VA allocations when this call is made.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_INVALID_STATE
*/
#define NV0080_CTRL_DMA_ENABLE_PRIVILEGED_RANGE (0x801810U) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_DMA_INTERFACE_ID << 8) | NV0080_CTRL_DMA_ENABLE_PRIVILEGED_RANGE_PARAMS_MESSAGE_ID" */
#define NV0080_CTRL_DMA_ENABLE_PRIVILEGED_RANGE_PARAMS_MESSAGE_ID (0x10U)
typedef struct NV0080_CTRL_DMA_ENABLE_PRIVILEGED_RANGE_PARAMS {
NvHandle hVASpace;
} NV0080_CTRL_DMA_ENABLE_PRIVILEGED_RANGE_PARAMS;
/*
* NV0080_CTRL_DMA_SET_DEFAULT_VASPACE
* This is a special control call provided for KMD to use.
@@ -769,7 +739,7 @@ typedef struct NV0080_CTRL_DMA_ENABLE_PRIVILEGED_RANGE_PARAMS {
* NV_ERR_INVALID_STATE
*
*/
#define NV0080_CTRL_DMA_SET_DEFAULT_VASPACE (0x801812U) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_DMA_INTERFACE_ID << 8) | NV0080_CTRL_DMA_SET_DEFAULT_VASPACE_PARAMS_MESSAGE_ID" */
#define NV0080_CTRL_DMA_SET_DEFAULT_VASPACE (0x801812U) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_DMA_INTERFACE_ID << 8) | NV0080_CTRL_DMA_SET_DEFAULT_VASPACE_PARAMS_MESSAGE_ID" */
#define NV0080_CTRL_DMA_SET_DEFAULT_VASPACE_PARAMS_MESSAGE_ID (0x12U)

5
src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080gr.h
View File

@@ -160,13 +160,14 @@ typedef NVXXXX_CTRL_XXX_INFO NV0080_CTRL_GR_INFO;
#define NV0080_CTRL_GR_INFO_INDEX_LITTER_MIN_SUBCTX_PER_SMC_ENG (0x00000037)
#define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_GPCS_PER_DIELET (0x00000038)
#define NV0080_CTRL_GR_INFO_INDEX_LITTER_MAX_NUM_SMC_ENGINES_PER_DIELET (0x00000039)
#define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_CPC_PER_GPC (0x0000003A)
/* When adding a new INDEX, please update MAX_SIZE accordingly
* NOTE: 0080 functionality is merged with 2080 functionality, so this max size
* reflects that.
*/
#define NV0080_CTRL_GR_INFO_INDEX_MAX (0x00000039)
#define NV0080_CTRL_GR_INFO_MAX_SIZE (0x3a) /* finn: Evaluated from "(NV0080_CTRL_GR_INFO_INDEX_MAX + 1)" */
#define NV0080_CTRL_GR_INFO_INDEX_MAX (0x0000003A)
#define NV0080_CTRL_GR_INFO_MAX_SIZE (0x3b) /* finn: Evaluated from "(NV0080_CTRL_GR_INFO_INDEX_MAX + 1)" */
/*
* NV0080_CTRL_CMD_GR_GET_INFO

2
src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080msenc.h
View File

@@ -68,7 +68,7 @@ typedef struct NV0080_CTRL_MSENC_GET_CAPS_PARAMS {
/* size in bytes of MSENC caps table */
#define NV0080_CTRL_MSENC_CAPS_TBL_SIZE 5
#define NV0080_CTRL_MSENC_CAPS_TBL_SIZE 6
/*
* NV0080_CTRL_CMD_MSENC_GET_CAPS_V2

39
src/common/sdk/nvidia/inc/ctrl/ctrl00de.h
View File

@@ -56,4 +56,43 @@ typedef struct NV00DE_CTRL_REQUEST_DATA_POLL_PARAMS {
NV_DECLARE_ALIGNED(NvU64 polledDataMask, 8);
} NV00DE_CTRL_REQUEST_DATA_POLL_PARAMS;
#define NV00DE_RUSD_POLLING_INTERVAL_MIN 100
/*
* NV00DE_CTRL_CMD_REQUEST_POLL_INTERVAL
*
* @brief Privileged control to set RUSD polling interval.
* Valid interval is between NV00DE_RUSD_POLLING_INTERVAL_MIN and
* the default value (decided by SKU and can be overriden by regkey).
* A 0 polling interval is a special value that resets the interval for
* this RUSD instance to the default value.
* Polling interval less than NV00DE_RUSD_POLLING_INTERVAL_MIN is
* invalid. Polling interval greater than the default value is considered
* a reset to default value as well. The reason is that a polling interval
* request from client is considered satisfied as long as RUSD polls more
* frequently than the request. The clients do not need to know the
* default or actual frequency that RUSD is running. Hence, we don't
* return an error when client requests a polling frequency higher than
* the default value.
*
* RUSD will poll at the minimum of all requested polling intervals that
* are valid.
*
* The polling interval can change when:
* 1. A client requests a polling interval
* 2. A client is freed
*
* @param[in] pollingIntervalMs
*
* @return NV_OK on success
* NV_ERR_ otherwise
*/
#define NV00DE_CTRL_CMD_REQUEST_POLL_INTERVAL (0xde0002U) /* finn: Evaluated from "(FINN_RM_USER_SHARED_DATA_INTERFACE_ID << 8) | NV00DE_CTRL_REQUEST_POLL_INTERVAL_PARAM_MESSAGE_ID" */
#define NV00DE_CTRL_REQUEST_POLL_INTERVAL_PARAM_MESSAGE_ID (0x2U)
typedef struct NV00DE_CTRL_REQUEST_POLL_INTERVAL_PARAM {
NvU32 pollingIntervalMs;
} NV00DE_CTRL_REQUEST_POLL_INTERVAL_PARAM;
/* _ctrl00de.h_ */

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