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This commit is contained in:
Maneet Singh
2025-12-02 15:32:25 -08:00
parent 2af9f1f0f7
commit a5bfb10e75
954 changed files with 421883 additions and 408177 deletions
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8
src/nvidia/inc/kernel/gpu/error_cont.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2021-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2021-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -175,9 +175,9 @@ typedef struct _NV_ERROR_CONT_LOCATION
"MMU", \
"GCC", \
"CTXSW", \
"PCIE", \
"PCIE", \
"PCIE", \
"PCIE Egress", \
"PCIE Ingress", \
"PCIE Ingress", \
"PMU", \
"SEC2", \
"GSP", \

3
src/nvidia/inc/kernel/gpu/gpu_child_list.h
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@@ -294,13 +294,12 @@
#if GPU_CHILD_MODULE(NVJPG)
GPU_CHILD_MULTI_INST( OBJNVJPG, GPU_GET_NVJPG, GPU_MAX_NVJPGS, NV_FALSE, pNvjpg )
#endif
#if RMCFG_MODULE_KERNEL_FSP && GPU_CHILD_MODULE(KERNEL_FSP)
#if GPU_CHILD_MODULE(KERNEL_FSP)
GPU_CHILD_SINGLE_INST( KernelFsp, GPU_GET_KERNEL_FSP, 1, NV_TRUE, pKernelFsp )
#endif
#if RMCFG_MODULE_SPDM && GPU_CHILD_MODULE(SPDM)
GPU_CHILD_SINGLE_INST( Spdm, GPU_GET_SPDM, 1, NV_TRUE, pSpdm )
#endif
#if RMCFG_MODULE_CONF_COMPUTE && GPU_CHILD_MODULE(CONF_COMPUTE)
GPU_CHILD_SINGLE_INST( ConfidentialCompute, GPU_GET_CONF_COMPUTE, 1, NV_TRUE, pConfCompute )
#endif

15
src/nvidia/inc/kernel/gpu/gpu_shared_data_map.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2022-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2022-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -41,8 +41,9 @@ typedef struct GpuSharedDataMap {
NvU64 lastPolledDataMask;
NvU32 processId;
NvU32 pollingRegistryOverride;
NvU32 pollingFrequencyMs;
NvBool bPollFrequencyOverridden;
NvU32 defaultPollingIntervalMs;
NvU32 pollingIntervalMs;
NvBool bPollIntervalOverridden;
TMR_EVENT *pRusdRefreshTmrEvent;
@@ -73,5 +74,13 @@ void gpushareddataWriteFinish_INTERNAL(OBJGPU *pGpu, NvU64 offset);
#define gpushareddataWriteFinish(pGpu, field) \
gpushareddataWriteFinish_INTERNAL(pGpu, NV_OFFSETOF(NV00DE_SHARED_DATA, field))
/*!
* @brief RUSD settings data
*/
typedef struct
{
NvU64 permanentPolledDataMask;
} GPU_DB_RUSD_SETTINGS;
#endif /* GPU_SHARED_DATA_MAP_H */

7
src/nvidia/inc/kernel/gpu/gpu_timeout.h
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@@ -79,6 +79,13 @@ typedef struct
volatile NvBool bScaled;
volatile NvU32 defaultus; //!< Default timeout in us
volatile NvU32 defaultResetus; //!< Default timeout reset value in us
//
// Default timeout reset value in Us for the reset FSM state transitions
// between ASSERT -> ASSERTED and DEASSERT -> DEASSERTED.
// This is for presilicon test only.
//
volatile NvBool bDefaultResetFSMStateTransitionOverridden;
volatile NvU32 defaultResetFSMStateTransitionUs;
NvU32 defaultFlags; //!< Default timeout mode
NvU32 scale; //!< Emulation/Simulation multiplier
OBJGPU *pGpu;

5
src/nvidia/inc/kernel/gpu/gpu_uuid.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2018-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2018-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -42,12 +42,15 @@ NV_STATUS nvGenerateGpuUuid(NvU16 chipId, NvU64 pdi, NvUuid *pUuid);
NV_STATUS nvGenerateSmcUuid(NvU16 chipId, NvU64 pdi,
NvU32 swizzId, NvU32 syspipeId, NvUuid *pUuid);
NV_STATUS nvGenerateUgpuUuid(NvU16 chipId, NvU32 ugpugId, NvU64 pdi, NvUuid *pUuid);
// 'G' 'P' 'U' '-'(x5), '\0x0', extra = 9
#define NV_UUID_STR_LEN ((NV_UUID_LEN << 1) + 9)
#define RM_UUID_PREFIX_GPU 0U
#define RM_UUID_PREFIX_MIG 1U
#define RM_UUID_PREFIX_DLA 2U
#define RM_UUID_PREFIX_UGC 3U
void nvGetUuidString(const NvUuid *pUuid, NvU8 prefix, char *pUuidStr);

3
src/nvidia/inc/kernel/gpu/gr/kernel_watchdog.h Normal file
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@@ -0,0 +1,3 @@
#include "g_kernel_watchdog_nvoc.h"

3
src/nvidia/inc/kernel/gpu/gsp/gsp_init_args.h
View File

@@ -25,6 +25,9 @@
#define GSP_INIT_ARGS_H
#include "nvtypes.h"
#include "gpu/mem_mgr/rm_page_size.h"
#define WPR_ALIGNMENT RM_PAGE_SIZE_128K
typedef struct {
NvU64 sharedMemPhysAddr;

6
src/nvidia/inc/kernel/gpu/gsp/gsp_static_config.h
View File

@@ -40,7 +40,6 @@
#include "platform/chipset/chipset.h" // BUSINFO
#include "gpu/nvbitmask.h" // NVGPU_ENGINE_CAPS_MASK_ARRAY_MAX
// VF related info for GSP-RM
typedef struct GSP_VF_INFO
{
@@ -82,6 +81,9 @@ typedef struct GspStaticConfigInfo_t
NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS SKUInfo;
NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_PARAMS fbRegionInfoParams;
NvBool bPdiValid;
NvU64 pdi;
NV0080_CTRL_GPU_GET_SRIOV_CAPS_PARAMS sriovCaps;
NvU32 sriovMaxGfid;
@@ -224,6 +226,8 @@ typedef struct GspSystemInfo
NvBool bGspNocatEnabled;
NvBool bS0ixSupport;
NvBool bWindowChannelAlwaysMapped;
NvU32 pciePowerControlValue;
NvBool bPciePowerControlPresent;
} GspSystemInfo;

114
src/nvidia/inc/kernel/gpu/hfrp/kernel_hfrp.h
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@@ -1,117 +1,3 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2024-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#include "g_kernel_hfrp_nvoc.h"
#ifndef _KERNELHFRP_H_
#define _KERNELHFRP_H_
#include "nvtypes.h"
#include "nvstatus.h"
#include "nvmisc.h"
#include "utils/nvprintf.h"
#include "os/os.h"
#include "gpu/eng_state.h"
#include "gpu/gpu.h"
#include "gpu/hfrp/kern_hfrp_common.h"
// Total number of HFRP Mailboxes available for the interface
#define HFRP_NUMBER_OF_MAILBOXES 2U
// Maximum Payload size for a message
#define HFRP_MAX_PAYLOAD_SIZE 50U
#define HFRP_COMMAND_MAILBOX_INDEX HFRP_COMMAND_MAILBOX_INDEX_DISPLAY
#define HFRP_RESPONSE_MAILBOX_INDEX HFRP_RESPONSE_MAILBOX_INDEX_DISPLAY
//
// Maximum values of Sequence Id index and Sequence Id Array index (each
// Sequence Id array element has 32 bits that represent 32 Sequence Ids)
//
#define HFRP_NUMBER_OF_SEQUENCEID_INDEX 0x400
#define HFRP_NUMBER_OF_SEQUENCEID_ARRAY_INDEX (HFRP_NUMBER_OF_SEQUENCEID_INDEX / 32U)
#define HFRP_ASYNC_NOTIFICATION_SEQUENCEID_INDEX 0x3FF
NVOC_PREFIX(khfrp) class KernelHFRP: OBJENGSTATE
{
public:
/*! HFRP Create Object */
virtual NV_STATUS khfrpStatePreInitLocked(OBJGPU *pGpu, KernelHFRP *pHfrp);
virtual NV_STATUS khfrpConstructEngine(OBJGPU *pGpu, KernelHFRP *pHfrp, ENGDESCRIPTOR engDesc);
/*! HFRP Destructor */
void khfrpDestruct(KernelHFRP *pHfrp);
void khfrpCommonConstruct(KernelHFRP *pHfrp);
NV_STATUS khfrpIoApertureConstruct(OBJGPU *pGpu, KernelHFRP *pHfrp);
void khfrpIoApertureDestruct(KernelHFRP *pHfrp, NvU32 index);
NvU32 khfrpReadBit(KernelHFRP *pHfrp, NvU32 virtualAddr, NvU32 bitIndex);
void khfrpWriteBit(KernelHFRP *pHfrp, NvU32 virtualAddr, NvU32 bitIndex, NvU32 data);
NV_STATUS khfrpMailboxQueueMessage(KernelHFRP *pHfrp, NvU32 messageHeader, NvU8 *pPayloadArray,
NvU32 payloadSize, NvU32 mailboxFlag);
NV_STATUS khfrpServiceEvent(KernelHFRP *pHfrp);
NvU32 khfrpAllocateSequenceId(KernelHFRP *pHfrp, NvU16 *pResponseStatus, void *pResponsePayload,
NvU32 *pResponsePayloadSize, NV_STATUS *pStatus, NvU32 *pSequenceId);
void khfrpFreeSequenceId(KernelHFRP *pHfrp, NvU32 index);
NvBool khfrpIsSequenceIdFree(KernelHFRP *pHfrp, NvU32 index);
NV_STATUS khfrpPollOnIrqWrapper(KernelHFRP *pHfrp, NvU32 irqRegAddr, NvU32 bitIndex, NvBool bData);
NV_STATUS khfrpPollOnIrqRm(KernelHFRP *pHfrp, NvU32 irqRegAddr, NvU32 bitIndex, NvBool bData);
NV_STATUS khfrpPostCommandBlocking(KernelHFRP *pHfrp, NvU16 commandIndex, void *pCommandPayload, NvU32 commandPayloadSize,
NvU16 *pResponseStatus, void *pResponsePayload, NvU32 *pResponsePayloadSize);
NV_STATUS khfrpInterfaceReset(KernelHFRP *pHfrp);
NVOC_PROPERTY NvBool PDB_PROP_KHFRP_IS_ENABLED;
NvU32 khfrpPrivBase[5];
NvU32 khfrpIntrCtrlReg[5];
IoAperture *pAperture[HFRP_NUMBER_OF_MAILBOXES];
HFRP_INFO khfrpInfo;
};
#define HFRP_REG_RD32(pKernelHfrp, virtualAddr) \
REG_RD32(pKernelHfrp->pAperture[virtualAddr / HFRP_MAILBOX_ACCESS_RANGE], \
virtualAddr % HFRP_MAILBOX_ACCESS_RANGE)
#define HFRP_REG_WR32(pKernelHfrp, virtualAddr, data32) \
REG_WR32(pKernelHfrp->pAperture[virtualAddr / HFRP_MAILBOX_ACCESS_RANGE], \
virtualAddr % HFRP_MAILBOX_ACCESS_RANGE, data32)
#define HFRP_POLL_ON_IRQ(pKernelHfrp, irqRegAddr, bitIndex, bData) \
khfrpPollOnIrqRm(pKernelHfrp, irqRegAddr, bitIndex, bData)
#endif // _KernelHFRP_H_

3
src/nvidia/inc/kernel/gpu/intr/engine_idx.h
View File

@@ -162,8 +162,9 @@
#define MC_ENGINE_IDX_GPIO 176
#define MC_ENGINE_IDX_DISP_LOW 177
#define MC_ENGINE_IDX_HFRP 178
#define MC_ENGINE_IDX_I2C 179
// This must be kept as the max bit if we need to add more engines
#define MC_ENGINE_IDX_MAX 179
#define MC_ENGINE_IDX_MAX 180
// Index GR reference
#define MC_ENGINE_IDX_GRn(x) (MC_ENGINE_IDX_GR0 + (x))

3
src/nvidia/inc/kernel/gpu/mem_mgr/heap_base.h
View File

@@ -83,9 +83,6 @@ typedef struct _def_fb_alloc_info
NvU32 possAttr; // AllocHint, BindCompr
NvU32 ctagOffset;
// Special flag for kernel allocations
NvBool bIsKernelAlloc;
//
// Number of 4KB pages in the PTE array
// For contiguous allocation, this will be set to '1'

6
src/nvidia/inc/kernel/gpu/mem_mgr/phys_mem_allocator/map_defines.h
View File

@@ -60,6 +60,9 @@ extern "C" {
#define PMA_LOCALIZED_MEMORY_ALLOC_STRIDE (32ULL * 1024 * 1024)
#define PMA_LOCALIZED_MEMORY_RESERVE_SIZE (2 * PMA_LOCALIZED_MEMORY_ALLOC_STRIDE)
// Same as NVOS32_ATTR2_ENABLE_LOCALIZED_MEMORY_UGPU_COUNT
#define PMA_MAX_LOCALIZED_REGION_COUNT 2
typedef NvU32 PMA_PAGESTATUS;
#define MAP_IDX_ALLOC_UNPIN 0
@@ -113,6 +116,9 @@ typedef struct _PMA_STATS
NvU64 numFreeFramesProtected; // PMA-wide free 64KB frame count in protected memory
NvU64 numFree2mbPagesProtected; // PMA-wide free 2MB pages count in protected memory
#endif // !defined(NVWATCH)
NvU64 num2mbPagesLocalizable[PMA_MAX_LOCALIZED_REGION_COUNT]; // PMA-wide free 64KB per-uGPU frame count
NvU64 numFreeFramesLocalizable[PMA_MAX_LOCALIZED_REGION_COUNT]; // PMA-wide free 64KB per-uGPU frame count
NvU64 numFree2mbPagesLocalizable[PMA_MAX_LOCALIZED_REGION_COUNT]; // PMA-wide free 64KB per-uGPU frame count
} PMA_STATS;
// Stores blacklisting information passed in from heap layer

25
src/nvidia/inc/kernel/gpu/mem_mgr/phys_mem_allocator/phys_mem_allocator.h
View File

@@ -529,6 +529,18 @@ void pmaUnregisterEvictionCb(PMA *pPma);
*/
void pmaGetTotalMemory(PMA *pPma, NvU64 *pBytesTotal);
/*!
* @brief Returns information about the total FB memory available for localized allocations on the requested uGPU core.
*
* @param[in] pPma PMA pointer
* @param[in] ugpuId uGPU core identifier
* @param[in] pBytesTotal Pointer that will return the total FB memory size.
*
* @return
* void
*/
void pmaGetUgpuTotalMemory(PMA *pPma, NvU32 ugpuId, NvU64 *pBytesTotal);
/*!
* @brief Returns information about each region managed by PMA
*
@@ -562,6 +574,19 @@ PMA_STATS *pmaGetStats(PMA *pPma);
*/
void pmaGetFreeMemory(PMA *pPma, NvU64 *pBytesFree);
/*!
* @brief Returns information about the total free FB memory available
* for localized allocations on the requested uGPU core.
*
* @param[in] pPma PMA pointer
* @param[in] ugpuId uGPU core identifier
* @param[in] pBytesFree Pointer that will return the free FB memory size.
*
* @return
* void
*/
void pmaGetUgpuFreeMemory(PMA *pPma, NvU32 ugpuId, NvU64 *pBytesFree);
/*!
* @brief Returns information about the client address space size
* that can be allocated

5
src/nvidia/inc/kernel/gpu/mmu/mmu_trace.h
View File

@@ -65,11 +65,9 @@ typedef NvU32 (*MmuTraceCbSwToHwLevel)(const void *pFmt, NvU32 level);
typedef enum
{
MMU_TRACE_MODE_TRACE = 0,
MMU_TRACE_MODE_TRACE_VERBOSE = 1,
MMU_TRACE_MODE_TRANSLATE = 2,
MMU_TRACE_MODE_VALIDATE = 3,
MMU_TRACE_MODE_DUMP_RANGE = 4
MMU_TRACE_MODE_DUMP_RANGE = 3
} MMU_TRACE_MODE, *PMMU_TRACE_MODE;
typedef struct
@@ -78,7 +76,6 @@ typedef struct
NvU32 aperture;
NvBool valid;
NV83DE_CTRL_DEBUG_GET_MAPPINGS_PARAMETERS *pMapParams;
NvU64 validateCount;
} MMU_TRACE_ARG, *PMMU_TRACE_ARG;
typedef struct

87
src/nvidia/inc/kernel/gpu/nvlink/bitvector_nvlink.h Normal file
View File

@@ -0,0 +1,87 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef BITVECTOR_NVLINK_H
#define BITVECTOR_NVLINK_H
/* ------------------------ System Includes --------------------------------- */
/* ------------------------ Application Includes ---------------------------- */
#include "utils/nvbitvector.h"
#include "ctrl/ctrl2080/ctrl2080nvlink_common.h" // rmcontrol mask structures
/* ------------------------ Global Variables -------------------------------- */
// NVLINK_BIT_VECTOR is the global bitvector type used in nvlink code
MAKE_BITVECTOR(NVLINK_BIT_VECTOR, NV2080_CTRL_NVLINK_MAX_LINKS);
/* ------------------------ Macros and Defines ------------------------------ */
/* ------------------------ Function Prototypes ----------------------------- */
/*!
* @brief Function takes in a NvU64 input mask and converts it to a usable BITVECTOR
* @param[in] inputLinkMask a NvU64 bitmask
* @param[out] pLocalLinkMask pointer to a NVLINK_BIT_VECTOR to copy the passed in bitmask to
*/
NV_STATUS
convertMaskToBitVector(NvU64 inputLinkMask, NVLINK_BIT_VECTOR *pLocalLinkMask);
/*!
* @brief Function takes in a NVLINK_BIT_VECTOR and returns a NvU32 bitmask
* @param[in] pBitVector pointer to a NVLINK_BIT_VECTOR to convert
* @param[out] linkMask pointer to a NvU32 which hold the converted bitmask
*/
NV_STATUS
convertBitVectorToLinkMask32(NVLINK_BIT_VECTOR *pBitVector, NvU32 *linkMask);
/*!
* @brief Function takes in a NVLINK_BIT_VECTOR and converts it to mask structures
* @param[in] pBitVector pointer to a NVLINK_BIT_VECTOR to convert
* @param[out] pOutputLinkMask1 pointer to a NvU64 which hold the converted bitmask
* Can be null which will skip the conversion
* @param[in] outputLinkMask1Size Details the number of bits in pOutputLinkMask1
* Size must be either 32 or 64
* @param[out] pOutputLinkMask2 Pointer to NV2080_CTRL_NVLINK_LINK_MASK to convert to
* Can be null which will skip the conversion
*/
NV_STATUS
convertBitVectorToLinkMasks(NVLINK_BIT_VECTOR *pBitVector,
void *pOutputLinkMask1, NvU32 outputLinkMask1Size,
NV2080_CTRL_NVLINK_LINK_MASK *pOutputLinkMask2);
/*!
* @brief Function that can take 2 masks, a primitive and NV2080_CTRL_NVLINK_LINK_MASK,
* and returns the OR of the 2 as a native NVLINK_BIT_VECTOR. One mask must
* be provided
* @param[in] pLinkMask2 pointer to a NV2080_CTRL_NVLINK_LINK_MASK to convert
* Can be null which will skip the conversion
* @param[in] pLinkMask1 pointer to a NvU64 which hold the converted bitmask
* Can be null which will skip the conversion
* @param[in] linkMask1Size Details the number of bits in pOutputLinkMask1
* Size must be either 32 or 64
* @param[out] pOutputBitVector Pointer to NVLINK_BIT_VECTOR to store conversion
*/
NV_STATUS
convertLinkMasksToBitVector(const void *pLinkMask1, NvU32 linkMask1Size,
const NV2080_CTRL_NVLINK_LINK_MASK *pLinkMask2,
NVLINK_BIT_VECTOR *pOutputBitVector);
#endif // BITVECTOR_NVLINK_H

19
src/nvidia/inc/kernel/gpu/nvlink/common_nvlink.h
View File

@@ -30,25 +30,6 @@
#include "utils/nvbitvector.h"
#include "ctrl/ctrl2080/ctrl2080nvlink.h" // rmcontrol params
MAKE_BITVECTOR(NV2080_NVLINK_BIT_VECTOR, NV2080_CTRL_NVLINK_MAX_LINKS);
NV_STATUS nvlinkCtrlCmdBusGetNvlinkCaps(OBJGPU *pGpu, NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS_PARAMS *pParams);
NV_STATUS
convertMaskToBitVector(NvU64 inputLinkMask, NV2080_NVLINK_BIT_VECTOR *pLocalLinkMask);
NV_STATUS
convertBitVectorToLinkMask32(NV2080_NVLINK_BIT_VECTOR *pBitVector, NvU32 *linkMask);
NV_STATUS
convertBitVectorToLinkMasks(NV2080_NVLINK_BIT_VECTOR *pLocalLinkMask,
void *pOutputLinkMask1, NvU32 outputLinkMask1Size,
NV2080_CTRL_NVLINK_LINK_MASK *pOutputLinkMask2);
NV_STATUS
convertLinkMasksToBitVector(const void *pLinkMask1, NvU32 linkMask1Size,
const NV2080_CTRL_NVLINK_LINK_MASK *pLinkMask2,
NV2080_NVLINK_BIT_VECTOR *pOutputBitVector);
#endif // COMMON_NVLINK_H

6
src/nvidia/inc/kernel/gpu/rc/kernel_rc_watchdog_private.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2021-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -44,7 +44,7 @@
#define WATCHDOG_RESET_QUEUE_SIZE (4)
// KernelWatchdog.flags
// KernelWatchdogState.flags
#define WATCHDOG_FLAGS_INITIALIZED NVBIT(0) // Fully initialized and ready
#define WATCHDOG_FLAGS_DISABLED NVBIT(1) // Disabled
#define WATCHDOG_FLAGS_ALLOC_UNCACHED_PCI NVBIT(2) // Alloc cached / uncached pushbuffer
@@ -80,7 +80,7 @@ typedef struct {
NvNotification *errorContext;
NvNotification *notifierToken;
NvBool bHandleValid;
} KernelWatchdog;
} KernelWatchdogState;
/*! Persistent watchdog state preserved across watchdog shutdowns */

2
src/nvidia/inc/kernel/gpu/rpc/objrpc.h
View File

@@ -53,6 +53,8 @@ TYPEDEF_BITVECTOR(MC_ENGINE_BITVECTOR);
#define RPC_TIMEOUT_GPU_RESET_THRESHOLD 3 // Reset GPU after 3 back to back GSP RPC timeout
#define RPC_TIMEOUT_PRINT_RATE_SKIP 29 // skip 29 of 30 prints
#define SLOW_RPC_THRESHOLD_US 66000
#define RPC_HISTORY_DEPTH 128
typedef struct RpcHistoryEntry