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545.23.06

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This commit is contained in:
Andy Ritger
2023-10-17 09:25:29 -07:00
parent f59818b751
commit b5bf85a8e3
917 changed files with 132480 additions and 110015 deletions
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37
src/common/modeset/hdmipacket/nvhdmipkt.c
View File

@@ -49,6 +49,8 @@
#include "class/clc67d.h"
#include "class/clc770.h"
#include "hdmi_spec.h"
// Class hierarchy structure
typedef struct tagNVHDMIPKT_CLASS_HIERARCHY
{
@@ -85,7 +87,7 @@ typedef struct tagNVHDMIPKT_CLASS_HIERARCHY
************************************************************************************************/
static const NVHDMIPKT_CLASS_HIERARCHY hierarchy[] =
{
{// Index 0==NVHDMIPKT_0073_CLASS
[NVHDMIPKT_0073_CLASS] = {// Index 0==NVHDMIPKT_0073_CLASS
NVHDMIPKT_0073_CLASS, // classId
NVHDMIPKT_0073_CLASS, // parentClassId
NV_TRUE, // isRootClass
@@ -95,7 +97,7 @@ static const NVHDMIPKT_CLASS_HIERARCHY hierarchy[] =
0, // displayClass
0 // coreDmaClass
},
{// Index 1==NVHDMIPKT_9171_CLASS
[NVHDMIPKT_9171_CLASS] = {// Index 1==NVHDMIPKT_9171_CLASS
NVHDMIPKT_9171_CLASS, // classId
NVHDMIPKT_9171_CLASS, // parentClassId
NV_TRUE, // isRootClass
@@ -105,7 +107,7 @@ static const NVHDMIPKT_CLASS_HIERARCHY hierarchy[] =
NV9170_DISPLAY, // displayClass
NV917D_CORE_CHANNEL_DMA // coreDmaClass
},
{// Index 2==NVHDMIPKT_9271_CLASS
[NVHDMIPKT_9271_CLASS] = {// Index 2==NVHDMIPKT_9271_CLASS
NVHDMIPKT_9271_CLASS, // classId
NVHDMIPKT_9171_CLASS, // parentClassId
NV_FALSE, // isRootClass
@@ -115,7 +117,7 @@ static const NVHDMIPKT_CLASS_HIERARCHY hierarchy[] =
NV9270_DISPLAY, // displayClass
NV927D_CORE_CHANNEL_DMA // coreDmaClass
},
{// Index 3==NVHDMIPKT_9471_CLASS
[NVHDMIPKT_9471_CLASS] = {// Index 3==NVHDMIPKT_9471_CLASS
NVHDMIPKT_9471_CLASS, // classId
NVHDMIPKT_9171_CLASS, // parentClassId
NV_FALSE, // isRootClass
@@ -125,7 +127,7 @@ static const NVHDMIPKT_CLASS_HIERARCHY hierarchy[] =
NV9470_DISPLAY, // displayClass
NV947D_CORE_CHANNEL_DMA // coreDmaClass
},
{// Index 4==NVHDMIPKT_9571_CLASS
[NVHDMIPKT_9571_CLASS] = {// Index 4==NVHDMIPKT_9571_CLASS
NVHDMIPKT_9571_CLASS, // classId
NVHDMIPKT_9171_CLASS, // parentClassId
NV_FALSE, // isRootClass
@@ -135,7 +137,7 @@ static const NVHDMIPKT_CLASS_HIERARCHY hierarchy[] =
NV9570_DISPLAY, // displayClass
NV957D_CORE_CHANNEL_DMA // coreDmaClass
},
{// Index 5==NVHDMIPKT_C371_CLASS
[NVHDMIPKT_C371_CLASS] = {// Index 5==NVHDMIPKT_C371_CLASS
NVHDMIPKT_C371_CLASS, // classId
NVHDMIPKT_9171_CLASS, // parentClassId
NV_FALSE, // isRootClass
@@ -145,7 +147,7 @@ static const NVHDMIPKT_CLASS_HIERARCHY hierarchy[] =
NVC370_DISPLAY, // displayClass
NVC37D_CORE_CHANNEL_DMA // coreDmaClass
},
{// Index 6==NVHDMIPKT_C571_CLASS
[NVHDMIPKT_C571_CLASS] = {// Index 6==NVHDMIPKT_C571_CLASS
// Note that Turing (C57x) has a distinct displayClass and coreDmaClass,
// but it inherits the _DISP_SF_USER class from Volta (C37x). We call this
// NVHDMIPKT_C571_CLASS, but reuse initInterface()/constructor()/destructor()
@@ -159,7 +161,7 @@ static const NVHDMIPKT_CLASS_HIERARCHY hierarchy[] =
NVC570_DISPLAY, // displayClass
NVC57D_CORE_CHANNEL_DMA // coreDmaClass
},
{// Index 7==NVHDMIPKT_C671_CLASS
[NVHDMIPKT_C671_CLASS] = {// Index 7==NVHDMIPKT_C671_CLASS
NVHDMIPKT_C671_CLASS, // classId
NVHDMIPKT_9171_CLASS, // parentClassId
NV_FALSE, // isRootClass
@@ -169,7 +171,7 @@ static const NVHDMIPKT_CLASS_HIERARCHY hierarchy[] =
NVC670_DISPLAY, // displayClass
NVC67D_CORE_CHANNEL_DMA // coreDmaClass
},
{// Index 8==NVHDMIPKT_C771_CLASS
[NVHDMIPKT_C771_CLASS] = {// Index 8==NVHDMIPKT_C771_CLASS
NVHDMIPKT_C771_CLASS, // classId
NVHDMIPKT_C671_CLASS, // parentClassId
NV_FALSE, // isRootClass
@@ -233,6 +235,23 @@ NvHdmiPkt_PacketWrite(NvHdmiPkt_Handle libHandle,
return NVHDMIPKT_INVALID_ARG;
}
HDMI_PACKET_TYPE infoframeType = pPacket[0]; // header byte 0 is packet type
// Lower bound check. Since actual infoframe size varies depending on the infoframe packet being sent,
// check all supported infoframe types and their expected sizes. This is not a strict == check becuase they may/may not need
// additional checksum byte (library clients take care of adding checksum byte if needed)
if (((infoframeType == hdmi_pktType_GeneralControl) && (packetLen < 6)) ||
((infoframeType == hdmi_pktType_GamutMetadata) && (packetLen < sizeof(NVT_GAMUT_METADATA))) ||
((infoframeType == hdmi_pktType_ExtendedMetadata) && (packetLen < sizeof(NVT_EXTENDED_METADATA_PACKET_INFOFRAME)))||
((infoframeType == hdmi_pktType_VendorSpecInfoFrame) && (packetLen < 8)) ||
((infoframeType == hdmi_pktType_AviInfoFrame) && (packetLen < sizeof(NVT_VIDEO_INFOFRAME))) ||
((infoframeType == hdmi_pktType_SrcProdDescInfoFrame) && (packetLen < sizeof(NVT_SPD_INFOFRAME))) ||
((infoframeType == hdmi_pktType_DynamicRangeMasteringInfoFrame) && (packetLen < sizeof(NVT_HDR_INFOFRAME))))
// Unused: hdmi_pktType_AudioClkRegeneration
// Unused: hdmi_pktType_MpegSrcInfoFrame
{
NvHdmiPkt_Print(pClass, "WARNING - packet length too small for infoframe type %d check payload ", infoframeType);
}
return pClass->hdmiPacketWrite(pClass,
subDevice,
displayId,

17
src/common/modeset/hdmipacket/nvhdmipkt.h
View File

@@ -56,7 +56,7 @@ typedef enum
NVHDMIPKT_TIMEOUT = 4,
NVHDMIPKT_ERR_GENERAL = 5,
NVHDMIPKT_INSUFFICIENT_BANDWIDTH = 6,
NVHDMIPKT_RETRY = 7
NVHDMIPKT_RETRY = 7,
} NVHDMIPKT_RESULT;
// NVHDMIPKT_TYPE: HDMI Packet Enums
@@ -69,14 +69,13 @@ typedef enum _NVHDMIPKT_TYPE
NVHDMIPKT_TYPE_GENERAL_CONTROL = 3, // GCP
NVHDMIPKT_TYPE_VENDOR_SPECIFIC_INFOFRAME = 4, // VSI
NVHDMIPKT_TYPE_AUDIO_INFOFRAME = 5, // Audio InfoFrame
NVHDMIPKT_TYPE_EXTENDED_METADATA_PACKET = 6, // Extended Metadata Packet (HDMI 2.1)
NVHDMIPKT_TYPE_SHARED_GENERIC1 = 7, // ADA+ Specifc shared generic infoframe 1~6
NVHDMIPKT_TYPE_SHARED_GENERIC2 = 8,
NVHDMIPKT_TYPE_SHARED_GENERIC3 = 9,
NVHDMIPKT_TYPE_SHARED_GENERIC4 = 10,
NVHDMIPKT_TYPE_SHARED_GENERIC5 = 11,
NVHDMIPKT_TYPE_SHARED_GENERIC6 = 12,
NVHDMIPKT_INVALID_PKT_TYPE = 13
NVHDMIPKT_TYPE_SHARED_GENERIC1 = 6, // ADA+ Specifc shared generic infoframe 1~6
NVHDMIPKT_TYPE_SHARED_GENERIC2 = 7,
NVHDMIPKT_TYPE_SHARED_GENERIC3 = 8,
NVHDMIPKT_TYPE_SHARED_GENERIC4 = 9,
NVHDMIPKT_TYPE_SHARED_GENERIC5 = 10,
NVHDMIPKT_TYPE_SHARED_GENERIC6 = 11,
NVHDMIPKT_INVALID_PKT_TYPE = 12
} NVHDMIPKT_TYPE;
// Hdmi packet TransmitControl defines. These definitions reflect the

12
src/common/modeset/hdmipacket/nvhdmipkt_0073.c
View File

@@ -337,10 +337,10 @@ hdmiQueryFRLConfigDummy(NVHDMIPKT_CLASS *pThis,
NVHDMIPKT_RESULT
hdmiSetFRLConfigDummy(NVHDMIPKT_CLASS *pThis,
NvU32 subDevice,
NvU32 displayId,
NvBool bFakeLt,
HDMI_FRL_CONFIG *pFRLConfig)
NvU32 subDevice,
NvU32 displayId,
NvBool bFakeLt,
HDMI_FRL_CONFIG *pFRLConfig)
{
NvHdmiPkt_Print(pThis, "ERROR - Dummy function hdmiSetFRLConfigDummy called. "
"Should never be called.");
@@ -350,8 +350,8 @@ hdmiSetFRLConfigDummy(NVHDMIPKT_CLASS *pThis,
NVHDMIPKT_RESULT
hdmiClearFRLConfigDummy(NVHDMIPKT_CLASS *pThis,
NvU32 subDevice,
NvU32 displayId)
NvU32 subDevice,
NvU32 displayId)
{
NvHdmiPkt_Print(pThis, "ERROR - Dummy function hdmiClearFRLConfigDummy called. "
"Should never be called.");

62
src/common/modeset/hdmipacket/nvhdmipkt_9171.c
View File

@@ -36,6 +36,9 @@
#include "ctrl/ctrl0073/ctrl0073specific.h"
#define NVHDMIPKT_9171_INVALID_PKT_TYPE ((NV9171_SF_HDMI_INFO_IDX_VSI) + 1)
#define NVHDMIPKT_CTAIF_MAX_PKT_BYTES 31 // 3 bytes header + 28 bytes data (CTA infoframe max payload size)
#define NVHDMIPKT_9171_MAX_PKT_BYTES_AVI 17 // 3 bytes header + 14 bytes data
NVHDMIPKT_RESULT
hdmiPacketWrite9171(NVHDMIPKT_CLASS* pThis,
NvU32 subDevice,
@@ -53,6 +56,14 @@ hdmiPacketCtrl9171(NVHDMIPKT_CLASS* pThis,
NvU32 head,
NVHDMIPKT_TYPE packetType,
NVHDMIPKT_TC transmitControl);
void
hdmiWriteAviPacket9171(NVHDMIPKT_CLASS* pThis,
NvU32* pBaseReg,
NvU32 head,
NvU32 packetLen,
NvU8 const *const pPacket);
/*
* hdmiReadPacketStatus9171
*/
@@ -135,7 +146,7 @@ hdmiWritePacketCtrl9171(NVHDMIPKT_CLASS* pThis,
/*
* hdmiWriteAviPacket9171
*/
static void
void
hdmiWriteAviPacket9171(NVHDMIPKT_CLASS* pThis,
NvU32* pBaseReg,
NvU32 head,
@@ -144,6 +155,12 @@ hdmiWriteAviPacket9171(NVHDMIPKT_CLASS* pThis,
{
NvU32 data = 0;
if (packetLen > NVHDMIPKT_9171_MAX_PKT_BYTES_AVI)
{
NvHdmiPkt_Print(pThis, "ERROR - input AVI packet length incorrect. Write will be capped to max allowable bytes");
NvHdmiPkt_Assert(0);
}
data = REG_RD32(pBaseReg, NV9171_SF_HDMI_AVI_INFOFRAME_HEADER(head));
data = FLD_SET_DRF_NUM(9171, _SF_HDMI_AVI_INFOFRAME_HEADER, _HB0, pPacket[0], data);
data = FLD_SET_DRF_NUM(9171, _SF_HDMI_AVI_INFOFRAME_HEADER, _HB1, pPacket[1], data);
@@ -512,41 +529,6 @@ checkPacketStatus_exit:
return result;
}
static NVHDMIPKT_RESULT
validateInputPacketLength(NvU32 pktType9171,
NvU32 packetLen,
NvU8 const *const pPacketIn)
{
NVHDMIPKT_RESULT result = NVHDMIPKT_SUCCESS;
HDMI_PACKET_TYPE infoframeType = pPacketIn[0];
// Lower bound check. Since actual infoframe size varies depending on the infoframe packet being sent,
// check all supported infoframe types and their expected sizes. This is not a strict == check becuase they may/may not need
// additional checksum byte (library clients take care of adding checksum byte if needed)
if (((infoframeType == hdmi_pktType_GeneralControl) && (packetLen < 6)) ||
((infoframeType == hdmi_pktType_GamutMetadata) && (packetLen < sizeof(NVT_GAMUT_METADATA))) ||
((infoframeType == hdmi_pktType_ExtendedMetadata) && (packetLen < sizeof(NVT_EXTENDED_METADATA_PACKET_INFOFRAME)))||
((infoframeType == hdmi_pktType_VendorSpecInfoFrame) && (packetLen < 8)) ||
((infoframeType == hdmi_pktType_AviInfoFrame) && (packetLen < sizeof(NVT_VIDEO_INFOFRAME))) ||
((infoframeType == hdmi_pktType_SrcProdDescInfoFrame) && (packetLen < sizeof(NVT_SPD_INFOFRAME))) ||
((infoframeType == hdmi_pktType_DynamicRangeMasteringInfoFrame) && (packetLen < sizeof(NVT_HDR_INFOFRAME))))
// Unused: hdmi_pktType_AudioClkRegeneration
// Unused: hdmi_pktType_MpegSrcInfoFrame
{
result = NVHDMIPKT_INVALID_ARG;
}
// Upper bound check. Check against number of bytes possible on the hw infoframe unit
if (((pktType9171 == NV9171_SF_HDMI_INFO_IDX_AVI_INFOFRAME) && (packetLen > 17)) || // 3 bytes header + 14 bytes data
((pktType9171 == NV9171_SF_HDMI_INFO_IDX_GENERIC_INFOFRAME) && (packetLen > 31)) || // 3 bytes header + 28 bytes data
((pktType9171 == NV9171_SF_HDMI_INFO_IDX_VSI) && (packetLen > 31))) // 3 bytes header + 28 bytes data
{
result = NVHDMIPKT_INVALID_ARG;
}
return result;
}
/*
* hdmiPacketWrite9171
*/
@@ -567,7 +549,7 @@ hdmiPacketWrite9171(NVHDMIPKT_CLASS* pThis,
NV0073_CTRL_SPECIFIC_CTRL_HDMI_PARAMS params = {0};
// packetIn can be of varying size. Use a fixed max size buffer for programing hw units to prevent out of bounds access
NvU8 pPacket[31] = {0};
NvU8 pPacket[NVHDMIPKT_CTAIF_MAX_PKT_BYTES] = {0};
if (pBaseReg == 0 || head >= NV9171_SF_HDMI_AVI_INFOFRAME_CTRL__SIZE_1 ||
packetLen == 0 || pPacketIn == 0 || pktType9171 == NVHDMIPKT_9171_INVALID_PKT_TYPE)
@@ -577,11 +559,11 @@ hdmiPacketWrite9171(NVHDMIPKT_CLASS* pThis,
goto hdmiPacketWrite9171_exit;
}
if ((result = validateInputPacketLength(pktType9171, packetLen, pPacketIn)) != NVHDMIPKT_SUCCESS)
if (packetLen > NVHDMIPKT_CTAIF_MAX_PKT_BYTES)
{
NvHdmiPkt_Print(pThis, "ERROR - input packet length incorrect %d", packetLen);
NvHdmiPkt_Print(pThis, "ERROR - input packet length incorrect %d Packet write will be capped to max allowable bytes", packetLen);
packetLen = NVHDMIPKT_CTAIF_MAX_PKT_BYTES;
NvHdmiPkt_Assert(0);
goto hdmiPacketWrite9171_exit;
}
// input packet looks ok to use, copy over the bytes

2
src/common/modeset/hdmipacket/nvhdmipkt_C771.c
View File

@@ -32,6 +32,8 @@
#include "class/clc771.h"
#define NVHDMIPKT_C771_MAX_PKT_BYTES_AVI 21 // 3 bytes header + 18 bytes payload
extern NVHDMIPKT_RESULT hdmiPacketWrite9171(NVHDMIPKT_CLASS* pThis,
NvU32 subDevice,
NvU32 displayId,

94
src/common/modeset/timing/displayid20.h
View File

@@ -65,7 +65,7 @@ typedef struct _tagDISPLAYID_2_0_SECTION_HEADER
NvU8 product_type:4; // Display Product Primary Use Case
NvU8 reserved:4; // RESERVED
NvU8 extension_count; // Total extension count.
} DISPLAYID_2_0_SECTION_HEADER;
} DISPLAYID_2_0_SECTION_HEADER;
typedef struct _tagDISPLAYID_2_0_SECTION
{
@@ -79,7 +79,7 @@ typedef struct _tagDISPLAYID_2_0_SECTION
#define DISPLAYID_2_0_PROD_EXTENSION 0 // Extension (same primary use case as base section)
#define DISPLAYID_2_0_PROD_TEST 1 // Test Structure/Test Equipment
#define DISPLAYID_2_0_PROD_GENERIC_DISPLAY 2 // None of the listed primary use cases; generic display
#define DISPLAYID_2_0_PROD_GENERIC_DISPLAY 2 // None of the listed primary use cases; generic display
#define DISPLAYID_2_0_PROD_TELEVISION 3 // Television (TV) display
#define DISPLAYID_2_0_PROD_DESKTOP_PRODUCTIVITY_DISPLAY 4 // Desktop productivity display
#define DISPLAYID_2_0_PROD_DESKTOP_GAMING_DISPLAY 5 // Desktop gaming display
@@ -95,25 +95,26 @@ typedef struct _tagDISPLAYID_2_0_DATA_BLOCK_HEADER
NvU8 data_bytes; // number of payload bytes in Block [ 0, 248]
} DISPLAYID_2_0_DATA_BLOCK_HEADER;
#define DISPLAYID_2_0_BLOCK_TYPE_PRODUCT_IDENTITY 0x20
#define DISPLAYID_2_0_BLOCK_TYPE_DISPLAY_PARAM 0x21
#define DISPLAYID_2_0_BLOCK_TYPE_TIMING_7 0x22
#define DISPLAYID_2_0_BLOCK_TYPE_TIMING_8 0x23
#define DISPLAYID_2_0_BLOCK_TYPE_TIMING_9 0x24
#define DISPLAYID_2_0_BLOCK_TYPE_RANGE_LIMITS 0x25
#define DISPLAYID_2_0_BLOCK_TYPE_INTERFACE_FEATURES 0x26
#define DISPLAYID_2_0_BLOCK_TYPE_STEREO 0x27
#define DISPLAYID_2_0_BLOCK_TYPE_TILED_DISPLAY 0x28
#define DISPLAYID_2_0_BLOCK_TYPE_CONTAINER_ID 0x29
#define DISPLAYID_2_0_BLOCK_TYPE_TIMING_10 0x2A
#define DISPLAYID_2_0_BLOCK_TYPE_ADAPTIVE_SYNC 0x2B
#define DISPLAYID_2_0_BLOCK_TYPE_ARVR_HMD 0x2C
#define DISPLAYID_2_0_BLOCK_TYPE_ARVR_LAYER 0x2D
// 0x7D - 0x2E RESERVED for Additional VESA-defined Data Blocks
#define DISPLAYID_2_0_BLOCK_TYPE_PRODUCT_IDENTITY 0x20
#define DISPLAYID_2_0_BLOCK_TYPE_DISPLAY_PARAM 0x21
#define DISPLAYID_2_0_BLOCK_TYPE_TIMING_7 0x22
#define DISPLAYID_2_0_BLOCK_TYPE_TIMING_8 0x23
#define DISPLAYID_2_0_BLOCK_TYPE_TIMING_9 0x24
#define DISPLAYID_2_0_BLOCK_TYPE_RANGE_LIMITS 0x25
#define DISPLAYID_2_0_BLOCK_TYPE_INTERFACE_FEATURES 0x26
#define DISPLAYID_2_0_BLOCK_TYPE_STEREO 0x27
#define DISPLAYID_2_0_BLOCK_TYPE_TILED_DISPLAY 0x28
#define DISPLAYID_2_0_BLOCK_TYPE_CONTAINER_ID 0x29
#define DISPLAYID_2_0_BLOCK_TYPE_TIMING_10 0x2A
#define DISPLAYID_2_0_BLOCK_TYPE_ADAPTIVE_SYNC 0x2B
#define DISPLAYID_2_0_BLOCK_TYPE_ARVR_HMD 0x2C
#define DISPLAYID_2_0_BLOCK_TYPE_ARVR_LAYER 0x2D
#define DISPLAYID_2_0_BLOCK_TYPE_BRIGHTNESS_LUMINANCE_RANGE 0x2E
// 0x7D - 0x2F RESERVED for Additional VESA-defined Data Blocks
#define DISPLAYID_2_0_BLOCK_TYPE_VENDOR_SPEC 0x7E
// 0x80 - 0x7F RESERVED
#define DISPLAYID_2_0_BLOCK_TYPE_CTA_DATA 0x81
// 0xFF - 0x82 RESERVED for additional data blocks related to external standards organization(s).
// 0xFF - 0x82 RESERVED for additional data blocks related to external standards organization(s).
#define DISPLAYID_2_0_PRODUCT_NAME_STRING_MAX_LEN ((0xFB - 0xF) + 1)
@@ -184,7 +185,7 @@ typedef struct _tagDISPLAYID_2_0_DISPLAY_PARAM_BLOCK
DISPLAYID_2_0_COLOR_CHROMATICITY primary_color_3_chromaticity;
DISPLAYID_2_0_COLOR_CHROMATICITY white_point_chromaticity;
NvU8 max_luminance_full_coverage[2];
NvU8 max_luminance_1_percent_rectangular_coverage[2];
NvU8 max_luminance_10_percent_rectangular_coverage[2];
NvU8 min_luminance[2];
struct {
@@ -525,7 +526,7 @@ typedef struct _tagDISPLAYID_2_0_STEREO_INTERFACE_BLOCK_HEADER
NvU8 type;
NvU8 revision:3;
NvU8 reserved:3;
NvU8 stereo_timing_support:2;
NvU8 stereo_timing_support:2;
} DISPLAYID_2_0_STEREO_INTERFACE_BLOCK_HEADER;
typedef struct _tagDISPLAYID_2_0_STEREO_TIMING_DESCRIPTOR
@@ -692,7 +693,7 @@ typedef struct _tagDISPLAYID_2_0_ADAPTIVE_SYNC_DESCRIPTOR
NvU8 successive_frame_dec_tolerance : 1;
NvU8 reserved : 2;
} operation_range_info;
// 6.2 format (six integer bits and two fractional bits)
// six integer bits == 0 - 63ms
// two fractional bits == 0.00(00), 0.25(01b),0.50(10), 0.75(11b)
@@ -704,9 +705,9 @@ typedef struct _tagDISPLAYID_2_0_ADAPTIVE_SYNC_DESCRIPTOR
NvU8 max_rr_9_8 : 2;
NvU8 reserved : 6;
} max_refresh_rate;
// same as max_single_frame_inc expression
NvU8 max_single_frame_dec;
NvU8 max_single_frame_dec;
} DISPLAYID_2_0_ADAPTIVE_SYNC_DESCRIPTOR;
typedef struct _tagDISPLAYID_2_0_ADAPTIVE_SYNC_BLOCK
@@ -715,6 +716,16 @@ typedef struct _tagDISPLAYID_2_0_ADAPTIVE_SYNC_BLOCK
DISPLAYID_2_0_ADAPTIVE_SYNC_DESCRIPTOR descriptors[DISPLAYID_2_0_ADAPTIVE_SYNC_DETAILED_TIMING_COUNT];
} DISPLAYID_2_0_ADAPTIVE_SYNC_BLOCK;
// Payload value as defined in DID2.1 spec
#define DISPLAYID_2_0_BRIGHTNESS_LUMINANCE_RANGE_BLOCK_PAYLOAD_LENGTH 6
typedef struct _tagDISPLAYID_2_0_BRIGHTNESS_LUMINANCE_RANGE_BLOCK
{
DISPLAYID_2_0_DATA_BLOCK_HEADER header;
NvU16 min_sdr_luminance; // 0x03 ~ 0x04
NvU16 max_sdr_luminance; // 0x05 ~ 0x06
NvU16 max_boost_sdr_luminance; // 0x07 ~ 0x08
} DISPLAYID_2_0_BRIGHTNESS_LUMINANCE_RANGE_BLOCK;
typedef struct _tagDISPLAYID_2_0_VENDOR_SPECIFIC_BLOCK
{
DISPLAYID_2_0_DATA_BLOCK_HEADER header;
@@ -732,8 +743,43 @@ typedef struct _tagDISPLAYID_2_0_CTA_BLOCK
#pragma pack()
#endif
#ifdef __cplusplus
extern "C" {
#endif
// Entry point functions both used in DID20 and DID20ext
NVT_STATUS parseDisplayId20DataBlock(const DISPLAYID_2_0_DATA_BLOCK_HEADER *pDataBlock, NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo);
NvU8 computeDisplayId20SectionCheckSum(const NvU8 *pSectionBytes, NvU32 length);
#endif // __DISPLAYID20_H_
// DisplayID20 as EDID extension entry point function
NVT_STATUS parseDisplayId20EDIDExtSection(DISPLAYID_2_0_SECTION *section, NVT_EDID_INFO *pEdidInfo);
// DisplayID20 Entry point functions
NVT_STATUS parseDisplayId20BaseSection(const DISPLAYID_2_0_SECTION *pSection, NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo);
NVT_STATUS parseDisplayId20SectionDataBlocks(const DISPLAYID_2_0_SECTION *pSection, NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo);
NVT_STATUS parseDisplayId20ExtensionSection(const DISPLAYID_2_0_SECTION *pSection, NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo);
// DisplayID20 Data Block Tag Allocation
NVT_STATUS parseDisplayId20ProductIdentity(const DISPLAYID_2_0_DATA_BLOCK_HEADER *pDataBlock, NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo); // 0x20 Product Identificaton
NVT_STATUS parseDisplayId20DisplayParam(const DISPLAYID_2_0_DATA_BLOCK_HEADER *pDataBlock, NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo); // 0x21 Display Parameters
NVT_STATUS parseDisplayId20Timing7(const DISPLAYID_2_0_DATA_BLOCK_HEADER *pDataBlock, NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo); // 0x22 Type VII Timing - Detailed Timing
NVT_STATUS parseDisplayId20Timing8(const DISPLAYID_2_0_DATA_BLOCK_HEADER *pDataBlock, NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo); // 0x23 Type VIII Timing - Enumerated Timing
NVT_STATUS parseDisplayId20Timing9(const DISPLAYID_2_0_DATA_BLOCK_HEADER *pDataBlock, NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo); // 0x24 Type IX Timing - Formula-based
NVT_STATUS parseDisplayId20RangeLimit(const DISPLAYID_2_0_DATA_BLOCK_HEADER *pDataBlock, NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo); // 0x25 Dynamic Video Timing Range Limits
NVT_STATUS parseDisplayId20DisplayInterfaceFeatures(const DISPLAYID_2_0_DATA_BLOCK_HEADER *pDataBlock, NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo); // 0x26 Display Interface Features
NVT_STATUS parseDisplayId20Stereo(const DISPLAYID_2_0_DATA_BLOCK_HEADER *pDataBlock, NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo); // 0x27 Stereo Display Interface
NVT_STATUS parseDisplayId20TiledDisplay(const DISPLAYID_2_0_DATA_BLOCK_HEADER *pDataBlock, NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo); // 0x28 Tiled Display Topology
NVT_STATUS parseDisplayId20ContainerId(const DISPLAYID_2_0_DATA_BLOCK_HEADER *pDataBlock, NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo); // 0x29 ContainerID
NVT_STATUS parseDisplayId20Timing10(const DISPLAYID_2_0_DATA_BLOCK_HEADER *pDataBlock, NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo); // 0x2A Type X Timing - Formula-based Timing
NVT_STATUS parseDisplayId20AdaptiveSync(const DISPLAYID_2_0_DATA_BLOCK_HEADER *pDataBlock, NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo); // 0x2B Adaptive-Sync
NVT_STATUS parseDisplayId20ARVRHMD(const DISPLAYID_2_0_DATA_BLOCK_HEADER *pDataBlock, NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo); // 0x2C ARVR HMD
NVT_STATUS parseDisplayId20ARVRLayer(const DISPLAYID_2_0_DATA_BLOCK_HEADER *pDataBlock, NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo); // 0x2D ARVR Layer
NVT_STATUS parseDisplayId20BrightnessLuminanceRange(const DISPLAYID_2_0_DATA_BLOCK_HEADER *pDataBlock, NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo); // 0x2E Brightness Luminance Range
NVT_STATUS parseDisplayId20VendorSpecific(const DISPLAYID_2_0_DATA_BLOCK_HEADER *pDataBlock, NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo); // 0x7E Vendor-specific
NVT_STATUS parseDisplayId20CtaData(const DISPLAYID_2_0_DATA_BLOCK_HEADER *pDataBlock, NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo); // 0x81 CTA DisplayID
#ifdef __cplusplus
}
#endif
#endif // __DISPLAYID20_H_1

1
src/common/modeset/timing/dpsdp.h
View File

@@ -260,6 +260,7 @@ typedef struct tagDPSDP_DP_PR_VSC_SDP_DESCRIPTOR
NvU8 db6;
NvU8 db7;
// DB8 - DB15 are undefined in DP 1.3 spec.
NvU8 db8;
NvU8 db9;
NvU8 db10;
NvU8 db11;

130
src/common/modeset/timing/nvt_displayid20.c
View File

@@ -30,38 +30,13 @@
#include "nvBinSegment.h"
#include "nvmisc.h"
#include "nvtiming.h"
#include "nvtiming_pvt.h"
#include "displayid20.h"
PUSH_SEGMENTS
// DisplayID20 Entry point functions
static NVT_STATUS parseDisplayId20BaseSection(const DISPLAYID_2_0_SECTION *pSection, NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo);
static NVT_STATUS parseDisplayId20SectionDataBlocks(const DISPLAYID_2_0_SECTION *pSection, NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo);
static NVT_STATUS parseDisplayId20ExtensionSection(const DISPLAYID_2_0_SECTION *pSection, NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo);
// DisplayID20 Data Block Tag Alloction
static NVT_STATUS parseDisplayId20ProductIdentity(const DISPLAYID_2_0_DATA_BLOCK_HEADER *pDataBlock, NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo); // 0x20 Product Identificaton
static NVT_STATUS parseDisplayId20DisplayParam(const DISPLAYID_2_0_DATA_BLOCK_HEADER *pDataBlock, NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo); // 0x21 Display Parameters
static NVT_STATUS parseDisplayId20Timing7(const DISPLAYID_2_0_DATA_BLOCK_HEADER *pDataBlock, NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo); // 0x22 Type VII Timing - Detailed Timing
static NVT_STATUS parseDisplayId20Timing8(const DISPLAYID_2_0_DATA_BLOCK_HEADER *pDataBlock, NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo); // 0x23 Type VIII Timing - Enumerated Timing
static NVT_STATUS parseDisplayId20Timing9(const DISPLAYID_2_0_DATA_BLOCK_HEADER *pDataBlock, NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo); // 0x24 Type IX Timing - Formula-based
static NVT_STATUS parseDisplayId20RangeLimit(const DISPLAYID_2_0_DATA_BLOCK_HEADER *pDataBlock, NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo); // 0x25 Dynamic Video Timing Range Limits
static NVT_STATUS parseDisplayId20DisplayInterfaceFeatures(const DISPLAYID_2_0_DATA_BLOCK_HEADER *pDataBlock, NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo); // 0x26 Display Interface Features
static NVT_STATUS parseDisplayId20Stereo(const DISPLAYID_2_0_DATA_BLOCK_HEADER *pDataBlock, NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo); // 0x27 Stereo Display Interface
static NVT_STATUS parseDisplayId20TiledDisplay(const DISPLAYID_2_0_DATA_BLOCK_HEADER *pDataBlock, NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo); // 0x28 Tiled Display Topology
static NVT_STATUS parseDisplayId20ContainerId(const DISPLAYID_2_0_DATA_BLOCK_HEADER *pDataBlock, NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo); // 0x29 ContainerID
static NVT_STATUS parseDisplayId20Timing10(const DISPLAYID_2_0_DATA_BLOCK_HEADER *pDataBlock, NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo); // 0x2A Type X Timing - Formula-based Timing
static NVT_STATUS parseDisplayId20AdaptiveSync(const DISPLAYID_2_0_DATA_BLOCK_HEADER *pDataBlock, NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo); // 0x2B Adaptive-Sync
static NVT_STATUS parseDisplayId20ARVRHMD(const DISPLAYID_2_0_DATA_BLOCK_HEADER *pDataBlock, NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo); // 0x2C ARVR HMD
static NVT_STATUS parseDisplayId20ARVRLayer(const DISPLAYID_2_0_DATA_BLOCK_HEADER *pDataBlock, NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo); // 0x2D ARVR Layer
static NVT_STATUS parseDisplayId20VendorSpecific(const DISPLAYID_2_0_DATA_BLOCK_HEADER *pDataBlock, NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo); // 0x7E Vendor-specific
static NVT_STATUS parseDisplayId20CtaData(const DISPLAYID_2_0_DATA_BLOCK_HEADER *pDataBlock, NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo); // 0x81 CTA DisplayID
// Helper function
static NVT_STATUS getPrimaryUseCase(NvU8 product_type, NVT_DISPLAYID_PRODUCT_PRIMARY_USE_CASE *primary_use_case);
static NVT_STATUS parseDisplayId20Timing9Descriptor(const DISPLAYID_2_0_TIMING_9_DESCRIPTOR *pDescriptor, NVT_TIMING *pTiming, NvU8 count);
static NvU32 greatestCommonDenominator(NvU32 x, NvU32 y);
static NvU8 getExistedTimingSeqNumber(NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo, enum NVT_TIMING_TYPE);
@@ -141,7 +116,9 @@ NvTiming_parseDisplayId20Info(
return status;
}
NvU32 NvTiming_DisplayID2ValidationMask(
CODE_SEGMENT(PAGE_DD_CODE)
NvU32
NvTiming_DisplayID2ValidationMask(
NVT_DISPLAYID_2_0_INFO *pDisplayId20Info,
NvBool bIsStrongValidation)
{
@@ -215,7 +192,7 @@ NvTiming_DisplayID2ValidationDataBlocks(
// DisplayID20 Entry point functions
CODE_SEGMENT(PAGE_DD_CODE)
static NVT_STATUS
NVT_STATUS
parseDisplayId20BaseSection(
const DISPLAYID_2_0_SECTION *pSection,
NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo)
@@ -245,7 +222,7 @@ parseDisplayId20BaseSection(
}
CODE_SEGMENT(PAGE_DD_CODE)
static NVT_STATUS
NVT_STATUS
parseDisplayId20ExtensionSection(
const DISPLAYID_2_0_SECTION *pSection,
NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo)
@@ -269,7 +246,7 @@ parseDisplayId20ExtensionSection(
}
CODE_SEGMENT(PAGE_DD_CODE)
static NVT_STATUS
NVT_STATUS
parseDisplayId20SectionDataBlocks(
const DISPLAYID_2_0_SECTION *pSection,
NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo)
@@ -355,31 +332,34 @@ parseDisplayId20SectionDataBlocks(
}
break;
case DISPLAYID_2_0_BLOCK_TYPE_STEREO:
pDisplayIdInfo->valid_data_blocks.stereo_interface_present = NV_TRUE;
pDisplayIdInfo->valid_data_blocks.stereo_interface_present = NV_TRUE;
break;
case DISPLAYID_2_0_BLOCK_TYPE_TILED_DISPLAY:
pDisplayIdInfo->valid_data_blocks.tiled_display_present = NV_TRUE;
pDisplayIdInfo->valid_data_blocks.tiled_display_present = NV_TRUE;
break;
case DISPLAYID_2_0_BLOCK_TYPE_CONTAINER_ID:
pDisplayIdInfo->valid_data_blocks.container_id_present = NV_TRUE;
pDisplayIdInfo->valid_data_blocks.container_id_present = NV_TRUE;
break;
case DISPLAYID_2_0_BLOCK_TYPE_TIMING_10:
pDisplayIdInfo->valid_data_blocks.type10Timing_present = NV_TRUE;
pDisplayIdInfo->valid_data_blocks.type10Timing_present = NV_TRUE;
break;
case DISPLAYID_2_0_BLOCK_TYPE_ADAPTIVE_SYNC:
pDisplayIdInfo->valid_data_blocks.adaptive_sync_present = NV_TRUE;
pDisplayIdInfo->valid_data_blocks.adaptive_sync_present = NV_TRUE;
break;
case DISPLAYID_2_0_BLOCK_TYPE_ARVR_HMD:
pDisplayIdInfo->valid_data_blocks.arvr_hmd_present = NV_TRUE;
pDisplayIdInfo->valid_data_blocks.arvr_hmd_present = NV_TRUE;
break;
case DISPLAYID_2_0_BLOCK_TYPE_ARVR_LAYER:
pDisplayIdInfo->valid_data_blocks.arvr_layer_present = NV_TRUE;
pDisplayIdInfo->valid_data_blocks.arvr_layer_present = NV_TRUE;
break;
case DISPLAYID_2_0_BLOCK_TYPE_BRIGHTNESS_LUMINANCE_RANGE:
pDisplayIdInfo->valid_data_blocks.brightness_luminance_range_present = NV_TRUE;
break;
case DISPLAYID_2_0_BLOCK_TYPE_VENDOR_SPEC:
pDisplayIdInfo->valid_data_blocks.vendor_specific_present = NV_TRUE;
pDisplayIdInfo->valid_data_blocks.vendor_specific_present = NV_TRUE;
break;
case DISPLAYID_2_0_BLOCK_TYPE_CTA_DATA:
pDisplayIdInfo->valid_data_blocks.cta_data_present = NV_TRUE;
pDisplayIdInfo->valid_data_blocks.cta_data_present = NV_TRUE;
break;
default:
status = NVT_STATUS_ERR;
@@ -444,6 +424,9 @@ parseDisplayId20DataBlock(
case DISPLAYID_2_0_BLOCK_TYPE_ARVR_LAYER:
status = parseDisplayId20ARVRLayer(pDataBlock, pDisplayIdInfo);
break;
case DISPLAYID_2_0_BLOCK_TYPE_BRIGHTNESS_LUMINANCE_RANGE:
status = parseDisplayId20BrightnessLuminanceRange(pDataBlock, pDisplayIdInfo);
break;
case DISPLAYID_2_0_BLOCK_TYPE_VENDOR_SPEC:
status = parseDisplayId20VendorSpecific(pDataBlock, pDisplayIdInfo);
break;
@@ -503,7 +486,7 @@ parseDisplayId20ProductIdentity(
CODE_SEGMENT(PAGE_DD_CODE)
static NVT_STATUS
NVT_STATUS
parseDisplayId20DisplayParam(
const DISPLAYID_2_0_DATA_BLOCK_HEADER *pDataBlock,
NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo)
@@ -561,8 +544,8 @@ parseDisplayId20DisplayParam(
// IEEE 754 half-precision binary floating-point format
pDisplayParam->native_max_luminance_full_coverage = pDisplayParamBlock->max_luminance_full_coverage[1] << 8 |
pDisplayParamBlock->max_luminance_full_coverage[0];
pDisplayParam->native_max_luminance_1_percent_rect_coverage = pDisplayParamBlock->max_luminance_1_percent_rectangular_coverage[1] << 8 |
pDisplayParamBlock->max_luminance_1_percent_rectangular_coverage[0];
pDisplayParam->native_max_luminance_10_percent_rect_coverage = pDisplayParamBlock->max_luminance_10_percent_rectangular_coverage[1] << 8 |
pDisplayParamBlock->max_luminance_10_percent_rectangular_coverage[0];
pDisplayParam->native_min_luminance = pDisplayParamBlock->min_luminance[1] << 8 |
pDisplayParamBlock->min_luminance[0];
@@ -598,7 +581,7 @@ parseDisplayId20DisplayParam(
}
CODE_SEGMENT(PAGE_DD_CODE)
static NVT_STATUS
NVT_STATUS
parseDisplayId20Timing7(
const DISPLAYID_2_0_DATA_BLOCK_HEADER *pDataBlock,
NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo)
@@ -687,7 +670,7 @@ parseDisplayId20Timing7(
}
CODE_SEGMENT(PAGE_DD_CODE)
static NVT_STATUS
NVT_STATUS
parseDisplayId20Timing8(
const DISPLAYID_2_0_DATA_BLOCK_HEADER *pDataBlock,
NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo)
@@ -751,7 +734,7 @@ parseDisplayId20Timing8(
}
CODE_SEGMENT(PAGE_DD_CODE)
static NVT_STATUS
NVT_STATUS
parseDisplayId20Timing9(
const DISPLAYID_2_0_DATA_BLOCK_HEADER *pDataBlock,
NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo)
@@ -798,7 +781,7 @@ parseDisplayId20Timing9(
}
CODE_SEGMENT(PAGE_DD_CODE)
static NVT_STATUS
NVT_STATUS
parseDisplayId20Timing10(
const DISPLAYID_2_0_DATA_BLOCK_HEADER *pDataBlock,
NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo)
@@ -909,7 +892,7 @@ parseDisplayId20Timing10(
}
CODE_SEGMENT(PAGE_DD_CODE)
static NVT_STATUS
NVT_STATUS
parseDisplayId20RangeLimit(
const DISPLAYID_2_0_DATA_BLOCK_HEADER *pDataBlock,
NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo)
@@ -970,7 +953,7 @@ parseDisplayId20RangeLimit(
} while(0)
CODE_SEGMENT(PAGE_DD_CODE)
static NVT_STATUS
NVT_STATUS
parseDisplayId20DisplayInterfaceFeatures(
const DISPLAYID_2_0_DATA_BLOCK_HEADER *pDataBlock,
NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo)
@@ -1088,7 +1071,7 @@ parseDisplayId20DisplayInterfaceFeatures(
}
CODE_SEGMENT(PAGE_DD_CODE)
static NVT_STATUS
NVT_STATUS
parseDisplayId20Stereo(
const DISPLAYID_2_0_DATA_BLOCK_HEADER *pDataBlock,
NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo)
@@ -1103,7 +1086,7 @@ parseDisplayId20Stereo(
}
CODE_SEGMENT(PAGE_DD_CODE)
static NVT_STATUS
NVT_STATUS
parseDisplayId20TiledDisplay(
const DISPLAYID_2_0_DATA_BLOCK_HEADER *pDataBlock,
NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo)
@@ -1166,7 +1149,7 @@ parseDisplayId20TiledDisplay(
}
CODE_SEGMENT(PAGE_DD_CODE)
static NVT_STATUS
NVT_STATUS
parseDisplayId20ContainerId(
const DISPLAYID_2_0_DATA_BLOCK_HEADER *pDataBlock,
NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo)
@@ -1207,7 +1190,7 @@ parseDisplayId20ContainerId(
}
CODE_SEGMENT(PAGE_DD_CODE)
static NVT_STATUS
NVT_STATUS
parseDisplayId20AdaptiveSync(
const DISPLAYID_2_0_DATA_BLOCK_HEADER *pDataBlock,
NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo)
@@ -1279,7 +1262,7 @@ parseDisplayId20AdaptiveSync(
}
CODE_SEGMENT(PAGE_DD_CODE)
static NVT_STATUS
NVT_STATUS
parseDisplayId20ARVRHMD(
const DISPLAYID_2_0_DATA_BLOCK_HEADER *pDataBlock,
NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo)
@@ -1294,7 +1277,7 @@ parseDisplayId20ARVRHMD(
}
CODE_SEGMENT(PAGE_DD_CODE)
static NVT_STATUS
NVT_STATUS
parseDisplayId20ARVRLayer(
const DISPLAYID_2_0_DATA_BLOCK_HEADER *pDataBlock,
NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo)
@@ -1308,10 +1291,36 @@ parseDisplayId20ARVRLayer(
return status;
}
CODE_SEGMENT(PAGE_DD_CODE)
NVT_STATUS
parseDisplayId20BrightnessLuminanceRange(
const DISPLAYID_2_0_DATA_BLOCK_HEADER *pDataBlock,
NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo)
{
NVT_STATUS status = NVT_STATUS_SUCCESS;
const DISPLAYID_2_0_BRIGHTNESS_LUMINANCE_RANGE_BLOCK *pBrightnessLuminanceRangeBlock = NULL;
NVT_DISPLAYID_BRIGHTNESS_LUMINANCE_RANGE *pluminanceRanges = NULL;
if ((pDataBlock == NULL) || pDataBlock->data_bytes != DISPLAYID_2_0_BRIGHTNESS_LUMINANCE_RANGE_BLOCK_PAYLOAD_LENGTH)
{
return NVT_STATUS_ERR;
}
if (pDisplayIdInfo == NULL) return status;
pBrightnessLuminanceRangeBlock = (const DISPLAYID_2_0_BRIGHTNESS_LUMINANCE_RANGE_BLOCK *)pDataBlock;
pluminanceRanges = &pDisplayIdInfo->luminance_ranges;
pluminanceRanges->revision = pDataBlock->revision;
pluminanceRanges->min_sdr_luminance = pBrightnessLuminanceRangeBlock->min_sdr_luminance;
pluminanceRanges->max_sdr_luminance = pBrightnessLuminanceRangeBlock->max_sdr_luminance;
pluminanceRanges->max_boost_sdr_luminance = pBrightnessLuminanceRangeBlock->max_boost_sdr_luminance;
return status;
}
CODE_SEGMENT(PAGE_DD_CODE)
static NVT_STATUS
NVT_STATUS
parseDisplayId20VendorSpecific(
const DISPLAYID_2_0_DATA_BLOCK_HEADER *pDataBlock,
NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo)
@@ -1365,7 +1374,7 @@ parseDisplayId20VendorSpecific(
}
CODE_SEGMENT(PAGE_DD_CODE)
static NVT_STATUS
NVT_STATUS
parseDisplayId20CtaData(
const DISPLAYID_2_0_DATA_BLOCK_HEADER *pDataBlock,
NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo)
@@ -1399,6 +1408,8 @@ parseDisplayId20CtaData(
p861Info = &(pDisplayIdInfo->cta.cta861_info);
parseCta861VsdbBlocks(p861Info, pDisplayIdInfo, FROM_DISPLAYID_20_DATA_BLOCK);
parseCta861VsvdbBlocks(p861Info, pDisplayIdInfo, FROM_DISPLAYID_20_DATA_BLOCK);
parseCta861HfScdb(p861Info, pDisplayIdInfo, FROM_DISPLAYID_20_DATA_BLOCK);
// This CTA 861 function to parse 861 part
parse861bShortTiming(p861Info, pDisplayIdInfo, FROM_DISPLAYID_20_DATA_BLOCK);
@@ -1406,8 +1417,6 @@ parseDisplayId20CtaData(
parse861bShortYuv420Timing(p861Info, pDisplayIdInfo, FROM_DISPLAYID_20_DATA_BLOCK);
parseCea861HdrStaticMetadataDataBlock(p861Info, pDisplayIdInfo, FROM_DISPLAYID_20_DATA_BLOCK);
parseCea861DvStaticMetadataDataBlock(p861Info, pDisplayIdInfo, FROM_DISPLAYID_20_DATA_BLOCK);
parseCea861Hdr10PlusDataBlock(p861Info, pDisplayIdInfo, FROM_DISPLAYID_20_DATA_BLOCK);
// CEA861-F at 7.5.12 section about VFPDB block.
if (p861Info->total_svr > 0)
@@ -1694,17 +1703,20 @@ parseDisplayId20Timing8Descriptor(
}
CODE_SEGMENT(PAGE_DD_CODE)
static NVT_STATUS
NVT_STATUS
parseDisplayId20Timing9Descriptor(
const DISPLAYID_2_0_TIMING_9_DESCRIPTOR *pDescriptor,
const void *pVoidDescriptor,
NVT_TIMING *pTiming,
NvU8 count)
{
NVT_STATUS status = NVT_STATUS_SUCCESS;
const DISPLAYID_2_0_TIMING_9_DESCRIPTOR* pDescriptor = NULL;
NvU32 width = 0;
NvU32 height = 0;
NvU32 rr = 0;
pDescriptor = (const DISPLAYID_2_0_TIMING_9_DESCRIPTOR *)pVoidDescriptor;
width = (pDescriptor->horizontal_active_pixels[1] << 8 | pDescriptor->horizontal_active_pixels[0]) + 1;
height = (pDescriptor->vertical_active_lines[1] << 8 | pDescriptor->vertical_active_lines[0]) + 1;
rr = pDescriptor->refresh_rate + 1;

156
src/common/modeset/timing/nvt_dsc_pps.c
View File

@@ -1219,6 +1219,45 @@ DSC_GetPeakThroughputMps(NvU32 peak_throughput)
return peak_throughput_mps;
}
/*
* @brief Get slice count mask upto max slice count.
*
* @param[in] max_slice_num max slice number to be considered while generating mask
* @param[in] bInclusive maximum slice number should be included in mask or not
*
* @returns slice count mask of all slice counts up to max slice count
*/
static NvU32
DSC_GetSliceCountMask
(
NvU32 maxSliceNum,
NvBool bInclusive
)
{
// Below are the valid slice counts according to DP2.0 spec.
NvU32 validSliceNum[] = {1,2,4,6,8,10,12,16,20,24};
NvU32 sliceCountMask = 0;
NvU32 sliceArrayCount;
NvU32 i;
sliceArrayCount = sizeof(validSliceNum)/sizeof(NvU32);
if (maxSliceNum == 0)
return 0;
for(i = 0; ((i < sliceArrayCount) && (validSliceNum[i] < maxSliceNum)); i++)
{
sliceCountMask |= NVBIT(validSliceNum[i] - 1);
}
if (bInclusive && (i < sliceArrayCount))
{
sliceCountMask |= NVBIT(validSliceNum[i] - 1);
}
return sliceCountMask;
}
/*
* @brief Get the next higher valid slice count.
*
@@ -1304,39 +1343,30 @@ DSC_PpsCalcSliceParams
NvU32 min_slice_num;
NvU32 slicew;
NvU32 peak_throughput_mps;
//
// Bits 0,1,3,4,5 represents slice counts 1,2,4,6,8.
// Bit 2 is reserved and Slice count = 6 is not supported
// by GPU, so that is not required to be set.
//
NvU32 gpu_slice_count_mask = DSC_DECODER_SLICES_PER_SINK_1 |
DSC_DECODER_SLICES_PER_SINK_2 |
DSC_DECODER_SLICES_PER_SINK_4;
NvU32 common_slice_count_mask;
NvU32 gpu_slice_count_mask;
NvU32 gpu_slice_count_mask_dual = DSC_DECODER_SLICES_PER_SINK_2 |
DSC_DECODER_SLICES_PER_SINK_4 |
DSC_DECODER_SLICES_PER_SINK_8;
gpu_slice_count_mask = DSC_GetSliceCountMask(max_slice_num, NV_TRUE /*bInclusive*/);
NvU32 common_slice_count_mask = dual_mode? gpu_slice_count_mask_dual & slice_count_mask :
gpu_slice_count_mask & slice_count_mask;
if (dual_mode)
{
// remove slice count 1 as it is not valid for 2Head1OR case.
gpu_slice_count_mask &= ~(0x1);
}
common_slice_count_mask = gpu_slice_count_mask & slice_count_mask;
if (!common_slice_count_mask)
{
DSC_Print("DSC cannot be supported since no common supported slice count\n");
return NVT_STATUS_ERR;
return NVT_STATUS_DSC_SLICE_ERROR;
}
peak_throughput_mps = DSC_GetPeakThroughputMps(peak_throughput);
if (!peak_throughput_mps)
{
DSC_Print("Peak throughput cannot be zero.\n");
return NVT_STATUS_ERR;
}
if (max_slice_width > MAX_WIDTH_PER_SLICE)
{
DSC_Print("GPU can support only a max of 5120 pixels across all slices\n");
max_slice_width = MAX_WIDTH_PER_SLICE;
return NVT_STATUS_INVALID_PEAK_THROUGHPUT;
}
if (out->slice_num == 0 && out->slice_width == 0)
@@ -1349,7 +1379,7 @@ DSC_PpsCalcSliceParams
if (max_slice_num < min_slice_num)
{
DSC_Print("Requested mode cannot be supported with DSC\n");
return NVT_STATUS_ERR;
return NVT_STATUS_MIN_SLICE_COUNT_ERROR;
}
if (!(DSC_SliceCountMaskforSliceNum(min_slice_num) & common_slice_count_mask))
@@ -1357,7 +1387,7 @@ DSC_PpsCalcSliceParams
if (DSC_GetHigherSliceCount(common_slice_count_mask, min_slice_num, dual_mode, &new_slice_num) == NVT_STATUS_ERR)
{
DSC_Print("DSC cannot be enabled for this mode\n");
return NVT_STATUS_ERR;
return NVT_STATUS_MIN_SLICE_COUNT_ERROR;
}
else
{
@@ -1376,14 +1406,14 @@ DSC_PpsCalcSliceParams
if (out->slice_width > max_slice_width)
{
DSC_Print("Error! Max Supported Slice Width = %u\n", max_slice_width);
return NVT_STATUS_ERR;
return NVT_STATUS_PPS_SLICE_WIDTH_ERROR;
}
out->slice_num = (out->pic_width + out->slice_width - 1) / out->slice_width;
if (!(DSC_SliceCountMaskforSliceNum(out->slice_num) & common_slice_count_mask))
{
DSC_Print("Slice count corresponding to requested slice_width is not supported\n");
return NVT_STATUS_ERR;
return NVT_STATUS_PPS_SLICE_COUNT_ERROR;
}
}
else if (out->slice_width == 0)
@@ -1391,7 +1421,7 @@ DSC_PpsCalcSliceParams
if (!(DSC_SliceCountMaskforSliceNum(out->slice_num) & common_slice_count_mask))
{
DSC_Print("Slice count requested is not supported\n");
return NVT_STATUS_ERR;
return NVT_STATUS_PPS_SLICE_COUNT_ERROR;
}
out->slice_width = (out->pic_width + out->slice_num - 1) / out->slice_num;
@@ -1404,7 +1434,7 @@ DSC_PpsCalcSliceParams
if (out->slice_width > max_slice_width)
{
DSC_Print("Slice width corresponding to the requested slice count is not supported\n");
return NVT_STATUS_ERR;
return NVT_STATUS_PPS_SLICE_WIDTH_ERROR;
}
}
else
@@ -1412,19 +1442,19 @@ DSC_PpsCalcSliceParams
if (!(DSC_SliceCountMaskforSliceNum(out->slice_num) & common_slice_count_mask))
{
DSC_Print("Requested slice count is not supported\n");
return NVT_STATUS_ERR;
return NVT_STATUS_PPS_SLICE_COUNT_ERROR;
}
if (out->slice_width > max_slice_width)
{
DSC_Print("Requested slice width cannot be supported\n");
return NVT_STATUS_ERR;
return NVT_STATUS_PPS_SLICE_WIDTH_ERROR;
}
if (out->slice_width != (out->pic_width + out->slice_num - 1) / out->slice_num)
{
DSC_Print("slice_width must equal CEIL(pic_width/slice_num) \n");
return NVT_STATUS_ERR;
return NVT_STATUS_PPS_SLICE_WIDTH_ERROR;
}
}
@@ -1442,7 +1472,7 @@ DSC_PpsCalcSliceParams
if (out->slice_width < 32)
{
DSC_Print("slice_width must >= 32\n");
return NVT_STATUS_ERR;
return NVT_STATUS_PPS_SLICE_WIDTH_ERROR;
}
slicew = out->slice_width >> (out->native_420 || out->native_422); // /2 in 4:2:0 mode
@@ -1509,7 +1539,7 @@ Dsc_PpsCalcHeight(DSC_OUTPUT_PARAMS *out)
return NVT_STATUS_SUCCESS;
}
DSC_Print("Error! can't find valid slice_height");
return NVT_STATUS_ERR;
return NVT_STATUS_PPS_SLICE_HEIGHT_ERROR;
}
RANGE_CHECK("slice_height", out->slice_height, 8, out->pic_height);
@@ -1517,13 +1547,13 @@ Dsc_PpsCalcHeight(DSC_OUTPUT_PARAMS *out)
if (out->pic_height % out->slice_height != 0)
{
DSC_Print("Error! pic_height %% slice_height must be 0");
return NVT_STATUS_ERR;
return NVT_STATUS_PPS_SLICE_HEIGHT_ERROR;
}
if(DSC_PpsCheckSliceHeight(out) != NVT_STATUS_SUCCESS)
{
DSC_Print("Error! slice_height not valid");
return NVT_STATUS_ERR;
return NVT_STATUS_PPS_SLICE_HEIGHT_ERROR;
}
return NVT_STATUS_SUCCESS;
}
@@ -1711,26 +1741,26 @@ _validateInput
if (pDscInfo->forcedDscParams.sliceCount > pDscInfo->sinkCaps.maxNumHztSlices)
{
DSC_Print("ERROR - Client can't specify forced slice count greater than what sink supports.");
return NVT_STATUS_INVALID_PARAMETER;
return NVT_STATUS_DSC_SLICE_ERROR;
}
if ((pDscInfo->forcedDscParams.sliceCount / (pModesetInfo->bDualMode ? 2 : 1)) > pDscInfo->gpuCaps.maxNumHztSlices)
{
DSC_Print("ERROR - Client can't specify forced slice count greater than what GPU supports.");
return NVT_STATUS_INVALID_PARAMETER;
return NVT_STATUS_DSC_SLICE_ERROR;
}
if (pDscInfo->forcedDscParams.sliceWidth > pDscInfo->sinkCaps.maxSliceWidth)
{
DSC_Print("ERROR - Client can't specify forced slice width greater than what sink supports.");
return NVT_STATUS_INVALID_PARAMETER;
return NVT_STATUS_DSC_SLICE_ERROR;
}
if ((pDscInfo->forcedDscParams.sliceCount > 0) &&
(pDscInfo->forcedDscParams.sliceWidth != 0))
{
DSC_Print("ERROR - Client can't specify both forced slice count and slice width.");
return NVT_STATUS_INVALID_PARAMETER;
return NVT_STATUS_DSC_SLICE_ERROR;
}
if ((pDscInfo->forcedDscParams.sliceCount != 0) &&
@@ -1740,19 +1770,19 @@ _validateInput
(pDscInfo->forcedDscParams.sliceCount != 8))
{
DSC_Print("ERROR - Forced Slice Count has to be 1/2/4/8.");
return NVT_STATUS_INVALID_PARAMETER;
return NVT_STATUS_DSC_SLICE_ERROR;
}
if (pDscInfo->forcedDscParams.sliceWidth > pModesetInfo->activeWidth)
{
DSC_Print("ERROR - Forced Slice Width can't be more than Active Width.");
return NVT_STATUS_INVALID_PARAMETER;
return NVT_STATUS_DSC_SLICE_ERROR;
}
if (pDscInfo->forcedDscParams.sliceHeight > pModesetInfo->activeHeight)
{
DSC_Print("ERROR - Forced Slice Height can't be more than Active Height.");
return NVT_STATUS_INVALID_PARAMETER;
return NVT_STATUS_DSC_SLICE_ERROR;
}
if (pDscInfo->forcedDscParams.dscRevision.versionMinor >
@@ -1778,7 +1808,7 @@ _validateInput
(pModesetInfo->pixelClockHz > pDscInfo->branchCaps.overallThroughputMode0 * MHZ_TO_HZ))
{
DSC_Print("ERROR - Pixel clock cannot be greater than Branch DSC Overall Throughput Mode 0");
return NVT_STATUS_INVALID_PARAMETER;
return NVT_STATUS_OVERALL_THROUGHPUT_ERROR;
}
if (pModesetInfo->activeWidth == 0)
@@ -1791,7 +1821,7 @@ _validateInput
pModesetInfo->activeWidth > pDscInfo->branchCaps.maxLineBufferWidth)
{
DSC_Print("ERROR - Active width cannot be greater than DSC Decompressor max line buffer width");
return NVT_STATUS_INVALID_PARAMETER;
return NVT_STATUS_MAX_LINE_BUFFER_ERROR;
}
if (pModesetInfo->activeHeight == 0)
@@ -1824,7 +1854,7 @@ _validateInput
(pDscInfo->sinkCaps.decoderColorFormatMask & DSC_DECODER_COLOR_FORMAT_Y_CB_CR_NATIVE_422))))
{
DSC_Print("ERROR - Can't enable YCbCr422 with current GPU and Sink DSC config.");
return NVT_STATUS_INVALID_PARAMETER;
return NVT_STATUS_COLOR_FORMAT_NOT_SUPPORTED;
}
}
@@ -1837,7 +1867,7 @@ _validateInput
(pDscInfo->sinkCaps.decoderColorFormatMask & DSC_DECODER_COLOR_FORMAT_Y_CB_CR_NATIVE_420)))
{
DSC_Print("ERROR - Can't enable YCbCr420 with current GPU and Sink DSC config.");
return NVT_STATUS_INVALID_PARAMETER;
return NVT_STATUS_COLOR_FORMAT_NOT_SUPPORTED;
}
}
@@ -1863,21 +1893,21 @@ _validateInput
if (!(pDscInfo->sinkCaps.decoderColorDepthMask & DSC_DECODER_COLOR_DEPTH_CAPS_12_BITS))
{
DSC_Print("ERROR - Sink DSC Decoder does not support 12 bpc");
return NVT_STATUS_INVALID_PARAMETER;
return NVT_STATUS_INVALID_BPC;
}
break;
case 10:
if (!(pDscInfo->sinkCaps.decoderColorDepthMask & DSC_DECODER_COLOR_DEPTH_CAPS_10_BITS))
{
DSC_Print("ERROR - Sink DSC Decoder does not support 10 bpc");
return NVT_STATUS_INVALID_PARAMETER;
return NVT_STATUS_INVALID_BPC;
}
break;
case 8:
if (!(pDscInfo->sinkCaps.decoderColorDepthMask & DSC_DECODER_COLOR_DEPTH_CAPS_8_BITS))
{
DSC_Print("ERROR - Sink DSC Decoder does not support 8 bpc");
return NVT_STATUS_INVALID_PARAMETER;
return NVT_STATUS_INVALID_BPC;
}
break;
@@ -1917,7 +1947,7 @@ _validateInput
if (pWARData->dpData.hBlank > MAX_HBLANK_PIXELS)
{
DSC_Print("ERROR - Incorrect DP HBlank info sent with WAR data");
return NVT_STATUS_INVALID_PARAMETER;
return NVT_STATUS_INVALID_HBLANK;
}
if ((pWARData->dpData.dpMode != DSC_DP_SST) && (pWARData->dpData.dpMode != DSC_DP_MST))
@@ -2016,7 +2046,7 @@ DSC_GeneratePPS
else
{
DSC_Print("ERROR - YCbCr422 is not possible with current config.");
ret = NVT_STATUS_INVALID_PARAMETER;
ret = NVT_STATUS_COLOR_FORMAT_NOT_SUPPORTED;
goto done;
}
break;
@@ -2031,14 +2061,14 @@ DSC_GeneratePPS
else
{
DSC_Print("ERROR - YCbCr420 is not possible with current config.");
ret = NVT_STATUS_INVALID_PARAMETER;
ret = NVT_STATUS_COLOR_FORMAT_NOT_SUPPORTED;
goto done;
}
break;
default:
DSC_Print("ERROR - Invalid color Format specified.");
ret = NVT_STATUS_INVALID_PARAMETER;
ret = NVT_STATUS_COLOR_FORMAT_NOT_SUPPORTED;
goto done;
}
@@ -2145,7 +2175,7 @@ DSC_GeneratePPS
(*pBitsPerPixelX16 > in->bits_per_pixel))
{
DSC_Print("ERROR - Invalid bits per pixel value specified.");
ret = NVT_STATUS_INVALID_PARAMETER;
ret = NVT_STATUS_INVALID_BPP;
goto done;
}
else
@@ -2157,14 +2187,14 @@ DSC_GeneratePPS
if (pModesetInfo->bDualMode && (in->bits_per_pixel > 256 /*bits_per_pixel = 16*/))
{
DSC_Print("ERROR - DSC Dual Mode, because of architectural limitation we can't use bits_per_pixel more than 16.");
ret = NVT_STATUS_INVALID_PARAMETER;
ret = NVT_STATUS_INVALID_BPP;
goto done;
}
if ((pDscInfo->sinkCaps.maxBitsPerPixelX16 != 0) && (*pBitsPerPixelX16 > pDscInfo->sinkCaps.maxBitsPerPixelX16))
{
DSC_Print("ERROR - bits per pixel value specified by user is greater than what DSC decompressor can support.");
ret = NVT_STATUS_INVALID_PARAMETER;
ret = NVT_STATUS_INVALID_BPP;
goto done;
}
}
@@ -2195,6 +2225,13 @@ DSC_GeneratePPS
}
}
if (pModesetInfo->bDualMode && (pDscInfo->gpuCaps.maxNumHztSlices > 4U))
{
DSC_Print("ERROR - Dual Mode should not be set when GPU can support more than 4 slices per head.");
ret = NVT_STATUS_INVALID_PARAMETER;
goto done;
}
in->dsc_version_minor = pDscInfo->forcedDscParams.dscRevision.versionMinor ? pDscInfo->forcedDscParams.dscRevision.versionMinor :
pDscInfo->sinkCaps.algorithmRevision.versionMinor;
in->pic_width = pModesetInfo->activeWidth;
@@ -2204,7 +2241,8 @@ DSC_GeneratePPS
in->slice_num = pDscInfo->forcedDscParams.sliceCount;
in->max_slice_num = MIN(pDscInfo->sinkCaps.maxNumHztSlices,
pModesetInfo->bDualMode ? pDscInfo->gpuCaps.maxNumHztSlices * 2 : pDscInfo->gpuCaps.maxNumHztSlices);
in->max_slice_width = pDscInfo->sinkCaps.maxSliceWidth;
// lineBufferSize is reported in 1024 units by HW, so need to multiply by 1024 to get pixels.
in->max_slice_width = MIN(pDscInfo->sinkCaps.maxSliceWidth, pDscInfo->gpuCaps.lineBufferSize * 1024);
in->pixel_clkMHz = (NvU32)(pModesetInfo->pixelClockHz / 1000000L);
in->dual_mode = pModesetInfo->bDualMode;
in->drop_mode = pModesetInfo->bDropMode;
@@ -2217,7 +2255,7 @@ DSC_GeneratePPS
if (in->dsc_version_minor == 1)
{
DSC_Print("Error! DSC1.1 can't support native422!\n");
ret = NVT_STATUS_INVALID_PARAMETER;
ret = NVT_STATUS_COLOR_FORMAT_NOT_SUPPORTED;
goto done;
}
//the bpp in native 422 mode is doubled.
@@ -2226,7 +2264,7 @@ DSC_GeneratePPS
{
DSC_Print("bits_per_pixelx16 (=%u) needs to be between %u and %u",
in->bits_per_pixel, 2*6*BPP_UNIT, 2*32*BPP_UNIT-1);
ret = NVT_STATUS_INVALID_PARAMETER;
ret = NVT_STATUS_INVALID_BPP;
goto done;
}
}
@@ -2237,7 +2275,7 @@ DSC_GeneratePPS
{
DSC_Print("bits_per_pixelx16 (=%u) needs to be between %u and %u",
in->bits_per_pixel, 8*BPP_UNIT, 32*BPP_UNIT);
ret = NVT_STATUS_INVALID_PARAMETER;
ret = NVT_STATUS_INVALID_BPP;
goto done;
}
}

72
src/common/modeset/timing/nvt_edid.c
View File

@@ -1053,16 +1053,11 @@ NVT_STATUS NV_STDCALL NvTiming_ParseEDIDInfo(NvU8 *pEdid, NvU32 length, NVT_EDID
// parseCta861VsdbBlocks() uses hfScdb info so need to be parsed first
parseCta861HfScdb(p861Info, pInfo, FROM_CTA861_EXTENSION);
parseCta861VsdbBlocks(p861Info, pInfo, FROM_CTA861_EXTENSION);
parseCta861VsvdbBlocks(p861Info, pInfo, FROM_CTA861_EXTENSION);
// parse HDR related information from the HDR static metadata data block
parseCea861HdrStaticMetadataDataBlock(p861Info, pInfo, FROM_CTA861_EXTENSION);
// parse Dolby Vision related information from the DV vendor specific video data block
parseCea861DvStaticMetadataDataBlock(p861Info, pInfo, FROM_CTA861_EXTENSION);
// parse HDR10+ related information from the HDR10+ LLC Vendor Specific Video Data Block
parseCea861Hdr10PlusDataBlock(p861Info, pInfo, FROM_CTA861_EXTENSION);
// Timings are listed (or shall) be listed in priority order
// So read SVD, yuv420 SVDs first before reading detailed timings
@@ -1443,6 +1438,7 @@ NVT_STATUS NvTiming_Get18ByteLongDescriptorIndex(NVT_EDID_INFO *pEdidInfo, NvU8
CODE_SEGMENT(PAGE_DD_CODE)
NVT_STATUS NvTiming_GetEdidTimingEx(NvU32 width, NvU32 height, NvU32 rr, NvU32 flag, NVT_EDID_INFO *pEdidInfo, NVT_TIMING *pT, NvU32 rrx1k)
{
NvU8 kth = 0;
NvU32 i, j;
NvU32 native_cta, preferred_cta, preferred_displayid_dtd, preferred_dtd1, dtd1, map0, map1, map2, map3, map4, ceaIndex, max, cvt;
NVT_TIMING *pEdidTiming;
@@ -1474,6 +1470,12 @@ NVT_STATUS NvTiming_GetEdidTimingEx(NvU32 width, NvU32 height, NvU32 rr, NvU32 f
// max - the timing with the max visible area
native_cta = preferred_cta = preferred_displayid_dtd = preferred_dtd1 = dtd1 = map0 = map1 = map2 = map3 = map4 = ceaIndex = pEdidInfo->total_timings;
max = cvt = 0;
if (pEdidInfo->ext861.total_svr > 1)
{
kth = getHighestPrioritySVRIdx(pEdidInfo->ext861.svr_vfpdb[0]);
}
for (i = 0; i < pEdidInfo->total_timings; i++)
{
// if the client prefers _NATIVE timing, then don't select custom timing
@@ -1542,7 +1544,25 @@ NVT_STATUS NvTiming_GetEdidTimingEx(NvU32 width, NvU32 height, NvU32 rr, NvU32 f
if (preferred_cta == pEdidInfo->total_timings && NVT_PREFERRED_TIMING_IS_CTA(pEdidTiming[i].etc.flag))
{
preferred_cta = i;
if (pEdidInfo->ext861.total_svr > 1)
{
if (kth != 0)
{
// svr == vic
if (NVT_IS_CTA861(pEdidTiming[i].etc.status) && (NVT_GET_CEA_FORMAT(pEdidTiming[i].etc.status) == kth))
{
preferred_cta = i;
}
else if (NVT_GET_TIMING_STATUS_SEQ(pEdidTiming[i].etc.status) == kth)
{
preferred_cta = i;
}
}
}
else
{
preferred_cta = i;
}
}
// find out the preferred timing just in case
@@ -2165,7 +2185,7 @@ NvU32 NvTiming_EDIDValidationMask(NvU8 *pEdid, NvU32 length, NvBool bIsStrongVal
// validate DTD blocks
pDTD = (DETAILEDTIMINGDESCRIPTOR *)&pExt[((EIA861EXTENSION *)pExt)->offset];
while ((pDTD->wDTPixelClock != 0) &&
(((NvU8 *)pDTD - pExt + sizeof(DETAILEDTIMINGDESCRIPTOR)) < ((NvU8)sizeof(EIA861EXTENSION) - 1)))
(((NvU8 *)pDTD - pExt + sizeof(DETAILEDTIMINGDESCRIPTOR)) < ((NvU8)sizeof(EIA861EXTENSION))))
{
if (parseEdidDetailedTimingDescriptor((NvU8 *)pDTD, NULL) != NVT_STATUS_SUCCESS)
{
@@ -2413,7 +2433,7 @@ NvU32 NvTiming_EDIDStrongValidationMask(NvU8 *pEdid, NvU32 length)
// validate DTD blocks
pDTD = (DETAILEDTIMINGDESCRIPTOR *)&pExt[((EIA861EXTENSION *)pExt)->offset];
while ((pDTD->wDTPixelClock != 0) &&
(((NvU8 *)pDTD - pExt + sizeof(DETAILEDTIMINGDESCRIPTOR)) < ((NvU8)sizeof(EIA861EXTENSION) -1)))
(((NvU8 *)pDTD - pExt + sizeof(DETAILEDTIMINGDESCRIPTOR)) < ((NvU8)sizeof(EIA861EXTENSION))))
{
if (parseEdidDetailedTimingDescriptor((NvU8 *)pDTD, NULL) != NVT_STATUS_SUCCESS)
ret |= NVT_EDID_VALIDATION_ERR_MASK(NVT_EDID_VALIDATION_ERR_EXT_DTD);
@@ -2463,8 +2483,8 @@ NvU32 NvTiming_EDIDStrongValidationMask(NvU8 *pEdid, NvU32 length)
// Sanity check every data blocks
while (((pDID2Header->type >= DISPLAYID_2_0_BLOCK_TYPE_PRODUCT_IDENTITY &&
pDID2Header->type <= DISPLAYID_2_0_BLOCK_TYPE_ARVR_LAYER) ||
pDID2Header->type == DISPLAYID_2_0_BLOCK_TYPE_VENDOR_SPEC ||
pDID2Header->type <= DISPLAYID_2_0_BLOCK_TYPE_BRIGHTNESS_LUMINANCE_RANGE) ||
pDID2Header->type == DISPLAYID_2_0_BLOCK_TYPE_VENDOR_SPEC ||
pDID2Header->type == DISPLAYID_2_0_BLOCK_TYPE_CTA_DATA) && pDID2Header->data_bytes != 0 &&
(pData_collection - pExt < (int)sizeof(DIDEXTENSION)))
{
@@ -2497,8 +2517,8 @@ NvU32 NvTiming_EDIDStrongValidationMask(NvU8 *pEdid, NvU32 length)
// if the first tag failed, ignore all the tags afterward then
if (!bAllZero &&
(pDID2Header->type < DISPLAYID_2_0_BLOCK_TYPE_PRODUCT_IDENTITY ||
(pDID2Header->type > DISPLAYID_2_0_BLOCK_TYPE_ARVR_LAYER &&
pDID2Header->type != DISPLAYID_2_0_BLOCK_TYPE_VENDOR_SPEC &&
(pDID2Header->type > DISPLAYID_2_0_BLOCK_TYPE_BRIGHTNESS_LUMINANCE_RANGE &&
pDID2Header->type != DISPLAYID_2_0_BLOCK_TYPE_VENDOR_SPEC &&
pDID2Header->type != DISPLAYID_2_0_BLOCK_TYPE_CTA_DATA)) &&
(pData_collection - pExt < (int)sizeof(DIDEXTENSION)))
{
@@ -2793,6 +2813,32 @@ NvBool assignNextAvailableTiming(NVT_EDID_INFO *pInfo,
return NV_TRUE;
}
/**
* @brief Return the first high priority nth index based on the different SVR
* @param svr Short Video Reference
*/
CODE_SEGMENT(PAGE_DD_CODE)
NvU8 getHighestPrioritySVRIdx(NvU8 svr)
{
// In general sink shall define the first one timing sequence
NvU8 kth = 1;
// Reserved
if (svr == 0 || svr == 128 || (svr >= 176 && svr <= 192) || svr == 255)
return 0;
if (svr >= 129 && svr <= 144) return svr - 128; // Interpret as the Kth 18-byte DTD in both base0 and CTA block (for N = 1 to 16)
else if (svr >= 145 && svr <= 160) return svr - 144; // Interpret as the Nth 20-byte DTD or 6- or 7-byte CVT-based descriptor. (for N = 1 to 16)
else if (svr >= 161 && svr <= 175) return svr - 160; // Interpret as the video format indicated by the first VFD of the first VFDB with Frame Rates of Rate Index N (for N = 1 to 15)
else if (svr == 254) return kth; // Interpret as the timing format indicated by the first code of the first T8VTDB (for N = 1)
else // assign corresponding CTA format's timing from pre-defined CE timing table, EIA861B
{
// ( SVR >= 1 and SVR <= 127) and (SVR >= 193 and SVR <= 253) needs to handle it by client
return svr;
}
return 0;
}
CODE_SEGMENT(PAGE_DD_CODE)
NVT_STATUS NvTiming_GetProductName(const NVT_EDID_INFO *pEdidInfo,
NvU8 *pProductName,

204
src/common/modeset/timing/nvt_edidext_861.c
View File

@@ -968,60 +968,41 @@ void parseCea861HdrStaticMetadataDataBlock(NVT_EDID_CEA861_INFO *pExt861,
}
CODE_SEGMENT(PAGE_DD_CODE)
void parseCea861DvStaticMetadataDataBlock(NVT_EDID_CEA861_INFO *pExt861, void *pRawInfo, NVT_CTA861_ORIGIN flag)
void parseCta861DvStaticMetadataDataBlock(VSVDB_DATA* pVsvdb, NVT_DV_STATIC_METADATA *pDvInfo)
{
NvU32 vsvdbVersion = 0;
NVT_DV_STATIC_METADATA_TYPE0 *pDvType0 = NULL;
NVT_DV_STATIC_METADATA_TYPE1 *pDvType1 = NULL;
NVT_DV_STATIC_METADATA_TYPE1_1 *pvDvType1_1 = NULL;
NVT_DV_STATIC_METADATA_TYPE2 *pDvType2 = NULL;
NVT_EDID_INFO *pInfo = NULL;
NVT_DISPLAYID_2_0_INFO *pDisplayID20 = NULL;
NVT_DV_STATIC_METADATA *pDvInfo = NULL;
if (pExt861 == NULL || pRawInfo == NULL)
if (pVsvdb == NULL || pDvInfo == NULL)
{
return;
}
if (flag == FROM_CTA861_EXTENSION || flag == FROM_DISPLAYID_13_DATA_BLOCK)
{
pInfo = (NVT_EDID_INFO *)pRawInfo;
pDvInfo = &pInfo->dv_static_metadata_info;
}
else if (flag == FROM_DISPLAYID_20_DATA_BLOCK)
{
pDisplayID20 = (NVT_DISPLAYID_2_0_INFO *)pRawInfo;
pDvInfo = &pDisplayID20->cta.dvInfo;
}
else
if(pVsvdb->ieee_id != NVT_CEA861_DV_IEEE_ID)
{
return;
}
if(pExt861->vsvdb.ieee_id != NVT_CEA861_DV_IEEE_ID)
{
return;
}
//init
NVMISC_MEMSET(pDvInfo, 0, sizeof(NVT_DV_STATIC_METADATA));
// copy ieee id
pDvInfo->ieee_id = pExt861->vsvdb.ieee_id;
pDvInfo->ieee_id = pVsvdb->ieee_id;
vsvdbVersion = (pExt861->vsvdb.vendor_data[0] & NVT_CEA861_VSVDB_VERSION_MASK) >> NVT_CEA861_VSVDB_VERSION_MASK_SHIFT;
vsvdbVersion = (pVsvdb->vendor_data[0] & NVT_CEA861_VSVDB_VERSION_MASK) >> NVT_CEA861_VSVDB_VERSION_MASK_SHIFT;
switch (vsvdbVersion)
{
case 0:
if (pExt861->vsvdb.vendor_data_size < sizeof(NVT_DV_STATIC_METADATA_TYPE0))
if (pVsvdb->vendor_data_size < sizeof(NVT_DV_STATIC_METADATA_TYPE0))
{
return;
}
pDvType0 = (NVT_DV_STATIC_METADATA_TYPE0 *)(&pExt861->vsvdb.vendor_data);
pDvType0 = (NVT_DV_STATIC_METADATA_TYPE0 *)(&pVsvdb->vendor_data);
// copy the data
pDvInfo->VSVDB_version = pDvType0->VSVDB_version;
pDvInfo->supports_2160p60hz = pDvType0->supports_2160p60hz;
@@ -1045,9 +1026,9 @@ void parseCea861DvStaticMetadataDataBlock(NVT_EDID_CEA861_INFO *pExt861, void *p
pDvInfo->supports_10b_12b_444 = 0;
break;
case 1:
if (pExt861->vsvdb.vendor_data_size == sizeof(NVT_DV_STATIC_METADATA_TYPE1))
if (pVsvdb->vendor_data_size == sizeof(NVT_DV_STATIC_METADATA_TYPE1))
{
pDvType1 = (NVT_DV_STATIC_METADATA_TYPE1 *)(&pExt861->vsvdb.vendor_data);
pDvType1 = (NVT_DV_STATIC_METADATA_TYPE1 *)(&pVsvdb->vendor_data);
// copy the data
pDvInfo->VSVDB_version = pDvType1->VSVDB_version;
pDvInfo->supports_2160p60hz = pDvType1->supports_2160p60hz;
@@ -1070,9 +1051,9 @@ void parseCea861DvStaticMetadataDataBlock(NVT_EDID_CEA861_INFO *pExt861, void *p
pDvInfo->cc_white_x = 0;
pDvInfo->cc_white_y = 0;
}
else if (pExt861->vsvdb.vendor_data_size == sizeof(NVT_DV_STATIC_METADATA_TYPE1_1))
else if (pVsvdb->vendor_data_size == sizeof(NVT_DV_STATIC_METADATA_TYPE1_1))
{
pvDvType1_1 = (NVT_DV_STATIC_METADATA_TYPE1_1 *)(&pExt861->vsvdb.vendor_data);
pvDvType1_1 = (NVT_DV_STATIC_METADATA_TYPE1_1 *)(&pVsvdb->vendor_data);
// copy the data
pDvInfo->VSVDB_version = pvDvType1_1->VSVDB_version;
pDvInfo->supports_2160p60hz = pvDvType1_1->supports_2160p60hz;
@@ -1102,11 +1083,11 @@ void parseCea861DvStaticMetadataDataBlock(NVT_EDID_CEA861_INFO *pExt861, void *p
break;
case 2:
if (pExt861->vsvdb.vendor_data_size < sizeof(NVT_DV_STATIC_METADATA_TYPE2))
if (pVsvdb->vendor_data_size < sizeof(NVT_DV_STATIC_METADATA_TYPE2))
{
return;
}
pDvType2 = (NVT_DV_STATIC_METADATA_TYPE2 *)(&pExt861->vsvdb.vendor_data);
pDvType2 = (NVT_DV_STATIC_METADATA_TYPE2 *)(&pVsvdb->vendor_data);
// copy the data
pDvInfo->VSVDB_version = pDvType2->VSVDB_version;
pDvInfo->supports_backlight_control = pDvType2->supports_backlight_control;
@@ -1234,6 +1215,67 @@ void parseCta861VsdbBlocks(NVT_EDID_CEA861_INFO *pExt861,
}
// parse vendor specific video data block (VSVDB) information
CODE_SEGMENT(PAGE_DD_CODE)
void parseCta861VsvdbBlocks(NVT_EDID_CEA861_INFO *pExt861,
void *pRawInfo,
NVT_CTA861_ORIGIN flag
)
{
NvU32 i;
NVT_EDID_INFO *pInfo = NULL;
NVT_DISPLAYID_2_0_INFO *pDisplayID20 = NULL;
NVT_DV_STATIC_METADATA *pDvInfo = NULL;
NVT_HDR10PLUS_INFO *pHdr10PlusInfo = NULL;
if (pExt861 == NULL || pRawInfo == NULL)
{
return;
}
if (flag == FROM_CTA861_EXTENSION || flag == FROM_DISPLAYID_13_DATA_BLOCK)
{
pInfo = (NVT_EDID_INFO *)pRawInfo;
pDvInfo = &pInfo->dv_static_metadata_info;
pHdr10PlusInfo = &pInfo->hdr10PlusInfo;
}
else if (flag == FROM_DISPLAYID_20_DATA_BLOCK)
{
pDisplayID20 = (NVT_DISPLAYID_2_0_INFO *)pRawInfo;
pDvInfo = &pDisplayID20->cta.dvInfo;
pHdr10PlusInfo = &pDisplayID20->cta.hdr10PlusInfo;
}
else
{
return;
}
if (pDvInfo == NULL || pHdr10PlusInfo == NULL || (pExt861->total_vsvdb == 0))
{
return;
}
for (i = 0; i < pExt861->total_vsvdb; i++)
{
// Assumes each vsvdb is unique for this CEA block, e.g., no two HDMI_IEEE_ID
switch (pExt861->vsvdb[i].ieee_id)
{
case NVT_CEA861_DV_IEEE_ID:
// parse Dolby Vision related information from the DV vendor specific video data block
parseCta861DvStaticMetadataDataBlock(&pExt861->vsvdb[i], pDvInfo);
pExt861->valid.dv_static_metadata = 1;
break;
case NVT_CEA861_HDR10PLUS_IEEE_ID:
// parse HDR10+ related information from the HDR10+ LLC Vendor Specific Video Data Block
parseCta861Hdr10PlusDataBlock(&pExt861->vsvdb[i], pHdr10PlusInfo);
pExt861->valid.hdr10Plus = 1;
break;
}
}
}
CODE_SEGMENT(PAGE_DD_CODE)
void parseCta861HfEeodb(NVT_EDID_CEA861_INFO *pExt861,
NvU32 *pTotalEdidExtensions)
@@ -1378,6 +1420,7 @@ NVT_STATUS parseCta861DataBlockInfo(NvU8 *p,
NvU32 audio_index = 0;
NvU32 speaker_index = 0;
NvU32 vendor_index = 0;
NvU32 vsvdb_index = 0;
NvU32 yuv420vdb_index = 0;
NvU32 yuv420cmdb_index = 0;
NvU8 didT7_index = 0;
@@ -1638,42 +1681,48 @@ NVT_STATUS parseCta861DataBlockInfo(NvU8 *p,
}
else if(ext_tag == NVT_CEA861_EXT_TAG_VENDOR_SPECIFIC_VIDEO)
{
ieee_id = p[i + 1]; //IEEE ID low byte
ieee_id |= (p[i + 2]) << 8; //IEEE ID middle byte
ieee_id |= (p[i + 3]) << 16; //IEEE ID high byte
if ((ieee_id == NVT_CEA861_DV_IEEE_ID) || (ieee_id == NVT_CEA861_HDR10PLUS_IEEE_ID))
if (vsvdb_index < NVT_CEA861_VSVDB_MAX_BLOCKS)
{
// exclude the extended tag
i++; payload--;
ieee_id = p[i + 1]; //IEEE ID low byte
ieee_id |= (p[i + 2]) << 8; //IEEE ID middle byte
ieee_id |= (p[i + 3]) << 16; //IEEE ID high byte
p861info->vsvdb.ieee_id = ieee_id;
p861info->vsvdb.vendor_data_size = payload - 3;
// move the pointer to the payload
i += 3;
// get the other vendor specific video data
for (j = 0; j < payload - 3; j++, i++)
if ((ieee_id == NVT_CEA861_DV_IEEE_ID) || (ieee_id == NVT_CEA861_HDR10PLUS_IEEE_ID))
{
if (j < NVT_CEA861_VSVDB_PAYLOAD_MAX_LENGTH)
// exclude the extended tag
i++; payload--;
p861info->vsvdb[vsvdb_index].ieee_id = ieee_id;
p861info->vsvdb[vsvdb_index].vendor_data_size = payload - 3;
// move the pointer to the payload
i += 3;
// get the other vendor specific video data
for (j = 0; j < payload - 3; j++, i++)
{
p861info->vsvdb.vendor_data[j] = p[i];
if (j < NVT_CEA861_VSVDB_PAYLOAD_MAX_LENGTH)
{
p861info->vsvdb[vsvdb_index].vendor_data[j] = p[i];
}
}
vsvdb_index++;
p861info->total_vsvdb = (NvU8)vsvdb_index;
}
if (p861info->vsvdb.ieee_id == NVT_CEA861_DV_IEEE_ID)
else
{
p861info->valid.dv_static_metadata = 1;
}
else if (p861info->vsvdb.ieee_id == NVT_CEA861_HDR10PLUS_IEEE_ID)
{
p861info->valid.hdr10Plus = 1;
// skip the unsupported extended block
i += payload;
}
}
else
{
// skip the unsupported extended block
// skip the extended block that we don't have a room for,
// the NVT_CEA861_VSVDB_MAX_BLOCKS should be incremented for new VSVDB types
nvt_assert(vsvdb_index >= NVT_CEA861_VSVDB_MAX_BLOCKS);
i += payload;
}
}
@@ -2509,7 +2558,7 @@ NVT_STATUS NvTiming_ConstructExtendedMetadataPacketInfoframe(
pInfoFrame->Header.firstLast = NVT_EMP_HEADER_FIRST_LAST;
pInfoFrame->Header.sequenceIndex = 0x00;
if (pCtrl->EnableQMS)
if (pCtrl->Sync)
{
nvt_nvu8_set_bits(pInfoFrame->Data.byte1, NVT_HDMI_EMP_BYTE1_SYNC_ENABLE,
NVT_HDMI_EMP_BYTE1_SYNC_MASK,
@@ -2579,6 +2628,14 @@ NVT_STATUS NvTiming_ConstructExtendedMetadataPacketInfoframe(
NVT_HDMI_EMP_BYTE8_MD2_RB_SHIFT);
}
if (pCtrl->version == NVT_EXTENDED_METADATA_PACKET_INFOFRAME_VER_HDMI21A && pCtrl->EnableQMS)
{
nvt_nvu8_set_bits(pInfoFrame->Data.metadataBytes[2],
pCtrl->NextTFR,
NVT_HDMI_EMP_BYTE8_MD2_NEXT_TFR_MASK,
NVT_HDMI_EMP_BYTE8_MD2_NEXT_TFR_SHIFT);
}
// MSB for Base Refresh Rate
nvt_nvu8_set_bits(pInfoFrame->Data.metadataBytes[2],
pCtrl->BaseRefreshRate >> 8,
@@ -3354,39 +3411,20 @@ void parseEdidHdmiForumVSDB(VSDB_DATA *pVsdb, NVT_HDMI_FORUM_INFO *pHdmiInfo)
}
CODE_SEGMENT(PAGE_DD_CODE)
void parseCea861Hdr10PlusDataBlock(NVT_EDID_CEA861_INFO *pExt861, void *pRawInfo, NVT_CTA861_ORIGIN flag)
void parseCta861Hdr10PlusDataBlock(VSVDB_DATA* pVsvdb, NVT_HDR10PLUS_INFO* pHdr10PlusInfo)
{
NVT_EDID_INFO *pInfo = NULL;
NVT_DISPLAYID_2_0_INFO *pDisplayID20 = NULL;
NVT_HDR10PLUS_INFO *pHdr10PlusInfo = NULL;
if (pExt861 == NULL || pRawInfo == NULL)
if (pVsvdb == NULL || pHdr10PlusInfo == NULL)
return;
if(pExt861->vsvdb.ieee_id != NVT_CEA861_HDR10PLUS_IEEE_ID)
if(pVsvdb->ieee_id != NVT_CEA861_HDR10PLUS_IEEE_ID)
return;
if (flag == FROM_CTA861_EXTENSION || flag == FROM_DISPLAYID_13_DATA_BLOCK)
{
pInfo = (NVT_EDID_INFO *)pRawInfo;
pHdr10PlusInfo = &pInfo->hdr10PlusInfo;
}
else if (flag == FROM_DISPLAYID_20_DATA_BLOCK)
{
pDisplayID20 = (NVT_DISPLAYID_2_0_INFO *)pRawInfo;
pHdr10PlusInfo = &pDisplayID20->cta.hdr10PlusInfo;
}
else
{
return;
}
NVMISC_MEMSET(pHdr10PlusInfo, 0, sizeof(NVT_HDR10PLUS_INFO));
if (pExt861->vsvdb.vendor_data_size < sizeof(NVT_HDR10PLUS_INFO))
if (pVsvdb->vendor_data_size < sizeof(NVT_HDR10PLUS_INFO))
return;
NVMISC_MEMCPY(pHdr10PlusInfo, &pExt861->vsvdb.vendor_data, sizeof(NVT_HDR10PLUS_INFO));
NVMISC_MEMCPY(pHdr10PlusInfo, &pVsvdb->vendor_data, sizeof(NVT_HDR10PLUS_INFO));
}
CODE_SEGMENT(PAGE_DD_CODE)

62
src/common/modeset/timing/nvt_edidext_displayid20.c
View File

@@ -34,9 +34,6 @@
PUSH_SEGMENTS
// DisplayId2 as EDID extension entry point functions
static NVT_STATUS parseDisplayId20EDIDExtSection(DISPLAYID_2_0_SECTION *section, NVT_EDID_INFO *pEdidInfo);
/**
*
* @brief Parses a displayId20 EDID Extension block, with timings stored in p and
@@ -183,6 +180,8 @@ parseDisplayId20EDIDExtDataBlocks(
NVT_STATUS status = NVT_STATUS_SUCCESS;
NVT_DISPLAYID_2_0_INFO *pDisplayId20Info = NULL;
NvU8 i;
// size sanity checking
if ((pDataBlock == NULL || RemainSectionLength <= NVT_DISPLAYID_DATABLOCK_HEADER_LEN) ||
(block_header->data_bytes > RemainSectionLength - NVT_DISPLAYID_DATABLOCK_HEADER_LEN))
@@ -195,7 +194,7 @@ parseDisplayId20EDIDExtDataBlocks(
if (pEdidInfo != NULL)
{
pDisplayId20Info = &(pEdidInfo->ext_displayid20);
pDisplayId20Info = &pEdidInfo->ext_displayid20;
}
*pCurrentDBLength = block_header->data_bytes + NVT_DISPLAYID_DATABLOCK_HEADER_LEN;
@@ -234,6 +233,24 @@ parseDisplayId20EDIDExtDataBlocks(
pDisplayId20Info->basic_caps |= NVT_DISPLAY_2_0_CAP_BASIC_AUDIO;
}
for (i = 0; i < pDisplayId20Info->interface_features.combination_count; i++)
{
if (pDisplayId20Info->interface_features.colorspace_eotf_combination[i].eotf == INTERFACE_EOTF_SMPTE_ST2084 &&
pDisplayId20Info->interface_features.colorspace_eotf_combination[i].color_space == INTERFACE_COLOR_SPACE_BT2020)
{
pEdidInfo->hdr_static_metadata_info.static_metadata_type = 1;
pEdidInfo->hdr_static_metadata_info.supported_eotf.smpte_st_2084_eotf = 1;
pEdidInfo->ext861.hdr_static_metadata.byte1 |= NVT_CEA861_EOTF_SMPTE_ST2084;
pEdidInfo->ext861.colorimetry.byte1 |= NVT_CEA861_COLORIMETRY_BT2020RGB;
if (IS_BPC_SUPPORTED_COLORFORMAT(pDisplayId20Info->interface_features.yuv444.bpcs) ||
IS_BPC_SUPPORTED_COLORFORMAT(pDisplayId20Info->interface_features.yuv422.bpcs))
{
pEdidInfo->ext861.colorimetry.byte1 |= NVT_CEA861_COLORIMETRY_BT2020YCC;
}
}
}
break;
// DisplayID_v2.0 E5 defined
@@ -241,7 +258,7 @@ parseDisplayId20EDIDExtDataBlocks(
// * support for 420 pixel encoding is limited to the timings exposed in the restricted set exposed in the CTA data block.
// * field of "Mini Pixel Rate at YCbCr420" shall be set 00h
case DISPLAYID_2_0_BLOCK_TYPE_CTA_DATA:
pDisplayId20Info->valid_data_blocks.cta_data_present = NV_TRUE;
pDisplayId20Info->valid_data_blocks.cta_data_present = NV_TRUE;
// copy all the vendor specific data block from DisplayId20 to pEdidInfo
// NOTE: mixed CTA extension block and DID2.0 extension block are not handled
@@ -268,7 +285,7 @@ parseDisplayId20EDIDExtDataBlocks(
pDisplayId20Info->basic_caps = pEdidInfo->ext861.basic_caps;
}
// this is the DisplayID20 Extension, so we need to copy from what is the CTA raw data in DID20 to Edid's CTA block
// this is the DisplayID20 Extension, so we need to copy the data from the CTA in DID20 to CTA section
if (pEdidInfo->ext861.revision == 0)
NVMISC_MEMCPY(&pEdidInfo->ext861, &pDisplayId20Info->cta.cta861_info, sizeof(NVT_EDID_CEA861_INFO));
else if (pEdidInfo->ext861_2.revision == 0)
@@ -276,9 +293,9 @@ parseDisplayId20EDIDExtDataBlocks(
break;
case DISPLAYID_2_0_BLOCK_TYPE_DISPLAY_PARAM:
pDisplayId20Info->valid_data_blocks.parameters_present = NV_TRUE;
pDisplayId20Info->valid_data_blocks.parameters_present = NV_TRUE;
// EDID only supported 10bits chromaitcity to match the OS D3DKMDT_2DOFFSET 10bits, so we don't need to transfer it here.
// EDID only supported 10bits chromaticity to match the OS D3DKMDT_2DOFFSET 10bits, so we don't need to transfer it here.
pEdidInfo->input.u.digital.bpc = NVT_COLORDEPTH_HIGHEST_BPC(pDisplayId20Info->display_param.native_color_depth);
pEdidInfo->gamma = pDisplayId20Info->display_param.gamma_x100;
@@ -288,36 +305,43 @@ parseDisplayId20EDIDExtDataBlocks(
pDisplayId20Info->basic_caps |= NVT_DISPLAY_2_0_CAP_BASIC_AUDIO;
}
if (pDisplayId20Info->display_param.gamma_x100 != 0)
{
pEdidInfo->hdr_static_metadata_info.supported_eotf.trad_gamma_sdr_eotf = 1;
}
break;
case DISPLAYID_2_0_BLOCK_TYPE_STEREO:
pDisplayId20Info->valid_data_blocks.stereo_interface_present = NV_TRUE;
pDisplayId20Info->valid_data_blocks.stereo_interface_present = NV_TRUE;
break;
case DISPLAYID_2_0_BLOCK_TYPE_TILED_DISPLAY:
pDisplayId20Info->valid_data_blocks.tiled_display_present = NV_TRUE;
pDisplayId20Info->valid_data_blocks.tiled_display_present = NV_TRUE;
break;
case DISPLAYID_2_0_BLOCK_TYPE_CONTAINER_ID:
pDisplayId20Info->valid_data_blocks.container_id_present = NV_TRUE;
pDisplayId20Info->valid_data_blocks.container_id_present = NV_TRUE;
break;
case DISPLAYID_2_0_BLOCK_TYPE_TIMING_7:
pDisplayId20Info->valid_data_blocks.type7Timing_present = NV_TRUE;
pDisplayId20Info->valid_data_blocks.type7Timing_present = NV_TRUE;
break;
case DISPLAYID_2_0_BLOCK_TYPE_TIMING_8:
pDisplayId20Info->valid_data_blocks.type8Timing_present = NV_TRUE;
pDisplayId20Info->valid_data_blocks.type8Timing_present = NV_TRUE;
break;
case DISPLAYID_2_0_BLOCK_TYPE_TIMING_9:
pDisplayId20Info->valid_data_blocks.type9Timing_present = NV_TRUE;
pDisplayId20Info->valid_data_blocks.type9Timing_present = NV_TRUE;
break;
case DISPLAYID_2_0_BLOCK_TYPE_TIMING_10:
pDisplayId20Info->valid_data_blocks.type10Timing_present = NV_TRUE;
pDisplayId20Info->valid_data_blocks.type10Timing_present = NV_TRUE;
break;
case DISPLAYID_2_0_BLOCK_TYPE_RANGE_LIMITS:
pDisplayId20Info->valid_data_blocks.dynamic_range_limit_present = NV_TRUE;
pDisplayId20Info->valid_data_blocks.dynamic_range_limit_present = NV_TRUE;
break;
case DISPLAYID_2_0_BLOCK_TYPE_ADAPTIVE_SYNC:
pDisplayId20Info->valid_data_blocks.adaptive_sync_present = NV_TRUE;
break;
pDisplayId20Info->valid_data_blocks.adaptive_sync_present = NV_TRUE;
break;
case DISPLAYID_2_0_BLOCK_TYPE_BRIGHTNESS_LUMINANCE_RANGE:
pDisplayId20Info->valid_data_blocks.brightness_luminance_range_present = NV_TRUE;
break;
case DISPLAYID_2_0_BLOCK_TYPE_VENDOR_SPEC:
pDisplayId20Info->valid_data_blocks.vendor_specific_present = NV_TRUE;
pDisplayId20Info->valid_data_blocks.vendor_specific_present = NV_TRUE;
break;
default:
break;

30
src/common/modeset/timing/nvt_ovt.c Normal file
View File

@@ -0,0 +1,30 @@
//*****************************************************************************
//
// SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
// SPDX-License-Identifier: MIT
//
// Permission is hereby granted, free of charge, to any person obtaining a
// copy of this software and associated documentation files (the "Software"),
// to deal in the Software without restriction, including without limitation
// the rights to use, copy, modify, merge, publish, distribute, sublicense,
// and/or sell copies of the Software, and to permit persons to whom the
// Software is furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
// THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
// FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
// DEALINGS IN THE SOFTWARE.
//
// File: nvt_ovt.c
//
// Purpose: calculate Optimized Video Timing (OVT) timing
//
//*****************************************************************************

77
src/common/modeset/timing/nvtiming.h
View File

@@ -806,7 +806,7 @@ typedef enum NVT_TV_FORMAT
#define NVT_CEA861_SPEAKER_ALLOC_RLC_RRC 0x40 // speaker allocation : Rear Left Center + Rear Right Center
//***********************
// vendor specific data
// vendor specific data block (VSDB)
//***********************
#define NVT_CEA861_VSDB_HEADER_SIZE 4
#define NVT_CEA861_VSDB_PAYLOAD_MAX_LENGTH 28 // max allowed vendor specific data block payload (in byte)
@@ -829,8 +829,9 @@ typedef struct VSDB_DATA
} VSDB_DATA;
//*******************************
// vendor specific video data
// vendor specific video data block (VSVDB)
//*******************************
#define NVT_CEA861_VSVDB_MAX_BLOCKS 2 // Dolby Vision, HDR10+ VSVDBs
#define NVT_CEA861_DV_IEEE_ID 0x00D046
#define NVT_CEA861_HDR10PLUS_IEEE_ID 0x90848B
#define NVT_CEA861_VSVDB_PAYLOAD_MAX_LENGTH 25 // max allowed vendor specific video data block payload (in byte)
@@ -1287,7 +1288,8 @@ typedef struct tagEDID_CEA861_INFO
VSDB_DATA vsdb[NVT_CEA861_VSDB_MAX_BLOCKS];
// vendor specific video data
VSVDB_DATA vsvdb;
NvU8 total_vsvdb;
VSVDB_DATA vsvdb[NVT_CEA861_VSVDB_MAX_BLOCKS];
// indicates which of the extended data blocks below contain valid data excluding extended blocks with total count
NVT_VALID_EXTENDED_BLOCKS valid;
@@ -2514,7 +2516,7 @@ typedef struct _tagNVT_DISPLAYID_DISPLAY_PARAMETERS
NVT_COLOR_POINT white;
NVT_NATIVE_LUMINANCE_INFO native_luminance_info;
NvU16 native_max_luminance_full_coverage;
NvU16 native_max_luminance_1_percent_rect_coverage;
NvU16 native_max_luminance_10_percent_rect_coverage;
NvU16 native_min_luminance;
NVT_COLORDEPTH native_color_depth;
NvU16 gamma_x100;
@@ -2592,6 +2594,14 @@ typedef struct _tagNVT_DISPLAYID_CTA
NVT_HDR10PLUS_INFO hdr10PlusInfo;
} NVT_DISPLAYID_CTA;
typedef struct _tagNVT_DISPLAYID_BRIGHTNESS_LUMINANCE_RANGE
{
NvU32 revision;
NvU16 min_sdr_luminance;
NvU16 max_sdr_luminance;
NvU16 max_boost_sdr_luminance;
} NVT_DISPLAYID_BRIGHTNESS_LUMINANCE_RANGE;
typedef struct _tagNVT_VALID_DATA_BLOCKS
{
NvBool product_id_present;
@@ -2608,6 +2618,7 @@ typedef struct _tagNVT_VALID_DATA_BLOCKS
NvBool adaptive_sync_present;
NvBool arvr_hmd_present;
NvBool arvr_layer_present;
NvBool brightness_luminance_range_present;
NvBool vendor_specific_present;
NvBool cta_data_present;
} NVT_VALID_DATA_BLOCKS;
@@ -2615,60 +2626,63 @@ typedef struct _tagNVT_VALID_DATA_BLOCKS
#define NVT_DISPLAYID_MAX_TOTAL_TIMING NVT_MAX_TOTAL_TIMING
typedef struct _tagNVT_DISPLAYID_2_0_INFO
{
NvU8 revision;
NvU8 version;
NvU8 revision;
NvU8 version;
// support audio/yuv444/yuv422 color for CTA861 compatible
NvU8 basic_caps;
NvU8 basic_caps;
// the all extensions that may appear following the base section
NvU32 extension_count;
NvU32 extension_count;
// this displayID20 is EDID extension or not
NvBool as_edid_extension;
NvBool as_edid_extension;
// data blocks present or not
NVT_VALID_DATA_BLOCKS valid_data_blocks;
NVT_VALID_DATA_BLOCKS valid_data_blocks;
NVT_DISPLAYID_PRODUCT_PRIMARY_USE_CASE primary_use_case;
NVT_DISPLAYID_PRODUCT_PRIMARY_USE_CASE primary_use_case;
// Product Identification Data Block (Mandatory)
NVT_DISPLAYID_PRODUCT_IDENTITY product_identity;
NVT_DISPLAYID_PRODUCT_IDENTITY product_identity;
// Display Parameter Data Block (Mandatory for Display Use)
NVT_DISPLAYID_DISPLAY_PARAMETERS display_param;
NVT_DISPLAYID_DISPLAY_PARAMETERS display_param;
// Detailed Timing Data Block (Mandatory for Display Use)
NvU32 total_timings;
NVT_TIMING timing[NVT_DISPLAYID_MAX_TOTAL_TIMING];
NvU32 total_timings;
NVT_TIMING timing[NVT_DISPLAYID_MAX_TOTAL_TIMING];
// Enumerated Timing Code Data Block (Not Mandatory)
// Formula-based Timing Data Block (Not Mandatory)
// Dynamic Video Timing Range Limits Data Block (Not Mandatory)
NVT_DISPLAYID_RANGE_LIMITS range_limits;
NVT_DISPLAYID_RANGE_LIMITS range_limits;
// Display Interface Features Data Block (Mandatory)
NVT_DISPLAYID_INTERFACE_FEATURES interface_features;
NVT_DISPLAYID_INTERFACE_FEATURES interface_features;
// Stereo Display Interface Data Block (Not Mandatory)
// Tiled Display Topology Data Block (Not Mandatory)
NVT_DISPLAYID_TILED_DISPLAY_TOPOLOGY tile_topo;
NVT_DISPLAYID_TILED_DISPLAY_TOPOLOGY tile_topo;
// ContainerID Data Block (Mandatory for Multi-function Device)
NVT_DISPLAYID_CONTAINERID container_id;
NVT_DISPLAYID_CONTAINERID container_id;
// Adaptive-Sync Data Block (Mandatory for display device supports Adaptive-Sync)
NvU32 total_adaptive_sync_descriptor;
NVT_DISPLAYID_ADAPTIVE_SYNC adaptive_sync_descriptor[NVT_ADAPTIVE_SYNC_DESCRIPTOR_MAX_COUNT];
NvU32 total_adaptive_sync_descriptor;
NVT_DISPLAYID_ADAPTIVE_SYNC adaptive_sync_descriptor[NVT_ADAPTIVE_SYNC_DESCRIPTOR_MAX_COUNT];
// Brightness Luminance Range Data Block (Mandatory for display device supports Nits based brightness control)
NVT_DISPLAYID_BRIGHTNESS_LUMINANCE_RANGE luminance_ranges;
// Vendor-specific Data Block (Not Mandatory)
NVT_DISPLAYID_VENDOR_SPECIFIC vendor_specific;
NVT_DISPLAYID_VENDOR_SPECIFIC vendor_specific;
// CTA DisplayID Data Block (Not Mandatory)
NVT_DISPLAYID_CTA cta;
NVT_DISPLAYID_CTA cta;
} NVT_DISPLAYID_2_0_INFO;
#define NVT_EDID_PRIMARY_COLOR_FP2INT_FACTOR 1024 // Per EDID 1.4, 10bit color primary is encoded in floating point as (bit9/2 + bit8/4 + bi7/8 + ... + bit0)
@@ -2934,6 +2948,8 @@ typedef struct tagNVT_EXTENDED_METADATA_PACKET_INFOFRAME_CTRL
NvU32 ReducedBlanking;
NvU32 BaseRefreshRate;
NvU32 EnableQMS;
NvU32 NextTFR;
NvU32 Sync;
} NVT_EXTENDED_METADATA_PACKET_INFOFRAME_CTRL;
typedef struct tagNVT_ADAPTIVE_SYNC_SDP_CTRL
@@ -3777,6 +3793,9 @@ typedef struct tagNVT_EXTENDED_METADATA_PACKET_INFOFRAME
#define NVT_HDMI_EMP_BYTE8_MD2_RB_DISABLE 0
#define NVT_HDMI_EMP_BYTE8_MD2_RB_ENABLE 1
#define NVT_HDMI_EMP_BYTE8_MD2_NEXT_TFR_MASK 0x1f
#define NVT_HDMI_EMP_BYTE8_MD2_NEXT_TFR_SHIFT 3
#define NVT_HDMI_EMP_BYTE8_MD2_BASE_RR_MSB_MASK 0x03
#define NVT_HDMI_EMP_BYTE8_MD2_BASE_RR_MSB_SHIFT 0
@@ -5492,6 +5511,18 @@ typedef enum
NVT_STATUS_ERR = 0x80000000, // generic get timing error
NVT_STATUS_INVALID_PARAMETER, // passed an invalid parameter
NVT_STATUS_NO_MEMORY, // memory allocation failed
NVT_STATUS_COLOR_FORMAT_NOT_SUPPORTED,
NVT_STATUS_INVALID_HBLANK,
NVT_STATUS_INVALID_BPC,
NVT_STATUS_INVALID_BPP,
NVT_STATUS_MAX_LINE_BUFFER_ERROR,
NVT_STATUS_OVERALL_THROUGHPUT_ERROR,
NVT_STATUS_DSC_SLICE_ERROR,
NVT_STATUS_PPS_SLICE_COUNT_ERROR,
NVT_STATUS_PPS_SLICE_HEIGHT_ERROR,
NVT_STATUS_PPS_SLICE_WIDTH_ERROR,
NVT_STATUS_INVALID_PEAK_THROUGHPUT,
NVT_STATUS_MIN_SLICE_COUNT_ERROR,
} NVT_STATUS;
//*************************************

15
src/common/modeset/timing/nvtiming_pvt.h
View File

@@ -46,6 +46,10 @@
#include <stddef.h> // NULL
#ifdef __cplusplus
extern "C" {
#endif
// EDID related private functions
NvU32 getEdidVersion(NvU8 *pData, NvU32 *pVer);
NvBool assignNextAvailableTiming(NVT_EDID_INFO *pInfo, const NVT_TIMING *pTiming);
@@ -70,6 +74,7 @@ void parse861bShortTiming(NVT_EDID_CEA861_INFO *pExt861, void *pRawInfo, N
void parse861bShortYuv420Timing(NVT_EDID_CEA861_INFO *pExt861, void *pRawInfo, NVT_CTA861_ORIGIN flag);
void parseCta861NativeOrPreferredTiming(NVT_EDID_CEA861_INFO *pExt861, void *pRawInfo, NVT_CTA861_ORIGIN flag);
void parseCta861VsdbBlocks(NVT_EDID_CEA861_INFO *pExt861, void *pRawInfo, NVT_CTA861_ORIGIN flag);
void parseCta861VsvdbBlocks(NVT_EDID_CEA861_INFO *pExt861, void *pRawInfo, NVT_CTA861_ORIGIN flag);
void parseCta861HfScdb(NVT_EDID_CEA861_INFO *pExt861, void *pRawInfo, NVT_CTA861_ORIGIN flag);
void parseCta861HfEeodb(NVT_EDID_CEA861_INFO *pExt861, NvU32 *pTotalEdidExtensions);
void parseEdidMsftVsdbBlock(VSDB_DATA *pVsdb, MSFT_VSDB_PARSED_INFO *vsdbInfo);
@@ -79,8 +84,8 @@ void getEdidHDM1_4bVsdbTiming(NVT_EDID_INFO *pInfo);
void parseEdidHDMILLCTiming(NVT_EDID_INFO *pInfo, VSDB_DATA *pVsdb, NvU32 *pSupported, HDMI3DSUPPORTMAP * pM);
void parseEdidNvidiaVSDBBlock(VSDB_DATA *pVsdb, NVDA_VSDB_PARSED_INFO *vsdbInfo);
void parseCea861HdrStaticMetadataDataBlock(NVT_EDID_CEA861_INFO *pExt861, void *pRawInfo, NVT_CTA861_ORIGIN flag);
void parseCea861DvStaticMetadataDataBlock(NVT_EDID_CEA861_INFO *pExt861, void *pRawInfo, NVT_CTA861_ORIGIN flag);
void parseCea861Hdr10PlusDataBlock(NVT_EDID_CEA861_INFO *pExt861, void *pRawInfo, NVT_CTA861_ORIGIN flag);
void parseCta861DvStaticMetadataDataBlock(VSVDB_DATA* pVsvdb, NVT_DV_STATIC_METADATA* pDvInfo);
void parseCta861Hdr10PlusDataBlock(VSVDB_DATA* pVsvdb, NVT_HDR10PLUS_INFO* pHdr10PlusInfo);
void parseCta861DIDType7VideoTimingDataBlock(NVT_EDID_CEA861_INFO *pExt861, void *pRawInfo);
void parseCta861DIDType8VideoTimingDataBlock(NVT_EDID_CEA861_INFO *pExt861, void *pRawInfo);
void parseCta861DIDType10VideoTimingDataBlock(NVT_EDID_CEA861_INFO *pExt861, void *pRawInfo);
@@ -89,6 +94,7 @@ NvBool isMatchedStandardTiming(NVT_EDID_INFO *pInfo, NVT_TIMING *pT);
NvBool isMatchedEstablishedTiming(NVT_EDID_INFO *pInfo, NVT_TIMING *pT);
NvU32 isHdmi3DStereoType(NvU8 StereoStructureType);
NvU32 getCEA861TimingAspectRatio(NvU32 vic);
NvU8 getHighestPrioritySVRIdx(NvU8 svr);
void SetActiveSpaceForHDMI3DStereo(const NVT_TIMING *pTiming, NVT_EXT_TIMING *pExtTiming);
void AddModeToSupportMap(HDMI3DSUPPORTMAP * pMap, NvU8 vic, NvU8 structure, NvU8 Detail);
void getMonitorDescriptorString(NvU8 *pEdid, NvU8 tag, char *str, int onceOnly);
@@ -102,12 +108,16 @@ NVT_STATUS getDisplayId20EDIDExtInfo(NvU8* pDisplayid, NvU32 edidSize, NVT_EDID_
NVT_STATUS parseDisplayId20EDIDExtDataBlocks(NvU8* pDataBlock, NvU8 remainSectionLength, NvU8* pCurrentDBLength, NVT_EDID_INFO* pEdidInfo);
NVT_STATUS parseDisplayId20Timing7Descriptor(const void *pDescriptor, NVT_TIMING *pTiming, NvU8 count);
NVT_STATUS parseDisplayId20Timing8Descriptor(const void *pDescriptor, NVT_TIMING *pTiming, NvU8 codeType, NvU8 codeSize, NvU8 index, NvU8 count);
NVT_STATUS parseDisplayId20Timing9Descriptor(const void *pDescriptor, NVT_TIMING *pTiming, NvU8 count);
NVT_STATUS parseDisplayId20Timing10Descriptor(const void *pDescriptor, NVT_TIMING *pTiming, NvU8 payloadBytes, NvU8 count);
void updateColorFormatForDisplayIdExtnTimings(NVT_EDID_INFO* pInfo, NvU32 timingIdx);
void updateColorFormatForDisplayId20ExtnTimings(NVT_EDID_INFO* pInfo, NvU32 timingIdx);
NvBool assignNextAvailableDisplayId20Timing(NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo, const NVT_TIMING *pTiming);
void updateColorFormatForDisplayId20Timings(NVT_DISPLAYID_2_0_INFO* pDisplayId2Info, NvU32 timingIdx);
// End DisplayID
#ifdef __cplusplus
}
#endif
NvU32 axb_div_c_old(NvU32 a, NvU32 b, NvU32 c);
@@ -151,3 +161,4 @@ NvU32 axb_div_c_old(NvU32 a, NvU32 b, NvU32 c);
#define NVT_TIMING_SENTINEL {0,0,0,0,0,0,0,0,0,0,0,0,0,0,NVT_TIMINGEXT_SENTINEL}
#endif //__NVTIMING_PVT_H_