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https://github.com/NVIDIA/open-gpu-kernel-modules.git
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545.23.06
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@@ -65,7 +65,7 @@ typedef struct _tagDISPLAYID_2_0_SECTION_HEADER
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NvU8 product_type:4; // Display Product Primary Use Case
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NvU8 reserved:4; // RESERVED
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NvU8 extension_count; // Total extension count.
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} DISPLAYID_2_0_SECTION_HEADER;
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} DISPLAYID_2_0_SECTION_HEADER;
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typedef struct _tagDISPLAYID_2_0_SECTION
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{
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@@ -79,7 +79,7 @@ typedef struct _tagDISPLAYID_2_0_SECTION
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#define DISPLAYID_2_0_PROD_EXTENSION 0 // Extension (same primary use case as base section)
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#define DISPLAYID_2_0_PROD_TEST 1 // Test Structure/Test Equipment
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#define DISPLAYID_2_0_PROD_GENERIC_DISPLAY 2 // None of the listed primary use cases; generic display
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#define DISPLAYID_2_0_PROD_GENERIC_DISPLAY 2 // None of the listed primary use cases; generic display
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#define DISPLAYID_2_0_PROD_TELEVISION 3 // Television (TV) display
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#define DISPLAYID_2_0_PROD_DESKTOP_PRODUCTIVITY_DISPLAY 4 // Desktop productivity display
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#define DISPLAYID_2_0_PROD_DESKTOP_GAMING_DISPLAY 5 // Desktop gaming display
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@@ -95,25 +95,26 @@ typedef struct _tagDISPLAYID_2_0_DATA_BLOCK_HEADER
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NvU8 data_bytes; // number of payload bytes in Block [ 0, 248]
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} DISPLAYID_2_0_DATA_BLOCK_HEADER;
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#define DISPLAYID_2_0_BLOCK_TYPE_PRODUCT_IDENTITY 0x20
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#define DISPLAYID_2_0_BLOCK_TYPE_DISPLAY_PARAM 0x21
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#define DISPLAYID_2_0_BLOCK_TYPE_TIMING_7 0x22
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#define DISPLAYID_2_0_BLOCK_TYPE_TIMING_8 0x23
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#define DISPLAYID_2_0_BLOCK_TYPE_TIMING_9 0x24
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#define DISPLAYID_2_0_BLOCK_TYPE_RANGE_LIMITS 0x25
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#define DISPLAYID_2_0_BLOCK_TYPE_INTERFACE_FEATURES 0x26
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#define DISPLAYID_2_0_BLOCK_TYPE_STEREO 0x27
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#define DISPLAYID_2_0_BLOCK_TYPE_TILED_DISPLAY 0x28
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#define DISPLAYID_2_0_BLOCK_TYPE_CONTAINER_ID 0x29
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#define DISPLAYID_2_0_BLOCK_TYPE_TIMING_10 0x2A
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#define DISPLAYID_2_0_BLOCK_TYPE_ADAPTIVE_SYNC 0x2B
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#define DISPLAYID_2_0_BLOCK_TYPE_ARVR_HMD 0x2C
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#define DISPLAYID_2_0_BLOCK_TYPE_ARVR_LAYER 0x2D
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// 0x7D - 0x2E RESERVED for Additional VESA-defined Data Blocks
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#define DISPLAYID_2_0_BLOCK_TYPE_PRODUCT_IDENTITY 0x20
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#define DISPLAYID_2_0_BLOCK_TYPE_DISPLAY_PARAM 0x21
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#define DISPLAYID_2_0_BLOCK_TYPE_TIMING_7 0x22
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#define DISPLAYID_2_0_BLOCK_TYPE_TIMING_8 0x23
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#define DISPLAYID_2_0_BLOCK_TYPE_TIMING_9 0x24
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#define DISPLAYID_2_0_BLOCK_TYPE_RANGE_LIMITS 0x25
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#define DISPLAYID_2_0_BLOCK_TYPE_INTERFACE_FEATURES 0x26
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#define DISPLAYID_2_0_BLOCK_TYPE_STEREO 0x27
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#define DISPLAYID_2_0_BLOCK_TYPE_TILED_DISPLAY 0x28
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#define DISPLAYID_2_0_BLOCK_TYPE_CONTAINER_ID 0x29
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#define DISPLAYID_2_0_BLOCK_TYPE_TIMING_10 0x2A
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#define DISPLAYID_2_0_BLOCK_TYPE_ADAPTIVE_SYNC 0x2B
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#define DISPLAYID_2_0_BLOCK_TYPE_ARVR_HMD 0x2C
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#define DISPLAYID_2_0_BLOCK_TYPE_ARVR_LAYER 0x2D
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#define DISPLAYID_2_0_BLOCK_TYPE_BRIGHTNESS_LUMINANCE_RANGE 0x2E
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// 0x7D - 0x2F RESERVED for Additional VESA-defined Data Blocks
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#define DISPLAYID_2_0_BLOCK_TYPE_VENDOR_SPEC 0x7E
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// 0x80 - 0x7F RESERVED
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#define DISPLAYID_2_0_BLOCK_TYPE_CTA_DATA 0x81
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// 0xFF - 0x82 RESERVED for additional data blocks related to external standards organization(s).
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// 0xFF - 0x82 RESERVED for additional data blocks related to external standards organization(s).
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#define DISPLAYID_2_0_PRODUCT_NAME_STRING_MAX_LEN ((0xFB - 0xF) + 1)
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@@ -184,7 +185,7 @@ typedef struct _tagDISPLAYID_2_0_DISPLAY_PARAM_BLOCK
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DISPLAYID_2_0_COLOR_CHROMATICITY primary_color_3_chromaticity;
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DISPLAYID_2_0_COLOR_CHROMATICITY white_point_chromaticity;
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NvU8 max_luminance_full_coverage[2];
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NvU8 max_luminance_1_percent_rectangular_coverage[2];
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NvU8 max_luminance_10_percent_rectangular_coverage[2];
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NvU8 min_luminance[2];
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struct {
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@@ -525,7 +526,7 @@ typedef struct _tagDISPLAYID_2_0_STEREO_INTERFACE_BLOCK_HEADER
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NvU8 type;
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NvU8 revision:3;
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NvU8 reserved:3;
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NvU8 stereo_timing_support:2;
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NvU8 stereo_timing_support:2;
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} DISPLAYID_2_0_STEREO_INTERFACE_BLOCK_HEADER;
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typedef struct _tagDISPLAYID_2_0_STEREO_TIMING_DESCRIPTOR
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@@ -692,7 +693,7 @@ typedef struct _tagDISPLAYID_2_0_ADAPTIVE_SYNC_DESCRIPTOR
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NvU8 successive_frame_dec_tolerance : 1;
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NvU8 reserved : 2;
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} operation_range_info;
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// 6.2 format (six integer bits and two fractional bits)
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// six integer bits == 0 - 63ms
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// two fractional bits == 0.00(00), 0.25(01b),0.50(10), 0.75(11b)
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@@ -704,9 +705,9 @@ typedef struct _tagDISPLAYID_2_0_ADAPTIVE_SYNC_DESCRIPTOR
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NvU8 max_rr_9_8 : 2;
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NvU8 reserved : 6;
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} max_refresh_rate;
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// same as max_single_frame_inc expression
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NvU8 max_single_frame_dec;
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NvU8 max_single_frame_dec;
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} DISPLAYID_2_0_ADAPTIVE_SYNC_DESCRIPTOR;
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typedef struct _tagDISPLAYID_2_0_ADAPTIVE_SYNC_BLOCK
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@@ -715,6 +716,16 @@ typedef struct _tagDISPLAYID_2_0_ADAPTIVE_SYNC_BLOCK
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DISPLAYID_2_0_ADAPTIVE_SYNC_DESCRIPTOR descriptors[DISPLAYID_2_0_ADAPTIVE_SYNC_DETAILED_TIMING_COUNT];
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} DISPLAYID_2_0_ADAPTIVE_SYNC_BLOCK;
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// Payload value as defined in DID2.1 spec
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#define DISPLAYID_2_0_BRIGHTNESS_LUMINANCE_RANGE_BLOCK_PAYLOAD_LENGTH 6
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typedef struct _tagDISPLAYID_2_0_BRIGHTNESS_LUMINANCE_RANGE_BLOCK
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{
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DISPLAYID_2_0_DATA_BLOCK_HEADER header;
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NvU16 min_sdr_luminance; // 0x03 ~ 0x04
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NvU16 max_sdr_luminance; // 0x05 ~ 0x06
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NvU16 max_boost_sdr_luminance; // 0x07 ~ 0x08
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} DISPLAYID_2_0_BRIGHTNESS_LUMINANCE_RANGE_BLOCK;
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typedef struct _tagDISPLAYID_2_0_VENDOR_SPECIFIC_BLOCK
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{
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DISPLAYID_2_0_DATA_BLOCK_HEADER header;
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@@ -732,8 +743,43 @@ typedef struct _tagDISPLAYID_2_0_CTA_BLOCK
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#pragma pack()
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#endif
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#ifdef __cplusplus
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extern "C" {
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#endif
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// Entry point functions both used in DID20 and DID20ext
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NVT_STATUS parseDisplayId20DataBlock(const DISPLAYID_2_0_DATA_BLOCK_HEADER *pDataBlock, NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo);
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NvU8 computeDisplayId20SectionCheckSum(const NvU8 *pSectionBytes, NvU32 length);
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#endif // __DISPLAYID20_H_
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// DisplayID20 as EDID extension entry point function
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NVT_STATUS parseDisplayId20EDIDExtSection(DISPLAYID_2_0_SECTION *section, NVT_EDID_INFO *pEdidInfo);
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// DisplayID20 Entry point functions
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NVT_STATUS parseDisplayId20BaseSection(const DISPLAYID_2_0_SECTION *pSection, NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo);
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NVT_STATUS parseDisplayId20SectionDataBlocks(const DISPLAYID_2_0_SECTION *pSection, NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo);
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NVT_STATUS parseDisplayId20ExtensionSection(const DISPLAYID_2_0_SECTION *pSection, NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo);
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// DisplayID20 Data Block Tag Allocation
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NVT_STATUS parseDisplayId20ProductIdentity(const DISPLAYID_2_0_DATA_BLOCK_HEADER *pDataBlock, NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo); // 0x20 Product Identificaton
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NVT_STATUS parseDisplayId20DisplayParam(const DISPLAYID_2_0_DATA_BLOCK_HEADER *pDataBlock, NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo); // 0x21 Display Parameters
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NVT_STATUS parseDisplayId20Timing7(const DISPLAYID_2_0_DATA_BLOCK_HEADER *pDataBlock, NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo); // 0x22 Type VII Timing - Detailed Timing
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NVT_STATUS parseDisplayId20Timing8(const DISPLAYID_2_0_DATA_BLOCK_HEADER *pDataBlock, NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo); // 0x23 Type VIII Timing - Enumerated Timing
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NVT_STATUS parseDisplayId20Timing9(const DISPLAYID_2_0_DATA_BLOCK_HEADER *pDataBlock, NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo); // 0x24 Type IX Timing - Formula-based
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NVT_STATUS parseDisplayId20RangeLimit(const DISPLAYID_2_0_DATA_BLOCK_HEADER *pDataBlock, NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo); // 0x25 Dynamic Video Timing Range Limits
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NVT_STATUS parseDisplayId20DisplayInterfaceFeatures(const DISPLAYID_2_0_DATA_BLOCK_HEADER *pDataBlock, NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo); // 0x26 Display Interface Features
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NVT_STATUS parseDisplayId20Stereo(const DISPLAYID_2_0_DATA_BLOCK_HEADER *pDataBlock, NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo); // 0x27 Stereo Display Interface
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NVT_STATUS parseDisplayId20TiledDisplay(const DISPLAYID_2_0_DATA_BLOCK_HEADER *pDataBlock, NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo); // 0x28 Tiled Display Topology
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NVT_STATUS parseDisplayId20ContainerId(const DISPLAYID_2_0_DATA_BLOCK_HEADER *pDataBlock, NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo); // 0x29 ContainerID
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NVT_STATUS parseDisplayId20Timing10(const DISPLAYID_2_0_DATA_BLOCK_HEADER *pDataBlock, NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo); // 0x2A Type X Timing - Formula-based Timing
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NVT_STATUS parseDisplayId20AdaptiveSync(const DISPLAYID_2_0_DATA_BLOCK_HEADER *pDataBlock, NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo); // 0x2B Adaptive-Sync
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NVT_STATUS parseDisplayId20ARVRHMD(const DISPLAYID_2_0_DATA_BLOCK_HEADER *pDataBlock, NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo); // 0x2C ARVR HMD
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NVT_STATUS parseDisplayId20ARVRLayer(const DISPLAYID_2_0_DATA_BLOCK_HEADER *pDataBlock, NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo); // 0x2D ARVR Layer
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NVT_STATUS parseDisplayId20BrightnessLuminanceRange(const DISPLAYID_2_0_DATA_BLOCK_HEADER *pDataBlock, NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo); // 0x2E Brightness Luminance Range
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NVT_STATUS parseDisplayId20VendorSpecific(const DISPLAYID_2_0_DATA_BLOCK_HEADER *pDataBlock, NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo); // 0x7E Vendor-specific
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NVT_STATUS parseDisplayId20CtaData(const DISPLAYID_2_0_DATA_BLOCK_HEADER *pDataBlock, NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo); // 0x81 CTA DisplayID
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#ifdef __cplusplus
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}
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#endif
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#endif // __DISPLAYID20_H_1
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