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This commit is contained in:
Andy Ritger
2023-10-17 09:25:29 -07:00
parent f59818b751
commit b5bf85a8e3
917 changed files with 132480 additions and 110015 deletions
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38
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080bus.h
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@@ -1467,44 +1467,6 @@ typedef struct NV2080_CTRL_BUS_SYSMEM_ACCESS_PARAMS {
NvBool bDisable;
} NV2080_CTRL_BUS_SYSMEM_ACCESS_PARAMS;
/*
* NV2080_CTRL_CMD_BUS_GET_C2C_ERR_INFO
*
* This command returns the C2C error info for a C2C links.
*
* errCnts[OUT]
* Array of structure that contains the error counts for
* number of times one of C2C fatal error interrupt has happened.
* The array size should be NV2080_CTRL_BUS_GET_C2C_ERR_INFO_MAX_NUM_C2C_INSTANCES
* * NV2080_CTRL_BUS_GET_C2C_ERR_INFO_MAX_C2C_LINKS_PER_INSTANCE.
*
* nrCrcErrIntr[OUT]
* Number of times CRC error interrupt triggered.
* nrReplayErrIntr[OUT]
* Number of times REPLAY error interrupt triggered.
* nrReplayB2bErrIntr[OUT]
* Number of times REPLAY_B2B error interrupt triggered.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_STATE
* NV_ERR_NOT_SUPPORTED
*/
#define NV2080_CTRL_CMD_BUS_GET_C2C_ERR_INFO (0x2080182d) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_BUS_GET_C2C_ERR_INFO_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_BUS_GET_C2C_ERR_INFO_MAX_NUM_C2C_INSTANCES 2
#define NV2080_CTRL_BUS_GET_C2C_ERR_INFO_MAX_C2C_LINKS_PER_INSTANCE 5
#define NV2080_CTRL_BUS_GET_C2C_ERR_INFO_PARAMS_MESSAGE_ID (0x2DU)
typedef struct NV2080_CTRL_BUS_GET_C2C_ERR_INFO_PARAMS {
struct {
NvU32 nrCrcErrIntr;
NvU32 nrReplayErrIntr;
NvU32 nrReplayB2bErrIntr;
} errCnts[NV2080_CTRL_BUS_GET_C2C_ERR_INFO_MAX_NUM_C2C_INSTANCES * NV2080_CTRL_BUS_GET_C2C_ERR_INFO_MAX_C2C_LINKS_PER_INSTANCE];
} NV2080_CTRL_BUS_GET_C2C_ERR_INFO_PARAMS;
/*

8
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080ce.h
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@@ -186,7 +186,7 @@ typedef struct NV2080_CTRL_CE_GET_CE_PCE_MASK_PARAMS {
#define NV2080_CTRL_CMD_CE_SET_PCE_LCE_CONFIG (0x20802a04) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_CE_INTERFACE_ID << 8) | NV2080_CTRL_CE_SET_PCE_LCE_CONFIG_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_MAX_PCES 32
#define NV2080_CTRL_MAX_GRCES 2
#define NV2080_CTRL_MAX_GRCES 4
#define NV2080_CTRL_CE_SET_PCE_LCE_CONFIG_PARAMS_MESSAGE_ID (0x4U)
@@ -323,11 +323,13 @@ typedef struct NV2080_CTRL_CE_GET_HUB_PCE_MASK_PARAMS {
#define NV2080_CTRL_CMD_CE_GET_ALL_CAPS (0x20802a0a) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_CE_INTERFACE_ID << 8) | NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_MAX_CES 64
#define NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS_MESSAGE_ID (0xaU)
typedef struct NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS {
NvU8 capsTbl[NV2080_CTRL_MAX_PCES][NV2080_CTRL_CE_CAPS_TBL_SIZE];
NvU32 present;
NvU8 capsTbl[NV2080_CTRL_MAX_CES][NV2080_CTRL_CE_CAPS_TBL_SIZE];
NV_DECLARE_ALIGNED(NvU64 present, 8);
} NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS;
#define NV2080_CTRL_CMD_CE_GET_ALL_PHYSICAL_CAPS (0x20802a0b) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_CE_INTERFACE_ID << 8) | NV2080_CTRL_CE_GET_ALL_PHYSICAL_CAPS_PARAMS_MESSAGE_ID" */

65
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080fb.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2006-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2006-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -266,6 +266,8 @@
* NV2080_CTRL_FB_INFO_INDEX_ECC_STATUS_SIZE
* Returns the ECC status size (corresponds to subpartitions or channels
* depending on architecture/memory type).
* NV2080_CTRL_FB_INFO_INDEX_IS_ZERO_FB
* Returns true if FB is not present on this chip
*/
typedef NVXXXX_CTRL_XXX_INFO NV2080_CTRL_FB_INFO;
@@ -328,9 +330,10 @@ typedef NVXXXX_CTRL_XXX_INFO NV2080_CTRL_FB_INFO;
#define NV2080_CTRL_FB_INFO_INDEX_PROTECTED_MEM_SIZE_TOTAL_KB (0x00000033U)
#define NV2080_CTRL_FB_INFO_INDEX_PROTECTED_MEM_SIZE_FREE_KB (0x00000034U)
#define NV2080_CTRL_FB_INFO_INDEX_ECC_STATUS_SIZE (0x00000035U)
#define NV2080_CTRL_FB_INFO_MAX_LIST_SIZE (0x00000036U)
#define NV2080_CTRL_FB_INFO_INDEX_IS_ZERO_FB (0x00000036U)
#define NV2080_CTRL_FB_INFO_MAX_LIST_SIZE (0x00000037U)
#define NV2080_CTRL_FB_INFO_INDEX_MAX (0x35U) /* finn: Evaluated from "(NV2080_CTRL_FB_INFO_MAX_LIST_SIZE - 1)" */
#define NV2080_CTRL_FB_INFO_INDEX_MAX (0x36U) /* finn: Evaluated from "(NV2080_CTRL_FB_INFO_MAX_LIST_SIZE - 1)" */
/* valid fb RAM type values */
#define NV2080_CTRL_FB_INFO_RAM_TYPE_UNKNOWN (0x00000000U)
@@ -2328,7 +2331,7 @@ typedef struct NV2080_CTRL_FB_FS_INFO_QUERY {
} NV2080_CTRL_FB_FS_INFO_QUERY;
// Max number of queries that can be batched in a single call to NV2080_CTRL_CMD_FB_GET_FS_INFO
#define NV2080_CTRL_FB_FS_INFO_MAX_QUERIES 96U
#define NV2080_CTRL_FB_FS_INFO_MAX_QUERIES 120U
#define NV2080_CTRL_FB_GET_FS_INFO_PARAMS_MESSAGE_ID (0x46U)
@@ -2651,4 +2654,58 @@ typedef struct NV2080_CTRL_FB_GET_SEMAPHORE_SURFACE_LAYOUT_PARAMS {
NvU32 caps;
} NV2080_CTRL_FB_GET_SEMAPHORE_SURFACE_LAYOUT_PARAMS;
typedef struct NV2080_CTRL_CMD_FB_STATS_ENTRY {
//! Total physical memory available (accounts row-remapping)
NV_DECLARE_ALIGNED(NvU64 totalSize, 8);
//! Total reserved memory (includes both Region 1 and region 2)
NV_DECLARE_ALIGNED(NvU64 rsvdSize, 8);
//! Total usable memory (Region 0) for OS/KMD
NV_DECLARE_ALIGNED(NvU64 osSize, 8);
//! Region 1 (RM Internal) memory
NV_DECLARE_ALIGNED(NvU64 r1Size, 8);
//! Region 2 (Reserved) memory
NV_DECLARE_ALIGNED(NvU64 r2Size, 8);
//! Free memory (reserved but not allocated)
NV_DECLARE_ALIGNED(NvU64 freeSize, 8);
} NV2080_CTRL_CMD_FB_STATS_ENTRY;
typedef struct NV2080_CTRL_CMD_FB_STATS_OWNER_INFO {
//! Total allocated size for this owner
NV_DECLARE_ALIGNED(NvU64 allocSize, 8);
//! Total memory blocks belonging this owner
NvU32 numBlocks;
//! Total reserved size for this owner
NV_DECLARE_ALIGNED(NvU64 rsvdSize, 8);
} NV2080_CTRL_CMD_FB_STATS_OWNER_INFO;
#define NV2080_CTRL_CMD_FB_STATS_MAX_OWNER 200U
/*
* NV2080_CTRL_CMD_FB_STATS_GET
*
* Get the FB allocations info.
*/
#define NV2080_CTRL_CMD_FB_STATS_GET (0x2080132a) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_CMD_FB_STATS_GET_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_CMD_FB_STATS_GET_PARAMS_MESSAGE_ID (0x2AU)
typedef struct NV2080_CTRL_CMD_FB_STATS_GET_PARAMS {
//! Version id for driver and tool matching
NV_DECLARE_ALIGNED(NvU64 version, 8);
//! All sizes info
NV_DECLARE_ALIGNED(NV2080_CTRL_CMD_FB_STATS_ENTRY fbSizeInfo, 8);
//! Level 2 owner info table
NV_DECLARE_ALIGNED(NV2080_CTRL_CMD_FB_STATS_OWNER_INFO fbBlockInfo[NV2080_CTRL_CMD_FB_STATS_MAX_OWNER], 8);
} NV2080_CTRL_CMD_FB_STATS_GET_PARAMS;
/* _ctrl2080fb_h_ */

42
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080gpu.h
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@@ -35,7 +35,7 @@
#include "nvcfg_sdk.h"
#include "nvstatus.h"
#define NV_GRID_LICENSE_INFO_MAX_LENGTH (128)
#define NV_GRID_LICENSE_INFO_MAX_LENGTH (128)
/* License info strings for vGPU products */
#define NV_GRID_LICENSE_FEATURE_VPC_EDITION "GRID-Virtual-PC,2.0;Quadro-Virtual-DWS,5.0;GRID-Virtual-WS,2.0;GRID-Virtual-WS-Ext,2.0"
@@ -54,11 +54,6 @@
/* NV20_SUBDEVICE_XX gpu control commands and parameters */
/* Valid feature values */
#define NV2080_CTRL_GPU_GET_FEATURES_CLK_ARCH_DOMAINS 0:0
#define NV2080_CTRL_GPU_GET_FEATURES_CLK_ARCH_DOMAINS_FALSE (0x00000000U)
#define NV2080_CTRL_GPU_GET_FEATURES_CLK_ARCH_DOMAINS_TRUE (0x00000001U)
typedef NVXXXX_CTRL_XXX_INFO NV2080_CTRL_GPU_INFO;
@@ -112,7 +107,10 @@ typedef NVXXXX_CTRL_XXX_INFO NV2080_CTRL_GPU_INFO;
#define NV2080_CTRL_GPU_INFO_INDEX_IS_RESETLESS_MIG_SUPPORTED (0x0000003fU)
#define NV2080_CTRL_GPU_INFO_MAX_LIST_SIZE (0x00000040U)
#define NV2080_CTRL_GPU_INFO_MAX_LIST_SIZE (0x00000041U)
/* valid minor revision extended values */
#define NV2080_CTRL_GPU_INFO_MINOR_REVISION_EXT_NONE (0x00000000U)
@@ -750,7 +748,7 @@ typedef struct NV2080_CTRL_GPU_GET_ENGINES_PARAMS {
#define NV2080_CTRL_CMD_GPU_GET_ENGINES_V2 (0x20800170U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_ENGINES_V2_PARAMS_MESSAGE_ID" */
/* Must match NV2080_ENGINE_TYPE_LAST from cl2080.h */
#define NV2080_GPU_MAX_ENGINES_LIST_SIZE 0x3EU
#define NV2080_GPU_MAX_ENGINES_LIST_SIZE 0x3FU
#define NV2080_CTRL_GPU_GET_ENGINES_V2_PARAMS_MESSAGE_ID (0x70U)
@@ -1123,7 +1121,7 @@ typedef struct NV2080_CTRL_GPU_QUERY_ECC_INTR_PARAMS {
#define NV2080_CTRL_CMD_GPU_QUERY_ECC_STATUS (0x2080012fU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_GPU_ECC_UNIT_COUNT (0x00000018U)
#define NV2080_CTRL_GPU_ECC_UNIT_COUNT (0x00000019U)
@@ -2244,16 +2242,6 @@ typedef struct NV2080_CTRL_GPU_GET_OEM_INFO_PARAMS {
NvU8 oemInfo[NV2080_GPU_MAX_OEM_INFO_LENGTH];
} NV2080_CTRL_GPU_GET_OEM_INFO_PARAMS;
/* NV2080_CTRL_CMD_GPU_PROCESS_POST_GC6_EXIT_TASKS
*
* Complete any pending tasks the need to be run after GC6 exit is complete at OS/KMD level
*
* Possible status return values are:
* NV_OK
* NV_ERR_NOT_READY
*/
#define NV2080_CTRL_CMD_GPU_PROCESS_POST_GC6_EXIT_TASKS (0x2080016aU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | 0x6A" */
/*
* NV2080_CTRL_CMD_GPU_GET_VPR_INFO
*
@@ -2286,7 +2274,7 @@ typedef struct NV2080_CTRL_GPU_GET_OEM_INFO_PARAMS {
* NV_OK
* NV_ERR_NOT_SUPPORTED
*/
#define NV2080_CTRL_CMD_GPU_GET_VPR_INFO (0x2080016bU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_VPR_INFO_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_CMD_GPU_GET_VPR_INFO (0x2080016bU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_VPR_INFO_PARAMS_MESSAGE_ID" */
typedef enum NV2080_CTRL_VPR_INFO_QUERY_TYPE {
@@ -2315,6 +2303,8 @@ typedef struct NV2080_CTRL_GPU_GET_VPR_INFO_PARAMS {
* H.264 encoding capacity on this GPU.
* 2. NV2080_CTRL_GPU_GET_ENCODER_CAPACITY_HEVC: Use this to query the
* H.265/HEVC encoding capacity on this GPU.
* 3. NV2080_CTRL_GPU_GET_ENCODER_CAPACITY_AV1: Use this to query the
* AV1 encoding capacity on this GPU.
*
* encoderCapacity [out]
* Encoder capacity value from 0 to 100. Value of 0x00 indicates encoder performance
@@ -2330,6 +2320,7 @@ typedef struct NV2080_CTRL_GPU_GET_VPR_INFO_PARAMS {
typedef enum NV2080_CTRL_ENCODER_CAPACITY_QUERY_TYPE {
NV2080_CTRL_GPU_GET_ENCODER_CAPACITY_H264 = 0,
NV2080_CTRL_GPU_GET_ENCODER_CAPACITY_HEVC = 1,
NV2080_CTRL_GPU_GET_ENCODER_CAPACITY_AV1 = 2,
} NV2080_CTRL_ENCODER_CAPACITY_QUERY_TYPE;
#define NV2080_CTRL_GPU_GET_ENCODER_CAPACITY_PARAMS_MESSAGE_ID (0x6CU)
@@ -2706,6 +2697,9 @@ typedef struct NV2080_CTRL_GPU_SET_PARTITIONS_PARAMS {
* validCTSIdMask[OUT]
* - Mask of CTS IDs usable by this partition, not reflecting current allocations
*
* validGfxCTSIdMask[OUT]
* - Mask of CTS IDs that contain Gfx capable Grs usable by this partition, not reflecting current allocations
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
@@ -2735,6 +2729,7 @@ typedef struct NV2080_CTRL_GPU_GET_PARTITION_INFO {
NvBool bValid;
NvBool bPartitionError;
NV_DECLARE_ALIGNED(NvU64 validCTSIdMask, 8);
NV_DECLARE_ALIGNED(NvU64 validGfxCTSIdMask, 8);
} NV2080_CTRL_GPU_GET_PARTITION_INFO;
/*
@@ -4041,7 +4036,9 @@ typedef struct NV2080_CTRL_GPU_GET_COMPUTE_PROFILES_PARAMS {
#define NV2080_GPU_FABRIC_CLUSTER_UUID_LEN 16U
#define NV2080_CTRL_GPU_FABRIC_PROBE_CAP_MC_SUPPORTED NVBIT64(0)
#define NV2080_CTRL_GPU_FABRIC_PROBE_CAP_MC_SUPPORTED NVBIT64(0)
/*!
* NV2080_CTRL_CMD_GET_GPU_FABRIC_PROBE_INFO_PARAMS
@@ -4070,6 +4067,8 @@ typedef struct NV2080_CTRL_GPU_GET_COMPUTE_PROFILES_PARAMS {
* - Summary of fabric capabilities received from probe resp
* Possible values are
* NV2080_CTRL_GPU_FABRIC_PROBE_CAP_*
* fabricCliqueId[OUT]
* - Unique ID of a set of GPUs within a fabric partition that can perform P2P
*/
#define NV2080_CTRL_CMD_GET_GPU_FABRIC_PROBE_INFO_PARAMS_MESSAGE_ID (0xA3U)
@@ -4079,6 +4078,7 @@ typedef struct NV2080_CTRL_CMD_GET_GPU_FABRIC_PROBE_INFO_PARAMS {
NvU8 clusterUuid[NV2080_GPU_FABRIC_CLUSTER_UUID_LEN];
NvU16 fabricPartitionId;
NV_DECLARE_ALIGNED(NvU64 fabricCaps, 8);
NvU32 fabricCliqueId;
} NV2080_CTRL_CMD_GET_GPU_FABRIC_PROBE_INFO_PARAMS;
#define NV2080_CTRL_CMD_GET_GPU_FABRIC_PROBE_INFO (0x208001a3) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_CMD_GET_GPU_FABRIC_PROBE_INFO_PARAMS_MESSAGE_ID" */

53
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080gr.h
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@@ -260,6 +260,9 @@ typedef NV0080_CTRL_GR_INFO NV2080_CTRL_GR_INFO;
#define NV2080_CTRL_GR_INFO_INDEX_DUMMY NV0080_CTRL_GR_INFO_INDEX_DUMMY
#define NV2080_CTRL_GR_INFO_INDEX_GFX_CAPABILITIES NV0080_CTRL_GR_INFO_INDEX_GFX_CAPABILITIES
#define NV2080_CTRL_GR_INFO_INDEX_MAX_MIG_ENGINES NV0080_CTRL_GR_INFO_INDEX_MAX_MIG_ENGINES
#define NV2080_CTRL_GR_INFO_INDEX_MAX_PARTITIONABLE_GPCS NV0080_CTRL_GR_INFO_INDEX_MAX_PARTITIONABLE_GPCS
#define NV2080_CTRL_GR_INFO_INDEX_LITTER_MIN_SUBCTX_PER_SMC_ENG NV0080_CTRL_GR_INFO_INDEX_LITTER_MIN_SUBCTX_PER_SMC_ENG
/* When adding a new INDEX, please update INDEX_MAX and MAX_SIZE accordingly
* NOTE: 0080 functionality is merged with 2080 functionality, so this max size
@@ -1276,16 +1279,24 @@ typedef struct NV2080_CTRL_GR_GFX_POOL_QUERY_SIZE_PARAMS {
* NV2080_CTRL_GR_GFX_POOL_INITIALIZE_PARAMS
* struct to hand in the required info to RM
*
* pControlStructure
* This input is the kernel CPU pointer to the control structure.
* maxSlots
* Max pool slots
* hMemory
* Handle to GFX Pool memory
* offset
* Offset of the control structure in GFX Pool memory
* size
* Size of the control structure
*/
#define NV2080_CTRL_CMD_GR_GFX_POOL_INITIALIZE (0x20801220U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_GFX_POOL_INITIALIZE_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_GR_GFX_POOL_INITIALIZE_PARAMS_MESSAGE_ID (0x20U)
typedef struct NV2080_CTRL_GR_GFX_POOL_INITIALIZE_PARAMS {
NV_DECLARE_ALIGNED(NvP64 pControlStructure, 8);
NvU32 maxSlots;
NvU32 maxSlots;
NvHandle hMemory;
NvU32 offset;
NvU32 size;
} NV2080_CTRL_GR_GFX_POOL_INITIALIZE_PARAMS;
#define NV2080_CTRL_GR_GFX_POOL_MAX_SLOTS 64U
@@ -1301,21 +1312,27 @@ typedef struct NV2080_CTRL_GR_GFX_POOL_INITIALIZE_PARAMS {
*
* NV2080_CTRL_GR_GFX_POOL_ADD_SLOTS_PARAMS
*
* pControlStructure
* This input is the kernel CPU pointer to the control structure
* numSlots
* This input indicates how many slots are being added and are contained in the slots parameter
* slots
* This input contains an array of the slots to be added to the control structure
* hMemory
* Handle to GFX Pool memory
* offset
* Offset of the control structure in GFX Pool memory
* size
* Size of the control structure
*/
#define NV2080_CTRL_CMD_GR_GFX_POOL_ADD_SLOTS (0x20801221U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_GFX_POOL_ADD_SLOTS_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_GR_GFX_POOL_ADD_SLOTS_PARAMS_MESSAGE_ID (0x21U)
typedef struct NV2080_CTRL_GR_GFX_POOL_ADD_SLOTS_PARAMS {
NV_DECLARE_ALIGNED(NvP64 pControlStructure, 8);
NvU32 numSlots;
NvU32 slots[NV2080_CTRL_GR_GFX_POOL_MAX_SLOTS];
NvU32 numSlots;
NvU32 slots[NV2080_CTRL_GR_GFX_POOL_MAX_SLOTS];
NvHandle hMemory;
NvU32 offset;
NvU32 size;
} NV2080_CTRL_GR_GFX_POOL_ADD_SLOTS_PARAMS;
/*
@@ -1330,8 +1347,6 @@ typedef struct NV2080_CTRL_GR_GFX_POOL_ADD_SLOTS_PARAMS {
*
* NV2080_CTRL_CMD_GR_GFX_POOL_REMOVE_SLOTS_PARAMS
*
* pControlStructure
* This input is the kernel CPU pointer to the control structure
* numSlots
* This input indicates how many slots are being removed. if
* bRemoveSpecificSlots is true, then it also indicates how many entries in
@@ -1348,16 +1363,24 @@ typedef struct NV2080_CTRL_GR_GFX_POOL_ADD_SLOTS_PARAMS {
* the number of slots they want removed and RM will pick up to that
* many. If there are not enough slots on the freelist to remove the
* requested amount, RM will return the number it was able to remove.
* hMemory
* Handle to GFX Pool memory
* offset
* Offset of the control structure in GFX Pool memory
* size
* Size of the control structure
*/
#define NV2080_CTRL_CMD_GR_GFX_POOL_REMOVE_SLOTS (0x20801222U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_GFX_POOL_REMOVE_SLOTS_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_GR_GFX_POOL_REMOVE_SLOTS_PARAMS_MESSAGE_ID (0x22U)
typedef struct NV2080_CTRL_GR_GFX_POOL_REMOVE_SLOTS_PARAMS {
NV_DECLARE_ALIGNED(NvP64 pControlStructure, 8);
NvU32 numSlots;
NvU32 slots[NV2080_CTRL_GR_GFX_POOL_MAX_SLOTS];
NvBool bRemoveSpecificSlots;
NvU32 numSlots;
NvU32 slots[NV2080_CTRL_GR_GFX_POOL_MAX_SLOTS];
NvBool bRemoveSpecificSlots;
NvHandle hMemory;
NvU32 offset;
NvU32 size;
} NV2080_CTRL_GR_GFX_POOL_REMOVE_SLOTS_PARAMS;

11
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080gsp.h
View File

@@ -75,9 +75,12 @@ typedef struct NV2080_CTRL_GSP_GET_FEATURES_PARAMS {
} NV2080_CTRL_GSP_GET_FEATURES_PARAMS;
/* Valid feature values */
#define NV2080_CTRL_GSP_GET_FEATURES_UVM_ENABLED 0:0
#define NV2080_CTRL_GSP_GET_FEATURES_UVM_ENABLED_FALSE (0x00000000)
#define NV2080_CTRL_GSP_GET_FEATURES_UVM_ENABLED_TRUE (0x00000001)
#define NV2080_CTRL_GSP_GET_FEATURES_UVM_ENABLED 0:0
#define NV2080_CTRL_GSP_GET_FEATURES_UVM_ENABLED_FALSE (0x00000000)
#define NV2080_CTRL_GSP_GET_FEATURES_UVM_ENABLED_TRUE (0x00000001)
#define NV2080_CTRL_GSP_GET_FEATURES_VGPU_GSP_MIG_REFACTORING_ENABLED 1:1
#define NV2080_CTRL_GSP_GET_FEATURES_VGPU_GSP_MIG_REFACTORING_ENABLED_FALSE (0x00000000)
#define NV2080_CTRL_GSP_GET_FEATURES_VGPU_GSP_MIG_REFACTORING_ENABLED_TRUE (0x00000001)
/*
* NV2080_CTRL_CMD_GSP_GET_RM_HEAP_STATS
@@ -95,7 +98,7 @@ typedef struct NV2080_CTRL_GSP_GET_FEATURES_PARAMS {
* An NV2080_CTRL_GSP_RM_HEAP_STATS_SNAPSHOT record corresponding to
* the "high water mark" of heap usage since GSP-RM was started.
*/
#define NV2080_CTRL_CMD_GSP_GET_RM_HEAP_STATS (0x20803602) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GSP_INTERFACE_ID << 8) | NV2080_CTRL_GSP_GET_RM_HEAP_STATS_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_CMD_GSP_GET_RM_HEAP_STATS (0x20803602) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GSP_INTERFACE_ID << 8) | NV2080_CTRL_GSP_GET_RM_HEAP_STATS_PARAMS_MESSAGE_ID" */
/*
* NV2080_CTRL_GSP_RM_HEAP_STATS_SNAPSHOT

18
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080hshub.h
View File

@@ -52,4 +52,22 @@ typedef struct NV2080_CTRL_CMD_HSHUB_GET_AVAILABLE_MASK_PARAMS {
#define NV2080_CTRL_CMD_HSHUB_GET_AVAILABLE_MASK (0x20804101) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_HSHUB_INTERFACE_ID << 8) | NV2080_CTRL_CMD_HSHUB_GET_AVAILABLE_MASK_PARAMS_MESSAGE_ID" */
/*
* NV2080_CTRL_CMD_HSHUB_SET_EC_THROTTLE_MODE
*
* This command sets EC throttle mode registers
*
* ecMode
* EC Mode 0-7 to write to mode register
* status
* return status
*/
#define NV2080_CTRL_CMD_HSHUB_SET_EC_THROTTLE_MODE_PARAMS_MESSAGE_ID (0x2U)
typedef struct NV2080_CTRL_CMD_HSHUB_SET_EC_THROTTLE_MODE_PARAMS {
NvU32 ecMode;
NvU32 status;
} NV2080_CTRL_CMD_HSHUB_SET_EC_THROTTLE_MODE_PARAMS;
#define NV2080_CTRL_CMD_HSHUB_SET_EC_THROTTLE_MODE (0x20804102) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_HSHUB_INTERFACE_ID << 8) | NV2080_CTRL_CMD_HSHUB_SET_EC_THROTTLE_MODE_PARAMS_MESSAGE_ID" */
/* _ctrl2080hshub_h_ */

115
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080internal.h
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@@ -219,6 +219,23 @@ typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_CAPS_PARAMS {
typedef NV2080_CTRL_INTERNAL_STATIC_GR_GET_CAPS_PARAMS NV2080_CTRL_INTERNAL_STATIC_KGR_GET_CAPS_PARAMS;
/*
* NV2080_CTRL_CMD_INTERNAL_FLCN_SET_VIDEO_EVENT_BUFFER_FLAGS
*
* Set flags for use by the video event buffer
*
* flags
* VIDEO_TRACE_FLAG__*
*
*/
#define NV2080_CTRL_CMD_INTERNAL_FLCN_SET_VIDEO_EVENT_BUFFER_FLAGS (0x20800a21) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_FLCN_SET_VIDEO_EVENT_BUFFER_FLAGS_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_INTERNAL_FLCN_SET_VIDEO_EVENT_BUFFER_FLAGS_PARAMS_MESSAGE_ID (0x21U)
typedef struct NV2080_CTRL_INTERNAL_FLCN_SET_VIDEO_EVENT_BUFFER_FLAGS_PARAMS {
NvU32 flags;
} NV2080_CTRL_INTERNAL_FLCN_SET_VIDEO_EVENT_BUFFER_FLAGS_PARAMS;
/*!
* @ref NV2080_CTRL_CMD_GR_GET_GLOBAL_SM_ORDER
* @ref NV2080_CTRL_CMD_GR_GET_SM_TO_GPC_TPC_MAPPINGS
@@ -793,37 +810,6 @@ typedef struct NV2080_CTRL_INTERNAL_GET_CONSTRUCTED_FALCON_INFO_PARAMS {
NV2080_CTRL_INTERNAL_CONSTRUCTED_FALCON_INFO constructedFalconsTable[NV2080_CTRL_CMD_INTERNAL_MAX_CONSTRUCTED_FALCONS];
} NV2080_CTRL_INTERNAL_GET_CONSTRUCTED_FALCON_INFO_PARAMS;
typedef struct NV2080_CTRL_INTERNAL_NV_RANGE {
NV_DECLARE_ALIGNED(NvU64 lo, 8);
NV_DECLARE_ALIGNED(NvU64 hi, 8);
} NV2080_CTRL_INTERNAL_NV_RANGE;
/*!
* NV2080_CTRL_INTERNAL_MIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS
*
* This structure specifies a target swizz-id and mem_range to update
*
* swizzId[IN]
* - Targeted swizz-id for which the memRange is being set
*
* memAddrRange[IN]
* - Memory Range for given GPU instance
*/
#define NV2080_CTRL_INTERNAL_MIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS_MESSAGE_ID (0x43U)
typedef struct NV2080_CTRL_INTERNAL_MIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS {
NvU32 swizzId;
NV_DECLARE_ALIGNED(NV2080_CTRL_INTERNAL_NV_RANGE memAddrRange, 8);
} NV2080_CTRL_INTERNAL_MIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS;
#define NV2080_CTRL_CMD_INTERNAL_KMIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE (0x20800a44) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_KMIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_INTERNAL_KMIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS_MESSAGE_ID (0x44U)
typedef NV2080_CTRL_INTERNAL_MIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS NV2080_CTRL_INTERNAL_KMIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS;
#define NV2080_CTRL_CMD_INTERNAL_MIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE (0x20800a43) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS_MESSAGE_ID" */
/**
* Get GR PDB properties synchronized between Kernel and Physical
*
@@ -1000,6 +986,9 @@ typedef struct NV2080_CTRL_INTERNAL_DISPLAY_SETUP_RG_LINE_INTR_PARAMS {
*
* validCTSIdMask [OUT]
* # mask of CTS IDs which can be assigned under this profile
*
* validGfxCTSIdMask [OUT]
* # mask of CTS IDs that contain Gfx capable Grs which can be assigned under this profile
*/
#define NV2080_CTRL_INTERNAL_GRMGR_PARTITION_MAX_TYPES 20
@@ -1020,6 +1009,7 @@ typedef struct NV2080_CTRL_INTERNAL_MIGMGR_PROFILE_INFO {
NvU32 nvJpgCount;
NvU32 nvOfaCount;
NV_DECLARE_ALIGNED(NvU64 validCTSIdMask, 8);
NV_DECLARE_ALIGNED(NvU64 validGfxCTSIdMask, 8);
} NV2080_CTRL_INTERNAL_MIGMGR_PROFILE_INFO;
/*!
@@ -1543,6 +1533,11 @@ typedef struct NV2080_CTRL_INTERNAL_DISPLAY_GET_ACTIVE_DISPLAY_DEVICES_PARAMS {
#define NV2080_CTRL_INTERNAL_MAX_SWIZZ_ID 15
typedef struct NV2080_CTRL_INTERNAL_NV_RANGE {
NV_DECLARE_ALIGNED(NvU64 lo, 8);
NV_DECLARE_ALIGNED(NvU64 hi, 8);
} NV2080_CTRL_INTERNAL_NV_RANGE;
#define NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES_PARAMS_MESSAGE_ID (0x60U)
typedef struct NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES_PARAMS {
@@ -1577,12 +1572,6 @@ typedef struct NV2080_CTRL_INTERNAL_FIFO_GET_NUM_CHANNELS_PARAMS {
typedef NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PROFILES_PARAMS NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_PROFILES_PARAMS;
/*!
* @ref NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_VALID_SWIZZID_MASK
* @ref NV2080_CTRL_CMD_INTERNAL_STATIC_MIGMGR_GET_VALID_SWIZZID_MASK
*/
#define NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_VALID_SWIZZID_MASK (0x20800a64) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x64" */
/*!
* NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_PARTITIONABLE_ENGINES
* NV2080_CTRL_CMD_INTERNAL_STATIC_MIGMGR_GET_PARTITIONABLE_ENGINES
@@ -1981,7 +1970,7 @@ typedef struct NV2080_CTRL_INTERNAL_PERF_BOOST_CLEAR_PARAMS_3X {
#define NV2080_CTRL_CMD_INTERNAL_STATIC_GRMGR_GET_SKYLINE_INFO (0x20800aa2) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_GRMGR_GET_SKYLINE_INFO_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_INTERNAL_GRMGR_SKYLINE_INFO_MAX_SKYLINES 8
#define NV2080_CTRL_INTERNAL_GRMGR_SKYLINE_INFO_MAX_NON_SINGLETON_VGPCS 8
#define NV2080_CTRL_INTERNAL_GRMGR_SKYLINE_INFO_MAX_NON_SINGLETON_VGPCS 12
/*!
* NV2080_CTRL_INTERNAL_GRMGR_SKYLINE_INFO
* skylineVgpcSize[OUT]
@@ -2181,6 +2170,8 @@ typedef struct NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_PARAMS {
typedef struct NV2080_CTRL_INTERNAL_BIF_GET_STATIC_INFO_PARAMS {
NvBool bPcieGen4Capable;
NvBool bIsC2CLinkUp;
NvBool bIsDeviceMultiFunction;
NvBool bGcxPmuCfgSpaceRestore;
NV_DECLARE_ALIGNED(NvU64 dmaWindowStartAddress, 8);
} NV2080_CTRL_INTERNAL_BIF_GET_STATIC_INFO_PARAMS;
@@ -3417,20 +3408,21 @@ typedef struct NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_VPSTATE_PARAMS {
} NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_VPSTATE_PARAMS;
/*
* NV2080_CTRL_CMD_INTERNAL_GC6_ENTRY_PREREQUISITE
* NV2080_CTRL_CMD_INTERNAL_GCX_ENTRY_PREREQUISITE
*
* This command gets if GPU is in a proper state (P8 and engine idle) to be ready to enter RTD3
*
* Possible status return values are:
* NV_OK Success
*/
#define NV2080_CTRL_CMD_INTERNAL_GC6_ENTRY_PREREQUISITE (0x2080a7d7) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_POWER_LEGACY_NON_PRIVILEGED_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GC6_ENTRY_PREREQUISITE_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_CMD_INTERNAL_GCX_ENTRY_PREREQUISITE (0x2080a7d7) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_POWER_LEGACY_NON_PRIVILEGED_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GCX_ENTRY_PREREQUISITE_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_INTERNAL_GC6_ENTRY_PREREQUISITE_PARAMS_MESSAGE_ID (0xD7U)
#define NV2080_CTRL_INTERNAL_GCX_ENTRY_PREREQUISITE_PARAMS_MESSAGE_ID (0xD7U)
typedef struct NV2080_CTRL_INTERNAL_GC6_ENTRY_PREREQUISITE_PARAMS {
NvBool bIsSatisfied;
} NV2080_CTRL_INTERNAL_GC6_ENTRY_PREREQUISITE_PARAMS;
typedef struct NV2080_CTRL_INTERNAL_GCX_ENTRY_PREREQUISITE_PARAMS {
NvBool bIsGC6Satisfied;
NvBool bIsGCOFFSatisfied;
} NV2080_CTRL_INTERNAL_GCX_ENTRY_PREREQUISITE_PARAMS;
/*
* This command unsets Dynamic Boost limit when nvidia-powerd is terminated unexpectedly.
@@ -3910,4 +3902,39 @@ typedef struct NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_GET_EDPP_LIMIT_INFO_P
NvU32 limitBattMax;
} NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_GET_EDPP_LIMIT_INFO_PARAMS;
/*
* NV2080_CTRL_CMD_INTERNAL_INIT_USER_SHARED_DATA
*
* @brief Initialize RM User Shared Data memory mapping on physical RM
*
* @param[in] physAddr Physical address of memdesc to link physical to kernel
* 0 to de-initialize
*
* @return NV_OK on success
* @return NV_ERR_ otherwise
*/
#define NV2080_CTRL_INTERNAL_INIT_USER_SHARED_DATA_PARAMS_MESSAGE_ID (0xFEU)
typedef struct NV2080_CTRL_INTERNAL_INIT_USER_SHARED_DATA_PARAMS {
NV_DECLARE_ALIGNED(NvU64 physAddr, 8);
} NV2080_CTRL_INTERNAL_INIT_USER_SHARED_DATA_PARAMS;
#define NV2080_CTRL_CMD_INTERNAL_INIT_USER_SHARED_DATA (0x20800afe) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_INIT_USER_SHARED_DATA_PARAMS_MESSAGE_ID" */
/*
* NV2080_CTRL_CMD_INTERNAL_USER_SHARED_DATA_SET_DATA_POLL
*
* @brief Set mask of data to be polled on physical for RUSD
*
* @param[in] polledDataMask Bitmask of data requested, defined in cl00de
*
* @return NV_OK on success
* @return NV_ERR_ otherwise
*/
#define NV2080_CTRL_INTERNAL_USER_SHARED_DATA_SET_DATA_POLL_PARAMS_MESSAGE_ID (0xFFU)
typedef struct NV2080_CTRL_INTERNAL_USER_SHARED_DATA_SET_DATA_POLL_PARAMS {
NV_DECLARE_ALIGNED(NvU64 polledDataMask, 8);
} NV2080_CTRL_INTERNAL_USER_SHARED_DATA_SET_DATA_POLL_PARAMS;
#define NV2080_CTRL_CMD_INTERNAL_USER_SHARED_DATA_SET_DATA_POLL (0x20800aff) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_USER_SHARED_DATA_SET_DATA_POLL_PARAMS_MESSAGE_ID" */
/* ctrl2080internal_h */

12
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080nvd.h
View File

@@ -281,6 +281,7 @@ typedef struct NV2080_CTRL_NVD_GET_NOCAT_JOURNAL_PARAMS {
#define NV2080_CTRL_NOCAT_JOURNAL_DATA_TYPE_TDR_REASON 1
#define NV2080_CTRL_NOCAT_JOURNAL_DATA_TYPE_INSERT_RECORD 2
#define NV2080_CTRL_NOCAT_JOURNAL_DATA_TYPE_SET_TAG 3
#define NV2080_CTRL_NOCAT_JOURNAL_DATA_TYPE_RCLOG 4
#define NV2080_CTRL_NOCAT_TDR_TYPE_NONE 0
#define NV2080_CTRL_NOCAT_TDR_TYPE_LEGACY 1
@@ -324,6 +325,16 @@ typedef struct NV2080CtrlNocatJournalSetTag {
NvU8 tag[NV2080_NOCAT_JOURNAL_MAX_STR_LEN];
} NV2080CtrlNocatJournalSetTag;
typedef struct NV2080CtrlNocatJournalRclog {
NvU32 flags;
NvU32 rclogSize; // rclog size
NvU32 rmGpuId; // RMGpuId associated with the adapter
NvU32 APIType; // API Type (dx9, dx1x, ogl, etc.)
NvU32 contextType; // Context type (OGL, DX, etc.)
NvU32 exceptType; // ROBUST_CHANNEL_* error identifier
NvU8 processImageName[NV2080_NOCAT_JOURNAL_MAX_STR_LEN]; // process image name (without path)
} NV2080CtrlNocatJournalRclog;
#define NV2080_CTRL_NVD_SET_NOCAT_JOURNAL_DATA_PARAMS_MESSAGE_ID (0xBU)
typedef struct NV2080_CTRL_NVD_SET_NOCAT_JOURNAL_DATA_PARAMS {
@@ -333,6 +344,7 @@ typedef struct NV2080_CTRL_NVD_SET_NOCAT_JOURNAL_DATA_PARAMS {
NV_DECLARE_ALIGNED(NV2080CtrlNocatJournalDataTdrReason tdrReason, 8);
NV_DECLARE_ALIGNED(NV2080CtrlNocatJournalInsertRecord insertData, 8);
NV2080CtrlNocatJournalSetTag tagData;
NV2080CtrlNocatJournalRclog rclog;
} nocatJournalData;
} NV2080_CTRL_NVD_SET_NOCAT_JOURNAL_DATA_PARAMS;
/* _ctr2080nvd_h_ */

89
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080nvlink.h
View File

@@ -2971,8 +2971,91 @@ typedef struct NV2080_CTRL_NVLINK_POST_FAULT_UP_PARAMS {
NvU32 linkId;
} NV2080_CTRL_NVLINK_POST_FAULT_UP_PARAMS;
#define NV2080_CTRL_CMD_NVLINK_POST_FAULT_UP (0x20803043U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_POST_FAULT_UP_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_CMD_NVLINK_POST_FAULT_UP (0x20803043U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_POST_FAULT_UP_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_NVLINK_PORT_EVENT_COUNT_SIZE 64U
/*
* Structure to store port event information
*
* portEventType
* Type of port even that occurred: NVLINK_PORT_EVENT_TYPE*
*
* gpuId
* Gpu that port event occurred on
*
* linkId
* Link id that port event occurred on
*
* time
* Platform time (nsec) when event occurred
*/
typedef struct NV2080_CTRL_NVLINK_PORT_EVENT {
NvU32 portEventType;
NvU32 gpuId;
NvU32 linkId;
NV_DECLARE_ALIGNED(NvU64 time, 8);
} NV2080_CTRL_NVLINK_PORT_EVENT;
/*
* NV2080_CTRL_CMD_NVLINK_GET_PORT_EVENTS
*
* This command returns the port up and port down events that have occurred
*
* Parameters:
*
* portEventIndex [IN/OUT]
* On input: The index of the first port event at which to start reading out of the driver.
*
* On output: The index of the first port event that wasn't reported through the 'port event' array
* in this call to NV2080_CTRL_CMD_NVLINK_GET_PORT_EVENTS.
*
* nextPortEventIndex[OUT]
* The index that will be assigned to the next port event that occurs.
* Users of the GET_PORT_EVENTS control call may set 'portEventIndex' to this field on initialization
* to bypass port events that have already occurred without making multiple control calls.
*
* portEventCount [OUT]
* Number of port events returned by the call. Currently, portEventCount is limited
* by NV2080_CTRL_NVLINK_PORT_EVENT_COUNT_SIZE. In order to query all the port events, a
* client needs to keep calling the control till portEventCount is zero.
*
* bOverflow [OUT]
* True when the port event log is overflowed and no longer contains all the port
* events that have occurred, false otherwise.
*
* portEvent [OUT]
* The port event entires.
*/
#define NV2080_CTRL_NVLINK_GET_PORT_EVENTS_PARAMS_MESSAGE_ID (0x44U)
typedef struct NV2080_CTRL_NVLINK_GET_PORT_EVENTS_PARAMS {
NV_DECLARE_ALIGNED(NvU64 portEventIndex, 8);
NV_DECLARE_ALIGNED(NvU64 nextPortEventIndex, 8);
NvU32 portEventCount;
NvBool bOverflow;
NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_PORT_EVENT portEvent[NV2080_CTRL_NVLINK_PORT_EVENT_COUNT_SIZE], 8);
} NV2080_CTRL_NVLINK_GET_PORT_EVENTS_PARAMS;
#define NV2080_CTRL_CMD_NVLINK_GET_PORT_EVENTS (0x20803044U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_GET_PORT_EVENTS_PARAMS_MESSAGE_ID" */
/*
* NV2080_CTRL_CMD_NVLINK_CYCLE_LINK
*
* This command cycles a link by faulting it and then retraining the link
*
* Parameters:
*
* linkId [IN]
* The link id of the link to be cycled
*/
#define NV2080_CTRL_NVLINK_CYCLE_LINK_PARAMS_MESSAGE_ID (0x45U)
typedef struct NV2080_CTRL_NVLINK_CYCLE_LINK_PARAMS {
NvU32 linkId;
} NV2080_CTRL_NVLINK_CYCLE_LINK_PARAMS;
#define NV2080_CTRL_CMD_NVLINK_CYCLE_LINK (0x20803045U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_CYCLE_LINK_PARAMS_MESSAGE_ID" */
/*
* NV2080_CTRL_CMD_NVLINK_IS_REDUCED_CONFIG
@@ -2982,13 +3065,13 @@ typedef struct NV2080_CTRL_NVLINK_POST_FAULT_UP_PARAMS {
* [out] bReducedNvlinkConfig
* Link number which the sequence should be triggered
*/
#define NV2080_CTRL_NVLINK_IS_REDUCED_CONFIG_PARAMS_MESSAGE_ID (0x44U)
#define NV2080_CTRL_NVLINK_IS_REDUCED_CONFIG_PARAMS_MESSAGE_ID (0x46U)
typedef struct NV2080_CTRL_NVLINK_IS_REDUCED_CONFIG_PARAMS {
NvBool bReducedNvlinkConfig;
} NV2080_CTRL_NVLINK_IS_REDUCED_CONFIG_PARAMS;
#define NV2080_CTRL_CMD_NVLINK_IS_REDUCED_CONFIG (0x20803044U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_IS_REDUCED_CONFIG_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_CMD_NVLINK_IS_REDUCED_CONFIG (0x20803046U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_IS_REDUCED_CONFIG_PARAMS_MESSAGE_ID" */
/* _ctrl2080nvlink_h_ */

3
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080spdm.h
View File

@@ -60,6 +60,9 @@ typedef struct RM_GSP_SPDM_CC_INIT_CTX {
NvU64_ALIGN32 dmaAddr; // The address RM allocate in SYS memory or FB memory.
NvU32 rmBufferSizeInByte; // The memort size allocated by RM(exclude NV_SPDM_DESC_HEADER)
} RM_GSP_SPDM_CC_INIT_CTX;
typedef struct RM_GSP_SPDM_CC_INIT_CTX *PRM_GSP_SPDM_CC_INIT_CTX;

2
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080ucodefuzzer.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2020-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a

6
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080vgpumgrinternal.h
View File

@@ -52,6 +52,8 @@
* guestFbLengthList - list of guest FB memory length in bytes
* pluginHeapMemoryPhysAddr - plugin heap memory offset
* pluginHeapMemoryLength - plugin heap memory length in bytes
* migRmHeapMemoryPhysAddr - Mig rm heap memory region's physical offset.
* migRmHeapMemoryLength - Mig rm heap memory length in bytes
* bDeviceProfilingEnabled - If set to true, profiling is allowed
*/
#define NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_BOOTLOAD_GSP_VGPU_PLUGIN_TASK (0x20804001) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_VGPU_MGR_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_VGPU_MGR_INTERNAL_BOOTLOAD_GSP_VGPU_PLUGIN_TASK_PARAMS_MESSAGE_ID" */
@@ -59,7 +61,7 @@
#define NV2080_CTRL_MAX_VMMU_SEGMENTS 384
/* Must match NV2080_ENGINE_TYPE_LAST from cl2080.h */
#define NV2080_GPU_MAX_ENGINES 0x3e
#define NV2080_GPU_MAX_ENGINES 0x3f
#define NV2080_CTRL_VGPU_MGR_INTERNAL_BOOTLOAD_GSP_VGPU_PLUGIN_TASK_PARAMS_MESSAGE_ID (0x1U)
@@ -83,6 +85,8 @@ typedef struct NV2080_CTRL_VGPU_MGR_INTERNAL_BOOTLOAD_GSP_VGPU_PLUGIN_TASK_PARAM
NV_DECLARE_ALIGNED(NvU64 initTaskLogBuffSize, 8);
NV_DECLARE_ALIGNED(NvU64 vgpuTaskLogBuffOffset, 8);
NV_DECLARE_ALIGNED(NvU64 vgpuTaskLogBuffSize, 8);
NV_DECLARE_ALIGNED(NvU64 migRmHeapMemoryPhysAddr, 8);
NV_DECLARE_ALIGNED(NvU64 migRmHeapMemoryLength, 8);
NvBool bDeviceProfilingEnabled;
} NV2080_CTRL_VGPU_MGR_INTERNAL_BOOTLOAD_GSP_VGPU_PLUGIN_TASK_PARAMS;