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https://github.com/NVIDIA/open-gpu-kernel-modules.git
synced 2026-02-24 00:43:57 +00:00
545.23.06
This commit is contained in:
Andy Ritger
@@ -219,6 +219,23 @@ typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_CAPS_PARAMS {
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typedef NV2080_CTRL_INTERNAL_STATIC_GR_GET_CAPS_PARAMS NV2080_CTRL_INTERNAL_STATIC_KGR_GET_CAPS_PARAMS;
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/*
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* NV2080_CTRL_CMD_INTERNAL_FLCN_SET_VIDEO_EVENT_BUFFER_FLAGS
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*
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* Set flags for use by the video event buffer
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*
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* flags
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* VIDEO_TRACE_FLAG__*
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*
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*/
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#define NV2080_CTRL_CMD_INTERNAL_FLCN_SET_VIDEO_EVENT_BUFFER_FLAGS (0x20800a21) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_FLCN_SET_VIDEO_EVENT_BUFFER_FLAGS_PARAMS_MESSAGE_ID" */
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#define NV2080_CTRL_INTERNAL_FLCN_SET_VIDEO_EVENT_BUFFER_FLAGS_PARAMS_MESSAGE_ID (0x21U)
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typedef struct NV2080_CTRL_INTERNAL_FLCN_SET_VIDEO_EVENT_BUFFER_FLAGS_PARAMS {
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NvU32 flags;
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} NV2080_CTRL_INTERNAL_FLCN_SET_VIDEO_EVENT_BUFFER_FLAGS_PARAMS;
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/*!
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* @ref NV2080_CTRL_CMD_GR_GET_GLOBAL_SM_ORDER
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* @ref NV2080_CTRL_CMD_GR_GET_SM_TO_GPC_TPC_MAPPINGS
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@@ -793,37 +810,6 @@ typedef struct NV2080_CTRL_INTERNAL_GET_CONSTRUCTED_FALCON_INFO_PARAMS {
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NV2080_CTRL_INTERNAL_CONSTRUCTED_FALCON_INFO constructedFalconsTable[NV2080_CTRL_CMD_INTERNAL_MAX_CONSTRUCTED_FALCONS];
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} NV2080_CTRL_INTERNAL_GET_CONSTRUCTED_FALCON_INFO_PARAMS;
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typedef struct NV2080_CTRL_INTERNAL_NV_RANGE {
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NV_DECLARE_ALIGNED(NvU64 lo, 8);
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NV_DECLARE_ALIGNED(NvU64 hi, 8);
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} NV2080_CTRL_INTERNAL_NV_RANGE;
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/*!
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* NV2080_CTRL_INTERNAL_MIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS
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*
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* This structure specifies a target swizz-id and mem_range to update
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*
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* swizzId[IN]
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* - Targeted swizz-id for which the memRange is being set
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*
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* memAddrRange[IN]
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* - Memory Range for given GPU instance
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*/
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#define NV2080_CTRL_INTERNAL_MIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS_MESSAGE_ID (0x43U)
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typedef struct NV2080_CTRL_INTERNAL_MIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS {
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NvU32 swizzId;
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NV_DECLARE_ALIGNED(NV2080_CTRL_INTERNAL_NV_RANGE memAddrRange, 8);
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} NV2080_CTRL_INTERNAL_MIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS;
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#define NV2080_CTRL_CMD_INTERNAL_KMIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE (0x20800a44) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_KMIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS_MESSAGE_ID" */
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#define NV2080_CTRL_INTERNAL_KMIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS_MESSAGE_ID (0x44U)
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typedef NV2080_CTRL_INTERNAL_MIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS NV2080_CTRL_INTERNAL_KMIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS;
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#define NV2080_CTRL_CMD_INTERNAL_MIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE (0x20800a43) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS_MESSAGE_ID" */
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/**
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* Get GR PDB properties synchronized between Kernel and Physical
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*
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@@ -1000,6 +986,9 @@ typedef struct NV2080_CTRL_INTERNAL_DISPLAY_SETUP_RG_LINE_INTR_PARAMS {
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*
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* validCTSIdMask [OUT]
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* # mask of CTS IDs which can be assigned under this profile
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*
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* validGfxCTSIdMask [OUT]
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* # mask of CTS IDs that contain Gfx capable Grs which can be assigned under this profile
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*/
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#define NV2080_CTRL_INTERNAL_GRMGR_PARTITION_MAX_TYPES 20
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@@ -1020,6 +1009,7 @@ typedef struct NV2080_CTRL_INTERNAL_MIGMGR_PROFILE_INFO {
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NvU32 nvJpgCount;
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NvU32 nvOfaCount;
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NV_DECLARE_ALIGNED(NvU64 validCTSIdMask, 8);
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NV_DECLARE_ALIGNED(NvU64 validGfxCTSIdMask, 8);
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} NV2080_CTRL_INTERNAL_MIGMGR_PROFILE_INFO;
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/*!
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@@ -1543,6 +1533,11 @@ typedef struct NV2080_CTRL_INTERNAL_DISPLAY_GET_ACTIVE_DISPLAY_DEVICES_PARAMS {
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#define NV2080_CTRL_INTERNAL_MAX_SWIZZ_ID 15
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typedef struct NV2080_CTRL_INTERNAL_NV_RANGE {
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NV_DECLARE_ALIGNED(NvU64 lo, 8);
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NV_DECLARE_ALIGNED(NvU64 hi, 8);
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} NV2080_CTRL_INTERNAL_NV_RANGE;
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#define NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES_PARAMS_MESSAGE_ID (0x60U)
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typedef struct NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES_PARAMS {
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@@ -1577,12 +1572,6 @@ typedef struct NV2080_CTRL_INTERNAL_FIFO_GET_NUM_CHANNELS_PARAMS {
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typedef NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PROFILES_PARAMS NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_PROFILES_PARAMS;
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/*!
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* @ref NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_VALID_SWIZZID_MASK
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* @ref NV2080_CTRL_CMD_INTERNAL_STATIC_MIGMGR_GET_VALID_SWIZZID_MASK
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*/
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#define NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_VALID_SWIZZID_MASK (0x20800a64) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x64" */
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/*!
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* NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_PARTITIONABLE_ENGINES
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* NV2080_CTRL_CMD_INTERNAL_STATIC_MIGMGR_GET_PARTITIONABLE_ENGINES
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@@ -1981,7 +1970,7 @@ typedef struct NV2080_CTRL_INTERNAL_PERF_BOOST_CLEAR_PARAMS_3X {
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#define NV2080_CTRL_CMD_INTERNAL_STATIC_GRMGR_GET_SKYLINE_INFO (0x20800aa2) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_GRMGR_GET_SKYLINE_INFO_PARAMS_MESSAGE_ID" */
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#define NV2080_CTRL_INTERNAL_GRMGR_SKYLINE_INFO_MAX_SKYLINES 8
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#define NV2080_CTRL_INTERNAL_GRMGR_SKYLINE_INFO_MAX_NON_SINGLETON_VGPCS 8
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#define NV2080_CTRL_INTERNAL_GRMGR_SKYLINE_INFO_MAX_NON_SINGLETON_VGPCS 12
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/*!
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* NV2080_CTRL_INTERNAL_GRMGR_SKYLINE_INFO
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* skylineVgpcSize[OUT]
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@@ -2181,6 +2170,8 @@ typedef struct NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_PARAMS {
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typedef struct NV2080_CTRL_INTERNAL_BIF_GET_STATIC_INFO_PARAMS {
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NvBool bPcieGen4Capable;
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NvBool bIsC2CLinkUp;
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NvBool bIsDeviceMultiFunction;
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NvBool bGcxPmuCfgSpaceRestore;
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NV_DECLARE_ALIGNED(NvU64 dmaWindowStartAddress, 8);
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} NV2080_CTRL_INTERNAL_BIF_GET_STATIC_INFO_PARAMS;
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@@ -3417,20 +3408,21 @@ typedef struct NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_VPSTATE_PARAMS {
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} NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_VPSTATE_PARAMS;
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/*
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* NV2080_CTRL_CMD_INTERNAL_GC6_ENTRY_PREREQUISITE
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* NV2080_CTRL_CMD_INTERNAL_GCX_ENTRY_PREREQUISITE
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*
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* This command gets if GPU is in a proper state (P8 and engine idle) to be ready to enter RTD3
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*
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* Possible status return values are:
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* NV_OK Success
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*/
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#define NV2080_CTRL_CMD_INTERNAL_GC6_ENTRY_PREREQUISITE (0x2080a7d7) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_POWER_LEGACY_NON_PRIVILEGED_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GC6_ENTRY_PREREQUISITE_PARAMS_MESSAGE_ID" */
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#define NV2080_CTRL_CMD_INTERNAL_GCX_ENTRY_PREREQUISITE (0x2080a7d7) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_POWER_LEGACY_NON_PRIVILEGED_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GCX_ENTRY_PREREQUISITE_PARAMS_MESSAGE_ID" */
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#define NV2080_CTRL_INTERNAL_GC6_ENTRY_PREREQUISITE_PARAMS_MESSAGE_ID (0xD7U)
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#define NV2080_CTRL_INTERNAL_GCX_ENTRY_PREREQUISITE_PARAMS_MESSAGE_ID (0xD7U)
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typedef struct NV2080_CTRL_INTERNAL_GC6_ENTRY_PREREQUISITE_PARAMS {
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NvBool bIsSatisfied;
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} NV2080_CTRL_INTERNAL_GC6_ENTRY_PREREQUISITE_PARAMS;
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typedef struct NV2080_CTRL_INTERNAL_GCX_ENTRY_PREREQUISITE_PARAMS {
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NvBool bIsGC6Satisfied;
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NvBool bIsGCOFFSatisfied;
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} NV2080_CTRL_INTERNAL_GCX_ENTRY_PREREQUISITE_PARAMS;
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/*
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* This command unsets Dynamic Boost limit when nvidia-powerd is terminated unexpectedly.
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@@ -3910,4 +3902,39 @@ typedef struct NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_GET_EDPP_LIMIT_INFO_P
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NvU32 limitBattMax;
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} NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_GET_EDPP_LIMIT_INFO_PARAMS;
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/*
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* NV2080_CTRL_CMD_INTERNAL_INIT_USER_SHARED_DATA
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*
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* @brief Initialize RM User Shared Data memory mapping on physical RM
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*
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* @param[in] physAddr Physical address of memdesc to link physical to kernel
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* 0 to de-initialize
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*
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* @return NV_OK on success
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* @return NV_ERR_ otherwise
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*/
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#define NV2080_CTRL_INTERNAL_INIT_USER_SHARED_DATA_PARAMS_MESSAGE_ID (0xFEU)
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typedef struct NV2080_CTRL_INTERNAL_INIT_USER_SHARED_DATA_PARAMS {
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NV_DECLARE_ALIGNED(NvU64 physAddr, 8);
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} NV2080_CTRL_INTERNAL_INIT_USER_SHARED_DATA_PARAMS;
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#define NV2080_CTRL_CMD_INTERNAL_INIT_USER_SHARED_DATA (0x20800afe) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_INIT_USER_SHARED_DATA_PARAMS_MESSAGE_ID" */
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/*
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* NV2080_CTRL_CMD_INTERNAL_USER_SHARED_DATA_SET_DATA_POLL
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*
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* @brief Set mask of data to be polled on physical for RUSD
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*
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* @param[in] polledDataMask Bitmask of data requested, defined in cl00de
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*
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* @return NV_OK on success
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* @return NV_ERR_ otherwise
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*/
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#define NV2080_CTRL_INTERNAL_USER_SHARED_DATA_SET_DATA_POLL_PARAMS_MESSAGE_ID (0xFFU)
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typedef struct NV2080_CTRL_INTERNAL_USER_SHARED_DATA_SET_DATA_POLL_PARAMS {
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NV_DECLARE_ALIGNED(NvU64 polledDataMask, 8);
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} NV2080_CTRL_INTERNAL_USER_SHARED_DATA_SET_DATA_POLL_PARAMS;
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#define NV2080_CTRL_CMD_INTERNAL_USER_SHARED_DATA_SET_DATA_POLL (0x20800aff) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_USER_SHARED_DATA_SET_DATA_POLL_PARAMS_MESSAGE_ID" */
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/* ctrl2080internal_h */
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