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This commit is contained in:
Andy Ritger
2023-10-17 09:25:29 -07:00
parent f59818b751
commit b5bf85a8e3
917 changed files with 132480 additions and 110015 deletions
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114
src/common/sdk/nvidia/inc/ctrl/ctrl90f1.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2014-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2014-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -32,6 +32,7 @@
#include "ctrl/ctrlxxxx.h"
#include "mmu_fmt_types.h"
#include "nvcfg_sdk.h"
#define GMMU_FMT_MAX_LEVELS 6U
@@ -85,30 +86,35 @@ typedef struct NV90F1_CTRL_VASPACE_GET_GMMU_FORMAT_PARAMS {
typedef struct NV_CTRL_VASPACE_PAGE_LEVEL {
/*!
* Format of this level.
*/
* Format of this level.
*/
NV_DECLARE_ALIGNED(struct MMU_FMT_LEVEL *pFmt, 8);
/*!
* Level/Sublevel Formats flattened
*/
* Level/Sublevel Formats flattened
*/
NV_DECLARE_ALIGNED(MMU_FMT_LEVEL levelFmt, 8);
NV_DECLARE_ALIGNED(MMU_FMT_LEVEL sublevelFmt[MMU_FMT_MAX_SUB_LEVELS], 8);
/*!
* Physical address of this page level instance.
*/
* Physical address of this page level instance.
*/
NV_DECLARE_ALIGNED(NvU64 physAddress, 8);
/*!
* Aperture in which this page level instance resides.
*/
* Aperture in which this page level instance resides.
*/
NvU32 aperture;
/*!
* Size in bytes allocated for this level instance.
*/
* Size in bytes allocated for this level instance.
*/
NV_DECLARE_ALIGNED(NvU64 size, 8);
/*!
* Entry Index for this offset.
*/
NvU32 entryIndex;
} NV_CTRL_VASPACE_PAGE_LEVEL;
#define NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_PARAMS_MESSAGE_ID (0x2U)
@@ -135,6 +141,12 @@ typedef struct NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_PARAMS {
*/
NV_DECLARE_ALIGNED(NvU64 pageSize, 8);
/*!
* [in] Flags
* Contains flags to control various aspects of page level info.
*/
NV_DECLARE_ALIGNED(NvU64 flags, 8);
/*!
* [out] Number of levels populated.
*/
@@ -146,6 +158,11 @@ typedef struct NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_PARAMS {
NV_DECLARE_ALIGNED(NV_CTRL_VASPACE_PAGE_LEVEL levels[GMMU_FMT_MAX_LEVELS], 8);
} NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_PARAMS;
/* valid flags parameter values */
#define NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_FLAG_NONE 0x0ULL
#define NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_FLAG_BAR1 NVBIT64(0)
/*!
* Reserve (allocate and bind) page directory/table entries up to
* a given level of the MMU format. Also referred to as "lock-down".
@@ -155,7 +172,7 @@ typedef struct NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_PARAMS {
* A particular VA range and level (page size) combination may only be
* locked down once at a given time, but each level is independent.
*/
#define NV90F1_CTRL_CMD_VASPACE_RESERVE_ENTRIES (0x90f10103U) /* finn: Evaluated from "(FINN_FERMI_VASPACE_A_VASPACE_INTERFACE_ID << 8) | NV90F1_CTRL_VASPACE_RESERVE_ENTRIES_PARAMS_MESSAGE_ID" */
#define NV90F1_CTRL_CMD_VASPACE_RESERVE_ENTRIES (0x90f10103U) /* finn: Evaluated from "(FINN_FERMI_VASPACE_A_VASPACE_INTERFACE_ID << 8) | NV90F1_CTRL_VASPACE_RESERVE_ENTRIES_PARAMS_MESSAGE_ID" */
#define NV90F1_CTRL_VASPACE_RESERVE_ENTRIES_PARAMS_MESSAGE_ID (0x3U)
@@ -314,4 +331,77 @@ typedef struct NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS {
} levels[GMMU_FMT_MAX_LEVELS];
} NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS;
/*!
* Retrieve extra VA range that RM needs to reserve from the OS
*/
#define NV90F1_CTRL_CMD_VASPACE_GET_HOST_RM_MANAGED_SIZE (0x90f10107U) /* finn: Evaluated from "(FINN_FERMI_VASPACE_A_VASPACE_INTERFACE_ID << 8) | NV90F1_CTRL_VASPACE_GET_HOST_RM_MANAGED_SIZE_PARAMS_MESSAGE_ID" */
#define NV90F1_CTRL_VASPACE_GET_HOST_RM_MANAGED_SIZE_PARAMS_MESSAGE_ID (0x7U)
typedef struct NV90F1_CTRL_VASPACE_GET_HOST_RM_MANAGED_SIZE_PARAMS {
/*!
* [in] GPU sub-device handle - this API only supports unicast.
* Pass 0 to use subDeviceId instead.
*/
NvHandle hSubDevice;
/*!
* [in] GPU sub-device ID. Ignored if hSubDevice is non-zero.
*/
NvU32 subDeviceId;
/*!
* [out] The required VA range, in Megabytes
*/
NV_DECLARE_ALIGNED(NvU64 requiredVaRange, 8);
} NV90F1_CTRL_VASPACE_GET_HOST_RM_MANAGED_SIZE_PARAMS;
/*!
* Retrieve info on a VAS heap - used only for the MODS test RandomVATest
*/
#define NV90F1_CTRL_CMD_VASPACE_GET_VAS_HEAP_INFO (0x90f10108U) /* finn: Evaluated from "(FINN_FERMI_VASPACE_A_VASPACE_INTERFACE_ID << 8) | NV90F1_CTRL_VASPACE_GET_VAS_HEAP_INFO_PARAMS_MESSAGE_ID" */
#define NV90F1_CTRL_VASPACE_GET_VAS_HEAP_INFO_PARAMS_MESSAGE_ID (0x8U)
typedef struct NV90F1_CTRL_VASPACE_GET_VAS_HEAP_INFO_PARAMS {
/*!
* [in] GPU sub-device handle - this API only supports unicast.
* Pass 0 to use subDeviceId instead.
*/
NvHandle hSubDevice;
/*!
* [in] GPU sub-device ID. Ignored if hSubDevice is non-zero.
*/
NvU32 subDeviceId;
/*!
* [out] Number of free bytes in the heap
*/
NV_DECLARE_ALIGNED(NvU64 bytesFree, 8);
/*!
* [out] Number of bytes in the heap
*/
NV_DECLARE_ALIGNED(NvU64 bytesTotal, 8);
/*!
* [out] Offset of largest free block
*/
NV_DECLARE_ALIGNED(NvU64 largestFreeOffset, 8);
/*!
* [out] Size of the largest free block
*/
NV_DECLARE_ALIGNED(NvU64 largestFreeSize, 8);
/*!
* [out] Number of usable free bytes
*/
NV_DECLARE_ALIGNED(NvU64 usableBytesFree, 8);
/*!
* [out] Number of free blocks
*/
NvU32 numFreeBlocks;
} NV90F1_CTRL_VASPACE_GET_VAS_HEAP_INFO_PARAMS;
/* _ctrl90f1_h_ */