545.23.06

2026-02-06 08:09:58 +00:00 · 2023-10-17 09:25:29 -07:00
parent f59818b751
commit b5bf85a8e3
917 changed files with 132480 additions and 110015 deletions
--- a/src/nvidia/arch/nvalloc/common/inc/flcnretval.h
+++ b/src/nvidia/arch/nvalloc/common/inc/flcnretval.h
@@ -160,6 +160,7 @@ typedef NvU8 FLCN_STATUS;
 #define FLCN_ERR_FREQ_NOT_SUPPORTED                                        (0x73U)
 #define FLCN_ERR_INVALID_SOURCE                                            (0x74U)
 #define FLCN_ERR_NOT_INITIALIZED                                           (0x75U)
+#define FLCN_ERR_CLOCK_NOT_SETTLED                                         (0x76U)

 // HDCP2.2 Errors
 #define FLCN_ERR_HDCP22_GETDKEY_FAILED                                     (0x80U)
@@ -235,7 +236,8 @@ typedef NvU8 FLCN_STATUS;
 #define FLCN_ERR_HS_APM_SCRATCH_INIT_INVALID                               (0xD0U)
 #define FLCN_ERR_HS_INVALID_KEY                                            (0xD1U)
 #define FLCN_ERR_HS_SWKG_INVALID_SIGNATURE                                 (0xD2U)
-
+#define FLCN_ERR_HS_SCP_LIB_DMHASH_FAILED                                  (0xD3U)
+#define FLCN_ERR_HS_SCP_LIB_AESKDF_FAILED                                  (0xD4U)

 //
 // BAR0/CSB Priv Read/Write Error Handling Defines
--- a/src/nvidia/arch/nvalloc/common/inc/gsp/gsp_fw_sr_meta.h
+++ b/src/nvidia/arch/nvalloc/common/inc/gsp/gsp_fw_sr_meta.h
@@ -75,11 +75,14 @@ typedef struct
    // Hash over data in WPR2 (skipping over free heap chunks; see Booter for details)
    NvU8 dataHash[32];

+    // Same as flags of GspFwWprMeta
+    NvU32 flags;
+
    //
    // Pad structure to exactly 256 bytes (1 DMA chunk).
    // Padding initialized to zero.
    //
-    NvU32 padding[24];
+    NvU32 padding[23];

 } GspFwSRMeta;

--- a/src/nvidia/arch/nvalloc/common/inc/gsp/gsp_fw_wpr_meta.h
+++ b/src/nvidia/arch/nvalloc/common/inc/gsp/gsp_fw_wpr_meta.h
@@ -187,9 +187,12 @@ typedef struct
    // Used during boot to ensure the heap is adequately sized
    NvU8 gspFwHeapVfPartitionCount;

+    // Flags to help decide GSP-FW flow.
+    NvU8 flags;
+
    // Pad structure to exactly 256 bytes.  Can replace padding with additional
    // fields without incrementing revision.  Padding initialized to 0.
-    NvU8 padding[7];
+    NvU8 padding[6];

    // BL to use for verification (i.e. Booter says OK to boot)
    NvU64 verified;  // 0x0 -> unverified, 0xa0a0a0a0a0a0a0a0 -> verified
@@ -220,4 +223,7 @@ typedef struct

 #define GSP_FW_HEAP_FREE_LIST_MAGIC 0x4845415046524545ULL

+#define GSP_FW_FLAGS                    8:0
+#define GSP_FW_FLAGS_CLOCK_BOOST        NVBIT(0)
+
 #endif // GSP_FW_WPR_META_H_
--- a/src/nvidia/arch/nvalloc/common/inc/inforom/ifrecc.h
+++ b/src/nvidia/arch/nvalloc/common/inc/inforom/ifrecc.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: Copyright (c) 2017-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-FileCopyrightText: Copyright (c) 2017-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
 * SPDX-License-Identifier: MIT
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
--- a/src/nvidia/arch/nvalloc/common/inc/inforom/ifrstruct.h
+++ b/src/nvidia/arch/nvalloc/common/inc/inforom/ifrstruct.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: Copyright (c) 1999-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-FileCopyrightText: Copyright (c) 1999-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
 * SPDX-License-Identifier: MIT
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
--- a/src/nvidia/arch/nvalloc/common/inc/oob/smbpbi.h
+++ b/src/nvidia/arch/nvalloc/common/inc/oob/smbpbi.h
@@ -135,8 +135,10 @@
 #define NV_MSGBOX_CMD_ARG1_PCIE_SPEED_V1                        0x00000012
 #define NV_MSGBOX_CMD_ARG1_PCIE_WIDTH_V1                        0x00000013
 #define NV_MSGBOX_CMD_ARG1_TGP_LIMIT_V1                         0x00000014
+#define NV_MSGBOX_CMD_ARG1_FRU_PART_NUMBER_V1                   0x00000015
 #define NV_MSGBOX_CMD_ARG1_MODULE_POWER_LIMIT_V1                0x00000016
-#define NV_MSGBOX_CMD_ARG1_SYS_ID_DATA_TYPE_MAX                 0x00000016    /* Adjust, when adding new types */
+#define NV_MSGBOX_CMD_ARG1_MAX_DRAM_CAPACITY_V1                 0x00000017
+#define NV_MSGBOX_CMD_ARG1_SYS_ID_DATA_TYPE_MAX                 0x00000017    /* Adjust, when adding new types */
 #define NV_MSGBOX_CMD_ARG1_REGISTER_ACCESS_WRITE                0x00000000
 #define NV_MSGBOX_CMD_ARG1_REGISTER_ACCESS_READ                 0x00000001
 #define NV_MSGBOX_CMD_ARG1_THERM_PARAM_TEMP_TARGET              0x00000000
@@ -772,9 +774,9 @@
 #define NV_MSGBOX_DATA_CAP_1_INFOROM_VER_V1                              14:14
 #define NV_MSGBOX_DATA_CAP_1_INFOROM_VER_V1_NOT_AVAILABLE           0x00000000
 #define NV_MSGBOX_DATA_CAP_1_INFOROM_VER_V1_AVAILABLE               0x00000001
-#define NV_MSGBOX_DATA_CAP_1_MODULE_LIMIT_V1                             15:15
-#define NV_MSGBOX_DATA_CAP_1_MODULE_LIMIT_V1_NOT_AVAILABLE          0x00000000
-#define NV_MSGBOX_DATA_CAP_1_MODULE_LIMIT_V1_AVAILABLE              0x00000001
+#define NV_MSGBOX_DATA_CAP_1_MODULE_POWER_LIMIT_V1                       15:15
+#define NV_MSGBOX_DATA_CAP_1_MODULE_POWER_LIMIT_V1_NOT_AVAILABLE    0x00000000
+#define NV_MSGBOX_DATA_CAP_1_MODULE_POWER_LIMIT_V1_AVAILABLE        0x00000001
 #define NV_MSGBOX_DATA_CAP_1_ECC_V1                                      16:16
 #define NV_MSGBOX_DATA_CAP_1_ECC_V1_NOT_AVAILABLE                   0x00000000
 #define NV_MSGBOX_DATA_CAP_1_ECC_V1_AVAILABLE                       0x00000001
@@ -902,6 +904,9 @@
 #define NV_MSGBOX_DATA_CAP_2_NVLINK_INFO_AVAILABILITY                       27:27
 #define NV_MSGBOX_DATA_CAP_2_NVLINK_INFO_AVAILABILITY_NOT_AVAILABLE    0x00000000
 #define NV_MSGBOX_DATA_CAP_2_NVLINK_INFO_AVAILABILITY_AVAILABLE        0x00000001
+#define NV_MSGBOX_DATA_CAP_2_FRU_PART_NUMBER_V1                             31:31
+#define NV_MSGBOX_DATA_CAP_2_FRU_PART_NUMBER_V1_NOT_AVAILABLE          0x00000000
+#define NV_MSGBOX_DATA_CAP_2_FRU_PART_NUMBER_V1_AVAILABLE              0x00000001

 #define NV_MSGBOX_DATA_CAP_4                                                     4
 #define NV_MSGBOX_DATA_CAP_4_HW_VIOLATION_TIME                                 0:0
@@ -946,9 +951,15 @@
 #define NV_MSGBOX_DATA_CAP_4_GPU_PERFORMANCE_MONITORING                                  24:24
 #define NV_MSGBOX_DATA_CAP_4_GPU_PERFORMANCE_MONITORING_NOT_AVAILABLE               0x00000000
 #define NV_MSGBOX_DATA_CAP_4_GPU_PERFORMANCE_MONITORING_AVAILABLE                   0x00000001
+#define NV_MSGBOX_DATA_CAP_4_DEM_BY_SEQNUM_TIMESTAMP                                     26:26
+#define NV_MSGBOX_DATA_CAP_4_DEM_BY_SEQNUM_TIMESTAMP_NOT_AVAILABLE                  0x00000000
+#define NV_MSGBOX_DATA_CAP_4_DEM_BY_SEQNUM_TIMESTAMP_AVAILABLE                      0x00000001
 #define NV_MSGBOX_DATA_CAP_4_CONFIGURE_PROGRAMMABLE_EDPP                                 30:30
 #define NV_MSGBOX_DATA_CAP_4_CONFIGURE_PROGRAMMABLE_EDPP_NOT_AVAILABLE              0x00000000
 #define NV_MSGBOX_DATA_CAP_4_CONFIGURE_PROGRAMMABLE_EDPP_AVAILABLE                  0x00000001
+#define NV_MSGBOX_DATA_CAP_4_MAX_DRAM_CAPACITY_V1                                        31:31
+#define NV_MSGBOX_DATA_CAP_4_MAX_DRAM_CAPACITY_V1_NOT_AVAILABLE                     0x00000000
+#define NV_MSGBOX_DATA_CAP_4_MAX_DRAM_CAPACITY_V1_AVAILABLE                         0x00000001

 /* ECC counters */
 #define NV_MSGBOX_DATA_ECC_CNT_16BIT_DBE                             31:16
@@ -1393,6 +1404,10 @@
 #define NV_MSGBOX_SYSID_DATA_SIZE_PRODUCT_HEIGHT_V1              4
 #define NV_MSGBOX_SYSID_DATA_SIZE_PCIE_SPEED_V1                  1
 #define NV_MSGBOX_SYSID_DATA_SIZE_PCIE_WIDTH_V1                  1
+#define NV_MSGBOX_SYSID_DATA_SIZE_TGP_LIMIT_V1                   4
+#define NV_MSGBOX_SYSID_DATA_SIZE_FRU_PART_NUMBER_V1            20
+#define NV_MSGBOX_SYSID_DATA_SIZE_MODULE_POWER_LIMIT_V1          4
+#define NV_MSGBOX_SYSID_DATA_SIZE_MAX_DRAM_CAPACITY_V1           4

 /*!
 * Response to NV_MSGBOX_CMD_ARG1_GET_POWER_HINT_INFO_CLK
--- a/src/nvidia/arch/nvalloc/unix/include/nv-chardev-numbers.h
+++ b/src/nvidia/arch/nvalloc/unix/include/nv-chardev-numbers.h
@@ -0,0 +1,43 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+
+#ifndef _NV_CHARDEV_NUMBERS_H_
+#define _NV_CHARDEV_NUMBERS_H_
+
+// NVIDIA's reserved major character device number (Linux).
+#define NV_MAJOR_DEVICE_NUMBER  195
+
+// Minor numbers 0 to 247 reserved for regular devices
+#define NV_MINOR_DEVICE_NUMBER_REGULAR_MAX         247
+
+// Minor numbers 248 to 253 currently unused
+
+// Minor number 254 reserved for the modeset device (provided by NVKMS)
+#define NV_MINOR_DEVICE_NUMBER_MODESET_DEVICE      254
+
+// Minor number 255 reserved for the control device
+#define NV_MINOR_DEVICE_NUMBER_CONTROL_DEVICE      255
+
+#endif  // _NV_CHARDEV_NUMBERS_H_
+
--- a/src/nvidia/arch/nvalloc/unix/include/nv-ioctl-lockless-diag.h
+++ b/src/nvidia/arch/nvalloc/unix/include/nv-ioctl-lockless-diag.h
@@ -21,15 +21,15 @@
 * DEALINGS IN THE SOFTWARE.
 */

-#if !defined(NV_IOCTL_NVLOG)
-#define NV_IOCTL_NVLOG
+#if !defined(NV_IOCTL_LOCKLESS_DIAG)
+#define NV_IOCTL_LOCKLESS_DIAG

 #include <nvtypes.h>
 #include "ctrl/ctrl0000/ctrl0000nvd.h"

 typedef struct
 {
-    NvU32 ctrl; // in
+    NvU32 cmd; // in
    NvU32 status; // out
    union // in/out
    {
@@ -37,7 +37,7 @@ typedef struct
        NV0000_CTRL_NVD_GET_NVLOG_BUFFER_INFO_PARAMS getNvlogBufferInfo;
        NV0000_CTRL_NVD_GET_NVLOG_PARAMS getNvlog;
    } params;
-} NV_NVLOG_CTRL_PARAMS;
+} NV_LOCKLESS_DIAGNOSTIC_PARAMS;

 #endif

--- a/src/nvidia/arch/nvalloc/unix/include/nv-ioctl-numa.h
+++ b/src/nvidia/arch/nvalloc/unix/include/nv-ioctl-numa.h
@@ -0,0 +1,81 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+
+#ifndef NV_IOCTL_NUMA_H
+#define NV_IOCTL_NUMA_H
+
+#include <nv-ioctl-numbers.h>
+
+#if defined(NV_KERNEL_INTERFACE_LAYER) && defined(NV_LINUX)
+#include <linux/types.h>
+#elif defined (NV_KERNEL_INTERFACE_LAYER) && defined(NV_BSD)
+#include <sys/stdint.h>
+#else
+
+#include <stdint.h>
+
+#if !defined(__aligned)
+#define __aligned(n) __attribute__((aligned(n)))
+#endif
+
+#endif
+
+#define NV_ESC_NUMA_INFO         (NV_IOCTL_BASE + 15)
+#define NV_ESC_SET_NUMA_STATUS   (NV_IOCTL_BASE + 16)
+
+#define NV_IOCTL_NUMA_INFO_MAX_OFFLINE_ADDRESSES 64
+typedef struct offline_addresses
+{
+    uint64_t addresses[NV_IOCTL_NUMA_INFO_MAX_OFFLINE_ADDRESSES] __aligned(8);
+    uint32_t numEntries;
+} nv_offline_addresses_t;
+
+
+/* per-device NUMA memory info as assigned by the system */
+typedef struct nv_ioctl_numa_info
+{
+    int32_t  nid;
+    int32_t  status;
+    uint64_t memblock_size __aligned(8);
+    uint64_t numa_mem_addr __aligned(8);
+    uint64_t numa_mem_size __aligned(8);
+    uint8_t  use_auto_online;
+    nv_offline_addresses_t offline_addresses __aligned(8);
+} nv_ioctl_numa_info_t;
+
+/* set the status of the device NUMA memory */
+typedef struct nv_ioctl_set_numa_status
+{
+    int32_t status;
+} nv_ioctl_set_numa_status_t;
+
+#define NV_IOCTL_NUMA_STATUS_DISABLED               0
+#define NV_IOCTL_NUMA_STATUS_OFFLINE                1
+#define NV_IOCTL_NUMA_STATUS_ONLINE_IN_PROGRESS     2
+#define NV_IOCTL_NUMA_STATUS_ONLINE                 3
+#define NV_IOCTL_NUMA_STATUS_ONLINE_FAILED          4
+#define NV_IOCTL_NUMA_STATUS_OFFLINE_IN_PROGRESS    5
+#define NV_IOCTL_NUMA_STATUS_OFFLINE_FAILED         6
+
+#endif
--- a/src/nvidia/arch/nvalloc/unix/include/nv-priv.h
+++ b/src/nvidia/arch/nvalloc/unix/include/nv-priv.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: Copyright (c) 1999-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-FileCopyrightText: Copyright (c) 1999-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
 * SPDX-License-Identifier: MIT
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
@@ -77,28 +77,6 @@ typedef struct nv_work_item_s
 #define NV_WORK_ITEM_FLAGS_REQUIRES_GPU     0x1
 #define NV_WORK_ITEM_FLAGS_DONT_FREE_DATA   0x2

-/*
- * pseudo-registry data structure
- */
-
-typedef enum
-{
-    NV_REGISTRY_ENTRY_TYPE_UNKNOWN = 0,
-    NV_REGISTRY_ENTRY_TYPE_DWORD,
-    NV_REGISTRY_ENTRY_TYPE_BINARY,
-    NV_REGISTRY_ENTRY_TYPE_STRING
-} nv_reg_type_t;
-
-typedef struct nv_reg_entry_s
-{
-    char *regParmStr;
-    NvU32 type;
-    NvU32 data;   // used when type == NV_REGISTRY_ENTRY_TYPE_DWORD
-    NvU8 *pdata;  // used when type == NV_REGISTRY_ENTRY_TYPE_{BINARY,STRING}
-    NvU32 len;    // used when type == NV_REGISTRY_ENTRY_TYPE_{BINARY,STRING}
-    struct nv_reg_entry_s *next;
-} nv_reg_entry_t;
-
 #define INVALID_DISP_ID 0xFFFFFFFF
 #define MAX_DISP_ID_PER_ADAPTER 0x2

--- a/src/nvidia/arch/nvalloc/unix/include/nv-reg.h
+++ b/src/nvidia/arch/nvalloc/unix/include/nv-reg.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: Copyright (c) 2006-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-FileCopyrightText: Copyright (c) 2006-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
 * SPDX-License-Identifier: MIT
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
@@ -771,16 +771,11 @@
 /*
 * Option: OpenRmEnableUnsupportedGpus
 *
- * Open nvidia.ko support for features beyond what is used on Data Center GPUs
- * is still fairly immature, so for now require users to opt into use of open
- * nvidia.ko with a special registry key, if not on a Data Center GPU.
+ * This option to require opt in for use of Open RM on non-Data Center
+ * GPUs is deprecated and no longer required. The kernel module parameter
+ * is left here, though ignored, for backwards compatibility.
 */
-
 #define __NV_OPENRM_ENABLE_UNSUPPORTED_GPUS OpenRmEnableUnsupportedGpus
-#define NV_REG_OPENRM_ENABLE_UNSUPPORTED_GPUS NV_REG_STRING(__NV_OPENRM_ENABLE_UNSUPPORTED_GPUS)
-#define NV_REG_OPENRM_ENABLE_UNSUPPORTED_GPUS_DISABLE 0x00000000
-#define NV_REG_OPENRM_ENABLE_UNSUPPORTED_GPUS_ENABLE  0x00000001
-#define NV_REG_OPENRM_ENABLE_UNSUPPORTED_GPUS_DEFAULT NV_REG_OPENRM_ENABLE_UNSUPPORTED_GPUS_DISABLE

 /*
 * Option: NVreg_DmaRemapPeerMmio
@@ -853,7 +848,7 @@ NV_DEFINE_REG_ENTRY(__NV_DYNAMIC_POWER_MANAGEMENT, 3);
 NV_DEFINE_REG_ENTRY(__NV_DYNAMIC_POWER_MANAGEMENT_VIDEO_MEMORY_THRESHOLD, 200);
 NV_DEFINE_REG_ENTRY(__NV_ENABLE_GPU_FIRMWARE, NV_REG_ENABLE_GPU_FIRMWARE_DEFAULT_VALUE);
 NV_DEFINE_REG_ENTRY(__NV_ENABLE_GPU_FIRMWARE_LOGS, NV_REG_ENABLE_GPU_FIRMWARE_LOGS_ENABLE_ON_DEBUG);
-NV_DEFINE_REG_ENTRY(__NV_OPENRM_ENABLE_UNSUPPORTED_GPUS, NV_REG_OPENRM_ENABLE_UNSUPPORTED_GPUS_DEFAULT);
+NV_DEFINE_REG_ENTRY(__NV_OPENRM_ENABLE_UNSUPPORTED_GPUS, 1);

 NV_DEFINE_REG_ENTRY_GLOBAL(__NV_ENABLE_USER_NUMA_MANAGEMENT, 1);
 NV_DEFINE_REG_ENTRY_GLOBAL(__NV_MEMORY_POOL_SIZE, 0);
--- a/src/nvidia/arch/nvalloc/unix/include/nv.h
+++ b/src/nvidia/arch/nvalloc/unix/include/nv.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: Copyright (c) 1999-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-FileCopyrightText: Copyright (c) 1999-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
 * SPDX-License-Identifier: MIT
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
@@ -42,6 +42,7 @@
 #include <nv-caps.h>
 #include <nv-firmware.h>
 #include <nv-ioctl.h>
+#include <nv-ioctl-numa.h>
 #include <nvmisc.h>

 extern nv_cap_t *nvidia_caps_root;
@@ -50,9 +51,6 @@ extern const NvBool nv_is_rm_firmware_supported_os;

 #include <nv-kernel-interface-api.h>

-/* NVIDIA's reserved major character device number (Linux). */
-#define NV_MAJOR_DEVICE_NUMBER 195
-
 #define GPU_UUID_LEN    (16)

 /*
@@ -478,8 +476,6 @@ typedef struct nv_state_t
    /* Bool to check if dma-buf is supported */
    NvBool dma_buf_supported;

-    NvBool printed_openrm_enable_unsupported_gpus_error;
-
    /* Check if NVPCF DSM function is implemented under NVPCF or GPU device scope */
    NvBool nvpcf_dsm_in_gpu_scope;

@@ -505,6 +501,7 @@ struct nv_file_private_t
    NvHandle *handles;
    NvU16 maxHandles;
    NvU32 deviceInstance;
+    NvU32 gpuInstanceId;
    NvU8 metadata[64];

    nv_file_private_t *ctl_nvfp;
@@ -765,7 +762,7 @@ nv_state_t*  NV_API_CALL  nv_get_ctl_state       (void);
 void   NV_API_CALL  nv_set_dma_address_size      (nv_state_t *, NvU32 );

 NV_STATUS  NV_API_CALL  nv_alias_pages           (nv_state_t *, NvU32, NvU32, NvU32, NvU64, NvU64 *, void **);
-NV_STATUS  NV_API_CALL  nv_alloc_pages           (nv_state_t *, NvU32, NvBool, NvU32, NvBool, NvBool, NvS32, NvU64 *, void **);
+NV_STATUS  NV_API_CALL  nv_alloc_pages           (nv_state_t *, NvU32, NvU64, NvBool, NvU32, NvBool, NvBool, NvS32, NvU64 *, void **);
 NV_STATUS  NV_API_CALL  nv_free_pages            (nv_state_t *, NvU32, NvBool, NvU32, void *);

 NV_STATUS  NV_API_CALL  nv_register_user_pages   (nv_state_t *, NvU64, NvU64 *, void *, void **);
@@ -981,7 +978,7 @@ NV_STATUS  NV_API_CALL  rm_dma_buf_dup_mem_handle (nvidia_stack_t *, nv_state_t
 void       NV_API_CALL  rm_dma_buf_undup_mem_handle(nvidia_stack_t *, nv_state_t *, NvHandle, NvHandle);
 NV_STATUS  NV_API_CALL  rm_dma_buf_map_mem_handle (nvidia_stack_t *, nv_state_t *, NvHandle, NvHandle, NvU64, NvU64, void *, nv_phys_addr_range_t **, NvU32 *);
 void       NV_API_CALL  rm_dma_buf_unmap_mem_handle(nvidia_stack_t *, nv_state_t *, NvHandle, NvHandle, NvU64, nv_phys_addr_range_t **, NvU32);
-NV_STATUS  NV_API_CALL  rm_dma_buf_get_client_and_device(nvidia_stack_t *, nv_state_t *, NvHandle, NvHandle *, NvHandle *, NvHandle *, void **, NvBool *);
+NV_STATUS  NV_API_CALL  rm_dma_buf_get_client_and_device(nvidia_stack_t *, nv_state_t *, NvHandle, NvHandle, NvHandle *, NvHandle *, NvHandle *, void **, NvBool *);
 void       NV_API_CALL  rm_dma_buf_put_client_and_device(nvidia_stack_t *, nv_state_t *, NvHandle, NvHandle, NvHandle, void *);
 NV_STATUS  NV_API_CALL  rm_log_gpu_crash          (nv_stack_t *, nv_state_t *);

@@ -993,7 +990,7 @@ NvBool     NV_API_CALL rm_gpu_need_4k_page_isolation(nv_state_t *);
 NvBool     NV_API_CALL rm_is_chipset_io_coherent(nv_stack_t *);
 NvBool     NV_API_CALL rm_init_event_locks(nvidia_stack_t *, nv_state_t *);
 void       NV_API_CALL rm_destroy_event_locks(nvidia_stack_t *, nv_state_t *);
-NV_STATUS  NV_API_CALL rm_get_gpu_numa_info(nvidia_stack_t *, nv_state_t *, NvS32 *, NvU64 *, NvU64 *, NvU64 *, NvU32 *);
+NV_STATUS  NV_API_CALL rm_get_gpu_numa_info(nvidia_stack_t *, nv_state_t *, nv_ioctl_numa_info_t *);
 NV_STATUS  NV_API_CALL rm_gpu_numa_online(nvidia_stack_t *, nv_state_t *);
 NV_STATUS  NV_API_CALL rm_gpu_numa_offline(nvidia_stack_t *, nv_state_t *);
 NvBool     NV_API_CALL rm_is_device_sequestered(nvidia_stack_t *, nv_state_t *);
@@ -1008,7 +1005,7 @@ void       NV_API_CALL rm_cleanup_dynamic_power_management(nvidia_stack_t *, nv_
 void       NV_API_CALL rm_enable_dynamic_power_management(nvidia_stack_t *, nv_state_t *);
 NV_STATUS  NV_API_CALL rm_ref_dynamic_power(nvidia_stack_t *, nv_state_t *, nv_dynamic_power_mode_t);
 void       NV_API_CALL rm_unref_dynamic_power(nvidia_stack_t *, nv_state_t *, nv_dynamic_power_mode_t);
-NV_STATUS  NV_API_CALL rm_transition_dynamic_power(nvidia_stack_t *, nv_state_t *, NvBool);
+NV_STATUS  NV_API_CALL rm_transition_dynamic_power(nvidia_stack_t *, nv_state_t *, NvBool, NvBool *);
 const char* NV_API_CALL rm_get_vidmem_power_status(nvidia_stack_t *, nv_state_t *);
 const char* NV_API_CALL rm_get_dynamic_power_management_status(nvidia_stack_t *, nv_state_t *);
 const char* NV_API_CALL rm_get_gpu_gcx_support(nvidia_stack_t *, nv_state_t *, NvBool);
@@ -1023,7 +1020,8 @@ NV_STATUS  NV_API_CALL  nv_vgpu_create_request(nvidia_stack_t *, nv_state_t *, c
 NV_STATUS  NV_API_CALL  nv_vgpu_delete(nvidia_stack_t *, const NvU8 *, NvU16);
 NV_STATUS  NV_API_CALL  nv_vgpu_get_type_ids(nvidia_stack_t *, nv_state_t *, NvU32 *, NvU32 *, NvBool, NvU8, NvBool);
 NV_STATUS  NV_API_CALL  nv_vgpu_get_type_info(nvidia_stack_t *, nv_state_t *, NvU32, char *, int, NvU8);
-NV_STATUS  NV_API_CALL  nv_vgpu_get_bar_info(nvidia_stack_t *, nv_state_t *, const NvU8 *, NvU64 *, NvU32, void *);
+NV_STATUS  NV_API_CALL  nv_vgpu_get_bar_info(nvidia_stack_t *, nv_state_t *, const NvU8 *, NvU64 *, NvU32, void *, NvBool *);
+NV_STATUS  NV_API_CALL  nv_vgpu_get_hbm_info(nvidia_stack_t *, nv_state_t *, const NvU8 *, NvU64 *, NvU64 *);
 NV_STATUS  NV_API_CALL  nv_vgpu_start(nvidia_stack_t *, const NvU8 *, void *, NvS32 *, NvU8 *, NvU32);
 NV_STATUS  NV_API_CALL  nv_vgpu_get_sparse_mmap(nvidia_stack_t *, nv_state_t *, const NvU8 *, NvU64 **, NvU64 **, NvU32 *);
 NV_STATUS  NV_API_CALL  nv_vgpu_process_vf_info(nvidia_stack_t *, nv_state_t *, NvU8, NvU32, NvU8, NvU8, NvU8, NvBool, void *);
--- a/src/nvidia/arch/nvalloc/unix/include/nv_escape.h
+++ b/src/nvidia/arch/nvalloc/unix/include/nv_escape.h
@@ -50,6 +50,6 @@
 #define NV_ESC_RM_EXPORT_OBJECT_TO_FD               0x5C
 #define NV_ESC_RM_IMPORT_OBJECT_FROM_FD             0x5D
 #define NV_ESC_RM_UPDATE_DEVICE_MAPPING_INFO        0x5E
-#define NV_ESC_RM_NVLOG_CTRL                        0x5F
+#define NV_ESC_RM_LOCKLESS_DIAGNOSTIC               0x5F

 #endif // NV_ESCAPE_H_INCLUDED
--- a/src/nvidia/arch/nvalloc/unix/include/os-interface.h
+++ b/src/nvidia/arch/nvalloc/unix/include/os-interface.h
@@ -162,7 +162,7 @@ NvBool      NV_API_CALL  os_is_vgx_hyper             (void);
 NV_STATUS   NV_API_CALL  os_inject_vgx_msi           (NvU16, NvU64, NvU32);
 NvBool      NV_API_CALL  os_is_grid_supported        (void);
 NvU32       NV_API_CALL  os_get_grid_csp_support     (void);
-void        NV_API_CALL  os_get_screen_info          (NvU64 *, NvU16 *, NvU16 *, NvU16 *, NvU16 *, NvU64, NvU64);
+void        NV_API_CALL  os_get_screen_info          (NvU64 *, NvU32 *, NvU32 *, NvU32 *, NvU32 *, NvU64, NvU64);
 void        NV_API_CALL  os_bug_check                (NvU32, const char *);
 NV_STATUS   NV_API_CALL  os_lock_user_pages          (void *, NvU64, void **, NvU32);
 NV_STATUS   NV_API_CALL  os_lookup_user_io_memory    (void *, NvU64, NvU64 **, void**);
@@ -230,12 +230,14 @@ extern NvBool os_dma_buf_enabled;
 * ---------------------------------------------------------------------------
 */

-#define NV_DBG_INFO       0x0
-#define NV_DBG_SETUP      0x1
-#define NV_DBG_USERERRORS 0x2
+#define NV_DBG_INFO       0x1
+#define NV_DBG_SETUP      0x2
 #define NV_DBG_WARNINGS   0x3
 #define NV_DBG_ERRORS     0x4
+#define NV_DBG_HW_ERRORS  0x5
+#define NV_DBG_FATAL      0x6

+#define NV_DBG_FORCE_LEVEL(level) ((level) | (1 << 8))

 void NV_API_CALL  out_string(const char *str);
 int  NV_API_CALL  nv_printf(NvU32 debuglevel, const char *printf_format, ...);
--- a/src/nvidia/arch/nvalloc/unix/include/osfuncs.h
+++ b/src/nvidia/arch/nvalloc/unix/include/osfuncs.h
@@ -32,13 +32,6 @@

 #include <os/os.h>

-OSQueueWorkItem                 osQueueWorkItem;
-OSQueueWorkItemWithFlags        osQueueWorkItemWithFlags;
-OSQueueSystemWorkItem           osQueueSystemWorkItem;
-OSDbgBreakpointEnabled          osDbgBreakpointEnabled;
-
-void*                           osGetStereoDongleInterface(void);
-
 #if defined(NVCPU_X86_64)
 OSnv_rdcr4                      nv_rdcr4;
 NvU64                           nv_rdcr3(OBJOS *);
--- a/src/nvidia/arch/nvalloc/unix/include/rmobjexportimport.h
+++ b/src/nvidia/arch/nvalloc/unix/include/rmobjexportimport.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: Copyright (c) 2016 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-FileCopyrightText: Copyright (c) 2016-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
 * SPDX-License-Identifier: MIT
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
@@ -36,7 +36,5 @@ void RmFreeObjExportHandle(RmObjExportHandle hObject);
 NV_STATUS RmImportObject(NvHandle hDstClient, NvHandle hDstParent,
                         NvHandle *phDstObject, RmObjExportHandle hSrcObject,
                         NvU8 *pObjectType);
-
-NV_STATUS RmGetExportObjectInfo(RmObjExportHandle hSrcObject, NvU32 *deviceInstance);
 #endif // _RMOBJEXPORTIMPORT_H_

--- a/src/nvidia/arch/nvalloc/unix/src/dynamic-power.c
+++ b/src/nvidia/arch/nvalloc/unix/src/dynamic-power.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: Copyright (c) 2019-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-FileCopyrightText: Copyright (c) 2019-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
 * SPDX-License-Identifier: MIT
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
@@ -128,7 +128,7 @@
 static void RmScheduleCallbackForIdlePreConditions(OBJGPU *);
 static void RmScheduleCallbackForIdlePreConditionsUnderGpuLock(OBJGPU *);
 static void RmScheduleCallbackToIndicateIdle(OBJGPU *);
-static NvBool RmCheckForGc6SupportOnCurrentState(OBJGPU *);
+static NvBool RmCheckForGcxSupportOnCurrentState(OBJGPU *);
 static void RmScheduleCallbackToRemoveIdleHoldoff(OBJGPU *);
 static void RmQueueIdleSustainedWorkitem(OBJGPU *);

@@ -246,18 +246,36 @@ NvBool nv_dynamic_power_state_transition(
 *
 * @return      TRUE if the GPU appears to be currently idle; FALSE otherwise.
 */
-static NvBool RmCheckForGpuIdlenessUnderGpuLock(
+static NvBool RmCanEnterGcxUnderGpuLock(
    OBJGPU *pGpu
 )
 {
    NV_ASSERT(rmDeviceGpuLockIsOwner(pGpu->gpuInstance));

+    /*
+     * If GPU does not support GC6 and the actual FB utilization is higher than the threshold,
+     * then the GPU can neither enter GC6 nor GCOFF. So, return from here.
+     */
+    if (!pGpu->getProperty(pGpu, PDB_PROP_GPU_RTD3_GC6_SUPPORTED))
+    {
+        NvU64          usedFbSize     = 0;
+        nv_state_t    *nv             = NV_GET_NV_STATE(pGpu);
+        nv_priv_t     *nvp            = NV_GET_NV_PRIV(nv);
+        MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu);
+
+        if (!((memmgrGetUsedRamSize(pGpu, pMemoryManager, &usedFbSize) == NV_OK) &&
+            (usedFbSize <= nvp->dynamic_power.gcoff_max_fb_size)))
+        {
+            return NV_FALSE;
+        }
+    }
+
    // Check the instantaneous engine level idleness.
-    return RmCheckForGc6SupportOnCurrentState(pGpu);
+    return RmCheckForGcxSupportOnCurrentState(pGpu);
 }

 /*!
- * @brief: Check if the GPU hardware appears to be idle.
+ * @brief: Check the feasibility of GPU engaging in a GCx cycle.
 *
 * Takes the GPU lock.
 *
@@ -265,7 +283,7 @@ static NvBool RmCheckForGpuIdlenessUnderGpuLock(
 *
 * @return      TRUE if the GPU appears to be currently idle; FALSE otherwise.
 */
-static NvBool RmCheckForGpuIdleness(
+static NvBool RmCanEnterGcx(
    OBJGPU *pGpu
 )
 {
@@ -279,7 +297,7 @@ static NvBool RmCheckForGpuIdleness(
                                   &gpuMask);
    if (status == NV_OK)
    {
-        result = RmCheckForGpuIdlenessUnderGpuLock(pGpu);
+        result = RmCanEnterGcxUnderGpuLock(pGpu);
        // UNLOCK: release per device lock
        rmGpuGroupLockRelease(gpuMask, GPUS_LOCK_FLAGS_NONE);
    }
@@ -365,7 +383,7 @@ static void RmIndicateIdle(

    if (nv_get_all_mappings_revoked_locked(nv) &&
        nvp->dynamic_power.state == NV_DYNAMIC_POWER_STATE_IDLE_SUSTAINED &&
-        RmCheckForGpuIdleness(pGpu))
+        RmCanEnterGcx(pGpu))
    {
        nv_set_safe_to_mmap_locked(nv, NV_FALSE);
        nv_dynamic_power_state_transition(nv, NV_DYNAMIC_POWER_STATE_IDLE_SUSTAINED,
@@ -400,11 +418,10 @@ NV_STATUS NV_API_CALL rm_schedule_gpu_wakeup(
    void *fp;
    NV_STATUS ret;
    OBJGPU *pGpu = NV_GET_NV_PRIV_PGPU(nv);
-    OBJOS *pOS = GPU_GET_OS(pGpu);

    NV_ENTER_RM_RUNTIME(sp, fp);

-    ret = pOS->osQueueWorkItem(pGpu, RmForceGpuNotIdle, NULL);
+    ret = osQueueWorkItem(pGpu, RmForceGpuNotIdle, NULL);

    NV_EXIT_RM_RUNTIME(sp, fp);

@@ -1293,36 +1310,36 @@ void osUnrefGpuAccessNeeded(
 }

 /*!
- * @brief Check if GC6 is supported on current pstate and if engines are idle.
+ * @brief Check if GCx is supported on current pstate and if engines are idle.
 *
 * @param[in]   pGpu    OBJGPU pointer.
 */
-static NvBool RmCheckForGc6SupportOnCurrentState(
+static NvBool RmCheckForGcxSupportOnCurrentState(
    OBJGPU *pGpu
 )
 {
    NV_STATUS   status = NV_OK;
    nv_state_t *nv     = NV_GET_NV_STATE(pGpu);
    RM_API     *pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL);
-    NV2080_CTRL_INTERNAL_GC6_ENTRY_PREREQUISITE_PARAMS entryPrerequisiteParams;
+    NV2080_CTRL_INTERNAL_GCX_ENTRY_PREREQUISITE_PARAMS entryPrerequisiteParams;

    portMemSet(&entryPrerequisiteParams, 0, sizeof(entryPrerequisiteParams));

    status = pRmApi->Control(pRmApi,
                             nv->rmapi.hClient,
                             nv->rmapi.hSubDevice,
-                             NV2080_CTRL_CMD_INTERNAL_GC6_ENTRY_PREREQUISITE,
+                             NV2080_CTRL_CMD_INTERNAL_GCX_ENTRY_PREREQUISITE,
                             (void*)&entryPrerequisiteParams,
                             sizeof(entryPrerequisiteParams));

    if (status != NV_OK)
    {
-        NV_PRINTF(LEVEL_ERROR, "NVRM, Failed to get GC6 pre-requisite, status=0x%x\n",
+        NV_PRINTF(LEVEL_ERROR, "NVRM, Failed to get GCx pre-requisite, status=0x%x\n",
                  status);
        return NV_FALSE;
    }

-    return entryPrerequisiteParams.bIsSatisfied;
+    return entryPrerequisiteParams.bIsGC6Satisfied || entryPrerequisiteParams.bIsGCOFFSatisfied;
 }

 /*!
@@ -1348,7 +1365,7 @@ static void RmRemoveIdleHoldoff(

    if (nvp->dynamic_power.b_idle_holdoff == NV_TRUE)
    {
-        if ((RmCheckForGc6SupportOnCurrentState(pGpu) == NV_TRUE) ||
+        if ((RmCheckForGcxSupportOnCurrentState(pGpu) == NV_TRUE) ||
            (nvp->dynamic_power.idle_precondition_check_callback_scheduled))
        {
            nv_indicate_idle(nv);
@@ -1372,12 +1389,11 @@ static void timerCallbackToRemoveIdleHoldoff(
 )
 {
    OBJGPU *pGpu   = reinterpretCast(pCallbackData, OBJGPU *);
-    OBJOS *pOS     = GPU_GET_OS(pGpu);

-    pOS->osQueueWorkItemWithFlags(pGpu,
-                                  RmRemoveIdleHoldoff,
-                                  NULL,
-                                  OS_QUEUE_WORKITEM_FLAGS_LOCK_GPU_GROUP_SUBDEVICE_RW);
+    osQueueWorkItemWithFlags(pGpu,
+                             RmRemoveIdleHoldoff,
+                             NULL,
+                             OS_QUEUE_WORKITEM_FLAGS_LOCK_GPU_GROUP_SUBDEVICE_RW);
 }

 /*!
@@ -1393,15 +1409,14 @@ static void timerCallbackToIndicateIdle(
    OBJGPU     *pGpu    = reinterpretCast(pCallbackData, OBJGPU *);
    nv_state_t *nv      = NV_GET_NV_STATE(pGpu);
    nv_priv_t  *nvp     = NV_GET_NV_PRIV(nv);
-    OBJOS      *pOS     = GPU_GET_OS(pGpu);

    nv_acquire_mmap_lock(nv);

    if (nv_get_all_mappings_revoked_locked(nv) &&
        nvp->dynamic_power.state == NV_DYNAMIC_POWER_STATE_IDLE_SUSTAINED &&
-        RmCheckForGpuIdlenessUnderGpuLock(pGpu))
+        RmCanEnterGcxUnderGpuLock(pGpu))
    {
-        pOS->osQueueWorkItem(pGpu, RmIndicateIdle, NULL);
+        osQueueWorkItem(pGpu, RmIndicateIdle, NULL);
    }
    else
    {
@@ -1459,7 +1474,7 @@ static void timerCallbackForIdlePreConditions(

    if (nvp->dynamic_power.state != NV_DYNAMIC_POWER_STATE_IN_USE)
    {
-        if (RmCheckForGpuIdlenessUnderGpuLock(pGpu))
+        if (RmCanEnterGcxUnderGpuLock(pGpu))
        {
            switch (nvp->dynamic_power.state)
            {
@@ -1927,7 +1942,7 @@ static void RmScheduleCallbackToRemoveIdleHoldoff(
 *
 * @param[in]   pGpu    OBJGPU pointer.
 */
-static NvBool RmCheckRtd3Gc6Support(
+static NvBool RmCheckRtd3GcxSupport(
    nv_state_t *pNv
 )
 {
@@ -1936,6 +1951,8 @@ static NvBool RmCheckRtd3Gc6Support(
    RM_API    *pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL);
    NV_STATUS  status;
    NV0080_CTRL_GPU_GET_VIRTUALIZATION_MODE_PARAMS virtModeParams = { 0 };
+    NvBool     bGC6Support   = NV_FALSE;
+    NvBool     bGCOFFSupport = NV_FALSE;

    if (!pGpu->getProperty(pGpu, PDB_PROP_GPU_UNIX_DYNAMIC_POWER_SUPPORTED))
    {
@@ -1943,15 +1960,22 @@ static NvBool RmCheckRtd3Gc6Support(
        return NV_FALSE;
    }

-    if (!pGpu->getProperty(pGpu, PDB_PROP_GPU_RTD3_GC6_SUPPORTED))
+    if (nvp->b_mobile_config_enabled)
    {
-        NV_PRINTF(LEVEL_NOTICE, "NVRM: RTD3/GC6 is not supported in Vbios\n");
-        return NV_FALSE;
+        bGC6Support = pGpu->getProperty(pGpu, PDB_PROP_GPU_RTD3_GC6_SUPPORTED);
+        bGCOFFSupport = bGC6Support;
+    }
+    else
+    {
+        bGC6Support = pGpu->getProperty(pGpu, PDB_PROP_GPU_RTD3_GC6_SUPPORTED);
+        bGCOFFSupport = pGpu->getProperty(pGpu, PDB_PROP_GPU_RTD3_GCOFF_SUPPORTED);
    }

-    if (!nvp->b_mobile_config_enabled)
+    if (!bGC6Support && !bGCOFFSupport)
    {
-        NV_PRINTF(LEVEL_NOTICE, "NVRM: Disabling RTD3/GC6, as it is only supported on Notebook SKU\n");
+        NV_PRINTF(LEVEL_NOTICE,
+                  "NVRM: Disabling RTD3. [GC6 support=%d GCOFF support=%d]\n",
+                  bGC6Support, bGCOFFSupport);
        return NV_FALSE;
    }

@@ -1997,7 +2021,7 @@ void RmInitDeferredDynamicPowerManagement(
        {
            OBJGPU *pGpu = NV_GET_NV_PRIV_PGPU(nv);

-            if (!RmCheckRtd3Gc6Support(nv))
+            if (!RmCheckRtd3GcxSupport(nv))
            {
                 nvp->dynamic_power.mode = NV_DYNAMIC_PM_NEVER;
                 nvp->dynamic_power.b_fine_not_supported = NV_TRUE;
@@ -2221,7 +2245,8 @@ RmPowerManagement(
 NV_STATUS RmGcxPowerManagement(
    OBJGPU *pGpu,
    NvBool  bEnter,
-    NvBool  bIsDynamicPM
+    NvBool  bIsDynamicPM,
+    NvBool *bTryAgain
 )
 {
    KernelMemorySystem *pKernelMemorySystem = GPU_GET_KERNEL_MEMORY_SYSTEM(pGpu);
@@ -2245,16 +2270,21 @@ NV_STATUS RmGcxPowerManagement(
    if (bEnter)
    {
        MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu);
-        NvU64          usedFbSize;
-        NvBool         bCanUseGc6;
+        NvU64          usedFbSize = 0;
+        NvBool         bCanUseGc6 = NV_FALSE;
+        NV_STATUS      fbsrStatus = NV_ERR_GENERIC;

        //
-        // Check if GC6 can be used for current power management request.
-        // For dynamic PM, it can be used always.
-        // For system PM, it can be used only if current system suspend
-        // happened with s2idle.
+        // If the GPU supports GC6, then check if GC6 can be used for
+        // the current power management request.
+        // 1. For dynamic PM, GC6 can be used if it is supported by the GPU.
+        // 2. For system PM with s2idle, GC6 can be used if it is
+        //    supported by the GPU.
        //
-        bCanUseGc6 = bIsDynamicPM ? NV_TRUE : nv_s2idle_pm_configured();
+        if (pGpu->getProperty(pGpu, PDB_PROP_GPU_RTD3_GC6_SUPPORTED))
+        {
+            bCanUseGc6 = bIsDynamicPM ? NV_TRUE : nv_s2idle_pm_configured();
+        }

        //
        // If GC6 cannot be used, then no need to compare the used FB size with
@@ -2262,8 +2292,8 @@ NV_STATUS RmGcxPowerManagement(
        //
        if ((memmgrGetUsedRamSize(pGpu, pMemoryManager, &usedFbSize) == NV_OK) &&
            (!bCanUseGc6 || RmCheckForGcOffPM(pGpu, usedFbSize, bIsDynamicPM)) &&
-            (fbsrReserveSysMemoryForPowerMgmt(pGpu, pMemoryManager->pFbsr[FBSR_TYPE_DMA],
-                                             usedFbSize) == NV_OK))
+            ((fbsrStatus = fbsrReserveSysMemoryForPowerMgmt(pGpu, pMemoryManager->pFbsr[FBSR_TYPE_DMA],
+                                             usedFbSize)) == NV_OK))
        {
            pGpu->setProperty(pGpu, PDB_PROP_GPU_GCOFF_STATE_ENTERING, NV_TRUE);

@@ -2330,19 +2360,32 @@ NV_STATUS RmGcxPowerManagement(
            }
        }
        //
-        // This condition will hit only for systems which support s2idle but
-        // are currently configured for deep sleep based system power
-        // management, and that too when sufficient system memory
-        // is not available. For this case, the suspend request will fail
-        // and the system will remain in S0.
+        // The else condition below will hit in the following cases: 
+        // Case 1. During system suspend transition: For systems that support s2idle but are configured
+        // for deep sleep, this "else" condition will be hit when the system memory 
+        // is not sufficient. In this case, we should unset bTryAgain to abort the current suspend entry. 
+        // Case 2. During runtime suspend transition: For systems that do not support GC6 but support 
+        // GCOFF, this "else" condition will be hit when system memory is not sufficent, In this case, we 
+        // should set bTryagain so that the kernel can reschedule the callback later. 
        //
        else
        {
-            status = NV_ERR_NOT_SUPPORTED;
-            NV_PRINTF(LEVEL_ERROR,
-                      "NVRM: %s: System suspend failed with current system suspend configuration. "
-                      "Please change the system suspend configuration to s2idle in /sys/power/mem_sleep.\n",
-                      __FUNCTION__);
+            if (bIsDynamicPM)
+            {
+                if (fbsrStatus == NV_ERR_NO_MEMORY)
+                {
+                    *bTryAgain = NV_TRUE;
+                }
+                status = fbsrStatus;
+            }
+            else
+            {
+                status = NV_ERR_NOT_SUPPORTED;
+                NV_PRINTF(LEVEL_ERROR,
+                          "NVRM: %s: System suspend failed with current system suspend configuration. "
+                          "Please change the system suspend configuration to s2idle in /sys/power/mem_sleep.\n",
+                          __FUNCTION__);
+            }
        }
    }
    else
@@ -2377,6 +2420,7 @@ NV_STATUS NV_API_CALL rm_power_management(
    THREAD_STATE_NODE threadState;
    NV_STATUS rmStatus = NV_OK;
    void *fp;
+    NvBool bTryAgain = NV_FALSE;

    NV_ENTER_RM_RUNTIME(sp,fp);
    threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE);
@@ -2421,7 +2465,7 @@ NV_STATUS NV_API_CALL rm_power_management(
                    {
                        rmStatus = RmGcxPowerManagement(pGpu,
                                        pmAction == NV_PM_ACTION_STANDBY,
-                                        NV_FALSE);
+                                        NV_FALSE, &bTryAgain);

                    }
                    else
@@ -2461,13 +2505,14 @@ NV_STATUS NV_API_CALL rm_power_management(
 */
 static NV_STATUS RmTransitionDynamicPower(
    OBJGPU *pGpu,
-    NvBool  bEnter
+    NvBool  bEnter,
+    NvBool *bTryAgain
 )
 {
    nv_state_t *nv   = NV_GET_NV_STATE(pGpu);
    NV_STATUS   status;

-    status = RmGcxPowerManagement(pGpu, bEnter, NV_TRUE);
+    status = RmGcxPowerManagement(pGpu, bEnter, NV_TRUE, bTryAgain);

    if (!bEnter && status == NV_OK)
    {
@@ -2493,7 +2538,8 @@ static NV_STATUS RmTransitionDynamicPower(
 NV_STATUS NV_API_CALL rm_transition_dynamic_power(
    nvidia_stack_t *sp,
    nv_state_t     *nv,
-    NvBool          bEnter
+    NvBool          bEnter,
+    NvBool         *bTryAgain
 )
 {
    OBJGPU             *pGpu = NV_GET_NV_PRIV_PGPU(nv);
@@ -2509,7 +2555,7 @@ NV_STATUS NV_API_CALL rm_transition_dynamic_power(
    status = rmGpuLocksAcquire(GPUS_LOCK_FLAGS_NONE, RM_LOCK_MODULES_DYN_POWER);
    if (status == NV_OK)
    {
-        status = RmTransitionDynamicPower(pGpu, bEnter);
+        status = RmTransitionDynamicPower(pGpu, bEnter, bTryAgain);

        // UNLOCK: release GPUs lock
        rmGpuLocksRelease(GPUS_LOCK_FLAGS_NONE, NULL);
@@ -2670,15 +2716,14 @@ static void RmQueueIdleSustainedWorkitem(
 {
    nv_state_t *nv   = NV_GET_NV_STATE(pGpu);
    nv_priv_t  *nvp  = NV_GET_NV_PRIV(nv);
-    OBJOS      *pOS  = GPU_GET_OS(pGpu);
    NV_STATUS status = NV_OK;

    if (!nvp->dynamic_power.b_idle_sustained_workitem_queued)
    {
-        status = pOS->osQueueWorkItemWithFlags(pGpu,
-                                               RmHandleIdleSustained,
-                                               NULL,
-                                               OS_QUEUE_WORKITEM_FLAGS_LOCK_GPU_GROUP_SUBDEVICE_RW);
+        status = osQueueWorkItemWithFlags(pGpu,
+                                          RmHandleIdleSustained,
+                                          NULL,
+                                          OS_QUEUE_WORKITEM_FLAGS_LOCK_GPU_GROUP_SUBDEVICE_RW);
        if (status != NV_OK)
        {
            NV_PRINTF(LEVEL_WARNING,
@@ -2703,10 +2748,16 @@ RmInitS0ixPowerManagement(
    NvU32       data;
    NvBool      bRtd3Gc6Support = NV_FALSE;

+    // S0ix-based S2Idle, on desktops, is not supported yet. Return early for desktop SKUs
+    if (!nvp->b_mobile_config_enabled)
+    {
+        return;
+    }
+
    // LOCK: acquire GPUs lock
    if (rmGpuLocksAcquire(GPUS_LOCK_FLAGS_NONE, RM_LOCK_MODULES_INIT) == NV_OK)
    {
-        bRtd3Gc6Support = RmCheckRtd3Gc6Support(nv);
+        bRtd3Gc6Support = RmCheckRtd3GcxSupport(nv);

        // UNLOCK: release GPUs lock
        rmGpuLocksRelease(GPUS_LOCK_FLAGS_NONE, NULL);
--- a/src/nvidia/arch/nvalloc/unix/src/escape.c
+++ b/src/nvidia/arch/nvalloc/unix/src/escape.c
@@ -48,7 +48,7 @@

 #include "rmapi/client_resource.h"
 #include "nvlog/nvlog.h"
-#include <nv-ioctl-nvlog.h>
+#include <nv-ioctl-lockless-diag.h>

 #include <ctrl/ctrl00fd.h>

@@ -70,18 +70,8 @@
    }                                          \
 }

-static NvBool RmIsDeviceRefNeeded(NVOS54_PARAMETERS *pApi)
-{
-    switch(pApi->cmd)
-    {
-        case NV00FD_CTRL_CMD_ATTACH_GPU:
-            return NV_TRUE;
-        default:
-            return NV_FALSE;
-    }
-}
-
-static NV_STATUS RmGetDeviceFd(NVOS54_PARAMETERS *pApi, NvS32 *pFd)
+static NV_STATUS RmGetDeviceFd(NVOS54_PARAMETERS *pApi, NvS32 *pFd,
+                               NvBool *pSkipDeviceRef)
 {
    RMAPI_PARAM_COPY paramCopy;
    void *pKernelParams;
@@ -89,6 +79,7 @@ static NV_STATUS RmGetDeviceFd(NVOS54_PARAMETERS *pApi, NvS32 *pFd)
    NV_STATUS status;

    *pFd = -1;
+    *pSkipDeviceRef = NV_TRUE;

    switch(pApi->cmd)
    {
@@ -96,7 +87,7 @@ static NV_STATUS RmGetDeviceFd(NVOS54_PARAMETERS *pApi, NvS32 *pFd)
            paramSize = sizeof(NV00FD_CTRL_ATTACH_GPU_PARAMS);
            break;
        default:
-            return NV_ERR_INVALID_ARGUMENT;
+            return NV_OK;
    }

    RMAPI_PARAM_COPY_INIT(paramCopy, pKernelParams, pApi->params, paramSize, 1);
@@ -108,7 +99,12 @@ static NV_STATUS RmGetDeviceFd(NVOS54_PARAMETERS *pApi, NvS32 *pFd)
    switch(pApi->cmd)
    {
        case NV00FD_CTRL_CMD_ATTACH_GPU:
-            *pFd = (NvS32)((NV00FD_CTRL_ATTACH_GPU_PARAMS *)pKernelParams)->devDescriptor;
+            {
+                NV00FD_CTRL_ATTACH_GPU_PARAMS *pAttachGpuParams = pKernelParams;
+
+                *pSkipDeviceRef = NV_FALSE;
+                 *pFd = (NvS32)pAttachGpuParams->devDescriptor;
+            }
            break;
        default:
            NV_ASSERT(0);
@@ -761,6 +757,7 @@ NV_STATUS RmIoctl(
            void *priv = NULL;
            nv_file_private_t *dev_nvfp = NULL;
            NvS32 fd;
+            NvBool bSkipDeviceRef;

            NV_CTL_DEVICE_ONLY(nv);

@@ -770,14 +767,14 @@ NV_STATUS RmIoctl(
                goto done;
            }

-            if (RmIsDeviceRefNeeded(pApi))
+            rmStatus = RmGetDeviceFd(pApi, &fd, &bSkipDeviceRef);
+            if (rmStatus != NV_OK)
            {
-                rmStatus = RmGetDeviceFd(pApi, &fd);
-                if (rmStatus != NV_OK)
-                {
-                    goto done;
-                }
+                goto done;
+            }

+            if (!bSkipDeviceRef)
+            {
                dev_nvfp = nv_get_file_private(fd, NV_FALSE, &priv);
                if (dev_nvfp == NULL)
                {
@@ -843,9 +840,9 @@ NV_STATUS RmIoctl(
            break;
        }

-        case NV_ESC_RM_NVLOG_CTRL:
+        case NV_ESC_RM_LOCKLESS_DIAGNOSTIC:
        {
-            NV_NVLOG_CTRL_PARAMS *pParams = data;
+            NV_LOCKLESS_DIAGNOSTIC_PARAMS *pParams = data;

            NV_CTL_DEVICE_ONLY(nv);

@@ -856,7 +853,7 @@ NV_STATUS RmIoctl(
                goto done;
            }

-            switch (pParams->ctrl)
+            switch (pParams->cmd)
            {
                // Do not use NVOC _DISPATCH here as it dereferences NULL RmClientResource*
                case NV0000_CTRL_CMD_NVD_GET_NVLOG_INFO:
--- a/src/nvidia/arch/nvalloc/unix/src/os-hypervisor.c
+++ b/src/nvidia/arch/nvalloc/unix/src/os-hypervisor.c
@@ -46,13 +46,14 @@
 #include <nv_ref.h>               // NV_PMC_BOOT_1_VGPU
 #include "nvdevid.h"

+#define NV_VFIO_PCI_BAR0_REGION_INDEX 0
 #define NV_VFIO_PCI_BAR1_REGION_INDEX 1
 #define NV_VFIO_PCI_BAR2_REGION_INDEX 2
 #define NV_VFIO_PCI_BAR3_REGION_INDEX 3

 static NV_STATUS nv_parse_config_params(const char *, const char *, const char, NvU32 *);

-void hypervisorSetHypervVgpuSupported_IMPL(POBJHYPERVISOR pHypervisor)
+void hypervisorSetHypervVgpuSupported_IMPL(OBJHYPERVISOR *pHypervisor)
 {
    pHypervisor->bIsHypervVgpuSupported = NV_TRUE;
 }
@@ -67,14 +68,14 @@ NvBool hypervisorIsAC_IMPL(void)
    return NV_FALSE;
 }

-void hypervisorSetACSupported_IMPL(POBJHYPERVISOR pHypervisor)
+void hypervisorSetACSupported_IMPL(OBJHYPERVISOR *pHypervisor)
 {
    pHypervisor->bIsACSupported = NV_TRUE;
 }

 NV_STATUS hypervisorInjectInterrupt_IMPL
 (
-    POBJHYPERVISOR pHypervisor,
+    OBJHYPERVISOR *pHypervisor,
    VGPU_NS_INTR   *pVgpuNsIntr
 )
 {
@@ -98,7 +99,7 @@ NV_STATUS hypervisorInjectInterrupt_IMPL
 HYPERVISOR_TYPE NV_API_CALL nv_get_hypervisor_type(void)
 {
    OBJSYS *pSys = SYS_GET_INSTANCE();
-    POBJHYPERVISOR pHypervisor = SYS_GET_HYPERVISOR(pSys);
+    OBJHYPERVISOR *pHypervisor = SYS_GET_HYPERVISOR(pSys);
    return hypervisorGetHypervisorType(pHypervisor);
 }

@@ -268,7 +269,7 @@ NV_STATUS  NV_API_CALL nv_vgpu_get_type_info(
                    case VGPU_TYPE_DESCRIPTION:
                         os_snprintf(buffer, MAX_STR_LEN,
                                     "num_heads=%d, frl_config=%d, "
-                                     "framebuffer=%dM, max_resolution=%dx%d, max_instance=%d\n",
+                                     "framebuffer=%lluM, max_resolution=%dx%d, max_instance=%d\n",
                                     vgpuTypeInfo->numHeads, vgpuTypeInfo->frlConfig,
                                     vgpuTypeInfo->profileSize >> 20,
                                     vgpuTypeInfo->maxResolutionX,
@@ -474,13 +475,56 @@ NV_STATUS  NV_API_CALL nv_vgpu_create_request(
    return rmStatus;
 }

+static NV_STATUS is_bar_64bit(
+    OBJGPU *pGpu,
+    NvU32 regionIndex,
+    NvBool *isBar64bit
+)
+{
+    NV_STATUS   rmStatus = NV_OK;
+
+    if (pGpu == NULL)
+    {
+        NV_PRINTF(LEVEL_ERROR, "%s GPU handle is not valid \n", __FUNCTION__);
+        rmStatus = NV_ERR_INVALID_STATE;
+        goto exit;
+    }
+
+    switch (regionIndex)
+    {
+        case NV_VFIO_PCI_BAR0_REGION_INDEX:
+            *isBar64bit = pGpu->sriovState.b64bitVFBar0;
+            break;
+
+        case NV_VFIO_PCI_BAR1_REGION_INDEX:
+            *isBar64bit = pGpu->sriovState.b64bitVFBar1;
+            break;
+
+        case NV_VFIO_PCI_BAR2_REGION_INDEX:
+            *isBar64bit = pGpu->sriovState.b64bitVFBar2;
+            break;
+
+        default:
+            NV_PRINTF(LEVEL_ERROR, "BAR%d region doesn't exist!\n", regionIndex);
+            rmStatus = NV_ERR_INVALID_ARGUMENT;
+            goto exit;
+            break;
+    }
+
+    NV_PRINTF(LEVEL_INFO, "BAR%d region is_64bit: %d\n", regionIndex, *isBar64bit);;
+
+exit:
+    return rmStatus;
+}
+
 NV_STATUS NV_API_CALL nv_vgpu_get_bar_info(
    nvidia_stack_t *sp,
    nv_state_t *pNv,
    const NvU8 *pMdevUuid,
    NvU64 *size,
    NvU32 regionIndex,
-    void *pVgpuVfioRef
+    void *pVgpuVfioRef,
+    NvBool *isBar64bit
 )
 {
    REQUEST_VGPU_INFO_NODE *pRequestVgpu = NULL;
@@ -497,6 +541,16 @@ NV_STATUS NV_API_CALL nv_vgpu_get_bar_info(
    NV_ENTER_RM_RUNTIME(sp,fp);
    threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE);

+    /*
+     * This function can be used to query both BAR 64bit state and/or BAR size
+     * If neither is queried, return with error.
+     */
+    if ((size == NULL) && (isBar64bit == NULL))
+    {
+        rmStatus = NV_ERR_INVALID_ARGUMENT;
+        goto exit;
+    }
+
    // LOCK: acquire API lock
    NV_CHECK_OK_OR_GOTO(rmStatus, LEVEL_SILENT, rmapiLockAcquire(API_LOCK_FLAGS_NONE, RM_LOCK_MODULES_HYPERVISOR), exit);

@@ -507,6 +561,18 @@ NV_STATUS NV_API_CALL nv_vgpu_get_bar_info(
        rmStatus = NV_ERR_INVALID_STATE;
        goto release_lock;
    }
+
+    /* Get input BAR index 64bit state */
+    if (isBar64bit != NULL)
+    {
+        NV_CHECK_OK_OR_GOTO(rmStatus, LEVEL_SILENT,
+            is_bar_64bit(pGpu, regionIndex, isBar64bit), release_lock);
+
+        /* Query is only for BAR index 64bit state*/
+        if (size == NULL)
+            goto release_lock;
+    }
+
    pKernelBus = GPU_GET_KERNEL_BUS(pGpu);
    *size = kbusGetPciBarSize(pKernelBus, regionIndex);

@@ -596,6 +662,71 @@ exit:
    return rmStatus;
 }

+NV_STATUS NV_API_CALL nv_vgpu_get_hbm_info(
+    nvidia_stack_t *sp,
+    nv_state_t *pNv,
+    const NvU8 *pMdevUuid,
+    NvU64 *hbmAddr,
+    NvU64 *size
+)
+{
+    NV_STATUS    rmStatus = NV_OK;
+    THREAD_STATE_NODE threadState;
+    OBJGPU      *pGpu = NULL;
+    KERNEL_HOST_VGPU_DEVICE *pKernelHostVgpuDevice;
+    void         *fp = NULL;
+
+    NV_ENTER_RM_RUNTIME(sp,fp);
+    threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE);
+
+    if ((size == NULL) || (hbmAddr == NULL))
+    {
+        rmStatus = NV_ERR_INVALID_ARGUMENT;
+        goto exit;
+    }
+
+    // LOCK: acquire API lock
+    NV_CHECK_OK_OR_GOTO(rmStatus, LEVEL_SILENT, rmapiLockAcquire(API_LOCK_FLAGS_NONE, RM_LOCK_MODULES_HYPERVISOR), exit);
+
+    pGpu = NV_GET_NV_PRIV_PGPU(pNv);
+    if (pGpu == NULL)
+    {
+        NV_PRINTF(LEVEL_ERROR, "%s GPU handle is not valid \n", __FUNCTION__);
+        rmStatus = NV_ERR_INVALID_STATE;
+        goto release_lock;
+    }
+
+    NV_CHECK_OK_OR_GOTO(rmStatus, LEVEL_SILENT,
+                        kvgpumgrGetHostVgpuDeviceFromMdevUuid(pNv->gpu_id,
+                                                              pMdevUuid,
+                                                              &pKernelHostVgpuDevice), release_lock);
+    if (pKernelHostVgpuDevice->numValidHbmRegions > 1)
+    {
+        NV_PRINTF(LEVEL_NOTICE, "non contiguous HBM region is not supported\n");
+        NV_ASSERT(0);
+    }
+
+    if (pKernelHostVgpuDevice->hbmRegionList != NULL)
+    {
+        *hbmAddr = pKernelHostVgpuDevice->hbmRegionList[0].hbmBaseAddr;
+        *size = pKernelHostVgpuDevice->hbmRegionList[0].size;
+    }
+    else
+    {
+        *hbmAddr = 0;
+        *size = 0;
+    }
+
+release_lock:
+    // UNLOCK: release API lock
+    rmapiLockRelease();
+exit:
+
+    threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE);
+    NV_EXIT_RM_RUNTIME(sp,fp);
+    return rmStatus;
+}
+
 NV_STATUS osVgpuVfioWake(
    void *waitQueue
 )
@@ -686,7 +817,7 @@ NV_STATUS  NV_API_CALL  nv_vgpu_get_sparse_mmap(
    THREAD_STATE_NODE threadState;
    NV_STATUS rmStatus = NV_ERR_INVALID_STATE, status;
    OBJGPU *pGpu = NULL;
-    POBJTMR pTmr = NULL;
+    OBJTMR *pTmr = NULL;
    KernelFifo *pKernelFifo = NULL;
    void *fp = NULL;
    REQUEST_VGPU_INFO_NODE *pRequestVgpu = NULL;
@@ -1038,7 +1169,7 @@ NV_STATUS rm_is_vgpu_supported_device(
 )
 {
    OBJSYS *pSys = SYS_GET_INSTANCE();
-    POBJHYPERVISOR pHypervisor = SYS_GET_HYPERVISOR(pSys);
+    OBJHYPERVISOR *pHypervisor = SYS_GET_HYPERVISOR(pSys);
    NvBool is_sriov_enabled = FLD_TEST_DRF(_PMC, _BOOT_1, _VGPU, _VF, pmc_boot_1);

    // if not running in vGPU mode (guest VM) return NV_OK
--- a/src/nvidia/arch/nvalloc/unix/src/os.c
+++ b/src/nvidia/arch/nvalloc/unix/src/os.c
@@ -40,6 +40,8 @@
 #include "nverror.h"
 #include "kernel/gpu/bif/kernel_bif.h"

+#include "gpu/mig_mgr/kernel_mig_manager.h"
+
 #include "gpu/mem_sys/kern_mem_sys.h"

 #include "mem_mgr/io_vaspace.h"
@@ -722,11 +724,6 @@ void osDetachFromProcess(void* pProcessInfo)
    return;
 }

-NvBool osDbgBreakpointEnabled(void)
-{
-    return NV_TRUE;
-}
-
 NV_STATUS osAcquireRmSema(void *pSema)
 {
    return NV_OK;
@@ -808,15 +805,6 @@ NV_STATUS osQueueWorkItemWithFlags(
    return status;
 }

-NV_STATUS osQueueWorkItem(
-    OBJGPU *pGpu,
-    OSWorkItemFunction pFunction,
-    void *pParams
-)
-{
-    return osQueueWorkItemWithFlags(pGpu, pFunction, pParams, OS_QUEUE_WORKITEM_FLAGS_NONE);
-}
-
 NV_STATUS osQueueSystemWorkItem(
    OSSystemWorkItemFunction pFunction,
    void *pParams
@@ -909,12 +897,13 @@ NV_STATUS osAllocPagesInternal(
    MEMORY_DESCRIPTOR *pMemDesc
 )
 {
-    OBJSYS    *pSys = SYS_GET_INSTANCE();
-    OBJGPU *pGpu = pMemDesc->pGpu;
-    nv_state_t *nv = NV_GET_NV_STATE(pGpu);
-    void *pMemData = NULL;
-    NV_STATUS status;
-    NvS32     nodeId = -1;
+    OBJSYS           *pSys      = SYS_GET_INSTANCE();
+    OBJGPU           *pGpu      = pMemDesc->pGpu;
+    nv_state_t       *nv        = NV_GET_NV_STATE(pGpu);
+    void             *pMemData  = NULL;
+    NV_STATUS         status;
+    NvS32             nodeId    = NV0000_CTRL_NO_NUMA_NODE;
+    NV_ADDRESS_SPACE  addrSpace = memdescGetAddressSpace(pMemDesc);

    memdescSetAddress(pMemDesc, NvP64_NULL);
    memdescSetMemData(pMemDesc, NULL, NULL);
@@ -955,7 +944,11 @@ NV_STATUS osAllocPagesInternal(
        //
        unencrypted = memdescGetFlag(pMemDesc, MEMDESC_FLAGS_ALLOC_IN_UNPROTECTED_MEMORY);

-        if (pMemDesc->_addressSpace == ADDR_EGM)
+        if (addrSpace == ADDR_SYSMEM)
+        {
+            nodeId = memdescGetNumaNode(pMemDesc);
+        }
+        else if (addrSpace == ADDR_EGM)
        {
            nodeId = GPU_GET_MEMORY_MANAGER(pGpu)->localEgmNodeId;
        }
@@ -966,9 +959,22 @@ NV_STATUS osAllocPagesInternal(
        }
        else
        {
+            NvU64 pageSize = osGetPageSize();
+
+            //
+            // Bug 4270864: Only non-contig EGM memory needs to specify order. Contig memory
+            // calculates it within nv_alloc_pages. The long term goal is to expand the ability
+            // to request large page size for all of sysmem.
+            //
+            if (memdescIsEgm(pMemDesc) && !memdescGetContiguity(pMemDesc, AT_CPU))
+            {
+                pageSize = memdescGetPageSize(pMemDesc, AT_GPU);
+            }
+
            status = nv_alloc_pages(
                NV_GET_NV_STATE(pGpu),
                NV_RM_PAGES_TO_OS_PAGES(pMemDesc->PageCount),
+                pageSize,
                memdescGetContiguity(pMemDesc, AT_CPU),
                memdescGetCpuCacheAttrib(pMemDesc),
                pSys->getProperty(pSys,
@@ -2018,6 +2024,7 @@ _initializeExportObjectFd
    RsResourceRef *pResourceRef;
    Device        *pDevice;
    NvU32          deviceInstance = NV_MAX_DEVICES;
+    NvU32          gpuInstanceId = NV_U32_MAX;

    if (nvfp->handles != NULL)
    {
@@ -2026,6 +2033,9 @@ _initializeExportObjectFd

    if (hDevice != 0)
    {
+        OBJGPU *pGpu;
+        MIG_INSTANCE_REF ref;
+
        status = serverutilGetResourceRef(hClient, hDevice, &pResourceRef);
        if (status != NV_OK)
        {
@@ -2039,6 +2049,18 @@ _initializeExportObjectFd
        }

        deviceInstance = pDevice->deviceInst;
+        pGpu = GPU_RES_GET_GPU(pDevice);
+
+        if (IS_MIG_IN_USE(pGpu))
+        {
+            KernelMIGManager *pKernelMIGManager = GPU_GET_KERNEL_MIG_MANAGER(pGpu);
+            status = kmigmgrGetInstanceRefFromDevice(pGpu, pKernelMIGManager,
+                                                     pDevice, &ref);
+            if (status == NV_OK)
+            {
+                gpuInstanceId = ref.pKernelMIGGpuInstance->swizzId;
+            }
+        }
    }

    NV_ASSERT_OK_OR_RETURN(os_alloc_mem((void **)&nvfp->handles,
@@ -2047,8 +2069,9 @@ _initializeExportObjectFd
    os_mem_set(nvfp->handles, 0,
               sizeof(nvfp->handles[0]) * maxObjects);

-    nvfp->maxHandles     = maxObjects;
-    nvfp->deviceInstance = deviceInstance;
+    nvfp->maxHandles        = maxObjects;
+    nvfp->deviceInstance    = deviceInstance;
+    nvfp->gpuInstanceId     = gpuInstanceId;

    if (metadata != NULL)
    {
@@ -2481,6 +2504,8 @@ cliresCtrlCmdOsUnixGetExportObjectInfo_IMPL

    pParams->maxObjects = nvfp->maxHandles;
    pParams->deviceInstance = nvfp->deviceInstance;
+    pParams->gpuInstanceId = nvfp->gpuInstanceId;
+
    os_mem_copy(pParams->metadata, nvfp->metadata, sizeof(nvfp->metadata));

 done:
@@ -3877,28 +3902,17 @@ osGetForcedC2CConnection
    int i, ret;
    NV_STATUS status;
    char path[64];
-    OBJOS *pOS;
-    OBJSYS *pSys;

    NV_ASSERT_OR_RETURN((pLinkConnection != NULL), NV_ERR_INVALID_POINTER);
    NV_ASSERT_OR_RETURN((maxLinks > 0), NV_ERR_NOT_SUPPORTED);
    NV_ASSERT_OR_RETURN((pGpu != NULL), NV_ERR_INVALID_ARGUMENT);

-    pSys = SYS_GET_INSTANCE();
-    pOS = SYS_GET_OS(pSys);
-    if (pOS == NULL || pOS->osSimEscapeRead == NULL)
-    {
-        NV_PRINTF(LEVEL_ERROR, "%s: escape reads not supported on platform\n",
-                  __FUNCTION__);
-        return NV_ERR_NOT_SUPPORTED;
-    }
-
    for (i = 0; i < maxLinks; i++)
    {
        ret = os_snprintf(path, sizeof(path), "CPU_MODEL|CM_ATS_ADDRESS|C2C%u", i);
        NV_ASSERT((ret > 0) && (ret < (sizeof(path) - 1)));

-        status = pOS->osSimEscapeRead(pGpu, path, 0, 4, &pLinkConnection[i]);
+        status = gpuSimEscapeRead(pGpu, path, 0, 4, &pLinkConnection[i]);
        if (status == NV_OK)
        {
            NV_PRINTF(LEVEL_INFO, "%s: %s=0x%X\n", __FUNCTION__,
@@ -3906,7 +3920,7 @@ osGetForcedC2CConnection
        }
        else
        {
-            NV_PRINTF(LEVEL_INFO, "%s: osSimEscapeRead for '%s' failed (%u)\n",
+            NV_PRINTF(LEVEL_INFO, "%s: gpuSimEscapeRead for '%s' failed (%u)\n",
                      __FUNCTION__, path, status);
            return NV_ERR_NOT_SUPPORTED;
        }
@@ -5468,14 +5482,6 @@ osDmabufIsSupported(void)
    return os_dma_buf_enabled;
 }

-void osAllocatedRmClient(void *pOsInfo)
-{
-    nv_file_private_t* nvfp = (nv_file_private_t*)pOsInfo;
-
-    if (nvfp != NULL)
-        nvfp->bCleanupRmapi = NV_TRUE;
-}
-
 NV_STATUS
 osGetEgmInfo
 (
@@ -5502,3 +5508,11 @@ osOfflinePageAtAddress
 {
    return os_offline_page_at_address(address);
 }
+
+void osAllocatedRmClient(void *pOsInfo)
+{
+    nv_file_private_t* nvfp = (nv_file_private_t*)pOsInfo;
+
+    if (nvfp != NULL)
+        nvfp->bCleanupRmapi = NV_TRUE;
+}
--- a/src/nvidia/arch/nvalloc/unix/src/osapi.c
+++ b/src/nvidia/arch/nvalloc/unix/src/osapi.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: Copyright (c) 1999-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-FileCopyrightText: Copyright (c) 1999-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
 * SPDX-License-Identifier: MIT
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
@@ -1339,10 +1339,37 @@ RmDmabufVerifyMemHandle(
    return NV_OK;
 }

+static NV_STATUS
+RmDmabufGetParentDevice(
+    OBJGPU    *pGpu,
+    NvHandle   hClient,
+    NvHandle   hMemory,
+    Device   **ppDevice
+)
+{
+    RsClient *pClient;
+    RsResourceRef *pDeviceRef;
+    RsResourceRef *pMemoryRef;
+
+    NV_CHECK_OK_OR_RETURN(LEVEL_ERROR,
+        serverGetClientUnderLock(&g_resServ, hClient, &pClient));
+
+    NV_CHECK_OK_OR_RETURN(LEVEL_ERROR,
+        clientGetResourceRef(pClient, hMemory, &pMemoryRef));
+
+    NV_CHECK_OK_OR_RETURN(LEVEL_ERROR,
+        refFindAncestorOfType(pMemoryRef, classId(Device), &pDeviceRef));
+
+    *ppDevice = dynamicCast(pDeviceRef->pResource, Device);
+
+    return NV_OK;
+}
+
 static NV_STATUS
 RmDmabufGetClientAndDevice(
    OBJGPU   *pGpu,
    NvHandle  hClient,
+    NvHandle  hMemory,
    NvHandle *phClient,
    NvHandle *phDevice,
    NvHandle *phSubdevice,
@@ -1355,10 +1382,18 @@ RmDmabufGetClientAndDevice(
    {
        NV_STATUS status;
        MIG_INSTANCE_REF ref;
+        Device *pParentDevice;
        KernelMIGManager *pKernelMIGManager = GPU_GET_KERNEL_MIG_MANAGER(pGpu);

-        status = kmigmgrGetInstanceRefFromClient(pGpu, pKernelMIGManager,
-                                                 hClient, &ref);
+        status = RmDmabufGetParentDevice(pGpu, hClient, hMemory,
+                                         &pParentDevice);
+        if (status != NV_OK)
+        {
+            return status;
+        }
+
+        status = kmigmgrGetInstanceRefFromDevice(pGpu, pKernelMIGManager,
+                                                 pParentDevice, &ref);
        if (status != NV_OK)
        {
            return status;
@@ -3067,7 +3102,7 @@ static NV_STATUS RmRunNanoTimerCallback(
    void *pTmrEvent
 )
 {
-    POBJTMR             pTmr = GPU_GET_TIMER(pGpu);
+    OBJTMR             *pTmr = GPU_GET_TIMER(pGpu);
    THREAD_STATE_NODE   threadState;
    NV_STATUS         status = NV_OK;
    // LOCK: try to acquire GPUs lock
@@ -3285,7 +3320,7 @@ NV_STATUS NV_API_CALL rm_is_supported_device(
    THREAD_STATE_NODE threadState;
    NV_STATUS   rmStatus;
    OBJSYS     *pSys;
-    POBJHALMGR  pHalMgr;
+    OBJHALMGR  *pHalMgr;
    GPUHWREG   *reg_mapping;
    NvU32       myHalPublicID;
    void       *fp;
@@ -4872,14 +4907,18 @@ rm_gpu_need_4k_page_isolation
    return nvp->b_4k_page_isolation_required;
 }

+//
+// This API updates only the following fields in nv_ioctl_numa_info_t:
+// - nid
+// - numa_mem_addr
+// - numa_mem_size
+// - offline_addresses
+//
+// Rest of the fields should be updated by caller.
 NV_STATUS NV_API_CALL rm_get_gpu_numa_info(
-    nvidia_stack_t *sp,
-    nv_state_t *nv,
-    NvS32 *pNid,
-    NvU64 *pNumaMemAddr,
-    NvU64 *pNumaMemSize,
-    NvU64 *pOfflineAddresses,
-    NvU32 *pOfflineAddressesCount
+    nvidia_stack_t          *sp,
+    nv_state_t              *nv,
+    nv_ioctl_numa_info_t    *numa_info
 )
 {
    NV2080_CTRL_FB_GET_NUMA_INFO_PARAMS *pParams;
@@ -4888,14 +4927,12 @@ NV_STATUS NV_API_CALL rm_get_gpu_numa_info(
    void               *fp;
    NV_STATUS           status = NV_OK;

-    if ((pNid == NULL) || (pNumaMemAddr == NULL) || (pNumaMemSize == NULL))
-    {
-        return NV_ERR_INVALID_ARGUMENT;
-    }
+    ct_assert(NV_ARRAY_ELEMENTS(numa_info->offline_addresses.addresses) >=
+          NV_ARRAY_ELEMENTS(pParams->numaOfflineAddresses));

-    if ((pOfflineAddressesCount != NULL) &&
-        ((pOfflineAddresses == NULL) ||
-         (*pOfflineAddressesCount > NV_ARRAY_ELEMENTS(pParams->numaOfflineAddresses))))
+    if ((numa_info == NULL) ||
+        (numa_info->offline_addresses.numEntries >
+         NV_ARRAY_ELEMENTS(pParams->numaOfflineAddresses)))
    {
        return NV_ERR_INVALID_ARGUMENT;
    }
@@ -4910,11 +4947,8 @@ NV_STATUS NV_API_CALL rm_get_gpu_numa_info(
    }

    portMemSet(pParams, 0, sizeof(*pParams));
-
-    if (pOfflineAddressesCount != NULL)
-    {
-        pParams->numaOfflineAddressesCount = *pOfflineAddressesCount;
-    }
+    pParams->numaOfflineAddressesCount =
+        numa_info->offline_addresses.numEntries;

    pRmApi = RmUnixRmApiPrologue(nv, &threadState, RM_LOCK_MODULES_MEM);
    if (pRmApi == NULL)
@@ -4933,14 +4967,16 @@ NV_STATUS NV_API_CALL rm_get_gpu_numa_info(
    {
        NvU32 i;

-        *pNid = pParams->numaNodeId;
-        *pNumaMemAddr = pParams->numaMemAddr;
-        *pNumaMemSize = pParams->numaMemSize;
-        *pOfflineAddressesCount = pParams->numaOfflineAddressesCount;
+        numa_info->nid = pParams->numaNodeId;
+        numa_info->numa_mem_addr = pParams->numaMemAddr;
+        numa_info->numa_mem_size = pParams->numaMemSize;
+        numa_info->offline_addresses.numEntries =
+            pParams->numaOfflineAddressesCount;

        for (i = 0; i < pParams->numaOfflineAddressesCount; i++)
        {
-            pOfflineAddresses[i] = pParams->numaOfflineAddresses[i];
+            numa_info->offline_addresses.addresses[i] =
+                pParams->numaOfflineAddresses[i];
        }
    }

@@ -5126,7 +5162,7 @@ NvBool rm_get_uefi_console_status(
    nv_state_t *nv
 )
 {
-    NvU16 fbWidth, fbHeight, fbDepth, fbPitch;
+    NvU32 fbWidth, fbHeight, fbDepth, fbPitch;
    NvU64 fbSize;
    NvU64 fbBaseAddress = 0;
    NvBool bConsoleDevice = NV_FALSE;
@@ -5140,7 +5176,7 @@ NvBool rm_get_uefi_console_status(
                       nv->bars[NV_GPU_BAR_INDEX_FB].cpu_address,
                       nv->bars[NV_GPU_BAR_INDEX_IMEM].cpu_address + 0x1000000);

-    fbSize = fbHeight * fbPitch;
+    fbSize = (NvU64)fbHeight * (NvU64)fbPitch;

    bConsoleDevice = (fbSize != 0);

@@ -5152,7 +5188,7 @@ NvU64 rm_get_uefi_console_size(
    NvU64      *pFbBaseAddress
 )
 {
-    NvU16 fbWidth, fbHeight, fbDepth, fbPitch;
+    NvU32 fbWidth, fbHeight, fbDepth, fbPitch;
    NvU64 fbSize;

    fbSize = fbWidth = fbHeight = fbDepth = fbPitch = 0;
@@ -5166,7 +5202,7 @@ NvU64 rm_get_uefi_console_size(
                       nv->bars[NV_GPU_BAR_INDEX_FB].cpu_address,
                       nv->bars[NV_GPU_BAR_INDEX_IMEM].cpu_address + 0x1000000);

-    fbSize = fbHeight * fbPitch;
+    fbSize = (NvU64)fbHeight * (NvU64)fbPitch;

    return fbSize;
 }
@@ -5545,6 +5581,7 @@ NV_STATUS NV_API_CALL rm_dma_buf_get_client_and_device(
    nvidia_stack_t *sp,
    nv_state_t     *nv,
    NvHandle        hClient,
+    NvHandle        hMemory,
    NvHandle       *phClient,
    NvHandle       *phDevice,
    NvHandle       *phSubdevice,
@@ -5568,7 +5605,8 @@ NV_STATUS NV_API_CALL rm_dma_buf_get_client_and_device(
        rmStatus = rmDeviceGpuLocksAcquire(pGpu, GPUS_LOCK_FLAGS_NONE, RM_LOCK_MODULES_OSAPI);
        if (rmStatus == NV_OK)
        {
-            rmStatus = RmDmabufGetClientAndDevice(pGpu, hClient, phClient, phDevice,
+            rmStatus = RmDmabufGetClientAndDevice(pGpu, hClient, hMemory,
+                                                  phClient, phDevice,
                                                  phSubdevice, ppGpuInstanceInfo);
            if (rmStatus == NV_OK)
            {
@@ -5641,7 +5679,7 @@ void NV_API_CALL rm_vgpu_vfio_set_driver_vm(
 )
 {
    OBJSYS *pSys;
-    POBJHYPERVISOR pHypervisor;
+    OBJHYPERVISOR *pHypervisor;
    void *fp;

    NV_ENTER_RM_RUNTIME(sp,fp);
--- a/src/nvidia/arch/nvalloc/unix/src/osinit.c
+++ b/src/nvidia/arch/nvalloc/unix/src/osinit.c
@@ -841,8 +841,8 @@ RmInitDeviceDma(
    if (nv->iovaspace_id != NV_IOVA_DOMAIN_NONE)
    {
        OBJSYS *pSys = SYS_GET_INSTANCE();
-        POBJVMM pVmm = SYS_GET_VMM(pSys);
-        POBJVASPACE pIOVAS;
+        OBJVMM *pVmm = SYS_GET_VMM(pSys);
+        OBJVASPACE *pIOVAS;
        NV_STATUS status = vmmCreateVaspace(pVmm, IO_VASPACE_A,
                                            nv->iovaspace_id, 0, 0ULL, ~0ULL,
                                            0ULL, 0ULL,
@@ -865,8 +865,8 @@ RmTeardownDeviceDma(
    if (nv->iovaspace_id != NV_IOVA_DOMAIN_NONE)
    {
        OBJSYS *pSys = SYS_GET_INSTANCE();
-        POBJVMM pVmm = SYS_GET_VMM(pSys);
-        POBJVASPACE pIOVAS;
+        OBJVMM *pVmm = SYS_GET_VMM(pSys);
+        OBJVASPACE *pIOVAS;

        if (NV_OK == vmmGetVaspaceFromId(pVmm, nv->iovaspace_id, IO_VASPACE_A, &pIOVAS))
        {
@@ -1564,22 +1564,6 @@ NvBool RmInitAdapter(

    pSys = SYS_GET_INSTANCE();

-    //
-    // WAR: If the below UEFI property is set, display RM will attempt to read
-    // the state cache during RM init in order to retrieve a snapshot of the
-    // display state that the UEFI driver has already programmed. On Orin
-    // (T234D), the UEFI boot flow is being enabled on Linux, but our UEFI
-    // driver doesn't have any display support right now. As such, our UEFI
-    // driver won't allocate any of the display channels, which means that RM
-    // will attempt to read the state cache for uninitialized channels. WAR this
-    // issue by un-setting the below UEFI property for now.
-    //
-    // JIRA task TDS-5094 tracks adding display support to the UEFI driver.
-    //
-    if (NV_IS_SOC_DISPLAY_DEVICE(nv)) {
-        pSys->setProperty(pSys, PDB_PROP_SYS_IS_UEFI, NV_FALSE);
-    }
-
    //
    // Get firmware from the OS, if requested, and decide if RM will run as a
    // firmware client.
@@ -1875,38 +1859,6 @@ NvBool RmInitAdapter(
        }
    }

-    {
-        // OpenRM support for features beyond what is used on Data Center GPUs
-        // is still fairly immature, so for now require users to opt into use of
-        // OpenRM with a special registry key, if not on a Data Center GPU.
-        const GspStaticConfigInfo *pSCI = GPU_GET_GSP_STATIC_INFO(pGpu);
-
-        if (pSCI->computeBranding != COMPUTE_BRANDING_TYPE_TESLA &&
-            ((pGpu->idInfo.PCIDeviceID >> 16) & 0xffff) != NV_PCI_DEVID_DEVICE_PG189_SKU600)
-        {
-            NvU32 data = NV_REG_OPENRM_ENABLE_UNSUPPORTED_GPUS_DEFAULT;
-            RmReadRegistryDword(nv, NV_REG_OPENRM_ENABLE_UNSUPPORTED_GPUS, &data);
-
-            if (data == NV_REG_OPENRM_ENABLE_UNSUPPORTED_GPUS_DISABLE)
-            {
-                if (!nv->printed_openrm_enable_unsupported_gpus_error)
-                {
-                    nv_printf(NV_DBG_ERRORS,
-                        "NVRM: Open nvidia.ko is only ready for use on Data Center GPUs.\n");
-                    nv_printf(NV_DBG_ERRORS,
-                        "NVRM: To force use of Open nvidia.ko on other GPUs, see the\n");
-                    nv_printf(NV_DBG_ERRORS,
-                        "NVRM: 'OpenRmEnableUnsupportedGpus' kernel module parameter described\n");
-                    nv_printf(NV_DBG_ERRORS,
-                        "NVRM: in the README.\n");
-                    nv->printed_openrm_enable_unsupported_gpus_error = NV_TRUE;
-                }
-                RM_SET_ERROR(status, RM_INIT_FIRMWARE_INIT_FAILED);
-                goto shutdown;
-            }
-        }
-    }
-
    NV_DEV_PRINTF(NV_DBG_SETUP, nv, "RmInitAdapter succeeded!\n");

    retVal = NV_TRUE;
--- a/src/nvidia/arch/nvalloc/unix/src/osmemdesc.c
+++ b/src/nvidia/arch/nvalloc/unix/src/osmemdesc.c
@@ -72,7 +72,6 @@ osCreateMemFromOsDescriptor
    void *pPrivate;

    pClient = serverutilGetClientUnderLock(hClient);
-
    if ((pDescriptor == NvP64_NULL) ||
        (*pLimit == 0) ||
        (pClient == NULL))
@@ -548,6 +547,7 @@ osCreateOsDescriptorFromPhysAddr
 )
 {
    NV_STATUS rmStatus;
+    nv_state_t *nv = NV_GET_NV_STATE(pGpu);
    MEMORY_DESCRIPTOR *pMemDesc;
    NvU64 *pPteArray;
    NvU64  base = 0;
@@ -556,6 +556,7 @@ osCreateOsDescriptorFromPhysAddr
    NvU64 *pPhys_addrs;
    NvU64  num_os_pages;
    NvU32  idx;
+
    // Currently only work with contiguous sysmem allocations
    if (!FLD_TEST_DRF(OS02, _FLAGS, _PHYSICALITY, _CONTIGUOUS, flags))
    {
@@ -566,6 +567,15 @@ osCreateOsDescriptorFromPhysAddr
    {
        // Syncpoint memory is uncached, DMA mapping needs to skip CPU sync.
        cache_type = NV_MEMORY_UNCACHED;
+
+        //
+        // Syncpoint memory is NISO. Don't attempt to IOMMU map if the NISO
+        // IOMMU isn't enabled.
+        //
+        if (!NV_SOC_IS_NISO_IOMMU_PRESENT(nv))
+        {
+            memdescFlags |= MEMDESC_FLAGS_SKIP_IOMMU_MAPPING;
+        }
    }

    if (FLD_TEST_DRF(OS02, _FLAGS, _ALLOC_NISO_DISPLAY, _YES, flags))
@@ -597,7 +607,7 @@ osCreateOsDescriptorFromPhysAddr
    num_os_pages = NV_RM_PAGES_TO_OS_PAGES(pMemDesc->PageCount);
    pPhys_addrs  = portMemAllocNonPaged(sizeof(NvU64) * num_os_pages);
    if (pPhys_addrs == NULL)
-        return NV_ERR_NO_MEMORY;
+        goto cleanup_memdesc;

    for (idx = 0; idx < num_os_pages; idx++) 
    {
@@ -605,20 +615,51 @@ osCreateOsDescriptorFromPhysAddr
    }

    *ppPrivate = NULL;
-    rmStatus = nv_register_phys_pages(NV_GET_NV_STATE(pGpu), pPhys_addrs,
-                                      num_os_pages,
+    rmStatus = nv_register_phys_pages(nv, pPhys_addrs, num_os_pages,
                                      memdescGetCpuCacheAttrib(pMemDesc),
                                      ppPrivate);
    if (rmStatus != NV_OK)
+        goto cleanup_memdesc;
+
+    //
+    // For syncpoint memory, if IOMMU skip flag wasn't set earlier,
+    // create IOVA mapping.
+    //
+    if (FLD_TEST_DRF(OS02, _FLAGS, _ALLOC_TYPE_SYNCPOINT, _APERTURE, flags) &&
+        !memdescGetFlag(pMemDesc, MEMDESC_FLAGS_SKIP_IOMMU_MAPPING))
    {
-        memdescDestroy(pMemDesc);
-        goto cleanup;
+        //
+        // memdescMapIommu() requires the OS-private data to be set on the memory
+        // descriptor, but we don't want to wire up the teardown callback just yet:
+        // that callback needs to unpin the pages, but that will already be done
+        // as part of failure handling further up the stack if memdescMapIommu()
+        // fails. So we only set up the priv-data cleanup callback once we're sure
+        // this call will succeed.
+        //
+        memdescSetMemData(pMemDesc, *ppPrivate, NULL);
+
+        rmStatus = memdescMapIommu(pMemDesc, pGpu->busInfo.iovaspaceId);
+        if (rmStatus != NV_OK)
+            goto cleanup_pages;
    }

+    // All is well - wire up the cleanup callback now
    memdescSetMemData(pMemDesc, *ppPrivate,
        osDestroyOsDescriptorFromPhysAddr);

-cleanup:
+    portMemFree(pPhys_addrs);
+
+    return NV_OK;
+
+cleanup_pages:
+    if (*ppPrivate != NULL)
+    {
+        nv_unregister_phys_pages(NV_GET_NV_STATE(pGpu), *ppPrivate);
+    }
+
+cleanup_memdesc:
+    memdescDestroy(pMemDesc);
+
    portMemFree(pPhys_addrs);

    return rmStatus;
--- a/src/nvidia/arch/nvalloc/unix/src/osnvlink.c
+++ b/src/nvidia/arch/nvalloc/unix/src/osnvlink.c
@@ -723,28 +723,17 @@ osGetForcedNVLinkConnection
    int i, ret;
    NV_STATUS status;
    char path[64];
-    OBJSYS *pSys;
-    OBJOS *pOS;

    NV_ASSERT_OR_RETURN((pLinkConnection != NULL), NV_ERR_INVALID_POINTER);
    NV_ASSERT_OR_RETURN((maxLinks > 0), NV_ERR_NOT_SUPPORTED);
    NV_ASSERT_OR_RETURN((pGpu != NULL), NV_ERR_INVALID_ARGUMENT);

-    pSys = SYS_GET_INSTANCE();
-    pOS = SYS_GET_OS(pSys);
-    if (pOS == NULL || pOS->osSimEscapeRead == NULL)
-    {
-        NV_PRINTF(LEVEL_ERROR, "%s: escape reads not supported on platform\n",
-                  __FUNCTION__);
-        return NV_ERR_NOT_SUPPORTED;
-    }
-
    for (i = 0; i < maxLinks; i++)
    {
        ret = os_snprintf(path, sizeof(path), "CPU_MODEL|CM_ATS_ADDRESS|NVLink%u", i);
        NV_ASSERT((ret > 0) && (ret < (sizeof(path) - 1)));

-        status = pOS->osSimEscapeRead(pGpu, path, 0, 4, &pLinkConnection[i]);
+        status = gpuSimEscapeRead(pGpu, path, 0, 4, &pLinkConnection[i]);
        if (status == NV_OK)
        {
            NV_PRINTF(LEVEL_INFO, "%s: %s=0x%X\n", __FUNCTION__,
@@ -752,7 +741,7 @@ osGetForcedNVLinkConnection
        }
        else
        {
-            NV_PRINTF(LEVEL_INFO, "%s: osSimEscapeRead for '%s' failed (%u)\n",
+            NV_PRINTF(LEVEL_INFO, "%s: gpuSimEscapeRead for '%s' failed (%u)\n",
                      __FUNCTION__, path, status);
            return NV_ERR_NOT_SUPPORTED;
        }
--- a/src/nvidia/arch/nvalloc/unix/src/osunix.c
+++ b/src/nvidia/arch/nvalloc/unix/src/osunix.c
@@ -53,9 +53,6 @@ initOSSpecificFunctionPointers(OBJOS *pOS)
 static void
 initMiscOSFunctionPointers(OBJOS *pOS)
 {
-    pOS->osQueueWorkItem           = osQueueWorkItem;
-    pOS->osQueueWorkItemWithFlags  = osQueueWorkItemWithFlags;
-    pOS->osQueueSystemWorkItem     = osQueueSystemWorkItem;
 }

 static void
@@ -65,8 +62,6 @@ initUnixOSFunctionPointers(OBJOS *pOS)
    pOS->osNv_rdcr4                  = nv_rdcr4;
    pOS->osNv_cpuid                  = nv_cpuid;
 #endif
-
-    pOS->osDbgBreakpointEnabled      = osDbgBreakpointEnabled;
 }

 static void
--- a/src/nvidia/arch/nvalloc/unix/src/rmobjexportimport.c
+++ b/src/nvidia/arch/nvalloc/unix/src/rmobjexportimport.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: Copyright (c) 2016-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-FileCopyrightText: Copyright (c) 2016-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
 * SPDX-License-Identifier: MIT
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
@@ -48,6 +48,9 @@
 #include "rmobjexportimport.h"
 #include "nvlimits.h"
 #include "gpu/device/device.h"
+#include "gpu/subdevice/subdevice.h"
+#include "gpu/mig_mgr/kernel_mig_manager.h"
+#include "gpu/mig_mgr/gpu_instance_subscription.h"

 #include "containers/map.h"
 #include "rmapi/rmapi.h"
@@ -62,11 +65,7 @@
 // A reference to an RmObjExportHandle
 // generated by function RmGenerateObjExportHandle().
 //
-typedef struct
-{
-    NvU32             deviceInstance;
-} RmObjExportHandleRef;
-MAKE_MAP(RmObjExportHandleMap, RmObjExportHandleRef);
+MAKE_MAP(RmObjExportHandleMap, NvU8);

 //
 // Memory allocator
@@ -99,9 +98,11 @@ typedef struct
 {
    NvHandle hRmDevice;
    NvHandle hRmSubDevice;
+    NvHandle hGpuInstSub;
 } RmObjExportDevice;
+MAKE_MAP(RmObjExportDeviceMap, RmObjExportDevice);

-RmObjExportDevice objExportDevice[NV_MAX_DEVICES];
+RmObjExportDeviceMap objExportDeviceMap;

 //
 // Usage reference counter for static object in this file like rm client used to
@@ -115,7 +116,7 @@ NvU64 objExportImportRefCount;
 static NV_STATUS  RmRefObjExportImport    (void);
 static void       RmUnrefObjExportImport  (void);

-static RmObjExportHandle RmGenerateObjExportHandle  (NvU32 deviceInstance);
+static RmObjExportHandle RmGenerateObjExportHandle  (void);
 static NV_STATUS         RmUnrefObjExportHandle     (RmObjExportHandle hObject);

 //
@@ -125,9 +126,7 @@ static NV_STATUS RmUnrefObjExportHandle(RmObjExportHandle hObject)
 {
    RM_API *pRmApi = rmapiGetInterface(RMAPI_API_LOCK_INTERNAL);

-    RmObjExportHandleRef *pHandleRef =
-                          mapFind(&objExportHandleMap, hObject);
-
+    void *pHandleRef = mapFind(&objExportHandleMap, hObject);
    if (pHandleRef == NULL)
    {
        return NV_ERR_OBJECT_NOT_FOUND;
@@ -150,7 +149,7 @@ static NV_STATUS RmUnrefObjExportHandle(RmObjExportHandle hObject)
 //
 // Generate unique RmObjExportHandle.
 //
-static RmObjExportHandle RmGenerateObjExportHandle(NvU32 deviceInstance)
+static RmObjExportHandle RmGenerateObjExportHandle(void)
 {
    //
    // The object export handle belongs to range of 0 to
@@ -168,7 +167,7 @@ static RmObjExportHandle RmGenerateObjExportHandle(NvU32 deviceInstance)

    do
    {
-        RmObjExportHandleRef *pHandleRef;
+        void *pHandleRef;

        hObject = hObjExportHandleNext++;
        /* Reset hObjExportHandleNext to next valid handle */
@@ -191,14 +190,9 @@ static RmObjExportHandle RmGenerateObjExportHandle(NvU32 deviceInstance)

    if (hObject != 0)
    {
-        RmObjExportHandleRef *pHandleRef =
-                    mapInsertNew(&objExportHandleMap, hObject);
+        void *pHandleRef = mapInsertNew(&objExportHandleMap, hObject);

-        if (pHandleRef != NULL)
-        {
-            pHandleRef->deviceInstance = deviceInstance;
-        }
-        else
+        if (pHandleRef == NULL)
        {
            hObject = 0;
        }
@@ -215,7 +209,7 @@ static RmObjExportHandle RmGenerateObjExportHandle(NvU32 deviceInstance)
 //
 static NvBool RmValidateHandleAgainstInternalHandles(RmObjExportHandle hObject)
 {
-    NvU32 i;
+    RmObjExportDeviceMapIter iter;

    //
    // No external RmObjExportHandle could be valid if hObjExportRmClient has
@@ -228,11 +222,15 @@ static NvBool RmValidateHandleAgainstInternalHandles(RmObjExportHandle hObject)
        return NV_FALSE;
    }

-    for (i = 0; i < NV_ARRAY_ELEMENTS(objExportDevice); i++)
+    iter = mapIterAll(&objExportDeviceMap);
+    while (mapIterNext(&iter))
    {
-        if (objExportDevice[i].hRmDevice != 0 &&
-            (hObject == objExportDevice[i].hRmDevice ||
-             hObject == objExportDevice[i].hRmSubDevice))
+        RmObjExportDevice *pRmObjExportDevice = iter.pValue;
+
+        if (pRmObjExportDevice->hRmDevice != 0 &&
+            (hObject == pRmObjExportDevice->hRmDevice ||
+             hObject == pRmObjExportDevice->hRmSubDevice ||
+             hObject == pRmObjExportDevice->hGpuInstSub))
        {
            return NV_FALSE;
        }
@@ -280,6 +278,7 @@ static NV_STATUS RmRefObjExportImport(void)
    }

    mapInit(&objExportHandleMap, pMemAllocator);
+    mapInit(&objExportDeviceMap, pMemAllocator);

    return NV_OK;

@@ -296,7 +295,7 @@ failed:
 //
 static void RmUnrefObjExportImport(void)
 {
-    RM_API *pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL);
+    RM_API *pRmApi = rmapiGetInterface(RMAPI_API_LOCK_INTERNAL);

    if ((--objExportImportRefCount) != 0)
    {
@@ -305,19 +304,7 @@ static void RmUnrefObjExportImport(void)

    if (pMemAllocator != NULL)
    {
-        NvU32 i;
-
-        for (i = 0; i < NV_ARRAY_ELEMENTS(objExportDevice); i++)
-        {
-            if (objExportDevice[i].hRmDevice != 0)
-            {
-                RmUnrefObjExportHandle(objExportDevice[i].hRmSubDevice);
-                objExportDevice[i].hRmSubDevice = 0;
-                RmUnrefObjExportHandle(objExportDevice[i].hRmDevice);
-                objExportDevice[i].hRmDevice = 0;
-            }
-        }
-
+        mapDestroy(&objExportDeviceMap);
        mapDestroy(&objExportHandleMap);

        portMemAllocatorRelease(pMemAllocator);
@@ -338,12 +325,16 @@ static void RmUnrefObjExportImport(void)
 NV_STATUS RmExportObject(NvHandle hSrcClient, NvHandle hSrcObject,
                         RmObjExportHandle *pDstObject, NvU32 *pDeviceInstance)
 {
-    RmObjExportHandle hDstObject;
-    NvU32             deviceInstance = NV_MAX_DEVICES;
-    NvHandle          hTmpObject;
-    NvBool            bClientAsDstParent = NV_FALSE;
-    NV_STATUS         status;
-    RM_API           *pRmApi = rmapiGetInterface(RMAPI_API_LOCK_INTERNAL);
+    RmObjExportHandle  hDstObject;
+    NvU32              deviceInstance = NV_MAX_DEVICES;
+    NvBool             bClientAsDstParent = NV_FALSE;
+    NV_STATUS          status;
+    RM_API            *pRmApi = rmapiGetInterface(RMAPI_API_LOCK_INTERNAL);
+    MIG_INSTANCE_REF   ref = kmigmgrMakeNoMIGReference();
+    NvU64              deviceMapIdx;
+    RmObjExportDevice *pObjExportDevice;
+    RsResourceRef     *pSrcResourceRef;
+    RsResourceRef     *pDeviceRef;

    if (pDstObject == NULL)
    {
@@ -353,27 +344,33 @@ NV_STATUS RmExportObject(NvHandle hSrcClient, NvHandle hSrcObject,
    //
    // Find the device instance on which the rm object exists.
    //
-    hTmpObject = hSrcObject;
-    do
+    NV_CHECK_OK_OR_RETURN(LEVEL_ERROR,
+        serverutilGetResourceRef(hSrcClient, hSrcObject, &pSrcResourceRef));
+
+    status = refFindAncestorOfType(pSrcResourceRef, classId(Device), &pDeviceRef);
+    if (status == NV_OK)
    {
-        RsResourceRef *pResourceRef;
+        Device *pDevice = dynamicCast(pDeviceRef->pResource, Device);
+        OBJGPU *pGpu = GPU_RES_GET_GPU(pDevice);
+        NvU64 swizzId = KMIGMGR_MAX_GPU_SWIZZID;

-        status = serverutilGetResourceRef(hSrcClient, hTmpObject, &pResourceRef);
-        if (status != NV_OK)
-            return status;
-
-        Device *pDevice = dynamicCast(pResourceRef->pResource, Device);
-        if (pDevice != NULL)
+        if (IS_MIG_IN_USE(pGpu))
        {
-            deviceInstance = pDevice->deviceInst;
-            break;
+            KernelMIGManager *pKernelMIGManager = GPU_GET_KERNEL_MIG_MANAGER(pGpu);
+
+            status = kmigmgrGetInstanceRefFromDevice(pGpu, pKernelMIGManager,
+                                                     pDevice, &ref);
+            if (status == NV_OK)
+            {
+               swizzId = ref.pKernelMIGGpuInstance->swizzId;
+            }
        }

-        hTmpObject = pResourceRef->pParentRef ? pResourceRef->pParentRef->hResource : 0;
-    } while (hTmpObject != 0);
-
-    // If a memory object is not parented by a device, use client as a parent.
-    if ((hTmpObject == 0) || (deviceInstance >= NV_MAX_DEVICES))
+        deviceMapIdx = pDevice->deviceInst | (swizzId << 32);
+        deviceInstance = pDevice->deviceInst;
+        pObjExportDevice = mapFind(&objExportDeviceMap, deviceMapIdx);
+    }
+    else
    {
        bClientAsDstParent = NV_TRUE;
    }
@@ -386,9 +383,9 @@ NV_STATUS RmExportObject(NvHandle hSrcClient, NvHandle hSrcObject,
    }

    if (!bClientAsDstParent &&
-        ((objExportDevice[deviceInstance].hRmDevice == 0) ||
+        ((pObjExportDevice == NULL) ||
         serverutilValidateNewResourceHandle(hObjExportRmClient,
-                        objExportDevice[deviceInstance].hRmDevice)))
+                pObjExportDevice->hRmDevice)))
    {
        //
        // Device object has not been created or it got destroyed in the
@@ -398,21 +395,22 @@ NV_STATUS RmExportObject(NvHandle hSrcClient, NvHandle hSrcObject,
        NV0080_ALLOC_PARAMETERS params;
        NV2080_ALLOC_PARAMETERS subdevParams;

-        if (objExportDevice[deviceInstance].hRmDevice == 0)
+        if (pObjExportDevice == NULL)
        {
-            NV_ASSERT(objExportDevice[deviceInstance].hRmSubDevice == 0);
+            pObjExportDevice = mapInsertNew(&objExportDeviceMap, deviceMapIdx);

-            objExportDevice[deviceInstance].hRmDevice =
-                            RmGenerateObjExportHandle(deviceInstance);
-            objExportDevice[deviceInstance].hRmSubDevice =
-                                RmGenerateObjExportHandle(deviceInstance);
+            pObjExportDevice->hRmDevice = RmGenerateObjExportHandle();
+            pObjExportDevice->hRmSubDevice = RmGenerateObjExportHandle();
+            pObjExportDevice->hGpuInstSub = NV01_NULL_OBJECT;

-            if (objExportDevice[deviceInstance].hRmDevice == 0 ||
-                objExportDevice[deviceInstance].hRmSubDevice == 0)
+            if (pObjExportDevice->hRmDevice == 0 ||
+                pObjExportDevice->hRmSubDevice == 0)
            {
                NV_PRINTF(LEVEL_ERROR, "Failed to allocate object handles in %s\n",
                          __FUNCTION__);

+                mapRemove(&objExportDeviceMap, pObjExportDevice);
+
                status = NV_ERR_NO_MEMORY;
                goto done;
            }
@@ -421,11 +419,12 @@ NV_STATUS RmExportObject(NvHandle hSrcClient, NvHandle hSrcObject,
        portMemSet(&params, 0, sizeof(NV0080_ALLOC_PARAMETERS));

        params.deviceId = deviceInstance;
+        params.hClientShare = hObjExportRmClient;

        status = pRmApi->AllocWithHandle(pRmApi,
                                         hObjExportRmClient,
                                         hObjExportRmClient,
-                                         objExportDevice[deviceInstance].hRmDevice,
+                                         pObjExportDevice->hRmDevice,
                                         NV01_DEVICE_0,
                                         &params,
                                         sizeof(params));
@@ -442,8 +441,8 @@ NV_STATUS RmExportObject(NvHandle hSrcClient, NvHandle hSrcObject,

        status = pRmApi->AllocWithHandle(pRmApi,
                                         hObjExportRmClient,
-                                         objExportDevice[deviceInstance].hRmDevice,
-                                         objExportDevice[deviceInstance].hRmSubDevice,
+                                         pObjExportDevice->hRmDevice,
+                                         pObjExportDevice->hRmSubDevice,
                                         NV20_SUBDEVICE_0,
                                         &subdevParams,
                                         sizeof(subdevParams));
@@ -453,12 +452,41 @@ NV_STATUS RmExportObject(NvHandle hSrcClient, NvHandle hSrcObject,
                      __FUNCTION__);

            (void) pRmApi->Free(pRmApi, hObjExportRmClient,
-                                objExportDevice[deviceInstance].hRmDevice);
+                                pObjExportDevice->hRmDevice);
            goto done;
        }
+
+        // Allocate MIG subscription, if needed
+        if ((ref.pKernelMIGGpuInstance != NULL) &&
+            (ref.pKernelMIGGpuInstance->swizzId < KMIGMGR_MAX_GPU_SWIZZID))
+        {
+            NVC637_ALLOCATION_PARAMETERS giSubAllocParams;
+
+            portMemSet(&giSubAllocParams, 0, sizeof(giSubAllocParams));
+            giSubAllocParams.swizzId = ref.pKernelMIGGpuInstance->swizzId;
+
+            pObjExportDevice->hGpuInstSub = RmGenerateObjExportHandle();
+
+            status = pRmApi->AllocWithHandle(pRmApi,
+                                             hObjExportRmClient,
+                                             pObjExportDevice->hRmSubDevice,
+                                             pObjExportDevice->hGpuInstSub,
+                                             AMPERE_SMC_PARTITION_REF,
+                                             &giSubAllocParams,
+                                             sizeof(giSubAllocParams));
+            if (status != NV_OK)
+            {
+                NV_PRINTF(LEVEL_ERROR, "Unable to alloc gpu instance subscription in %s\n",
+                          __FUNCTION__);
+
+                (void) pRmApi->Free(pRmApi, hObjExportRmClient,
+                                    pObjExportDevice->hRmDevice);
+                goto done;
+            }
+        }
    }

-    hDstObject = RmGenerateObjExportHandle(deviceInstance);
+    hDstObject = RmGenerateObjExportHandle();

    if (hDstObject == 0)
    {
@@ -472,7 +500,7 @@ NV_STATUS RmExportObject(NvHandle hSrcClient, NvHandle hSrcObject,
    status = pRmApi->DupObject(pRmApi,
                               hObjExportRmClient,
                               bClientAsDstParent ? hObjExportRmClient :
-                               objExportDevice[deviceInstance].hRmDevice,
+                               pObjExportDevice->hRmDevice,
                               &hDstObject,
                               hSrcClient,
                               hSrcObject,
@@ -488,7 +516,7 @@ NV_STATUS RmExportObject(NvHandle hSrcClient, NvHandle hSrcObject,

            status = pRmApi->DupObject(pRmApi,
                                       hObjExportRmClient,
-                                       objExportDevice[deviceInstance].hRmSubDevice,
+                                       pObjExportDevice->hRmSubDevice,
                                       &hDstObject,
                                       hSrcClient,
                                       hSrcObject,
@@ -565,7 +593,12 @@ NV_STATUS RmImportObject(NvHandle hDstClient, NvHandle hDstParent,
    if (pObjectType != NULL)
    {
        params.hObject = hSrcObject;
-        params.mapFlags = 0;
+    //
+    // rmApiGetEffectiveAddrSpace expect mapping flags to be set as DIRECT for
+    // GPU cacheable Sysmem for Pre-Ampere chips. We are not doing any mapping
+    // here, so passing this as workaround to get the expected address space.
+    //
+        params.mapFlags = FLD_SET_DRF(OS33, _FLAGS, _MAPPING, _DIRECT, 0);
        params.addrSpaceType = \
                NV0000_CTRL_CMD_CLIENT_GET_ADDR_SPACE_TYPE_INVALID;

@@ -616,22 +649,3 @@ NV_STATUS RmImportObject(NvHandle hDstClient, NvHandle hDstParent,

    return NV_OK;
 }
-
-NV_STATUS RmGetExportObjectInfo(RmObjExportHandle hSrcObject, NvU32 *deviceInstance)
-{
-    RmObjExportHandleRef *pHandleRef = NULL;
-
-    if (!RmValidateHandleAgainstInternalHandles(hSrcObject))
-    {
-        return NV_ERR_INVALID_ARGUMENT;
-    }
-
-    pHandleRef = mapFind(&objExportHandleMap, hSrcObject);
-    if (pHandleRef == NULL)
-    {
-        return NV_ERR_OBJECT_NOT_FOUND;
-    }
-
-    *deviceInstance = pHandleRef->deviceInstance;
-    return NV_OK;
-}
--- a/src/nvidia/arch/nvalloc/unix/src/unix_console.c
+++ b/src/nvidia/arch/nvalloc/unix/src/unix_console.c
@@ -337,6 +337,7 @@ NV_STATUS deviceCtrlCmdOsUnixVTGetFBInfo_IMPL
            if ((memmgrGetReservedConsoleMemDesc(pGpu, pMemoryManager) != NULL) && bContinue)
            {
                NvU64 baseAddr;
+                NvU32 width, height, depth, pitch;

                // There should only be one.
                NV_ASSERT(pParams->width == 0);
@@ -344,12 +345,15 @@ NV_STATUS deviceCtrlCmdOsUnixVTGetFBInfo_IMPL
                pParams->subDeviceInstance = gpumgrGetSubDeviceInstanceFromGpu(pGpu);

                // Console is either mapped to BAR1 or BAR2 + 16 MB
-                os_get_screen_info(&baseAddr, &pParams->width,
-                                   &pParams->height, &pParams->depth,
-                                   &pParams->pitch,
+                os_get_screen_info(&baseAddr, &width, &height, &depth, &pitch,
                                   nv->bars[NV_GPU_BAR_INDEX_FB].cpu_address,
                                   nv->bars[NV_GPU_BAR_INDEX_IMEM].cpu_address + 0x1000000);

+                pParams->width = (NvU16)width;
+                pParams->height = (NvU16)height;
+                pParams->depth = (NvU16)depth;
+                pParams->pitch = (NvU16)pitch;
+
                if (baseAddr != 0)
                {
                    bContinue = NV_FALSE; 
--- a/src/nvidia/arch/nvalloc/unix/src/unix_intr.c
+++ b/src/nvidia/arch/nvalloc/unix/src/unix_intr.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
 * SPDX-License-Identifier: MIT
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
@@ -41,7 +41,7 @@ static NvBool osInterruptPending(
    THREAD_STATE_NODE *pThreadState
 )
 {
-    POBJDISP pDisp;
+    OBJDISP *pDisp;
    KernelDisplay   *pKernelDisplay;
    NvBool pending, sema_release;
    THREAD_STATE_NODE threadState;
@@ -128,7 +128,7 @@ static NvBool osInterruptPending(
                }

                intrGetPendingStall_HAL(pGpu, pIntr, &intr0Pending, &threadState);
-                POBJTMR pTmr = GPU_GET_TIMER(pGpu);
+                OBJTMR *pTmr = GPU_GET_TIMER(pGpu);
                *serviced = tmrServiceSwrlWrapper(pGpu, pTmr, &intr0Pending, &threadState);
            }
        }
@@ -338,18 +338,11 @@ void osEnableInterrupts(OBJGPU *pGpu)

        intrEn = intrGetIntrEn(pIntr);
        intrSetIntrEnInHw_HAL(pGpu, pIntr, intrEn, NULL);
-
-        if (pIntr != NULL)
-        {
-            intrSetStall_HAL(pGpu, pIntr, intrEn, NULL);
-        }
+        intrSetStall_HAL(pGpu, pIntr, intrEn, NULL);

        if (pGpu->getProperty(pGpu, PDB_PROP_GPU_ALTERNATE_TREE_ENABLED))
        {
-            if (pIntr != NULL)
-            {
-                intrRestoreNonStall_HAL(pGpu, pIntr, intrGetIntrEn(pIntr), NULL);
-            }
+            intrRestoreNonStall_HAL(pGpu, pIntr, intrGetIntrEn(pIntr), NULL);
        }

    }
@@ -373,23 +366,17 @@ void osDisableInterrupts(

        intrSetIntrEnInHw_HAL(pGpu, pIntr, new_intr_en_0, NULL);

-        if (pIntr != NULL)
-        {
-            intrSetStall_HAL(pGpu, pIntr, new_intr_en_0, NULL);
-        }
+        intrSetStall_HAL(pGpu, pIntr, new_intr_en_0, NULL);

        if (pGpu->getProperty(pGpu, PDB_PROP_GPU_ALTERNATE_TREE_ENABLED))
        {
-            if (pIntr != NULL)
+            if (pGpu->getProperty(pGpu, PDB_PROP_GPU_ALTERNATE_TREE_HANDLE_LOCKLESS))
            {
-                if (pGpu->getProperty(pGpu, PDB_PROP_GPU_ALTERNATE_TREE_HANDLE_LOCKLESS))
-                {
-                    intrRestoreNonStall_HAL(pGpu, pIntr, intrGetIntrEn(pIntr), NULL);
-                }
-                else
-                {
-                    intrRestoreNonStall_HAL(pGpu, pIntr, new_intr_en_0, NULL);
-                }
+                intrRestoreNonStall_HAL(pGpu, pIntr, intrGetIntrEn(pIntr), NULL);
+            }
+            else
+            {
+                intrRestoreNonStall_HAL(pGpu, pIntr, new_intr_en_0, NULL);
            }
        }
    }
@@ -405,7 +392,7 @@ static void RmIsrBottomHalf(
    NvU32 gpuMask, gpuInstance;
    OBJGPU *pDeviceLockGpu = pGpu;
    Intr *pIntr = NULL;
-    POBJDISP pDisp = NULL;
+    OBJDISP *pDisp = NULL;
    NvU8 stackAllocator[TLS_ISR_ALLOCATOR_SIZE]; // ISR allocations come from this buffer
    PORT_MEM_ALLOCATOR *pIsrAllocator;

--- a/src/nvidia/arch/nvalloc/unix/x86emu/prim_ops.c
+++ b/src/nvidia/arch/nvalloc/unix/x86emu/prim_ops.c
@@ -1794,20 +1794,20 @@ u8 sbb_byte(u8 d, u8 s)
    register u32 res;   /* all operands in native machine order */
    register u32 bc;

-        if (ACCESS_FLAG(F_CF))
-                res = d - s - 1;
-        else
-                res = d - s;
-        CONDITIONAL_SET_FLAG(res & 0x80, F_SF);
-        CONDITIONAL_SET_FLAG((res & 0xff) == 0, F_ZF);
-        CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF);
+    if (ACCESS_FLAG(F_CF))
+        res = d - s - 1;
+    else
+        res = d - s;
+    CONDITIONAL_SET_FLAG(res & 0x80, F_SF);
+    CONDITIONAL_SET_FLAG((res & 0xff) == 0, F_ZF);
+    CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF);

-        /* calculate the borrow chain.  See note at top */
-        bc = (res & (~d | s)) | (~d & s);
-        CONDITIONAL_SET_FLAG(bc & 0x80, F_CF);
-        CONDITIONAL_SET_FLAG(XOR2(bc >> 6), F_OF);
-        CONDITIONAL_SET_FLAG(bc & 0x8, F_AF);
-        return (u8)res;
+    /* calculate the borrow chain.  See note at top */
+    bc = (res & (~d | s)) | (~d & s);
+    CONDITIONAL_SET_FLAG(bc & 0x80, F_CF);
+    CONDITIONAL_SET_FLAG(XOR2(bc >> 6), F_OF);
+    CONDITIONAL_SET_FLAG(bc & 0x8, F_AF);
+    return (u8)res;
 }

 /****************************************************************************
@@ -1819,20 +1819,20 @@ u16 sbb_word(u16 d, u16 s)
    register u32 res;   /* all operands in native machine order */
    register u32 bc;

-        if (ACCESS_FLAG(F_CF))
+    if (ACCESS_FLAG(F_CF))
        res = d - s - 1;
    else
        res = d - s;
-        CONDITIONAL_SET_FLAG(res & 0x8000, F_SF);
-        CONDITIONAL_SET_FLAG((res & 0xffff) == 0, F_ZF);
-        CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF);
+    CONDITIONAL_SET_FLAG(res & 0x8000, F_SF);
+    CONDITIONAL_SET_FLAG((res & 0xffff) == 0, F_ZF);
+    CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF);

-        /* calculate the borrow chain.  See note at top */
-        bc = (res & (~d | s)) | (~d & s);
-        CONDITIONAL_SET_FLAG(bc & 0x8000, F_CF);
-        CONDITIONAL_SET_FLAG(XOR2(bc >> 14), F_OF);
-        CONDITIONAL_SET_FLAG(bc & 0x8, F_AF);
-        return (u16)res;
+    /* calculate the borrow chain.  See note at top */
+    bc = (res & (~d | s)) | (~d & s);
+    CONDITIONAL_SET_FLAG(bc & 0x8000, F_CF);
+    CONDITIONAL_SET_FLAG(XOR2(bc >> 14), F_OF);
+    CONDITIONAL_SET_FLAG(bc & 0x8, F_AF);
+    return (u16)res;
 }

 /****************************************************************************
@@ -1841,23 +1841,23 @@ Implements the SBB instruction and side effects.
 ****************************************************************************/
 u32 sbb_long(u32 d, u32 s)
 {
-        register u32 res;   /* all operands in native machine order */
-        register u32 bc;
+    register u32 res;   /* all operands in native machine order */
+    register u32 bc;

-        if (ACCESS_FLAG(F_CF))
+    if (ACCESS_FLAG(F_CF))
        res = d - s - 1;
    else
        res = d - s;
-        CONDITIONAL_SET_FLAG(res & 0x80000000, F_SF);
-        CONDITIONAL_SET_FLAG((res & 0xffffffff) == 0, F_ZF);
-        CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF);
+    CONDITIONAL_SET_FLAG(res & 0x80000000, F_SF);
+    CONDITIONAL_SET_FLAG((res & 0xffffffff) == 0, F_ZF);
+    CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF);

-        /* calculate the borrow chain.  See note at top */
-        bc = (res & (~d | s)) | (~d & s);
-        CONDITIONAL_SET_FLAG(bc & 0x80000000, F_CF);
-        CONDITIONAL_SET_FLAG(XOR2(bc >> 30), F_OF);
-        CONDITIONAL_SET_FLAG(bc & 0x8, F_AF);
-        return res;
+    /* calculate the borrow chain.  See note at top */
+    bc = (res & (~d | s)) | (~d & s);
+    CONDITIONAL_SET_FLAG(bc & 0x80000000, F_CF);
+    CONDITIONAL_SET_FLAG(XOR2(bc >> 30), F_OF);
+    CONDITIONAL_SET_FLAG(bc & 0x8, F_AF);
+    return res;
 }

 /****************************************************************************