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This commit is contained in:
Andy Ritger
2023-10-17 09:25:29 -07:00
parent f59818b751
commit b5bf85a8e3
917 changed files with 132480 additions and 110015 deletions
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4
src/nvidia/inc/kernel/core/locks.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -28,6 +28,7 @@
// Forward declarations
typedef struct OBJSYS OBJSYS;
typedef struct NV0000_CTRL_SYSTEM_GET_LOCK_TIMES_PARAMS NV0000_CTRL_SYSTEM_GET_LOCK_TIMES_PARAMS;
typedef enum
{
@@ -161,6 +162,7 @@ NvBool rmGpuLockIsOwner(void);
NvU32 rmGpuLocksGetOwnedMask(void);
NvBool rmGpuLockIsHidden(OBJGPU *);
NV_STATUS rmGpuLockSetOwner(OS_THREAD_HANDLE);
void rmGpuLockGetTimes(NV0000_CTRL_SYSTEM_GET_LOCK_TIMES_PARAMS *);
NV_STATUS rmGpuGroupLockAcquire(NvU32, GPU_LOCK_GRP_ID, NvU32, NvU32, GPU_MASK *);
NV_STATUS rmGpuGroupLockRelease(GPU_MASK, NvU32);
NvBool rmGpuGroupLockIsOwner(NvU32, GPU_LOCK_GRP_ID, GPU_MASK*);

8
src/nvidia/inc/kernel/core/printf.h
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@@ -56,7 +56,7 @@ extern "C" {
// NV_DBG_BREAKPOINT_ALLOWED can be overridden through CFLAGS
#if !defined(NV_DBG_BREAKPOINT_ALLOWED)
#if defined(DEBUG) || defined(ASSERT_BUILD) || defined(NV_MODS) || defined(QA_BUILD) || (defined(NVRM) && NVCPU_IS_RISCV64)
#if defined(DEBUG) || defined(ASSERT_BUILD) || defined(NV_MODS) || defined(QA_BUILD) || (defined(NVRM) && NVOS_IS_LIBOS)
#define NV_DBG_BREAKPOINT_ALLOWED 1
#else
#define NV_DBG_BREAKPOINT_ALLOWED 0
@@ -116,7 +116,7 @@ void osFlushLog(void);
#if NV_DBG_BREAKPOINT_ALLOWED
#if !NVCPU_IS_RISCV64
#if !NVOS_IS_LIBOS
#define DBG_BREAKPOINT_EX(PGPU, LEVEL) \
do \
@@ -126,7 +126,7 @@ void osFlushLog(void);
DBG_ROUTINE(); \
} while (0)
#else // !NVCPU_IS_RISCV64
#else // !NVOS_IS_LIBOS
#define DBG_BREAKPOINT_EX(PGPU, LEVEL) \
do \
@@ -134,7 +134,7 @@ void osFlushLog(void);
NV_ASSERT_FAILED("DBG_BREAKPOINT"); \
} while (0)
#endif // !NVCPU_IS_RISCV64
#endif // !NVOS_IS_LIBOS
#define DBG_BREAKPOINT() DBG_BREAKPOINT_EX(NULL, 0)

6
src/nvidia/inc/kernel/core/thread_state.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -132,6 +132,10 @@ typedef struct THREAD_STATE_DB
* sequencer id via @ref threadStateInitXYZ().
*/
NvU32 threadSeqCntr;
/*!
* Thread state sequencer id counter for only GSP task_interrupt.
*/
NvU32 gspIsrThreadSeqCntr;
PORT_SPINLOCK *spinlock;
ThreadStateNodeMap dbRoot;
ThreadStateNodeMap dbRootPreempted;

4
src/nvidia/inc/kernel/gpu/ce/kernel_ce_shared.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -30,7 +30,7 @@
* Routines shared between CE and KCE.
*/
NvBool ceIsCeGrce(OBJGPU *pGpu, NvU32 ceEngineType);
NvBool ceIsCeGrce(OBJGPU *pGpu, RM_ENGINE_TYPE ceEngineType);
NvU32 ceCountGrCe(OBJGPU *pGpu);
#endif

3
src/nvidia/inc/kernel/gpu/disp/kern_disp_max.h
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@@ -28,8 +28,7 @@
* @brief Defines max values used for the KernelDisplay Engine Object,
* including values shared by OBJDISP code.
*/
#define OBJ_MAX_HEADS 4
#define OBJ_MAX_HEADS 8
#define MAX_RG_LINE_CALLBACKS_PER_HEAD 2
#define OBJ_MAX_DFPS 31

117
src/nvidia/inc/kernel/gpu/fifo/engine_info.h Normal file
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@@ -0,0 +1,117 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _ENGINE_INFO_H_
#define _ENGINE_INFO_H_
typedef enum
{
/* *************************************************************************
* Bug 3820969
* THINK BEFORE CHANGING ENUM ORDER HERE.
* VGPU-guest uses this same ordering. Because this enum is not versioned,
* changing the order here WILL BREAK old-guest-on-newer-host compatibility.
* ************************************************************************/
// *ENG_XYZ, e.g.: ENG_GR, ENG_CE etc.,
ENGINE_INFO_TYPE_ENG_DESC = 0,
// HW engine ID
ENGINE_INFO_TYPE_FIFO_TAG,
// RM_ENGINE_TYPE_*
ENGINE_INFO_TYPE_RM_ENGINE_TYPE,
//
// runlist id (meaning varies by GPU)
// Valid only for Esched-driven engines
//
ENGINE_INFO_TYPE_RUNLIST,
// NV_PFIFO_INTR_MMU_FAULT_ENG_ID_*
ENGINE_INFO_TYPE_MMU_FAULT_ID,
// ROBUST_CHANNEL_*
ENGINE_INFO_TYPE_RC_MASK,
// Reset Bit Position. On Ampere, only valid if not _INVALID
ENGINE_INFO_TYPE_RESET,
// Interrupt Bit Position
ENGINE_INFO_TYPE_INTR,
// log2(MC_ENGINE_*)
ENGINE_INFO_TYPE_MC,
// The DEV_TYPE_ENUM for this engine
ENGINE_INFO_TYPE_DEV_TYPE_ENUM,
// The particular instance of this engine type
ENGINE_INFO_TYPE_INSTANCE_ID,
//
// The base address for this engine's NV_RUNLIST. Valid only on Ampere+
// Valid only for Esched-driven engines
//
ENGINE_INFO_TYPE_RUNLIST_PRI_BASE,
//
// If this entry is a host-driven engine.
// Update _isEngineInfoTypeValidForOnlyHostDriven when adding any new entry.
//
ENGINE_INFO_TYPE_IS_HOST_DRIVEN_ENGINE,
//
// The index into the per-engine NV_RUNLIST registers. Valid only on Ampere+
// Valid only for Esched-driven engines
//
ENGINE_INFO_TYPE_RUNLIST_ENGINE_ID,
//
// The base address for this engine's NV_CHRAM registers. Valid only on
// Ampere+
//
// Valid only for Esched-driven engines
//
ENGINE_INFO_TYPE_CHRAM_PRI_BASE,
// This entry added to copy data at RMCTRL_EXPORT() call for Kernel RM
ENGINE_INFO_TYPE_KERNEL_RM_MAX,
// Used for iterating the engine info table by the index passed.
ENGINE_INFO_TYPE_INVALID = ENGINE_INFO_TYPE_KERNEL_RM_MAX,
// Size of FIFO_ENGINE_LIST.engineData
ENGINE_INFO_TYPE_ENGINE_DATA_ARRAY_SIZE = ENGINE_INFO_TYPE_INVALID,
// Input-only parameter for kfifoEngineInfoXlate.
ENGINE_INFO_TYPE_PBDMA_ID
/* *************************************************************************
* Bug 3820969
* THINK BEFORE CHANGING ENUM ORDER HERE.
* VGPU-guest uses this same ordering. Because this enum is not versioned,
* changing the order here WILL BREAK old-guest-on-newer-host compatibility.
* ************************************************************************/
} ENGINE_INFO_TYPE;
#endif // _ENGINE_INFO_H_

2
src/nvidia/inc/kernel/gpu/gpu_child_list.h
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@@ -295,7 +295,7 @@
GPU_CHILD_SINGLE_INST( KernelFsp, GPU_GET_KERNEL_FSP, 1, NV_FALSE, pKernelFsp )
#endif
#if GPU_CHILD_MODULE(OFA)
GPU_CHILD_SINGLE_INST( OBJOFA, GPU_GET_OFA, 1, NV_FALSE, pOfa )
GPU_CHILD_MULTI_INST( OBJOFA, GPU_GET_OFA, GPU_MAX_OFAS, NV_FALSE, pOfa )
#endif
#if RMCFG_MODULE_CONF_COMPUTE && GPU_CHILD_MODULE(CONF_COMPUTE)
GPU_CHILD_SINGLE_INST( ConfidentialCompute, GPU_GET_CONF_COMPUTE, 1, NV_TRUE, pConfCompute )

25
src/nvidia/inc/kernel/gpu/gpu_engine_type.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -27,6 +27,7 @@
#include "class/cl2080.h"
#include "nvrangetypes.h"
#include "utils/nvbitvector.h"
#include "rmconfig.h"
typedef enum
{
@@ -49,6 +50,16 @@ typedef enum
RM_ENGINE_TYPE_COPY7 = (0x00000010),
RM_ENGINE_TYPE_COPY8 = (0x00000011),
RM_ENGINE_TYPE_COPY9 = (0x00000012),
RM_ENGINE_TYPE_RESERVED13 = (0x00000013),
RM_ENGINE_TYPE_RESERVED14 = (0x00000014),
RM_ENGINE_TYPE_RESERVED15 = (0x00000015),
RM_ENGINE_TYPE_RESERVED16 = (0x00000016),
RM_ENGINE_TYPE_RESERVED17 = (0x00000017),
RM_ENGINE_TYPE_RESERVED18 = (0x00000018),
RM_ENGINE_TYPE_RESERVED19 = (0x00000019),
RM_ENGINE_TYPE_RESERVED1a = (0x0000001a),
RM_ENGINE_TYPE_RESERVED1b = (0x0000001b),
RM_ENGINE_TYPE_RESERVED1c = (0x0000001c),
RM_ENGINE_TYPE_NVDEC0 = (0x0000001d),
RM_ENGINE_TYPE_NVDEC1 = (0x0000001e),
RM_ENGINE_TYPE_NVDEC2 = (0x0000001f),
@@ -81,8 +92,9 @@ typedef enum
RM_ENGINE_TYPE_NVJPEG5 = (0x0000003a),
RM_ENGINE_TYPE_NVJPEG6 = (0x0000003b),
RM_ENGINE_TYPE_NVJPEG7 = (0x0000003c),
RM_ENGINE_TYPE_OFA = (0x0000003d),
RM_ENGINE_TYPE_LAST = (0x0000003e),
RM_ENGINE_TYPE_OFA0 = (0x0000003d),
RM_ENGINE_TYPE_RESERVED3e = (0x0000003e),
RM_ENGINE_TYPE_LAST = (0x0000003f),
} RM_ENGINE_TYPE;
//
@@ -119,9 +131,9 @@ typedef enum
#define RM_ENGINE_TYPE_IS_NVJPEG(i) (((i) >= RM_ENGINE_TYPE_NVJPEG0) && ((i) < RM_ENGINE_TYPE_NVJPEG(RM_ENGINE_TYPE_NVJPEG_SIZE)))
#define RM_ENGINE_TYPE_NVJPEG_IDX(i) ((i) - RM_ENGINE_TYPE_NVJPEG0)
#define RM_ENGINE_TYPE_OFA(i) (RM_ENGINE_TYPE_OFA+(i))
#define RM_ENGINE_TYPE_IS_OFA(i) (((i) >= RM_ENGINE_TYPE_OFA) && ((i) < RM_ENGINE_TYPE_OFA(RM_ENGINE_TYPE_OFA_SIZE)))
#define RM_ENGINE_TYPE_OFA_IDX(i) ((i) - RM_ENGINE_TYPE_OFA)
#define RM_ENGINE_TYPE_OFA(i) (RM_ENGINE_TYPE_OFA0+(i))
#define RM_ENGINE_TYPE_IS_OFA(i) (((i) >= RM_ENGINE_TYPE_OFA0) && ((i) < RM_ENGINE_TYPE_OFA(RM_ENGINE_TYPE_OFA_SIZE)))
#define RM_ENGINE_TYPE_OFA_IDX(i) ((i) - RM_ENGINE_TYPE_OFA0)
#define RM_ENGINE_TYPE_IS_VIDEO(i) (RM_ENGINE_TYPE_IS_NVENC(i) | \
RM_ENGINE_TYPE_IS_NVDEC(i) | \
@@ -140,6 +152,7 @@ typedef enum
#define RM_ENGINE_RANGE_NVDEC() rangeMake(RM_ENGINE_TYPE_NVDEC(0), RM_ENGINE_TYPE_NVDEC(RM_ENGINE_TYPE_NVDEC_SIZE - 1))
#define RM_ENGINE_RANGE_NVENC() rangeMake(RM_ENGINE_TYPE_NVENC(0), RM_ENGINE_TYPE_NVENC(RM_ENGINE_TYPE_NVENC_SIZE - 1))
#define RM_ENGINE_RANGE_NVJPEG() rangeMake(RM_ENGINE_TYPE_NVJPEG(0), RM_ENGINE_TYPE_NVJPEG(RM_ENGINE_TYPE_NVJPEG_SIZE - 1))
#define RM_ENGINE_RANGE_OFA() rangeMake(RM_ENGINE_TYPE_OFA(0), RM_ENGINE_TYPE_OFA(RM_ENGINE_TYPE_OFA_SIZE - 1))
// Bit Vectors
MAKE_BITVECTOR(ENGTYPE_BIT_VECTOR, RM_ENGINE_TYPE_LAST);

1
src/nvidia/inc/kernel/gpu/gpu_fabric_probe.h
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@@ -52,6 +52,7 @@ NV_STATUS gpuFabricProbeGetGpaAddressRange(GPU_FABRIC_PROBE_INFO_KERNEL *pInfo,
NV_STATUS gpuFabricProbeGetFlaAddress(GPU_FABRIC_PROBE_INFO_KERNEL *pInfo, NvU64 *pFlaAddress);
NV_STATUS gpuFabricProbeGetFlaAddressRange(GPU_FABRIC_PROBE_INFO_KERNEL *pInfo, NvU64 *pFlaAddressRange);
NV_STATUS gpuFabricProbeGetNumProbeReqs(GPU_FABRIC_PROBE_INFO_KERNEL *pInfo, NvU64 *numProbes);
NV_STATUS gpuFabricProbeGetFabricCliqueId(GPU_FABRIC_PROBE_INFO_KERNEL *pInfo, NvU32 *pFabricCliqueId);
NvBool gpuFabricProbeIsReceived(GPU_FABRIC_PROBE_INFO_KERNEL *pGpuFabricProbeInfoKernel);
NvBool gpuFabricProbeIsSuccess(GPU_FABRIC_PROBE_INFO_KERNEL *pGpuFabricProbeInfoKernel);

23
src/nvidia/inc/kernel/gpu/gpu_shared_data_map.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2022-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -28,22 +28,29 @@
#include "gpu/mem_mgr/mem_desc.h"
#include "class/cl00de.h"
#include "tmr.h"
// ****************************************************************************
// Type definitions
// ****************************************************************************
typedef struct RusdQueryCache RUSD_QUERY_CACHE;
typedef struct GpuSharedDataMap {
MEMORY_DESCRIPTOR *pMemDesc;
NvP64 pMapBuffer;
NvP64 pMapBufferPriv;
NvU64 lastPolledDataMask;
NvU32 processId;
NV00DE_SHARED_DATA data;
} GpuSharedDataMap;
TMR_EVENT *pRusdRefreshTmrEvent;
typedef struct GspUserSharedData {
NvU32 gspAssertCount;
} GspUserSharedData;
NV00DE_SHARED_DATA data;
// Private data to assist metrics query
RUSD_QUERY_CACHE *pRusdQueryCache;
NvU8 curGroup;
NvBool bWorkItemPending;
} GpuSharedDataMap;
/**
* Start data write, returns data struct to write into
@@ -52,8 +59,12 @@ typedef struct GspUserSharedData {
* call gpushareddataWriteFinish to push the new data into the user mapping
*/
NV00DE_SHARED_DATA * gpushareddataWriteStart(OBJGPU *pGpu);
// Finish data write, pushes data cached by above into mapped data
void gpushareddataWriteFinish(OBJGPU *pGpu);
// Unmap and free memory in GpuSharedDataMap
void gpushareddataDestroy(OBJGPU *pGpu);
#endif /* GPU_SHARED_DATA_MAP_H */

18
src/nvidia/inc/kernel/gpu/gsp/gsp_fw_heap.h
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@@ -24,9 +24,13 @@
#ifndef GSP_FW_HEAP_H
#define GSP_FW_HEAP_H
#include "rmconfig.h"
// Static defines for the GSP FW WPR Heap
#define GSP_FW_HEAP_PARAM_OS_SIZE_LIBOS2 (0 << 20) // No FB heap usage
#define GSP_FW_HEAP_PARAM_OS_SIZE_LIBOS3 (20 << 20)
#define GSP_FW_HEAP_PARAM_OS_SIZE_LIBOS3_BAREMETAL (22 << 20)
#define GSP_FW_HEAP_PARAM_OS_SIZE_LIBOS3_VGPU (36 << 20)
//
// Calibrated by observing RM init heap usage - the amount of GSP-RM heap memory
@@ -64,16 +68,18 @@
//
#define GSP_FW_HEAP_PARAM_CLIENT_ALLOC_SIZE ((48 << 10) * 2048) // Support 2048 channels
#define GSP_FW_HEAP_SIZE_VGPU_DEFAULT (549 << 20) // Default for all VGPU configs
#define GSP_FW_HEAP_SIZE_VGPU_DEFAULT (565 << 20) // Default for all VGPU configs
// Min/max bounds for heap size override by regkey
#define GSP_FW_HEAP_SIZE_OVERRIDE_LIBOS2_MIN_MB (64u)
#define GSP_FW_HEAP_SIZE_OVERRIDE_LIBOS2_MAX_MB (256u)
#define GSP_FW_HEAP_SIZE_OVERRIDE_LIBOS3_BAREMETAL_MIN_MB (84u)
#define GSP_FW_HEAP_SIZE_OVERRIDE_LIBOS3_BAREMETAL_MAX_MB (276u)
#define GSP_FW_HEAP_SIZE_OVERRIDE_LIBOS3_BAREMETAL_MIN_MB (86u)
#define GSP_FW_HEAP_SIZE_OVERRIDE_LIBOS3_BAREMETAL_MAX_MB (278u)
#define GSP_FW_HEAP_SIZE_OVERRIDE_LIBOS3_VGPU_MIN_MB (549u)
#define GSP_FW_HEAP_SIZE_OVERRIDE_LIBOS3_VGPU_MAX_MB (1024u)
#define GSP_FW_HEAP_SIZE_OVERRIDE_LIBOS3_VGPU_MIN_MB (565u)
#define GSP_FW_HEAP_SIZE_OVERRIDE_LIBOS3_VGPU_MAX_MB (1040u)
#endif // GSP_FW_HEAP_H

2
src/nvidia/inc/kernel/gpu/gsp/gsp_static_config.h
View File

@@ -164,6 +164,8 @@ typedef struct GspSystemInfo
NvU64 clPdbProperties;
NvU32 Chipset;
NvBool bGpuBehindBridge;
NvBool bFlrSupported;
NvBool b64bBar0Supported;
NvBool bMnocAvailable;
NvBool bUpstreamL0sUnsupported;
NvBool bUpstreamL1Unsupported;

73
src/nvidia/inc/kernel/gpu/intr/engine_idx.h
View File

@@ -62,12 +62,22 @@
#define MC_ENGINE_IDX_CE8 23
#define MC_ENGINE_IDX_CE9 24
#define MC_ENGINE_IDX_CE_MAX MC_ENGINE_IDX_CE9
#define MC_ENGINE_IDX_RESERVED25 25
#define MC_ENGINE_IDX_RESERVED26 26
#define MC_ENGINE_IDX_RESERVED27 27
#define MC_ENGINE_IDX_RESERVED28 28
#define MC_ENGINE_IDX_RESERVED29 29
#define MC_ENGINE_IDX_RESERVED30 30
#define MC_ENGINE_IDX_RESERVED31 31
#define MC_ENGINE_IDX_RESERVED32 32
#define MC_ENGINE_IDX_RESERVED33 33
#define MC_ENGINE_IDX_RESERVED34 34
#define MC_ENGINE_IDX_VIC 35
#define MC_ENGINE_IDX_ISOHUB 36
#define MC_ENGINE_IDX_VGPU 37
#define MC_ENGINE_IDX_MSENC 38
#define MC_ENGINE_IDX_MSENC1 39
#define MC_ENGINE_IDX_MSENC2 40
#define MC_ENGINE_IDX_NVENC 38
#define MC_ENGINE_IDX_NVENC1 39
#define MC_ENGINE_IDX_NVENC2 40
#define MC_ENGINE_IDX_C2C 41
#define MC_ENGINE_IDX_LTC 42
#define MC_ENGINE_IDX_FBHUB 43
@@ -112,35 +122,35 @@
#define MC_ENGINE_IDX_XBAR 78
#define MC_ENGINE_IDX_ZPW 79
#define MC_ENGINE_IDX_OFA0 80
#define MC_ENGINE_IDX_TEGRA 81
#define MC_ENGINE_IDX_GR 82
#define MC_ENGINE_IDX_RESERVED81 81
#define MC_ENGINE_IDX_TEGRA 82
#define MC_ENGINE_IDX_GR 83
#define MC_ENGINE_IDX_GR0 MC_ENGINE_IDX_GR
#define MC_ENGINE_IDX_GR1 83
#define MC_ENGINE_IDX_GR2 84
#define MC_ENGINE_IDX_GR3 85
#define MC_ENGINE_IDX_GR4 86
#define MC_ENGINE_IDX_GR5 87
#define MC_ENGINE_IDX_GR6 88
#define MC_ENGINE_IDX_GR7 89
#define MC_ENGINE_IDX_ESCHED 90
#define MC_ENGINE_IDX_GR1 84
#define MC_ENGINE_IDX_GR2 85
#define MC_ENGINE_IDX_GR3 86
#define MC_ENGINE_IDX_GR4 87
#define MC_ENGINE_IDX_GR5 88
#define MC_ENGINE_IDX_GR6 89
#define MC_ENGINE_IDX_GR7 90
#define MC_ENGINE_IDX_ESCHED 91
#define MC_ENGINE_IDX_ESCHED__SIZE 64
#define MC_ENGINE_IDX_GR_FECS_LOG 154
#define MC_ENGINE_IDX_GR_FECS_LOG 155
#define MC_ENGINE_IDX_GR0_FECS_LOG MC_ENGINE_IDX_GR_FECS_LOG
#define MC_ENGINE_IDX_GR1_FECS_LOG 155
#define MC_ENGINE_IDX_GR2_FECS_LOG 156
#define MC_ENGINE_IDX_GR3_FECS_LOG 157
#define MC_ENGINE_IDX_GR4_FECS_LOG 158
#define MC_ENGINE_IDX_GR5_FECS_LOG 159
#define MC_ENGINE_IDX_GR6_FECS_LOG 160
#define MC_ENGINE_IDX_GR7_FECS_LOG 161
#define MC_ENGINE_IDX_TMR_SWRL 162
#define MC_ENGINE_IDX_DISP_GSP 163
#define MC_ENGINE_IDX_REPLAYABLE_FAULT_CPU 164
#define MC_ENGINE_IDX_NON_REPLAYABLE_FAULT_CPU 165
#define MC_ENGINE_IDX_PXUC 166
#define MC_ENGINE_IDX_MAX 167 // This must be kept as the max bit if
// we need to add more engines
#define MC_ENGINE_IDX_INVALID 0xFFFFFFFF
#define MC_ENGINE_IDX_GR1_FECS_LOG 156
#define MC_ENGINE_IDX_GR2_FECS_LOG 157
#define MC_ENGINE_IDX_GR3_FECS_LOG 158
#define MC_ENGINE_IDX_GR4_FECS_LOG 159
#define MC_ENGINE_IDX_GR5_FECS_LOG 160
#define MC_ENGINE_IDX_GR6_FECS_LOG 161
#define MC_ENGINE_IDX_GR7_FECS_LOG 162
#define MC_ENGINE_IDX_TMR_SWRL 163
#define MC_ENGINE_IDX_DISP_GSP 164
#define MC_ENGINE_IDX_REPLAYABLE_FAULT_CPU 165
#define MC_ENGINE_IDX_NON_REPLAYABLE_FAULT_CPU 166
#define MC_ENGINE_IDX_PXUC 167
// This must be kept as the max bit if we need to add more engines
#define MC_ENGINE_IDX_MAX 168
// Index GR reference
#define MC_ENGINE_IDX_GRn(x) (MC_ENGINE_IDX_GR0 + (x))
@@ -150,7 +160,7 @@
#define MC_ENGINE_IDX_CE(x) (MC_ENGINE_IDX_CE0 + (x))
// Index MSENC reference
#define MC_ENGINE_IDX_MSENCn(x) (MC_ENGINE_IDX_MSENC + (x))
#define MC_ENGINE_IDX_NVENCn(x) (MC_ENGINE_IDX_NVENC + (x))
// Index NVDEC reference
#define MC_ENGINE_IDX_NVDECn(x) (MC_ENGINE_IDX_NVDEC + (x))
@@ -164,6 +174,9 @@
#define MC_ENGINE_IDX_IS_CE(x) \
((MC_ENGINE_IDX_CE(0) <= (x)) && ((x) <= MC_ENGINE_IDX_CE_MAX))
// Index OFA reference
#define MC_ENGINE_IDX_OFA(x) (MC_ENGINE_IDX_OFA0 + (x))
MAKE_BITVECTOR(MC_ENGINE_BITVECTOR, MC_ENGINE_IDX_MAX);
typedef MC_ENGINE_BITVECTOR *PMC_ENGINE_BITVECTOR;

8
src/nvidia/inc/kernel/gpu/intr/intr_common.h
View File

@@ -26,7 +26,13 @@
/*! Common defines used by both Intr and OBJINTRABLE */
/*! Kinds of interrupts that a unit can have. */
/*! Kinds of interrupts that a unit can have.
*
* Different interrupt vectors can route to the same MC_ENGINE_IDX_* (and its
* associated #IntrService).
* This enum is used to disambiguate which handler function within an
* #IntrService should be called depending on the actual interrupt vector.
*/
typedef enum {
/*!
* Legacy concept of "stalling" interrupts.

3
src/nvidia/inc/kernel/gpu/kern_gpu_power.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2004-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2004-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -41,6 +41,7 @@ typedef enum
// TODO-SC use mask for the bool variables
typedef struct
{
NvU32 refCount;
GPU_GC6_STATE currentState;
NvU32 executedStepMask; // step mask executed during entry sequence
NvU32 stepMask[NV2080_CTRL_GC6_FLAVOR_ID_MAX]; // step mask cache

4
src/nvidia/inc/kernel/gpu/mem_mgr/ce_utils.h
View File

@@ -53,6 +53,7 @@ typedef struct
NvU64 submittedWorkId; // Payload to poll for async completion
} CEUTILS_MEMCOPY_PARAMS;
class KernelChannel;
NVOC_PREFIX(ceutils) class CeUtils : Object
{
@@ -83,6 +84,9 @@ public:
NvU32 hTdCopyClass;
NvU64 lastSubmittedPayload;
NvU64 lastCompletedPayload;
// Only used by fifo lite implementation
KernelChannel *pLiteKernelChannel;
};

1
src/nvidia/inc/kernel/gpu/mem_mgr/mem_utils.h
View File

@@ -28,7 +28,6 @@
#define CLEAR_HAL_ATTR(a) \
a = (a &~(DRF_NUM(OS32, _ATTR, _COMPR, 0x3) | \
DRF_NUM(OS32, _ATTR, _TILED, 0x3) | \
DRF_NUM(OS32, _ATTR, _ZCULL, 0x3)));
#define CLEAR_HAL_ATTR2(a) \

9
src/nvidia/inc/kernel/gpu/mem_mgr/phys_mem_allocator/phys_mem_allocator_util.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2015-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2015-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -40,6 +40,7 @@ NvU32 findRegionID(PMA *pPma, NvU64 address);
void pmaPrintBlockStatus(PMA_PAGESTATUS blockStatus);
void pmaRegionPrint(PMA *pPma, PMA_REGION_DESCRIPTOR *pRegion, void *pMap);
NvBool pmaStateCheck(PMA *pPma);
NV_STATUS pmaCheckRangeAgainstRegionDesc(PMA *pPma, NvU64 base, NvU64 size);
// Temporary putting these here. TODO refactor them in the next CL.
NV_STATUS _pmaEvictContiguous(PMA *pPma, void *pMap, NvU64 evictStart, NvU64 evictEnd,
@@ -182,12 +183,16 @@ void pmaFreeList(PMA *pPma, PRANGELISTTYPE *ppList);
* @param[in] physAddrBase The base address of this address tree
* @param[in] pBlacklistPageBase Structure that contains the blacklisted pages
* @param[in] blacklistCount Number of blacklisted pages
* @param[in] bBlacklistFromInforom Whether the blacklisted pages are coming from
* inforom (i.e., from heap/PMA init) or not
* (i.e., from ECC interrupt handling)
*
* @return NV_OK
* NV_ERR_NO_MEMORY if memory allocation fails
*/
NV_STATUS pmaRegisterBlacklistInfo(PMA *pPma, NvU64 physAddrBase,
PPMA_BLACKLIST_ADDRESS pBlacklistPageBase, NvU32 blacklistCount);
PPMA_BLACKLIST_ADDRESS pBlacklistPageBase, NvU32 blacklistCount,
NvBool bBlacklistFromInforom);
/*!
* @brief Query blacklisting states tracked by PMA

9
src/nvidia/inc/kernel/gpu/mem_mgr/virt_mem_allocator_common.h
View File

@@ -41,6 +41,7 @@ typedef struct ChannelDescendant ChannelDescendant;
typedef struct ContextDma ContextDma;
typedef struct Memory Memory;
typedef struct EVENTNOTIFICATION EVENTNOTIFICATION;
typedef struct Device Device;
//---------------------------------------------------------------------------
//
@@ -87,8 +88,8 @@ void notifyFillNOTIFICATION(OBJGPU *pGpu,
NV_STATUS CompletionStatus,
NvBool TimeSupplied,
NvU64 Time);
NV_STATUS notifyFillNotifierGPUVA (OBJGPU*, RsClient*, NvHandle, NvU64, NvV32, NvV16, NV_STATUS, NvU32);
NV_STATUS notifyFillNotifierGPUVATimestamp (OBJGPU*, RsClient*, NvHandle, NvU64, NvV32, NvV16, NV_STATUS, NvU32, NvU64);
NV_STATUS notifyFillNotifierGPUVA (OBJGPU*, Device*, NvHandle, NvU64, NvV32, NvV16, NV_STATUS, NvU32);
NV_STATUS notifyFillNotifierGPUVATimestamp (OBJGPU*, Device*, NvHandle, NvU64, NvV32, NvV16, NV_STATUS, NvU32, NvU64);
NV_STATUS notifyFillNotifierMemory (OBJGPU*, Memory *, NvV32, NvV16, NV_STATUS, NvU32);
NV_STATUS notifyFillNotifierMemoryTimestamp(OBJGPU*, Memory *, NvV32, NvV16, NV_STATUS, NvU32, NvU64);
void notifyFillNvNotification(OBJGPU *pGpu,
@@ -99,8 +100,8 @@ void notifyFillNvNotification(OBJGPU *pGpu,
NvBool TimeSupplied,
NvU64 Time);
NV_STATUS semaphoreFillGPUVA (OBJGPU*, RsClient*, NvHandle, NvU64, NvV32, NvV32, NvBool);
NV_STATUS semaphoreFillGPUVATimestamp(OBJGPU*, RsClient*, NvHandle, NvU64, NvV32, NvV32, NvBool, NvU64);
NV_STATUS semaphoreFillGPUVA (OBJGPU*, Device*, NvHandle, NvU64, NvV32, NvV32, NvBool);
NV_STATUS semaphoreFillGPUVATimestamp(OBJGPU*, Device*, NvHandle, NvU64, NvV32, NvV32, NvBool, NvU64);
RM_ATTR_PAGE_SIZE dmaNvos32ToPageSizeAttr(NvU32 attr, NvU32 attr2);

3
src/nvidia/inc/kernel/gpu/video/kernel_video_engine.h Normal file
View File

@@ -0,0 +1,3 @@
#include "g_kernel_video_engine_nvoc.h"

241
src/nvidia/inc/kernel/gpuvideo/video_event.h Normal file
View File

@@ -0,0 +1,241 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2020-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef VIDEO_EVENT_H
#define VIDEO_EVENT_H
/*!
************** Defines used for Video HW event logging! ***********************
*/
/*!
* Defines a skip factor when event buffer is full,
* i.e. 1/(RM_VIDEO_TRACE_SURFACE_SKIP_FACTOR) of the event buffers
* will be skipped and over-written.
*/
#define RM_VIDEO_TRACE_SURFACE_SKIP_FACTOR (16UL)
/*!
* Defines max size of a variable data in one record. For event data has a size
* that is larger than this define, multiple event records will be used for logging.
*/
#define RM_VIDEO_TRACE_MAX_VARIABLE_DATA_SIZE (0x1000UL)
/*!
* Defines magic value for hardware video events
*/
#define ENG_VIDEO_TRACE_EVENT_MAGIC_HI (0xdeadbeefUL)
#define ENG_VIDEO_TRACE_EVENT_MAGIC_LO (0xdead0001UL)
/*!
* Define the type of the engine. Since engine uCode can not determine the actual id,
* such as NVENC0, NVENC1 etc., we will defer this to RM to determine the actual id
* and populate it in final event data structure.
*/
typedef enum
{
VIDEO_ENGINE_TYPE__NVDEC = 0,
VIDEO_ENGINE_TYPE__NVENC,
VIDEO_ENGINE_TYPE__NVJPG,
VIDEO_ENGINE_TYPE__OFA,
VIDEO_ENGINE_TYPE__NUM
} VIDEO_ENGINE_TYPE;
/*!
* Defines video codec types
*/
typedef enum
{
VIDEO_ENGINE_CODEC_ID__OFA = 0, /* Only codec supported for OFA engine. */
VIDEO_ENGINE_CODEC_ID__JPEG = 0, /* Only codec supported for NVJPEG engine. */
VIDEO_ENGINE_CODEC_ID__MPEG2 = 0,
VIDEO_ENGINE_CODEC_ID__VC1,
VIDEO_ENGINE_CODEC_ID__H264,
VIDEO_ENGINE_CODEC_ID__MPEG4,
VIDEO_ENGINE_CODEC_ID__VP8,
VIDEO_ENGINE_CODEC_ID__VP9,
VIDEO_ENGINE_CODEC_ID__HEVC,
VIDEO_ENGINE_CODEC_ID__AVD,
VIDEO_ENGINE_CODEC_ID__NUM
} VIDEO_ENGINE_CODEC_ID;
/*!
* Defines types of video events
*/
typedef enum
{
VIDEO_ENGINE_EVENT_ID__SESSION_START = 0,
VIDEO_ENGINE_EVENT_ID__SESSION_END,
VIDEO_ENGINE_EVENT_ID__POWER_STATE_CHANGE,
VIDEO_ENGINE_EVENT_ID__LOG_DATA,
VIDEO_ENGINE_EVENT_ID__NUM
} VIDEO_ENGINE_EVENT_ID;
/*!
* Defines types of the log data of video events if VIDEO_ENGINE_EVENT__LOG_DATA_MAGIC present
* as first DWORD of log data.
*/
typedef enum
{
VIDEO_ENGINE_EVENT_LOG_DATA_TYPE__GENERIC = 0, /* Generic opaque data */
VIDEO_ENGINE_EVENT_LOG_DATA_TYPE__STR, /* Log data can be interpret as string */
VIDEO_ENGINE_EVENT_LOG_DATA_TYPE__BIN, /* Log data are binary data */
VIDEO_ENGINE_EVENT_LOG_DATA_TYPE__NUM
} VIDEO_ENGINE_EVENT_LOG_DATA_TYPE;
/*!
* Defines return status for VIDEO_ENGINE_EVENT_ID__SESSION_END
*/
typedef enum
{
VIDEO_ENGINE_STATUS__OK = 0,
VIDEO_ENGINE_STATUS__ERR,
VIDEO_ENGINE_STATUS__NUM
} VIDEO_ENGINE_STATUS;
/*!
* Defines structs for various types of trace events
*/
typedef struct {
NvU8 engine_type;
NvU8 engine_id;
NvU16 codec_id;
NvU32 reserved1;
} VIDEO_ENGINE_EVENT__SESSION_START;
typedef struct {
NvU8 engine_type;
NvU8 engine_id;
NvU16 codec_id;
NvU32 status;
} VIDEO_ENGINE_EVENT__SESSION_END;
typedef struct {
NvU16 from;
NvU16 to;
NvU32 reserved2;
} VIDEO_ENGINE_EVENT__POWER_STATE_CHANGE;
typedef struct
{
NvU8 engine_type;
NvU8 engine_id;
NvU16 codec_id;
NvU32 size; /* size of data being logged in NvU32 */
} VIDEO_ENGINE_EVENT__LOG_DATA;
#define VIDEO_ENGINE_EVENT__LOG_DATA_MAGIC RM_VIDEO_TRACE_EVENT_MAGIC_HI
typedef struct
{
NvU32 magic;
VIDEO_ENGINE_EVENT_LOG_DATA_TYPE type;
NvU32 data[];
} VIDEO_ENGINE_EVENT__LOG_DATA_HDR;
/*!
* Defines the struct for a full trace record contains various event structs.
*/
typedef struct
{
NvU32 magic_lo;
NvU32 magic_hi;
union
{
NvU64 ts;
struct
{
NvU32 ts_lo;
NvU32 ts_hi;
};
};
VIDEO_ENGINE_EVENT_ID event_id;
NvU32 seq_no;
union {
NvU64 event_data;
VIDEO_ENGINE_EVENT__SESSION_START event_start;
VIDEO_ENGINE_EVENT__SESSION_END event_end;
VIDEO_ENGINE_EVENT__POWER_STATE_CHANGE event_pstate_change;
VIDEO_ENGINE_EVENT__LOG_DATA event_log_data;
};
// Client information from RM
NvU64 userInfo;
NvU32 context_id;
NvU32 pid;
NvU64 api_id;
NvU32 gfid;
NvU32 reserved;
} VIDEO_ENGINE_EVENT__RECORD;
#define VIDEO_ENGINE_EVENT__LOG_DATA_SIZE(s) (sizeof(VIDEO_ENGINE_EVENT__RECORD) + s.event_log_data.size)
/*!
* Client information passing down by RM and saved at offset VIDEO_ENGINE_EVENT__LOG_INFO__OFFSET
* with the size of VIDEO_ENGINE_EVENT__LOG_INFO__SIZE in context allocation.
*/
#define VIDEO_ENGINE_EVENT__LOG_INFO__OFFSET (0xFA0UL)
#define VIDEO_ENGINE_EVENT__LOG_INFO__SIZE (0x20UL)
#define VIDEO_ENGINE_EVENT__LOG_INFO__LOG_SIZE (5UL)
#define VIDEO_ENGINE_EVENT__KERNEL_PID (0xFFFFFFFFUL)
#define VIDEO_ENGINE_EVENT__KERNEL_CONTEXT (0xFFFFFFFFUL)
typedef struct {
NvU64 userInfo;
NvU32 context_id;
NvU32 pid;
NvU32 gfid;
NvU8 engine_id;
NvU8 reserved3[31];
} VIDEO_ENGINE_EVENT__LOG_INFO;
/*!
* Data-structure for ringbuffer structure related to video ringbuffer surfaces.
*/
typedef struct {
NvU32 bufferSize;
NvU32 readPtr;
NvU32 writePtr;
NvU32 flags;
NvU8 pData[];
} VIDEO_TRACE_RING_BUFFER, *PVIDEO_TRACE_RING_BUFFER;
/* Macro convert data offer to ringbuffer offset*/
#define VIDEO_TRACE_RING_BUFFER__DATA_OFFSET(o) (o + sizeof(VIDEO_TRACE_RING_BUFFER))
#define VIDEO_TRACE_RING_BUFFER__OFFSET(t) (&(((PVIDEO_TRACE_RING_BUFFER)0)->t))
#define VIDEO_TRACE_RING_BUFFER__SIZEOF(t) (sizeof(((PVIDEO_TRACE_RING_BUFFER)0)->t))
#define VIDEO_TRACE_FLAG__LOGGING_ENABLED (0x00000001UL)
#define VIDEO_TRACE_FLAG__RESERVED (0xFFFFFFFEUL)
#endif // VIDEO_EVENT_H

52
src/nvidia/inc/kernel/os/os_fixed_mode_timings_props.h
View File

@@ -1,52 +0,0 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _OS_FIXED_MODE_TIMINGS_PROPS_H_
#define _OS_FIXED_MODE_TIMINGS_PROPS_H_
#include "gpu/disp/kern_disp_max.h"
#include "nvtypes.h"
typedef struct
{
NvU16 hActive;
NvU16 hFrontPorch;
NvU16 hSyncWidth;
NvU16 hBackPorch;
NvU16 vActive;
NvU16 vFrontPorch;
NvU16 vSyncWidth;
NvU16 vBackPorch;
NvU32 pclkKHz;
NvU32 rrx1k;
} OS_MODE_TIMING;
typedef struct
{
OS_MODE_TIMING timingsPerStream[OBJ_MAX_HEADS];
NvU8 numTimings;
} OS_FIXED_MODE_TIMINGS;
#endif

19
src/nvidia/inc/kernel/os/os_stub.h
View File

@@ -36,36 +36,17 @@
// Each of these stub functions returns a different type. Used to
// stub out function pointers in OBJOS.
//
OSQADbgRegistryInit stubOsQADbgRegistryInit;
OSnv_rdcr4 stubOsnv_rdcr4;
OSnv_rdxcr0 stubOsnv_rdxcr0;
OSnv_cpuid stubOsnv_cpuid;
OSnv_rdmsr stubOsnv_rdmsr;
OSnv_wrmsr stubOsnv_wrmsr;
OSRobustChannelsDefaultState stubOsRobustChannelsDefaultState;
OSSpinLoop stubOsSpinLoop;
OSDbgBreakpointEnabled stubOsDbgBreakpointEnabled;
OSQueueWorkItem stubOsQueueWorkItem;
OSQueueWorkItemWithFlags stubOsQueueWorkItemWithFlags;
OSQueueSystemWorkItem stubOsQueueSystemWorkItem;
OSSimEscapeWrite stubOsSimEscapeWrite;
OSSimEscapeWriteBuffer stubOsSimEscapeWriteBuffer;
OSSimEscapeRead stubOsSimEscapeRead;
OSSimEscapeReadBuffer stubOsSimEscapeReadBuffer;
OSSetSurfaceName stubOsSetSurfaceName;
OSCallACPI_NVHG_GPUSTA stubOsCallWMI_NVHG_GPUSTA;
OSCallACPI_NVHG_MXDS stubOsCallWMI_NVHG_MXDS;
OSCallACPI_NVHG_MXMX stubOsCallWMI_NVHG_MXMX;
OSCallACPI_NVHG_DOS stubOsCallWMI_NVHG_DOS;
OSCallACPI_NVHG_DCS stubOsCallWMI_NVHG_DCS;
OSCheckCallback stubOsCheckCallback;
OSRCCallback stubOsRCCallback;
OSSetupVBlank stubOsSetupVBlank;
OSObjectEventNotification stubOsObjectEventNotification;
OSPageArrayGetPhysAddr stubOsPageArrayGetPhysAddr;
OSInternalReserveFreeCallback stubOsInternalReserveFreeCallback;
OSInternalReserveAllocCallback stubOsInternalReserveAllocCallback;
OSGetUefiVariable stubOsGetUefiVariable;
#endif // OS_STUB_H

2
src/nvidia/inc/kernel/rmapi/binary_api.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2021-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a

12
src/nvidia/inc/kernel/rmapi/control.h
View File

@@ -317,6 +317,18 @@ NV_STATUS embeddedParamCopyOut(RMAPI_PARAM_COPY *pParamCopy, RmCtrlParams *pRmC
// is enabled; see g_bRsAccessEnabled.
//
/*
* On T234, RM is in kernel mode, so when RM is running in kernel mode it
* does not allow usermode clients like MODs to call control calls that are
* marked as KERNEL_PRIVILEGED.
* So defining new macro DISPLAY_PRIVILEGED(i.e PRIVILEGED) for Tegra and mark
* control calls needed by MODs with this so that MODs running as root can call
* these control calls. However keeping same privilege level for DGPUs which
* does not change the current behaviour.
*/
#define DISPLAY_PRIVILEGED KERNEL_PRIVILEGED
#endif // _CONTROL_H_

21
src/nvidia/inc/kernel/rmapi/rmapi.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2018-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2018-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -38,6 +38,7 @@ typedef struct CALL_CONTEXT CALL_CONTEXT;
typedef struct MEMORY_DESCRIPTOR MEMORY_DESCRIPTOR;
typedef struct RS_RES_FREE_PARAMS_INTERNAL RS_RES_FREE_PARAMS_INTERNAL;
typedef struct RS_LOCK_INFO RS_LOCK_INFO;
typedef struct NV0000_CTRL_SYSTEM_GET_LOCK_TIMES_PARAMS NV0000_CTRL_SYSTEM_GET_LOCK_TIMES_PARAMS;
typedef NvU32 NV_ADDRESS_SPACE;
extern RsServer g_resServ;
@@ -90,6 +91,15 @@ void rmapiLockRelease(void);
*/
NvBool rmapiLockIsOwner(void);
/**
* Check if current thread owns the RW API lock
*/
NvBool rmapiLockIsWriteOwner(void);
/**
* Retrieve total RM API lock wait and hold times
*/
void rmapiLockGetTimes(NV0000_CTRL_SYSTEM_GET_LOCK_TIMES_PARAMS *);
/**
* Type of RM API client interface
@@ -309,12 +319,13 @@ rmapiEpilogue
RM_API_CONTEXT *pContext
);
void
NV_STATUS
rmapiInitLockInfo
(
RM_API *pRmApi,
NvHandle hClient,
RS_LOCK_INFO *pLockInfo
RM_API *pRmApi,
NvHandle hClient,
NvHandle hSecondClient,
RS_LOCK_INFO *pLockInfo
);
//

4
src/nvidia/inc/kernel/virtualization/common_vgpu_mgr.h
View File

@@ -96,7 +96,7 @@ vgpuMgrReserveSystemChannelIDs(OBJGPU *pGpu,
NvU32 gfid,
NvU32 *pChidOffset,
NvU32 *pChannelCount,
NvHandle hClient,
Device *pMigDevice,
NvU32 numChannels,
NvU32 engineFifoListNumEntries,
FIFO_ENGINE_LIST *engineFifoList);
@@ -106,7 +106,7 @@ vgpuMgrFreeSystemChannelIDs(OBJGPU *pGpu,
NvU32 gfid,
NvU32 *pChidOffset,
NvU32 *pChannelCount,
NvHandle hClient,
Device *pMigDevice,
NvU32 engineFifoListNumEntries,
FIFO_ENGINE_LIST *engineFifoList);