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545.29.02

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This commit is contained in:
Andy Ritger
2023-10-31 16:31:08 -07:00
parent a2f89d6b59
commit be3cd9abcb
28 changed files with 900 additions and 659 deletions
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6
src/common/displayport/src/dp_deviceimpl.cpp
View File

@@ -2068,11 +2068,13 @@ void DeviceImpl::setDscDecompressionDevice(bool bDscCapBasedOnParent)
}
}
}
else if (this->parent && this->parent->isDSCDecompressionSupported())
else if (this->parent && this->parent->isDSCDecompressionSupported() &&
!(this->isLogical()))
{
//
// This condition takes care of sink devices not capable of DSC
// but parent is capable of DSC decompression.
// but parent is capable of DSC decompression. We need to skip this
// if sink is at logical port.
//
this->bDSCPossible = true;
this->devDoingDscDecompression = this->parent;

20
src/common/inc/nvBldVer.h
View File

@@ -36,25 +36,25 @@
// and then checked back in. You cannot make changes to these sections without
// corresponding changes to the buildmeister script
#ifndef NV_BUILD_BRANCH
#define NV_BUILD_BRANCH r545_74
#define NV_BUILD_BRANCH r545_96
#endif
#ifndef NV_PUBLIC_BRANCH
#define NV_PUBLIC_BRANCH r545_74
#define NV_PUBLIC_BRANCH r545_96
#endif
#if defined(NV_LINUX) || defined(NV_BSD) || defined(NV_SUNOS)
#define NV_BUILD_BRANCH_VERSION "rel/gpu_drv/r545/r545_74-96"
#define NV_BUILD_CHANGELIST_NUM (33409679)
#define NV_BUILD_BRANCH_VERSION "rel/gpu_drv/r545/r545_96-120"
#define NV_BUILD_CHANGELIST_NUM (33457372)
#define NV_BUILD_TYPE "Official"
#define NV_BUILD_NAME "rel/gpu_drv/r545/r545_74-96"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (33409679)
#define NV_BUILD_NAME "rel/gpu_drv/r545/r545_96-120"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (33457372)
#else /* Windows builds */
#define NV_BUILD_BRANCH_VERSION "r545_74-8"
#define NV_BUILD_CHANGELIST_NUM (33409679)
#define NV_BUILD_BRANCH_VERSION "r545_96-2"
#define NV_BUILD_CHANGELIST_NUM (33457372)
#define NV_BUILD_TYPE "Official"
#define NV_BUILD_NAME "545.87"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (33409679)
#define NV_BUILD_NAME "546.01"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (33457372)
#define NV_BUILD_BRANCH_BASE_VERSION R545
#endif
// End buildmeister python edited section

2
src/common/inc/nvUnixVersion.h
View File

@@ -4,7 +4,7 @@
#if defined(NV_LINUX) || defined(NV_BSD) || defined(NV_SUNOS) || defined(NV_VMWARE) || defined(NV_QNX) || defined(NV_INTEGRITY) || \
(defined(RMCFG_FEATURE_PLATFORM_GSP) && RMCFG_FEATURE_PLATFORM_GSP == 1)
#define NV_VERSION_STRING "545.23.06"
#define NV_VERSION_STRING "545.29.02"
#else

55
src/common/sdk/nvidia/inc/ctrl/ctrl30f1.h
View File

@@ -887,10 +887,6 @@ typedef struct NV30F1_CTRL_GSYNC_GET_CONTROL_SWAP_LOCK_WINDOW_PARAMS {
* This parameter is set by the client to indicate the
* gpuId of the GPU to which the display to be optimized
* is attached.
* display
* This parameter is not used by RM currently.
* Clients can ignore this parameter. Note that this
* parameter will be removed in future.
* output
* This parameter is set by the client to indicate the
* output resource type of the display to be optimized.
@@ -1033,6 +1029,12 @@ typedef struct NV30F1_CTRL_GSYNC_GET_CONTROL_SWAP_LOCK_WINDOW_PARAMS {
* optimal pixel clock to use with the adjusted mode,
* in units of Hz.
*
*
* bOptimized[out]
* This is set to NV_TRUE if the timings were successfully optimized, and
* NV_FALSE otherwise.
*
*
* Progressive Raster Structure
*
* hSyncEnd hTotal
@@ -1145,28 +1147,29 @@ typedef struct NV30F1_CTRL_GSYNC_GET_CONTROL_SWAP_LOCK_WINDOW_PARAMS {
#define NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_PARAMS_MESSAGE_ID (0x60U)
typedef struct NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_PARAMS {
NvU32 gpuId;
NvU32 display;
NvU32 output;
NvU32 protocol;
NvU32 structure;
NvU32 adjust;
NvU32 hDeltaStep;
NvU32 hDeltaMax;
NvU32 vDeltaStep;
NvU32 vDeltaMax;
NvU32 hSyncEnd;
NvU32 hBlankEnd;
NvU32 hBlankStart;
NvU32 hTotal;
NvU32 vSyncEnd;
NvU32 vBlankEnd;
NvU32 vBlankStart;
NvU32 vInterlacedBlankEnd;
NvU32 vInterlacedBlankStart;
NvU32 vTotal;
NvU32 refreshX10K;
NvU32 pixelClockHz;
NvU32 gpuId;
NvU32 output;
NvU32 protocol;
NvU32 structure;
NvU32 adjust;
NvU32 hDeltaStep;
NvU32 hDeltaMax;
NvU32 vDeltaStep;
NvU32 vDeltaMax;
NvU32 hSyncEnd;
NvU32 hBlankEnd;
NvU32 hBlankStart;
NvU32 hTotal;
NvU32 vSyncEnd;
NvU32 vBlankEnd;
NvU32 vBlankStart;
NvU32 vInterlacedBlankEnd;
NvU32 vInterlacedBlankStart;
NvU32 vTotal;
NvU32 refreshX10K;
NvU32 pixelClockHz;
NvBool bOptimized;
} NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_PARAMS;
/* output values */